1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Analog Devices LTC2947 high precision power and energy monitor
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/hwmon.h>
12 #include <linux/module.h>
13 #include <linux/math64.h>
14 #include <linux/property.h>
15 #include <linux/regmap.h>
16
17 #include "ltc2947.h"
18
19 /* register's */
20 #define LTC2947_REG_PAGE_CTRL 0xFF
21 #define LTC2947_REG_CTRL 0xF0
22 #define LTC2947_REG_TBCTL 0xE9
23 #define LTC2947_CONT_MODE_MASK BIT(3)
24 #define LTC2947_CONT_MODE(x) FIELD_PREP(LTC2947_CONT_MODE_MASK, x)
25 #define LTC2947_PRE_MASK GENMASK(2, 0)
26 #define LTC2947_PRE(x) FIELD_PREP(LTC2947_PRE_MASK, x)
27 #define LTC2947_DIV_MASK GENMASK(7, 3)
28 #define LTC2947_DIV(x) FIELD_PREP(LTC2947_DIV_MASK, x)
29 #define LTC2947_SHUTDOWN_MASK BIT(0)
30 #define LTC2947_REG_ACCUM_POL 0xE1
31 #define LTC2947_ACCUM_POL_1_MASK GENMASK(1, 0)
32 #define LTC2947_ACCUM_POL_1(x) FIELD_PREP(LTC2947_ACCUM_POL_1_MASK, x)
33 #define LTC2947_ACCUM_POL_2_MASK GENMASK(3, 2)
34 #define LTC2947_ACCUM_POL_2(x) FIELD_PREP(LTC2947_ACCUM_POL_2_MASK, x)
35 #define LTC2947_REG_ACCUM_DEADBAND 0xE4
36 #define LTC2947_REG_GPIOSTATCTL 0x67
37 #define LTC2947_GPIO_EN_MASK BIT(0)
38 #define LTC2947_GPIO_EN(x) FIELD_PREP(LTC2947_GPIO_EN_MASK, x)
39 #define LTC2947_GPIO_FAN_EN_MASK BIT(6)
40 #define LTC2947_GPIO_FAN_EN(x) FIELD_PREP(LTC2947_GPIO_FAN_EN_MASK, x)
41 #define LTC2947_GPIO_FAN_POL_MASK BIT(7)
42 #define LTC2947_GPIO_FAN_POL(x) FIELD_PREP(LTC2947_GPIO_FAN_POL_MASK, x)
43 #define LTC2947_REG_GPIO_ACCUM 0xE3
44 /* 200Khz */
45 #define LTC2947_CLK_MIN 200000
46 /* 25Mhz */
47 #define LTC2947_CLK_MAX 25000000
48 #define LTC2947_PAGE0 0
49 #define LTC2947_PAGE1 1
50 /* Voltage registers */
51 #define LTC2947_REG_VOLTAGE 0xA0
52 #define LTC2947_REG_VOLTAGE_MAX 0x50
53 #define LTC2947_REG_VOLTAGE_MIN 0x52
54 #define LTC2947_REG_VOLTAGE_THRE_H 0x90
55 #define LTC2947_REG_VOLTAGE_THRE_L 0x92
56 #define LTC2947_REG_DVCC 0xA4
57 #define LTC2947_REG_DVCC_MAX 0x58
58 #define LTC2947_REG_DVCC_MIN 0x5A
59 #define LTC2947_REG_DVCC_THRE_H 0x98
60 #define LTC2947_REG_DVCC_THRE_L 0x9A
61 #define LTC2947_VOLTAGE_GEN_CHAN 0
62 #define LTC2947_VOLTAGE_DVCC_CHAN 1
63 /* in mV */
64 #define VOLTAGE_MAX 15500
65 #define VOLTAGE_MIN -300
66 #define VDVCC_MAX 15000
67 #define VDVCC_MIN 4750
68 /* Current registers */
69 #define LTC2947_REG_CURRENT 0x90
70 #define LTC2947_REG_CURRENT_MAX 0x40
71 #define LTC2947_REG_CURRENT_MIN 0x42
72 #define LTC2947_REG_CURRENT_THRE_H 0x80
73 #define LTC2947_REG_CURRENT_THRE_L 0x82
74 /* in mA */
75 #define CURRENT_MAX 30000
76 #define CURRENT_MIN -30000
77 /* Power registers */
78 #define LTC2947_REG_POWER 0x93
79 #define LTC2947_REG_POWER_MAX 0x44
80 #define LTC2947_REG_POWER_MIN 0x46
81 #define LTC2947_REG_POWER_THRE_H 0x84
82 #define LTC2947_REG_POWER_THRE_L 0x86
83 /* in uW */
84 #define POWER_MAX 450000000
85 #define POWER_MIN -450000000
86 /* Temperature registers */
87 #define LTC2947_REG_TEMP 0xA2
88 #define LTC2947_REG_TEMP_MAX 0x54
89 #define LTC2947_REG_TEMP_MIN 0x56
90 #define LTC2947_REG_TEMP_THRE_H 0x94
91 #define LTC2947_REG_TEMP_THRE_L 0x96
92 #define LTC2947_REG_TEMP_FAN_THRE_H 0x9C
93 #define LTC2947_REG_TEMP_FAN_THRE_L 0x9E
94 #define LTC2947_TEMP_FAN_CHAN 1
95 /* in millidegress Celsius */
96 #define TEMP_MAX 85000
97 #define TEMP_MIN -40000
98 /* Energy registers */
99 #define LTC2947_REG_ENERGY1 0x06
100 #define LTC2947_REG_ENERGY2 0x16
101 /* Status/Alarm/Overflow registers */
102 #define LTC2947_REG_STATUS 0x80
103 #define LTC2947_REG_STATVT 0x81
104 #define LTC2947_REG_STATIP 0x82
105 #define LTC2947_REG_STATVDVCC 0x87
106
107 #define LTC2947_ALERTS_SIZE (LTC2947_REG_STATVDVCC - LTC2947_REG_STATUS)
108 #define LTC2947_MAX_VOLTAGE_MASK BIT(0)
109 #define LTC2947_MIN_VOLTAGE_MASK BIT(1)
110 #define LTC2947_MAX_CURRENT_MASK BIT(0)
111 #define LTC2947_MIN_CURRENT_MASK BIT(1)
112 #define LTC2947_MAX_POWER_MASK BIT(2)
113 #define LTC2947_MIN_POWER_MASK BIT(3)
114 #define LTC2947_MAX_TEMP_MASK BIT(2)
115 #define LTC2947_MIN_TEMP_MASK BIT(3)
116 #define LTC2947_MAX_TEMP_FAN_MASK BIT(4)
117 #define LTC2947_MIN_TEMP_FAN_MASK BIT(5)
118
119 struct ltc2947_data {
120 struct regmap *map;
121 struct device *dev;
122 u32 lsb_energy;
123 bool gpio_out;
124 };
125
__ltc2947_val_read16(const struct ltc2947_data * st,const u8 reg,u64 * val)126 static int __ltc2947_val_read16(const struct ltc2947_data *st, const u8 reg,
127 u64 *val)
128 {
129 __be16 __val = 0;
130 int ret;
131
132 ret = regmap_bulk_read(st->map, reg, &__val, 2);
133 if (ret)
134 return ret;
135
136 *val = be16_to_cpu(__val);
137
138 return 0;
139 }
140
__ltc2947_val_read24(const struct ltc2947_data * st,const u8 reg,u64 * val)141 static int __ltc2947_val_read24(const struct ltc2947_data *st, const u8 reg,
142 u64 *val)
143 {
144 __be32 __val = 0;
145 int ret;
146
147 ret = regmap_bulk_read(st->map, reg, &__val, 3);
148 if (ret)
149 return ret;
150
151 *val = be32_to_cpu(__val) >> 8;
152
153 return 0;
154 }
155
__ltc2947_val_read64(const struct ltc2947_data * st,const u8 reg,u64 * val)156 static int __ltc2947_val_read64(const struct ltc2947_data *st, const u8 reg,
157 u64 *val)
158 {
159 __be64 __val = 0;
160 int ret;
161
162 ret = regmap_bulk_read(st->map, reg, &__val, 6);
163 if (ret)
164 return ret;
165
166 *val = be64_to_cpu(__val) >> 16;
167
168 return 0;
169 }
170
ltc2947_val_read(struct ltc2947_data * st,const u8 reg,const u8 page,const size_t size,s64 * val)171 static int ltc2947_val_read(struct ltc2947_data *st, const u8 reg,
172 const u8 page, const size_t size, s64 *val)
173 {
174 int ret;
175 u64 __val = 0;
176
177 ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, page);
178 if (ret)
179 return ret;
180
181 dev_dbg(st->dev, "Read val, reg:%02X, p:%d sz:%zu\n", reg, page,
182 size);
183
184 switch (size) {
185 case 2:
186 ret = __ltc2947_val_read16(st, reg, &__val);
187 break;
188 case 3:
189 ret = __ltc2947_val_read24(st, reg, &__val);
190 break;
191 case 6:
192 ret = __ltc2947_val_read64(st, reg, &__val);
193 break;
194 default:
195 ret = -EINVAL;
196 break;
197 }
198
199 if (ret)
200 return ret;
201
202 *val = sign_extend64(__val, (8 * size) - 1);
203
204 dev_dbg(st->dev, "Got s:%lld, u:%016llX\n", *val, __val);
205
206 return 0;
207 }
208
__ltc2947_val_write64(const struct ltc2947_data * st,const u8 reg,const u64 val)209 static int __ltc2947_val_write64(const struct ltc2947_data *st, const u8 reg,
210 const u64 val)
211 {
212 __be64 __val;
213
214 __val = cpu_to_be64(val << 16);
215 return regmap_bulk_write(st->map, reg, &__val, 6);
216 }
217
__ltc2947_val_write16(const struct ltc2947_data * st,const u8 reg,const u16 val)218 static int __ltc2947_val_write16(const struct ltc2947_data *st, const u8 reg,
219 const u16 val)
220 {
221 __be16 __val;
222
223 __val = cpu_to_be16(val);
224 return regmap_bulk_write(st->map, reg, &__val, 2);
225 }
226
ltc2947_val_write(struct ltc2947_data * st,const u8 reg,const u8 page,const size_t size,const u64 val)227 static int ltc2947_val_write(struct ltc2947_data *st, const u8 reg,
228 const u8 page, const size_t size, const u64 val)
229 {
230 int ret;
231
232 /* set device on correct page */
233 ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, page);
234 if (ret)
235 return ret;
236
237 dev_dbg(st->dev, "Write val, r:%02X, p:%d, sz:%zu, val:%016llX\n",
238 reg, page, size, val);
239
240 switch (size) {
241 case 2:
242 ret = __ltc2947_val_write16(st, reg, val);
243 break;
244 case 6:
245 ret = __ltc2947_val_write64(st, reg, val);
246 break;
247 default:
248 ret = -EINVAL;
249 break;
250 }
251
252 return ret;
253 }
254
ltc2947_reset_history(struct ltc2947_data * st,const u8 reg_h,const u8 reg_l)255 static int ltc2947_reset_history(struct ltc2947_data *st, const u8 reg_h,
256 const u8 reg_l)
257 {
258 int ret;
259 /*
260 * let's reset the tracking register's. Tracking register's have all
261 * 2 bytes size
262 */
263 ret = ltc2947_val_write(st, reg_h, LTC2947_PAGE0, 2, 0x8000U);
264 if (ret)
265 return ret;
266
267 return ltc2947_val_write(st, reg_l, LTC2947_PAGE0, 2, 0x7FFFU);
268 }
269
ltc2947_alarm_read(struct ltc2947_data * st,const u8 reg,const u32 mask,long * val)270 static int ltc2947_alarm_read(struct ltc2947_data *st, const u8 reg,
271 const u32 mask, long *val)
272 {
273 u8 offset = reg - LTC2947_REG_STATUS;
274 /* +1 to include status reg */
275 char alarms[LTC2947_ALERTS_SIZE + 1];
276 int ret = 0;
277
278 memset(alarms, 0, sizeof(alarms));
279
280 ret = regmap_write(st->map, LTC2947_REG_PAGE_CTRL, LTC2947_PAGE0);
281 if (ret)
282 return ret;
283
284 dev_dbg(st->dev, "Read alarm, reg:%02X, mask:%02X\n", reg, mask);
285 /*
286 * As stated in the datasheet, when Threshold and Overflow registers
287 * are used, the status and all alert registers must be read in one
288 * multi-byte transaction.
289 */
290 ret = regmap_bulk_read(st->map, LTC2947_REG_STATUS, alarms,
291 sizeof(alarms));
292 if (ret)
293 return ret;
294
295 /* get the alarm */
296 *val = !!(alarms[offset] & mask);
297 return 0;
298 }
299
ltc2947_read_temp(struct device * dev,const u32 attr,long * val,const int channel)300 static int ltc2947_read_temp(struct device *dev, const u32 attr, long *val,
301 const int channel)
302 {
303 int ret;
304 struct ltc2947_data *st = dev_get_drvdata(dev);
305 s64 __val = 0;
306
307 switch (attr) {
308 case hwmon_temp_input:
309 ret = ltc2947_val_read(st, LTC2947_REG_TEMP, LTC2947_PAGE0,
310 2, &__val);
311 break;
312 case hwmon_temp_highest:
313 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_MAX, LTC2947_PAGE0,
314 2, &__val);
315 break;
316 case hwmon_temp_lowest:
317 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_MIN, LTC2947_PAGE0,
318 2, &__val);
319 break;
320 case hwmon_temp_max_alarm:
321 if (channel == LTC2947_TEMP_FAN_CHAN)
322 return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
323 LTC2947_MAX_TEMP_FAN_MASK,
324 val);
325
326 return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
327 LTC2947_MAX_TEMP_MASK, val);
328 case hwmon_temp_min_alarm:
329 if (channel == LTC2947_TEMP_FAN_CHAN)
330 return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
331 LTC2947_MIN_TEMP_FAN_MASK,
332 val);
333
334 return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
335 LTC2947_MIN_TEMP_MASK, val);
336 case hwmon_temp_max:
337 if (channel == LTC2947_TEMP_FAN_CHAN)
338 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_FAN_THRE_H,
339 LTC2947_PAGE1, 2, &__val);
340 else
341 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_THRE_H,
342 LTC2947_PAGE1, 2, &__val);
343 break;
344 case hwmon_temp_min:
345 if (channel == LTC2947_TEMP_FAN_CHAN)
346 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_FAN_THRE_L,
347 LTC2947_PAGE1, 2, &__val);
348 else
349 ret = ltc2947_val_read(st, LTC2947_REG_TEMP_THRE_L,
350 LTC2947_PAGE1, 2, &__val);
351 break;
352 default:
353 return -ENOTSUPP;
354 }
355
356 if (ret)
357 return ret;
358
359 /* in milidegrees celcius, temp is given by: */
360 *val = (__val * 204) + 5500;
361
362 return 0;
363 }
364
ltc2947_read_power(struct device * dev,const u32 attr,long * val)365 static int ltc2947_read_power(struct device *dev, const u32 attr, long *val)
366 {
367 struct ltc2947_data *st = dev_get_drvdata(dev);
368 int ret;
369 u32 lsb = 200000; /* in uW */
370 s64 __val = 0;
371
372 switch (attr) {
373 case hwmon_power_input:
374 ret = ltc2947_val_read(st, LTC2947_REG_POWER, LTC2947_PAGE0,
375 3, &__val);
376 lsb = 50000;
377 break;
378 case hwmon_power_input_highest:
379 ret = ltc2947_val_read(st, LTC2947_REG_POWER_MAX, LTC2947_PAGE0,
380 2, &__val);
381 break;
382 case hwmon_power_input_lowest:
383 ret = ltc2947_val_read(st, LTC2947_REG_POWER_MIN, LTC2947_PAGE0,
384 2, &__val);
385 break;
386 case hwmon_power_max_alarm:
387 return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
388 LTC2947_MAX_POWER_MASK, val);
389 case hwmon_power_min_alarm:
390 return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
391 LTC2947_MIN_POWER_MASK, val);
392 case hwmon_power_max:
393 ret = ltc2947_val_read(st, LTC2947_REG_POWER_THRE_H,
394 LTC2947_PAGE1, 2, &__val);
395 break;
396 case hwmon_power_min:
397 ret = ltc2947_val_read(st, LTC2947_REG_POWER_THRE_L,
398 LTC2947_PAGE1, 2, &__val);
399 break;
400 default:
401 return -ENOTSUPP;
402 }
403
404 if (ret)
405 return ret;
406
407 *val = __val * lsb;
408
409 return 0;
410 }
411
ltc2947_read_curr(struct device * dev,const u32 attr,long * val)412 static int ltc2947_read_curr(struct device *dev, const u32 attr, long *val)
413 {
414 struct ltc2947_data *st = dev_get_drvdata(dev);
415 int ret;
416 u8 lsb = 12; /* in mA */
417 s64 __val = 0;
418
419 switch (attr) {
420 case hwmon_curr_input:
421 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT,
422 LTC2947_PAGE0, 3, &__val);
423 lsb = 3;
424 break;
425 case hwmon_curr_highest:
426 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_MAX,
427 LTC2947_PAGE0, 2, &__val);
428 break;
429 case hwmon_curr_lowest:
430 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_MIN,
431 LTC2947_PAGE0, 2, &__val);
432 break;
433 case hwmon_curr_max_alarm:
434 return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
435 LTC2947_MAX_CURRENT_MASK, val);
436 case hwmon_curr_min_alarm:
437 return ltc2947_alarm_read(st, LTC2947_REG_STATIP,
438 LTC2947_MIN_CURRENT_MASK, val);
439 case hwmon_curr_max:
440 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_THRE_H,
441 LTC2947_PAGE1, 2, &__val);
442 break;
443 case hwmon_curr_min:
444 ret = ltc2947_val_read(st, LTC2947_REG_CURRENT_THRE_L,
445 LTC2947_PAGE1, 2, &__val);
446 break;
447 default:
448 return -ENOTSUPP;
449 }
450
451 if (ret)
452 return ret;
453
454 *val = __val * lsb;
455
456 return 0;
457 }
458
ltc2947_read_in(struct device * dev,const u32 attr,long * val,const int channel)459 static int ltc2947_read_in(struct device *dev, const u32 attr, long *val,
460 const int channel)
461 {
462 struct ltc2947_data *st = dev_get_drvdata(dev);
463 int ret;
464 u8 lsb = 2; /* in mV */
465 s64 __val = 0;
466
467 if (channel < 0 || channel > LTC2947_VOLTAGE_DVCC_CHAN) {
468 dev_err(st->dev, "Invalid chan%d for voltage", channel);
469 return -EINVAL;
470 }
471
472 switch (attr) {
473 case hwmon_in_input:
474 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
475 ret = ltc2947_val_read(st, LTC2947_REG_DVCC,
476 LTC2947_PAGE0, 2, &__val);
477 lsb = 145;
478 } else {
479 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE,
480 LTC2947_PAGE0, 2, &__val);
481 }
482 break;
483 case hwmon_in_highest:
484 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
485 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_MAX,
486 LTC2947_PAGE0, 2, &__val);
487 lsb = 145;
488 } else {
489 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_MAX,
490 LTC2947_PAGE0, 2, &__val);
491 }
492 break;
493 case hwmon_in_lowest:
494 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
495 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_MIN,
496 LTC2947_PAGE0, 2, &__val);
497 lsb = 145;
498 } else {
499 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_MIN,
500 LTC2947_PAGE0, 2, &__val);
501 }
502 break;
503 case hwmon_in_max_alarm:
504 if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
505 return ltc2947_alarm_read(st, LTC2947_REG_STATVDVCC,
506 LTC2947_MAX_VOLTAGE_MASK,
507 val);
508
509 return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
510 LTC2947_MAX_VOLTAGE_MASK, val);
511 case hwmon_in_min_alarm:
512 if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
513 return ltc2947_alarm_read(st, LTC2947_REG_STATVDVCC,
514 LTC2947_MIN_VOLTAGE_MASK,
515 val);
516
517 return ltc2947_alarm_read(st, LTC2947_REG_STATVT,
518 LTC2947_MIN_VOLTAGE_MASK, val);
519 case hwmon_in_max:
520 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
521 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_THRE_H,
522 LTC2947_PAGE1, 2, &__val);
523 lsb = 145;
524 } else {
525 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_THRE_H,
526 LTC2947_PAGE1, 2, &__val);
527 }
528 break;
529 case hwmon_in_min:
530 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
531 ret = ltc2947_val_read(st, LTC2947_REG_DVCC_THRE_L,
532 LTC2947_PAGE1, 2, &__val);
533 lsb = 145;
534 } else {
535 ret = ltc2947_val_read(st, LTC2947_REG_VOLTAGE_THRE_L,
536 LTC2947_PAGE1, 2, &__val);
537 }
538 break;
539 default:
540 return -ENOTSUPP;
541 }
542
543 if (ret)
544 return ret;
545
546 *val = __val * lsb;
547
548 return 0;
549 }
550
ltc2947_read_energy(struct device * dev,s64 * val,const int channel)551 static int ltc2947_read_energy(struct device *dev, s64 *val, const int channel)
552 {
553 int reg = channel ? LTC2947_REG_ENERGY2 : LTC2947_REG_ENERGY1;
554 struct ltc2947_data *st = dev_get_drvdata(dev);
555 s64 __val = 0;
556 int ret;
557
558 ret = ltc2947_val_read(st, reg, LTC2947_PAGE0, 6, &__val);
559 if (ret)
560 return ret;
561
562 /* value in microJoule. st->lsb_energy was multiplied by 10E9 */
563 *val = DIV_S64_ROUND_CLOSEST(__val * st->lsb_energy, 1000);
564
565 return 0;
566 }
567
ltc2947_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)568 static int ltc2947_read(struct device *dev, enum hwmon_sensor_types type,
569 u32 attr, int channel, long *val)
570 {
571 switch (type) {
572 case hwmon_in:
573 return ltc2947_read_in(dev, attr, val, channel);
574 case hwmon_curr:
575 return ltc2947_read_curr(dev, attr, val);
576 case hwmon_power:
577 return ltc2947_read_power(dev, attr, val);
578 case hwmon_temp:
579 return ltc2947_read_temp(dev, attr, val, channel);
580 case hwmon_energy64:
581 return ltc2947_read_energy(dev, (s64 *)val, channel);
582 default:
583 return -ENOTSUPP;
584 }
585 }
586
ltc2947_write_temp(struct device * dev,const u32 attr,long val,const int channel)587 static int ltc2947_write_temp(struct device *dev, const u32 attr,
588 long val, const int channel)
589 {
590 struct ltc2947_data *st = dev_get_drvdata(dev);
591
592 if (channel < 0 || channel > LTC2947_TEMP_FAN_CHAN) {
593 dev_err(st->dev, "Invalid chan%d for temperature", channel);
594 return -EINVAL;
595 }
596
597 switch (attr) {
598 case hwmon_temp_reset_history:
599 if (val != 1)
600 return -EINVAL;
601 return ltc2947_reset_history(st, LTC2947_REG_TEMP_MAX,
602 LTC2947_REG_TEMP_MIN);
603 case hwmon_temp_max:
604 val = clamp_val(val, TEMP_MIN, TEMP_MAX);
605 if (channel == LTC2947_TEMP_FAN_CHAN) {
606 if (!st->gpio_out)
607 return -ENOTSUPP;
608
609 return ltc2947_val_write(st,
610 LTC2947_REG_TEMP_FAN_THRE_H,
611 LTC2947_PAGE1, 2,
612 DIV_ROUND_CLOSEST(val - 550, 204));
613 }
614
615 return ltc2947_val_write(st, LTC2947_REG_TEMP_THRE_H,
616 LTC2947_PAGE1, 2,
617 DIV_ROUND_CLOSEST(val - 550, 204));
618 case hwmon_temp_min:
619 val = clamp_val(val, TEMP_MIN, TEMP_MAX);
620 if (channel == LTC2947_TEMP_FAN_CHAN) {
621 if (!st->gpio_out)
622 return -ENOTSUPP;
623
624 return ltc2947_val_write(st,
625 LTC2947_REG_TEMP_FAN_THRE_L,
626 LTC2947_PAGE1, 2,
627 DIV_ROUND_CLOSEST(val - 550, 204));
628 }
629
630 return ltc2947_val_write(st, LTC2947_REG_TEMP_THRE_L,
631 LTC2947_PAGE1, 2,
632 DIV_ROUND_CLOSEST(val - 550, 204));
633 default:
634 return -ENOTSUPP;
635 }
636 }
637
ltc2947_write_power(struct device * dev,const u32 attr,long val)638 static int ltc2947_write_power(struct device *dev, const u32 attr,
639 long val)
640 {
641 struct ltc2947_data *st = dev_get_drvdata(dev);
642
643 switch (attr) {
644 case hwmon_power_reset_history:
645 if (val != 1)
646 return -EINVAL;
647 return ltc2947_reset_history(st, LTC2947_REG_POWER_MAX,
648 LTC2947_REG_POWER_MIN);
649 case hwmon_power_max:
650 val = clamp_val(val, POWER_MIN, POWER_MAX);
651 return ltc2947_val_write(st, LTC2947_REG_POWER_THRE_H,
652 LTC2947_PAGE1, 2,
653 DIV_ROUND_CLOSEST(val, 200000));
654 case hwmon_power_min:
655 val = clamp_val(val, POWER_MIN, POWER_MAX);
656 return ltc2947_val_write(st, LTC2947_REG_POWER_THRE_L,
657 LTC2947_PAGE1, 2,
658 DIV_ROUND_CLOSEST(val, 200000));
659 default:
660 return -ENOTSUPP;
661 }
662 }
663
ltc2947_write_curr(struct device * dev,const u32 attr,long val)664 static int ltc2947_write_curr(struct device *dev, const u32 attr,
665 long val)
666 {
667 struct ltc2947_data *st = dev_get_drvdata(dev);
668
669 switch (attr) {
670 case hwmon_curr_reset_history:
671 if (val != 1)
672 return -EINVAL;
673 return ltc2947_reset_history(st, LTC2947_REG_CURRENT_MAX,
674 LTC2947_REG_CURRENT_MIN);
675 case hwmon_curr_max:
676 val = clamp_val(val, CURRENT_MIN, CURRENT_MAX);
677 return ltc2947_val_write(st, LTC2947_REG_CURRENT_THRE_H,
678 LTC2947_PAGE1, 2,
679 DIV_ROUND_CLOSEST(val, 12));
680 case hwmon_curr_min:
681 val = clamp_val(val, CURRENT_MIN, CURRENT_MAX);
682 return ltc2947_val_write(st, LTC2947_REG_CURRENT_THRE_L,
683 LTC2947_PAGE1, 2,
684 DIV_ROUND_CLOSEST(val, 12));
685 default:
686 return -ENOTSUPP;
687 }
688 }
689
ltc2947_write_in(struct device * dev,const u32 attr,long val,const int channel)690 static int ltc2947_write_in(struct device *dev, const u32 attr, long val,
691 const int channel)
692 {
693 struct ltc2947_data *st = dev_get_drvdata(dev);
694
695 if (channel > LTC2947_VOLTAGE_DVCC_CHAN) {
696 dev_err(st->dev, "Invalid chan%d for voltage", channel);
697 return -EINVAL;
698 }
699
700 switch (attr) {
701 case hwmon_in_reset_history:
702 if (val != 1)
703 return -EINVAL;
704
705 if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
706 return ltc2947_reset_history(st, LTC2947_REG_DVCC_MAX,
707 LTC2947_REG_DVCC_MIN);
708
709 return ltc2947_reset_history(st, LTC2947_REG_VOLTAGE_MAX,
710 LTC2947_REG_VOLTAGE_MIN);
711 case hwmon_in_max:
712 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
713 val = clamp_val(val, VDVCC_MIN, VDVCC_MAX);
714 return ltc2947_val_write(st, LTC2947_REG_DVCC_THRE_H,
715 LTC2947_PAGE1, 2,
716 DIV_ROUND_CLOSEST(val, 145));
717 }
718
719 val = clamp_val(val, VOLTAGE_MIN, VOLTAGE_MAX);
720 return ltc2947_val_write(st, LTC2947_REG_VOLTAGE_THRE_H,
721 LTC2947_PAGE1, 2,
722 DIV_ROUND_CLOSEST(val, 2));
723 case hwmon_in_min:
724 if (channel == LTC2947_VOLTAGE_DVCC_CHAN) {
725 val = clamp_val(val, VDVCC_MIN, VDVCC_MAX);
726 return ltc2947_val_write(st, LTC2947_REG_DVCC_THRE_L,
727 LTC2947_PAGE1, 2,
728 DIV_ROUND_CLOSEST(val, 145));
729 }
730
731 val = clamp_val(val, VOLTAGE_MIN, VOLTAGE_MAX);
732 return ltc2947_val_write(st, LTC2947_REG_VOLTAGE_THRE_L,
733 LTC2947_PAGE1, 2,
734 DIV_ROUND_CLOSEST(val, 2));
735 default:
736 return -ENOTSUPP;
737 }
738 }
739
ltc2947_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)740 static int ltc2947_write(struct device *dev,
741 enum hwmon_sensor_types type,
742 u32 attr, int channel, long val)
743 {
744 switch (type) {
745 case hwmon_in:
746 return ltc2947_write_in(dev, attr, val, channel);
747 case hwmon_curr:
748 return ltc2947_write_curr(dev, attr, val);
749 case hwmon_power:
750 return ltc2947_write_power(dev, attr, val);
751 case hwmon_temp:
752 return ltc2947_write_temp(dev, attr, val, channel);
753 default:
754 return -ENOTSUPP;
755 }
756 }
757
ltc2947_read_labels(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)758 static int ltc2947_read_labels(struct device *dev,
759 enum hwmon_sensor_types type,
760 u32 attr, int channel, const char **str)
761 {
762 switch (type) {
763 case hwmon_in:
764 if (channel == LTC2947_VOLTAGE_DVCC_CHAN)
765 *str = "DVCC";
766 else
767 *str = "VP-VM";
768 return 0;
769 case hwmon_curr:
770 *str = "IP-IM";
771 return 0;
772 case hwmon_temp:
773 if (channel == LTC2947_TEMP_FAN_CHAN)
774 *str = "TEMPFAN";
775 else
776 *str = "Ambient";
777 return 0;
778 case hwmon_power:
779 *str = "Power";
780 return 0;
781 default:
782 return -ENOTSUPP;
783 }
784 }
785
ltc2947_in_is_visible(const u32 attr)786 static int ltc2947_in_is_visible(const u32 attr)
787 {
788 switch (attr) {
789 case hwmon_in_input:
790 case hwmon_in_highest:
791 case hwmon_in_lowest:
792 case hwmon_in_max_alarm:
793 case hwmon_in_min_alarm:
794 case hwmon_in_label:
795 return 0444;
796 case hwmon_in_reset_history:
797 return 0200;
798 case hwmon_in_max:
799 case hwmon_in_min:
800 return 0644;
801 default:
802 return 0;
803 }
804 }
805
ltc2947_curr_is_visible(const u32 attr)806 static int ltc2947_curr_is_visible(const u32 attr)
807 {
808 switch (attr) {
809 case hwmon_curr_input:
810 case hwmon_curr_highest:
811 case hwmon_curr_lowest:
812 case hwmon_curr_max_alarm:
813 case hwmon_curr_min_alarm:
814 case hwmon_curr_label:
815 return 0444;
816 case hwmon_curr_reset_history:
817 return 0200;
818 case hwmon_curr_max:
819 case hwmon_curr_min:
820 return 0644;
821 default:
822 return 0;
823 }
824 }
825
ltc2947_power_is_visible(const u32 attr)826 static int ltc2947_power_is_visible(const u32 attr)
827 {
828 switch (attr) {
829 case hwmon_power_input:
830 case hwmon_power_input_highest:
831 case hwmon_power_input_lowest:
832 case hwmon_power_label:
833 case hwmon_power_max_alarm:
834 case hwmon_power_min_alarm:
835 return 0444;
836 case hwmon_power_reset_history:
837 return 0200;
838 case hwmon_power_max:
839 case hwmon_power_min:
840 return 0644;
841 default:
842 return 0;
843 }
844 }
845
ltc2947_temp_is_visible(const u32 attr)846 static int ltc2947_temp_is_visible(const u32 attr)
847 {
848 switch (attr) {
849 case hwmon_temp_input:
850 case hwmon_temp_highest:
851 case hwmon_temp_lowest:
852 case hwmon_temp_max_alarm:
853 case hwmon_temp_min_alarm:
854 case hwmon_temp_label:
855 return 0444;
856 case hwmon_temp_reset_history:
857 return 0200;
858 case hwmon_temp_max:
859 case hwmon_temp_min:
860 return 0644;
861 default:
862 return 0;
863 }
864 }
865
ltc2947_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)866 static umode_t ltc2947_is_visible(const void *data,
867 enum hwmon_sensor_types type,
868 u32 attr, int channel)
869 {
870 switch (type) {
871 case hwmon_in:
872 return ltc2947_in_is_visible(attr);
873 case hwmon_curr:
874 return ltc2947_curr_is_visible(attr);
875 case hwmon_power:
876 return ltc2947_power_is_visible(attr);
877 case hwmon_temp:
878 return ltc2947_temp_is_visible(attr);
879 case hwmon_energy64:
880 return 0444;
881 default:
882 return 0;
883 }
884 }
885
886 static const struct hwmon_channel_info * const ltc2947_info[] = {
887 HWMON_CHANNEL_INFO(in,
888 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
889 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_RESET_HISTORY |
890 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM |
891 HWMON_I_LABEL,
892 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
893 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_RESET_HISTORY |
894 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM |
895 HWMON_I_LABEL),
896 HWMON_CHANNEL_INFO(curr,
897 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST |
898 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_RESET_HISTORY |
899 HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM |
900 HWMON_C_LABEL),
901 HWMON_CHANNEL_INFO(power,
902 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST |
903 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN |
904 HWMON_P_RESET_HISTORY | HWMON_P_MAX_ALARM |
905 HWMON_P_MIN_ALARM | HWMON_P_LABEL),
906 HWMON_CHANNEL_INFO(temp,
907 HWMON_T_INPUT | HWMON_T_LOWEST | HWMON_T_HIGHEST |
908 HWMON_T_MAX | HWMON_T_MIN | HWMON_T_RESET_HISTORY |
909 HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM |
910 HWMON_T_LABEL,
911 HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM | HWMON_T_MAX |
912 HWMON_T_MIN | HWMON_T_LABEL),
913 HWMON_CHANNEL_INFO(energy64,
914 HWMON_E_INPUT,
915 HWMON_E_INPUT),
916 NULL
917 };
918
919 static const struct hwmon_ops ltc2947_hwmon_ops = {
920 .is_visible = ltc2947_is_visible,
921 .read = ltc2947_read,
922 .write = ltc2947_write,
923 .read_string = ltc2947_read_labels,
924 };
925
926 static const struct hwmon_chip_info ltc2947_chip_info = {
927 .ops = <c2947_hwmon_ops,
928 .info = ltc2947_info,
929 };
930
ltc2947_setup(struct ltc2947_data * st)931 static int ltc2947_setup(struct ltc2947_data *st)
932 {
933 int ret;
934 struct clk *extclk;
935 u32 dummy, deadband, pol;
936 u32 accum[2];
937
938 /* clear status register by reading it */
939 ret = regmap_read(st->map, LTC2947_REG_STATUS, &dummy);
940 if (ret)
941 return ret;
942 /*
943 * Set max/min for power here since the default values x scale
944 * would overflow on 32bit arch
945 */
946 ret = ltc2947_val_write(st, LTC2947_REG_POWER_THRE_H, LTC2947_PAGE1, 2,
947 POWER_MAX / 200000);
948 if (ret)
949 return ret;
950
951 ret = ltc2947_val_write(st, LTC2947_REG_POWER_THRE_L, LTC2947_PAGE1, 2,
952 POWER_MIN / 200000);
953 if (ret)
954 return ret;
955
956 /* check external clock presence */
957 extclk = devm_clk_get_optional_enabled(st->dev, NULL);
958 if (IS_ERR(extclk))
959 return dev_err_probe(st->dev, PTR_ERR(extclk),
960 "Failed to get external clock\n");
961
962 if (extclk) {
963 unsigned long rate_hz;
964 u8 pre = 0, div, tbctl;
965 u64 aux;
966
967 /* let's calculate and set the right valus in TBCTL */
968 rate_hz = clk_get_rate(extclk);
969 if (rate_hz < LTC2947_CLK_MIN || rate_hz > LTC2947_CLK_MAX) {
970 dev_err(st->dev, "Invalid rate:%lu for external clock",
971 rate_hz);
972 return -EINVAL;
973 }
974
975 /* as in table 1 of the datasheet */
976 if (rate_hz >= LTC2947_CLK_MIN && rate_hz <= 1000000)
977 pre = 0;
978 else if (rate_hz > 1000000 && rate_hz <= 2000000)
979 pre = 1;
980 else if (rate_hz > 2000000 && rate_hz <= 4000000)
981 pre = 2;
982 else if (rate_hz > 4000000 && rate_hz <= 8000000)
983 pre = 3;
984 else if (rate_hz > 8000000 && rate_hz <= 16000000)
985 pre = 4;
986 else if (rate_hz > 16000000 && rate_hz <= LTC2947_CLK_MAX)
987 pre = 5;
988 /*
989 * Div is given by:
990 * floor(fref / (2^PRE * 32768))
991 */
992 div = rate_hz / ((1 << pre) * 32768);
993 tbctl = LTC2947_PRE(pre) | LTC2947_DIV(div);
994
995 ret = regmap_write(st->map, LTC2947_REG_TBCTL, tbctl);
996 if (ret)
997 return ret;
998 /*
999 * The energy lsb is given by (in W*s):
1000 * 06416 * (1/fref) * 2^PRE * (DIV + 1)
1001 * The value is multiplied by 10E9
1002 */
1003 aux = (div + 1) * ((1 << pre) * 641600000ULL);
1004 st->lsb_energy = DIV_ROUND_CLOSEST_ULL(aux, rate_hz);
1005 } else {
1006 /* 19.89E-6 * 10E9 */
1007 st->lsb_energy = 19890;
1008 }
1009 ret = device_property_read_u32_array(st->dev, "adi,accumulator-ctl-pol",
1010 accum, ARRAY_SIZE(accum));
1011 if (!ret) {
1012 u32 accum_reg = LTC2947_ACCUM_POL_1(accum[0]) |
1013 LTC2947_ACCUM_POL_2(accum[1]);
1014
1015 ret = regmap_write(st->map, LTC2947_REG_ACCUM_POL, accum_reg);
1016 if (ret)
1017 return ret;
1018 }
1019 ret = device_property_read_u32(st->dev,
1020 "adi,accumulation-deadband-microamp",
1021 &deadband);
1022 if (!ret) {
1023 /* the LSB is the same as the current, so 3mA */
1024 ret = regmap_write(st->map, LTC2947_REG_ACCUM_DEADBAND,
1025 deadband / (1000 * 3));
1026 if (ret)
1027 return ret;
1028 }
1029 /* check gpio cfg */
1030 ret = device_property_read_u32(st->dev, "adi,gpio-out-pol", &pol);
1031 if (!ret) {
1032 /* setup GPIO as output */
1033 u32 gpio_ctl = LTC2947_GPIO_EN(1) | LTC2947_GPIO_FAN_EN(1) |
1034 LTC2947_GPIO_FAN_POL(pol);
1035
1036 st->gpio_out = true;
1037 ret = regmap_write(st->map, LTC2947_REG_GPIOSTATCTL, gpio_ctl);
1038 if (ret)
1039 return ret;
1040 }
1041 ret = device_property_read_u32_array(st->dev, "adi,gpio-in-accum",
1042 accum, ARRAY_SIZE(accum));
1043 if (!ret) {
1044 /*
1045 * Setup the accum options. The gpioctl is already defined as
1046 * input by default.
1047 */
1048 u32 accum_val = LTC2947_ACCUM_POL_1(accum[0]) |
1049 LTC2947_ACCUM_POL_2(accum[1]);
1050
1051 if (st->gpio_out) {
1052 dev_err(st->dev,
1053 "Cannot have input gpio config if already configured as output");
1054 return -EINVAL;
1055 }
1056
1057 ret = regmap_write(st->map, LTC2947_REG_GPIO_ACCUM, accum_val);
1058 if (ret)
1059 return ret;
1060 }
1061
1062 /* set continuos mode */
1063 return regmap_update_bits(st->map, LTC2947_REG_CTRL,
1064 LTC2947_CONT_MODE_MASK, LTC2947_CONT_MODE(1));
1065 }
1066
ltc2947_core_probe(struct regmap * map,const char * name)1067 int ltc2947_core_probe(struct regmap *map, const char *name)
1068 {
1069 struct ltc2947_data *st;
1070 struct device *dev = regmap_get_device(map);
1071 struct device *hwmon;
1072 int ret;
1073
1074 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
1075 if (!st)
1076 return -ENOMEM;
1077
1078 st->map = map;
1079 st->dev = dev;
1080 dev_set_drvdata(dev, st);
1081
1082 ret = ltc2947_setup(st);
1083 if (ret)
1084 return ret;
1085
1086 hwmon = devm_hwmon_device_register_with_info(dev, name, st,
1087 <c2947_chip_info, NULL);
1088 return PTR_ERR_OR_ZERO(hwmon);
1089 }
1090 EXPORT_SYMBOL_GPL(ltc2947_core_probe);
1091
ltc2947_resume(struct device * dev)1092 static int ltc2947_resume(struct device *dev)
1093 {
1094 struct ltc2947_data *st = dev_get_drvdata(dev);
1095 u32 ctrl = 0;
1096 int ret;
1097
1098 /* dummy read to wake the device */
1099 ret = regmap_read(st->map, LTC2947_REG_CTRL, &ctrl);
1100 if (ret)
1101 return ret;
1102 /*
1103 * Wait for the device. It takes 100ms to wake up so, 10ms extra
1104 * should be enough.
1105 */
1106 msleep(110);
1107 ret = regmap_read(st->map, LTC2947_REG_CTRL, &ctrl);
1108 if (ret)
1109 return ret;
1110 /* ctrl should be 0 */
1111 if (ctrl != 0) {
1112 dev_err(st->dev, "Device failed to wake up, ctl:%02X\n", ctrl);
1113 return -ETIMEDOUT;
1114 }
1115
1116 /* set continuous mode */
1117 return regmap_update_bits(st->map, LTC2947_REG_CTRL,
1118 LTC2947_CONT_MODE_MASK, LTC2947_CONT_MODE(1));
1119 }
1120
ltc2947_suspend(struct device * dev)1121 static int ltc2947_suspend(struct device *dev)
1122 {
1123 struct ltc2947_data *st = dev_get_drvdata(dev);
1124
1125 return regmap_update_bits(st->map, LTC2947_REG_CTRL,
1126 LTC2947_SHUTDOWN_MASK, 1);
1127 }
1128
1129 EXPORT_SIMPLE_DEV_PM_OPS(ltc2947_pm_ops, ltc2947_suspend, ltc2947_resume);
1130
1131 const struct of_device_id ltc2947_of_match[] = {
1132 { .compatible = "adi,ltc2947" },
1133 {}
1134 };
1135 EXPORT_SYMBOL_GPL(ltc2947_of_match);
1136 MODULE_DEVICE_TABLE(of, ltc2947_of_match);
1137
1138 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1139 MODULE_DESCRIPTION("LTC2947 power and energy monitor core driver");
1140 MODULE_LICENSE("GPL");
1141