1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH11K_QMI_H 8 #define ATH11K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH11K_HOST_VERSION_STRING "WIN" 14 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 17 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 18 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 19 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 20 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 23 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 24 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 25 #define ATH11K_QMI_RESP_LEN_MAX 8192 26 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 27 #define ATH11K_QMI_CALDB_SIZE 0x480000 28 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 29 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5 30 31 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 32 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 33 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x003E 34 #define QMI_WLFW_FW_READY_IND_V01 0x0021 35 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 36 37 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 38 #define ATH11K_FIRMWARE_MODE_OFF 4 39 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) 40 41 #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 42 43 struct ath11k_base; 44 45 enum ath11k_qmi_file_type { 46 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 47 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 48 ATH11K_QMI_FILE_TYPE_EEPROM, 49 ATH11K_QMI_MAX_FILE_TYPE, 50 }; 51 52 enum ath11k_qmi_bdf_type { 53 ATH11K_QMI_BDF_TYPE_BIN = 0, 54 ATH11K_QMI_BDF_TYPE_ELF = 1, 55 ATH11K_QMI_BDF_TYPE_REGDB = 4, 56 }; 57 58 enum ath11k_qmi_event_type { 59 ATH11K_QMI_EVENT_SERVER_ARRIVE, 60 ATH11K_QMI_EVENT_SERVER_EXIT, 61 ATH11K_QMI_EVENT_REQUEST_MEM, 62 ATH11K_QMI_EVENT_FW_MEM_READY, 63 ATH11K_QMI_EVENT_FW_READY, 64 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 65 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 66 ATH11K_QMI_EVENT_REGISTER_DRIVER, 67 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 68 ATH11K_QMI_EVENT_RECOVERY, 69 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 70 ATH11K_QMI_EVENT_POWER_UP, 71 ATH11K_QMI_EVENT_POWER_DOWN, 72 ATH11K_QMI_EVENT_FW_INIT_DONE, 73 ATH11K_QMI_EVENT_MAX, 74 }; 75 76 struct ath11k_qmi_driver_event { 77 struct list_head list; 78 enum ath11k_qmi_event_type type; 79 void *data; 80 }; 81 82 struct ath11k_qmi_ce_cfg { 83 const struct ce_pipe_config *tgt_ce; 84 int tgt_ce_len; 85 const struct service_to_pipe *svc_to_ce_map; 86 int svc_to_ce_map_len; 87 const u8 *shadow_reg; 88 int shadow_reg_len; 89 u32 *shadow_reg_v2; 90 int shadow_reg_v2_len; 91 }; 92 93 struct ath11k_qmi_event_msg { 94 struct list_head list; 95 enum ath11k_qmi_event_type type; 96 }; 97 98 struct target_mem_chunk { 99 u32 size; 100 u32 type; 101 u32 prev_size; 102 u32 prev_type; 103 dma_addr_t paddr; 104 union { 105 u32 *vaddr; 106 void __iomem *iaddr; 107 void *anyaddr; 108 }; 109 }; 110 111 struct target_info { 112 u32 chip_id; 113 u32 chip_family; 114 u32 board_id; 115 u32 soc_id; 116 u32 fw_version; 117 u32 eeprom_caldata; 118 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 119 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 120 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH]; 121 }; 122 123 struct m3_mem_region { 124 u32 size; 125 dma_addr_t paddr; 126 void *vaddr; 127 }; 128 129 struct ath11k_qmi { 130 struct ath11k_base *ab; 131 struct qmi_handle handle; 132 struct sockaddr_qrtr sq; 133 struct work_struct event_work; 134 struct workqueue_struct *event_wq; 135 struct list_head event_list; 136 spinlock_t event_lock; /* spinlock for qmi event list */ 137 struct ath11k_qmi_ce_cfg ce_cfg; 138 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 139 u32 mem_seg_count; 140 u32 target_mem_mode; 141 bool target_mem_delayed; 142 u8 cal_done; 143 struct target_info target; 144 struct m3_mem_region m3_mem; 145 unsigned int service_ins_id; 146 wait_queue_head_t cold_boot_waitq; 147 }; 148 149 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 150 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 151 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 152 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 153 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 154 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 155 #define HOST_DDR_REGION_TYPE 0x1 156 #define BDF_MEM_REGION_TYPE 0x2 157 #define M3_DUMP_REGION_TYPE 0x3 158 #define CALDB_MEM_REGION_TYPE 0x4 159 #define PAGEABLE_MEM_REGION_TYPE 0x9 160 161 struct qmi_wlanfw_host_cap_req_msg_v01 { 162 u8 num_clients_valid; 163 u32 num_clients; 164 u8 wake_msi_valid; 165 u32 wake_msi; 166 u8 gpios_valid; 167 u32 gpios_len; 168 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 169 u8 nm_modem_valid; 170 u8 nm_modem; 171 u8 bdf_support_valid; 172 u8 bdf_support; 173 u8 bdf_cache_support_valid; 174 u8 bdf_cache_support; 175 u8 m3_support_valid; 176 u8 m3_support; 177 u8 m3_cache_support_valid; 178 u8 m3_cache_support; 179 u8 cal_filesys_support_valid; 180 u8 cal_filesys_support; 181 u8 cal_cache_support_valid; 182 u8 cal_cache_support; 183 u8 cal_done_valid; 184 u8 cal_done; 185 u8 mem_bucket_valid; 186 u32 mem_bucket; 187 u8 mem_cfg_mode_valid; 188 u8 mem_cfg_mode; 189 }; 190 191 struct qmi_wlanfw_host_cap_resp_msg_v01 { 192 struct qmi_response_type_v01 resp; 193 }; 194 195 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 196 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 197 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 198 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 199 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 200 201 struct qmi_wlanfw_ind_register_req_msg_v01 { 202 u8 fw_ready_enable_valid; 203 u8 fw_ready_enable; 204 u8 initiate_cal_download_enable_valid; 205 u8 initiate_cal_download_enable; 206 u8 initiate_cal_update_enable_valid; 207 u8 initiate_cal_update_enable; 208 u8 msa_ready_enable_valid; 209 u8 msa_ready_enable; 210 u8 pin_connect_result_enable_valid; 211 u8 pin_connect_result_enable; 212 u8 client_id_valid; 213 u32 client_id; 214 u8 request_mem_enable_valid; 215 u8 request_mem_enable; 216 u8 fw_mem_ready_enable_valid; 217 u8 fw_mem_ready_enable; 218 u8 fw_init_done_enable_valid; 219 u8 fw_init_done_enable; 220 u8 rejuvenate_enable_valid; 221 u32 rejuvenate_enable; 222 u8 xo_cal_enable_valid; 223 u8 xo_cal_enable; 224 u8 cal_done_enable_valid; 225 u8 cal_done_enable; 226 }; 227 228 struct qmi_wlanfw_ind_register_resp_msg_v01 { 229 struct qmi_response_type_v01 resp; 230 u8 fw_status_valid; 231 u64 fw_status; 232 }; 233 234 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 235 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 236 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 237 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 238 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 239 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 240 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 241 242 struct qmi_wlanfw_mem_cfg_s_v01 { 243 u64 offset; 244 u32 size; 245 u8 secure_flag; 246 }; 247 248 enum qmi_wlanfw_mem_type_enum_v01 { 249 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 250 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 251 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 252 QMI_WLANFW_MEM_BDF_V01 = 2, 253 QMI_WLANFW_MEM_M3_V01 = 3, 254 QMI_WLANFW_MEM_CAL_V01 = 4, 255 QMI_WLANFW_MEM_DPD_V01 = 5, 256 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 257 }; 258 259 struct qmi_wlanfw_mem_seg_s_v01 { 260 u32 size; 261 enum qmi_wlanfw_mem_type_enum_v01 type; 262 u32 mem_cfg_len; 263 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 264 }; 265 266 struct qmi_wlanfw_request_mem_ind_msg_v01 { 267 u32 mem_seg_len; 268 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 269 }; 270 271 struct qmi_wlanfw_mem_seg_resp_s_v01 { 272 u64 addr; 273 u32 size; 274 enum qmi_wlanfw_mem_type_enum_v01 type; 275 u8 restore; 276 }; 277 278 struct qmi_wlanfw_respond_mem_req_msg_v01 { 279 u32 mem_seg_len; 280 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 281 }; 282 283 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 284 struct qmi_response_type_v01 resp; 285 }; 286 287 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 288 char placeholder; 289 }; 290 291 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 292 char placeholder; 293 }; 294 295 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 296 char placeholder; 297 }; 298 299 struct qmi_wlfw_fw_init_done_ind_msg_v01 { 300 char placeholder; 301 }; 302 303 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 304 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 305 #define QMI_WLANFW_CAP_REQ_V01 0x0024 306 #define QMI_WLANFW_CAP_RESP_V01 0x0024 307 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 308 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 309 310 enum qmi_wlanfw_pipedir_enum_v01 { 311 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 312 QMI_WLFW_PIPEDIR_IN_V01 = 1, 313 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 314 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 315 }; 316 317 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 318 __le32 pipe_num; 319 __le32 pipe_dir; 320 __le32 nentries; 321 __le32 nbytes_max; 322 __le32 flags; 323 }; 324 325 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 326 __le32 service_id; 327 __le32 pipe_dir; 328 __le32 pipe_num; 329 }; 330 331 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 332 u16 id; 333 u16 offset; 334 }; 335 336 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 337 u32 addr; 338 }; 339 340 struct qmi_wlanfw_memory_region_info_s_v01 { 341 u64 region_addr; 342 u32 size; 343 u8 secure_flag; 344 }; 345 346 struct qmi_wlanfw_rf_chip_info_s_v01 { 347 u32 chip_id; 348 u32 chip_family; 349 }; 350 351 struct qmi_wlanfw_rf_board_info_s_v01 { 352 u32 board_id; 353 }; 354 355 struct qmi_wlanfw_soc_info_s_v01 { 356 u32 soc_id; 357 }; 358 359 struct qmi_wlanfw_fw_version_info_s_v01 { 360 u32 fw_version; 361 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 362 }; 363 364 enum qmi_wlanfw_cal_temp_id_enum_v01 { 365 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 366 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 367 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 368 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 369 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 370 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 371 }; 372 373 struct qmi_wlanfw_cap_resp_msg_v01 { 374 struct qmi_response_type_v01 resp; 375 u8 chip_info_valid; 376 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 377 u8 board_info_valid; 378 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 379 u8 soc_info_valid; 380 struct qmi_wlanfw_soc_info_s_v01 soc_info; 381 u8 fw_version_info_valid; 382 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 383 u8 fw_build_id_valid; 384 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 385 u8 num_macs_valid; 386 u8 num_macs; 387 u8 voltage_mv_valid; 388 u32 voltage_mv; 389 u8 time_freq_hz_valid; 390 u32 time_freq_hz; 391 u8 otp_version_valid; 392 u32 otp_version; 393 u8 eeprom_read_timeout_valid; 394 u32 eeprom_read_timeout; 395 }; 396 397 struct qmi_wlanfw_cap_req_msg_v01 { 398 char placeholder; 399 }; 400 401 struct qmi_wlanfw_device_info_req_msg_v01 { 402 char placeholder; 403 }; 404 405 struct qmi_wlanfw_device_info_resp_msg_v01 { 406 struct qmi_response_type_v01 resp; 407 u64 bar_addr; 408 u32 bar_size; 409 u8 bar_addr_valid; 410 u8 bar_size_valid; 411 }; 412 413 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 414 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 415 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 416 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 417 /* TODO: Need to check with MCL and FW team that data can be pointer and 418 * can be last element in structure 419 */ 420 struct qmi_wlanfw_bdf_download_req_msg_v01 { 421 u8 valid; 422 u8 file_id_valid; 423 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 424 u8 total_size_valid; 425 u32 total_size; 426 u8 seg_id_valid; 427 u32 seg_id; 428 u8 data_valid; 429 u32 data_len; 430 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 431 u8 end_valid; 432 u8 end; 433 u8 bdf_type_valid; 434 u8 bdf_type; 435 436 }; 437 438 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 439 struct qmi_response_type_v01 resp; 440 }; 441 442 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 443 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 444 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 445 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 446 447 struct qmi_wlanfw_m3_info_req_msg_v01 { 448 u64 addr; 449 u32 size; 450 }; 451 452 struct qmi_wlanfw_m3_info_resp_msg_v01 { 453 struct qmi_response_type_v01 resp; 454 }; 455 456 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 457 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 458 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 459 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 460 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 461 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 462 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 463 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 464 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 465 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 466 #define QMI_WLANFW_MAX_STR_LEN_V01 16 467 #define QMI_WLANFW_MAX_NUM_CE_V01 12 468 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 469 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 470 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 471 472 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 473 u32 mode; 474 u8 hw_debug_valid; 475 u8 hw_debug; 476 }; 477 478 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 479 struct qmi_response_type_v01 resp; 480 }; 481 482 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 483 u8 host_version_valid; 484 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 485 u8 tgt_cfg_valid; 486 u32 tgt_cfg_len; 487 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 488 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 489 u8 svc_cfg_valid; 490 u32 svc_cfg_len; 491 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 492 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 493 u8 shadow_reg_valid; 494 u32 shadow_reg_len; 495 struct qmi_wlanfw_shadow_reg_cfg_s_v01 496 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 497 u8 shadow_reg_v2_valid; 498 u32 shadow_reg_v2_len; 499 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 500 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 501 }; 502 503 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 504 struct qmi_response_type_v01 resp; 505 }; 506 507 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 508 /* Must be set to true if enablefwlog is being passed */ 509 u8 enablefwlog_valid; 510 u8 enablefwlog; 511 }; 512 513 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 514 struct qmi_response_type_v01 resp; 515 }; 516 517 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 518 u32 mode); 519 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 520 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 521 int ath11k_qmi_init_service(struct ath11k_base *ab); 522 void ath11k_qmi_free_resource(struct ath11k_base *ab); 523 int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab); 524 525 #endif 526