1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/err.h>
12 #include <linux/mutex.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/property.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_clk.h>
20 #include <linux/clk.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rockchip_sip.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rockchip,rv1126-power.h>
28 #include <dt-bindings/power/rockchip,rv1126b-power-controller.h>
29 #include <dt-bindings/power/rk3036-power.h>
30 #include <dt-bindings/power/rk3066-power.h>
31 #include <dt-bindings/power/rk3128-power.h>
32 #include <dt-bindings/power/rk3188-power.h>
33 #include <dt-bindings/power/rk3228-power.h>
34 #include <dt-bindings/power/rk3288-power.h>
35 #include <dt-bindings/power/rk3328-power.h>
36 #include <dt-bindings/power/rk3366-power.h>
37 #include <dt-bindings/power/rk3368-power.h>
38 #include <dt-bindings/power/rk3399-power.h>
39 #include <dt-bindings/power/rockchip,rk3528-power.h>
40 #include <dt-bindings/power/rockchip,rk3562-power.h>
41 #include <dt-bindings/power/rk3568-power.h>
42 #include <dt-bindings/power/rockchip,rk3576-power.h>
43 #include <dt-bindings/power/rk3588-power.h>
44
45 struct rockchip_domain_info {
46 const char *name;
47 int pwr_mask;
48 int status_mask;
49 int req_mask;
50 int idle_mask;
51 int ack_mask;
52 bool active_wakeup;
53 bool need_regulator;
54 int pwr_w_mask;
55 int req_w_mask;
56 int clk_ungate_mask;
57 int mem_status_mask;
58 int repair_status_mask;
59 u32 pwr_offset;
60 u32 mem_offset;
61 u32 req_offset;
62 };
63
64 struct rockchip_pmu_info {
65 u32 pwr_offset;
66 u32 status_offset;
67 u32 req_offset;
68 u32 idle_offset;
69 u32 ack_offset;
70 u32 mem_pwr_offset;
71 u32 chain_status_offset;
72 u32 mem_status_offset;
73 u32 repair_status_offset;
74 u32 clk_ungate_offset;
75
76 u32 core_pwrcnt_offset;
77 u32 gpu_pwrcnt_offset;
78
79 unsigned int core_power_transition_time;
80 unsigned int gpu_power_transition_time;
81
82 int num_domains;
83 const struct rockchip_domain_info *domain_info;
84 };
85
86 #define MAX_QOS_REGS_NUM 5
87 #define QOS_PRIORITY 0x08
88 #define QOS_MODE 0x0c
89 #define QOS_BANDWIDTH 0x10
90 #define QOS_SATURATION 0x14
91 #define QOS_EXTCONTROL 0x18
92
93 struct rockchip_pm_domain {
94 struct generic_pm_domain genpd;
95 const struct rockchip_domain_info *info;
96 struct rockchip_pmu *pmu;
97 int num_qos;
98 struct regmap **qos_regmap;
99 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
100 int num_clks;
101 struct clk_bulk_data *clks;
102 struct device_node *node;
103 struct regulator *supply;
104 };
105
106 struct rockchip_pmu {
107 struct device *dev;
108 struct regmap *regmap;
109 const struct rockchip_pmu_info *info;
110 struct mutex mutex; /* mutex lock for pmu */
111 struct genpd_onecell_data genpd_data;
112 struct generic_pm_domain *domains[];
113 };
114
115 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
116
117 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
118 { \
119 .name = _name, \
120 .pwr_mask = (pwr), \
121 .status_mask = (status), \
122 .req_mask = (req), \
123 .idle_mask = (idle), \
124 .ack_mask = (ack), \
125 .active_wakeup = (wakeup), \
126 }
127
128 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
129 { \
130 .name = _name, \
131 .pwr_w_mask = (pwr) << 16, \
132 .pwr_mask = (pwr), \
133 .status_mask = (status), \
134 .req_w_mask = (req) << 16, \
135 .req_mask = (req), \
136 .idle_mask = (idle), \
137 .ack_mask = (ack), \
138 .active_wakeup = wakeup, \
139 }
140
141 #define DOMAIN_M_G(_name, pwr, status, req, idle, ack, g_mask, wakeup, keepon) \
142 { \
143 .name = _name, \
144 .pwr_w_mask = (pwr) << 16, \
145 .pwr_mask = (pwr), \
146 .status_mask = (status), \
147 .req_w_mask = (req) << 16, \
148 .req_mask = (req), \
149 .idle_mask = (idle), \
150 .ack_mask = (ack), \
151 .clk_ungate_mask = (g_mask), \
152 .active_wakeup = wakeup, \
153 }
154
155 #define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \
156 { \
157 .name = _name, \
158 .pwr_w_mask = (pwr) << 16, \
159 .pwr_mask = (pwr), \
160 .status_mask = (status), \
161 .req_w_mask = (req) << 16, \
162 .req_mask = (req), \
163 .idle_mask = (idle), \
164 .ack_mask = (ack), \
165 .clk_ungate_mask = (g_mask), \
166 .active_wakeup = wakeup, \
167 }
168
169 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \
170 { \
171 .name = _name, \
172 .pwr_offset = p_offset, \
173 .pwr_w_mask = (pwr) << 16, \
174 .pwr_mask = (pwr), \
175 .status_mask = (status), \
176 .mem_offset = m_offset, \
177 .mem_status_mask = (m_status), \
178 .repair_status_mask = (r_status), \
179 .req_offset = r_offset, \
180 .req_w_mask = (req) << 16, \
181 .req_mask = (req), \
182 .idle_mask = (idle), \
183 .ack_mask = (ack), \
184 .active_wakeup = wakeup, \
185 .need_regulator = regulator, \
186 }
187
188 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
189 { \
190 .name = _name, \
191 .pwr_offset = p_offset, \
192 .pwr_w_mask = (pwr) << 16, \
193 .pwr_mask = (pwr), \
194 .status_mask = (status), \
195 .mem_offset = m_offset, \
196 .mem_status_mask = (m_status), \
197 .repair_status_mask = (r_status), \
198 .req_offset = r_offset, \
199 .req_w_mask = (req) << 16, \
200 .req_mask = (req), \
201 .idle_mask = (idle), \
202 .clk_ungate_mask = (g_mask), \
203 .ack_mask = (ack), \
204 .active_wakeup = wakeup, \
205 }
206
207 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
208 { \
209 .name = _name, \
210 .req_mask = (req), \
211 .req_w_mask = (req) << 16, \
212 .ack_mask = (ack), \
213 .idle_mask = (idle), \
214 .active_wakeup = wakeup, \
215 }
216
217 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \
218 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
219
220 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
221 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
222
223 #define DOMAIN_RV1126B(name, pwr, req, wakeup) \
224 DOMAIN_M_G(name, pwr, pwr, req, req, req, req, wakeup, true)
225
226 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
227 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
228
229 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
230 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
231
232 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
233 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
234
235 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
236 DOMAIN(name, pwr, status, req, req, req, wakeup)
237
238 #define DOMAIN_RK3528(name, pwr, req) \
239 DOMAIN_M(name, pwr, pwr, req, req, req, false)
240
241 #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
242 DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
243
244 #define DOMAIN_RK3568(name, pwr, req, wakeup) \
245 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
246
247 #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
248 DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
249
250 /*
251 * Dynamic Memory Controller may need to coordinate with us -- see
252 * rockchip_pmu_block().
253 *
254 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
255 * block() while we're initializing the PMU.
256 */
257 static DEFINE_MUTEX(dmc_pmu_mutex);
258 static struct rockchip_pmu *dmc_pmu;
259
260 /*
261 * Block PMU transitions and make sure they don't interfere with ARM Trusted
262 * Firmware operations. There are two conflicts, noted in the comments below.
263 *
264 * Caller must unblock PMU transitions via rockchip_pmu_unblock().
265 */
rockchip_pmu_block(void)266 int rockchip_pmu_block(void)
267 {
268 struct rockchip_pmu *pmu;
269 struct generic_pm_domain *genpd;
270 struct rockchip_pm_domain *pd;
271 int i, ret;
272
273 mutex_lock(&dmc_pmu_mutex);
274
275 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
276 if (!dmc_pmu)
277 return 0;
278 pmu = dmc_pmu;
279
280 /*
281 * mutex blocks all idle transitions: we can't touch the
282 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
283 * Firmware might be using it.
284 */
285 mutex_lock(&pmu->mutex);
286
287 /*
288 * Power domain clocks: Per Rockchip, we *must* keep certain clocks
289 * enabled for the duration of power-domain transitions. Most
290 * transitions are handled by this driver, but some cases (in
291 * particular, DRAM DVFS / memory-controller idle) must be handled by
292 * firmware. Firmware can handle most clock management via a special
293 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
294 * doesn't handle PLLs. We can assist this transition by doing the
295 * clock management on behalf of firmware.
296 */
297 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
298 genpd = pmu->genpd_data.domains[i];
299 if (genpd) {
300 pd = to_rockchip_pd(genpd);
301 ret = clk_bulk_enable(pd->num_clks, pd->clks);
302 if (ret < 0) {
303 dev_err(pmu->dev,
304 "failed to enable clks for domain '%s': %d\n",
305 genpd->name, ret);
306 goto err;
307 }
308 }
309 }
310
311 return 0;
312
313 err:
314 for (i = i - 1; i >= 0; i--) {
315 genpd = pmu->genpd_data.domains[i];
316 if (genpd) {
317 pd = to_rockchip_pd(genpd);
318 clk_bulk_disable(pd->num_clks, pd->clks);
319 }
320 }
321 mutex_unlock(&pmu->mutex);
322 mutex_unlock(&dmc_pmu_mutex);
323
324 return ret;
325 }
326 EXPORT_SYMBOL_GPL(rockchip_pmu_block);
327
328 /* Unblock PMU transitions. */
rockchip_pmu_unblock(void)329 void rockchip_pmu_unblock(void)
330 {
331 struct rockchip_pmu *pmu;
332 struct generic_pm_domain *genpd;
333 struct rockchip_pm_domain *pd;
334 int i;
335
336 if (dmc_pmu) {
337 pmu = dmc_pmu;
338 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
339 genpd = pmu->genpd_data.domains[i];
340 if (genpd) {
341 pd = to_rockchip_pd(genpd);
342 clk_bulk_disable(pd->num_clks, pd->clks);
343 }
344 }
345
346 mutex_unlock(&pmu->mutex);
347 }
348
349 mutex_unlock(&dmc_pmu_mutex);
350 }
351 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
352
353 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup, regulator) \
354 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, regulator)
355
rockchip_pmu_domain_is_idle(struct rockchip_pm_domain * pd)356 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
357 {
358 struct rockchip_pmu *pmu = pd->pmu;
359 const struct rockchip_domain_info *pd_info = pd->info;
360 unsigned int val;
361
362 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
363 return (val & pd_info->idle_mask) == pd_info->idle_mask;
364 }
365
rockchip_pmu_read_ack(struct rockchip_pmu * pmu)366 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
367 {
368 unsigned int val;
369
370 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
371 return val;
372 }
373
rockchip_pmu_ungate_clk(struct rockchip_pm_domain * pd,bool ungate)374 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
375 {
376 const struct rockchip_domain_info *pd_info = pd->info;
377 struct rockchip_pmu *pmu = pd->pmu;
378 unsigned int val;
379 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16;
380
381 if (!pd_info->clk_ungate_mask)
382 return 0;
383
384 if (!pmu->info->clk_ungate_offset)
385 return 0;
386
387 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
388 clk_ungate_w_mask;
389 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
390
391 return 0;
392 }
393
rockchip_pmu_set_idle_request(struct rockchip_pm_domain * pd,bool idle)394 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
395 bool idle)
396 {
397 const struct rockchip_domain_info *pd_info = pd->info;
398 struct generic_pm_domain *genpd = &pd->genpd;
399 struct rockchip_pmu *pmu = pd->pmu;
400 u32 pd_req_offset = pd_info->req_offset;
401 unsigned int target_ack;
402 unsigned int val;
403 bool is_idle;
404 int ret;
405
406 if (pd_info->req_mask == 0)
407 return 0;
408 else if (pd_info->req_w_mask)
409 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
410 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
411 pd_info->req_w_mask);
412 else
413 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
414 pd_info->req_mask, idle ? -1U : 0);
415
416 wmb();
417
418 /* Wait util idle_ack = 1 */
419 target_ack = idle ? pd_info->ack_mask : 0;
420 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
421 (val & pd_info->ack_mask) == target_ack,
422 0, 10000);
423 if (ret) {
424 dev_err(pmu->dev,
425 "failed to get ack on domain '%s', val=0x%x\n",
426 genpd->name, val);
427 return ret;
428 }
429
430 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
431 is_idle, is_idle == idle, 0, 10000);
432 if (ret) {
433 dev_err(pmu->dev,
434 "failed to set idle on domain '%s', val=%d\n",
435 genpd->name, is_idle);
436 return ret;
437 }
438
439 return 0;
440 }
441
rockchip_pmu_save_qos(struct rockchip_pm_domain * pd)442 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
443 {
444 int i;
445
446 for (i = 0; i < pd->num_qos; i++) {
447 regmap_read(pd->qos_regmap[i],
448 QOS_PRIORITY,
449 &pd->qos_save_regs[0][i]);
450 regmap_read(pd->qos_regmap[i],
451 QOS_MODE,
452 &pd->qos_save_regs[1][i]);
453 regmap_read(pd->qos_regmap[i],
454 QOS_BANDWIDTH,
455 &pd->qos_save_regs[2][i]);
456 regmap_read(pd->qos_regmap[i],
457 QOS_SATURATION,
458 &pd->qos_save_regs[3][i]);
459 regmap_read(pd->qos_regmap[i],
460 QOS_EXTCONTROL,
461 &pd->qos_save_regs[4][i]);
462 }
463 return 0;
464 }
465
rockchip_pmu_restore_qos(struct rockchip_pm_domain * pd)466 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
467 {
468 int i;
469
470 for (i = 0; i < pd->num_qos; i++) {
471 regmap_write(pd->qos_regmap[i],
472 QOS_PRIORITY,
473 pd->qos_save_regs[0][i]);
474 regmap_write(pd->qos_regmap[i],
475 QOS_MODE,
476 pd->qos_save_regs[1][i]);
477 regmap_write(pd->qos_regmap[i],
478 QOS_BANDWIDTH,
479 pd->qos_save_regs[2][i]);
480 regmap_write(pd->qos_regmap[i],
481 QOS_SATURATION,
482 pd->qos_save_regs[3][i]);
483 regmap_write(pd->qos_regmap[i],
484 QOS_EXTCONTROL,
485 pd->qos_save_regs[4][i]);
486 }
487
488 return 0;
489 }
490
rockchip_pmu_domain_is_on(struct rockchip_pm_domain * pd)491 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
492 {
493 struct rockchip_pmu *pmu = pd->pmu;
494 unsigned int val;
495
496 if (pd->info->repair_status_mask) {
497 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
498 /* 1'b1: power on, 1'b0: power off */
499 return val & pd->info->repair_status_mask;
500 }
501
502 /* check idle status for idle-only domains */
503 if (pd->info->status_mask == 0)
504 return !rockchip_pmu_domain_is_idle(pd);
505
506 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
507
508 /* 1'b0: power on, 1'b1: power off */
509 return !(val & pd->info->status_mask);
510 }
511
rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain * pd)512 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
513 {
514 struct rockchip_pmu *pmu = pd->pmu;
515 unsigned int val;
516
517 regmap_read(pmu->regmap,
518 pmu->info->mem_status_offset + pd->info->mem_offset, &val);
519
520 /* 1'b0: power on, 1'b1: power off */
521 return !(val & pd->info->mem_status_mask);
522 }
523
rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain * pd)524 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
525 {
526 struct rockchip_pmu *pmu = pd->pmu;
527 unsigned int val;
528
529 regmap_read(pmu->regmap,
530 pmu->info->chain_status_offset + pd->info->mem_offset, &val);
531
532 /* 1'b1: power on, 1'b0: power off */
533 return val & pd->info->mem_status_mask;
534 }
535
rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain * pd)536 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
537 {
538 struct rockchip_pmu *pmu = pd->pmu;
539 struct generic_pm_domain *genpd = &pd->genpd;
540 bool is_on;
541 int ret = 0;
542
543 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
544 is_on == true, 0, 10000);
545 if (ret) {
546 dev_err(pmu->dev,
547 "failed to get chain status '%s', target_on=1, val=%d\n",
548 genpd->name, is_on);
549 goto error;
550 }
551
552 udelay(20);
553
554 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
555 (pd->info->pwr_mask | pd->info->pwr_w_mask));
556 wmb();
557
558 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
559 is_on == false, 0, 10000);
560 if (ret) {
561 dev_err(pmu->dev,
562 "failed to get mem status '%s', target_on=0, val=%d\n",
563 genpd->name, is_on);
564 goto error;
565 }
566
567 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
568 pd->info->pwr_w_mask);
569 wmb();
570
571 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
572 is_on == true, 0, 10000);
573 if (ret) {
574 dev_err(pmu->dev,
575 "failed to get mem status '%s', target_on=1, val=%d\n",
576 genpd->name, is_on);
577 }
578
579 error:
580 return ret;
581 }
582
rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain * pd,bool on)583 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
584 bool on)
585 {
586 struct rockchip_pmu *pmu = pd->pmu;
587 struct generic_pm_domain *genpd = &pd->genpd;
588 u32 pd_pwr_offset = pd->info->pwr_offset;
589 bool is_on, is_mem_on = false;
590 struct arm_smccc_res res;
591 int ret;
592
593 if (pd->info->pwr_mask == 0)
594 return 0;
595
596 if (on && pd->info->mem_status_mask)
597 is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
598
599 if (pd->info->pwr_w_mask)
600 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
601 on ? pd->info->pwr_w_mask :
602 (pd->info->pwr_mask | pd->info->pwr_w_mask));
603 else
604 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
605 pd->info->pwr_mask, on ? 0 : -1U);
606
607 wmb();
608
609 if (is_mem_on) {
610 ret = rockchip_pmu_domain_mem_reset(pd);
611 if (ret)
612 return ret;
613 }
614
615
616 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
617 is_on == on, 0, 10000);
618 if (ret) {
619 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n",
620 genpd->name, on ? "on" : "off", is_on);
621 return ret;
622 }
623
624 /* Inform firmware to keep this pd on or off */
625 if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE)
626 arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
627 pmu->info->pwr_offset + pd_pwr_offset,
628 pd->info->pwr_mask, on, 0, 0, 0, &res);
629
630 return 0;
631 }
632
rockchip_pd_power(struct rockchip_pm_domain * pd,bool power_on)633 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
634 {
635 struct rockchip_pmu *pmu = pd->pmu;
636 int ret;
637
638 guard(mutex)(&pmu->mutex);
639
640 if (rockchip_pmu_domain_is_on(pd) == power_on)
641 return 0;
642
643 ret = clk_bulk_enable(pd->num_clks, pd->clks);
644 if (ret < 0) {
645 dev_err(pmu->dev, "failed to enable clocks\n");
646 return ret;
647 }
648
649 rockchip_pmu_ungate_clk(pd, true);
650
651 if (!power_on) {
652 rockchip_pmu_save_qos(pd);
653
654 /* if powering down, idle request to NIU first */
655 ret = rockchip_pmu_set_idle_request(pd, true);
656 if (ret < 0)
657 goto out;
658 }
659
660 ret = rockchip_do_pmu_set_power_domain(pd, power_on);
661 if (ret < 0)
662 goto out;
663
664 if (power_on) {
665 /* if powering up, leave idle mode */
666 ret = rockchip_pmu_set_idle_request(pd, false);
667 if (ret < 0)
668 goto out;
669
670 rockchip_pmu_restore_qos(pd);
671 }
672
673 out:
674 rockchip_pmu_ungate_clk(pd, false);
675 clk_bulk_disable(pd->num_clks, pd->clks);
676
677 return ret;
678 }
679
rockchip_pd_regulator_disable(struct rockchip_pm_domain * pd)680 static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd)
681 {
682 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply);
683 }
684
rockchip_pd_regulator_enable(struct rockchip_pm_domain * pd)685 static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd)
686 {
687 struct rockchip_pmu *pmu = pd->pmu;
688
689 if (!pd->info->need_regulator)
690 return 0;
691
692 if (IS_ERR_OR_NULL(pd->supply)) {
693 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain");
694
695 if (IS_ERR(pd->supply))
696 return PTR_ERR(pd->supply);
697 }
698
699 return regulator_enable(pd->supply);
700 }
701
rockchip_pd_power_on(struct generic_pm_domain * domain)702 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
703 {
704 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
705 int ret;
706
707 ret = rockchip_pd_regulator_enable(pd);
708 if (ret) {
709 dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret);
710 return ret;
711 }
712
713 ret = rockchip_pd_power(pd, true);
714 if (ret)
715 rockchip_pd_regulator_disable(pd);
716
717 return ret;
718 }
719
rockchip_pd_power_off(struct generic_pm_domain * domain)720 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
721 {
722 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
723 int ret;
724
725 ret = rockchip_pd_power(pd, false);
726 if (ret)
727 return ret;
728
729 rockchip_pd_regulator_disable(pd);
730 return ret;
731 }
732
rockchip_pd_attach_dev(struct generic_pm_domain * genpd,struct device * dev)733 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
734 struct device *dev)
735 {
736 struct clk *clk;
737 int i;
738 int error;
739
740 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
741
742 error = pm_clk_create(dev);
743 if (error) {
744 dev_err(dev, "pm_clk_create failed %d\n", error);
745 return error;
746 }
747
748 i = 0;
749 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
750 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
751 error = pm_clk_add_clk(dev, clk);
752 if (error) {
753 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
754 clk_put(clk);
755 pm_clk_destroy(dev);
756 return error;
757 }
758 }
759
760 return 0;
761 }
762
rockchip_pd_detach_dev(struct generic_pm_domain * genpd,struct device * dev)763 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
764 struct device *dev)
765 {
766 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
767
768 pm_clk_destroy(dev);
769 }
770
rockchip_pm_add_one_domain(struct rockchip_pmu * pmu,struct device_node * node)771 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
772 struct device_node *node)
773 {
774 const struct rockchip_domain_info *pd_info;
775 struct rockchip_pm_domain *pd;
776 struct device_node *qos_node;
777 int i, j;
778 u32 id;
779 int error;
780
781 error = of_property_read_u32(node, "reg", &id);
782 if (error) {
783 dev_err(pmu->dev,
784 "%pOFn: failed to retrieve domain id (reg): %d\n",
785 node, error);
786 return -EINVAL;
787 }
788
789 if (id >= pmu->info->num_domains) {
790 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
791 node, id);
792 return -EINVAL;
793 }
794 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
795 if (pmu->genpd_data.domains[id])
796 return 0;
797
798 pd_info = &pmu->info->domain_info[id];
799 if (!pd_info) {
800 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
801 node, id);
802 return -EINVAL;
803 }
804
805 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
806 if (!pd)
807 return -ENOMEM;
808
809 pd->info = pd_info;
810 pd->pmu = pmu;
811 pd->node = node;
812
813 pd->num_clks = of_clk_get_parent_count(node);
814 if (pd->num_clks > 0) {
815 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
816 sizeof(*pd->clks), GFP_KERNEL);
817 if (!pd->clks)
818 return -ENOMEM;
819 } else {
820 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
821 node, pd->num_clks);
822 pd->num_clks = 0;
823 }
824
825 for (i = 0; i < pd->num_clks; i++) {
826 pd->clks[i].clk = of_clk_get(node, i);
827 if (IS_ERR(pd->clks[i].clk)) {
828 error = PTR_ERR(pd->clks[i].clk);
829 dev_err(pmu->dev,
830 "%pOFn: failed to get clk at index %d: %d\n",
831 node, i, error);
832 return error;
833 }
834 }
835
836 error = clk_bulk_prepare(pd->num_clks, pd->clks);
837 if (error)
838 goto err_put_clocks;
839
840 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
841 NULL);
842
843 if (pd->num_qos > 0) {
844 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
845 sizeof(*pd->qos_regmap),
846 GFP_KERNEL);
847 if (!pd->qos_regmap) {
848 error = -ENOMEM;
849 goto err_unprepare_clocks;
850 }
851
852 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
853 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
854 pd->num_qos,
855 sizeof(u32),
856 GFP_KERNEL);
857 if (!pd->qos_save_regs[j]) {
858 error = -ENOMEM;
859 goto err_unprepare_clocks;
860 }
861 }
862
863 for (j = 0; j < pd->num_qos; j++) {
864 qos_node = of_parse_phandle(node, "pm_qos", j);
865 if (!qos_node) {
866 error = -ENODEV;
867 goto err_unprepare_clocks;
868 }
869 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
870 of_node_put(qos_node);
871 if (IS_ERR(pd->qos_regmap[j])) {
872 error = -ENODEV;
873 goto err_unprepare_clocks;
874 }
875 }
876 }
877
878 if (pd->info->name)
879 pd->genpd.name = pd->info->name;
880 else
881 pd->genpd.name = kbasename(node->full_name);
882
883 /*
884 * power domain's needing a regulator should default to off, since
885 * the regulator state is unknown at probe time. Also the regulator
886 * state cannot be checked, since that usually requires IP needing
887 * (a different) power domain.
888 */
889 if (pd->info->need_regulator)
890 rockchip_pd_power(pd, false);
891
892 pd->genpd.power_off = rockchip_pd_power_off;
893 pd->genpd.power_on = rockchip_pd_power_on;
894 pd->genpd.attach_dev = rockchip_pd_attach_dev;
895 pd->genpd.detach_dev = rockchip_pd_detach_dev;
896 pd->genpd.flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_NO_STAY_ON;
897 if (pd_info->active_wakeup)
898 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
899 pm_genpd_init(&pd->genpd, NULL,
900 !rockchip_pmu_domain_is_on(pd) ||
901 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
902
903 pmu->genpd_data.domains[id] = &pd->genpd;
904 return 0;
905
906 err_unprepare_clocks:
907 clk_bulk_unprepare(pd->num_clks, pd->clks);
908 err_put_clocks:
909 clk_bulk_put(pd->num_clks, pd->clks);
910 return error;
911 }
912
rockchip_pm_remove_one_domain(struct rockchip_pm_domain * pd)913 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
914 {
915 int ret;
916
917 /*
918 * We're in the error cleanup already, so we only complain,
919 * but won't emit another error on top of the original one.
920 */
921 ret = pm_genpd_remove(&pd->genpd);
922 if (ret < 0)
923 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
924 pd->genpd.name, ret);
925
926 clk_bulk_unprepare(pd->num_clks, pd->clks);
927 clk_bulk_put(pd->num_clks, pd->clks);
928
929 /* protect the zeroing of pm->num_clks */
930 mutex_lock(&pd->pmu->mutex);
931 pd->num_clks = 0;
932 mutex_unlock(&pd->pmu->mutex);
933
934 /* devm will free our memory */
935 }
936
rockchip_pm_domain_cleanup(struct rockchip_pmu * pmu)937 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
938 {
939 struct generic_pm_domain *genpd;
940 struct rockchip_pm_domain *pd;
941 int i;
942
943 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
944 genpd = pmu->genpd_data.domains[i];
945 if (genpd) {
946 pd = to_rockchip_pd(genpd);
947 rockchip_pm_remove_one_domain(pd);
948 }
949 }
950
951 /* devm will free our memory */
952 }
953
rockchip_configure_pd_cnt(struct rockchip_pmu * pmu,u32 domain_reg_offset,unsigned int count)954 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
955 u32 domain_reg_offset,
956 unsigned int count)
957 {
958 /* First configure domain power down transition count ... */
959 regmap_write(pmu->regmap, domain_reg_offset, count);
960 /* ... and then power up count. */
961 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
962 }
963
rockchip_pm_add_subdomain(struct rockchip_pmu * pmu,struct device_node * parent)964 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
965 struct device_node *parent)
966 {
967 struct generic_pm_domain *child_domain, *parent_domain;
968 int error;
969
970 for_each_child_of_node_scoped(parent, np) {
971 u32 idx;
972
973 error = of_property_read_u32(parent, "reg", &idx);
974 if (error) {
975 dev_err(pmu->dev,
976 "%pOFn: failed to retrieve domain id (reg): %d\n",
977 parent, error);
978 return error;
979 }
980 parent_domain = pmu->genpd_data.domains[idx];
981
982 error = rockchip_pm_add_one_domain(pmu, np);
983 if (error) {
984 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
985 np, error);
986 return error;
987 }
988
989 error = of_property_read_u32(np, "reg", &idx);
990 if (error) {
991 dev_err(pmu->dev,
992 "%pOFn: failed to retrieve domain id (reg): %d\n",
993 np, error);
994 return error;
995 }
996 child_domain = pmu->genpd_data.domains[idx];
997
998 error = pm_genpd_add_subdomain(parent_domain, child_domain);
999 if (error) {
1000 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
1001 parent_domain->name, child_domain->name, error);
1002 return error;
1003 } else {
1004 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
1005 parent_domain->name, child_domain->name);
1006 }
1007
1008 rockchip_pm_add_subdomain(pmu, np);
1009 }
1010
1011 return 0;
1012 }
1013
rockchip_pm_domain_probe(struct platform_device * pdev)1014 static int rockchip_pm_domain_probe(struct platform_device *pdev)
1015 {
1016 struct device *dev = &pdev->dev;
1017 struct device_node *np = dev->of_node;
1018 struct device *parent;
1019 struct rockchip_pmu *pmu;
1020 const struct rockchip_pmu_info *pmu_info;
1021 int error;
1022
1023 if (!np) {
1024 dev_err(dev, "device tree node not found\n");
1025 return -ENODEV;
1026 }
1027
1028 pmu_info = device_get_match_data(dev);
1029
1030 pmu = devm_kzalloc(dev,
1031 struct_size(pmu, domains, pmu_info->num_domains),
1032 GFP_KERNEL);
1033 if (!pmu)
1034 return -ENOMEM;
1035
1036 pmu->dev = &pdev->dev;
1037 mutex_init(&pmu->mutex);
1038
1039 pmu->info = pmu_info;
1040
1041 pmu->genpd_data.domains = pmu->domains;
1042 pmu->genpd_data.num_domains = pmu_info->num_domains;
1043
1044 parent = dev->parent;
1045 if (!parent) {
1046 dev_err(dev, "no parent for syscon devices\n");
1047 return -ENODEV;
1048 }
1049
1050 pmu->regmap = syscon_node_to_regmap(parent->of_node);
1051 if (IS_ERR(pmu->regmap)) {
1052 dev_err(dev, "no regmap available\n");
1053 return PTR_ERR(pmu->regmap);
1054 }
1055
1056 /*
1057 * Configure power up and down transition delays for CORE
1058 * and GPU domains.
1059 */
1060 if (pmu_info->core_power_transition_time)
1061 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
1062 pmu_info->core_power_transition_time);
1063 if (pmu_info->gpu_pwrcnt_offset)
1064 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
1065 pmu_info->gpu_power_transition_time);
1066
1067 error = -ENODEV;
1068
1069 /*
1070 * Prevent any rockchip_pmu_block() from racing with the remainder of
1071 * setup (clocks, register initialization).
1072 */
1073 guard(mutex)(&dmc_pmu_mutex);
1074
1075 for_each_available_child_of_node_scoped(np, node) {
1076 error = rockchip_pm_add_one_domain(pmu, node);
1077 if (error) {
1078 dev_err(dev, "failed to handle node %pOFn: %d\n",
1079 node, error);
1080 goto err_out;
1081 }
1082
1083 error = rockchip_pm_add_subdomain(pmu, node);
1084 if (error < 0) {
1085 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1086 node, error);
1087 goto err_out;
1088 }
1089 }
1090
1091 if (error) {
1092 dev_dbg(dev, "no power domains defined\n");
1093 goto err_out;
1094 }
1095
1096 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
1097 if (error) {
1098 dev_err(dev, "failed to add provider: %d\n", error);
1099 goto err_out;
1100 }
1101
1102 /* We only expect one PMU. */
1103 if (!WARN_ON_ONCE(dmc_pmu))
1104 dmc_pmu = pmu;
1105
1106 return 0;
1107
1108 err_out:
1109 rockchip_pm_domain_cleanup(pmu);
1110 return error;
1111 }
1112
1113 static const struct rockchip_domain_info px30_pm_domains[] = {
1114 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
1115 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1116 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1117 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
1118 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
1119 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
1120 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
1121 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
1122 };
1123
1124 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1125 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
1126 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
1127 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
1128 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
1129 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
1130 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
1131 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
1132 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
1133 };
1134
1135 static const struct rockchip_domain_info rv1126b_pm_domains[] = {
1136 /* name pwr req wakeup */
1137 [RV1126B_PD_NPU] = DOMAIN_RV1126B("npu", BIT(0), BIT(8), false),
1138 [RV1126B_PD_VDO] = DOMAIN_RV1126B("vdo", BIT(1), BIT(9), false),
1139 [RV1126B_PD_AIISP] = DOMAIN_RV1126B("aiisp", BIT(2), BIT(10), false),
1140 };
1141
1142 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1143 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1144 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1145 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1146 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
1147 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
1148 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
1149 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
1150 };
1151
1152 static const struct rockchip_domain_info rk3066_pm_domains[] = {
1153 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1154 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1155 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1156 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1157 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
1158 };
1159
1160 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1161 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1162 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1163 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
1164 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1165 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1166 };
1167
1168 static const struct rockchip_domain_info rk3188_pm_domains[] = {
1169 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1170 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1171 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1172 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1173 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1174 };
1175
1176 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1177 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1178 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1179 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1180 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1181 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1182 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1183 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1184 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1185 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1186 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1187 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1188 };
1189
1190 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1191 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
1192 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1193 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1194 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1195 };
1196
1197 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1198 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1199 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1200 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1201 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1202 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1203 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1204 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1205 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1206 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1207 };
1208
1209 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1210 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1211 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
1212 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1213 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1214 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1215 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1216 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1217 };
1218
1219 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1220 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1221 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
1222 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1223 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1224 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1225 };
1226
1227 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1228 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1229 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1230 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1231 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1232 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1233 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1234 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1235 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1236 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
1237 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1238 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1239 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1240 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1241 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1242 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1243 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1244 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1245 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1246 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1247 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1248 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1249 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1250 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1251 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1252 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1253 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1254 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1255 };
1256
1257 static const struct rockchip_domain_info rk3528_pm_domains[] = {
1258 [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4)),
1259 [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5)),
1260 [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6)),
1261 [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7)),
1262 [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8)),
1263 };
1264
1265 static const struct rockchip_domain_info rk3562_pm_domains[] = {
1266 /* name pwr req g_mask mem wakeup */
1267 [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false),
1268 [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false),
1269 [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false),
1270 [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false),
1271 [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false),
1272 [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false),
1273 [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false),
1274 [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false),
1275 };
1276
1277 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1278 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1279 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1280 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1281 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1282 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1283 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1284 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1285 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1286 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1287 };
1288
1289 static const struct rockchip_domain_info rk3576_pm_domains[] = {
1290 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false),
1291 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false),
1292 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false),
1293 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false),
1294 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false),
1295 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false),
1296 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
1297 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
1298 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
1299 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
1300 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
1301 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
1302 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
1303 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
1304 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
1305 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
1306 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
1307 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
1308 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
1309 };
1310
1311 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1312 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
1313 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
1314 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, false),
1315 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
1316 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
1317 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
1318 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
1319 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
1320 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
1321 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false, false),
1322 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false, false),
1323 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false, false),
1324 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false, false),
1325 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false, false),
1326 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false, false),
1327 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false, false),
1328 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false, false),
1329 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false, false),
1330 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false, false),
1331 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false, false),
1332 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false, false),
1333 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false, false),
1334 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false, false),
1335 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true, false),
1336 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false, false),
1337 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false, false),
1338 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false, false),
1339 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true, false),
1340 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false, false),
1341 };
1342
1343 static const struct rockchip_pmu_info px30_pmu = {
1344 .pwr_offset = 0x18,
1345 .status_offset = 0x20,
1346 .req_offset = 0x64,
1347 .idle_offset = 0x6c,
1348 .ack_offset = 0x6c,
1349
1350 .num_domains = ARRAY_SIZE(px30_pm_domains),
1351 .domain_info = px30_pm_domains,
1352 };
1353
1354 static const struct rockchip_pmu_info rk3036_pmu = {
1355 .req_offset = 0x148,
1356 .idle_offset = 0x14c,
1357 .ack_offset = 0x14c,
1358
1359 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1360 .domain_info = rk3036_pm_domains,
1361 };
1362
1363 static const struct rockchip_pmu_info rk3066_pmu = {
1364 .pwr_offset = 0x08,
1365 .status_offset = 0x0c,
1366 .req_offset = 0x38, /* PMU_MISC_CON1 */
1367 .idle_offset = 0x0c,
1368 .ack_offset = 0x0c,
1369
1370 .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1371 .domain_info = rk3066_pm_domains,
1372 };
1373
1374 static const struct rockchip_pmu_info rk3128_pmu = {
1375 .pwr_offset = 0x04,
1376 .status_offset = 0x08,
1377 .req_offset = 0x0c,
1378 .idle_offset = 0x10,
1379 .ack_offset = 0x10,
1380
1381 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1382 .domain_info = rk3128_pm_domains,
1383 };
1384
1385 static const struct rockchip_pmu_info rk3188_pmu = {
1386 .pwr_offset = 0x08,
1387 .status_offset = 0x0c,
1388 .req_offset = 0x38, /* PMU_MISC_CON1 */
1389 .idle_offset = 0x0c,
1390 .ack_offset = 0x0c,
1391
1392 .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1393 .domain_info = rk3188_pm_domains,
1394 };
1395
1396 static const struct rockchip_pmu_info rk3228_pmu = {
1397 .req_offset = 0x40c,
1398 .idle_offset = 0x488,
1399 .ack_offset = 0x488,
1400
1401 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1402 .domain_info = rk3228_pm_domains,
1403 };
1404
1405 static const struct rockchip_pmu_info rk3288_pmu = {
1406 .pwr_offset = 0x08,
1407 .status_offset = 0x0c,
1408 .req_offset = 0x10,
1409 .idle_offset = 0x14,
1410 .ack_offset = 0x14,
1411
1412 .core_pwrcnt_offset = 0x34,
1413 .gpu_pwrcnt_offset = 0x3c,
1414
1415 .core_power_transition_time = 24, /* 1us */
1416 .gpu_power_transition_time = 24, /* 1us */
1417
1418 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1419 .domain_info = rk3288_pm_domains,
1420 };
1421
1422 static const struct rockchip_pmu_info rk3328_pmu = {
1423 .req_offset = 0x414,
1424 .idle_offset = 0x484,
1425 .ack_offset = 0x484,
1426
1427 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1428 .domain_info = rk3328_pm_domains,
1429 };
1430
1431 static const struct rockchip_pmu_info rk3366_pmu = {
1432 .pwr_offset = 0x0c,
1433 .status_offset = 0x10,
1434 .req_offset = 0x3c,
1435 .idle_offset = 0x40,
1436 .ack_offset = 0x40,
1437
1438 .core_pwrcnt_offset = 0x48,
1439 .gpu_pwrcnt_offset = 0x50,
1440
1441 .core_power_transition_time = 24,
1442 .gpu_power_transition_time = 24,
1443
1444 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1445 .domain_info = rk3366_pm_domains,
1446 };
1447
1448 static const struct rockchip_pmu_info rk3368_pmu = {
1449 .pwr_offset = 0x0c,
1450 .status_offset = 0x10,
1451 .req_offset = 0x3c,
1452 .idle_offset = 0x40,
1453 .ack_offset = 0x40,
1454
1455 .core_pwrcnt_offset = 0x48,
1456 .gpu_pwrcnt_offset = 0x50,
1457
1458 .core_power_transition_time = 24,
1459 .gpu_power_transition_time = 24,
1460
1461 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1462 .domain_info = rk3368_pm_domains,
1463 };
1464
1465 static const struct rockchip_pmu_info rk3399_pmu = {
1466 .pwr_offset = 0x14,
1467 .status_offset = 0x18,
1468 .req_offset = 0x60,
1469 .idle_offset = 0x64,
1470 .ack_offset = 0x68,
1471
1472 /* ARM Trusted Firmware manages power transition times */
1473
1474 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1475 .domain_info = rk3399_pm_domains,
1476 };
1477
1478 static const struct rockchip_pmu_info rk3528_pmu = {
1479 .pwr_offset = 0x1210,
1480 .status_offset = 0x1230,
1481 .req_offset = 0x1110,
1482 .idle_offset = 0x1128,
1483 .ack_offset = 0x1120,
1484
1485 .num_domains = ARRAY_SIZE(rk3528_pm_domains),
1486 .domain_info = rk3528_pm_domains,
1487 };
1488
1489 static const struct rockchip_pmu_info rk3562_pmu = {
1490 .pwr_offset = 0x210,
1491 .status_offset = 0x230,
1492 .req_offset = 0x110,
1493 .idle_offset = 0x128,
1494 .ack_offset = 0x120,
1495 .clk_ungate_offset = 0x140,
1496
1497 .num_domains = ARRAY_SIZE(rk3562_pm_domains),
1498 .domain_info = rk3562_pm_domains,
1499 };
1500
1501 static const struct rockchip_pmu_info rk3568_pmu = {
1502 .pwr_offset = 0xa0,
1503 .status_offset = 0x98,
1504 .req_offset = 0x50,
1505 .idle_offset = 0x68,
1506 .ack_offset = 0x60,
1507
1508 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1509 .domain_info = rk3568_pm_domains,
1510 };
1511
1512 static const struct rockchip_pmu_info rk3576_pmu = {
1513 .pwr_offset = 0x210,
1514 .status_offset = 0x230,
1515 .chain_status_offset = 0x248,
1516 .mem_status_offset = 0x250,
1517 .mem_pwr_offset = 0x300,
1518 .req_offset = 0x110,
1519 .idle_offset = 0x128,
1520 .ack_offset = 0x120,
1521 .repair_status_offset = 0x570,
1522 .clk_ungate_offset = 0x140,
1523
1524 .num_domains = ARRAY_SIZE(rk3576_pm_domains),
1525 .domain_info = rk3576_pm_domains,
1526 };
1527
1528 static const struct rockchip_pmu_info rk3588_pmu = {
1529 .pwr_offset = 0x14c,
1530 .status_offset = 0x180,
1531 .req_offset = 0x10c,
1532 .idle_offset = 0x120,
1533 .ack_offset = 0x118,
1534 .mem_pwr_offset = 0x1a0,
1535 .chain_status_offset = 0x1f0,
1536 .mem_status_offset = 0x1f8,
1537 .repair_status_offset = 0x290,
1538
1539 .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1540 .domain_info = rk3588_pm_domains,
1541 };
1542
1543 static const struct rockchip_pmu_info rv1126_pmu = {
1544 .pwr_offset = 0x110,
1545 .status_offset = 0x108,
1546 .req_offset = 0xc0,
1547 .idle_offset = 0xd8,
1548 .ack_offset = 0xd0,
1549
1550 .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1551 .domain_info = rv1126_pm_domains,
1552 };
1553
1554 static const struct rockchip_pmu_info rv1126b_pmu = {
1555 .pwr_offset = 0x210,
1556 .status_offset = 0x230,
1557 .req_offset = 0x110,
1558 .idle_offset = 0x128,
1559 .ack_offset = 0x120,
1560 .clk_ungate_offset = 0x140,
1561
1562 .num_domains = ARRAY_SIZE(rv1126b_pm_domains),
1563 .domain_info = rv1126b_pm_domains,
1564 };
1565
1566 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1567 {
1568 .compatible = "rockchip,px30-power-controller",
1569 .data = (void *)&px30_pmu,
1570 },
1571 {
1572 .compatible = "rockchip,rk3036-power-controller",
1573 .data = (void *)&rk3036_pmu,
1574 },
1575 {
1576 .compatible = "rockchip,rk3066-power-controller",
1577 .data = (void *)&rk3066_pmu,
1578 },
1579 {
1580 .compatible = "rockchip,rk3128-power-controller",
1581 .data = (void *)&rk3128_pmu,
1582 },
1583 {
1584 .compatible = "rockchip,rk3188-power-controller",
1585 .data = (void *)&rk3188_pmu,
1586 },
1587 {
1588 .compatible = "rockchip,rk3228-power-controller",
1589 .data = (void *)&rk3228_pmu,
1590 },
1591 {
1592 .compatible = "rockchip,rk3288-power-controller",
1593 .data = (void *)&rk3288_pmu,
1594 },
1595 {
1596 .compatible = "rockchip,rk3328-power-controller",
1597 .data = (void *)&rk3328_pmu,
1598 },
1599 {
1600 .compatible = "rockchip,rk3366-power-controller",
1601 .data = (void *)&rk3366_pmu,
1602 },
1603 {
1604 .compatible = "rockchip,rk3368-power-controller",
1605 .data = (void *)&rk3368_pmu,
1606 },
1607 {
1608 .compatible = "rockchip,rk3399-power-controller",
1609 .data = (void *)&rk3399_pmu,
1610 },
1611 {
1612 .compatible = "rockchip,rk3528-power-controller",
1613 .data = (void *)&rk3528_pmu,
1614 },
1615 {
1616 .compatible = "rockchip,rk3562-power-controller",
1617 .data = (void *)&rk3562_pmu,
1618 },
1619 {
1620 .compatible = "rockchip,rk3568-power-controller",
1621 .data = (void *)&rk3568_pmu,
1622 },
1623 {
1624 .compatible = "rockchip,rk3576-power-controller",
1625 .data = (void *)&rk3576_pmu,
1626 },
1627 {
1628 .compatible = "rockchip,rk3588-power-controller",
1629 .data = (void *)&rk3588_pmu,
1630 },
1631 {
1632 .compatible = "rockchip,rv1126-power-controller",
1633 .data = (void *)&rv1126_pmu,
1634 },
1635 {
1636 .compatible = "rockchip,rv1126b-power-controller",
1637 .data = (void *)&rv1126b_pmu,
1638 },
1639 { /* sentinel */ },
1640 };
1641
1642 static struct platform_driver rockchip_pm_domain_driver = {
1643 .probe = rockchip_pm_domain_probe,
1644 .driver = {
1645 .name = "rockchip-pm-domain",
1646 .of_match_table = rockchip_pm_domain_dt_match,
1647 /*
1648 * We can't forcibly eject devices from the power
1649 * domain, so we can't really remove power domains
1650 * once they were added.
1651 */
1652 .suppress_bind_attrs = true,
1653 },
1654 };
1655
rockchip_pm_domain_drv_register(void)1656 static int __init rockchip_pm_domain_drv_register(void)
1657 {
1658 return platform_driver_register(&rockchip_pm_domain_driver);
1659 }
1660 postcore_initcall(rockchip_pm_domain_drv_register);
1661