1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Ltd
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
14
15 #include "bcm-voter.h"
16 #include "icc-rpmh.h"
17 #include "sc8280xp.h"
18
19 static struct qcom_icc_node qhm_qspi = {
20 .name = "qhm_qspi",
21 .id = SC8280XP_MASTER_QSPI_0,
22 .channels = 1,
23 .buswidth = 4,
24 .num_links = 1,
25 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
26 };
27
28 static struct qcom_icc_node qhm_qup1 = {
29 .name = "qhm_qup1",
30 .id = SC8280XP_MASTER_QUP_1,
31 .channels = 1,
32 .buswidth = 4,
33 .num_links = 1,
34 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
35 };
36
37 static struct qcom_icc_node qhm_qup2 = {
38 .name = "qhm_qup2",
39 .id = SC8280XP_MASTER_QUP_2,
40 .channels = 1,
41 .buswidth = 4,
42 .num_links = 1,
43 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
44 };
45
46 static struct qcom_icc_node qnm_a1noc_cfg = {
47 .name = "qnm_a1noc_cfg",
48 .id = SC8280XP_MASTER_A1NOC_CFG,
49 .channels = 1,
50 .buswidth = 4,
51 .num_links = 1,
52 .links = { SC8280XP_SLAVE_SERVICE_A1NOC },
53 };
54
55 static struct qcom_icc_node qxm_ipa = {
56 .name = "qxm_ipa",
57 .id = SC8280XP_MASTER_IPA,
58 .channels = 1,
59 .buswidth = 8,
60 .num_links = 1,
61 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
62 };
63
64 static struct qcom_icc_node xm_emac_1 = {
65 .name = "xm_emac_1",
66 .id = SC8280XP_MASTER_EMAC_1,
67 .channels = 1,
68 .buswidth = 8,
69 .num_links = 1,
70 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
71 };
72
73 static struct qcom_icc_node xm_sdc4 = {
74 .name = "xm_sdc4",
75 .id = SC8280XP_MASTER_SDCC_4,
76 .channels = 1,
77 .buswidth = 8,
78 .num_links = 1,
79 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
80 };
81
82 static struct qcom_icc_node xm_ufs_mem = {
83 .name = "xm_ufs_mem",
84 .id = SC8280XP_MASTER_UFS_MEM,
85 .channels = 1,
86 .buswidth = 8,
87 .num_links = 1,
88 .links = { SC8280XP_SLAVE_A1NOC_SNOC },
89 };
90
91 static struct qcom_icc_node xm_usb3_0 = {
92 .name = "xm_usb3_0",
93 .id = SC8280XP_MASTER_USB3_0,
94 .channels = 1,
95 .buswidth = 8,
96 .num_links = 1,
97 .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
98 };
99
100 static struct qcom_icc_node xm_usb3_1 = {
101 .name = "xm_usb3_1",
102 .id = SC8280XP_MASTER_USB3_1,
103 .channels = 1,
104 .buswidth = 8,
105 .num_links = 1,
106 .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
107 };
108
109 static struct qcom_icc_node xm_usb3_mp = {
110 .name = "xm_usb3_mp",
111 .id = SC8280XP_MASTER_USB3_MP,
112 .channels = 1,
113 .buswidth = 16,
114 .num_links = 1,
115 .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
116 };
117
118 static struct qcom_icc_node xm_usb4_host0 = {
119 .name = "xm_usb4_host0",
120 .id = SC8280XP_MASTER_USB4_0,
121 .channels = 1,
122 .buswidth = 16,
123 .num_links = 1,
124 .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
125 };
126
127 static struct qcom_icc_node xm_usb4_host1 = {
128 .name = "xm_usb4_host1",
129 .id = SC8280XP_MASTER_USB4_1,
130 .channels = 1,
131 .buswidth = 16,
132 .num_links = 1,
133 .links = { SC8280XP_SLAVE_USB_NOC_SNOC },
134 };
135
136 static struct qcom_icc_node qhm_qdss_bam = {
137 .name = "qhm_qdss_bam",
138 .id = SC8280XP_MASTER_QDSS_BAM,
139 .channels = 1,
140 .buswidth = 4,
141 .num_links = 1,
142 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
143 };
144
145 static struct qcom_icc_node qhm_qup0 = {
146 .name = "qhm_qup0",
147 .id = SC8280XP_MASTER_QUP_0,
148 .channels = 1,
149 .buswidth = 4,
150 .num_links = 1,
151 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
152 };
153
154 static struct qcom_icc_node qnm_a2noc_cfg = {
155 .name = "qnm_a2noc_cfg",
156 .id = SC8280XP_MASTER_A2NOC_CFG,
157 .channels = 1,
158 .buswidth = 4,
159 .num_links = 1,
160 .links = { SC8280XP_SLAVE_SERVICE_A2NOC },
161 };
162
163 static struct qcom_icc_node qxm_crypto = {
164 .name = "qxm_crypto",
165 .id = SC8280XP_MASTER_CRYPTO,
166 .channels = 1,
167 .buswidth = 8,
168 .num_links = 1,
169 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
170 };
171
172 static struct qcom_icc_node qxm_sensorss_q6 = {
173 .name = "qxm_sensorss_q6",
174 .id = SC8280XP_MASTER_SENSORS_PROC,
175 .channels = 1,
176 .buswidth = 8,
177 .num_links = 1,
178 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
179 };
180
181 static struct qcom_icc_node qxm_sp = {
182 .name = "qxm_sp",
183 .id = SC8280XP_MASTER_SP,
184 .channels = 1,
185 .buswidth = 8,
186 .num_links = 1,
187 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
188 };
189
190 static struct qcom_icc_node xm_emac_0 = {
191 .name = "xm_emac_0",
192 .id = SC8280XP_MASTER_EMAC,
193 .channels = 1,
194 .buswidth = 8,
195 .num_links = 1,
196 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
197 };
198
199 static struct qcom_icc_node xm_pcie3_0 = {
200 .name = "xm_pcie3_0",
201 .id = SC8280XP_MASTER_PCIE_0,
202 .channels = 1,
203 .buswidth = 16,
204 .num_links = 1,
205 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
206 };
207
208 static struct qcom_icc_node xm_pcie3_1 = {
209 .name = "xm_pcie3_1",
210 .id = SC8280XP_MASTER_PCIE_1,
211 .channels = 1,
212 .buswidth = 16,
213 .num_links = 1,
214 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
215 };
216
217 static struct qcom_icc_node xm_pcie3_2a = {
218 .name = "xm_pcie3_2a",
219 .id = SC8280XP_MASTER_PCIE_2A,
220 .channels = 1,
221 .buswidth = 16,
222 .num_links = 1,
223 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
224 };
225
226 static struct qcom_icc_node xm_pcie3_2b = {
227 .name = "xm_pcie3_2b",
228 .id = SC8280XP_MASTER_PCIE_2B,
229 .channels = 1,
230 .buswidth = 8,
231 .num_links = 1,
232 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
233 };
234
235 static struct qcom_icc_node xm_pcie3_3a = {
236 .name = "xm_pcie3_3a",
237 .id = SC8280XP_MASTER_PCIE_3A,
238 .channels = 1,
239 .buswidth = 16,
240 .num_links = 1,
241 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
242 };
243
244 static struct qcom_icc_node xm_pcie3_3b = {
245 .name = "xm_pcie3_3b",
246 .id = SC8280XP_MASTER_PCIE_3B,
247 .channels = 1,
248 .buswidth = 8,
249 .num_links = 1,
250 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
251 };
252
253 static struct qcom_icc_node xm_pcie3_4 = {
254 .name = "xm_pcie3_4",
255 .id = SC8280XP_MASTER_PCIE_4,
256 .channels = 1,
257 .buswidth = 8,
258 .num_links = 1,
259 .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
260 };
261
262 static struct qcom_icc_node xm_qdss_etr = {
263 .name = "xm_qdss_etr",
264 .id = SC8280XP_MASTER_QDSS_ETR,
265 .channels = 1,
266 .buswidth = 8,
267 .num_links = 1,
268 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
269 };
270
271 static struct qcom_icc_node xm_sdc2 = {
272 .name = "xm_sdc2",
273 .id = SC8280XP_MASTER_SDCC_2,
274 .channels = 1,
275 .buswidth = 8,
276 .num_links = 1,
277 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
278 };
279
280 static struct qcom_icc_node xm_ufs_card = {
281 .name = "xm_ufs_card",
282 .id = SC8280XP_MASTER_UFS_CARD,
283 .channels = 1,
284 .buswidth = 8,
285 .num_links = 1,
286 .links = { SC8280XP_SLAVE_A2NOC_SNOC },
287 };
288
289 static struct qcom_icc_node qup0_core_master = {
290 .name = "qup0_core_master",
291 .id = SC8280XP_MASTER_QUP_CORE_0,
292 .channels = 1,
293 .buswidth = 4,
294 .num_links = 1,
295 .links = { SC8280XP_SLAVE_QUP_CORE_0 },
296 };
297
298 static struct qcom_icc_node qup1_core_master = {
299 .name = "qup1_core_master",
300 .id = SC8280XP_MASTER_QUP_CORE_1,
301 .channels = 1,
302 .buswidth = 4,
303 .num_links = 1,
304 .links = { SC8280XP_SLAVE_QUP_CORE_1 },
305 };
306
307 static struct qcom_icc_node qup2_core_master = {
308 .name = "qup2_core_master",
309 .id = SC8280XP_MASTER_QUP_CORE_2,
310 .channels = 1,
311 .buswidth = 4,
312 .num_links = 1,
313 .links = { SC8280XP_SLAVE_QUP_CORE_2 },
314 };
315
316 static struct qcom_icc_node qnm_gemnoc_cnoc = {
317 .name = "qnm_gemnoc_cnoc",
318 .id = SC8280XP_MASTER_GEM_NOC_CNOC,
319 .channels = 1,
320 .buswidth = 16,
321 .num_links = 76,
322 .links = { SC8280XP_SLAVE_AHB2PHY_0,
323 SC8280XP_SLAVE_AHB2PHY_1,
324 SC8280XP_SLAVE_AHB2PHY_2,
325 SC8280XP_SLAVE_AOSS,
326 SC8280XP_SLAVE_APPSS,
327 SC8280XP_SLAVE_CAMERA_CFG,
328 SC8280XP_SLAVE_CLK_CTL,
329 SC8280XP_SLAVE_CDSP_CFG,
330 SC8280XP_SLAVE_CDSP1_CFG,
331 SC8280XP_SLAVE_RBCPR_CX_CFG,
332 SC8280XP_SLAVE_RBCPR_MMCX_CFG,
333 SC8280XP_SLAVE_RBCPR_MX_CFG,
334 SC8280XP_SLAVE_CPR_NSPCX,
335 SC8280XP_SLAVE_CRYPTO_0_CFG,
336 SC8280XP_SLAVE_CX_RDPM,
337 SC8280XP_SLAVE_DCC_CFG,
338 SC8280XP_SLAVE_DISPLAY_CFG,
339 SC8280XP_SLAVE_DISPLAY1_CFG,
340 SC8280XP_SLAVE_EMAC_CFG,
341 SC8280XP_SLAVE_EMAC1_CFG,
342 SC8280XP_SLAVE_GFX3D_CFG,
343 SC8280XP_SLAVE_HWKM,
344 SC8280XP_SLAVE_IMEM_CFG,
345 SC8280XP_SLAVE_IPA_CFG,
346 SC8280XP_SLAVE_IPC_ROUTER_CFG,
347 SC8280XP_SLAVE_LPASS,
348 SC8280XP_SLAVE_MX_RDPM,
349 SC8280XP_SLAVE_MXC_RDPM,
350 SC8280XP_SLAVE_PCIE_0_CFG,
351 SC8280XP_SLAVE_PCIE_1_CFG,
352 SC8280XP_SLAVE_PCIE_2A_CFG,
353 SC8280XP_SLAVE_PCIE_2B_CFG,
354 SC8280XP_SLAVE_PCIE_3A_CFG,
355 SC8280XP_SLAVE_PCIE_3B_CFG,
356 SC8280XP_SLAVE_PCIE_4_CFG,
357 SC8280XP_SLAVE_PCIE_RSC_CFG,
358 SC8280XP_SLAVE_PDM,
359 SC8280XP_SLAVE_PIMEM_CFG,
360 SC8280XP_SLAVE_PKA_WRAPPER_CFG,
361 SC8280XP_SLAVE_PMU_WRAPPER_CFG,
362 SC8280XP_SLAVE_QDSS_CFG,
363 SC8280XP_SLAVE_QSPI_0,
364 SC8280XP_SLAVE_QUP_0,
365 SC8280XP_SLAVE_QUP_1,
366 SC8280XP_SLAVE_QUP_2,
367 SC8280XP_SLAVE_SDCC_2,
368 SC8280XP_SLAVE_SDCC_4,
369 SC8280XP_SLAVE_SECURITY,
370 SC8280XP_SLAVE_SMMUV3_CFG,
371 SC8280XP_SLAVE_SMSS_CFG,
372 SC8280XP_SLAVE_SPSS_CFG,
373 SC8280XP_SLAVE_TCSR,
374 SC8280XP_SLAVE_TLMM,
375 SC8280XP_SLAVE_UFS_CARD_CFG,
376 SC8280XP_SLAVE_UFS_MEM_CFG,
377 SC8280XP_SLAVE_USB3_0,
378 SC8280XP_SLAVE_USB3_1,
379 SC8280XP_SLAVE_USB3_MP,
380 SC8280XP_SLAVE_USB4_0,
381 SC8280XP_SLAVE_USB4_1,
382 SC8280XP_SLAVE_VENUS_CFG,
383 SC8280XP_SLAVE_VSENSE_CTRL_CFG,
384 SC8280XP_SLAVE_VSENSE_CTRL_R_CFG,
385 SC8280XP_SLAVE_A1NOC_CFG,
386 SC8280XP_SLAVE_A2NOC_CFG,
387 SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG,
388 SC8280XP_SLAVE_DDRSS_CFG,
389 SC8280XP_SLAVE_CNOC_MNOC_CFG,
390 SC8280XP_SLAVE_SNOC_CFG,
391 SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG,
392 SC8280XP_SLAVE_IMEM,
393 SC8280XP_SLAVE_PIMEM,
394 SC8280XP_SLAVE_SERVICE_CNOC,
395 SC8280XP_SLAVE_QDSS_STM,
396 SC8280XP_SLAVE_SMSS,
397 SC8280XP_SLAVE_TCU
398 },
399 };
400
401 static struct qcom_icc_node qnm_gemnoc_pcie = {
402 .name = "qnm_gemnoc_pcie",
403 .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC,
404 .channels = 1,
405 .buswidth = 16,
406 .num_links = 7,
407 .links = { SC8280XP_SLAVE_PCIE_0,
408 SC8280XP_SLAVE_PCIE_1,
409 SC8280XP_SLAVE_PCIE_2A,
410 SC8280XP_SLAVE_PCIE_2B,
411 SC8280XP_SLAVE_PCIE_3A,
412 SC8280XP_SLAVE_PCIE_3B,
413 SC8280XP_SLAVE_PCIE_4
414 },
415 };
416
417 static struct qcom_icc_node qnm_cnoc_dc_noc = {
418 .name = "qnm_cnoc_dc_noc",
419 .id = SC8280XP_MASTER_CNOC_DC_NOC,
420 .channels = 1,
421 .buswidth = 4,
422 .num_links = 2,
423 .links = { SC8280XP_SLAVE_LLCC_CFG,
424 SC8280XP_SLAVE_GEM_NOC_CFG
425 },
426 };
427
428 static struct qcom_icc_node alm_gpu_tcu = {
429 .name = "alm_gpu_tcu",
430 .id = SC8280XP_MASTER_GPU_TCU,
431 .channels = 1,
432 .buswidth = 8,
433 .num_links = 2,
434 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
435 SC8280XP_SLAVE_LLCC
436 },
437 };
438
439 static struct qcom_icc_node alm_pcie_tcu = {
440 .name = "alm_pcie_tcu",
441 .id = SC8280XP_MASTER_PCIE_TCU,
442 .channels = 1,
443 .buswidth = 8,
444 .num_links = 2,
445 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
446 SC8280XP_SLAVE_LLCC
447 },
448 };
449
450 static struct qcom_icc_node alm_sys_tcu = {
451 .name = "alm_sys_tcu",
452 .id = SC8280XP_MASTER_SYS_TCU,
453 .channels = 1,
454 .buswidth = 8,
455 .num_links = 2,
456 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
457 SC8280XP_SLAVE_LLCC
458 },
459 };
460
461 static struct qcom_icc_node chm_apps = {
462 .name = "chm_apps",
463 .id = SC8280XP_MASTER_APPSS_PROC,
464 .channels = 2,
465 .buswidth = 32,
466 .num_links = 3,
467 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
468 SC8280XP_SLAVE_LLCC,
469 SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC
470 },
471 };
472
473 static struct qcom_icc_node qnm_cmpnoc0 = {
474 .name = "qnm_cmpnoc0",
475 .id = SC8280XP_MASTER_COMPUTE_NOC,
476 .channels = 2,
477 .buswidth = 32,
478 .num_links = 2,
479 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
480 SC8280XP_SLAVE_LLCC
481 },
482 };
483
484 static struct qcom_icc_node qnm_cmpnoc1 = {
485 .name = "qnm_cmpnoc1",
486 .id = SC8280XP_MASTER_COMPUTE_NOC_1,
487 .channels = 2,
488 .buswidth = 32,
489 .num_links = 2,
490 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
491 SC8280XP_SLAVE_LLCC
492 },
493 };
494
495 static struct qcom_icc_node qnm_gemnoc_cfg = {
496 .name = "qnm_gemnoc_cfg",
497 .id = SC8280XP_MASTER_GEM_NOC_CFG,
498 .channels = 1,
499 .buswidth = 4,
500 .num_links = 3,
501 .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1,
502 SC8280XP_SLAVE_SERVICE_GEM_NOC_2,
503 SC8280XP_SLAVE_SERVICE_GEM_NOC
504 },
505 };
506
507 static struct qcom_icc_node qnm_gpu = {
508 .name = "qnm_gpu",
509 .id = SC8280XP_MASTER_GFX3D,
510 .channels = 4,
511 .buswidth = 32,
512 .num_links = 2,
513 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
514 SC8280XP_SLAVE_LLCC
515 },
516 };
517
518 static struct qcom_icc_node qnm_mnoc_hf = {
519 .name = "qnm_mnoc_hf",
520 .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC,
521 .channels = 2,
522 .buswidth = 32,
523 .num_links = 2,
524 .links = { SC8280XP_SLAVE_LLCC,
525 SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC
526 },
527 };
528
529 static struct qcom_icc_node qnm_mnoc_sf = {
530 .name = "qnm_mnoc_sf",
531 .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC,
532 .channels = 2,
533 .buswidth = 32,
534 .num_links = 2,
535 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
536 SC8280XP_SLAVE_LLCC
537 },
538 };
539
540 static struct qcom_icc_node qnm_pcie = {
541 .name = "qnm_pcie",
542 .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC,
543 .channels = 1,
544 .buswidth = 32,
545 .num_links = 2,
546 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
547 SC8280XP_SLAVE_LLCC
548 },
549 };
550
551 static struct qcom_icc_node qnm_snoc_gc = {
552 .name = "qnm_snoc_gc",
553 .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC,
554 .channels = 1,
555 .buswidth = 8,
556 .num_links = 1,
557 .links = { SC8280XP_SLAVE_LLCC },
558 };
559
560 static struct qcom_icc_node qnm_snoc_sf = {
561 .name = "qnm_snoc_sf",
562 .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC,
563 .channels = 1,
564 .buswidth = 16,
565 .num_links = 3,
566 .links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
567 SC8280XP_SLAVE_LLCC,
568 SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC },
569 };
570
571 static struct qcom_icc_node qhm_config_noc = {
572 .name = "qhm_config_noc",
573 .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC,
574 .channels = 1,
575 .buswidth = 4,
576 .num_links = 6,
577 .links = { SC8280XP_SLAVE_LPASS_CORE_CFG,
578 SC8280XP_SLAVE_LPASS_LPI_CFG,
579 SC8280XP_SLAVE_LPASS_MPU_CFG,
580 SC8280XP_SLAVE_LPASS_TOP_CFG,
581 SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
582 SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC
583 },
584 };
585
586 static struct qcom_icc_node qxm_lpass_dsp = {
587 .name = "qxm_lpass_dsp",
588 .id = SC8280XP_MASTER_LPASS_PROC,
589 .channels = 1,
590 .buswidth = 8,
591 .num_links = 4,
592 .links = { SC8280XP_SLAVE_LPASS_TOP_CFG,
593 SC8280XP_SLAVE_LPASS_SNOC,
594 SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
595 SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC
596 },
597 };
598
599 static struct qcom_icc_node llcc_mc = {
600 .name = "llcc_mc",
601 .id = SC8280XP_MASTER_LLCC,
602 .channels = 8,
603 .buswidth = 4,
604 .num_links = 1,
605 .links = { SC8280XP_SLAVE_EBI1 },
606 };
607
608 static struct qcom_icc_node qnm_camnoc_hf = {
609 .name = "qnm_camnoc_hf",
610 .id = SC8280XP_MASTER_CAMNOC_HF,
611 .channels = 2,
612 .buswidth = 32,
613 .num_links = 1,
614 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
615 };
616
617 static struct qcom_icc_node qnm_mdp0_0 = {
618 .name = "qnm_mdp0_0",
619 .id = SC8280XP_MASTER_MDP0,
620 .channels = 1,
621 .buswidth = 32,
622 .num_links = 1,
623 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
624 };
625
626 static struct qcom_icc_node qnm_mdp0_1 = {
627 .name = "qnm_mdp0_1",
628 .id = SC8280XP_MASTER_MDP1,
629 .channels = 1,
630 .buswidth = 32,
631 .num_links = 1,
632 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
633 };
634
635 static struct qcom_icc_node qnm_mdp1_0 = {
636 .name = "qnm_mdp1_0",
637 .id = SC8280XP_MASTER_MDP_CORE1_0,
638 .channels = 1,
639 .buswidth = 32,
640 .num_links = 1,
641 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
642 };
643
644 static struct qcom_icc_node qnm_mdp1_1 = {
645 .name = "qnm_mdp1_1",
646 .id = SC8280XP_MASTER_MDP_CORE1_1,
647 .channels = 1,
648 .buswidth = 32,
649 .num_links = 1,
650 .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
651 };
652
653 static struct qcom_icc_node qnm_mnoc_cfg = {
654 .name = "qnm_mnoc_cfg",
655 .id = SC8280XP_MASTER_CNOC_MNOC_CFG,
656 .channels = 1,
657 .buswidth = 4,
658 .num_links = 1,
659 .links = { SC8280XP_SLAVE_SERVICE_MNOC },
660 };
661
662 static struct qcom_icc_node qnm_rot_0 = {
663 .name = "qnm_rot_0",
664 .id = SC8280XP_MASTER_ROTATOR,
665 .channels = 1,
666 .buswidth = 32,
667 .num_links = 1,
668 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
669 };
670
671 static struct qcom_icc_node qnm_rot_1 = {
672 .name = "qnm_rot_1",
673 .id = SC8280XP_MASTER_ROTATOR_1,
674 .channels = 1,
675 .buswidth = 32,
676 .num_links = 1,
677 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
678 };
679
680 static struct qcom_icc_node qnm_video0 = {
681 .name = "qnm_video0",
682 .id = SC8280XP_MASTER_VIDEO_P0,
683 .channels = 1,
684 .buswidth = 32,
685 .num_links = 1,
686 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
687 };
688
689 static struct qcom_icc_node qnm_video1 = {
690 .name = "qnm_video1",
691 .id = SC8280XP_MASTER_VIDEO_P1,
692 .channels = 1,
693 .buswidth = 32,
694 .num_links = 1,
695 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
696 };
697
698 static struct qcom_icc_node qnm_video_cvp = {
699 .name = "qnm_video_cvp",
700 .id = SC8280XP_MASTER_VIDEO_PROC,
701 .channels = 1,
702 .buswidth = 32,
703 .num_links = 1,
704 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
705 };
706
707 static struct qcom_icc_node qxm_camnoc_icp = {
708 .name = "qxm_camnoc_icp",
709 .id = SC8280XP_MASTER_CAMNOC_ICP,
710 .channels = 1,
711 .buswidth = 8,
712 .num_links = 1,
713 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
714 };
715
716 static struct qcom_icc_node qxm_camnoc_sf = {
717 .name = "qxm_camnoc_sf",
718 .id = SC8280XP_MASTER_CAMNOC_SF,
719 .channels = 1,
720 .buswidth = 32,
721 .num_links = 1,
722 .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
723 };
724
725 static struct qcom_icc_node qhm_nsp_noc_config = {
726 .name = "qhm_nsp_noc_config",
727 .id = SC8280XP_MASTER_CDSP_NOC_CFG,
728 .channels = 1,
729 .buswidth = 4,
730 .num_links = 1,
731 .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC },
732 };
733
734 static struct qcom_icc_node qxm_nsp = {
735 .name = "qxm_nsp",
736 .id = SC8280XP_MASTER_CDSP_PROC,
737 .channels = 2,
738 .buswidth = 32,
739 .num_links = 2,
740 .links = { SC8280XP_SLAVE_CDSP_MEM_NOC,
741 SC8280XP_SLAVE_NSP_XFR
742 },
743 };
744
745 static struct qcom_icc_node qhm_nspb_noc_config = {
746 .name = "qhm_nspb_noc_config",
747 .id = SC8280XP_MASTER_CDSPB_NOC_CFG,
748 .channels = 1,
749 .buswidth = 4,
750 .num_links = 1,
751 .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC },
752 };
753
754 static struct qcom_icc_node qxm_nspb = {
755 .name = "qxm_nspb",
756 .id = SC8280XP_MASTER_CDSP_PROC_B,
757 .channels = 2,
758 .buswidth = 32,
759 .num_links = 2,
760 .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC,
761 SC8280XP_SLAVE_NSPB_XFR
762 },
763 };
764
765 static struct qcom_icc_node qnm_aggre1_noc = {
766 .name = "qnm_aggre1_noc",
767 .id = SC8280XP_MASTER_A1NOC_SNOC,
768 .channels = 1,
769 .buswidth = 16,
770 .num_links = 1,
771 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
772 };
773
774 static struct qcom_icc_node qnm_aggre2_noc = {
775 .name = "qnm_aggre2_noc",
776 .id = SC8280XP_MASTER_A2NOC_SNOC,
777 .channels = 1,
778 .buswidth = 16,
779 .num_links = 1,
780 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
781 };
782
783 static struct qcom_icc_node qnm_aggre_usb_noc = {
784 .name = "qnm_aggre_usb_noc",
785 .id = SC8280XP_MASTER_USB_NOC_SNOC,
786 .channels = 1,
787 .buswidth = 16,
788 .num_links = 1,
789 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
790 };
791
792 static struct qcom_icc_node qnm_lpass_noc = {
793 .name = "qnm_lpass_noc",
794 .id = SC8280XP_MASTER_LPASS_ANOC,
795 .channels = 1,
796 .buswidth = 16,
797 .num_links = 1,
798 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
799 };
800
801 static struct qcom_icc_node qnm_snoc_cfg = {
802 .name = "qnm_snoc_cfg",
803 .id = SC8280XP_MASTER_SNOC_CFG,
804 .channels = 1,
805 .buswidth = 4,
806 .num_links = 1,
807 .links = { SC8280XP_SLAVE_SERVICE_SNOC },
808 };
809
810 static struct qcom_icc_node qxm_pimem = {
811 .name = "qxm_pimem",
812 .id = SC8280XP_MASTER_PIMEM,
813 .channels = 1,
814 .buswidth = 8,
815 .num_links = 1,
816 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC },
817 };
818
819 static struct qcom_icc_node xm_gic = {
820 .name = "xm_gic",
821 .id = SC8280XP_MASTER_GIC,
822 .channels = 1,
823 .buswidth = 8,
824 .num_links = 1,
825 .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC },
826 };
827
828 static struct qcom_icc_node qns_a1noc_snoc = {
829 .name = "qns_a1noc_snoc",
830 .id = SC8280XP_SLAVE_A1NOC_SNOC,
831 .channels = 1,
832 .buswidth = 16,
833 .num_links = 1,
834 .links = { SC8280XP_MASTER_A1NOC_SNOC },
835 };
836
837 static struct qcom_icc_node qns_aggre_usb_snoc = {
838 .name = "qns_aggre_usb_snoc",
839 .id = SC8280XP_SLAVE_USB_NOC_SNOC,
840 .channels = 1,
841 .buswidth = 16,
842 .num_links = 1,
843 .links = { SC8280XP_MASTER_USB_NOC_SNOC },
844 };
845
846 static struct qcom_icc_node srvc_aggre1_noc = {
847 .name = "srvc_aggre1_noc",
848 .id = SC8280XP_SLAVE_SERVICE_A1NOC,
849 .channels = 1,
850 .buswidth = 4,
851 };
852
853 static struct qcom_icc_node qns_a2noc_snoc = {
854 .name = "qns_a2noc_snoc",
855 .id = SC8280XP_SLAVE_A2NOC_SNOC,
856 .channels = 1,
857 .buswidth = 16,
858 .num_links = 1,
859 .links = { SC8280XP_MASTER_A2NOC_SNOC },
860 };
861
862 static struct qcom_icc_node qns_pcie_gem_noc = {
863 .name = "qns_pcie_gem_noc",
864 .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC,
865 .channels = 1,
866 .buswidth = 32,
867 .num_links = 1,
868 .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC },
869 };
870
871 static struct qcom_icc_node srvc_aggre2_noc = {
872 .name = "srvc_aggre2_noc",
873 .id = SC8280XP_SLAVE_SERVICE_A2NOC,
874 .channels = 1,
875 .buswidth = 4,
876 };
877
878 static struct qcom_icc_node qup0_core_slave = {
879 .name = "qup0_core_slave",
880 .id = SC8280XP_SLAVE_QUP_CORE_0,
881 .channels = 1,
882 .buswidth = 4,
883 };
884
885 static struct qcom_icc_node qup1_core_slave = {
886 .name = "qup1_core_slave",
887 .id = SC8280XP_SLAVE_QUP_CORE_1,
888 .channels = 1,
889 .buswidth = 4,
890 };
891
892 static struct qcom_icc_node qup2_core_slave = {
893 .name = "qup2_core_slave",
894 .id = SC8280XP_SLAVE_QUP_CORE_2,
895 .channels = 1,
896 .buswidth = 4,
897 };
898
899 static struct qcom_icc_node qhs_ahb2phy0 = {
900 .name = "qhs_ahb2phy0",
901 .id = SC8280XP_SLAVE_AHB2PHY_0,
902 .channels = 1,
903 .buswidth = 4,
904 };
905
906 static struct qcom_icc_node qhs_ahb2phy1 = {
907 .name = "qhs_ahb2phy1",
908 .id = SC8280XP_SLAVE_AHB2PHY_1,
909 .channels = 1,
910 .buswidth = 4,
911 };
912
913 static struct qcom_icc_node qhs_ahb2phy2 = {
914 .name = "qhs_ahb2phy2",
915 .id = SC8280XP_SLAVE_AHB2PHY_2,
916 .channels = 1,
917 .buswidth = 4,
918 };
919
920 static struct qcom_icc_node qhs_aoss = {
921 .name = "qhs_aoss",
922 .id = SC8280XP_SLAVE_AOSS,
923 .channels = 1,
924 .buswidth = 4,
925 };
926
927 static struct qcom_icc_node qhs_apss = {
928 .name = "qhs_apss",
929 .id = SC8280XP_SLAVE_APPSS,
930 .channels = 1,
931 .buswidth = 8,
932 };
933
934 static struct qcom_icc_node qhs_camera_cfg = {
935 .name = "qhs_camera_cfg",
936 .id = SC8280XP_SLAVE_CAMERA_CFG,
937 .channels = 1,
938 .buswidth = 4,
939 };
940
941 static struct qcom_icc_node qhs_clk_ctl = {
942 .name = "qhs_clk_ctl",
943 .id = SC8280XP_SLAVE_CLK_CTL,
944 .channels = 1,
945 .buswidth = 4,
946 };
947
948 static struct qcom_icc_node qhs_compute0_cfg = {
949 .name = "qhs_compute0_cfg",
950 .id = SC8280XP_SLAVE_CDSP_CFG,
951 .channels = 1,
952 .buswidth = 4,
953 .num_links = 1,
954 .links = { SC8280XP_MASTER_CDSP_NOC_CFG },
955 };
956
957 static struct qcom_icc_node qhs_compute1_cfg = {
958 .name = "qhs_compute1_cfg",
959 .id = SC8280XP_SLAVE_CDSP1_CFG,
960 .channels = 1,
961 .buswidth = 4,
962 .num_links = 1,
963 .links = { SC8280XP_MASTER_CDSPB_NOC_CFG },
964 };
965
966 static struct qcom_icc_node qhs_cpr_cx = {
967 .name = "qhs_cpr_cx",
968 .id = SC8280XP_SLAVE_RBCPR_CX_CFG,
969 .channels = 1,
970 .buswidth = 4,
971 };
972
973 static struct qcom_icc_node qhs_cpr_mmcx = {
974 .name = "qhs_cpr_mmcx",
975 .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG,
976 .channels = 1,
977 .buswidth = 4,
978 };
979
980 static struct qcom_icc_node qhs_cpr_mx = {
981 .name = "qhs_cpr_mx",
982 .id = SC8280XP_SLAVE_RBCPR_MX_CFG,
983 .channels = 1,
984 .buswidth = 4,
985 };
986
987 static struct qcom_icc_node qhs_cpr_nspcx = {
988 .name = "qhs_cpr_nspcx",
989 .id = SC8280XP_SLAVE_CPR_NSPCX,
990 .channels = 1,
991 .buswidth = 4,
992 };
993
994 static struct qcom_icc_node qhs_crypto0_cfg = {
995 .name = "qhs_crypto0_cfg",
996 .id = SC8280XP_SLAVE_CRYPTO_0_CFG,
997 .channels = 1,
998 .buswidth = 4,
999 };
1000
1001 static struct qcom_icc_node qhs_cx_rdpm = {
1002 .name = "qhs_cx_rdpm",
1003 .id = SC8280XP_SLAVE_CX_RDPM,
1004 .channels = 1,
1005 .buswidth = 4,
1006 };
1007
1008 static struct qcom_icc_node qhs_dcc_cfg = {
1009 .name = "qhs_dcc_cfg",
1010 .id = SC8280XP_SLAVE_DCC_CFG,
1011 .channels = 1,
1012 .buswidth = 4,
1013 };
1014
1015 static struct qcom_icc_node qhs_display0_cfg = {
1016 .name = "qhs_display0_cfg",
1017 .id = SC8280XP_SLAVE_DISPLAY_CFG,
1018 .channels = 1,
1019 .buswidth = 4,
1020 };
1021
1022 static struct qcom_icc_node qhs_display1_cfg = {
1023 .name = "qhs_display1_cfg",
1024 .id = SC8280XP_SLAVE_DISPLAY1_CFG,
1025 .channels = 1,
1026 .buswidth = 4,
1027 };
1028
1029 static struct qcom_icc_node qhs_emac0_cfg = {
1030 .name = "qhs_emac0_cfg",
1031 .id = SC8280XP_SLAVE_EMAC_CFG,
1032 .channels = 1,
1033 .buswidth = 4,
1034 };
1035
1036 static struct qcom_icc_node qhs_emac1_cfg = {
1037 .name = "qhs_emac1_cfg",
1038 .id = SC8280XP_SLAVE_EMAC1_CFG,
1039 .channels = 1,
1040 .buswidth = 4,
1041 };
1042
1043 static struct qcom_icc_node qhs_gpuss_cfg = {
1044 .name = "qhs_gpuss_cfg",
1045 .id = SC8280XP_SLAVE_GFX3D_CFG,
1046 .channels = 1,
1047 .buswidth = 8,
1048 };
1049
1050 static struct qcom_icc_node qhs_hwkm = {
1051 .name = "qhs_hwkm",
1052 .id = SC8280XP_SLAVE_HWKM,
1053 .channels = 1,
1054 .buswidth = 4,
1055 };
1056
1057 static struct qcom_icc_node qhs_imem_cfg = {
1058 .name = "qhs_imem_cfg",
1059 .id = SC8280XP_SLAVE_IMEM_CFG,
1060 .channels = 1,
1061 .buswidth = 4,
1062 };
1063
1064 static struct qcom_icc_node qhs_ipa = {
1065 .name = "qhs_ipa",
1066 .id = SC8280XP_SLAVE_IPA_CFG,
1067 .channels = 1,
1068 .buswidth = 4,
1069 };
1070
1071 static struct qcom_icc_node qhs_ipc_router = {
1072 .name = "qhs_ipc_router",
1073 .id = SC8280XP_SLAVE_IPC_ROUTER_CFG,
1074 .channels = 1,
1075 .buswidth = 4,
1076 };
1077
1078 static struct qcom_icc_node qhs_lpass_cfg = {
1079 .name = "qhs_lpass_cfg",
1080 .id = SC8280XP_SLAVE_LPASS,
1081 .channels = 1,
1082 .buswidth = 4,
1083 .num_links = 1,
1084 .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC },
1085 };
1086
1087 static struct qcom_icc_node qhs_mx_rdpm = {
1088 .name = "qhs_mx_rdpm",
1089 .id = SC8280XP_SLAVE_MX_RDPM,
1090 .channels = 1,
1091 .buswidth = 4,
1092 };
1093
1094 static struct qcom_icc_node qhs_mxc_rdpm = {
1095 .name = "qhs_mxc_rdpm",
1096 .id = SC8280XP_SLAVE_MXC_RDPM,
1097 .channels = 1,
1098 .buswidth = 4,
1099 };
1100
1101 static struct qcom_icc_node qhs_pcie0_cfg = {
1102 .name = "qhs_pcie0_cfg",
1103 .id = SC8280XP_SLAVE_PCIE_0_CFG,
1104 .channels = 1,
1105 .buswidth = 4,
1106 };
1107
1108 static struct qcom_icc_node qhs_pcie1_cfg = {
1109 .name = "qhs_pcie1_cfg",
1110 .id = SC8280XP_SLAVE_PCIE_1_CFG,
1111 .channels = 1,
1112 .buswidth = 4,
1113 };
1114
1115 static struct qcom_icc_node qhs_pcie2a_cfg = {
1116 .name = "qhs_pcie2a_cfg",
1117 .id = SC8280XP_SLAVE_PCIE_2A_CFG,
1118 .channels = 1,
1119 .buswidth = 4,
1120 };
1121
1122 static struct qcom_icc_node qhs_pcie2b_cfg = {
1123 .name = "qhs_pcie2b_cfg",
1124 .id = SC8280XP_SLAVE_PCIE_2B_CFG,
1125 .channels = 1,
1126 .buswidth = 4,
1127 };
1128
1129 static struct qcom_icc_node qhs_pcie3a_cfg = {
1130 .name = "qhs_pcie3a_cfg",
1131 .id = SC8280XP_SLAVE_PCIE_3A_CFG,
1132 .channels = 1,
1133 .buswidth = 4,
1134 };
1135
1136 static struct qcom_icc_node qhs_pcie3b_cfg = {
1137 .name = "qhs_pcie3b_cfg",
1138 .id = SC8280XP_SLAVE_PCIE_3B_CFG,
1139 .channels = 1,
1140 .buswidth = 4,
1141 };
1142
1143 static struct qcom_icc_node qhs_pcie4_cfg = {
1144 .name = "qhs_pcie4_cfg",
1145 .id = SC8280XP_SLAVE_PCIE_4_CFG,
1146 .channels = 1,
1147 .buswidth = 4,
1148 };
1149
1150 static struct qcom_icc_node qhs_pcie_rsc_cfg = {
1151 .name = "qhs_pcie_rsc_cfg",
1152 .id = SC8280XP_SLAVE_PCIE_RSC_CFG,
1153 .channels = 1,
1154 .buswidth = 4,
1155 };
1156
1157 static struct qcom_icc_node qhs_pdm = {
1158 .name = "qhs_pdm",
1159 .id = SC8280XP_SLAVE_PDM,
1160 .channels = 1,
1161 .buswidth = 4,
1162 };
1163
1164 static struct qcom_icc_node qhs_pimem_cfg = {
1165 .name = "qhs_pimem_cfg",
1166 .id = SC8280XP_SLAVE_PIMEM_CFG,
1167 .channels = 1,
1168 .buswidth = 4,
1169 };
1170
1171 static struct qcom_icc_node qhs_pka_wrapper_cfg = {
1172 .name = "qhs_pka_wrapper_cfg",
1173 .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG,
1174 .channels = 1,
1175 .buswidth = 4,
1176 };
1177
1178 static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
1179 .name = "qhs_pmu_wrapper_cfg",
1180 .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG,
1181 .channels = 1,
1182 .buswidth = 4,
1183 };
1184
1185 static struct qcom_icc_node qhs_qdss_cfg = {
1186 .name = "qhs_qdss_cfg",
1187 .id = SC8280XP_SLAVE_QDSS_CFG,
1188 .channels = 1,
1189 .buswidth = 4,
1190 };
1191
1192 static struct qcom_icc_node qhs_qspi = {
1193 .name = "qhs_qspi",
1194 .id = SC8280XP_SLAVE_QSPI_0,
1195 .channels = 1,
1196 .buswidth = 4,
1197 };
1198
1199 static struct qcom_icc_node qhs_qup0 = {
1200 .name = "qhs_qup0",
1201 .id = SC8280XP_SLAVE_QUP_0,
1202 .channels = 1,
1203 .buswidth = 4,
1204 };
1205
1206 static struct qcom_icc_node qhs_qup1 = {
1207 .name = "qhs_qup1",
1208 .id = SC8280XP_SLAVE_QUP_1,
1209 .channels = 1,
1210 .buswidth = 4,
1211 };
1212
1213 static struct qcom_icc_node qhs_qup2 = {
1214 .name = "qhs_qup2",
1215 .id = SC8280XP_SLAVE_QUP_2,
1216 .channels = 1,
1217 .buswidth = 4,
1218 };
1219
1220 static struct qcom_icc_node qhs_sdc2 = {
1221 .name = "qhs_sdc2",
1222 .id = SC8280XP_SLAVE_SDCC_2,
1223 .channels = 1,
1224 .buswidth = 4,
1225 };
1226
1227 static struct qcom_icc_node qhs_sdc4 = {
1228 .name = "qhs_sdc4",
1229 .id = SC8280XP_SLAVE_SDCC_4,
1230 .channels = 1,
1231 .buswidth = 4,
1232 };
1233
1234 static struct qcom_icc_node qhs_security = {
1235 .name = "qhs_security",
1236 .id = SC8280XP_SLAVE_SECURITY,
1237 .channels = 1,
1238 .buswidth = 4,
1239 };
1240
1241 static struct qcom_icc_node qhs_smmuv3_cfg = {
1242 .name = "qhs_smmuv3_cfg",
1243 .id = SC8280XP_SLAVE_SMMUV3_CFG,
1244 .channels = 1,
1245 .buswidth = 8,
1246 };
1247
1248 static struct qcom_icc_node qhs_smss_cfg = {
1249 .name = "qhs_smss_cfg",
1250 .id = SC8280XP_SLAVE_SMSS_CFG,
1251 .channels = 1,
1252 .buswidth = 4,
1253 };
1254
1255 static struct qcom_icc_node qhs_spss_cfg = {
1256 .name = "qhs_spss_cfg",
1257 .id = SC8280XP_SLAVE_SPSS_CFG,
1258 .channels = 1,
1259 .buswidth = 4,
1260 };
1261
1262 static struct qcom_icc_node qhs_tcsr = {
1263 .name = "qhs_tcsr",
1264 .id = SC8280XP_SLAVE_TCSR,
1265 .channels = 1,
1266 .buswidth = 4,
1267 };
1268
1269 static struct qcom_icc_node qhs_tlmm = {
1270 .name = "qhs_tlmm",
1271 .id = SC8280XP_SLAVE_TLMM,
1272 .channels = 1,
1273 .buswidth = 4,
1274 };
1275
1276 static struct qcom_icc_node qhs_ufs_card_cfg = {
1277 .name = "qhs_ufs_card_cfg",
1278 .id = SC8280XP_SLAVE_UFS_CARD_CFG,
1279 .channels = 1,
1280 .buswidth = 4,
1281 };
1282
1283 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1284 .name = "qhs_ufs_mem_cfg",
1285 .id = SC8280XP_SLAVE_UFS_MEM_CFG,
1286 .channels = 1,
1287 .buswidth = 4,
1288 };
1289
1290 static struct qcom_icc_node qhs_usb3_0 = {
1291 .name = "qhs_usb3_0",
1292 .id = SC8280XP_SLAVE_USB3_0,
1293 .channels = 1,
1294 .buswidth = 4,
1295 };
1296
1297 static struct qcom_icc_node qhs_usb3_1 = {
1298 .name = "qhs_usb3_1",
1299 .id = SC8280XP_SLAVE_USB3_1,
1300 .channels = 1,
1301 .buswidth = 4,
1302 };
1303
1304 static struct qcom_icc_node qhs_usb3_mp = {
1305 .name = "qhs_usb3_mp",
1306 .id = SC8280XP_SLAVE_USB3_MP,
1307 .channels = 1,
1308 .buswidth = 4,
1309 };
1310
1311 static struct qcom_icc_node qhs_usb4_host_0 = {
1312 .name = "qhs_usb4_host_0",
1313 .id = SC8280XP_SLAVE_USB4_0,
1314 .channels = 1,
1315 .buswidth = 4,
1316 };
1317
1318 static struct qcom_icc_node qhs_usb4_host_1 = {
1319 .name = "qhs_usb4_host_1",
1320 .id = SC8280XP_SLAVE_USB4_1,
1321 .channels = 1,
1322 .buswidth = 4,
1323 };
1324
1325 static struct qcom_icc_node qhs_venus_cfg = {
1326 .name = "qhs_venus_cfg",
1327 .id = SC8280XP_SLAVE_VENUS_CFG,
1328 .channels = 1,
1329 .buswidth = 4,
1330 };
1331
1332 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1333 .name = "qhs_vsense_ctrl_cfg",
1334 .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG,
1335 .channels = 1,
1336 .buswidth = 4,
1337 };
1338
1339 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = {
1340 .name = "qhs_vsense_ctrl_r_cfg",
1341 .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG,
1342 .channels = 1,
1343 .buswidth = 4,
1344 };
1345
1346 static struct qcom_icc_node qns_a1_noc_cfg = {
1347 .name = "qns_a1_noc_cfg",
1348 .id = SC8280XP_SLAVE_A1NOC_CFG,
1349 .channels = 1,
1350 .buswidth = 4,
1351 .num_links = 1,
1352 .links = { SC8280XP_MASTER_A1NOC_CFG },
1353 };
1354
1355 static struct qcom_icc_node qns_a2_noc_cfg = {
1356 .name = "qns_a2_noc_cfg",
1357 .id = SC8280XP_SLAVE_A2NOC_CFG,
1358 .channels = 1,
1359 .buswidth = 4,
1360 .num_links = 1,
1361 .links = { SC8280XP_MASTER_A2NOC_CFG },
1362 };
1363
1364 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = {
1365 .name = "qns_anoc_pcie_bridge_cfg",
1366 .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG,
1367 .channels = 1,
1368 .buswidth = 4,
1369 };
1370
1371 static struct qcom_icc_node qns_ddrss_cfg = {
1372 .name = "qns_ddrss_cfg",
1373 .id = SC8280XP_SLAVE_DDRSS_CFG,
1374 .channels = 1,
1375 .buswidth = 4,
1376 .num_links = 1,
1377 .links = { SC8280XP_MASTER_CNOC_DC_NOC },
1378 };
1379
1380 static struct qcom_icc_node qns_mnoc_cfg = {
1381 .name = "qns_mnoc_cfg",
1382 .id = SC8280XP_SLAVE_CNOC_MNOC_CFG,
1383 .channels = 1,
1384 .buswidth = 4,
1385 .num_links = 1,
1386 .links = { SC8280XP_MASTER_CNOC_MNOC_CFG },
1387 };
1388
1389 static struct qcom_icc_node qns_snoc_cfg = {
1390 .name = "qns_snoc_cfg",
1391 .id = SC8280XP_SLAVE_SNOC_CFG,
1392 .channels = 1,
1393 .buswidth = 4,
1394 .num_links = 1,
1395 .links = { SC8280XP_MASTER_SNOC_CFG },
1396 };
1397
1398 static struct qcom_icc_node qns_snoc_sf_bridge_cfg = {
1399 .name = "qns_snoc_sf_bridge_cfg",
1400 .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG,
1401 .channels = 1,
1402 .buswidth = 4,
1403 };
1404
1405 static struct qcom_icc_node qxs_imem = {
1406 .name = "qxs_imem",
1407 .id = SC8280XP_SLAVE_IMEM,
1408 .channels = 1,
1409 .buswidth = 8,
1410 };
1411
1412 static struct qcom_icc_node qxs_pimem = {
1413 .name = "qxs_pimem",
1414 .id = SC8280XP_SLAVE_PIMEM,
1415 .channels = 1,
1416 .buswidth = 8,
1417 };
1418
1419 static struct qcom_icc_node srvc_cnoc = {
1420 .name = "srvc_cnoc",
1421 .id = SC8280XP_SLAVE_SERVICE_CNOC,
1422 .channels = 1,
1423 .buswidth = 4,
1424 };
1425
1426 static struct qcom_icc_node xs_pcie_0 = {
1427 .name = "xs_pcie_0",
1428 .id = SC8280XP_SLAVE_PCIE_0,
1429 .channels = 1,
1430 .buswidth = 16,
1431 };
1432
1433 static struct qcom_icc_node xs_pcie_1 = {
1434 .name = "xs_pcie_1",
1435 .id = SC8280XP_SLAVE_PCIE_1,
1436 .channels = 1,
1437 .buswidth = 16,
1438 };
1439
1440 static struct qcom_icc_node xs_pcie_2a = {
1441 .name = "xs_pcie_2a",
1442 .id = SC8280XP_SLAVE_PCIE_2A,
1443 .channels = 1,
1444 .buswidth = 16,
1445 };
1446
1447 static struct qcom_icc_node xs_pcie_2b = {
1448 .name = "xs_pcie_2b",
1449 .id = SC8280XP_SLAVE_PCIE_2B,
1450 .channels = 1,
1451 .buswidth = 8,
1452 };
1453
1454 static struct qcom_icc_node xs_pcie_3a = {
1455 .name = "xs_pcie_3a",
1456 .id = SC8280XP_SLAVE_PCIE_3A,
1457 .channels = 1,
1458 .buswidth = 16,
1459 };
1460
1461 static struct qcom_icc_node xs_pcie_3b = {
1462 .name = "xs_pcie_3b",
1463 .id = SC8280XP_SLAVE_PCIE_3B,
1464 .channels = 1,
1465 .buswidth = 8,
1466 };
1467
1468 static struct qcom_icc_node xs_pcie_4 = {
1469 .name = "xs_pcie_4",
1470 .id = SC8280XP_SLAVE_PCIE_4,
1471 .channels = 1,
1472 .buswidth = 8,
1473 };
1474
1475 static struct qcom_icc_node xs_qdss_stm = {
1476 .name = "xs_qdss_stm",
1477 .id = SC8280XP_SLAVE_QDSS_STM,
1478 .channels = 1,
1479 .buswidth = 4,
1480 };
1481
1482 static struct qcom_icc_node xs_smss = {
1483 .name = "xs_smss",
1484 .id = SC8280XP_SLAVE_SMSS,
1485 .channels = 1,
1486 .buswidth = 8,
1487 };
1488
1489 static struct qcom_icc_node xs_sys_tcu_cfg = {
1490 .name = "xs_sys_tcu_cfg",
1491 .id = SC8280XP_SLAVE_TCU,
1492 .channels = 1,
1493 .buswidth = 8,
1494 };
1495
1496 static struct qcom_icc_node qhs_llcc = {
1497 .name = "qhs_llcc",
1498 .id = SC8280XP_SLAVE_LLCC_CFG,
1499 .channels = 1,
1500 .buswidth = 4,
1501 };
1502
1503 static struct qcom_icc_node qns_gemnoc = {
1504 .name = "qns_gemnoc",
1505 .id = SC8280XP_SLAVE_GEM_NOC_CFG,
1506 .channels = 1,
1507 .buswidth = 4,
1508 .num_links = 1,
1509 .links = { SC8280XP_MASTER_GEM_NOC_CFG },
1510 };
1511
1512 static struct qcom_icc_node qns_gem_noc_cnoc = {
1513 .name = "qns_gem_noc_cnoc",
1514 .id = SC8280XP_SLAVE_GEM_NOC_CNOC,
1515 .channels = 1,
1516 .buswidth = 16,
1517 .num_links = 1,
1518 .links = { SC8280XP_MASTER_GEM_NOC_CNOC },
1519 };
1520
1521 static struct qcom_icc_node qns_llcc = {
1522 .name = "qns_llcc",
1523 .id = SC8280XP_SLAVE_LLCC,
1524 .channels = 8,
1525 .buswidth = 16,
1526 .num_links = 1,
1527 .links = { SC8280XP_MASTER_LLCC },
1528 };
1529
1530 static struct qcom_icc_node qns_pcie = {
1531 .name = "qns_pcie",
1532 .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC,
1533 .channels = 1,
1534 .buswidth = 16,
1535 .num_links = 1,
1536 .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC },
1537 };
1538
1539 static struct qcom_icc_node srvc_even_gemnoc = {
1540 .name = "srvc_even_gemnoc",
1541 .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1,
1542 .channels = 1,
1543 .buswidth = 4,
1544 };
1545
1546 static struct qcom_icc_node srvc_odd_gemnoc = {
1547 .name = "srvc_odd_gemnoc",
1548 .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2,
1549 .channels = 1,
1550 .buswidth = 4,
1551 };
1552
1553 static struct qcom_icc_node srvc_sys_gemnoc = {
1554 .name = "srvc_sys_gemnoc",
1555 .id = SC8280XP_SLAVE_SERVICE_GEM_NOC,
1556 .channels = 1,
1557 .buswidth = 4,
1558 };
1559
1560 static struct qcom_icc_node qhs_lpass_core = {
1561 .name = "qhs_lpass_core",
1562 .id = SC8280XP_SLAVE_LPASS_CORE_CFG,
1563 .channels = 1,
1564 .buswidth = 4,
1565 };
1566
1567 static struct qcom_icc_node qhs_lpass_lpi = {
1568 .name = "qhs_lpass_lpi",
1569 .id = SC8280XP_SLAVE_LPASS_LPI_CFG,
1570 .channels = 1,
1571 .buswidth = 4,
1572 };
1573
1574 static struct qcom_icc_node qhs_lpass_mpu = {
1575 .name = "qhs_lpass_mpu",
1576 .id = SC8280XP_SLAVE_LPASS_MPU_CFG,
1577 .channels = 1,
1578 .buswidth = 4,
1579 };
1580
1581 static struct qcom_icc_node qhs_lpass_top = {
1582 .name = "qhs_lpass_top",
1583 .id = SC8280XP_SLAVE_LPASS_TOP_CFG,
1584 .channels = 1,
1585 .buswidth = 4,
1586 };
1587
1588 static struct qcom_icc_node qns_sysnoc = {
1589 .name = "qns_sysnoc",
1590 .id = SC8280XP_SLAVE_LPASS_SNOC,
1591 .channels = 1,
1592 .buswidth = 16,
1593 .num_links = 1,
1594 .links = { SC8280XP_MASTER_LPASS_ANOC },
1595 };
1596
1597 static struct qcom_icc_node srvc_niu_aml_noc = {
1598 .name = "srvc_niu_aml_noc",
1599 .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
1600 .channels = 1,
1601 .buswidth = 4,
1602 };
1603
1604 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1605 .name = "srvc_niu_lpass_agnoc",
1606 .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC,
1607 .channels = 1,
1608 .buswidth = 4,
1609 };
1610
1611 static struct qcom_icc_node ebi = {
1612 .name = "ebi",
1613 .id = SC8280XP_SLAVE_EBI1,
1614 .channels = 8,
1615 .buswidth = 4,
1616 };
1617
1618 static struct qcom_icc_node qns_mem_noc_hf = {
1619 .name = "qns_mem_noc_hf",
1620 .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC,
1621 .channels = 2,
1622 .buswidth = 32,
1623 .num_links = 1,
1624 .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC },
1625 };
1626
1627 static struct qcom_icc_node qns_mem_noc_sf = {
1628 .name = "qns_mem_noc_sf",
1629 .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC,
1630 .channels = 2,
1631 .buswidth = 32,
1632 .num_links = 1,
1633 .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC },
1634 };
1635
1636 static struct qcom_icc_node srvc_mnoc = {
1637 .name = "srvc_mnoc",
1638 .id = SC8280XP_SLAVE_SERVICE_MNOC,
1639 .channels = 1,
1640 .buswidth = 4,
1641 };
1642
1643 static struct qcom_icc_node qns_nsp_gemnoc = {
1644 .name = "qns_nsp_gemnoc",
1645 .id = SC8280XP_SLAVE_CDSP_MEM_NOC,
1646 .channels = 2,
1647 .buswidth = 32,
1648 .num_links = 1,
1649 .links = { SC8280XP_MASTER_COMPUTE_NOC },
1650 };
1651
1652 static struct qcom_icc_node qxs_nsp_xfr = {
1653 .name = "qxs_nsp_xfr",
1654 .id = SC8280XP_SLAVE_NSP_XFR,
1655 .channels = 1,
1656 .buswidth = 32,
1657 };
1658
1659 static struct qcom_icc_node service_nsp_noc = {
1660 .name = "service_nsp_noc",
1661 .id = SC8280XP_SLAVE_SERVICE_NSP_NOC,
1662 .channels = 1,
1663 .buswidth = 4,
1664 };
1665
1666 static struct qcom_icc_node qns_nspb_gemnoc = {
1667 .name = "qns_nspb_gemnoc",
1668 .id = SC8280XP_SLAVE_CDSPB_MEM_NOC,
1669 .channels = 2,
1670 .buswidth = 32,
1671 .num_links = 1,
1672 .links = { SC8280XP_MASTER_COMPUTE_NOC_1 },
1673 };
1674
1675 static struct qcom_icc_node qxs_nspb_xfr = {
1676 .name = "qxs_nspb_xfr",
1677 .id = SC8280XP_SLAVE_NSPB_XFR,
1678 .channels = 1,
1679 .buswidth = 32,
1680 };
1681
1682 static struct qcom_icc_node service_nspb_noc = {
1683 .name = "service_nspb_noc",
1684 .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC,
1685 .channels = 1,
1686 .buswidth = 4,
1687 };
1688
1689 static struct qcom_icc_node qns_gemnoc_gc = {
1690 .name = "qns_gemnoc_gc",
1691 .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC,
1692 .channels = 1,
1693 .buswidth = 8,
1694 .num_links = 1,
1695 .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC },
1696 };
1697
1698 static struct qcom_icc_node qns_gemnoc_sf = {
1699 .name = "qns_gemnoc_sf",
1700 .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF,
1701 .channels = 1,
1702 .buswidth = 16,
1703 .num_links = 1,
1704 .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC },
1705 };
1706
1707 static struct qcom_icc_node srvc_snoc = {
1708 .name = "srvc_snoc",
1709 .id = SC8280XP_SLAVE_SERVICE_SNOC,
1710 .channels = 1,
1711 .buswidth = 4,
1712 };
1713
1714 static struct qcom_icc_bcm bcm_acv = {
1715 .name = "ACV",
1716 .enable_mask = BIT(3),
1717 .num_nodes = 1,
1718 .nodes = { &ebi },
1719 };
1720
1721 static struct qcom_icc_bcm bcm_ce0 = {
1722 .name = "CE0",
1723 .num_nodes = 1,
1724 .nodes = { &qxm_crypto },
1725 };
1726
1727 static struct qcom_icc_bcm bcm_cn0 = {
1728 .name = "CN0",
1729 .keepalive = true,
1730 .num_nodes = 9,
1731 .nodes = { &qnm_gemnoc_cnoc,
1732 &qnm_gemnoc_pcie,
1733 &xs_pcie_0,
1734 &xs_pcie_1,
1735 &xs_pcie_2a,
1736 &xs_pcie_2b,
1737 &xs_pcie_3a,
1738 &xs_pcie_3b,
1739 &xs_pcie_4
1740 },
1741 };
1742
1743 static struct qcom_icc_bcm bcm_cn1 = {
1744 .name = "CN1",
1745 .num_nodes = 67,
1746 .nodes = { &qhs_ahb2phy0,
1747 &qhs_ahb2phy1,
1748 &qhs_ahb2phy2,
1749 &qhs_aoss,
1750 &qhs_apss,
1751 &qhs_camera_cfg,
1752 &qhs_clk_ctl,
1753 &qhs_compute0_cfg,
1754 &qhs_compute1_cfg,
1755 &qhs_cpr_cx,
1756 &qhs_cpr_mmcx,
1757 &qhs_cpr_mx,
1758 &qhs_cpr_nspcx,
1759 &qhs_crypto0_cfg,
1760 &qhs_cx_rdpm,
1761 &qhs_dcc_cfg,
1762 &qhs_display0_cfg,
1763 &qhs_display1_cfg,
1764 &qhs_emac0_cfg,
1765 &qhs_emac1_cfg,
1766 &qhs_gpuss_cfg,
1767 &qhs_hwkm,
1768 &qhs_imem_cfg,
1769 &qhs_ipa,
1770 &qhs_ipc_router,
1771 &qhs_lpass_cfg,
1772 &qhs_mx_rdpm,
1773 &qhs_mxc_rdpm,
1774 &qhs_pcie0_cfg,
1775 &qhs_pcie1_cfg,
1776 &qhs_pcie2a_cfg,
1777 &qhs_pcie2b_cfg,
1778 &qhs_pcie3a_cfg,
1779 &qhs_pcie3b_cfg,
1780 &qhs_pcie4_cfg,
1781 &qhs_pcie_rsc_cfg,
1782 &qhs_pdm,
1783 &qhs_pimem_cfg,
1784 &qhs_pka_wrapper_cfg,
1785 &qhs_pmu_wrapper_cfg,
1786 &qhs_qdss_cfg,
1787 &qhs_sdc2,
1788 &qhs_sdc4,
1789 &qhs_security,
1790 &qhs_smmuv3_cfg,
1791 &qhs_smss_cfg,
1792 &qhs_spss_cfg,
1793 &qhs_tcsr,
1794 &qhs_tlmm,
1795 &qhs_ufs_card_cfg,
1796 &qhs_ufs_mem_cfg,
1797 &qhs_usb3_0,
1798 &qhs_usb3_1,
1799 &qhs_usb3_mp,
1800 &qhs_usb4_host_0,
1801 &qhs_usb4_host_1,
1802 &qhs_venus_cfg,
1803 &qhs_vsense_ctrl_cfg,
1804 &qhs_vsense_ctrl_r_cfg,
1805 &qns_a1_noc_cfg,
1806 &qns_a2_noc_cfg,
1807 &qns_anoc_pcie_bridge_cfg,
1808 &qns_ddrss_cfg,
1809 &qns_mnoc_cfg,
1810 &qns_snoc_cfg,
1811 &qns_snoc_sf_bridge_cfg,
1812 &srvc_cnoc
1813 },
1814 };
1815
1816 static struct qcom_icc_bcm bcm_cn2 = {
1817 .name = "CN2",
1818 .num_nodes = 4,
1819 .nodes = { &qhs_qspi,
1820 &qhs_qup0,
1821 &qhs_qup1,
1822 &qhs_qup2
1823 },
1824 };
1825
1826 static struct qcom_icc_bcm bcm_cn3 = {
1827 .name = "CN3",
1828 .num_nodes = 3,
1829 .nodes = { &qxs_imem,
1830 &xs_smss,
1831 &xs_sys_tcu_cfg
1832 },
1833 };
1834
1835 static struct qcom_icc_bcm bcm_mc0 = {
1836 .name = "MC0",
1837 .keepalive = true,
1838 .num_nodes = 1,
1839 .nodes = { &ebi },
1840 };
1841
1842 static struct qcom_icc_bcm bcm_mm0 = {
1843 .name = "MM0",
1844 .keepalive = true,
1845 .num_nodes = 5,
1846 .nodes = { &qnm_camnoc_hf,
1847 &qnm_mdp0_0,
1848 &qnm_mdp0_1,
1849 &qnm_mdp1_0,
1850 &qns_mem_noc_hf
1851 },
1852 };
1853
1854 static struct qcom_icc_bcm bcm_mm1 = {
1855 .name = "MM1",
1856 .num_nodes = 8,
1857 .nodes = { &qnm_rot_0,
1858 &qnm_rot_1,
1859 &qnm_video0,
1860 &qnm_video1,
1861 &qnm_video_cvp,
1862 &qxm_camnoc_icp,
1863 &qxm_camnoc_sf,
1864 &qns_mem_noc_sf
1865 },
1866 };
1867
1868 static struct qcom_icc_bcm bcm_nsa0 = {
1869 .name = "NSA0",
1870 .num_nodes = 2,
1871 .nodes = { &qns_nsp_gemnoc,
1872 &qxs_nsp_xfr
1873 },
1874 };
1875
1876 static struct qcom_icc_bcm bcm_nsa1 = {
1877 .name = "NSA1",
1878 .num_nodes = 1,
1879 .nodes = { &qxm_nsp },
1880 };
1881
1882 static struct qcom_icc_bcm bcm_nsb0 = {
1883 .name = "NSB0",
1884 .num_nodes = 2,
1885 .nodes = { &qns_nspb_gemnoc,
1886 &qxs_nspb_xfr
1887 },
1888 };
1889
1890 static struct qcom_icc_bcm bcm_nsb1 = {
1891 .name = "NSB1",
1892 .num_nodes = 1,
1893 .nodes = { &qxm_nspb },
1894 };
1895
1896 static struct qcom_icc_bcm bcm_pci0 = {
1897 .name = "PCI0",
1898 .num_nodes = 1,
1899 .nodes = { &qns_pcie_gem_noc },
1900 };
1901
1902 static struct qcom_icc_bcm bcm_qup0 = {
1903 .name = "QUP0",
1904 .vote_scale = 1,
1905 .num_nodes = 1,
1906 .nodes = { &qup0_core_slave },
1907 };
1908
1909 static struct qcom_icc_bcm bcm_qup1 = {
1910 .name = "QUP1",
1911 .vote_scale = 1,
1912 .num_nodes = 1,
1913 .nodes = { &qup1_core_slave },
1914 };
1915
1916 static struct qcom_icc_bcm bcm_qup2 = {
1917 .name = "QUP2",
1918 .vote_scale = 1,
1919 .num_nodes = 1,
1920 .nodes = { &qup2_core_slave },
1921 };
1922
1923 static struct qcom_icc_bcm bcm_sh0 = {
1924 .name = "SH0",
1925 .keepalive = true,
1926 .num_nodes = 1,
1927 .nodes = { &qns_llcc },
1928 };
1929
1930 static struct qcom_icc_bcm bcm_sh2 = {
1931 .name = "SH2",
1932 .num_nodes = 1,
1933 .nodes = { &chm_apps },
1934 };
1935
1936 static struct qcom_icc_bcm bcm_sn0 = {
1937 .name = "SN0",
1938 .keepalive = true,
1939 .num_nodes = 1,
1940 .nodes = { &qns_gemnoc_sf },
1941 };
1942
1943 static struct qcom_icc_bcm bcm_sn1 = {
1944 .name = "SN1",
1945 .num_nodes = 1,
1946 .nodes = { &qns_gemnoc_gc },
1947 };
1948
1949 static struct qcom_icc_bcm bcm_sn2 = {
1950 .name = "SN2",
1951 .num_nodes = 1,
1952 .nodes = { &qxs_pimem },
1953 };
1954
1955 static struct qcom_icc_bcm bcm_sn3 = {
1956 .name = "SN3",
1957 .num_nodes = 2,
1958 .nodes = { &qns_a1noc_snoc,
1959 &qnm_aggre1_noc
1960 },
1961 };
1962
1963 static struct qcom_icc_bcm bcm_sn4 = {
1964 .name = "SN4",
1965 .num_nodes = 2,
1966 .nodes = { &qns_a2noc_snoc,
1967 &qnm_aggre2_noc
1968 },
1969 };
1970
1971 static struct qcom_icc_bcm bcm_sn5 = {
1972 .name = "SN5",
1973 .num_nodes = 2,
1974 .nodes = { &qns_aggre_usb_snoc,
1975 &qnm_aggre_usb_noc
1976 },
1977 };
1978
1979 static struct qcom_icc_bcm bcm_sn9 = {
1980 .name = "SN9",
1981 .num_nodes = 2,
1982 .nodes = { &qns_sysnoc,
1983 &qnm_lpass_noc
1984 },
1985 };
1986
1987 static struct qcom_icc_bcm bcm_sn10 = {
1988 .name = "SN10",
1989 .num_nodes = 1,
1990 .nodes = { &xs_qdss_stm },
1991 };
1992
1993 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1994 &bcm_sn3,
1995 &bcm_sn5,
1996 };
1997
1998 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1999 [MASTER_QSPI_0] = &qhm_qspi,
2000 [MASTER_QUP_1] = &qhm_qup1,
2001 [MASTER_QUP_2] = &qhm_qup2,
2002 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
2003 [MASTER_IPA] = &qxm_ipa,
2004 [MASTER_EMAC_1] = &xm_emac_1,
2005 [MASTER_SDCC_4] = &xm_sdc4,
2006 [MASTER_UFS_MEM] = &xm_ufs_mem,
2007 [MASTER_USB3_0] = &xm_usb3_0,
2008 [MASTER_USB3_1] = &xm_usb3_1,
2009 [MASTER_USB3_MP] = &xm_usb3_mp,
2010 [MASTER_USB4_0] = &xm_usb4_host0,
2011 [MASTER_USB4_1] = &xm_usb4_host1,
2012 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
2013 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc,
2014 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
2015 };
2016
2017 static const struct qcom_icc_desc sc8280xp_aggre1_noc = {
2018 .nodes = aggre1_noc_nodes,
2019 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
2020 .bcms = aggre1_noc_bcms,
2021 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
2022 };
2023
2024 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
2025 &bcm_ce0,
2026 &bcm_pci0,
2027 &bcm_sn4,
2028 };
2029
2030 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
2031 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
2032 [MASTER_QUP_0] = &qhm_qup0,
2033 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
2034 [MASTER_CRYPTO] = &qxm_crypto,
2035 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6,
2036 [MASTER_SP] = &qxm_sp,
2037 [MASTER_EMAC] = &xm_emac_0,
2038 [MASTER_PCIE_0] = &xm_pcie3_0,
2039 [MASTER_PCIE_1] = &xm_pcie3_1,
2040 [MASTER_PCIE_2A] = &xm_pcie3_2a,
2041 [MASTER_PCIE_2B] = &xm_pcie3_2b,
2042 [MASTER_PCIE_3A] = &xm_pcie3_3a,
2043 [MASTER_PCIE_3B] = &xm_pcie3_3b,
2044 [MASTER_PCIE_4] = &xm_pcie3_4,
2045 [MASTER_QDSS_ETR] = &xm_qdss_etr,
2046 [MASTER_SDCC_2] = &xm_sdc2,
2047 [MASTER_UFS_CARD] = &xm_ufs_card,
2048 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
2049 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc,
2050 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
2051 };
2052
2053 static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
2054 .nodes = aggre2_noc_nodes,
2055 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
2056 .bcms = aggre2_noc_bcms,
2057 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
2058 };
2059
2060 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
2061 &bcm_qup0,
2062 &bcm_qup1,
2063 &bcm_qup2,
2064 };
2065
2066 static struct qcom_icc_node * const clk_virt_nodes[] = {
2067 [MASTER_QUP_CORE_0] = &qup0_core_master,
2068 [MASTER_QUP_CORE_1] = &qup1_core_master,
2069 [MASTER_QUP_CORE_2] = &qup2_core_master,
2070 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
2071 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
2072 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
2073 };
2074
2075 static const struct qcom_icc_desc sc8280xp_clk_virt = {
2076 .nodes = clk_virt_nodes,
2077 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
2078 .bcms = clk_virt_bcms,
2079 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
2080 };
2081
2082 static struct qcom_icc_bcm * const config_noc_bcms[] = {
2083 &bcm_cn0,
2084 &bcm_cn1,
2085 &bcm_cn2,
2086 &bcm_cn3,
2087 &bcm_sn2,
2088 &bcm_sn10,
2089 };
2090
2091 static struct qcom_icc_node * const config_noc_nodes[] = {
2092 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
2093 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
2094 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
2095 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
2096 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
2097 [SLAVE_AOSS] = &qhs_aoss,
2098 [SLAVE_APPSS] = &qhs_apss,
2099 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
2100 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
2101 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
2102 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
2103 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
2104 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
2105 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
2106 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
2107 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
2108 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
2109 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
2110 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
2111 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
2112 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
2113 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
2114 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
2115 [SLAVE_HWKM] = &qhs_hwkm,
2116 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
2117 [SLAVE_IPA_CFG] = &qhs_ipa,
2118 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
2119 [SLAVE_LPASS] = &qhs_lpass_cfg,
2120 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
2121 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
2122 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
2123 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
2124 [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg,
2125 [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg,
2126 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg,
2127 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg,
2128 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg,
2129 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
2130 [SLAVE_PDM] = &qhs_pdm,
2131 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
2132 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
2133 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
2134 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
2135 [SLAVE_QSPI_0] = &qhs_qspi,
2136 [SLAVE_QUP_0] = &qhs_qup0,
2137 [SLAVE_QUP_1] = &qhs_qup1,
2138 [SLAVE_QUP_2] = &qhs_qup2,
2139 [SLAVE_SDCC_2] = &qhs_sdc2,
2140 [SLAVE_SDCC_4] = &qhs_sdc4,
2141 [SLAVE_SECURITY] = &qhs_security,
2142 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg,
2143 [SLAVE_SMSS_CFG] = &qhs_smss_cfg,
2144 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
2145 [SLAVE_TCSR] = &qhs_tcsr,
2146 [SLAVE_TLMM] = &qhs_tlmm,
2147 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
2148 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
2149 [SLAVE_USB3_0] = &qhs_usb3_0,
2150 [SLAVE_USB3_1] = &qhs_usb3_1,
2151 [SLAVE_USB3_MP] = &qhs_usb3_mp,
2152 [SLAVE_USB4_0] = &qhs_usb4_host_0,
2153 [SLAVE_USB4_1] = &qhs_usb4_host_1,
2154 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
2155 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
2156 [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg,
2157 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
2158 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
2159 [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg,
2160 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
2161 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
2162 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
2163 [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg,
2164 [SLAVE_IMEM] = &qxs_imem,
2165 [SLAVE_PIMEM] = &qxs_pimem,
2166 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
2167 [SLAVE_PCIE_0] = &xs_pcie_0,
2168 [SLAVE_PCIE_1] = &xs_pcie_1,
2169 [SLAVE_PCIE_2A] = &xs_pcie_2a,
2170 [SLAVE_PCIE_2B] = &xs_pcie_2b,
2171 [SLAVE_PCIE_3A] = &xs_pcie_3a,
2172 [SLAVE_PCIE_3B] = &xs_pcie_3b,
2173 [SLAVE_PCIE_4] = &xs_pcie_4,
2174 [SLAVE_QDSS_STM] = &xs_qdss_stm,
2175 [SLAVE_SMSS] = &xs_smss,
2176 [SLAVE_TCU] = &xs_sys_tcu_cfg,
2177 };
2178
2179 static const struct qcom_icc_desc sc8280xp_config_noc = {
2180 .nodes = config_noc_nodes,
2181 .num_nodes = ARRAY_SIZE(config_noc_nodes),
2182 .bcms = config_noc_bcms,
2183 .num_bcms = ARRAY_SIZE(config_noc_bcms),
2184 };
2185
2186 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
2187 };
2188
2189 static struct qcom_icc_node * const dc_noc_nodes[] = {
2190 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2191 [SLAVE_LLCC_CFG] = &qhs_llcc,
2192 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2193 };
2194
2195 static const struct qcom_icc_desc sc8280xp_dc_noc = {
2196 .nodes = dc_noc_nodes,
2197 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
2198 .bcms = dc_noc_bcms,
2199 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
2200 };
2201
2202 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
2203 &bcm_sh0,
2204 &bcm_sh2,
2205 };
2206
2207 static struct qcom_icc_node * const gem_noc_nodes[] = {
2208 [MASTER_GPU_TCU] = &alm_gpu_tcu,
2209 [MASTER_PCIE_TCU] = &alm_pcie_tcu,
2210 [MASTER_SYS_TCU] = &alm_sys_tcu,
2211 [MASTER_APPSS_PROC] = &chm_apps,
2212 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
2213 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
2214 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
2215 [MASTER_GFX3D] = &qnm_gpu,
2216 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2217 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2218 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
2219 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
2220 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2221 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
2222 [SLAVE_LLCC] = &qns_llcc,
2223 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
2224 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
2225 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
2226 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
2227 };
2228
2229 static const struct qcom_icc_desc sc8280xp_gem_noc = {
2230 .nodes = gem_noc_nodes,
2231 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
2232 .bcms = gem_noc_bcms,
2233 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
2234 };
2235
2236 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
2237 &bcm_sn9,
2238 };
2239
2240 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2241 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2242 [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2243 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
2244 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
2245 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
2246 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
2247 [SLAVE_LPASS_SNOC] = &qns_sysnoc,
2248 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
2249 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2250 };
2251
2252 static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = {
2253 .nodes = lpass_ag_noc_nodes,
2254 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2255 .bcms = lpass_ag_noc_bcms,
2256 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2257 };
2258
2259 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2260 &bcm_acv,
2261 &bcm_mc0,
2262 };
2263
2264 static struct qcom_icc_node * const mc_virt_nodes[] = {
2265 [MASTER_LLCC] = &llcc_mc,
2266 [SLAVE_EBI1] = &ebi,
2267 };
2268
2269 static const struct qcom_icc_desc sc8280xp_mc_virt = {
2270 .nodes = mc_virt_nodes,
2271 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
2272 .bcms = mc_virt_bcms,
2273 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
2274 };
2275
2276 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2277 &bcm_mm0,
2278 &bcm_mm1,
2279 };
2280
2281 static struct qcom_icc_node * const mmss_noc_nodes[] = {
2282 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2283 [MASTER_MDP0] = &qnm_mdp0_0,
2284 [MASTER_MDP1] = &qnm_mdp0_1,
2285 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
2286 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
2287 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
2288 [MASTER_ROTATOR] = &qnm_rot_0,
2289 [MASTER_ROTATOR_1] = &qnm_rot_1,
2290 [MASTER_VIDEO_P0] = &qnm_video0,
2291 [MASTER_VIDEO_P1] = &qnm_video1,
2292 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
2293 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
2294 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
2295 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2296 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2297 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2298 };
2299
2300 static const struct qcom_icc_desc sc8280xp_mmss_noc = {
2301 .nodes = mmss_noc_nodes,
2302 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2303 .bcms = mmss_noc_bcms,
2304 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2305 };
2306
2307 static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
2308 &bcm_nsa0,
2309 &bcm_nsa1,
2310 };
2311
2312 static struct qcom_icc_node * const nspa_noc_nodes[] = {
2313 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2314 [MASTER_CDSP_PROC] = &qxm_nsp,
2315 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2316 [SLAVE_NSP_XFR] = &qxs_nsp_xfr,
2317 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2318 };
2319
2320 static const struct qcom_icc_desc sc8280xp_nspa_noc = {
2321 .nodes = nspa_noc_nodes,
2322 .num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2323 .bcms = nspa_noc_bcms,
2324 .num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2325 };
2326
2327 static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
2328 &bcm_nsb0,
2329 &bcm_nsb1,
2330 };
2331
2332 static struct qcom_icc_node * const nspb_noc_nodes[] = {
2333 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2334 [MASTER_CDSP_PROC_B] = &qxm_nspb,
2335 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
2336 [SLAVE_NSPB_XFR] = &qxs_nspb_xfr,
2337 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
2338 };
2339
2340 static const struct qcom_icc_desc sc8280xp_nspb_noc = {
2341 .nodes = nspb_noc_nodes,
2342 .num_nodes = ARRAY_SIZE(nspb_noc_nodes),
2343 .bcms = nspb_noc_bcms,
2344 .num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2345 };
2346
2347 static struct qcom_icc_bcm * const system_noc_main_bcms[] = {
2348 &bcm_sn0,
2349 &bcm_sn1,
2350 &bcm_sn3,
2351 &bcm_sn4,
2352 &bcm_sn5,
2353 &bcm_sn9,
2354 };
2355
2356 static struct qcom_icc_node * const system_noc_main_nodes[] = {
2357 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2358 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2359 [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc,
2360 [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2361 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2362 [MASTER_PIMEM] = &qxm_pimem,
2363 [MASTER_GIC] = &xm_gic,
2364 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2365 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2366 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
2367 };
2368
2369 static const struct qcom_icc_desc sc8280xp_system_noc_main = {
2370 .nodes = system_noc_main_nodes,
2371 .num_nodes = ARRAY_SIZE(system_noc_main_nodes),
2372 .bcms = system_noc_main_bcms,
2373 .num_bcms = ARRAY_SIZE(system_noc_main_bcms),
2374 };
2375
2376 static const struct of_device_id qnoc_of_match[] = {
2377 { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, },
2378 { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, },
2379 { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, },
2380 { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, },
2381 { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, },
2382 { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, },
2383 { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, },
2384 { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, },
2385 { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, },
2386 { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, },
2387 { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, },
2388 { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, },
2389 { }
2390 };
2391 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2392
2393 static struct platform_driver qnoc_driver = {
2394 .probe = qcom_icc_rpmh_probe,
2395 .remove = qcom_icc_rpmh_remove,
2396 .driver = {
2397 .name = "qnoc-sc8280xp",
2398 .of_match_table = qnoc_of_match,
2399 .sync_state = icc_sync_state,
2400 },
2401 };
2402
qnoc_driver_init(void)2403 static int __init qnoc_driver_init(void)
2404 {
2405 return platform_driver_register(&qnoc_driver);
2406 }
2407 core_initcall(qnoc_driver_init);
2408
qnoc_driver_exit(void)2409 static void __exit qnoc_driver_exit(void)
2410 {
2411 platform_driver_unregister(&qnoc_driver);
2412 }
2413 module_exit(qnoc_driver_exit);
2414
2415 MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver");
2416 MODULE_LICENSE("GPL");
2417