1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
4 * Pin compatible with the LMK0482x family
5 *
6 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
7 *
8 * Copyright (c) 2020, Xiphos Systems Corp.
9 *
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/device.h>
16 #include <linux/gcd.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/module.h>
19 #include <linux/regmap.h>
20 #include <linux/spi/spi.h>
21
22 /* 0x000 - 0x00d System Functions */
23 #define LMK04832_REG_RST3W 0x000
24 #define LMK04832_BIT_RESET BIT(7)
25 #define LMK04832_BIT_SPI_3WIRE_DIS BIT(4)
26 #define LMK04832_REG_POWERDOWN 0x002
27 #define LMK04832_REG_ID_DEV_TYPE 0x003
28 #define LMK04832_REG_ID_PROD_MSB 0x004
29 #define LMK04832_REG_ID_PROD_LSB 0x005
30 #define LMK04832_REG_ID_MASKREV 0x006
31 #define LMK04832_REG_ID_VNDR_MSB 0x00c
32 #define LMK04832_REG_ID_VNDR_LSB 0x00d
33
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
35 #define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8)
36 #define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0)
37 #define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8)
38 #define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0)
39 #define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8)
40 #define LMK04832_BIT_CLKOUTX_Y_PD BIT(7)
41 #define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4)
42 #define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2)
43 #define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0)
44 #define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
45 #define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5)
46 #define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8)
47 #define LMK04832_BIT_DCLKX_Y_PD BIT(4)
48 #define LMK04832_BIT_DCLKX_Y_DCC BIT(2)
49 #define LMK04832_BIT_DCLKX_Y_HS BIT(0)
50 #define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8)
51 #define LMK04832_BIT_SCLK_PD BIT(4)
52 #define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2)
53 #define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8)
54 #define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8)
55 #define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0)
56 #define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8)
57 #define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f)
58 #define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00
59 #define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01
60 #define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02
61 #define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03
62 #define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04
63 #define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05
64 #define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06
65 #define LMK04832_VAL_CLKOUT_FMT_CML16 0x07
66 #define LMK04832_VAL_CLKOUT_FMT_CML24 0x08
67 #define LMK04832_VAL_CLKOUT_FMT_CML32 0x09
68 #define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a
69 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b
70 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c
71 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d
72 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e
73 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f
74
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
76 #define LMK04832_REG_VCO_OSCOUT 0x138
77 #define LMK04832_BIT_VCO_MUX GENMASK(6, 5)
78 #define LMK04832_VAL_VCO_MUX_VCO0 0x00
79 #define LMK04832_VAL_VCO_MUX_VCO1 0x01
80 #define LMK04832_VAL_VCO_MUX_EXT 0x02
81 #define LMK04832_REG_SYSREF_OUT 0x139
82 #define LMK04832_BIT_SYSREF_REQ_EN BIT(6)
83 #define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0)
84 #define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00
85 #define LMK04832_VAL_SYSREF_MUX_RECLK 0x01
86 #define LMK04832_VAL_SYSREF_MUX_PULSER 0x02
87 #define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03
88 #define LMK04832_REG_SYSREF_DIV_MSB 0x13a
89 #define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0)
90 #define LMK04832_REG_SYSREF_DIV_LSB 0x13b
91 #define LMK04832_REG_SYSREF_DDLY_MSB 0x13c
92 #define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0)
93 #define LMK04832_REG_SYSREF_DDLY_LSB 0x13d
94 #define LMK04832_REG_SYSREF_PULSE_CNT 0x13e
95 #define LMK04832_REG_FB_CTRL 0x13f
96 #define LMK04832_BIT_PLL2_RCLK_MUX BIT(7)
97 #define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00
98 #define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01
99 #define LMK04832_BIT_PLL2_NCLK_MUX BIT(5)
100 #define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00
101 #define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01
102 #define LMK04832_BIT_FB_MUX_EN BIT(0)
103 #define LMK04832_REG_MAIN_PD 0x140
104 #define LMK04832_BIT_PLL1_PD BIT(7)
105 #define LMK04832_BIT_VCO_LDO_PD BIT(6)
106 #define LMK04832_BIT_VCO_PD BIT(5)
107 #define LMK04832_BIT_OSCIN_PD BIT(4)
108 #define LMK04832_BIT_SYSREF_GBL_PD BIT(3)
109 #define LMK04832_BIT_SYSREF_PD BIT(2)
110 #define LMK04832_BIT_SYSREF_DDLY_PD BIT(1)
111 #define LMK04832_BIT_SYSREF_PLSR_PD BIT(0)
112 #define LMK04832_REG_SYNC 0x143
113 #define LMK04832_BIT_SYNC_CLR BIT(7)
114 #define LMK04832_BIT_SYNC_1SHOT_EN BIT(6)
115 #define LMK04832_BIT_SYNC_POL BIT(5)
116 #define LMK04832_BIT_SYNC_EN BIT(4)
117 #define LMK04832_BIT_SYNC_MODE GENMASK(1, 0)
118 #define LMK04832_VAL_SYNC_MODE_OFF 0x00
119 #define LMK04832_VAL_SYNC_MODE_ON 0x01
120 #define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02
121 #define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03
122 #define LMK04832_REG_SYNC_DIS 0x144
123
124 /* 0x146 - 0x14a CLKin Control */
125 #define LMK04832_REG_CLKIN_SEL0 0x148
126 #define LMK04832_REG_CLKIN_SEL1 0x149
127 #define LMK04832_REG_CLKIN_RST 0x14a
128 #define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6)
129 #define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3)
130 #define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06
131 #define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0)
132 #define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03
133
134 /* 0x14b - 0x152 Holdover */
135
136 /* 0x153 - 0x15f PLL1 Configuration */
137 #define LMK04832_REG_PLL1_LD 0x15f
138 #define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)
139 #define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07
140 #define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)
141 #define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03
142
143 /* 0x160 - 0x16e PLL2 Configuration */
144 #define LMK04832_REG_PLL2_R_MSB 0x160
145 #define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0)
146 #define LMK04832_REG_PLL2_R_LSB 0x161
147 #define LMK04832_REG_PLL2_MISC 0x162
148 #define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5)
149 #define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0)
150 #define LMK04832_REG_PLL2_N_CAL_0 0x163
151 #define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0)
152 #define LMK04832_REG_PLL2_N_CAL_1 0x164
153 #define LMK04832_REG_PLL2_N_CAL_2 0x165
154 #define LMK04832_REG_PLL2_N_0 0x166
155 #define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0)
156 #define LMK04832_REG_PLL2_N_1 0x167
157 #define LMK04832_REG_PLL2_N_2 0x168
158 #define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a
159 #define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b
160 #define LMK04832_REG_PLL2_LD 0x16e
161 #define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3)
162 #define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02
163 #define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0)
164 #define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03
165
166 /* 0x16F - 0x555 Misc Registers */
167 #define LMK04832_REG_PLL2_PD 0x173
168 #define LMK04832_BIT_PLL2_PRE_PD BIT(6)
169 #define LMK04832_BIT_PLL2_PD BIT(5)
170 #define LMK04832_REG_PLL1R_RST 0x177
171 #define LMK04832_REG_CLR_PLL_LOST 0x182
172 #define LMK04832_REG_RB_PLL_LD 0x183
173 #define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184
174 #define LMK04832_REG_RB_DAC_VAL_LSB 0x185
175 #define LMK04832_REG_RB_HOLDOVER 0x188
176 #define LMK04832_REG_SPI_LOCK 0x555
177
178 /**
179 * struct lmk04832_device_info - Holds static device information that is
180 * specific to the chip revision
181 *
182 * @pid: Product Identifier
183 * @maskrev: IC version identifier
184 * @num_channels: Number of available output channels (clkout count)
185 * @vco0_range: {min, max} of the VCO0 operating range (in MHz)
186 * @vco1_range: {min, max} of the VCO1 operating range (in MHz)
187 */
188 struct lmk04832_device_info {
189 u16 pid;
190 u8 maskrev;
191 size_t num_channels;
192 unsigned int vco0_range[2];
193 unsigned int vco1_range[2];
194 };
195
196 static const struct lmk04832_device_info lmk04832_device_info = {
197 .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
198 .maskrev = 0x70,
199 .num_channels = 14,
200 .vco0_range = { 2440, 2580 },
201 .vco1_range = { 2945, 3255 },
202 };
203
204 enum lmk04832_rdbk_type {
205 RDBK_CLKIN_SEL0,
206 RDBK_CLKIN_SEL1,
207 RDBK_RESET,
208 RDBK_PLL1_LD,
209 };
210
211 struct lmk_dclk {
212 struct lmk04832 *lmk;
213 struct clk_hw hw;
214 u8 id;
215 };
216
217 struct lmk_clkout {
218 struct lmk04832 *lmk;
219 struct clk_hw hw;
220 bool sysref;
221 u32 format;
222 u8 id;
223 };
224
225 /**
226 * struct lmk04832 - The LMK04832 device structure
227 *
228 * @dev: reference to a struct device, linked to the spi_device
229 * @regmap: struct regmap instance use to access the chip
230 * @sync_mode: operational mode for SYNC signal
231 * @sysref_mux: select SYSREF source
232 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
233 * mode.
234 * @sysref_ddly: SYSREF digital delay value
235 * @oscin: PLL2 input clock
236 * @vco: reference to the internal VCO clock
237 * @sclk: reference to the internal sysref clock (SCLK)
238 * @vco_rate: user provided VCO rate
239 * @reset_gpio: reference to the reset GPIO
240 * @dclk: list of internal device clock references.
241 * Each pair of clkout clocks share a single device clock (DCLKX_Y)
242 * @clkout: list of output clock references
243 * @clk_data: holds clkout related data like clk_hw* and number of clocks
244 */
245 struct lmk04832 {
246 struct device *dev;
247 struct regmap *regmap;
248
249 unsigned int sync_mode;
250 unsigned int sysref_mux;
251 unsigned int sysref_pulse_cnt;
252 unsigned int sysref_ddly;
253
254 struct clk *oscin;
255 struct clk_hw vco;
256 struct clk_hw sclk;
257 unsigned int vco_rate;
258
259 struct gpio_desc *reset_gpio;
260
261 struct lmk_dclk *dclk;
262 struct lmk_clkout *clkout;
263 struct clk_hw_onecell_data *clk_data;
264 };
265
lmk04832_regmap_rd_regs(struct device * dev,unsigned int reg)266 static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
267 {
268 switch (reg) {
269 case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
270 case LMK04832_REG_ID_VNDR_MSB:
271 case LMK04832_REG_ID_VNDR_LSB:
272 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
273 case LMK04832_REG_PLL2_LD:
274 case LMK04832_REG_PLL2_PD:
275 case LMK04832_REG_PLL1R_RST:
276 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
277 case LMK04832_REG_RB_HOLDOVER:
278 case LMK04832_REG_SPI_LOCK:
279 return true;
280 default:
281 return false;
282 };
283 }
284
lmk04832_regmap_wr_regs(struct device * dev,unsigned int reg)285 static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
286 {
287 switch (reg) {
288 case LMK04832_REG_RST3W:
289 case LMK04832_REG_POWERDOWN:
290 return true;
291 case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
292 case LMK04832_REG_ID_VNDR_MSB:
293 case LMK04832_REG_ID_VNDR_LSB:
294 return false;
295 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
296 case LMK04832_REG_PLL2_LD:
297 case LMK04832_REG_PLL2_PD:
298 case LMK04832_REG_PLL1R_RST:
299 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
300 case LMK04832_REG_RB_HOLDOVER:
301 case LMK04832_REG_SPI_LOCK:
302 return true;
303 default:
304 return false;
305 };
306 }
307
308 static const struct regmap_config regmap_config = {
309 .name = "lmk04832",
310 .reg_bits = 16,
311 .val_bits = 8,
312 .use_single_read = 1,
313 .use_single_write = 1,
314 .read_flag_mask = 0x80,
315 .write_flag_mask = 0x00,
316 .readable_reg = lmk04832_regmap_rd_regs,
317 .writeable_reg = lmk04832_regmap_wr_regs,
318 .cache_type = REGCACHE_NONE,
319 .max_register = LMK04832_REG_SPI_LOCK,
320 };
321
lmk04832_vco_is_enabled(struct clk_hw * hw)322 static int lmk04832_vco_is_enabled(struct clk_hw *hw)
323 {
324 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
325 unsigned int tmp;
326 int ret;
327
328 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
329 if (ret)
330 return ret;
331
332 return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
333 FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
334 FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
335 }
336
lmk04832_vco_prepare(struct clk_hw * hw)337 static int lmk04832_vco_prepare(struct clk_hw *hw)
338 {
339 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
340 int ret;
341
342 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
343 LMK04832_BIT_PLL2_PRE_PD |
344 LMK04832_BIT_PLL2_PD,
345 0x00);
346 if (ret)
347 return ret;
348
349 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
350 LMK04832_BIT_VCO_LDO_PD |
351 LMK04832_BIT_VCO_PD |
352 LMK04832_BIT_OSCIN_PD, 0x00);
353 }
354
lmk04832_vco_unprepare(struct clk_hw * hw)355 static void lmk04832_vco_unprepare(struct clk_hw *hw)
356 {
357 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
358
359 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
360 LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
361 0xff);
362
363 /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
364 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
365 LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
366 }
367
lmk04832_vco_recalc_rate(struct clk_hw * hw,unsigned long prate)368 static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
369 unsigned long prate)
370 {
371 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
372 static const unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
373 unsigned int pll2_n, p, pll2_r;
374 unsigned int pll2_misc;
375 unsigned long vco_rate;
376 u8 tmp[3];
377 int ret;
378
379 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
380 if (ret)
381 return ret;
382
383 p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
384
385 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
386 if (ret)
387 return ret;
388
389 pll2_n = FIELD_PREP(0x030000, tmp[0]) |
390 FIELD_PREP(0x00ff00, tmp[1]) |
391 FIELD_PREP(0x0000ff, tmp[2]);
392
393 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
394 if (ret)
395 return ret;
396
397 pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
398 FIELD_PREP(0x00ff, tmp[1]);
399
400 vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
401 pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
402
403 return vco_rate;
404 }
405
406 /**
407 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
408 *
409 * @lmk: Reference to the lmk device
410 * @rate: Desired output rate for the VCO
411 *
412 * The LMK04832 has 2 internal VCO, each with independent operating ranges.
413 * Use the device_info structure to determine which VCO to use based on rate.
414 *
415 * Returns: VCO_MUX value or negative errno.
416 */
lmk04832_check_vco_ranges(struct lmk04832 * lmk,unsigned long rate)417 static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
418 {
419 const struct lmk04832_device_info *info;
420 unsigned long mhz = rate / 1000000;
421
422 info = &lmk04832_device_info;
423
424 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
425 return LMK04832_VAL_VCO_MUX_VCO0;
426
427 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
428 return LMK04832_VAL_VCO_MUX_VCO1;
429
430 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
431 return -ERANGE;
432 }
433
434 /**
435 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
436 *
437 * @prate: parent rate to the PLL2, usually OSCin
438 * @rate: Desired output rate for the VCO
439 * @n: reference to PLL2_N
440 * @p: reference to PLL2_P
441 * @r: reference to PLL2_R
442 *
443 * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
444 * recommended in the datasheet because a higher phase detector frequencies
445 * makes the design of wider loop bandwidth filters possible.
446 *
447 * the VCO rate can be calculated using the following expression:
448 *
449 * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
450 *
451 * Returns: vco rate or negative errno.
452 */
lmk04832_calc_pll2_params(unsigned long prate,unsigned long rate,unsigned int * n,unsigned int * p,unsigned int * r)453 static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
454 unsigned int *n, unsigned int *p,
455 unsigned int *r)
456 {
457 unsigned int pll2_n, pll2_p, pll2_r;
458 unsigned long num, div;
459
460 /* Set PLL2_P to a fixed value to simplify optimizations */
461 pll2_p = 2;
462
463 div = gcd(rate, prate);
464
465 num = DIV_ROUND_CLOSEST(rate, div);
466 pll2_r = DIV_ROUND_CLOSEST(prate, div);
467
468 if (num > 4) {
469 pll2_n = num >> 2;
470 } else {
471 pll2_r = pll2_r << 2;
472 pll2_n = num;
473 }
474
475 if (pll2_n < 1 || pll2_n > 0x03ffff)
476 return -EINVAL;
477 if (pll2_r < 1 || pll2_r > 0xfff)
478 return -EINVAL;
479
480 *n = pll2_n;
481 *p = pll2_p;
482 *r = pll2_r;
483
484 return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
485 }
486
lmk04832_vco_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)487 static int lmk04832_vco_determine_rate(struct clk_hw *hw,
488 struct clk_rate_request *req)
489 {
490 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
491 unsigned int n, p, r;
492 long vco_rate;
493 int ret;
494
495 ret = lmk04832_check_vco_ranges(lmk, req->rate);
496 if (ret < 0)
497 return ret;
498
499 vco_rate = lmk04832_calc_pll2_params(req->best_parent_rate, req->rate,
500 &n, &p, &r);
501 if (vco_rate < 0) {
502 dev_err(lmk->dev, "PLL2 parameters out of range\n");
503 req->rate = vco_rate;
504
505 return 0;
506 }
507
508 if (req->rate != vco_rate)
509 return -EINVAL;
510
511 req->rate = vco_rate;
512
513 return 0;
514 }
515
lmk04832_vco_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)516 static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
517 unsigned long prate)
518 {
519 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
520 unsigned int n, p, r;
521 long vco_rate;
522 int vco_mux;
523 int ret;
524
525 vco_mux = lmk04832_check_vco_ranges(lmk, rate);
526 if (vco_mux < 0)
527 return vco_mux;
528
529 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
530 LMK04832_BIT_VCO_MUX,
531 FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
532 if (ret)
533 return ret;
534
535 vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
536 if (vco_rate < 0) {
537 dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
538 return vco_rate;
539 }
540
541 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
542 LMK04832_BIT_PLL2_R_MSB,
543 FIELD_GET(0x000700, r));
544 if (ret)
545 return ret;
546
547 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
548 FIELD_GET(0x0000ff, r));
549 if (ret)
550 return ret;
551
552 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
553 LMK04832_BIT_PLL2_MISC_P,
554 FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
555 if (ret)
556 return ret;
557
558 /*
559 * PLL2_N registers must be programmed after other PLL2 dividers are
560 * programmed to ensure proper VCO frequency calibration
561 */
562 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
563 FIELD_GET(0x030000, n));
564 if (ret)
565 return ret;
566 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
567 FIELD_GET(0x00ff00, n));
568 if (ret)
569 return ret;
570
571 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
572 FIELD_GET(0x0000ff, n));
573 }
574
575 static const struct clk_ops lmk04832_vco_ops = {
576 .is_enabled = lmk04832_vco_is_enabled,
577 .prepare = lmk04832_vco_prepare,
578 .unprepare = lmk04832_vco_unprepare,
579 .recalc_rate = lmk04832_vco_recalc_rate,
580 .determine_rate = lmk04832_vco_determine_rate,
581 .set_rate = lmk04832_vco_set_rate,
582 };
583
584 /*
585 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
586 * path in PLL2 single loop mode.
587 */
lmk04832_register_vco(struct lmk04832 * lmk)588 static int lmk04832_register_vco(struct lmk04832 *lmk)
589 {
590 const char *parent_names[1];
591 struct clk_init_data init;
592 int ret;
593
594 init.name = "lmk-vco";
595 parent_names[0] = __clk_get_name(lmk->oscin);
596 init.parent_names = parent_names;
597
598 init.ops = &lmk04832_vco_ops;
599 init.num_parents = 1;
600
601 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
602 LMK04832_BIT_VCO_MUX,
603 FIELD_PREP(LMK04832_BIT_VCO_MUX,
604 LMK04832_VAL_VCO_MUX_VCO1));
605 if (ret)
606 return ret;
607
608 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
609 LMK04832_BIT_PLL2_RCLK_MUX |
610 LMK04832_BIT_PLL2_NCLK_MUX,
611 FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
612 LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
613 FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
614 LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
615 if (ret)
616 return ret;
617
618 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
619 LMK04832_BIT_PLL2_MISC_REF_2X_EN,
620 LMK04832_BIT_PLL2_MISC_REF_2X_EN);
621 if (ret)
622 return ret;
623
624 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
625 FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
626 LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
627 FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
628 LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
629 if (ret)
630 return ret;
631
632 lmk->vco.init = &init;
633 return devm_clk_hw_register(lmk->dev, &lmk->vco);
634 }
635
lmk04832_clkout_set_ddly(struct lmk04832 * lmk,int id)636 static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
637 {
638 static const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
639 unsigned int sclkx_y_ddly = 10;
640 unsigned int dclkx_y_ddly;
641 unsigned int dclkx_y_div;
642 unsigned int sysref_ddly;
643 unsigned int dclkx_y_hs;
644 unsigned int lsb, msb;
645 int ret;
646
647 ret = regmap_update_bits(lmk->regmap,
648 LMK04832_REG_CLKOUT_CTRL2(id),
649 LMK04832_BIT_DCLKX_Y_DDLY_PD,
650 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
651 if (ret)
652 return ret;
653
654 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
655 if (ret)
656 return ret;
657
658 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
659 if (ret)
660 return ret;
661
662 sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
663
664 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
665 if (ret)
666 return ret;
667
668 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
669 if (ret)
670 return ret;
671
672 dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
673
674 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
675 if (ret)
676 return ret;
677
678 dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
679
680 dclkx_y_ddly = sysref_ddly + 1 -
681 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] -
682 dclkx_y_hs + sclkx_y_ddly;
683
684 if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
685 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
686 dclkx_y_ddly);
687 return -EINVAL;
688 }
689
690 ret = regmap_write(lmk->regmap,
691 LMK04832_REG_SCLKX_Y_DDLY(id),
692 FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
693 if (ret)
694 return ret;
695
696 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
697 FIELD_GET(0x00ff, dclkx_y_ddly));
698 if (ret)
699 return ret;
700
701 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
702 "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
703 id, sysref_ddly, dclkx_y_ddly,
704 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
705 dclkx_y_hs, sclkx_y_ddly);
706
707 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
708 LMK04832_BIT_DCLKX_Y_DDLY_MSB,
709 FIELD_GET(0x0300, dclkx_y_ddly));
710 }
711
712 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
713 * and dclk
714 *
715 * @lmk: Reference to the lmk device
716 *
717 * The synchronization sequence:
718 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
719 * (8.3.3.1 How to enable SYSREF)
720 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
721 *
722 * Returns 0 or negative errno.
723 */
lmk04832_sclk_sync_sequence(struct lmk04832 * lmk)724 static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
725 {
726 int ret;
727 int i;
728
729 /* 1. (optional) mute all sysref_outputs during synchronization */
730 /* 2. Enable and write device clock digital delay to applicable clocks */
731 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
732 LMK04832_BIT_SYSREF_DDLY_PD,
733 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
734 if (ret)
735 return ret;
736
737 for (i = 0; i < lmk->clk_data->num; i += 2) {
738 ret = lmk04832_clkout_set_ddly(lmk, i);
739 if (ret)
740 return ret;
741 }
742
743 /*
744 * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
745 * and clear SYSREF_REQ_EN (see 6.)
746 */
747 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
748 LMK04832_BIT_SYSREF_REQ_EN |
749 LMK04832_BIT_SYSREF_MUX,
750 FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
751 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
752 LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
753 if (ret)
754 return ret;
755
756 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
757 LMK04832_BIT_SYNC_MODE,
758 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
759 LMK04832_VAL_SYNC_MODE_ON));
760 if (ret)
761 return ret;
762
763 /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
764 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
765 if (ret)
766 return ret;
767
768 /*
769 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
770 * distribution path cycles (VCO cycles), then back to 0. In
771 * PLL2-only use case, this will be complete in less than one SPI
772 * transaction. If SYSREF local digital delay is not used, this step
773 * can be skipped.
774 */
775 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
776 LMK04832_BIT_SYNC_CLR,
777 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
778 if (ret)
779 return ret;
780
781 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
782 LMK04832_BIT_SYNC_CLR,
783 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
784 if (ret)
785 return ret;
786
787 /*
788 * 6. Toggle SYNC_POL state between inverted and not inverted.
789 * If you use an external signal on the SYNC pin instead of toggling
790 * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
791 * does not shift into continuous SYSREF mode.
792 */
793 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
794 LMK04832_BIT_SYNC_POL,
795 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
796 if (ret)
797 return ret;
798
799 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
800 LMK04832_BIT_SYNC_POL,
801 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
802 if (ret)
803 return ret;
804
805 /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
806 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
807 if (ret)
808 return ret;
809
810 /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
811 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
812 LMK04832_BIT_SYSREF_MUX,
813 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
814 lmk->sysref_mux));
815 if (ret)
816 return ret;
817
818 /*
819 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
820 * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
821 * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
822 * option.
823 */
824
825 /*
826 * 10. (optional) To reduce power consumption, after the synchronization
827 * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
828 * digital delay counters (which are only used immediately after the
829 * SYNC pulse to delay the output by some number of VCO counts).
830 */
831
832 return regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
833 LMK04832_BIT_SYNC_MODE,
834 FIELD_PREP(LMK04832_BIT_SYNC_MODE,
835 lmk->sync_mode));
836 }
837
lmk04832_sclk_is_enabled(struct clk_hw * hw)838 static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
839 {
840 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
841 unsigned int tmp;
842 int ret;
843
844 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
845 if (ret)
846 return ret;
847
848 return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
849 }
850
lmk04832_sclk_prepare(struct clk_hw * hw)851 static int lmk04832_sclk_prepare(struct clk_hw *hw)
852 {
853 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
854
855 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
856 LMK04832_BIT_SYSREF_PD, 0x00);
857 }
858
lmk04832_sclk_unprepare(struct clk_hw * hw)859 static void lmk04832_sclk_unprepare(struct clk_hw *hw)
860 {
861 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
862
863 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
864 LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
865 }
866
lmk04832_sclk_recalc_rate(struct clk_hw * hw,unsigned long prate)867 static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
868 unsigned long prate)
869 {
870 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
871 unsigned int sysref_div;
872 u8 tmp[2];
873 int ret;
874
875 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
876 if (ret)
877 return ret;
878
879 sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
880 tmp[1];
881
882 return DIV_ROUND_CLOSEST(prate, sysref_div);
883 }
884
lmk04832_sclk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)885 static int lmk04832_sclk_determine_rate(struct clk_hw *hw,
886 struct clk_rate_request *req)
887 {
888 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
889 unsigned long sclk_rate;
890 unsigned int sysref_div;
891
892 sysref_div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
893 sclk_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, sysref_div);
894
895 if (sysref_div < 0x07 || sysref_div > 0x1fff) {
896 dev_err(lmk->dev, "SYSREF divider out of range\n");
897 return -EINVAL;
898 }
899
900 if (req->rate != sclk_rate)
901 return -EINVAL;
902
903 req->rate = sclk_rate;
904
905 return 0;
906 }
907
lmk04832_sclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)908 static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
909 unsigned long prate)
910 {
911 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
912 unsigned int sysref_div;
913 int ret;
914
915 sysref_div = DIV_ROUND_CLOSEST(prate, rate);
916
917 if (sysref_div < 0x07 || sysref_div > 0x1fff) {
918 dev_err(lmk->dev, "SYSREF divider out of range\n");
919 return -EINVAL;
920 }
921
922 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
923 FIELD_GET(0x1f00, sysref_div));
924 if (ret)
925 return ret;
926
927 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
928 FIELD_GET(0x00ff, sysref_div));
929 if (ret)
930 return ret;
931
932 ret = lmk04832_sclk_sync_sequence(lmk);
933 if (ret)
934 dev_err(lmk->dev, "SYNC sequence failed\n");
935
936 return ret;
937 }
938
939 static const struct clk_ops lmk04832_sclk_ops = {
940 .is_enabled = lmk04832_sclk_is_enabled,
941 .prepare = lmk04832_sclk_prepare,
942 .unprepare = lmk04832_sclk_unprepare,
943 .recalc_rate = lmk04832_sclk_recalc_rate,
944 .determine_rate = lmk04832_sclk_determine_rate,
945 .set_rate = lmk04832_sclk_set_rate,
946 };
947
lmk04832_register_sclk(struct lmk04832 * lmk)948 static int lmk04832_register_sclk(struct lmk04832 *lmk)
949 {
950 const char *parent_names[1];
951 struct clk_init_data init;
952 int ret;
953
954 init.name = "lmk-sclk";
955 parent_names[0] = clk_hw_get_name(&lmk->vco);
956 init.parent_names = parent_names;
957
958 init.ops = &lmk04832_sclk_ops;
959 init.flags = CLK_SET_RATE_PARENT;
960 init.num_parents = 1;
961
962 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
963 LMK04832_BIT_SYSREF_MUX,
964 FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
965 lmk->sysref_mux));
966 if (ret)
967 return ret;
968
969 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
970 FIELD_GET(0x00ff, lmk->sysref_ddly));
971 if (ret)
972 return ret;
973
974 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
975 FIELD_GET(0x1f00, lmk->sysref_ddly));
976 if (ret)
977 return ret;
978
979 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
980 ilog2(lmk->sysref_pulse_cnt));
981 if (ret)
982 return ret;
983
984 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
985 LMK04832_BIT_SYSREF_DDLY_PD |
986 LMK04832_BIT_SYSREF_PLSR_PD,
987 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
988 FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
989 if (ret)
990 return ret;
991
992 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
993 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
994 FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
995 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
996 if (ret)
997 return ret;
998
999 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
1000 if (ret)
1001 return ret;
1002
1003 lmk->sclk.init = &init;
1004 return devm_clk_hw_register(lmk->dev, &lmk->sclk);
1005 }
1006
lmk04832_dclk_is_enabled(struct clk_hw * hw)1007 static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
1008 {
1009 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1010 struct lmk04832 *lmk = dclk->lmk;
1011 unsigned int tmp;
1012 int ret;
1013
1014 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1015 &tmp);
1016 if (ret)
1017 return ret;
1018
1019 return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
1020 }
1021
lmk04832_dclk_prepare(struct clk_hw * hw)1022 static int lmk04832_dclk_prepare(struct clk_hw *hw)
1023 {
1024 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1025 struct lmk04832 *lmk = dclk->lmk;
1026
1027 return regmap_update_bits(lmk->regmap,
1028 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1029 LMK04832_BIT_DCLKX_Y_PD, 0x00);
1030 }
1031
lmk04832_dclk_unprepare(struct clk_hw * hw)1032 static void lmk04832_dclk_unprepare(struct clk_hw *hw)
1033 {
1034 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1035 struct lmk04832 *lmk = dclk->lmk;
1036
1037 regmap_update_bits(lmk->regmap,
1038 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1039 LMK04832_BIT_DCLKX_Y_PD, 0xff);
1040 }
1041
lmk04832_dclk_recalc_rate(struct clk_hw * hw,unsigned long prate)1042 static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
1043 unsigned long prate)
1044 {
1045 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1046 struct lmk04832 *lmk = dclk->lmk;
1047 unsigned int dclk_div;
1048 unsigned int lsb, msb;
1049 unsigned long rate;
1050 int ret;
1051
1052 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1053 &lsb);
1054 if (ret)
1055 return ret;
1056
1057 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1058 &msb);
1059 if (ret)
1060 return ret;
1061
1062 dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
1063 rate = DIV_ROUND_CLOSEST(prate, dclk_div);
1064
1065 return rate;
1066 }
1067
lmk04832_dclk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)1068 static int lmk04832_dclk_determine_rate(struct clk_hw *hw,
1069 struct clk_rate_request *req)
1070 {
1071 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1072 struct lmk04832 *lmk = dclk->lmk;
1073 unsigned long dclk_rate;
1074 unsigned int dclk_div;
1075
1076 dclk_div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
1077 dclk_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, dclk_div);
1078
1079 if (dclk_div < 1 || dclk_div > 0x3ff) {
1080 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1081 return -EINVAL;
1082 }
1083
1084 if (req->rate != dclk_rate)
1085 return -EINVAL;
1086
1087 req->rate = dclk_rate;
1088
1089 return 0;
1090 }
1091
lmk04832_dclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1092 static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
1093 unsigned long prate)
1094 {
1095 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1096 struct lmk04832 *lmk = dclk->lmk;
1097 unsigned int dclk_div;
1098 int ret;
1099
1100 dclk_div = DIV_ROUND_CLOSEST(prate, rate);
1101
1102 if (dclk_div > 0x3ff) {
1103 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1104 return -EINVAL;
1105 }
1106
1107 /* Enable Duty Cycle Correction */
1108 if (dclk_div == 1) {
1109 ret = regmap_update_bits(lmk->regmap,
1110 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1111 LMK04832_BIT_DCLKX_Y_DCC,
1112 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
1113 if (ret)
1114 return ret;
1115 }
1116
1117 /*
1118 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
1119 * procedure requires to first program Divide-by-4 and then back to
1120 * Divide-by-2 or Divide-by-3 before doing SYNC.
1121 */
1122 if (dclk_div == 2 || dclk_div == 3) {
1123 ret = regmap_update_bits(lmk->regmap,
1124 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1125 LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1126 if (ret)
1127 return ret;
1128
1129 ret = regmap_write(lmk->regmap,
1130 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
1131 if (ret)
1132 return ret;
1133 }
1134
1135 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1136 FIELD_GET(0x0ff, dclk_div));
1137 if (ret)
1138 return ret;
1139
1140 ret = regmap_update_bits(lmk->regmap,
1141 LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1142 LMK04832_BIT_DCLK_DIV_MSB,
1143 FIELD_GET(0x300, dclk_div));
1144 if (ret)
1145 return ret;
1146
1147 ret = lmk04832_sclk_sync_sequence(lmk);
1148 if (ret)
1149 dev_err(lmk->dev, "SYNC sequence failed\n");
1150
1151 return ret;
1152 }
1153
1154 static const struct clk_ops lmk04832_dclk_ops = {
1155 .is_enabled = lmk04832_dclk_is_enabled,
1156 .prepare = lmk04832_dclk_prepare,
1157 .unprepare = lmk04832_dclk_unprepare,
1158 .recalc_rate = lmk04832_dclk_recalc_rate,
1159 .determine_rate = lmk04832_dclk_determine_rate,
1160 .set_rate = lmk04832_dclk_set_rate,
1161 };
1162
lmk04832_clkout_is_enabled(struct clk_hw * hw)1163 static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
1164 {
1165 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1166 struct lmk04832 *lmk = clkout->lmk;
1167 unsigned int clkoutx_y_pd;
1168 unsigned int sclkx_y_pd;
1169 unsigned int tmp;
1170 u32 enabled;
1171 int ret;
1172 u8 fmt;
1173
1174 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1175 &clkoutx_y_pd);
1176 if (ret)
1177 return ret;
1178
1179 enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
1180
1181 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1182 &tmp);
1183 if (ret)
1184 return ret;
1185
1186 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1187 ret = regmap_read(lmk->regmap,
1188 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1189 &sclkx_y_pd);
1190 if (ret)
1191 return ret;
1192
1193 enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
1194 }
1195
1196 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1197 &tmp);
1198 if (ret)
1199 return ret;
1200
1201 if (clkout->id % 2)
1202 fmt = FIELD_GET(0xf0, tmp);
1203 else
1204 fmt = FIELD_GET(0x0f, tmp);
1205
1206 return enabled && !fmt;
1207 }
1208
lmk04832_clkout_prepare(struct clk_hw * hw)1209 static int lmk04832_clkout_prepare(struct clk_hw *hw)
1210 {
1211 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1212 struct lmk04832 *lmk = clkout->lmk;
1213 unsigned int tmp;
1214 int ret;
1215
1216 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
1217 dev_err(lmk->dev, "prepared %s but format is powerdown\n",
1218 clk_hw_get_name(hw));
1219
1220 ret = regmap_update_bits(lmk->regmap,
1221 LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1222 LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1223 if (ret)
1224 return ret;
1225
1226 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1227 &tmp);
1228 if (ret)
1229 return ret;
1230
1231 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1232 ret = regmap_update_bits(lmk->regmap,
1233 LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1234 LMK04832_BIT_SCLK_PD, 0x00);
1235 if (ret)
1236 return ret;
1237 }
1238
1239 return regmap_update_bits(lmk->regmap,
1240 LMK04832_REG_CLKOUT_FMT(clkout->id),
1241 LMK04832_BIT_CLKOUT_FMT(clkout->id),
1242 clkout->format << 4 * (clkout->id % 2));
1243 }
1244
lmk04832_clkout_unprepare(struct clk_hw * hw)1245 static void lmk04832_clkout_unprepare(struct clk_hw *hw)
1246 {
1247 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1248 struct lmk04832 *lmk = clkout->lmk;
1249
1250 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1251 LMK04832_BIT_CLKOUT_FMT(clkout->id),
1252 0x00);
1253 }
1254
lmk04832_clkout_set_parent(struct clk_hw * hw,uint8_t index)1255 static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
1256 {
1257 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1258 struct lmk04832 *lmk = clkout->lmk;
1259
1260 return regmap_update_bits(lmk->regmap,
1261 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1262 LMK04832_BIT_CLKOUT_SRC_MUX,
1263 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1264 index));
1265 }
1266
lmk04832_clkout_get_parent(struct clk_hw * hw)1267 static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
1268 {
1269 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1270 struct lmk04832 *lmk = clkout->lmk;
1271 unsigned int tmp;
1272 int ret;
1273
1274 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1275 &tmp);
1276 if (ret)
1277 return ret;
1278
1279 return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
1280 }
1281
1282 static const struct clk_ops lmk04832_clkout_ops = {
1283 .is_enabled = lmk04832_clkout_is_enabled,
1284 .prepare = lmk04832_clkout_prepare,
1285 .unprepare = lmk04832_clkout_unprepare,
1286 .determine_rate = __clk_mux_determine_rate,
1287 .set_parent = lmk04832_clkout_set_parent,
1288 .get_parent = lmk04832_clkout_get_parent,
1289 };
1290
lmk04832_register_clkout(struct lmk04832 * lmk,const int num)1291 static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
1292 {
1293 char name[] = "lmk-clkoutXX";
1294 char dclk_name[] = "lmk-dclkXX_YY";
1295 const char *parent_names[2];
1296 struct clk_init_data init;
1297 int dclk_num = num / 2;
1298 int ret;
1299
1300 if (num % 2 == 0) {
1301 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
1302 init.name = dclk_name;
1303 parent_names[0] = clk_hw_get_name(&lmk->vco);
1304 init.parent_names = parent_names;
1305 init.ops = &lmk04832_dclk_ops;
1306 init.flags = CLK_SET_RATE_PARENT;
1307 init.num_parents = 1;
1308
1309 lmk->dclk[dclk_num].id = num;
1310 lmk->dclk[dclk_num].lmk = lmk;
1311 lmk->dclk[dclk_num].hw.init = &init;
1312
1313 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
1314 if (ret)
1315 return ret;
1316 } else {
1317 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
1318 }
1319
1320 if (of_property_read_string_index(lmk->dev->of_node,
1321 "clock-output-names",
1322 num, &init.name)) {
1323 sprintf(name, "lmk-clkout%02d", num);
1324 init.name = name;
1325 }
1326
1327 parent_names[0] = dclk_name;
1328 parent_names[1] = clk_hw_get_name(&lmk->sclk);
1329 init.parent_names = parent_names;
1330 init.ops = &lmk04832_clkout_ops;
1331 init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
1332 init.num_parents = ARRAY_SIZE(parent_names);
1333
1334 lmk->clkout[num].id = num;
1335 lmk->clkout[num].lmk = lmk;
1336 lmk->clkout[num].hw.init = &init;
1337 lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
1338
1339 /* Set initial parent */
1340 regmap_update_bits(lmk->regmap,
1341 LMK04832_REG_CLKOUT_SRC_MUX(num),
1342 LMK04832_BIT_CLKOUT_SRC_MUX,
1343 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1344 lmk->clkout[num].sysref));
1345
1346 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
1347 }
1348
lmk04832_set_spi_rdbk(const struct lmk04832 * lmk,const int rdbk_pin)1349 static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
1350 {
1351 int reg;
1352 int ret;
1353 int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
1354 LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
1355 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
1356 LMK04832_VAL_CLKIN_SEL_TYPE_OUT);
1357
1358 dev_info(lmk->dev, "setting up 4-wire mode\n");
1359 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
1360 LMK04832_BIT_SPI_3WIRE_DIS);
1361 if (ret)
1362 return ret;
1363
1364 switch (rdbk_pin) {
1365 case RDBK_CLKIN_SEL0:
1366 reg = LMK04832_REG_CLKIN_SEL0;
1367 break;
1368 case RDBK_CLKIN_SEL1:
1369 reg = LMK04832_REG_CLKIN_SEL1;
1370 break;
1371 case RDBK_RESET:
1372 reg = LMK04832_REG_CLKIN_RST;
1373 break;
1374 case RDBK_PLL1_LD:
1375 reg = LMK04832_REG_PLL1_LD;
1376 val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,
1377 LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |
1378 FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,
1379 LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);
1380 break;
1381 default:
1382 return -EINVAL;
1383 }
1384
1385 return regmap_write(lmk->regmap, reg, val);
1386 }
1387
lmk04832_probe(struct spi_device * spi)1388 static int lmk04832_probe(struct spi_device *spi)
1389 {
1390 const struct lmk04832_device_info *info;
1391 int rdbk_pin = RDBK_CLKIN_SEL1;
1392 struct lmk04832 *lmk;
1393 u8 tmp[3];
1394 int ret;
1395 int i;
1396
1397 info = &lmk04832_device_info;
1398
1399 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
1400 if (!lmk)
1401 return -ENOMEM;
1402
1403 lmk->dev = &spi->dev;
1404
1405 lmk->oscin = devm_clk_get_enabled(lmk->dev, "oscin");
1406 if (IS_ERR(lmk->oscin)) {
1407 dev_err(lmk->dev, "failed to get oscin clock\n");
1408 return PTR_ERR(lmk->oscin);
1409 }
1410
1411 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1412 GPIOD_OUT_LOW);
1413
1414 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
1415 sizeof(struct lmk_dclk), GFP_KERNEL);
1416 if (!lmk->dclk) {
1417 ret = -ENOMEM;
1418 return ret;
1419 }
1420
1421 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
1422 sizeof(*lmk->clkout), GFP_KERNEL);
1423 if (!lmk->clkout) {
1424 ret = -ENOMEM;
1425 return ret;
1426 }
1427
1428 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
1429 info->num_channels),
1430 GFP_KERNEL);
1431 if (!lmk->clk_data) {
1432 ret = -ENOMEM;
1433 return ret;
1434 }
1435
1436 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
1437
1438 lmk->sysref_ddly = 8;
1439 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
1440
1441 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
1442 device_property_read_u32(lmk->dev, "ti,sysref-mux",
1443 &lmk->sysref_mux);
1444
1445 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
1446 device_property_read_u32(lmk->dev, "ti,sync-mode",
1447 &lmk->sync_mode);
1448
1449 lmk->sysref_pulse_cnt = 4;
1450 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
1451 &lmk->sysref_pulse_cnt);
1452
1453 for_each_child_of_node_scoped(lmk->dev->of_node, child) {
1454 int reg;
1455
1456 ret = of_property_read_u32(child, "reg", ®);
1457 if (ret) {
1458 dev_err(lmk->dev, "missing reg property in child: %s\n",
1459 child->full_name);
1460 return ret;
1461 }
1462
1463 of_property_read_u32(child, "ti,clkout-fmt",
1464 &lmk->clkout[reg].format);
1465
1466 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
1467 && reg != 8 && reg != 10)
1468 dev_err(lmk->dev, "invalid format for clkout%02d\n",
1469 reg);
1470
1471 lmk->clkout[reg].sysref =
1472 of_property_read_bool(child, "ti,clkout-sysref");
1473 }
1474
1475 lmk->regmap = devm_regmap_init_spi(spi, ®map_config);
1476 if (IS_ERR(lmk->regmap)) {
1477 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
1478
1479 __func__, PTR_ERR(lmk->regmap));
1480 ret = PTR_ERR(lmk->regmap);
1481 return ret;
1482 }
1483
1484 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
1485
1486 if (!(spi->mode & SPI_3WIRE)) {
1487 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
1488 &rdbk_pin);
1489 ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
1490 if (ret)
1491 return ret;
1492 }
1493
1494 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
1495 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
1496 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
1497 tmp[0] << 8 | tmp[1], tmp[2]);
1498 ret = -EINVAL;
1499 return ret;
1500 }
1501
1502 ret = lmk04832_register_vco(lmk);
1503 if (ret) {
1504 dev_err(lmk->dev, "failed to init device clock path\n");
1505 return ret;
1506 }
1507
1508 if (lmk->vco_rate) {
1509 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
1510 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
1511 if (ret) {
1512 dev_err(lmk->dev, "failed to set VCO rate\n");
1513 return ret;
1514 }
1515 }
1516
1517 ret = lmk04832_register_sclk(lmk);
1518 if (ret) {
1519 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
1520 return ret;
1521 }
1522
1523 for (i = 0; i < info->num_channels; i++) {
1524 ret = lmk04832_register_clkout(lmk, i);
1525 if (ret) {
1526 dev_err(lmk->dev, "failed to register clk %d\n", i);
1527 return ret;
1528 }
1529 }
1530
1531 lmk->clk_data->num = info->num_channels;
1532 ret = devm_of_clk_add_hw_provider(lmk->dev, of_clk_hw_onecell_get,
1533 lmk->clk_data);
1534 if (ret) {
1535 dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
1536 return ret;
1537 }
1538
1539 spi_set_drvdata(spi, lmk);
1540
1541 return 0;
1542 }
1543
1544 static const struct spi_device_id lmk04832_id[] = {
1545 { .name = "lmk04832" },
1546 { }
1547 };
1548 MODULE_DEVICE_TABLE(spi, lmk04832_id);
1549
1550 static const struct of_device_id lmk04832_of_id[] = {
1551 { .compatible = "ti,lmk04832" },
1552 {}
1553 };
1554 MODULE_DEVICE_TABLE(of, lmk04832_of_id);
1555
1556 static struct spi_driver lmk04832_driver = {
1557 .driver = {
1558 .name = "lmk04832",
1559 .of_match_table = lmk04832_of_id,
1560 },
1561 .probe = lmk04832_probe,
1562 .id_table = lmk04832_id,
1563 };
1564 module_spi_driver(lmk04832_driver);
1565
1566 MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
1567 MODULE_DESCRIPTION("Texas Instruments LMK04832");
1568 MODULE_LICENSE("GPL v2");
1569