1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * NXP S32G2 SoC family 4 * 5 * Copyright (c) 2021 SUSE LLC 6 * Copyright 2017-2021, 2024-2026 NXP 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "nxp,s32g2"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 scmi_buf: shm@d0000000 { 23 compatible = "arm,scmi-shmem"; 24 reg = <0x0 0xd0000000 0x0 0x80>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&cluster0_l2>; 39 }; 40 41 cpu1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x1>; 45 enable-method = "psci"; 46 next-level-cache = <&cluster0_l2>; 47 }; 48 49 cpu2: cpu@100 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x100>; 53 enable-method = "psci"; 54 next-level-cache = <&cluster1_l2>; 55 }; 56 57 cpu3: cpu@101 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x101>; 61 enable-method = "psci"; 62 next-level-cache = <&cluster1_l2>; 63 }; 64 65 cluster0_l2: l2-cache0 { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 71 cluster1_l2: l2-cache1 { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 }; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 86 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 87 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 88 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 89 }; 90 91 firmware { 92 scmi { 93 compatible = "arm,scmi-smc"; 94 arm,smc-id = <0xc20000fe>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 shmem = <&scmi_buf>; 98 99 clks: protocol@14 { 100 reg = <0x14>; 101 #clock-cells = <1>; 102 }; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 }; 110 111 soc@0 { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0 0 0 0x80000000>; 116 117 rtc0: rtc@40060000 { 118 compatible = "nxp,s32g2-rtc"; 119 reg = <0x40060000 0x1000>; 120 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&clks 54>, <&clks 55>; 122 clock-names = "ipg", "source0"; 123 }; 124 125 pinctrl: pinctrl@4009c240 { 126 compatible = "nxp,s32g2-siul2-pinctrl"; 127 /* MSCR0-MSCR101 registers on siul2_0 */ 128 reg = <0x4009c240 0x198>, 129 /* MSCR112-MSCR122 registers on siul2_1 */ 130 <0x44010400 0x2c>, 131 /* MSCR144-MSCR190 registers on siul2_1 */ 132 <0x44010480 0xbc>, 133 /* IMCR0-IMCR83 registers on siul2_0 */ 134 <0x4009ca40 0x150>, 135 /* IMCR119-IMCR397 registers on siul2_1 */ 136 <0x44010c1c 0x45c>, 137 /* IMCR430-IMCR495 registers on siul2_1 */ 138 <0x440110f8 0x108>; 139 140 jtag_pins: jtag-pins { 141 jtag-grp0 { 142 pinmux = <0x0>; 143 input-enable; 144 bias-pull-up; 145 slew-rate = <166>; 146 }; 147 148 jtag-grp1 { 149 pinmux = <0x11>; 150 slew-rate = <166>; 151 }; 152 153 jtag-grp2 { 154 pinmux = <0x40>; 155 input-enable; 156 bias-pull-down; 157 slew-rate = <166>; 158 }; 159 160 jtag-grp3 { 161 pinmux = <0x23c0>, 162 <0x23d0>, 163 <0x2320>; 164 }; 165 166 jtag-grp4 { 167 pinmux = <0x51>; 168 input-enable; 169 bias-pull-up; 170 slew-rate = <166>; 171 }; 172 }; 173 174 pinctrl_usdhc0: usdhc0grp-pins { 175 usdhc0-grp0 { 176 pinmux = <0x2e1>, 177 <0x381>; 178 output-enable; 179 bias-pull-down; 180 slew-rate = <150>; 181 }; 182 183 usdhc0-grp1 { 184 pinmux = <0x2f1>, 185 <0x301>, 186 <0x311>, 187 <0x321>, 188 <0x331>, 189 <0x341>, 190 <0x351>, 191 <0x361>, 192 <0x371>; 193 output-enable; 194 input-enable; 195 bias-pull-up; 196 slew-rate = <150>; 197 }; 198 199 usdhc0-grp2 { 200 pinmux = <0x391>; 201 output-enable; 202 slew-rate = <150>; 203 }; 204 205 usdhc0-grp3 { 206 pinmux = <0x3a0>; 207 input-enable; 208 slew-rate = <150>; 209 }; 210 211 usdhc0-grp4 { 212 pinmux = <0x2032>, 213 <0x2042>, 214 <0x2052>, 215 <0x2062>, 216 <0x2072>, 217 <0x2082>, 218 <0x2092>, 219 <0x20a2>, 220 <0x20b2>, 221 <0x20c2>; 222 }; 223 }; 224 225 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 226 usdhc0-100mhz-grp0 { 227 pinmux = <0x2e1>, 228 <0x381>; 229 output-enable; 230 bias-pull-down; 231 slew-rate = <150>; 232 }; 233 234 usdhc0-100mhz-grp1 { 235 pinmux = <0x2f1>, 236 <0x301>, 237 <0x311>, 238 <0x321>, 239 <0x331>, 240 <0x341>, 241 <0x351>, 242 <0x361>, 243 <0x371>; 244 output-enable; 245 input-enable; 246 bias-pull-up; 247 slew-rate = <150>; 248 }; 249 250 usdhc0-100mhz-grp2 { 251 pinmux = <0x391>; 252 output-enable; 253 slew-rate = <150>; 254 }; 255 256 usdhc0-100mhz-grp3 { 257 pinmux = <0x3a0>; 258 input-enable; 259 slew-rate = <150>; 260 }; 261 262 usdhc0-100mhz-grp4 { 263 pinmux = <0x2032>, 264 <0x2042>, 265 <0x2052>, 266 <0x2062>, 267 <0x2072>, 268 <0x2082>, 269 <0x2092>, 270 <0x20a2>, 271 <0x20b2>, 272 <0x20c2>; 273 }; 274 }; 275 276 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 277 usdhc0-200mhz-grp0 { 278 pinmux = <0x2e1>, 279 <0x381>; 280 output-enable; 281 bias-pull-down; 282 slew-rate = <208>; 283 }; 284 285 usdhc0-200mhz-grp1 { 286 pinmux = <0x2f1>, 287 <0x301>, 288 <0x311>, 289 <0x321>, 290 <0x331>, 291 <0x341>, 292 <0x351>, 293 <0x361>, 294 <0x371>; 295 output-enable; 296 input-enable; 297 bias-pull-up; 298 slew-rate = <208>; 299 }; 300 301 usdhc0-200mhz-grp2 { 302 pinmux = <0x391>; 303 output-enable; 304 slew-rate = <208>; 305 }; 306 307 usdhc0-200mhz-grp3 { 308 pinmux = <0x3a0>; 309 input-enable; 310 slew-rate = <208>; 311 }; 312 313 usdhc0-200mhz-grp4 { 314 pinmux = <0x2032>, 315 <0x2042>, 316 <0x2052>, 317 <0x2062>, 318 <0x2072>, 319 <0x2082>, 320 <0x2092>, 321 <0x20a2>, 322 <0x20b2>, 323 <0x20c2>; 324 }; 325 }; 326 }; 327 328 ocotp: nvmem@400a4000 { 329 compatible = "nxp,s32g2-ocotp"; 330 reg = <0x400a4000 0x400>; 331 #address-cells = <1>; 332 #size-cells = <1>; 333 }; 334 335 swt0: watchdog@40100000 { 336 compatible = "nxp,s32g2-swt"; 337 reg = <0x40100000 0x1000>; 338 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 339 clock-names = "counter", "module", "register"; 340 status = "disabled"; 341 }; 342 343 swt1: watchdog@40104000 { 344 compatible = "nxp,s32g2-swt"; 345 reg = <0x40104000 0x1000>; 346 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 347 clock-names = "counter", "module", "register"; 348 status = "disabled"; 349 }; 350 351 swt2: watchdog@40108000 { 352 compatible = "nxp,s32g2-swt"; 353 reg = <0x40108000 0x1000>; 354 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 355 clock-names = "counter", "module", "register"; 356 status = "disabled"; 357 }; 358 359 swt3: watchdog@4010c000 { 360 compatible = "nxp,s32g2-swt"; 361 reg = <0x4010c000 0x1000>; 362 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 363 clock-names = "counter", "module", "register"; 364 status = "disabled"; 365 }; 366 367 stm0: timer@4011c000 { 368 compatible = "nxp,s32g2-stm"; 369 reg = <0x4011c000 0x3000>; 370 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 372 clock-names = "counter", "module", "register"; 373 status = "disabled"; 374 }; 375 376 stm1: timer@40120000 { 377 compatible = "nxp,s32g2-stm"; 378 reg = <0x40120000 0x3000>; 379 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 381 clock-names = "counter", "module", "register"; 382 status = "disabled"; 383 }; 384 385 stm2: timer@40124000 { 386 compatible = "nxp,s32g2-stm"; 387 reg = <0x40124000 0x3000>; 388 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 390 clock-names = "counter", "module", "register"; 391 status = "disabled"; 392 }; 393 394 stm3: timer@40128000 { 395 compatible = "nxp,s32g2-stm"; 396 reg = <0x40128000 0x3000>; 397 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 399 clock-names = "counter", "module", "register"; 400 status = "disabled"; 401 }; 402 403 edma0: dma-controller@40144000 { 404 compatible = "nxp,s32g2-edma"; 405 reg = <0x40144000 0x24000>, 406 <0x4012c000 0x3000>, 407 <0x40130000 0x3000>; 408 #dma-cells = <2>; 409 dma-channels = <32>; 410 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "tx-0-15", 414 "tx-16-31", 415 "err"; 416 clocks = <&clks 63>, <&clks 64>; 417 clock-names = "dmamux0", "dmamux1"; 418 }; 419 420 pit0: timer@40188000 { 421 compatible = "nxp,s32g2-pit"; 422 reg = <0x40188000 0x3000>; 423 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&clks 61>; 425 clock-names = "pit"; 426 status = "disabled"; 427 }; 428 429 can0: can@401b4000 { 430 compatible = "nxp,s32g2-flexcan"; 431 reg = <0x401b4000 0xa000>; 432 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-names = "mb-0", "state", "berr", "mb-1"; 437 clocks = <&clks 9>, <&clks 11>; 438 clock-names = "ipg", "per"; 439 status = "disabled"; 440 }; 441 442 can1: can@401be000 { 443 compatible = "nxp,s32g2-flexcan"; 444 reg = <0x401be000 0xa000>; 445 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-names = "mb-0", "state", "berr", "mb-1"; 450 clocks = <&clks 9>, <&clks 11>; 451 clock-names = "ipg", "per"; 452 status = "disabled"; 453 }; 454 455 uart0: serial@401c8000 { 456 compatible = "nxp,s32g2-linflexuart", 457 "fsl,s32v234-linflexuart"; 458 reg = <0x401c8000 0x3000>; 459 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 460 status = "disabled"; 461 }; 462 463 uart1: serial@401cc000 { 464 compatible = "nxp,s32g2-linflexuart", 465 "fsl,s32v234-linflexuart"; 466 reg = <0x401cc000 0x3000>; 467 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 468 status = "disabled"; 469 }; 470 471 usbmisc: usbmisc@44064200 { 472 #index-cells = <1>; 473 compatible = "nxp,s32g2-usbmisc"; 474 reg = <0x44064200 0x200>; 475 }; 476 477 usbotg: usb@44064000 { 478 compatible = "nxp,s32g2-usb"; 479 reg = <0x44064000 0x200>; 480 interrupt-parent = <&gic>; 481 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ 482 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ 483 clocks = <&clks 94>, <&clks 95>; 484 fsl,usbmisc = <&usbmisc 0>; 485 ahb-burst-config = <0x3>; 486 tx-burst-size-dword = <0x10>; 487 rx-burst-size-dword = <0x10>; 488 phy_type = "ulpi"; 489 dr_mode = "host"; 490 maximum-speed = "high-speed"; 491 status = "disabled"; 492 }; 493 494 spi0: spi@401d4000 { 495 compatible = "nxp,s32g2-dspi"; 496 reg = <0x401d4000 0x1000>; 497 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clks 26>; 499 clock-names = "dspi"; 500 spi-num-chipselects = <8>; 501 bus-num = <0>; 502 dmas = <&edma0 0 7>, <&edma0 0 8>; 503 dma-names = "tx", "rx"; 504 status = "disabled"; 505 }; 506 507 spi1: spi@401d8000 { 508 compatible = "nxp,s32g2-dspi"; 509 reg = <0x401d8000 0x1000>; 510 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clks 26>; 512 clock-names = "dspi"; 513 spi-num-chipselects = <5>; 514 bus-num = <1>; 515 dmas = <&edma0 0 10>, <&edma0 0 11>; 516 dma-names = "tx", "rx"; 517 status = "disabled"; 518 }; 519 520 spi2: spi@401dc000 { 521 compatible = "nxp,s32g2-dspi"; 522 reg = <0x401dc000 0x1000>; 523 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clks 26>; 525 clock-names = "dspi"; 526 spi-num-chipselects = <5>; 527 bus-num = <2>; 528 dmas = <&edma0 0 13>, <&edma0 0 14>; 529 dma-names = "tx", "rx"; 530 status = "disabled"; 531 }; 532 533 i2c0: i2c@401e4000 { 534 compatible = "nxp,s32g2-i2c"; 535 reg = <0x401e4000 0x1000>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clks 40>; 540 clock-names = "ipg"; 541 status = "disabled"; 542 }; 543 544 i2c1: i2c@401e8000 { 545 compatible = "nxp,s32g2-i2c"; 546 reg = <0x401e8000 0x1000>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clks 40>; 551 clock-names = "ipg"; 552 status = "disabled"; 553 }; 554 555 i2c2: i2c@401ec000 { 556 compatible = "nxp,s32g2-i2c"; 557 reg = <0x401ec000 0x1000>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&clks 40>; 562 clock-names = "ipg"; 563 status = "disabled"; 564 }; 565 566 pwm0: pwm@401f4000 { 567 compatible = "nxp,s32g2-ftm-pwm"; 568 reg = <0x401f4000 0x1000>; 569 #pwm-cells = <3>; 570 clocks = <&clks 5>, 571 <&clks 6>, 572 <&clks 5>, 573 <&clks 5>; 574 clock-names = "ftm_sys", "ftm_ext", 575 "ftm_fix", "ftm_cnt_clk_en"; 576 status = "disabled"; 577 }; 578 579 adc0: adc@401f8000 { 580 compatible = "nxp,s32g2-sar-adc"; 581 reg = <0x401f8000 0x1000>; 582 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clks 0x41>; 584 dmas = <&edma0 0 32>; 585 dma-names = "rx"; 586 status = "disabled"; 587 }; 588 589 swt4: watchdog@40200000 { 590 compatible = "nxp,s32g2-swt"; 591 reg = <0x40200000 0x1000>; 592 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 593 clock-names = "counter", "module", "register"; 594 status = "disabled"; 595 }; 596 597 swt5: watchdog@40204000 { 598 compatible = "nxp,s32g2-swt"; 599 reg = <0x40204000 0x1000>; 600 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 601 clock-names = "counter", "module", "register"; 602 status = "disabled"; 603 }; 604 605 swt6: watchdog@40208000 { 606 compatible = "nxp,s32g2-swt"; 607 reg = <0x40208000 0x1000>; 608 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; 609 clock-names = "counter", "module", "register"; 610 status = "disabled"; 611 }; 612 613 stm4: timer@4021c000 { 614 compatible = "nxp,s32g2-stm"; 615 reg = <0x4021c000 0x3000>; 616 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 617 clock-names = "counter", "module", "register"; 618 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 619 status = "disabled"; 620 }; 621 622 stm5: timer@40220000 { 623 compatible = "nxp,s32g2-stm"; 624 reg = <0x40220000 0x3000>; 625 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 626 clock-names = "counter", "module", "register"; 627 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 628 status = "disabled"; 629 }; 630 631 stm6: timer@40224000 { 632 compatible = "nxp,s32g2-stm"; 633 reg = <0x40224000 0x3000>; 634 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; 635 clock-names = "counter", "module", "register"; 636 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 637 status = "disabled"; 638 }; 639 640 edma1: dma-controller@40244000 { 641 compatible = "nxp,s32g2-edma"; 642 reg = <0x40244000 0x24000>, 643 <0x4022c000 0x3000>, 644 <0x40230000 0x3000>; 645 #dma-cells = <2>; 646 dma-channels = <32>; 647 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 650 interrupt-names = "tx-0-15", 651 "tx-16-31", 652 "err"; 653 clocks = <&clks 63>, <&clks 64>; 654 clock-names = "dmamux0", "dmamux1"; 655 }; 656 657 pit1: timer@40288000 { 658 compatible = "nxp,s32g2-pit"; 659 reg = <0x40288000 0x3000>; 660 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&clks 61>; 662 clock-names = "pit"; 663 status = "disabled"; 664 }; 665 666 can2: can@402a8000 { 667 compatible = "nxp,s32g2-flexcan"; 668 reg = <0x402a8000 0xa000>; 669 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 673 interrupt-names = "mb-0", "state", "berr", "mb-1"; 674 clocks = <&clks 9>, <&clks 11>; 675 clock-names = "ipg", "per"; 676 status = "disabled"; 677 }; 678 679 can3: can@402b2000 { 680 compatible = "nxp,s32g2-flexcan"; 681 reg = <0x402b2000 0xa000>; 682 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 686 interrupt-names = "mb-0", "state", "berr", "mb-1"; 687 clocks = <&clks 9>, <&clks 11>; 688 clock-names = "ipg", "per"; 689 status = "disabled"; 690 }; 691 692 uart2: serial@402bc000 { 693 compatible = "nxp,s32g2-linflexuart", 694 "fsl,s32v234-linflexuart"; 695 reg = <0x402bc000 0x3000>; 696 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 697 status = "disabled"; 698 }; 699 700 spi3: spi@402c8000 { 701 compatible = "nxp,s32g2-dspi"; 702 reg = <0x402c8000 0x1000>; 703 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clks 26>; 705 clock-names = "dspi"; 706 spi-num-chipselects = <5>; 707 bus-num = <3>; 708 dmas = <&edma0 1 7>, <&edma0 1 8>; 709 dma-names = "tx", "rx"; 710 status = "disabled"; 711 }; 712 713 spi4: spi@402cc000 { 714 compatible = "nxp,s32g2-dspi"; 715 reg = <0x402cc000 0x1000>; 716 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clks 26>; 718 clock-names = "dspi"; 719 spi-num-chipselects = <5>; 720 bus-num = <4>; 721 dmas = <&edma0 1 10>, <&edma0 1 11>; 722 dma-names = "tx", "rx"; 723 status = "disabled"; 724 }; 725 726 spi5: spi@402d0000 { 727 compatible = "nxp,s32g2-dspi"; 728 reg = <0x402d0000 0x1000>; 729 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&clks 26>; 731 clock-names = "dspi"; 732 spi-num-chipselects = <5>; 733 bus-num = <5>; 734 dmas = <&edma0 1 13>, <&edma0 1 14>; 735 dma-names = "tx", "rx"; 736 status = "disabled"; 737 }; 738 739 i2c3: i2c@402d8000 { 740 compatible = "nxp,s32g2-i2c"; 741 reg = <0x402d8000 0x1000>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&clks 40>; 746 clock-names = "ipg"; 747 status = "disabled"; 748 }; 749 750 i2c4: i2c@402dc000 { 751 compatible = "nxp,s32g2-i2c"; 752 reg = <0x402dc000 0x1000>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&clks 40>; 757 clock-names = "ipg"; 758 status = "disabled"; 759 }; 760 761 pwm1: pwm@402e4000 { 762 compatible = "nxp,s32g2-ftm-pwm"; 763 reg = <0x402e4000 0x1000>; 764 #pwm-cells = <3>; 765 clocks = <&clks 7>, 766 <&clks 8>, 767 <&clks 7>, 768 <&clks 7>; 769 clock-names = "ftm_sys", "ftm_ext", 770 "ftm_fix", "ftm_cnt_clk_en"; 771 status = "disabled"; 772 }; 773 774 adc1: adc@402e8000 { 775 compatible = "nxp,s32g2-sar-adc"; 776 reg = <0x402e8000 0x1000>; 777 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&clks 0x41>; 779 dmas = <&edma1 1 32>; 780 dma-names = "rx"; 781 status = "disabled"; 782 }; 783 784 usdhc0: mmc@402f0000 { 785 compatible = "nxp,s32g2-usdhc"; 786 reg = <0x402f0000 0x1000>; 787 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&clks 32>, <&clks 31>, <&clks 33>; 789 clock-names = "ipg", "ahb", "per"; 790 bus-width = <8>; 791 status = "disabled"; 792 }; 793 794 gmac0: ethernet@4033c000 { 795 compatible = "nxp,s32g2-dwmac"; 796 reg = <0x4033c000 0x2000>, /* gmac IP */ 797 <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ 798 interrupt-parent = <&gic>; 799 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "macirq"; 801 snps,mtl-rx-config = <&mtl_rx_setup>; 802 snps,mtl-tx-config = <&mtl_tx_setup>; 803 status = "disabled"; 804 805 mtl_rx_setup: rx-queues-config { 806 snps,rx-queues-to-use = <5>; 807 808 queue0 { 809 }; 810 811 queue1 { 812 }; 813 814 queue2 { 815 }; 816 817 queue3 { 818 }; 819 820 queue4 { 821 }; 822 }; 823 824 mtl_tx_setup: tx-queues-config { 825 snps,tx-queues-to-use = <5>; 826 827 queue0 { 828 }; 829 830 queue1 { 831 }; 832 833 queue2 { 834 }; 835 836 queue3 { 837 }; 838 839 queue4 { 840 }; 841 }; 842 843 gmac0mdio: mdio { 844 compatible = "snps,dwmac-mdio"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 }; 848 }; 849 850 gic: interrupt-controller@50800000 { 851 compatible = "arm,gic-v3"; 852 reg = <0x50800000 0x10000>, 853 <0x50880000 0x80000>, 854 <0x50400000 0x2000>, 855 <0x50410000 0x2000>, 856 <0x50420000 0x2000>; 857 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 858 interrupt-controller; 859 #interrupt-cells = <3>; 860 }; 861 }; 862}; 863