1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-sm8450.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sm8450-camcc.h> 11#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 12#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 13#include <dt-bindings/clock/qcom,sm8450-videocc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/interconnect/qcom,icc.h> 22#include <dt-bindings/interconnect/qcom,sm8450.h> 23#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <76800000>; 42 }; 43 44 sleep_clk: sleep-clk { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <32764>; 48 }; 49 }; 50 51 cpus { 52 #address-cells = <2>; 53 #size-cells = <0>; 54 55 cpu0: cpu@0 { 56 device_type = "cpu"; 57 compatible = "qcom,kryo780"; 58 reg = <0x0 0x0>; 59 enable-method = "psci"; 60 next-level-cache = <&l2_0>; 61 power-domains = <&cpu_pd0>; 62 power-domain-names = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 #cooling-cells = <2>; 65 clocks = <&cpufreq_hw 0>; 66 l2_0: l2-cache { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 next-level-cache = <&l3_0>; 71 l3_0: l3-cache { 72 compatible = "cache"; 73 cache-level = <3>; 74 cache-unified; 75 }; 76 }; 77 }; 78 79 cpu1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo780"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 next-level-cache = <&l2_100>; 85 power-domains = <&cpu_pd1>; 86 power-domain-names = "psci"; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 #cooling-cells = <2>; 89 clocks = <&cpufreq_hw 0>; 90 l2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo780"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_200>; 104 power-domains = <&cpu_pd2>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 #cooling-cells = <2>; 108 clocks = <&cpufreq_hw 0>; 109 l2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&l3_0>; 114 }; 115 }; 116 117 cpu3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo780"; 120 reg = <0x0 0x300>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_300>; 123 power-domains = <&cpu_pd3>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 #cooling-cells = <2>; 127 clocks = <&cpufreq_hw 0>; 128 l2_300: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 next-level-cache = <&l3_0>; 133 }; 134 }; 135 136 cpu4: cpu@400 { 137 device_type = "cpu"; 138 compatible = "qcom,kryo780"; 139 reg = <0x0 0x400>; 140 enable-method = "psci"; 141 next-level-cache = <&l2_400>; 142 power-domains = <&cpu_pd4>; 143 power-domain-names = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 #cooling-cells = <2>; 146 clocks = <&cpufreq_hw 1>; 147 l2_400: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 next-level-cache = <&l3_0>; 152 }; 153 }; 154 155 cpu5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo780"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 next-level-cache = <&l2_500>; 161 power-domains = <&cpu_pd5>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 #cooling-cells = <2>; 165 clocks = <&cpufreq_hw 1>; 166 l2_500: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 cache-unified; 170 next-level-cache = <&l3_0>; 171 }; 172 }; 173 174 cpu6: cpu@600 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo780"; 177 reg = <0x0 0x600>; 178 enable-method = "psci"; 179 next-level-cache = <&l2_600>; 180 power-domains = <&cpu_pd6>; 181 power-domain-names = "psci"; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 #cooling-cells = <2>; 184 clocks = <&cpufreq_hw 1>; 185 l2_600: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&l3_0>; 190 }; 191 }; 192 193 cpu7: cpu@700 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo780"; 196 reg = <0x0 0x700>; 197 enable-method = "psci"; 198 next-level-cache = <&l2_700>; 199 power-domains = <&cpu_pd7>; 200 power-domain-names = "psci"; 201 qcom,freq-domain = <&cpufreq_hw 2>; 202 #cooling-cells = <2>; 203 clocks = <&cpufreq_hw 2>; 204 l2_700: l2-cache { 205 compatible = "cache"; 206 cache-level = <2>; 207 cache-unified; 208 next-level-cache = <&l3_0>; 209 }; 210 }; 211 212 cpu-map { 213 cluster0 { 214 core0 { 215 cpu = <&cpu0>; 216 }; 217 218 core1 { 219 cpu = <&cpu1>; 220 }; 221 222 core2 { 223 cpu = <&cpu2>; 224 }; 225 226 core3 { 227 cpu = <&cpu3>; 228 }; 229 230 core4 { 231 cpu = <&cpu4>; 232 }; 233 234 core5 { 235 cpu = <&cpu5>; 236 }; 237 238 core6 { 239 cpu = <&cpu6>; 240 }; 241 242 core7 { 243 cpu = <&cpu7>; 244 }; 245 }; 246 }; 247 248 idle-states { 249 entry-method = "psci"; 250 251 little_cpu_sleep_0: cpu-sleep-0-0 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "silver-rail-power-collapse"; 254 arm,psci-suspend-param = <0x40000004>; 255 entry-latency-us = <800>; 256 exit-latency-us = <750>; 257 min-residency-us = <4090>; 258 local-timer-stop; 259 }; 260 261 big_cpu_sleep_0: cpu-sleep-1-0 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "gold-rail-power-collapse"; 264 arm,psci-suspend-param = <0x40000004>; 265 entry-latency-us = <600>; 266 exit-latency-us = <1550>; 267 min-residency-us = <4791>; 268 local-timer-stop; 269 }; 270 }; 271 272 domain-idle-states { 273 cluster_sleep_0: cluster-sleep-0 { 274 compatible = "domain-idle-state"; 275 arm,psci-suspend-param = <0x41000044>; 276 entry-latency-us = <1050>; 277 exit-latency-us = <2500>; 278 min-residency-us = <5309>; 279 }; 280 281 cluster_sleep_1: cluster-sleep-1 { 282 compatible = "domain-idle-state"; 283 arm,psci-suspend-param = <0x4100c344>; 284 entry-latency-us = <2700>; 285 exit-latency-us = <3500>; 286 min-residency-us = <13959>; 287 }; 288 }; 289 }; 290 291 ete-0 { 292 compatible = "arm,embedded-trace-extension"; 293 cpu = <&cpu0>; 294 295 out-ports { 296 port { 297 ete0_out_funnel_ete: endpoint { 298 remote-endpoint = <&funnel_ete_in_ete0>; 299 }; 300 }; 301 }; 302 }; 303 304 ete-1 { 305 compatible = "arm,embedded-trace-extension"; 306 cpu = <&cpu1>; 307 308 out-ports { 309 port { 310 ete1_out_funnel_ete: endpoint { 311 remote-endpoint = <&funnel_ete_in_ete1>; 312 }; 313 }; 314 }; 315 }; 316 317 ete-2 { 318 compatible = "arm,embedded-trace-extension"; 319 cpu = <&cpu2>; 320 321 out-ports { 322 port { 323 ete2_out_funnel_ete: endpoint { 324 remote-endpoint = <&funnel_ete_in_ete2>; 325 }; 326 }; 327 }; 328 }; 329 330 ete-3 { 331 compatible = "arm,embedded-trace-extension"; 332 cpu = <&cpu3>; 333 334 out-ports { 335 port { 336 ete3_out_funnel_ete: endpoint { 337 remote-endpoint = <&funnel_ete_in_ete3>; 338 }; 339 }; 340 }; 341 }; 342 343 ete-4 { 344 compatible = "arm,embedded-trace-extension"; 345 cpu = <&cpu4>; 346 347 out-ports { 348 port { 349 ete4_out_funnel_ete: endpoint { 350 remote-endpoint = <&funnel_ete_in_ete4>; 351 }; 352 }; 353 }; 354 }; 355 356 ete-5 { 357 compatible = "arm,embedded-trace-extension"; 358 cpu = <&cpu5>; 359 360 out-ports { 361 port { 362 ete5_out_funnel_ete: endpoint { 363 remote-endpoint = <&funnel_ete_in_ete5>; 364 }; 365 }; 366 }; 367 }; 368 369 ete-6 { 370 compatible = "arm,embedded-trace-extension"; 371 cpu = <&cpu6>; 372 373 out-ports { 374 port { 375 ete6_out_funnel_ete: endpoint { 376 remote-endpoint = <&funnel_ete_in_ete6>; 377 }; 378 }; 379 }; 380 }; 381 382 ete-7 { 383 compatible = "arm,embedded-trace-extension"; 384 cpu = <&cpu7>; 385 386 out-ports { 387 port { 388 ete7_out_funnel_ete: endpoint { 389 remote-endpoint = <&funnel_ete_in_ete7>; 390 }; 391 }; 392 }; 393 }; 394 395 funnel-ete { 396 compatible = "arm,coresight-static-funnel"; 397 398 out-ports { 399 port { 400 funnel_ete_out_funnel_apss: endpoint { 401 remote-endpoint = 402 <&funnel_apss_in_funnel_ete>; 403 }; 404 }; 405 }; 406 407 in-ports { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 411 port@0 { 412 reg = <0>; 413 funnel_ete_in_ete0: endpoint { 414 remote-endpoint = 415 <&ete0_out_funnel_ete>; 416 }; 417 }; 418 419 port@1 { 420 reg = <1>; 421 funnel_ete_in_ete1: endpoint { 422 remote-endpoint = 423 <&ete1_out_funnel_ete>; 424 }; 425 }; 426 427 port@2 { 428 reg = <2>; 429 funnel_ete_in_ete2: endpoint { 430 remote-endpoint = 431 <&ete2_out_funnel_ete>; 432 }; 433 }; 434 435 port@3 { 436 reg = <3>; 437 funnel_ete_in_ete3: endpoint { 438 remote-endpoint = 439 <&ete3_out_funnel_ete>; 440 }; 441 }; 442 443 port@4 { 444 reg = <4>; 445 funnel_ete_in_ete4: endpoint { 446 remote-endpoint = 447 <&ete4_out_funnel_ete>; 448 }; 449 }; 450 451 port@5 { 452 reg = <5>; 453 funnel_ete_in_ete5: endpoint { 454 remote-endpoint = 455 <&ete5_out_funnel_ete>; 456 }; 457 }; 458 459 port@6 { 460 reg = <6>; 461 funnel_ete_in_ete6: endpoint { 462 remote-endpoint = 463 <&ete6_out_funnel_ete>; 464 }; 465 }; 466 467 port@7 { 468 reg = <7>; 469 funnel_ete_in_ete7: endpoint { 470 remote-endpoint = 471 <&ete7_out_funnel_ete>; 472 }; 473 }; 474 }; 475 }; 476 477 firmware { 478 scm: scm { 479 compatible = "qcom,scm-sm8450", "qcom,scm"; 480 qcom,dload-mode = <&tcsr 0x13000>; 481 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 482 #reset-cells = <1>; 483 }; 484 }; 485 486 clk_virt: interconnect-0 { 487 compatible = "qcom,sm8450-clk-virt"; 488 #interconnect-cells = <2>; 489 qcom,bcm-voters = <&apps_bcm_voter>; 490 }; 491 492 mc_virt: interconnect-1 { 493 compatible = "qcom,sm8450-mc-virt"; 494 #interconnect-cells = <2>; 495 qcom,bcm-voters = <&apps_bcm_voter>; 496 }; 497 498 memory@a0000000 { 499 device_type = "memory"; 500 /* We expect the bootloader to fill in the size */ 501 reg = <0x0 0xa0000000 0x0 0x0>; 502 }; 503 504 pmu { 505 compatible = "arm,armv8-pmuv3"; 506 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 507 }; 508 509 psci { 510 compatible = "arm,psci-1.0"; 511 method = "smc"; 512 513 cpu_pd0: power-domain-cpu0 { 514 #power-domain-cells = <0>; 515 power-domains = <&cluster_pd>; 516 domain-idle-states = <&little_cpu_sleep_0>; 517 }; 518 519 cpu_pd1: power-domain-cpu1 { 520 #power-domain-cells = <0>; 521 power-domains = <&cluster_pd>; 522 domain-idle-states = <&little_cpu_sleep_0>; 523 }; 524 525 cpu_pd2: power-domain-cpu2 { 526 #power-domain-cells = <0>; 527 power-domains = <&cluster_pd>; 528 domain-idle-states = <&little_cpu_sleep_0>; 529 }; 530 531 cpu_pd3: power-domain-cpu3 { 532 #power-domain-cells = <0>; 533 power-domains = <&cluster_pd>; 534 domain-idle-states = <&little_cpu_sleep_0>; 535 }; 536 537 cpu_pd4: power-domain-cpu4 { 538 #power-domain-cells = <0>; 539 power-domains = <&cluster_pd>; 540 domain-idle-states = <&big_cpu_sleep_0>; 541 }; 542 543 cpu_pd5: power-domain-cpu5 { 544 #power-domain-cells = <0>; 545 power-domains = <&cluster_pd>; 546 domain-idle-states = <&big_cpu_sleep_0>; 547 }; 548 549 cpu_pd6: power-domain-cpu6 { 550 #power-domain-cells = <0>; 551 power-domains = <&cluster_pd>; 552 domain-idle-states = <&big_cpu_sleep_0>; 553 }; 554 555 cpu_pd7: power-domain-cpu7 { 556 #power-domain-cells = <0>; 557 power-domains = <&cluster_pd>; 558 domain-idle-states = <&big_cpu_sleep_0>; 559 }; 560 561 cluster_pd: power-domain-cpu-cluster0 { 562 #power-domain-cells = <0>; 563 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 564 }; 565 }; 566 567 qup_opp_table_100mhz: opp-table-qup { 568 compatible = "operating-points-v2"; 569 570 opp-50000000 { 571 opp-hz = /bits/ 64 <50000000>; 572 required-opps = <&rpmhpd_opp_min_svs>; 573 }; 574 575 opp-75000000 { 576 opp-hz = /bits/ 64 <75000000>; 577 required-opps = <&rpmhpd_opp_low_svs>; 578 }; 579 580 opp-100000000 { 581 opp-hz = /bits/ 64 <100000000>; 582 required-opps = <&rpmhpd_opp_svs>; 583 }; 584 }; 585 586 reserved_memory: reserved-memory { 587 #address-cells = <2>; 588 #size-cells = <2>; 589 ranges; 590 591 hyp_mem: memory@80000000 { 592 reg = <0x0 0x80000000 0x0 0x600000>; 593 no-map; 594 }; 595 596 xbl_dt_log_mem: memory@80600000 { 597 reg = <0x0 0x80600000 0x0 0x40000>; 598 no-map; 599 }; 600 601 xbl_ramdump_mem: memory@80640000 { 602 reg = <0x0 0x80640000 0x0 0x180000>; 603 no-map; 604 }; 605 606 xbl_sc_mem: memory@807c0000 { 607 reg = <0x0 0x807c0000 0x0 0x40000>; 608 no-map; 609 }; 610 611 aop_image_mem: memory@80800000 { 612 reg = <0x0 0x80800000 0x0 0x60000>; 613 no-map; 614 }; 615 616 aop_cmd_db_mem: memory@80860000 { 617 compatible = "qcom,cmd-db"; 618 reg = <0x0 0x80860000 0x0 0x20000>; 619 no-map; 620 }; 621 622 aop_config_mem: memory@80880000 { 623 reg = <0x0 0x80880000 0x0 0x20000>; 624 no-map; 625 }; 626 627 tme_crash_dump_mem: memory@808a0000 { 628 reg = <0x0 0x808a0000 0x0 0x40000>; 629 no-map; 630 }; 631 632 tme_log_mem: memory@808e0000 { 633 reg = <0x0 0x808e0000 0x0 0x4000>; 634 no-map; 635 }; 636 637 uefi_log_mem: memory@808e4000 { 638 reg = <0x0 0x808e4000 0x0 0x10000>; 639 no-map; 640 }; 641 642 /* secdata region can be reused by apps */ 643 smem: memory@80900000 { 644 compatible = "qcom,smem"; 645 reg = <0x0 0x80900000 0x0 0x200000>; 646 hwlocks = <&tcsr_mutex 3>; 647 no-map; 648 }; 649 650 cpucp_fw_mem: memory@80b00000 { 651 reg = <0x0 0x80b00000 0x0 0x100000>; 652 no-map; 653 }; 654 655 cdsp_secure_heap: memory@80c00000 { 656 reg = <0x0 0x80c00000 0x0 0x4600000>; 657 no-map; 658 }; 659 660 video_mem: memory@85700000 { 661 reg = <0x0 0x85700000 0x0 0x700000>; 662 no-map; 663 }; 664 665 adsp_mem: memory@85e00000 { 666 reg = <0x0 0x85e00000 0x0 0x2100000>; 667 no-map; 668 }; 669 670 slpi_mem: memory@88000000 { 671 reg = <0x0 0x88000000 0x0 0x1900000>; 672 no-map; 673 }; 674 675 cdsp_mem: memory@89900000 { 676 reg = <0x0 0x89900000 0x0 0x2000000>; 677 no-map; 678 }; 679 680 ipa_fw_mem: memory@8b900000 { 681 reg = <0x0 0x8b900000 0x0 0x10000>; 682 no-map; 683 }; 684 685 ipa_gsi_mem: memory@8b910000 { 686 reg = <0x0 0x8b910000 0x0 0xa000>; 687 no-map; 688 }; 689 690 gpu_micro_code_mem: memory@8b91a000 { 691 reg = <0x0 0x8b91a000 0x0 0x2000>; 692 no-map; 693 }; 694 695 spss_region_mem: memory@8ba00000 { 696 reg = <0x0 0x8ba00000 0x0 0x180000>; 697 no-map; 698 }; 699 700 /* First part of the "SPU secure shared memory" region */ 701 spu_tz_shared_mem: memory@8bb80000 { 702 reg = <0x0 0x8bb80000 0x0 0x60000>; 703 no-map; 704 }; 705 706 /* Second part of the "SPU secure shared memory" region */ 707 spu_modem_shared_mem: memory@8bbe0000 { 708 reg = <0x0 0x8bbe0000 0x0 0x20000>; 709 no-map; 710 }; 711 712 mpss_mem: memory@8bc00000 { 713 reg = <0x0 0x8bc00000 0x0 0x13200000>; 714 no-map; 715 }; 716 717 cvp_mem: memory@9ee00000 { 718 reg = <0x0 0x9ee00000 0x0 0x700000>; 719 no-map; 720 }; 721 722 camera_mem: memory@9f500000 { 723 reg = <0x0 0x9f500000 0x0 0x800000>; 724 no-map; 725 }; 726 727 rmtfs_mem: memory@9fd00000 { 728 compatible = "qcom,rmtfs-mem"; 729 reg = <0x0 0x9fd00000 0x0 0x280000>; 730 no-map; 731 732 qcom,client-id = <1>; 733 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 734 }; 735 736 xbl_sc_mem2: memory@a6e00000 { 737 reg = <0x0 0xa6e00000 0x0 0x40000>; 738 no-map; 739 }; 740 741 global_sync_mem: memory@a6f00000 { 742 reg = <0x0 0xa6f00000 0x0 0x100000>; 743 no-map; 744 }; 745 746 /* uefi region can be reused by APPS */ 747 748 /* Linux kernel image is loaded at 0xa0000000 */ 749 750 oem_vm_mem: memory@bb000000 { 751 reg = <0x0 0xbb000000 0x0 0x5000000>; 752 no-map; 753 }; 754 755 mte_mem: memory@c0000000 { 756 reg = <0x0 0xc0000000 0x0 0x20000000>; 757 no-map; 758 }; 759 760 qheebsp_reserved_mem: memory@e0000000 { 761 reg = <0x0 0xe0000000 0x0 0x600000>; 762 no-map; 763 }; 764 765 cpusys_vm_mem: memory@e0600000 { 766 reg = <0x0 0xe0600000 0x0 0x400000>; 767 no-map; 768 }; 769 770 hyp_reserved_mem: memory@e0a00000 { 771 reg = <0x0 0xe0a00000 0x0 0x100000>; 772 no-map; 773 }; 774 775 trust_ui_vm_mem: memory@e0b00000 { 776 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 777 no-map; 778 }; 779 780 trust_ui_vm_qrtr: memory@e55f3000 { 781 reg = <0x0 0xe55f3000 0x0 0x9000>; 782 no-map; 783 }; 784 785 trust_ui_vm_vblk0_ring: memory@e55fc000 { 786 reg = <0x0 0xe55fc000 0x0 0x4000>; 787 no-map; 788 }; 789 790 trust_ui_vm_swiotlb: memory@e5600000 { 791 reg = <0x0 0xe5600000 0x0 0x100000>; 792 no-map; 793 }; 794 795 tz_stat_mem: memory@e8800000 { 796 reg = <0x0 0xe8800000 0x0 0x100000>; 797 no-map; 798 }; 799 800 tags_mem: memory@e8900000 { 801 reg = <0x0 0xe8900000 0x0 0x1200000>; 802 no-map; 803 }; 804 805 qtee_mem: memory@e9b00000 { 806 reg = <0x0 0xe9b00000 0x0 0x500000>; 807 no-map; 808 }; 809 810 trusted_apps_mem: memory@ea000000 { 811 reg = <0x0 0xea000000 0x0 0x3900000>; 812 no-map; 813 }; 814 815 trusted_apps_ext_mem: memory@ed900000 { 816 reg = <0x0 0xed900000 0x0 0x3b00000>; 817 no-map; 818 }; 819 }; 820 821 smp2p-adsp { 822 compatible = "qcom,smp2p"; 823 qcom,smem = <443>, <429>; 824 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 825 IPCC_MPROC_SIGNAL_SMP2P 826 IRQ_TYPE_EDGE_RISING>; 827 mboxes = <&ipcc IPCC_CLIENT_LPASS 828 IPCC_MPROC_SIGNAL_SMP2P>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <2>; 832 833 smp2p_adsp_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 smp2p_adsp_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 interrupt-controller; 841 #interrupt-cells = <2>; 842 }; 843 }; 844 845 smp2p-cdsp { 846 compatible = "qcom,smp2p"; 847 qcom,smem = <94>, <432>; 848 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 849 IPCC_MPROC_SIGNAL_SMP2P 850 IRQ_TYPE_EDGE_RISING>; 851 mboxes = <&ipcc IPCC_CLIENT_CDSP 852 IPCC_MPROC_SIGNAL_SMP2P>; 853 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <5>; 856 857 smp2p_cdsp_out: master-kernel { 858 qcom,entry-name = "master-kernel"; 859 #qcom,smem-state-cells = <1>; 860 }; 861 862 smp2p_cdsp_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 interrupt-controller; 865 #interrupt-cells = <2>; 866 }; 867 }; 868 869 smp2p-modem { 870 compatible = "qcom,smp2p"; 871 qcom,smem = <435>, <428>; 872 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 873 IPCC_MPROC_SIGNAL_SMP2P 874 IRQ_TYPE_EDGE_RISING>; 875 mboxes = <&ipcc IPCC_CLIENT_MPSS 876 IPCC_MPROC_SIGNAL_SMP2P>; 877 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <1>; 880 881 smp2p_modem_out: master-kernel { 882 qcom,entry-name = "master-kernel"; 883 #qcom,smem-state-cells = <1>; 884 }; 885 886 smp2p_modem_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 }; 891 892 ipa_smp2p_out: ipa-ap-to-modem { 893 qcom,entry-name = "ipa"; 894 #qcom,smem-state-cells = <1>; 895 }; 896 897 ipa_smp2p_in: ipa-modem-to-ap { 898 qcom,entry-name = "ipa"; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 }; 902 }; 903 904 smp2p-slpi { 905 compatible = "qcom,smp2p"; 906 qcom,smem = <481>, <430>; 907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 908 IPCC_MPROC_SIGNAL_SMP2P 909 IRQ_TYPE_EDGE_RISING>; 910 mboxes = <&ipcc IPCC_CLIENT_SLPI 911 IPCC_MPROC_SIGNAL_SMP2P>; 912 913 qcom,local-pid = <0>; 914 qcom,remote-pid = <3>; 915 916 smp2p_slpi_out: master-kernel { 917 qcom,entry-name = "master-kernel"; 918 #qcom,smem-state-cells = <1>; 919 }; 920 921 smp2p_slpi_in: slave-kernel { 922 qcom,entry-name = "slave-kernel"; 923 interrupt-controller; 924 #interrupt-cells = <2>; 925 }; 926 }; 927 928 soc: soc@0 { 929 #address-cells = <2>; 930 #size-cells = <2>; 931 ranges = <0 0 0 0 0x10 0>; 932 dma-ranges = <0 0 0 0 0x10 0>; 933 compatible = "simple-bus"; 934 935 gcc: clock-controller@100000 { 936 compatible = "qcom,gcc-sm8450"; 937 reg = <0x0 0x00100000 0x0 0x1f4200>; 938 #clock-cells = <1>; 939 #reset-cells = <1>; 940 #power-domain-cells = <1>; 941 clocks = <&rpmhcc RPMH_CXO_CLK>, 942 <&sleep_clk>, 943 <&pcie0_phy>, 944 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 945 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 946 <&ufs_mem_phy 0>, 947 <&ufs_mem_phy 1>, 948 <&ufs_mem_phy 2>, 949 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 950 clock-names = "bi_tcxo", 951 "sleep_clk", 952 "pcie_0_pipe_clk", 953 "pcie_1_pipe_clk", 954 "pcie_1_phy_aux_clk", 955 "ufs_phy_rx_symbol_0_clk", 956 "ufs_phy_rx_symbol_1_clk", 957 "ufs_phy_tx_symbol_0_clk", 958 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 959 }; 960 961 gpi_dma2: dma-controller@800000 { 962 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 963 #dma-cells = <3>; 964 reg = <0 0x00800000 0 0x60000>; 965 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 977 dma-channels = <12>; 978 dma-channel-mask = <0x7e>; 979 iommus = <&apps_smmu 0x496 0x0>; 980 status = "disabled"; 981 }; 982 983 qupv3_id_2: geniqup@8c0000 { 984 compatible = "qcom,geni-se-qup"; 985 reg = <0x0 0x008c0000 0x0 0x2000>; 986 clock-names = "m-ahb", "s-ahb"; 987 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 988 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 989 iommus = <&apps_smmu 0x483 0x0>; 990 #address-cells = <2>; 991 #size-cells = <2>; 992 ranges; 993 status = "disabled"; 994 995 i2c15: i2c@880000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0x0 0x00880000 0x0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c15_data_clk>; 1002 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1006 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1007 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1009 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1010 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1011 dma-names = "tx", "rx"; 1012 status = "disabled"; 1013 }; 1014 1015 spi15: spi@880000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0x0 0x00880000 0x0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1020 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1024 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1025 interconnect-names = "qup-core", "qup-config"; 1026 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1027 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1028 dma-names = "tx", "rx"; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 i2c16: i2c@884000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0x0 0x00884000 0x0 0x4000>; 1037 clock-names = "se"; 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_i2c16_data_clk>; 1041 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1045 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1046 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1048 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1049 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 status = "disabled"; 1052 }; 1053 1054 spi16: spi@884000 { 1055 compatible = "qcom,geni-spi"; 1056 reg = <0x0 0x00884000 0x0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1059 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 1062 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1063 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1064 interconnect-names = "qup-core", "qup-config"; 1065 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1066 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1067 dma-names = "tx", "rx"; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 status = "disabled"; 1071 }; 1072 1073 i2c17: i2c@888000 { 1074 compatible = "qcom,geni-i2c"; 1075 reg = <0x0 0x00888000 0x0 0x4000>; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&qup_i2c17_data_clk>; 1080 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1085 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 status = "disabled"; 1091 }; 1092 1093 spi17: spi@888000 { 1094 compatible = "qcom,geni-spi"; 1095 reg = <0x0 0x00888000 0x0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1098 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1102 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1103 interconnect-names = "qup-core", "qup-config"; 1104 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1105 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1106 dma-names = "tx", "rx"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 i2c18: i2c@88c000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0x0 0x0088c000 0x0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c18_data_clk>; 1119 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1123 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1124 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1126 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1127 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1128 dma-names = "tx", "rx"; 1129 status = "disabled"; 1130 }; 1131 1132 spi18: spi@88c000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x0088c000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1137 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1141 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1144 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1145 dma-names = "tx", "rx"; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 status = "disabled"; 1149 }; 1150 1151 i2c19: i2c@890000 { 1152 compatible = "qcom,geni-i2c"; 1153 reg = <0x0 0x00890000 0x0 0x4000>; 1154 clock-names = "se"; 1155 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_i2c19_data_clk>; 1158 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1162 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1163 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1164 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1165 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 status = "disabled"; 1169 }; 1170 1171 spi19: spi@890000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x00890000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1180 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1183 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1184 dma-names = "tx", "rx"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c20: i2c@894000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0x0 0x00894000 0x0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_i2c20_data_clk>; 1197 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1201 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1202 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1203 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1204 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1205 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1206 dma-names = "tx", "rx"; 1207 status = "disabled"; 1208 }; 1209 1210 uart20: serial@894000 { 1211 compatible = "qcom,geni-uart"; 1212 reg = <0 0x00894000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_uart20_default>; 1217 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1219 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1220 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1221 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1222 interconnect-names = "qup-core", 1223 "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 spi20: spi@894000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0 0x00894000 0 0x4000>; 1230 clock-names = "se"; 1231 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1232 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1235 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1236 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1237 interconnect-names = "qup-core", "qup-config"; 1238 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1239 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1240 dma-names = "tx", "rx"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c21: i2c@898000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0x0 0x00898000 0x0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c21_data_clk>; 1253 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1257 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1258 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1259 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1260 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1261 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 spi21: spi@898000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00898000 0 0x4000>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1271 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1275 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1276 interconnect-names = "qup-core", "qup-config"; 1277 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1278 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1279 dma-names = "tx", "rx"; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 }; 1285 1286 gpi_dma0: dma-controller@900000 { 1287 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1288 #dma-cells = <3>; 1289 reg = <0 0x00900000 0 0x60000>; 1290 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1302 dma-channels = <12>; 1303 dma-channel-mask = <0x7e>; 1304 iommus = <&apps_smmu 0x5b6 0x0>; 1305 status = "disabled"; 1306 }; 1307 1308 qupv3_id_0: geniqup@9c0000 { 1309 compatible = "qcom,geni-se-qup"; 1310 reg = <0x0 0x009c0000 0x0 0x2000>; 1311 clock-names = "m-ahb", "s-ahb"; 1312 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1313 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1314 iommus = <&apps_smmu 0x5a3 0x0>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1316 interconnect-names = "qup-core"; 1317 #address-cells = <2>; 1318 #size-cells = <2>; 1319 ranges; 1320 status = "disabled"; 1321 1322 i2c0: i2c@980000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0x0 0x00980000 0x0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c0_data_clk>; 1329 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1333 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1334 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1335 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1336 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1337 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1338 dma-names = "tx", "rx"; 1339 status = "disabled"; 1340 }; 1341 1342 spi0: spi@980000 { 1343 compatible = "qcom,geni-spi"; 1344 reg = <0x0 0x00980000 0x0 0x4000>; 1345 clock-names = "se"; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1347 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1350 power-domains = <&rpmhpd RPMHPD_CX>; 1351 operating-points-v2 = <&qup_opp_table_100mhz>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1354 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1357 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1358 dma-names = "tx", "rx"; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 i2c1: i2c@984000 { 1365 compatible = "qcom,geni-i2c"; 1366 reg = <0x0 0x00984000 0x0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_i2c1_data_clk>; 1371 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1375 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1377 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1378 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1379 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1380 dma-names = "tx", "rx"; 1381 status = "disabled"; 1382 }; 1383 1384 spi1: spi@984000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0x0 0x00984000 0x0 0x4000>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1389 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1394 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1395 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1396 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1397 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1398 dma-names = "tx", "rx"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 i2c2: i2c@988000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0x0 0x00988000 0x0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c2_data_clk>; 1411 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1415 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1416 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1419 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1420 dma-names = "tx", "rx"; 1421 status = "disabled"; 1422 }; 1423 1424 spi2: spi@988000 { 1425 compatible = "qcom,geni-spi"; 1426 reg = <0x0 0x00988000 0x0 0x4000>; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1429 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1433 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1434 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1436 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 status = "disabled"; 1442 }; 1443 1444 1445 i2c3: i2c@98c000 { 1446 compatible = "qcom,geni-i2c"; 1447 reg = <0x0 0x0098c000 0x0 0x4000>; 1448 clock-names = "se"; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_i2c3_data_clk>; 1452 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1456 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1457 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1458 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1459 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1460 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1461 dma-names = "tx", "rx"; 1462 status = "disabled"; 1463 }; 1464 1465 spi3: spi@98c000 { 1466 compatible = "qcom,geni-spi"; 1467 reg = <0x0 0x0098c000 0x0 0x4000>; 1468 clock-names = "se"; 1469 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1470 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1474 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1475 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1478 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1479 dma-names = "tx", "rx"; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 status = "disabled"; 1483 }; 1484 1485 i2c4: i2c@990000 { 1486 compatible = "qcom,geni-i2c"; 1487 reg = <0x0 0x00990000 0x0 0x4000>; 1488 clock-names = "se"; 1489 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1490 pinctrl-names = "default"; 1491 pinctrl-0 = <&qup_i2c4_data_clk>; 1492 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1496 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1497 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1500 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1501 dma-names = "tx", "rx"; 1502 status = "disabled"; 1503 }; 1504 1505 spi4: spi@990000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0x0 0x00990000 0x0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1510 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1513 power-domains = <&rpmhpd RPMHPD_CX>; 1514 operating-points-v2 = <&qup_opp_table_100mhz>; 1515 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1516 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1517 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1518 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1520 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1521 dma-names = "tx", "rx"; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 i2c5: i2c@994000 { 1528 compatible = "qcom,geni-i2c"; 1529 reg = <0x0 0x00994000 0x0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_i2c5_data_clk>; 1534 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1538 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1539 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1542 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1543 dma-names = "tx", "rx"; 1544 status = "disabled"; 1545 }; 1546 1547 spi5: spi@994000 { 1548 compatible = "qcom,geni-spi"; 1549 reg = <0x0 0x00994000 0x0 0x4000>; 1550 clock-names = "se"; 1551 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1552 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1553 pinctrl-names = "default"; 1554 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1555 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1556 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1557 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1558 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1559 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1560 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1561 dma-names = "tx", "rx"; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 status = "disabled"; 1565 }; 1566 1567 1568 i2c6: i2c@998000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0x0 0x00998000 0x0 0x4000>; 1571 clock-names = "se"; 1572 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c6_data_clk>; 1575 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1579 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1580 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1582 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1583 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1584 dma-names = "tx", "rx"; 1585 status = "disabled"; 1586 }; 1587 1588 spi6: spi@998000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0x0 0x00998000 0x0 0x4000>; 1591 clock-names = "se"; 1592 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1593 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1597 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1598 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1599 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1600 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1601 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1602 dma-names = "tx", "rx"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 uart7: serial@99c000 { 1609 compatible = "qcom,geni-debug-uart"; 1610 reg = <0 0x0099c000 0 0x4000>; 1611 clock-names = "se"; 1612 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1613 pinctrl-names = "default"; 1614 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1615 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1616 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1617 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1618 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1619 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1620 interconnect-names = "qup-core", 1621 "qup-config"; 1622 status = "disabled"; 1623 }; 1624 }; 1625 1626 gpi_dma1: dma-controller@a00000 { 1627 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1628 #dma-cells = <3>; 1629 reg = <0 0x00a00000 0 0x60000>; 1630 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1642 dma-channels = <12>; 1643 dma-channel-mask = <0x7e>; 1644 iommus = <&apps_smmu 0x56 0x0>; 1645 status = "disabled"; 1646 }; 1647 1648 qupv3_id_1: geniqup@ac0000 { 1649 compatible = "qcom,geni-se-qup"; 1650 reg = <0x0 0x00ac0000 0x0 0x6000>; 1651 clock-names = "m-ahb", "s-ahb"; 1652 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1653 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1654 iommus = <&apps_smmu 0x43 0x0>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1656 interconnect-names = "qup-core"; 1657 #address-cells = <2>; 1658 #size-cells = <2>; 1659 ranges; 1660 status = "disabled"; 1661 1662 i2c8: i2c@a80000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0x0 0x00a80000 0x0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c8_data_clk>; 1669 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1673 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1674 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1675 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1676 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1677 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1678 dma-names = "tx", "rx"; 1679 status = "disabled"; 1680 }; 1681 1682 spi8: spi@a80000 { 1683 compatible = "qcom,geni-spi"; 1684 reg = <0x0 0x00a80000 0x0 0x4000>; 1685 clock-names = "se"; 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1687 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1688 pinctrl-names = "default"; 1689 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1690 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1691 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1692 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1693 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1694 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1695 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1696 dma-names = "tx", "rx"; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 status = "disabled"; 1700 }; 1701 1702 i2c9: i2c@a84000 { 1703 compatible = "qcom,geni-i2c"; 1704 reg = <0x0 0x00a84000 0x0 0x4000>; 1705 clock-names = "se"; 1706 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1707 pinctrl-names = "default"; 1708 pinctrl-0 = <&qup_i2c9_data_clk>; 1709 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1713 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1714 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1715 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1716 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1717 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1718 dma-names = "tx", "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 spi9: spi@a84000 { 1723 compatible = "qcom,geni-spi"; 1724 reg = <0x0 0x00a84000 0x0 0x4000>; 1725 clock-names = "se"; 1726 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1727 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1728 pinctrl-names = "default"; 1729 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1731 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1732 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1733 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1734 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1735 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1736 dma-names = "tx", "rx"; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 i2c10: i2c@a88000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0x0 0x00a88000 0x0 0x4000>; 1745 clock-names = "se"; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c10_data_clk>; 1749 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1757 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1758 dma-names = "tx", "rx"; 1759 status = "disabled"; 1760 }; 1761 1762 spi10: spi@a88000 { 1763 compatible = "qcom,geni-spi"; 1764 reg = <0x0 0x00a88000 0x0 0x4000>; 1765 clock-names = "se"; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1767 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1770 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1771 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1772 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1773 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1774 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1775 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1776 dma-names = "tx", "rx"; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 i2c11: i2c@a8c000 { 1783 compatible = "qcom,geni-i2c"; 1784 reg = <0x0 0x00a8c000 0x0 0x4000>; 1785 clock-names = "se"; 1786 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&qup_i2c11_data_clk>; 1789 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1793 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1794 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1795 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1796 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1797 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1798 dma-names = "tx", "rx"; 1799 status = "disabled"; 1800 }; 1801 1802 spi11: spi@a8c000 { 1803 compatible = "qcom,geni-spi"; 1804 reg = <0x0 0x00a8c000 0x0 0x4000>; 1805 clock-names = "se"; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1807 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1811 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1813 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1814 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1815 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1816 dma-names = "tx", "rx"; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 status = "disabled"; 1820 }; 1821 1822 i2c12: i2c@a90000 { 1823 compatible = "qcom,geni-i2c"; 1824 reg = <0x0 0x00a90000 0x0 0x4000>; 1825 clock-names = "se"; 1826 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1827 pinctrl-names = "default"; 1828 pinctrl-0 = <&qup_i2c12_data_clk>; 1829 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1833 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1834 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1835 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1836 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1837 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 spi12: spi@a90000 { 1843 compatible = "qcom,geni-spi"; 1844 reg = <0x0 0x00a90000 0x0 0x4000>; 1845 clock-names = "se"; 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1847 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1851 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1852 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1853 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1854 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1855 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1856 dma-names = "tx", "rx"; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 i2c13: i2c@a94000 { 1863 compatible = "qcom,geni-i2c"; 1864 reg = <0 0x00a94000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_i2c13_data_clk>; 1869 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1874 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1875 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1876 dma-names = "tx", "rx"; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 status = "disabled"; 1880 }; 1881 1882 spi13: spi@a94000 { 1883 compatible = "qcom,geni-spi"; 1884 reg = <0x0 0x00a94000 0x0 0x4000>; 1885 clock-names = "se"; 1886 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1887 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1888 pinctrl-names = "default"; 1889 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1890 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1891 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1892 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1894 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1896 dma-names = "tx", "rx"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 status = "disabled"; 1900 }; 1901 1902 i2c14: i2c@a98000 { 1903 compatible = "qcom,geni-i2c"; 1904 reg = <0 0x00a98000 0 0x4000>; 1905 clock-names = "se"; 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_i2c14_data_clk>; 1909 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1911 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1912 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1913 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1914 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1915 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1916 dma-names = "tx", "rx"; 1917 #address-cells = <1>; 1918 #size-cells = <0>; 1919 status = "disabled"; 1920 }; 1921 1922 spi14: spi@a98000 { 1923 compatible = "qcom,geni-spi"; 1924 reg = <0x0 0x00a98000 0x0 0x4000>; 1925 clock-names = "se"; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1927 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1928 pinctrl-names = "default"; 1929 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1931 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1932 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1933 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1934 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1935 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1936 dma-names = "tx", "rx"; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 status = "disabled"; 1940 }; 1941 }; 1942 1943 rng: rng@10c3000 { 1944 compatible = "qcom,sm8450-trng", "qcom,trng"; 1945 reg = <0 0x010c3000 0 0x1000>; 1946 }; 1947 1948 pcie0: pcie@1c00000 { 1949 compatible = "qcom,pcie-sm8450-pcie0"; 1950 reg = <0 0x01c00000 0 0x3000>, 1951 <0 0x60000000 0 0xf1d>, 1952 <0 0x60000f20 0 0xa8>, 1953 <0 0x60001000 0 0x1000>, 1954 <0 0x60100000 0 0x100000>; 1955 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1956 device_type = "pci"; 1957 linux,pci-domain = <0>; 1958 bus-range = <0x00 0xff>; 1959 num-lanes = <1>; 1960 1961 #address-cells = <3>; 1962 #size-cells = <2>; 1963 1964 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1966 1967 msi-map = <0x0 &gic_its 0x5980 0x1>, 1968 <0x100 &gic_its 0x5981 0x1>; 1969 msi-map-mask = <0xff00>; 1970 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1979 interrupt-names = "msi0", 1980 "msi1", 1981 "msi2", 1982 "msi3", 1983 "msi4", 1984 "msi5", 1985 "msi6", 1986 "msi7", 1987 "global"; 1988 #interrupt-cells = <1>; 1989 interrupt-map-mask = <0 0 0 0x7>; 1990 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1991 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1992 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1993 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1994 1995 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1996 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1997 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1998 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1999 interconnect-names = "pcie-mem", "cpu-pcie"; 2000 2001 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2002 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2003 <&pcie0_phy>, 2004 <&rpmhcc RPMH_CXO_CLK>, 2005 <&gcc GCC_PCIE_0_AUX_CLK>, 2006 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2007 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2008 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2009 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2010 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2011 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2012 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2013 clock-names = "pipe", 2014 "pipe_mux", 2015 "phy_pipe", 2016 "ref", 2017 "aux", 2018 "cfg", 2019 "bus_master", 2020 "bus_slave", 2021 "slave_q2a", 2022 "ddrss_sf_tbu", 2023 "aggre0", 2024 "aggre1"; 2025 2026 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2027 <0x100 &apps_smmu 0x1c01 0x1>; 2028 2029 resets = <&gcc GCC_PCIE_0_BCR>; 2030 reset-names = "pci"; 2031 2032 power-domains = <&gcc PCIE_0_GDSC>; 2033 2034 phys = <&pcie0_phy>; 2035 phy-names = "pciephy"; 2036 2037 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 2038 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 2039 2040 pinctrl-names = "default"; 2041 pinctrl-0 = <&pcie0_default_state>; 2042 2043 operating-points-v2 = <&pcie0_opp_table>; 2044 2045 status = "disabled"; 2046 2047 pcie0_opp_table: opp-table { 2048 compatible = "operating-points-v2"; 2049 2050 /* 2.5 GT/s x1 */ 2051 opp-2500000 { 2052 opp-hz = /bits/ 64 <2500000>; 2053 required-opps = <&rpmhpd_opp_low_svs>; 2054 opp-peak-kBps = <250000 1>; 2055 opp-level = <1>; 2056 }; 2057 2058 /* 5 GT/s x1 */ 2059 opp-5000000 { 2060 opp-hz = /bits/ 64 <5000000>; 2061 required-opps = <&rpmhpd_opp_low_svs>; 2062 opp-peak-kBps = <500000 1>; 2063 opp-level = <2>; 2064 }; 2065 2066 /* 8 GT/s x1 */ 2067 opp-8000000 { 2068 opp-hz = /bits/ 64 <8000000>; 2069 required-opps = <&rpmhpd_opp_nom>; 2070 opp-peak-kBps = <984500 1>; 2071 opp-level = <3>; 2072 }; 2073 }; 2074 2075 pcieport0: pcie@0 { 2076 device_type = "pci"; 2077 reg = <0x0 0x0 0x0 0x0 0x0>; 2078 bus-range = <0x01 0xff>; 2079 2080 #address-cells = <3>; 2081 #size-cells = <2>; 2082 ranges; 2083 }; 2084 }; 2085 2086 pcie0_phy: phy@1c06000 { 2087 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 2088 reg = <0 0x01c06000 0 0x2000>; 2089 2090 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2091 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2092 <&gcc GCC_PCIE_0_CLKREF_EN>, 2093 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2094 <&gcc GCC_PCIE_0_PIPE_CLK>; 2095 clock-names = "aux", 2096 "cfg_ahb", 2097 "ref", 2098 "rchng", 2099 "pipe"; 2100 2101 clock-output-names = "pcie_0_pipe_clk"; 2102 #clock-cells = <0>; 2103 2104 #phy-cells = <0>; 2105 2106 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2107 reset-names = "phy"; 2108 2109 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2110 assigned-clock-rates = <100000000>; 2111 2112 status = "disabled"; 2113 }; 2114 2115 pcie1: pcie@1c08000 { 2116 compatible = "qcom,pcie-sm8450-pcie1"; 2117 reg = <0 0x01c08000 0 0x3000>, 2118 <0 0x40000000 0 0xf1d>, 2119 <0 0x40000f20 0 0xa8>, 2120 <0 0x40001000 0 0x1000>, 2121 <0 0x40100000 0 0x100000>; 2122 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2123 device_type = "pci"; 2124 linux,pci-domain = <1>; 2125 bus-range = <0x00 0xff>; 2126 num-lanes = <2>; 2127 2128 #address-cells = <3>; 2129 #size-cells = <2>; 2130 2131 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2132 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2133 2134 msi-map = <0x0 &gic_its 0x5a00 0x1>, 2135 <0x100 &gic_its 0x5a01 0x1>; 2136 msi-map-mask = <0xff00>; 2137 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2146 interrupt-names = "msi0", 2147 "msi1", 2148 "msi2", 2149 "msi3", 2150 "msi4", 2151 "msi5", 2152 "msi6", 2153 "msi7", 2154 "global"; 2155 #interrupt-cells = <1>; 2156 interrupt-map-mask = <0 0 0 0x7>; 2157 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2158 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2159 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2160 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2161 2162 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2163 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2164 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2165 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2166 interconnect-names = "pcie-mem", "cpu-pcie"; 2167 2168 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2169 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2170 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 2171 <&rpmhcc RPMH_CXO_CLK>, 2172 <&gcc GCC_PCIE_1_AUX_CLK>, 2173 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2174 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2175 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2176 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2177 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2178 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2179 clock-names = "pipe", 2180 "pipe_mux", 2181 "phy_pipe", 2182 "ref", 2183 "aux", 2184 "cfg", 2185 "bus_master", 2186 "bus_slave", 2187 "slave_q2a", 2188 "ddrss_sf_tbu", 2189 "aggre1"; 2190 2191 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2192 <0x100 &apps_smmu 0x1c81 0x1>; 2193 2194 resets = <&gcc GCC_PCIE_1_BCR>; 2195 reset-names = "pci"; 2196 2197 power-domains = <&gcc PCIE_1_GDSC>; 2198 2199 phys = <&pcie1_phy>; 2200 phy-names = "pciephy"; 2201 2202 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 2203 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 2204 2205 pinctrl-names = "default"; 2206 pinctrl-0 = <&pcie1_default_state>; 2207 2208 operating-points-v2 = <&pcie1_opp_table>; 2209 2210 status = "disabled"; 2211 2212 pcie1_opp_table: opp-table { 2213 compatible = "operating-points-v2"; 2214 2215 /* 2.5 GT/s x1 */ 2216 opp-2500000-1 { 2217 opp-hz = /bits/ 64 <2500000>; 2218 required-opps = <&rpmhpd_opp_low_svs>; 2219 opp-peak-kBps = <250000 1>; 2220 opp-level = <1>; 2221 }; 2222 2223 /* 2.5 GT/s x2 */ 2224 opp-5000000-1 { 2225 opp-hz = /bits/ 64 <5000000>; 2226 required-opps = <&rpmhpd_opp_low_svs>; 2227 opp-peak-kBps = <500000 1>; 2228 opp-level = <1>; 2229 }; 2230 2231 /* 5 GT/s x1 */ 2232 opp-5000000-2 { 2233 opp-hz = /bits/ 64 <5000000>; 2234 required-opps = <&rpmhpd_opp_low_svs>; 2235 opp-peak-kBps = <500000 1>; 2236 opp-level = <2>; 2237 }; 2238 2239 /* 5 GT/s x2 */ 2240 opp-10000000-2 { 2241 opp-hz = /bits/ 64 <10000000>; 2242 required-opps = <&rpmhpd_opp_low_svs>; 2243 opp-peak-kBps = <1000000 1>; 2244 opp-level = <2>; 2245 }; 2246 2247 /* 8 GT/s x1 */ 2248 opp-8000000-3 { 2249 opp-hz = /bits/ 64 <8000000>; 2250 required-opps = <&rpmhpd_opp_nom>; 2251 opp-peak-kBps = <984500 1>; 2252 opp-level = <3>; 2253 }; 2254 2255 /* 8 GT/s x2 */ 2256 opp-16000000-3 { 2257 opp-hz = /bits/ 64 <16000000>; 2258 required-opps = <&rpmhpd_opp_nom>; 2259 opp-peak-kBps = <1969000 1>; 2260 opp-level = <3>; 2261 }; 2262 2263 /* 16 GT/s x1 */ 2264 opp-16000000-4 { 2265 opp-hz = /bits/ 64 <16000000>; 2266 required-opps = <&rpmhpd_opp_nom>; 2267 opp-peak-kBps = <1969000 1>; 2268 opp-level = <4>; 2269 }; 2270 2271 /* 16 GT/s x2 */ 2272 opp-32000000-4 { 2273 opp-hz = /bits/ 64 <32000000>; 2274 required-opps = <&rpmhpd_opp_nom>; 2275 opp-peak-kBps = <3938000 1>; 2276 opp-level = <4>; 2277 }; 2278 }; 2279 2280 pcie@0 { 2281 device_type = "pci"; 2282 reg = <0x0 0x0 0x0 0x0 0x0>; 2283 bus-range = <0x01 0xff>; 2284 2285 #address-cells = <3>; 2286 #size-cells = <2>; 2287 ranges; 2288 }; 2289 }; 2290 2291 pcie1_ep: pcie-ep@1c08000 { 2292 compatible = "qcom,sm8450-pcie-ep"; 2293 reg = <0x0 0x01c08000 0x0 0x3000>, 2294 <0x0 0x40000000 0x0 0xf1d>, 2295 <0x0 0x40000f20 0x0 0xa8>, 2296 <0x0 0x40001000 0x0 0x1000>, 2297 <0x0 0x40200000 0x0 0x1000000>, 2298 <0x0 0x01c0b000 0x0 0x1000>, 2299 <0x0 0x40002000 0x0 0x1000>; 2300 reg-names = "parf", 2301 "dbi", 2302 "elbi", 2303 "atu", 2304 "addr_space", 2305 "mmio", 2306 "dma"; 2307 2308 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2309 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2310 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2311 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2312 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2313 <&rpmhcc RPMH_CXO_CLK>, 2314 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2315 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2316 clock-names = "aux", 2317 "cfg", 2318 "bus_master", 2319 "bus_slave", 2320 "slave_q2a", 2321 "ref", 2322 "ddrss_sf_tbu", 2323 "aggre_noc_axi"; 2324 2325 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2326 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 2327 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2328 interrupt-names = "global", 2329 "doorbell", 2330 "dma"; 2331 2332 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2333 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2334 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2335 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2336 interconnect-names = "pcie-mem", 2337 "cpu-pcie"; 2338 2339 iommus = <&apps_smmu 0x1c80 0x7f>; 2340 resets = <&gcc GCC_PCIE_1_BCR>; 2341 reset-names = "core"; 2342 power-domains = <&gcc PCIE_1_GDSC>; 2343 phys = <&pcie1_phy>; 2344 phy-names = "pciephy"; 2345 num-lanes = <2>; 2346 2347 pinctrl-names = "default"; 2348 pinctrl-0 = <&pcie1_default_state>; 2349 2350 status = "disabled"; 2351 }; 2352 2353 pcie1_phy: phy@1c0e000 { 2354 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 2355 reg = <0 0x01c0e000 0 0x2000>; 2356 2357 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2358 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2359 <&gcc GCC_PCIE_1_CLKREF_EN>, 2360 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2361 <&gcc GCC_PCIE_1_PIPE_CLK>; 2362 clock-names = "aux", 2363 "cfg_ahb", 2364 "ref", 2365 "rchng", 2366 "pipe"; 2367 2368 clock-output-names = "pcie_1_pipe_clk"; 2369 #clock-cells = <1>; 2370 2371 #phy-cells = <0>; 2372 2373 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2374 reset-names = "phy"; 2375 2376 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2377 assigned-clock-rates = <100000000>; 2378 2379 status = "disabled"; 2380 }; 2381 2382 config_noc: interconnect@1500000 { 2383 compatible = "qcom,sm8450-config-noc"; 2384 reg = <0 0x01500000 0 0x1c000>; 2385 #interconnect-cells = <2>; 2386 qcom,bcm-voters = <&apps_bcm_voter>; 2387 }; 2388 2389 system_noc: interconnect@1680000 { 2390 compatible = "qcom,sm8450-system-noc"; 2391 reg = <0 0x01680000 0 0x1e200>; 2392 #interconnect-cells = <2>; 2393 qcom,bcm-voters = <&apps_bcm_voter>; 2394 }; 2395 2396 pcie_noc: interconnect@16c0000 { 2397 compatible = "qcom,sm8450-pcie-anoc"; 2398 reg = <0 0x016c0000 0 0xe280>; 2399 #interconnect-cells = <2>; 2400 qcom,bcm-voters = <&apps_bcm_voter>; 2401 }; 2402 2403 aggre1_noc: interconnect@16e0000 { 2404 compatible = "qcom,sm8450-aggre1-noc"; 2405 reg = <0 0x016e0000 0 0x1c080>; 2406 #interconnect-cells = <2>; 2407 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2408 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2409 qcom,bcm-voters = <&apps_bcm_voter>; 2410 }; 2411 2412 aggre2_noc: interconnect@1700000 { 2413 compatible = "qcom,sm8450-aggre2-noc"; 2414 reg = <0 0x01700000 0 0x31080>; 2415 #interconnect-cells = <2>; 2416 qcom,bcm-voters = <&apps_bcm_voter>; 2417 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2418 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2419 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2420 <&rpmhcc RPMH_IPA_CLK>; 2421 }; 2422 2423 mmss_noc: interconnect@1740000 { 2424 compatible = "qcom,sm8450-mmss-noc"; 2425 reg = <0 0x01740000 0 0x1f080>; 2426 #interconnect-cells = <2>; 2427 qcom,bcm-voters = <&apps_bcm_voter>; 2428 }; 2429 2430 tcsr_mutex: hwlock@1f40000 { 2431 compatible = "qcom,tcsr-mutex"; 2432 reg = <0x0 0x01f40000 0x0 0x40000>; 2433 #hwlock-cells = <1>; 2434 }; 2435 2436 tcsr: syscon@1fc0000 { 2437 compatible = "qcom,sm8450-tcsr", "syscon"; 2438 reg = <0x0 0x1fc0000 0x0 0x30000>; 2439 }; 2440 2441 gpu: gpu@3d00000 { 2442 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2443 reg = <0x0 0x03d00000 0x0 0x40000>, 2444 <0x0 0x03d9e000 0x0 0x1000>, 2445 <0x0 0x03d61000 0x0 0x800>; 2446 reg-names = "kgsl_3d0_reg_memory", 2447 "cx_mem", 2448 "cx_dbgc"; 2449 2450 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2451 2452 iommus = <&adreno_smmu 0 0x400>, 2453 <&adreno_smmu 1 0x400>; 2454 2455 operating-points-v2 = <&gpu_opp_table>; 2456 2457 qcom,gmu = <&gmu>; 2458 #cooling-cells = <2>; 2459 2460 status = "disabled"; 2461 2462 gpu_zap_shader: zap-shader { 2463 memory-region = <&gpu_micro_code_mem>; 2464 }; 2465 2466 gpu_opp_table: opp-table { 2467 compatible = "operating-points-v2"; 2468 2469 opp-818000000 { 2470 opp-hz = /bits/ 64 <818000000>; 2471 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2472 }; 2473 2474 opp-791000000 { 2475 opp-hz = /bits/ 64 <791000000>; 2476 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2477 }; 2478 2479 opp-734000000 { 2480 opp-hz = /bits/ 64 <734000000>; 2481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2482 }; 2483 2484 opp-640000000 { 2485 opp-hz = /bits/ 64 <640000000>; 2486 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2487 }; 2488 2489 opp-599000000 { 2490 opp-hz = /bits/ 64 <599000000>; 2491 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2492 }; 2493 2494 opp-545000000 { 2495 opp-hz = /bits/ 64 <545000000>; 2496 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2497 }; 2498 2499 opp-492000000 { 2500 opp-hz = /bits/ 64 <492000000>; 2501 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2502 }; 2503 2504 opp-421000000 { 2505 opp-hz = /bits/ 64 <421000000>; 2506 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2507 }; 2508 2509 opp-350000000 { 2510 opp-hz = /bits/ 64 <350000000>; 2511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2512 }; 2513 2514 opp-317000000 { 2515 opp-hz = /bits/ 64 <317000000>; 2516 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2517 }; 2518 2519 opp-285000000 { 2520 opp-hz = /bits/ 64 <285000000>; 2521 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2522 }; 2523 2524 opp-220000000 { 2525 opp-hz = /bits/ 64 <220000000>; 2526 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2527 }; 2528 }; 2529 }; 2530 2531 gmu: gmu@3d6a000 { 2532 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2533 reg = <0x0 0x03d6a000 0x0 0x35000>, 2534 <0x0 0x03d50000 0x0 0x10000>, 2535 <0x0 0x0b290000 0x0 0x10000>; 2536 reg-names = "gmu", "rscc", "gmu_pdc"; 2537 2538 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2540 interrupt-names = "hfi", "gmu"; 2541 2542 clocks = <&gpucc GPU_CC_AHB_CLK>, 2543 <&gpucc GPU_CC_CX_GMU_CLK>, 2544 <&gpucc GPU_CC_CXO_CLK>, 2545 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2546 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2547 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2548 <&gpucc GPU_CC_DEMET_CLK>; 2549 clock-names = "ahb", 2550 "gmu", 2551 "cxo", 2552 "axi", 2553 "memnoc", 2554 "hub", 2555 "demet"; 2556 2557 power-domains = <&gpucc GPU_CX_GDSC>, 2558 <&gpucc GPU_GX_GDSC>; 2559 power-domain-names = "cx", 2560 "gx"; 2561 2562 iommus = <&adreno_smmu 5 0x400>; 2563 2564 qcom,qmp = <&aoss_qmp>; 2565 2566 operating-points-v2 = <&gmu_opp_table>; 2567 2568 gmu_opp_table: opp-table { 2569 compatible = "operating-points-v2"; 2570 2571 opp-500000000 { 2572 opp-hz = /bits/ 64 <500000000>; 2573 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2574 }; 2575 2576 opp-200000000 { 2577 opp-hz = /bits/ 64 <200000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2579 }; 2580 }; 2581 }; 2582 2583 gpucc: clock-controller@3d90000 { 2584 compatible = "qcom,sm8450-gpucc"; 2585 reg = <0x0 0x03d90000 0x0 0xa000>; 2586 clocks = <&rpmhcc RPMH_CXO_CLK>, 2587 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2588 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2589 #clock-cells = <1>; 2590 #reset-cells = <1>; 2591 #power-domain-cells = <1>; 2592 }; 2593 2594 adreno_smmu: iommu@3da0000 { 2595 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2596 "qcom,smmu-500", "arm,mmu-500"; 2597 reg = <0x0 0x03da0000 0x0 0x40000>; 2598 #iommu-cells = <2>; 2599 #global-interrupts = <1>; 2600 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2618 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2619 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2620 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2622 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2623 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2625 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2626 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2627 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2628 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2629 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2630 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2631 <&gpucc GPU_CC_AHB_CLK>; 2632 clock-names = "gmu", 2633 "hub", 2634 "hlos", 2635 "bus", 2636 "iface", 2637 "ahb"; 2638 power-domains = <&gpucc GPU_CX_GDSC>; 2639 dma-coherent; 2640 }; 2641 2642 usb_1_hsphy: phy@88e3000 { 2643 compatible = "qcom,sm8450-usb-hs-phy", 2644 "qcom,usb-snps-hs-7nm-phy"; 2645 reg = <0 0x088e3000 0 0x400>; 2646 status = "disabled"; 2647 #phy-cells = <0>; 2648 2649 clocks = <&rpmhcc RPMH_CXO_CLK>; 2650 clock-names = "ref"; 2651 2652 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2653 }; 2654 2655 usb_1_qmpphy: phy@88e8000 { 2656 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2657 reg = <0 0x088e8000 0 0x3000>; 2658 2659 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2660 <&rpmhcc RPMH_CXO_CLK>, 2661 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2662 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2663 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2664 2665 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2666 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2667 reset-names = "phy", "common"; 2668 2669 #clock-cells = <1>; 2670 #phy-cells = <1>; 2671 2672 orientation-switch; 2673 2674 status = "disabled"; 2675 2676 ports { 2677 #address-cells = <1>; 2678 #size-cells = <0>; 2679 2680 port@0 { 2681 reg = <0>; 2682 2683 usb_1_qmpphy_out: endpoint { 2684 }; 2685 }; 2686 2687 port@1 { 2688 reg = <1>; 2689 2690 usb_1_qmpphy_usb_ss_in: endpoint { 2691 remote-endpoint = <&usb_1_dwc3_ss>; 2692 }; 2693 }; 2694 2695 port@2 { 2696 reg = <2>; 2697 2698 usb_1_qmpphy_dp_in: endpoint { 2699 remote-endpoint = <&mdss_dp0_out>; 2700 }; 2701 }; 2702 }; 2703 }; 2704 2705 remoteproc_slpi: remoteproc@2400000 { 2706 compatible = "qcom,sm8450-slpi-pas"; 2707 reg = <0 0x02400000 0 0x4000>; 2708 2709 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2710 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2711 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2712 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2713 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2714 interrupt-names = "wdog", "fatal", "ready", 2715 "handover", "stop-ack"; 2716 2717 clocks = <&rpmhcc RPMH_CXO_CLK>; 2718 clock-names = "xo"; 2719 2720 power-domains = <&rpmhpd RPMHPD_LCX>, 2721 <&rpmhpd RPMHPD_LMX>; 2722 power-domain-names = "lcx", "lmx"; 2723 2724 memory-region = <&slpi_mem>; 2725 2726 qcom,qmp = <&aoss_qmp>; 2727 2728 qcom,smem-states = <&smp2p_slpi_out 0>; 2729 qcom,smem-state-names = "stop"; 2730 2731 status = "disabled"; 2732 2733 glink-edge { 2734 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2735 IPCC_MPROC_SIGNAL_GLINK_QMP 2736 IRQ_TYPE_EDGE_RISING>; 2737 mboxes = <&ipcc IPCC_CLIENT_SLPI 2738 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2739 2740 label = "slpi"; 2741 qcom,remote-pid = <3>; 2742 2743 fastrpc { 2744 compatible = "qcom,fastrpc"; 2745 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2746 label = "sdsp"; 2747 qcom,non-secure-domain; 2748 #address-cells = <1>; 2749 #size-cells = <0>; 2750 2751 compute-cb@1 { 2752 compatible = "qcom,fastrpc-compute-cb"; 2753 reg = <1>; 2754 iommus = <&apps_smmu 0x0541 0x0>; 2755 }; 2756 2757 compute-cb@2 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <2>; 2760 iommus = <&apps_smmu 0x0542 0x0>; 2761 }; 2762 2763 compute-cb@3 { 2764 compatible = "qcom,fastrpc-compute-cb"; 2765 reg = <3>; 2766 iommus = <&apps_smmu 0x0543 0x0>; 2767 /* note: shared-cb = <4> in downstream */ 2768 }; 2769 }; 2770 }; 2771 }; 2772 2773 remoteproc_adsp: remoteproc@3000000 { 2774 compatible = "qcom,sm8450-adsp-pas"; 2775 reg = <0x0 0x03000000 0x0 0x10000>; 2776 2777 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2778 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2779 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2780 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2781 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2782 interrupt-names = "wdog", "fatal", "ready", 2783 "handover", "stop-ack"; 2784 2785 clocks = <&rpmhcc RPMH_CXO_CLK>; 2786 clock-names = "xo"; 2787 2788 power-domains = <&rpmhpd RPMHPD_LCX>, 2789 <&rpmhpd RPMHPD_LMX>; 2790 power-domain-names = "lcx", "lmx"; 2791 2792 memory-region = <&adsp_mem>; 2793 2794 qcom,qmp = <&aoss_qmp>; 2795 2796 qcom,smem-states = <&smp2p_adsp_out 0>; 2797 qcom,smem-state-names = "stop"; 2798 2799 status = "disabled"; 2800 2801 remoteproc_adsp_glink: glink-edge { 2802 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2803 IPCC_MPROC_SIGNAL_GLINK_QMP 2804 IRQ_TYPE_EDGE_RISING>; 2805 mboxes = <&ipcc IPCC_CLIENT_LPASS 2806 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2807 2808 label = "lpass"; 2809 qcom,remote-pid = <2>; 2810 2811 gpr { 2812 compatible = "qcom,gpr"; 2813 qcom,glink-channels = "adsp_apps"; 2814 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2815 qcom,intents = <512 20>; 2816 #address-cells = <1>; 2817 #size-cells = <0>; 2818 2819 q6apm: service@1 { 2820 compatible = "qcom,q6apm"; 2821 reg = <GPR_APM_MODULE_IID>; 2822 #sound-dai-cells = <0>; 2823 qcom,protection-domain = "avs/audio", 2824 "msm/adsp/audio_pd"; 2825 2826 q6apmdai: dais { 2827 compatible = "qcom,q6apm-dais"; 2828 iommus = <&apps_smmu 0x1801 0x0>; 2829 }; 2830 2831 q6apmbedai: bedais { 2832 compatible = "qcom,q6apm-lpass-dais"; 2833 #sound-dai-cells = <1>; 2834 }; 2835 }; 2836 2837 q6prm: service@2 { 2838 compatible = "qcom,q6prm"; 2839 reg = <GPR_PRM_MODULE_IID>; 2840 qcom,protection-domain = "avs/audio", 2841 "msm/adsp/audio_pd"; 2842 2843 q6prmcc: clock-controller { 2844 compatible = "qcom,q6prm-lpass-clocks"; 2845 #clock-cells = <2>; 2846 }; 2847 }; 2848 }; 2849 2850 fastrpc { 2851 compatible = "qcom,fastrpc"; 2852 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2853 label = "adsp"; 2854 qcom,non-secure-domain; 2855 #address-cells = <1>; 2856 #size-cells = <0>; 2857 2858 compute-cb@3 { 2859 compatible = "qcom,fastrpc-compute-cb"; 2860 reg = <3>; 2861 iommus = <&apps_smmu 0x1803 0x0>; 2862 }; 2863 2864 compute-cb@4 { 2865 compatible = "qcom,fastrpc-compute-cb"; 2866 reg = <4>; 2867 iommus = <&apps_smmu 0x1804 0x0>; 2868 }; 2869 2870 compute-cb@5 { 2871 compatible = "qcom,fastrpc-compute-cb"; 2872 reg = <5>; 2873 iommus = <&apps_smmu 0x1805 0x0>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 wsa2macro: codec@31e0000 { 2880 compatible = "qcom,sm8450-lpass-wsa-macro"; 2881 reg = <0 0x031e0000 0 0x1000>; 2882 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2883 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2884 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2885 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2886 <&vamacro>; 2887 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2888 2889 #clock-cells = <0>; 2890 clock-output-names = "wsa2-mclk"; 2891 #sound-dai-cells = <1>; 2892 }; 2893 2894 swr4: soundwire@31f0000 { 2895 compatible = "qcom,soundwire-v1.7.0"; 2896 reg = <0 0x031f0000 0 0x2000>; 2897 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2898 clocks = <&wsa2macro>; 2899 clock-names = "iface"; 2900 label = "WSA2"; 2901 2902 pinctrl-0 = <&wsa2_swr_active>; 2903 pinctrl-names = "default"; 2904 2905 qcom,din-ports = <2>; 2906 qcom,dout-ports = <6>; 2907 2908 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2909 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2910 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2911 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2912 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2913 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2914 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2915 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2916 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2917 2918 #address-cells = <2>; 2919 #size-cells = <0>; 2920 #sound-dai-cells = <1>; 2921 status = "disabled"; 2922 }; 2923 2924 rxmacro: codec@3200000 { 2925 compatible = "qcom,sm8450-lpass-rx-macro"; 2926 reg = <0 0x03200000 0 0x1000>; 2927 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2928 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2929 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2930 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2931 <&vamacro>; 2932 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2933 2934 #clock-cells = <0>; 2935 clock-output-names = "mclk"; 2936 #sound-dai-cells = <1>; 2937 }; 2938 2939 swr1: soundwire@3210000 { 2940 compatible = "qcom,soundwire-v1.7.0"; 2941 reg = <0 0x03210000 0 0x2000>; 2942 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2943 clocks = <&rxmacro>; 2944 clock-names = "iface"; 2945 label = "RX"; 2946 qcom,din-ports = <0>; 2947 qcom,dout-ports = <5>; 2948 2949 pinctrl-0 = <&rx_swr_active>; 2950 pinctrl-names = "default"; 2951 2952 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2953 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2954 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2955 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2956 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2957 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2958 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2959 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2960 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2961 2962 #address-cells = <2>; 2963 #size-cells = <0>; 2964 #sound-dai-cells = <1>; 2965 status = "disabled"; 2966 }; 2967 2968 txmacro: codec@3220000 { 2969 compatible = "qcom,sm8450-lpass-tx-macro"; 2970 reg = <0 0x03220000 0 0x1000>; 2971 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2972 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2973 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2974 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2975 <&vamacro>; 2976 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2977 2978 #clock-cells = <0>; 2979 clock-output-names = "mclk"; 2980 #sound-dai-cells = <1>; 2981 }; 2982 2983 wsamacro: codec@3240000 { 2984 compatible = "qcom,sm8450-lpass-wsa-macro"; 2985 reg = <0 0x03240000 0 0x1000>; 2986 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2987 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2988 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2989 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2990 <&vamacro>; 2991 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2992 2993 #clock-cells = <0>; 2994 clock-output-names = "mclk"; 2995 #sound-dai-cells = <1>; 2996 }; 2997 2998 swr0: soundwire@3250000 { 2999 compatible = "qcom,soundwire-v1.7.0"; 3000 reg = <0 0x03250000 0 0x2000>; 3001 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3002 clocks = <&wsamacro>; 3003 clock-names = "iface"; 3004 label = "WSA"; 3005 3006 pinctrl-0 = <&wsa_swr_active>; 3007 pinctrl-names = "default"; 3008 3009 qcom,din-ports = <2>; 3010 qcom,dout-ports = <6>; 3011 3012 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 3013 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 3014 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 3015 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3016 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3017 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3018 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 3019 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3020 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3021 3022 #address-cells = <2>; 3023 #size-cells = <0>; 3024 #sound-dai-cells = <1>; 3025 status = "disabled"; 3026 }; 3027 3028 swr2: soundwire@33b0000 { 3029 compatible = "qcom,soundwire-v1.7.0"; 3030 reg = <0 0x033b0000 0 0x2000>; 3031 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3033 interrupt-names = "core", "wakeup"; 3034 3035 clocks = <&txmacro>; 3036 clock-names = "iface"; 3037 label = "TX"; 3038 3039 pinctrl-0 = <&tx_swr_active>; 3040 pinctrl-names = "default"; 3041 3042 qcom,din-ports = <4>; 3043 qcom,dout-ports = <0>; 3044 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3045 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3046 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3047 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3048 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3049 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3050 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3051 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3052 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3053 3054 #address-cells = <2>; 3055 #size-cells = <0>; 3056 #sound-dai-cells = <1>; 3057 status = "disabled"; 3058 }; 3059 3060 vamacro: codec@33f0000 { 3061 compatible = "qcom,sm8450-lpass-va-macro"; 3062 reg = <0 0x033f0000 0 0x1000>; 3063 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3064 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3065 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3066 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3067 clock-names = "mclk", "macro", "dcodec", "npl"; 3068 3069 #clock-cells = <0>; 3070 clock-output-names = "fsgen"; 3071 #sound-dai-cells = <1>; 3072 status = "disabled"; 3073 }; 3074 3075 remoteproc_cdsp: remoteproc@32300000 { 3076 compatible = "qcom,sm8450-cdsp-pas"; 3077 reg = <0 0x32300000 0 0x10000>; 3078 3079 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3080 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3081 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3082 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3083 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3084 interrupt-names = "wdog", "fatal", "ready", 3085 "handover", "stop-ack"; 3086 3087 clocks = <&rpmhcc RPMH_CXO_CLK>; 3088 clock-names = "xo"; 3089 3090 power-domains = <&rpmhpd RPMHPD_CX>, 3091 <&rpmhpd RPMHPD_MXC>; 3092 power-domain-names = "cx", "mxc"; 3093 3094 memory-region = <&cdsp_mem>; 3095 3096 qcom,qmp = <&aoss_qmp>; 3097 3098 qcom,smem-states = <&smp2p_cdsp_out 0>; 3099 qcom,smem-state-names = "stop"; 3100 3101 status = "disabled"; 3102 3103 glink-edge { 3104 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3105 IPCC_MPROC_SIGNAL_GLINK_QMP 3106 IRQ_TYPE_EDGE_RISING>; 3107 mboxes = <&ipcc IPCC_CLIENT_CDSP 3108 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3109 3110 label = "cdsp"; 3111 qcom,remote-pid = <5>; 3112 3113 fastrpc { 3114 compatible = "qcom,fastrpc"; 3115 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3116 label = "cdsp"; 3117 qcom,non-secure-domain; 3118 #address-cells = <1>; 3119 #size-cells = <0>; 3120 3121 compute-cb@1 { 3122 compatible = "qcom,fastrpc-compute-cb"; 3123 reg = <1>; 3124 iommus = <&apps_smmu 0x2161 0x0400>, 3125 <&apps_smmu 0x1021 0x1420>; 3126 }; 3127 3128 compute-cb@2 { 3129 compatible = "qcom,fastrpc-compute-cb"; 3130 reg = <2>; 3131 iommus = <&apps_smmu 0x2162 0x0400>, 3132 <&apps_smmu 0x1022 0x1420>; 3133 }; 3134 3135 compute-cb@3 { 3136 compatible = "qcom,fastrpc-compute-cb"; 3137 reg = <3>; 3138 iommus = <&apps_smmu 0x2163 0x0400>, 3139 <&apps_smmu 0x1023 0x1420>; 3140 }; 3141 3142 compute-cb@4 { 3143 compatible = "qcom,fastrpc-compute-cb"; 3144 reg = <4>; 3145 iommus = <&apps_smmu 0x2164 0x0400>, 3146 <&apps_smmu 0x1024 0x1420>; 3147 }; 3148 3149 compute-cb@5 { 3150 compatible = "qcom,fastrpc-compute-cb"; 3151 reg = <5>; 3152 iommus = <&apps_smmu 0x2165 0x0400>, 3153 <&apps_smmu 0x1025 0x1420>; 3154 }; 3155 3156 compute-cb@6 { 3157 compatible = "qcom,fastrpc-compute-cb"; 3158 reg = <6>; 3159 iommus = <&apps_smmu 0x2166 0x0400>, 3160 <&apps_smmu 0x1026 0x1420>; 3161 }; 3162 3163 compute-cb@7 { 3164 compatible = "qcom,fastrpc-compute-cb"; 3165 reg = <7>; 3166 iommus = <&apps_smmu 0x2167 0x0400>, 3167 <&apps_smmu 0x1027 0x1420>; 3168 }; 3169 3170 compute-cb@8 { 3171 compatible = "qcom,fastrpc-compute-cb"; 3172 reg = <8>; 3173 iommus = <&apps_smmu 0x2168 0x0400>, 3174 <&apps_smmu 0x1028 0x1420>; 3175 }; 3176 3177 /* note: secure cb9 in downstream */ 3178 }; 3179 }; 3180 }; 3181 3182 remoteproc_mpss: remoteproc@4080000 { 3183 compatible = "qcom,sm8450-mpss-pas"; 3184 reg = <0x0 0x04080000 0x0 0x10000>; 3185 3186 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3187 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 3188 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 3189 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 3190 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 3191 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 3192 interrupt-names = "wdog", "fatal", "ready", "handover", 3193 "stop-ack", "shutdown-ack"; 3194 3195 clocks = <&rpmhcc RPMH_CXO_CLK>; 3196 clock-names = "xo"; 3197 3198 power-domains = <&rpmhpd RPMHPD_CX>, 3199 <&rpmhpd RPMHPD_MSS>; 3200 power-domain-names = "cx", "mss"; 3201 3202 memory-region = <&mpss_mem>; 3203 3204 qcom,qmp = <&aoss_qmp>; 3205 3206 qcom,smem-states = <&smp2p_modem_out 0>; 3207 qcom,smem-state-names = "stop"; 3208 3209 status = "disabled"; 3210 3211 glink-edge { 3212 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3213 IPCC_MPROC_SIGNAL_GLINK_QMP 3214 IRQ_TYPE_EDGE_RISING>; 3215 mboxes = <&ipcc IPCC_CLIENT_MPSS 3216 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3217 label = "modem"; 3218 qcom,remote-pid = <1>; 3219 }; 3220 }; 3221 3222 videocc: clock-controller@aaf0000 { 3223 compatible = "qcom,sm8450-videocc"; 3224 reg = <0 0x0aaf0000 0 0x10000>; 3225 clocks = <&rpmhcc RPMH_CXO_CLK>, 3226 <&gcc GCC_VIDEO_AHB_CLK>; 3227 power-domains = <&rpmhpd RPMHPD_MMCX>, 3228 <&rpmhpd RPMHPD_MXC>; 3229 required-opps = <&rpmhpd_opp_low_svs>, 3230 <&rpmhpd_opp_low_svs>; 3231 #clock-cells = <1>; 3232 #reset-cells = <1>; 3233 #power-domain-cells = <1>; 3234 }; 3235 3236 cci0: cci@ac15000 { 3237 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3238 reg = <0 0x0ac15000 0 0x1000>; 3239 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3240 power-domains = <&camcc TITAN_TOP_GDSC>; 3241 3242 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3243 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3244 <&camcc CAM_CC_CPAS_AHB_CLK>, 3245 <&camcc CAM_CC_CCI_0_CLK>, 3246 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3247 clock-names = "camnoc_axi", 3248 "slow_ahb_src", 3249 "cpas_ahb", 3250 "cci", 3251 "cci_src"; 3252 pinctrl-0 = <&cci0_default &cci1_default>; 3253 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3254 pinctrl-names = "default", "sleep"; 3255 3256 status = "disabled"; 3257 #address-cells = <1>; 3258 #size-cells = <0>; 3259 3260 cci0_i2c0: i2c-bus@0 { 3261 reg = <0>; 3262 clock-frequency = <1000000>; 3263 #address-cells = <1>; 3264 #size-cells = <0>; 3265 }; 3266 3267 cci0_i2c1: i2c-bus@1 { 3268 reg = <1>; 3269 clock-frequency = <1000000>; 3270 #address-cells = <1>; 3271 #size-cells = <0>; 3272 }; 3273 }; 3274 3275 cci1: cci@ac16000 { 3276 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3277 reg = <0 0x0ac16000 0 0x1000>; 3278 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3279 power-domains = <&camcc TITAN_TOP_GDSC>; 3280 3281 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3282 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3283 <&camcc CAM_CC_CPAS_AHB_CLK>, 3284 <&camcc CAM_CC_CCI_1_CLK>, 3285 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3286 clock-names = "camnoc_axi", 3287 "slow_ahb_src", 3288 "cpas_ahb", 3289 "cci", 3290 "cci_src"; 3291 pinctrl-0 = <&cci2_default &cci3_default>; 3292 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 3293 pinctrl-names = "default", "sleep"; 3294 3295 status = "disabled"; 3296 #address-cells = <1>; 3297 #size-cells = <0>; 3298 3299 cci1_i2c0: i2c-bus@0 { 3300 reg = <0>; 3301 clock-frequency = <1000000>; 3302 #address-cells = <1>; 3303 #size-cells = <0>; 3304 }; 3305 3306 cci1_i2c1: i2c-bus@1 { 3307 reg = <1>; 3308 clock-frequency = <1000000>; 3309 #address-cells = <1>; 3310 #size-cells = <0>; 3311 }; 3312 }; 3313 3314 camcc: clock-controller@ade0000 { 3315 compatible = "qcom,sm8450-camcc"; 3316 reg = <0 0x0ade0000 0 0x20000>; 3317 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3318 <&rpmhcc RPMH_CXO_CLK>, 3319 <&rpmhcc RPMH_CXO_CLK_A>, 3320 <&sleep_clk>; 3321 power-domains = <&rpmhpd RPMHPD_MMCX>, 3322 <&rpmhpd RPMHPD_MXC>; 3323 required-opps = <&rpmhpd_opp_low_svs>, 3324 <&rpmhpd_opp_low_svs>; 3325 #clock-cells = <1>; 3326 #reset-cells = <1>; 3327 #power-domain-cells = <1>; 3328 }; 3329 3330 mdss: display-subsystem@ae00000 { 3331 compatible = "qcom,sm8450-mdss"; 3332 reg = <0 0x0ae00000 0 0x1000>; 3333 reg-names = "mdss"; 3334 3335 /* same path used twice */ 3336 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3337 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3338 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3339 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3340 interconnect-names = "mdp0-mem", 3341 "mdp1-mem", 3342 "cpu-cfg"; 3343 3344 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3345 3346 power-domains = <&dispcc MDSS_GDSC>; 3347 3348 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3349 <&gcc GCC_DISP_HF_AXI_CLK>, 3350 <&gcc GCC_DISP_SF_AXI_CLK>, 3351 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3352 3353 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3354 interrupt-controller; 3355 #interrupt-cells = <1>; 3356 3357 iommus = <&apps_smmu 0x2800 0x402>; 3358 3359 #address-cells = <2>; 3360 #size-cells = <2>; 3361 ranges; 3362 3363 status = "disabled"; 3364 3365 mdss_mdp: display-controller@ae01000 { 3366 compatible = "qcom,sm8450-dpu"; 3367 reg = <0 0x0ae01000 0 0x8f000>, 3368 <0 0x0aeb0000 0 0x3000>; 3369 reg-names = "mdp", "vbif"; 3370 3371 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3372 <&gcc GCC_DISP_SF_AXI_CLK>, 3373 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3374 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3375 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3376 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3377 clock-names = "bus", 3378 "nrt_bus", 3379 "iface", 3380 "lut", 3381 "core", 3382 "vsync"; 3383 3384 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3385 assigned-clock-rates = <19200000>; 3386 3387 operating-points-v2 = <&mdp_opp_table>; 3388 power-domains = <&rpmhpd RPMHPD_MMCX>; 3389 3390 interrupt-parent = <&mdss>; 3391 interrupts = <0>; 3392 3393 ports { 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 port@0 { 3398 reg = <0>; 3399 dpu_intf1_out: endpoint { 3400 remote-endpoint = <&mdss_dsi0_in>; 3401 }; 3402 }; 3403 3404 port@1 { 3405 reg = <1>; 3406 dpu_intf2_out: endpoint { 3407 remote-endpoint = <&mdss_dsi1_in>; 3408 }; 3409 }; 3410 3411 port@2 { 3412 reg = <2>; 3413 dpu_intf0_out: endpoint { 3414 remote-endpoint = <&mdss_dp0_in>; 3415 }; 3416 }; 3417 }; 3418 3419 mdp_opp_table: opp-table { 3420 compatible = "operating-points-v2"; 3421 3422 opp-172000000 { 3423 opp-hz = /bits/ 64 <172000000>; 3424 required-opps = <&rpmhpd_opp_low_svs_d1>; 3425 }; 3426 3427 opp-200000000 { 3428 opp-hz = /bits/ 64 <200000000>; 3429 required-opps = <&rpmhpd_opp_low_svs>; 3430 }; 3431 3432 opp-325000000 { 3433 opp-hz = /bits/ 64 <325000000>; 3434 required-opps = <&rpmhpd_opp_svs>; 3435 }; 3436 3437 opp-375000000 { 3438 opp-hz = /bits/ 64 <375000000>; 3439 required-opps = <&rpmhpd_opp_svs_l1>; 3440 }; 3441 3442 opp-500000000 { 3443 opp-hz = /bits/ 64 <500000000>; 3444 required-opps = <&rpmhpd_opp_nom>; 3445 }; 3446 }; 3447 }; 3448 3449 mdss_dp0: displayport-controller@ae90000 { 3450 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3451 reg = <0 0xae90000 0 0x200>, 3452 <0 0xae90200 0 0x200>, 3453 <0 0xae90400 0 0xc00>, 3454 <0 0xae91000 0 0x400>, 3455 <0 0xae91400 0 0x400>; 3456 interrupt-parent = <&mdss>; 3457 interrupts = <12>; 3458 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3459 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3460 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3461 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3462 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 3463 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 3464 clock-names = "core_iface", 3465 "core_aux", 3466 "ctrl_link", 3467 "ctrl_link_iface", 3468 "stream_pixel", 3469 "stream_1_pixel"; 3470 3471 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3472 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 3473 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 3474 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3475 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3476 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3477 3478 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3479 phy-names = "dp"; 3480 3481 #sound-dai-cells = <0>; 3482 3483 operating-points-v2 = <&dp_opp_table>; 3484 power-domains = <&rpmhpd RPMHPD_MMCX>; 3485 3486 status = "disabled"; 3487 3488 ports { 3489 #address-cells = <1>; 3490 #size-cells = <0>; 3491 3492 port@0 { 3493 reg = <0>; 3494 mdss_dp0_in: endpoint { 3495 remote-endpoint = <&dpu_intf0_out>; 3496 }; 3497 }; 3498 3499 port@1 { 3500 reg = <1>; 3501 3502 mdss_dp0_out: endpoint { 3503 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3504 }; 3505 }; 3506 }; 3507 3508 dp_opp_table: opp-table { 3509 compatible = "operating-points-v2"; 3510 3511 opp-160000000 { 3512 opp-hz = /bits/ 64 <160000000>; 3513 required-opps = <&rpmhpd_opp_low_svs>; 3514 }; 3515 3516 opp-270000000 { 3517 opp-hz = /bits/ 64 <270000000>; 3518 required-opps = <&rpmhpd_opp_svs>; 3519 }; 3520 3521 opp-540000000 { 3522 opp-hz = /bits/ 64 <540000000>; 3523 required-opps = <&rpmhpd_opp_svs_l1>; 3524 }; 3525 3526 opp-810000000 { 3527 opp-hz = /bits/ 64 <810000000>; 3528 required-opps = <&rpmhpd_opp_nom>; 3529 }; 3530 }; 3531 }; 3532 3533 mdss_dsi0: dsi@ae94000 { 3534 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3535 reg = <0 0x0ae94000 0 0x400>; 3536 reg-names = "dsi_ctrl"; 3537 3538 interrupt-parent = <&mdss>; 3539 interrupts = <4>; 3540 3541 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3542 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3543 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3544 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3545 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3546 <&gcc GCC_DISP_HF_AXI_CLK>; 3547 clock-names = "byte", 3548 "byte_intf", 3549 "pixel", 3550 "core", 3551 "iface", 3552 "bus"; 3553 3554 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3555 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3556 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3557 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3558 3559 operating-points-v2 = <&mdss_dsi_opp_table>; 3560 power-domains = <&rpmhpd RPMHPD_MMCX>; 3561 3562 phys = <&mdss_dsi0_phy>; 3563 phy-names = "dsi"; 3564 3565 #address-cells = <1>; 3566 #size-cells = <0>; 3567 3568 status = "disabled"; 3569 3570 ports { 3571 #address-cells = <1>; 3572 #size-cells = <0>; 3573 3574 port@0 { 3575 reg = <0>; 3576 mdss_dsi0_in: endpoint { 3577 remote-endpoint = <&dpu_intf1_out>; 3578 }; 3579 }; 3580 3581 port@1 { 3582 reg = <1>; 3583 mdss_dsi0_out: endpoint { 3584 }; 3585 }; 3586 }; 3587 3588 mdss_dsi_opp_table: opp-table { 3589 compatible = "operating-points-v2"; 3590 3591 opp-187500000 { 3592 opp-hz = /bits/ 64 <187500000>; 3593 required-opps = <&rpmhpd_opp_low_svs>; 3594 }; 3595 3596 opp-300000000 { 3597 opp-hz = /bits/ 64 <300000000>; 3598 required-opps = <&rpmhpd_opp_svs>; 3599 }; 3600 3601 opp-358000000 { 3602 opp-hz = /bits/ 64 <358000000>; 3603 required-opps = <&rpmhpd_opp_svs_l1>; 3604 }; 3605 }; 3606 }; 3607 3608 mdss_dsi0_phy: phy@ae94400 { 3609 compatible = "qcom,sm8450-dsi-phy-5nm"; 3610 reg = <0 0x0ae94400 0 0x200>, 3611 <0 0x0ae94600 0 0x280>, 3612 <0 0x0ae94900 0 0x260>; 3613 reg-names = "dsi_phy", 3614 "dsi_phy_lane", 3615 "dsi_pll"; 3616 3617 #clock-cells = <1>; 3618 #phy-cells = <0>; 3619 3620 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3621 <&rpmhcc RPMH_CXO_CLK>; 3622 clock-names = "iface", "ref"; 3623 3624 status = "disabled"; 3625 }; 3626 3627 mdss_dsi1: dsi@ae96000 { 3628 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3629 reg = <0 0x0ae96000 0 0x400>; 3630 reg-names = "dsi_ctrl"; 3631 3632 interrupt-parent = <&mdss>; 3633 interrupts = <5>; 3634 3635 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3636 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3637 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3638 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3639 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3640 <&gcc GCC_DISP_HF_AXI_CLK>; 3641 clock-names = "byte", 3642 "byte_intf", 3643 "pixel", 3644 "core", 3645 "iface", 3646 "bus"; 3647 3648 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3649 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3650 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3651 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3652 3653 operating-points-v2 = <&mdss_dsi_opp_table>; 3654 power-domains = <&rpmhpd RPMHPD_MMCX>; 3655 3656 phys = <&mdss_dsi1_phy>; 3657 phy-names = "dsi"; 3658 3659 #address-cells = <1>; 3660 #size-cells = <0>; 3661 3662 status = "disabled"; 3663 3664 ports { 3665 #address-cells = <1>; 3666 #size-cells = <0>; 3667 3668 port@0 { 3669 reg = <0>; 3670 mdss_dsi1_in: endpoint { 3671 remote-endpoint = <&dpu_intf2_out>; 3672 }; 3673 }; 3674 3675 port@1 { 3676 reg = <1>; 3677 mdss_dsi1_out: endpoint { 3678 }; 3679 }; 3680 }; 3681 }; 3682 3683 mdss_dsi1_phy: phy@ae96400 { 3684 compatible = "qcom,sm8450-dsi-phy-5nm"; 3685 reg = <0 0x0ae96400 0 0x200>, 3686 <0 0x0ae96600 0 0x280>, 3687 <0 0x0ae96900 0 0x260>; 3688 reg-names = "dsi_phy", 3689 "dsi_phy_lane", 3690 "dsi_pll"; 3691 3692 #clock-cells = <1>; 3693 #phy-cells = <0>; 3694 3695 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3696 <&rpmhcc RPMH_CXO_CLK>; 3697 clock-names = "iface", "ref"; 3698 3699 status = "disabled"; 3700 }; 3701 }; 3702 3703 dispcc: clock-controller@af00000 { 3704 compatible = "qcom,sm8450-dispcc"; 3705 reg = <0 0x0af00000 0 0x20000>; 3706 clocks = <&rpmhcc RPMH_CXO_CLK>, 3707 <&rpmhcc RPMH_CXO_CLK_A>, 3708 <&gcc GCC_DISP_AHB_CLK>, 3709 <&sleep_clk>, 3710 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3711 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3712 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3713 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3714 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3715 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3716 <0>, /* dp1 */ 3717 <0>, 3718 <0>, /* dp2 */ 3719 <0>, 3720 <0>, /* dp3 */ 3721 <0>; 3722 power-domains = <&rpmhpd RPMHPD_MMCX>; 3723 required-opps = <&rpmhpd_opp_low_svs>; 3724 #clock-cells = <1>; 3725 #reset-cells = <1>; 3726 #power-domain-cells = <1>; 3727 }; 3728 3729 pdc: interrupt-controller@b220000 { 3730 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3731 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3732 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3733 <94 609 31>, <125 63 1>, <126 716 12>; 3734 #interrupt-cells = <2>; 3735 interrupt-parent = <&intc>; 3736 interrupt-controller; 3737 }; 3738 3739 tsens0: thermal-sensor@c263000 { 3740 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3741 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3742 <0 0x0c222000 0 0x1000>; /* SROT */ 3743 #qcom,sensors = <16>; 3744 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3746 interrupt-names = "uplow", "critical"; 3747 #thermal-sensor-cells = <1>; 3748 }; 3749 3750 tsens1: thermal-sensor@c265000 { 3751 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3752 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3753 <0 0x0c223000 0 0x1000>; /* SROT */ 3754 #qcom,sensors = <16>; 3755 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3757 interrupt-names = "uplow", "critical"; 3758 #thermal-sensor-cells = <1>; 3759 }; 3760 3761 aoss_qmp: power-management@c300000 { 3762 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3763 reg = <0 0x0c300000 0 0x400>; 3764 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3765 IRQ_TYPE_EDGE_RISING>; 3766 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3767 3768 #clock-cells = <0>; 3769 }; 3770 3771 sram@c3f0000 { 3772 compatible = "qcom,rpmh-stats"; 3773 reg = <0 0x0c3f0000 0 0x400>; 3774 qcom,qmp = <&aoss_qmp>; 3775 }; 3776 3777 spmi_bus: spmi@c400000 { 3778 compatible = "qcom,spmi-pmic-arb"; 3779 reg = <0 0x0c400000 0 0x00003000>, 3780 <0 0x0c500000 0 0x00400000>, 3781 <0 0x0c440000 0 0x00080000>, 3782 <0 0x0c4c0000 0 0x00010000>, 3783 <0 0x0c42d000 0 0x00010000>; 3784 reg-names = "core", 3785 "chnls", 3786 "obsrvr", 3787 "intr", 3788 "cnfg"; 3789 interrupt-names = "periph_irq"; 3790 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3791 qcom,ee = <0>; 3792 qcom,channel = <0>; 3793 interrupt-controller; 3794 #interrupt-cells = <4>; 3795 #address-cells = <2>; 3796 #size-cells = <0>; 3797 }; 3798 3799 ipcc: mailbox@ed18000 { 3800 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3801 reg = <0 0x0ed18000 0 0x1000>; 3802 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3803 interrupt-controller; 3804 #interrupt-cells = <3>; 3805 #mbox-cells = <2>; 3806 }; 3807 3808 tlmm: pinctrl@f100000 { 3809 compatible = "qcom,sm8450-tlmm"; 3810 reg = <0 0x0f100000 0 0x300000>; 3811 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3812 gpio-controller; 3813 #gpio-cells = <2>; 3814 interrupt-controller; 3815 #interrupt-cells = <2>; 3816 gpio-ranges = <&tlmm 0 0 211>; 3817 wakeup-parent = <&pdc>; 3818 3819 sdc2_default_state: sdc2-default-state { 3820 clk-pins { 3821 pins = "sdc2_clk"; 3822 drive-strength = <16>; 3823 bias-disable; 3824 }; 3825 3826 cmd-pins { 3827 pins = "sdc2_cmd"; 3828 drive-strength = <16>; 3829 bias-pull-up; 3830 }; 3831 3832 data-pins { 3833 pins = "sdc2_data"; 3834 drive-strength = <16>; 3835 bias-pull-up; 3836 }; 3837 }; 3838 3839 sdc2_sleep_state: sdc2-sleep-state { 3840 clk-pins { 3841 pins = "sdc2_clk"; 3842 drive-strength = <2>; 3843 bias-disable; 3844 }; 3845 3846 cmd-pins { 3847 pins = "sdc2_cmd"; 3848 drive-strength = <2>; 3849 bias-pull-up; 3850 }; 3851 3852 data-pins { 3853 pins = "sdc2_data"; 3854 drive-strength = <2>; 3855 bias-pull-up; 3856 }; 3857 }; 3858 3859 cci0_default: cci0-default-state { 3860 /* SDA, SCL */ 3861 pins = "gpio110", "gpio111"; 3862 function = "cci_i2c"; 3863 drive-strength = <2>; 3864 bias-pull-up; 3865 }; 3866 3867 cci0_sleep: cci0-sleep-state { 3868 /* SDA, SCL */ 3869 pins = "gpio110", "gpio111"; 3870 function = "cci_i2c"; 3871 drive-strength = <2>; 3872 bias-pull-down; 3873 }; 3874 3875 cci1_default: cci1-default-state { 3876 /* SDA, SCL */ 3877 pins = "gpio112", "gpio113"; 3878 function = "cci_i2c"; 3879 drive-strength = <2>; 3880 bias-pull-up; 3881 }; 3882 3883 cci1_sleep: cci1-sleep-state { 3884 /* SDA, SCL */ 3885 pins = "gpio112", "gpio113"; 3886 function = "cci_i2c"; 3887 drive-strength = <2>; 3888 bias-pull-down; 3889 }; 3890 3891 cci2_default: cci2-default-state { 3892 /* SDA, SCL */ 3893 pins = "gpio114", "gpio115"; 3894 function = "cci_i2c"; 3895 drive-strength = <2>; 3896 bias-pull-up; 3897 }; 3898 3899 cci2_sleep: cci2-sleep-state { 3900 /* SDA, SCL */ 3901 pins = "gpio114", "gpio115"; 3902 function = "cci_i2c"; 3903 drive-strength = <2>; 3904 bias-pull-down; 3905 }; 3906 3907 cci3_default: cci3-default-state { 3908 /* SDA, SCL */ 3909 pins = "gpio208", "gpio209"; 3910 function = "cci_i2c"; 3911 drive-strength = <2>; 3912 bias-pull-up; 3913 }; 3914 3915 cci3_sleep: cci3-sleep-state { 3916 /* SDA, SCL */ 3917 pins = "gpio208", "gpio209"; 3918 function = "cci_i2c"; 3919 drive-strength = <2>; 3920 bias-pull-down; 3921 }; 3922 3923 pcie0_default_state: pcie0-default-state { 3924 perst-pins { 3925 pins = "gpio94"; 3926 function = "gpio"; 3927 drive-strength = <2>; 3928 bias-pull-down; 3929 }; 3930 3931 clkreq-pins { 3932 pins = "gpio95"; 3933 function = "pcie0_clkreqn"; 3934 drive-strength = <2>; 3935 bias-pull-up; 3936 }; 3937 3938 wake-pins { 3939 pins = "gpio96"; 3940 function = "gpio"; 3941 drive-strength = <2>; 3942 bias-pull-up; 3943 }; 3944 }; 3945 3946 pcie1_default_state: pcie1-default-state { 3947 perst-pins { 3948 pins = "gpio97"; 3949 function = "gpio"; 3950 drive-strength = <2>; 3951 bias-pull-down; 3952 }; 3953 3954 clkreq-pins { 3955 pins = "gpio98"; 3956 function = "pcie1_clkreqn"; 3957 drive-strength = <2>; 3958 bias-pull-up; 3959 }; 3960 3961 wake-pins { 3962 pins = "gpio99"; 3963 function = "gpio"; 3964 drive-strength = <2>; 3965 bias-pull-up; 3966 }; 3967 }; 3968 3969 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3970 pins = "gpio0", "gpio1"; 3971 function = "qup0"; 3972 }; 3973 3974 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3975 pins = "gpio4", "gpio5"; 3976 function = "qup1"; 3977 }; 3978 3979 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3980 pins = "gpio8", "gpio9"; 3981 function = "qup2"; 3982 }; 3983 3984 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3985 pins = "gpio12", "gpio13"; 3986 function = "qup3"; 3987 }; 3988 3989 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3990 pins = "gpio16", "gpio17"; 3991 function = "qup4"; 3992 }; 3993 3994 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3995 pins = "gpio206", "gpio207"; 3996 function = "qup5"; 3997 }; 3998 3999 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4000 pins = "gpio20", "gpio21"; 4001 function = "qup6"; 4002 }; 4003 4004 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4005 pins = "gpio28", "gpio29"; 4006 function = "qup8"; 4007 }; 4008 4009 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4010 pins = "gpio32", "gpio33"; 4011 function = "qup9"; 4012 }; 4013 4014 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4015 pins = "gpio36", "gpio37"; 4016 function = "qup10"; 4017 }; 4018 4019 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4020 pins = "gpio40", "gpio41"; 4021 function = "qup11"; 4022 }; 4023 4024 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4025 pins = "gpio44", "gpio45"; 4026 function = "qup12"; 4027 }; 4028 4029 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4030 pins = "gpio48", "gpio49"; 4031 function = "qup13"; 4032 drive-strength = <2>; 4033 bias-pull-up; 4034 }; 4035 4036 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4037 pins = "gpio52", "gpio53"; 4038 function = "qup14"; 4039 drive-strength = <2>; 4040 bias-pull-up; 4041 }; 4042 4043 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4044 pins = "gpio56", "gpio57"; 4045 function = "qup15"; 4046 }; 4047 4048 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4049 pins = "gpio60", "gpio61"; 4050 function = "qup16"; 4051 }; 4052 4053 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4054 pins = "gpio64", "gpio65"; 4055 function = "qup17"; 4056 }; 4057 4058 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4059 pins = "gpio68", "gpio69"; 4060 function = "qup18"; 4061 }; 4062 4063 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4064 pins = "gpio72", "gpio73"; 4065 function = "qup19"; 4066 }; 4067 4068 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 4069 pins = "gpio76", "gpio77"; 4070 function = "qup20"; 4071 }; 4072 4073 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 4074 pins = "gpio80", "gpio81"; 4075 function = "qup21"; 4076 }; 4077 4078 qup_spi0_cs: qup-spi0-cs-state { 4079 pins = "gpio3"; 4080 function = "qup0"; 4081 }; 4082 4083 qup_spi0_data_clk: qup-spi0-data-clk-state { 4084 pins = "gpio0", "gpio1", "gpio2"; 4085 function = "qup0"; 4086 }; 4087 4088 qup_spi1_cs: qup-spi1-cs-state { 4089 pins = "gpio7"; 4090 function = "qup1"; 4091 }; 4092 4093 qup_spi1_data_clk: qup-spi1-data-clk-state { 4094 pins = "gpio4", "gpio5", "gpio6"; 4095 function = "qup1"; 4096 }; 4097 4098 qup_spi2_cs: qup-spi2-cs-state { 4099 pins = "gpio11"; 4100 function = "qup2"; 4101 }; 4102 4103 qup_spi2_data_clk: qup-spi2-data-clk-state { 4104 pins = "gpio8", "gpio9", "gpio10"; 4105 function = "qup2"; 4106 }; 4107 4108 qup_spi3_cs: qup-spi3-cs-state { 4109 pins = "gpio15"; 4110 function = "qup3"; 4111 }; 4112 4113 qup_spi3_data_clk: qup-spi3-data-clk-state { 4114 pins = "gpio12", "gpio13", "gpio14"; 4115 function = "qup3"; 4116 }; 4117 4118 qup_spi4_cs: qup-spi4-cs-state { 4119 pins = "gpio19"; 4120 function = "qup4"; 4121 drive-strength = <6>; 4122 bias-disable; 4123 }; 4124 4125 qup_spi4_data_clk: qup-spi4-data-clk-state { 4126 pins = "gpio16", "gpio17", "gpio18"; 4127 function = "qup4"; 4128 }; 4129 4130 qup_spi5_cs: qup-spi5-cs-state { 4131 pins = "gpio85"; 4132 function = "qup5"; 4133 }; 4134 4135 qup_spi5_data_clk: qup-spi5-data-clk-state { 4136 pins = "gpio206", "gpio207", "gpio84"; 4137 function = "qup5"; 4138 }; 4139 4140 qup_spi6_cs: qup-spi6-cs-state { 4141 pins = "gpio23"; 4142 function = "qup6"; 4143 }; 4144 4145 qup_spi6_data_clk: qup-spi6-data-clk-state { 4146 pins = "gpio20", "gpio21", "gpio22"; 4147 function = "qup6"; 4148 }; 4149 4150 qup_spi8_cs: qup-spi8-cs-state { 4151 pins = "gpio31"; 4152 function = "qup8"; 4153 }; 4154 4155 qup_spi8_data_clk: qup-spi8-data-clk-state { 4156 pins = "gpio28", "gpio29", "gpio30"; 4157 function = "qup8"; 4158 }; 4159 4160 qup_spi9_cs: qup-spi9-cs-state { 4161 pins = "gpio35"; 4162 function = "qup9"; 4163 }; 4164 4165 qup_spi9_data_clk: qup-spi9-data-clk-state { 4166 pins = "gpio32", "gpio33", "gpio34"; 4167 function = "qup9"; 4168 }; 4169 4170 qup_spi10_cs: qup-spi10-cs-state { 4171 pins = "gpio39"; 4172 function = "qup10"; 4173 }; 4174 4175 qup_spi10_data_clk: qup-spi10-data-clk-state { 4176 pins = "gpio36", "gpio37", "gpio38"; 4177 function = "qup10"; 4178 }; 4179 4180 qup_spi11_cs: qup-spi11-cs-state { 4181 pins = "gpio43"; 4182 function = "qup11"; 4183 }; 4184 4185 qup_spi11_data_clk: qup-spi11-data-clk-state { 4186 pins = "gpio40", "gpio41", "gpio42"; 4187 function = "qup11"; 4188 }; 4189 4190 qup_spi12_cs: qup-spi12-cs-state { 4191 pins = "gpio47"; 4192 function = "qup12"; 4193 }; 4194 4195 qup_spi12_data_clk: qup-spi12-data-clk-state { 4196 pins = "gpio44", "gpio45", "gpio46"; 4197 function = "qup12"; 4198 }; 4199 4200 qup_spi13_cs: qup-spi13-cs-state { 4201 pins = "gpio51"; 4202 function = "qup13"; 4203 }; 4204 4205 qup_spi13_data_clk: qup-spi13-data-clk-state { 4206 pins = "gpio48", "gpio49", "gpio50"; 4207 function = "qup13"; 4208 }; 4209 4210 qup_spi14_cs: qup-spi14-cs-state { 4211 pins = "gpio55"; 4212 function = "qup14"; 4213 }; 4214 4215 qup_spi14_data_clk: qup-spi14-data-clk-state { 4216 pins = "gpio52", "gpio53", "gpio54"; 4217 function = "qup14"; 4218 }; 4219 4220 qup_spi15_cs: qup-spi15-cs-state { 4221 pins = "gpio59"; 4222 function = "qup15"; 4223 }; 4224 4225 qup_spi15_data_clk: qup-spi15-data-clk-state { 4226 pins = "gpio56", "gpio57", "gpio58"; 4227 function = "qup15"; 4228 }; 4229 4230 qup_spi16_cs: qup-spi16-cs-state { 4231 pins = "gpio63"; 4232 function = "qup16"; 4233 }; 4234 4235 qup_spi16_data_clk: qup-spi16-data-clk-state { 4236 pins = "gpio60", "gpio61", "gpio62"; 4237 function = "qup16"; 4238 }; 4239 4240 qup_spi17_cs: qup-spi17-cs-state { 4241 pins = "gpio67"; 4242 function = "qup17"; 4243 }; 4244 4245 qup_spi17_data_clk: qup-spi17-data-clk-state { 4246 pins = "gpio64", "gpio65", "gpio66"; 4247 function = "qup17"; 4248 }; 4249 4250 qup_spi18_cs: qup-spi18-cs-state { 4251 pins = "gpio71"; 4252 function = "qup18"; 4253 drive-strength = <6>; 4254 bias-disable; 4255 }; 4256 4257 qup_spi18_data_clk: qup-spi18-data-clk-state { 4258 pins = "gpio68", "gpio69", "gpio70"; 4259 function = "qup18"; 4260 drive-strength = <6>; 4261 bias-disable; 4262 }; 4263 4264 qup_spi19_cs: qup-spi19-cs-state { 4265 pins = "gpio75"; 4266 function = "qup19"; 4267 drive-strength = <6>; 4268 bias-disable; 4269 }; 4270 4271 qup_spi19_data_clk: qup-spi19-data-clk-state { 4272 pins = "gpio72", "gpio73", "gpio74"; 4273 function = "qup19"; 4274 drive-strength = <6>; 4275 bias-disable; 4276 }; 4277 4278 qup_spi20_cs: qup-spi20-cs-state { 4279 pins = "gpio79"; 4280 function = "qup20"; 4281 }; 4282 4283 qup_spi20_data_clk: qup-spi20-data-clk-state { 4284 pins = "gpio76", "gpio77", "gpio78"; 4285 function = "qup20"; 4286 }; 4287 4288 qup_spi21_cs: qup-spi21-cs-state { 4289 pins = "gpio83"; 4290 function = "qup21"; 4291 }; 4292 4293 qup_spi21_data_clk: qup-spi21-data-clk-state { 4294 pins = "gpio80", "gpio81", "gpio82"; 4295 function = "qup21"; 4296 }; 4297 4298 qup_uart7_rx: qup-uart7-rx-state { 4299 pins = "gpio26"; 4300 function = "qup7"; 4301 drive-strength = <2>; 4302 bias-disable; 4303 }; 4304 4305 qup_uart7_tx: qup-uart7-tx-state { 4306 pins = "gpio27"; 4307 function = "qup7"; 4308 drive-strength = <2>; 4309 bias-disable; 4310 }; 4311 4312 qup_uart20_default: qup-uart20-default-state { 4313 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 4314 function = "qup20"; 4315 }; 4316 }; 4317 4318 lpass_tlmm: pinctrl@3440000 { 4319 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 4320 reg = <0 0x03440000 0x0 0x20000>, 4321 <0 0x034d0000 0x0 0x10000>; 4322 gpio-controller; 4323 #gpio-cells = <2>; 4324 gpio-ranges = <&lpass_tlmm 0 0 23>; 4325 4326 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4327 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4328 clock-names = "core", "audio"; 4329 4330 tx_swr_active: tx-swr-active-state { 4331 clk-pins { 4332 pins = "gpio0"; 4333 function = "swr_tx_clk"; 4334 drive-strength = <2>; 4335 slew-rate = <1>; 4336 bias-disable; 4337 }; 4338 4339 data-pins { 4340 pins = "gpio1", "gpio2", "gpio14"; 4341 function = "swr_tx_data"; 4342 drive-strength = <2>; 4343 slew-rate = <1>; 4344 bias-bus-hold; 4345 }; 4346 }; 4347 4348 rx_swr_active: rx-swr-active-state { 4349 clk-pins { 4350 pins = "gpio3"; 4351 function = "swr_rx_clk"; 4352 drive-strength = <2>; 4353 slew-rate = <1>; 4354 bias-disable; 4355 }; 4356 4357 data-pins { 4358 pins = "gpio4", "gpio5"; 4359 function = "swr_rx_data"; 4360 drive-strength = <2>; 4361 slew-rate = <1>; 4362 bias-bus-hold; 4363 }; 4364 }; 4365 4366 dmic01_default: dmic01-default-state { 4367 clk-pins { 4368 pins = "gpio6"; 4369 function = "dmic1_clk"; 4370 drive-strength = <8>; 4371 output-high; 4372 }; 4373 4374 data-pins { 4375 pins = "gpio7"; 4376 function = "dmic1_data"; 4377 drive-strength = <8>; 4378 }; 4379 }; 4380 4381 dmic23_default: dmic23-default-state { 4382 clk-pins { 4383 pins = "gpio8"; 4384 function = "dmic2_clk"; 4385 drive-strength = <8>; 4386 output-high; 4387 }; 4388 4389 data-pins { 4390 pins = "gpio9"; 4391 function = "dmic2_data"; 4392 drive-strength = <8>; 4393 }; 4394 }; 4395 4396 wsa_swr_active: wsa-swr-active-state { 4397 clk-pins { 4398 pins = "gpio10"; 4399 function = "wsa_swr_clk"; 4400 drive-strength = <2>; 4401 slew-rate = <1>; 4402 bias-disable; 4403 }; 4404 4405 data-pins { 4406 pins = "gpio11"; 4407 function = "wsa_swr_data"; 4408 drive-strength = <2>; 4409 slew-rate = <1>; 4410 bias-bus-hold; 4411 }; 4412 }; 4413 4414 wsa2_swr_active: wsa2-swr-active-state { 4415 clk-pins { 4416 pins = "gpio15"; 4417 function = "wsa2_swr_clk"; 4418 drive-strength = <2>; 4419 slew-rate = <1>; 4420 bias-disable; 4421 }; 4422 4423 data-pins { 4424 pins = "gpio16"; 4425 function = "wsa2_swr_data"; 4426 drive-strength = <2>; 4427 slew-rate = <1>; 4428 bias-bus-hold; 4429 }; 4430 }; 4431 }; 4432 4433 stm@10002000 { 4434 compatible = "arm,coresight-stm", "arm,primecell"; 4435 reg = <0x0 0x10002000 0x0 0x1000>, 4436 <0x0 0x16280000 0x0 0x180000>; 4437 reg-names = "stm-base", "stm-stimulus-base"; 4438 4439 clocks = <&aoss_qmp>; 4440 clock-names = "apb_pclk"; 4441 4442 out-ports { 4443 port { 4444 stm_out_funnel_in0: endpoint { 4445 remote-endpoint = 4446 <&funnel_in0_in_stm>; 4447 }; 4448 }; 4449 }; 4450 }; 4451 4452 funnel@10041000 { 4453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4454 reg = <0x0 0x10041000 0x0 0x1000>; 4455 4456 clocks = <&aoss_qmp>; 4457 clock-names = "apb_pclk"; 4458 4459 in-ports { 4460 #address-cells = <1>; 4461 #size-cells = <0>; 4462 4463 port@7 { 4464 reg = <7>; 4465 funnel_in0_in_stm: endpoint { 4466 remote-endpoint = 4467 <&stm_out_funnel_in0>; 4468 }; 4469 }; 4470 }; 4471 4472 out-ports { 4473 port { 4474 funnel_in0_out_funnel_qdss: endpoint { 4475 remote-endpoint = 4476 <&funnel_qdss_in_funnel_in0>; 4477 }; 4478 }; 4479 }; 4480 }; 4481 4482 funnel@10042000 { 4483 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4484 4485 reg = <0x0 0x10042000 0x0 0x1000>; 4486 4487 clocks = <&aoss_qmp>; 4488 clock-names = "apb_pclk"; 4489 4490 in-ports { 4491 #address-cells = <1>; 4492 #size-cells = <0>; 4493 4494 port@4 { 4495 reg = <4>; 4496 funnel_in1_in_funnel_apss: endpoint { 4497 remote-endpoint = 4498 <&funnel_apss_out_funnel_in1>; 4499 }; 4500 }; 4501 4502 port@6 { 4503 reg = <6>; 4504 funnel_in1_in_funnel_dl_center: endpoint { 4505 remote-endpoint = 4506 <&funnel_dl_center_out_funnel_in1>; 4507 }; 4508 }; 4509 }; 4510 4511 out-ports { 4512 port { 4513 funnel_in1_out_funnel_qdss: endpoint { 4514 remote-endpoint = 4515 <&funnel_qdss_in_funnel_in1>; 4516 }; 4517 }; 4518 }; 4519 }; 4520 4521 funnel@10045000 { 4522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4523 reg = <0x0 0x10045000 0x0 0x1000>; 4524 4525 clocks = <&aoss_qmp>; 4526 clock-names = "apb_pclk"; 4527 4528 in-ports { 4529 #address-cells = <1>; 4530 #size-cells = <0>; 4531 4532 port@0 { 4533 reg = <0>; 4534 funnel_qdss_in_funnel_in0: endpoint { 4535 remote-endpoint = 4536 <&funnel_in0_out_funnel_qdss>; 4537 }; 4538 }; 4539 4540 port@1 { 4541 reg = <1>; 4542 funnel_qdss_in_funnel_in1: endpoint { 4543 remote-endpoint = 4544 <&funnel_in1_out_funnel_qdss>; 4545 }; 4546 }; 4547 }; 4548 4549 out-ports { 4550 port { 4551 funnel_qdss_out_funnel_aoss: endpoint { 4552 remote-endpoint = 4553 <&funnel_aoss_in_funnel_qdss>; 4554 }; 4555 }; 4556 }; 4557 }; 4558 4559 replicator@10046000 { 4560 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4561 reg = <0x0 0x10046000 0x0 0x1000>; 4562 4563 clocks = <&aoss_qmp>; 4564 clock-names = "apb_pclk"; 4565 4566 in-ports { 4567 port { 4568 replicator_qdss_in_replicator_swao: endpoint { 4569 remote-endpoint = 4570 <&replicator_swao_out_replicator_qdss>; 4571 }; 4572 }; 4573 }; 4574 4575 out-ports { 4576 4577 port { 4578 replicator_qdss_out_replicator_etr: endpoint { 4579 remote-endpoint = 4580 <&replicator_etr_in_replicator_qdss>; 4581 }; 4582 }; 4583 }; 4584 }; 4585 4586 tmc_etr: tmc@10048000 { 4587 compatible = "arm,coresight-tmc", "arm,primecell"; 4588 reg = <0x0 0x10048000 0x0 0x1000>; 4589 4590 iommus = <&apps_smmu 0x0600 0>; 4591 arm,buffer-size = <0x10000>; 4592 4593 arm,scatter-gather; 4594 clocks = <&aoss_qmp>; 4595 clock-names = "apb_pclk"; 4596 4597 in-ports { 4598 port { 4599 tmc_etr_in_replicator_etr: endpoint { 4600 remote-endpoint = 4601 <&replicator_etr_out_tmc_etr>; 4602 }; 4603 }; 4604 }; 4605 }; 4606 4607 replicator@1004e000 { 4608 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4609 reg = <0x0 0x1004e000 0x0 0x1000>; 4610 4611 clocks = <&aoss_qmp>; 4612 clock-names = "apb_pclk"; 4613 4614 in-ports { 4615 port { 4616 replicator_etr_in_replicator_qdss: endpoint { 4617 remote-endpoint = 4618 <&replicator_qdss_out_replicator_etr>; 4619 }; 4620 }; 4621 }; 4622 4623 out-ports { 4624 4625 port { 4626 4627 replicator_etr_out_tmc_etr: endpoint { 4628 remote-endpoint = 4629 <&tmc_etr_in_replicator_etr>; 4630 }; 4631 }; 4632 }; 4633 }; 4634 4635 funnel@10b04000 { 4636 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4637 4638 reg = <0x0 0x10b04000 0x0 0x1000>; 4639 4640 clocks = <&aoss_qmp>; 4641 clock-names = "apb_pclk"; 4642 4643 in-ports { 4644 #address-cells = <1>; 4645 #size-cells = <0>; 4646 4647 port@6 { 4648 reg = <6>; 4649 funnel_aoss_in_tpda_aoss: endpoint { 4650 remote-endpoint = 4651 <&tpda_aoss_out_funnel_aoss>; 4652 }; 4653 }; 4654 4655 port@7 { 4656 reg = <7>; 4657 funnel_aoss_in_funnel_qdss: endpoint { 4658 remote-endpoint = 4659 <&funnel_qdss_out_funnel_aoss>; 4660 }; 4661 }; 4662 }; 4663 4664 out-ports { 4665 port { 4666 funnel_aoss_out_tmc_etf: endpoint { 4667 remote-endpoint = 4668 <&tmc_etf_in_funnel_aoss>; 4669 }; 4670 }; 4671 }; 4672 }; 4673 4674 tmc@10b05000 { 4675 compatible = "arm,coresight-tmc", "arm,primecell"; 4676 reg = <0x0 0x10b05000 0x0 0x1000>; 4677 4678 clocks = <&aoss_qmp>; 4679 clock-names = "apb_pclk"; 4680 4681 in-ports { 4682 port { 4683 tmc_etf_in_funnel_aoss: endpoint { 4684 remote-endpoint = 4685 <&funnel_aoss_out_tmc_etf>; 4686 }; 4687 }; 4688 }; 4689 4690 out-ports { 4691 port { 4692 tmc_etf_out_replicator_swao: endpoint { 4693 remote-endpoint = 4694 <&replicator_swao_in_tmc_etf>; 4695 }; 4696 }; 4697 }; 4698 }; 4699 4700 replicator@10b06000 { 4701 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4702 reg = <0x0 0x10b06000 0x0 0x1000>; 4703 4704 qcom,replicator-loses-context; 4705 clocks = <&aoss_qmp>; 4706 clock-names = "apb_pclk"; 4707 4708 in-ports { 4709 port { 4710 replicator_swao_in_tmc_etf: endpoint { 4711 remote-endpoint = 4712 <&tmc_etf_out_replicator_swao>; 4713 }; 4714 }; 4715 }; 4716 4717 out-ports { 4718 4719 port { 4720 replicator_swao_out_replicator_qdss: endpoint { 4721 remote-endpoint = 4722 <&replicator_qdss_in_replicator_swao>; 4723 }; 4724 }; 4725 }; 4726 }; 4727 4728 tpda@10b08000 { 4729 compatible = "qcom,coresight-tpda", "arm,primecell"; 4730 4731 reg = <0x0 0x10b08000 0x0 0x1000>; 4732 4733 clocks = <&aoss_qmp>; 4734 clock-names = "apb_pclk"; 4735 4736 in-ports { 4737 4738 #address-cells = <1>; 4739 #size-cells = <0>; 4740 4741 port@0 { 4742 reg = <0>; 4743 tpda_aoss_in_tpdm_swao_prio_0: endpoint { 4744 remote-endpoint = 4745 <&tpdm_swao_prio_0_out_tpda_aoss>; 4746 }; 4747 }; 4748 4749 port@4 { 4750 reg = <4>; 4751 tpda_aoss_in_tpdm_swao: endpoint { 4752 remote-endpoint = 4753 <&tpdm_swao_out_tpda_aoss>; 4754 }; 4755 }; 4756 }; 4757 4758 out-ports { 4759 4760 port { 4761 tpda_aoss_out_funnel_aoss: endpoint { 4762 remote-endpoint = 4763 <&funnel_aoss_in_tpda_aoss>; 4764 }; 4765 }; 4766 }; 4767 }; 4768 4769 tpdm@10b09000 { 4770 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4771 reg = <0x0 0x10b09000 0x0 0x1000>; 4772 4773 4774 clocks = <&aoss_qmp>; 4775 clock-names = "apb_pclk"; 4776 4777 out-ports { 4778 port { 4779 tpdm_swao_prio_0_out_tpda_aoss: endpoint { 4780 remote-endpoint = 4781 <&tpda_aoss_in_tpdm_swao_prio_0>; 4782 }; 4783 }; 4784 }; 4785 }; 4786 4787 tpdm@10b0d000 { 4788 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4789 reg = <0x0 0x10b0d000 0x0 0x1000>; 4790 4791 clocks = <&aoss_qmp>; 4792 clock-names = "apb_pclk"; 4793 4794 out-ports { 4795 port { 4796 tpdm_swao_out_tpda_aoss: endpoint { 4797 remote-endpoint = 4798 <&tpda_aoss_in_tpdm_swao>; 4799 }; 4800 }; 4801 }; 4802 }; 4803 4804 tpdm@10c28000 { 4805 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4806 reg = <0x0 0x10c28000 0x0 0x1000>; 4807 4808 clocks = <&aoss_qmp>; 4809 clock-names = "apb_pclk"; 4810 4811 out-ports { 4812 port { 4813 tpdm_dlct_out_tpda_dl_center_26: endpoint { 4814 remote-endpoint = 4815 <&tpda_dl_center_26_in_tpdm_dlct>; 4816 }; 4817 }; 4818 }; 4819 }; 4820 4821 tpdm@10c29000 { 4822 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4823 reg = <0x0 0x10c29000 0x0 0x1000>; 4824 4825 clocks = <&aoss_qmp>; 4826 clock-names = "apb_pclk"; 4827 4828 out-ports { 4829 port { 4830 tpdm_ipcc_out_tpda_dl_center_27: endpoint { 4831 remote-endpoint = 4832 <&tpda_dl_center_27_in_tpdm_ipcc>; 4833 }; 4834 }; 4835 }; 4836 }; 4837 4838 cti@10c2a000 { 4839 compatible = "arm,coresight-cti", "arm,primecell"; 4840 reg = <0x0 0x10c2a000 0x0 0x1000>; 4841 4842 clocks = <&aoss_qmp>; 4843 clock-names = "apb_pclk"; 4844 }; 4845 4846 cti@10c2b000 { 4847 compatible = "arm,coresight-cti", "arm,primecell"; 4848 reg = <0x0 0x10c2b000 0x0 0x1000>; 4849 4850 clocks = <&aoss_qmp>; 4851 clock-names = "apb_pclk"; 4852 }; 4853 4854 tpda@10c2e000 { 4855 compatible = "qcom,coresight-tpda", "arm,primecell"; 4856 reg = <0x0 0x10c2e000 0x0 0x1000>; 4857 4858 clocks = <&aoss_qmp>; 4859 clock-names = "apb_pclk"; 4860 4861 in-ports { 4862 4863 #address-cells = <1>; 4864 #size-cells = <0>; 4865 4866 port@1a { 4867 reg = <26>; 4868 tpda_dl_center_26_in_tpdm_dlct: endpoint { 4869 remote-endpoint = 4870 <&tpdm_dlct_out_tpda_dl_center_26>; 4871 }; 4872 }; 4873 4874 port@1b { 4875 reg = <27>; 4876 tpda_dl_center_27_in_tpdm_ipcc: endpoint { 4877 remote-endpoint = 4878 <&tpdm_ipcc_out_tpda_dl_center_27>; 4879 }; 4880 }; 4881 }; 4882 4883 out-ports { 4884 4885 port { 4886 tpda_dl_center_out_funnel_dl_center: endpoint { 4887 remote-endpoint = 4888 <&funnel_dl_center_in_tpda_dl_center>; 4889 }; 4890 }; 4891 }; 4892 }; 4893 4894 funnel@10c2f000 { 4895 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4896 reg = <0x0 0x10c2f000 0x0 0x1000>; 4897 4898 clocks = <&aoss_qmp>; 4899 clock-names = "apb_pclk"; 4900 4901 in-ports { 4902 4903 port { 4904 funnel_dl_center_in_tpda_dl_center: endpoint { 4905 remote-endpoint = 4906 <&tpda_dl_center_out_funnel_dl_center>; 4907 }; 4908 }; 4909 }; 4910 4911 out-ports { 4912 port { 4913 funnel_dl_center_out_funnel_in1: endpoint { 4914 remote-endpoint = 4915 <&funnel_in1_in_funnel_dl_center>; 4916 }; 4917 }; 4918 }; 4919 }; 4920 4921 funnel@13810000 { 4922 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4923 4924 reg = <0x0 0x13810000 0x0 0x1000>; 4925 4926 clocks = <&aoss_qmp>; 4927 clock-names = "apb_pclk"; 4928 4929 in-ports { 4930 4931 port { 4932 funnel_apss_in_funnel_ete: endpoint { 4933 remote-endpoint = 4934 <&funnel_ete_out_funnel_apss>; 4935 }; 4936 }; 4937 }; 4938 4939 out-ports { 4940 port { 4941 funnel_apss_out_funnel_in1: endpoint { 4942 remote-endpoint = 4943 <&funnel_in1_in_funnel_apss>; 4944 }; 4945 }; 4946 }; 4947 }; 4948 4949 cti@138e0000 { 4950 compatible = "arm,coresight-cti", "arm,primecell"; 4951 reg = <0x0 0x138e0000 0x0 0x1000>; 4952 4953 clocks = <&aoss_qmp>; 4954 clock-names = "apb_pclk"; 4955 }; 4956 4957 cti@138f0000 { 4958 compatible = "arm,coresight-cti", "arm,primecell"; 4959 reg = <0x0 0x138f0000 0x0 0x1000>; 4960 4961 clocks = <&aoss_qmp>; 4962 clock-names = "apb_pclk"; 4963 }; 4964 4965 cti@13900000 { 4966 compatible = "arm,coresight-cti", "arm,primecell"; 4967 reg = <0x0 0x13900000 0x0 0x1000>; 4968 4969 clocks = <&aoss_qmp>; 4970 clock-names = "apb_pclk"; 4971 }; 4972 4973 sram@146aa000 { 4974 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 4975 reg = <0 0x146aa000 0 0x1000>; 4976 ranges = <0 0 0x146aa000 0x1000>; 4977 4978 #address-cells = <1>; 4979 #size-cells = <1>; 4980 4981 pil-reloc@94c { 4982 compatible = "qcom,pil-reloc-info"; 4983 reg = <0x94c 0xc8>; 4984 }; 4985 }; 4986 4987 apps_smmu: iommu@15000000 { 4988 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4989 reg = <0 0x15000000 0 0x100000>; 4990 #iommu-cells = <2>; 4991 #global-interrupts = <1>; 4992 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4993 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4994 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4995 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4996 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4997 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4998 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4999 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5000 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5001 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5002 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5003 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 5089 dma-coherent; 5090 }; 5091 5092 intc: interrupt-controller@17100000 { 5093 compatible = "arm,gic-v3"; 5094 #interrupt-cells = <3>; 5095 interrupt-controller; 5096 #redistributor-regions = <1>; 5097 redistributor-stride = <0x0 0x40000>; 5098 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 5099 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 5100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5101 #address-cells = <2>; 5102 #size-cells = <2>; 5103 ranges; 5104 5105 gic_its: msi-controller@17140000 { 5106 compatible = "arm,gic-v3-its"; 5107 reg = <0x0 0x17140000 0x0 0x20000>; 5108 msi-controller; 5109 #msi-cells = <1>; 5110 }; 5111 }; 5112 5113 timer@17420000 { 5114 compatible = "arm,armv7-timer-mem"; 5115 #address-cells = <1>; 5116 #size-cells = <1>; 5117 ranges = <0 0 0 0x20000000>; 5118 reg = <0x0 0x17420000 0x0 0x1000>; 5119 clock-frequency = <19200000>; 5120 5121 frame@17421000 { 5122 frame-number = <0>; 5123 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5125 reg = <0x17421000 0x1000>, 5126 <0x17422000 0x1000>; 5127 }; 5128 5129 frame@17423000 { 5130 frame-number = <1>; 5131 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5132 reg = <0x17423000 0x1000>; 5133 status = "disabled"; 5134 }; 5135 5136 frame@17425000 { 5137 frame-number = <2>; 5138 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5139 reg = <0x17425000 0x1000>; 5140 status = "disabled"; 5141 }; 5142 5143 frame@17427000 { 5144 frame-number = <3>; 5145 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5146 reg = <0x17427000 0x1000>; 5147 status = "disabled"; 5148 }; 5149 5150 frame@17429000 { 5151 frame-number = <4>; 5152 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5153 reg = <0x17429000 0x1000>; 5154 status = "disabled"; 5155 }; 5156 5157 frame@1742b000 { 5158 frame-number = <5>; 5159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5160 reg = <0x1742b000 0x1000>; 5161 status = "disabled"; 5162 }; 5163 5164 frame@1742d000 { 5165 frame-number = <6>; 5166 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5167 reg = <0x1742d000 0x1000>; 5168 status = "disabled"; 5169 }; 5170 }; 5171 5172 apps_rsc: rsc@17a00000 { 5173 label = "apps_rsc"; 5174 compatible = "qcom,rpmh-rsc"; 5175 reg = <0x0 0x17a00000 0x0 0x10000>, 5176 <0x0 0x17a10000 0x0 0x10000>, 5177 <0x0 0x17a20000 0x0 0x10000>, 5178 <0x0 0x17a30000 0x0 0x10000>; 5179 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5180 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5183 qcom,tcs-offset = <0xd00>; 5184 qcom,drv-id = <2>; 5185 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5186 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5187 power-domains = <&cluster_pd>; 5188 5189 apps_bcm_voter: bcm-voter { 5190 compatible = "qcom,bcm-voter"; 5191 }; 5192 5193 rpmhcc: clock-controller { 5194 compatible = "qcom,sm8450-rpmh-clk"; 5195 #clock-cells = <1>; 5196 clock-names = "xo"; 5197 clocks = <&xo_board>; 5198 }; 5199 5200 rpmhpd: power-controller { 5201 compatible = "qcom,sm8450-rpmhpd"; 5202 #power-domain-cells = <1>; 5203 operating-points-v2 = <&rpmhpd_opp_table>; 5204 5205 rpmhpd_opp_table: opp-table { 5206 compatible = "operating-points-v2"; 5207 5208 rpmhpd_opp_ret: opp1 { 5209 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5210 }; 5211 5212 rpmhpd_opp_min_svs: opp2 { 5213 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5214 }; 5215 5216 rpmhpd_opp_low_svs_d1: opp3 { 5217 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5218 }; 5219 5220 rpmhpd_opp_low_svs: opp4 { 5221 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5222 }; 5223 5224 rpmhpd_opp_low_svs_l1: opp5 { 5225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5226 }; 5227 5228 rpmhpd_opp_svs: opp6 { 5229 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5230 }; 5231 5232 rpmhpd_opp_svs_l0: opp7 { 5233 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5234 }; 5235 5236 rpmhpd_opp_svs_l1: opp8 { 5237 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5238 }; 5239 5240 rpmhpd_opp_svs_l2: opp9 { 5241 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5242 }; 5243 5244 rpmhpd_opp_nom: opp10 { 5245 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5246 }; 5247 5248 rpmhpd_opp_nom_l1: opp11 { 5249 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5250 }; 5251 5252 rpmhpd_opp_nom_l2: opp12 { 5253 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5254 }; 5255 5256 rpmhpd_opp_turbo: opp13 { 5257 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5258 }; 5259 5260 rpmhpd_opp_turbo_l1: opp14 { 5261 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5262 }; 5263 }; 5264 }; 5265 }; 5266 5267 cpufreq_hw: cpufreq@17d91000 { 5268 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 5269 reg = <0 0x17d91000 0 0x1000>, 5270 <0 0x17d92000 0 0x1000>, 5271 <0 0x17d93000 0 0x1000>; 5272 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5273 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5274 clock-names = "xo", "alternate"; 5275 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5277 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5278 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5279 #freq-domain-cells = <1>; 5280 #clock-cells = <1>; 5281 }; 5282 5283 gem_noc: interconnect@19100000 { 5284 compatible = "qcom,sm8450-gem-noc"; 5285 reg = <0 0x19100000 0 0xbb800>; 5286 #interconnect-cells = <2>; 5287 qcom,bcm-voters = <&apps_bcm_voter>; 5288 }; 5289 5290 system-cache-controller@19200000 { 5291 compatible = "qcom,sm8450-llcc"; 5292 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 5293 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 5294 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; 5295 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 5296 "llcc3_base", "llcc_broadcast_base", 5297 "llcc_broadcast_and_base"; 5298 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5299 }; 5300 5301 ufs_mem_hc: ufshc@1d84000 { 5302 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 5303 "jedec,ufs-2.0"; 5304 reg = <0 0x01d84000 0 0x3000>; 5305 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 5306 phys = <&ufs_mem_phy>; 5307 phy-names = "ufsphy"; 5308 lanes-per-direction = <2>; 5309 #reset-cells = <1>; 5310 resets = <&gcc GCC_UFS_PHY_BCR>; 5311 reset-names = "rst"; 5312 5313 power-domains = <&gcc UFS_PHY_GDSC>; 5314 5315 iommus = <&apps_smmu 0xe0 0x0>; 5316 dma-coherent; 5317 5318 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 5319 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 5320 interconnect-names = "ufs-ddr", "cpu-ufs"; 5321 clock-names = 5322 "core_clk", 5323 "bus_aggr_clk", 5324 "iface_clk", 5325 "core_clk_unipro", 5326 "ref_clk", 5327 "tx_lane0_sync_clk", 5328 "rx_lane0_sync_clk", 5329 "rx_lane1_sync_clk"; 5330 clocks = 5331 <&gcc GCC_UFS_PHY_AXI_CLK>, 5332 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 5333 <&gcc GCC_UFS_PHY_AHB_CLK>, 5334 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 5335 <&rpmhcc RPMH_CXO_CLK>, 5336 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 5337 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 5338 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 5339 freq-table-hz = 5340 <75000000 300000000>, 5341 <0 0>, 5342 <0 0>, 5343 <75000000 300000000>, 5344 <75000000 300000000>, 5345 <0 0>, 5346 <0 0>, 5347 <0 0>; 5348 qcom,ice = <&ice>; 5349 5350 status = "disabled"; 5351 }; 5352 5353 ufs_mem_phy: phy@1d87000 { 5354 compatible = "qcom,sm8450-qmp-ufs-phy"; 5355 reg = <0 0x01d87000 0 0x1000>; 5356 5357 clock-names = "ref", "ref_aux", "qref"; 5358 clocks = <&rpmhcc RPMH_CXO_CLK>, 5359 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 5360 <&gcc GCC_UFS_0_CLKREF_EN>; 5361 5362 power-domains = <&gcc UFS_PHY_GDSC>; 5363 5364 resets = <&ufs_mem_hc 0>; 5365 reset-names = "ufsphy"; 5366 5367 #clock-cells = <1>; 5368 #phy-cells = <0>; 5369 5370 status = "disabled"; 5371 }; 5372 5373 ice: crypto@1d88000 { 5374 compatible = "qcom,sm8450-inline-crypto-engine", 5375 "qcom,inline-crypto-engine"; 5376 reg = <0 0x01d88000 0 0x8000>; 5377 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 5378 }; 5379 5380 cryptobam: dma-controller@1dc4000 { 5381 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5382 reg = <0 0x01dc4000 0 0x28000>; 5383 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 5384 #dma-cells = <1>; 5385 qcom,ee = <0>; 5386 qcom,num-ees = <4>; 5387 num-channels = <16>; 5388 qcom,controlled-remotely; 5389 iommus = <&apps_smmu 0x584 0x11>, 5390 <&apps_smmu 0x588 0x0>, 5391 <&apps_smmu 0x598 0x5>, 5392 <&apps_smmu 0x59a 0x0>, 5393 <&apps_smmu 0x59f 0x0>; 5394 }; 5395 5396 crypto: crypto@1dfa000 { 5397 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 5398 reg = <0 0x01dfa000 0 0x6000>; 5399 dmas = <&cryptobam 4>, <&cryptobam 5>; 5400 dma-names = "rx", "tx"; 5401 iommus = <&apps_smmu 0x584 0x11>, 5402 <&apps_smmu 0x588 0x0>, 5403 <&apps_smmu 0x598 0x5>, 5404 <&apps_smmu 0x59a 0x0>, 5405 <&apps_smmu 0x59f 0x0>; 5406 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 5407 interconnect-names = "memory"; 5408 }; 5409 5410 sdhc_2: mmc@8804000 { 5411 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 5412 reg = <0 0x08804000 0 0x1000>; 5413 5414 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 5415 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 5416 interrupt-names = "hc_irq", "pwr_irq"; 5417 5418 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 5419 <&gcc GCC_SDCC2_APPS_CLK>, 5420 <&rpmhcc RPMH_CXO_CLK>; 5421 clock-names = "iface", "core", "xo"; 5422 resets = <&gcc GCC_SDCC2_BCR>; 5423 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 5424 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 5425 interconnect-names = "sdhc-ddr","cpu-sdhc"; 5426 iommus = <&apps_smmu 0x4a0 0x0>; 5427 power-domains = <&rpmhpd RPMHPD_CX>; 5428 operating-points-v2 = <&sdhc2_opp_table>; 5429 bus-width = <4>; 5430 dma-coherent; 5431 5432 /* Forbid SDR104/SDR50 - broken hw! */ 5433 sdhci-caps-mask = <0x3 0x0>; 5434 5435 status = "disabled"; 5436 5437 sdhc2_opp_table: opp-table { 5438 compatible = "operating-points-v2"; 5439 5440 opp-100000000 { 5441 opp-hz = /bits/ 64 <100000000>; 5442 required-opps = <&rpmhpd_opp_low_svs>; 5443 }; 5444 5445 opp-202000000 { 5446 opp-hz = /bits/ 64 <202000000>; 5447 required-opps = <&rpmhpd_opp_svs_l1>; 5448 }; 5449 }; 5450 }; 5451 5452 usb_1: usb@a600000 { 5453 compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3"; 5454 reg = <0 0x0a600000 0 0xfc100>; 5455 status = "disabled"; 5456 5457 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5458 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5459 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5460 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5461 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5462 <&gcc GCC_USB3_0_CLKREF_EN>; 5463 clock-names = "cfg_noc", 5464 "core", 5465 "iface", 5466 "sleep", 5467 "mock_utmi", 5468 "xo"; 5469 5470 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5471 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5472 assigned-clock-rates = <19200000>, <200000000>; 5473 5474 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 5475 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 5476 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 5477 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5478 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5479 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5480 interrupt-names = "dwc_usb3", 5481 "pwr_event", 5482 "hs_phy_irq", 5483 "dp_hs_phy_irq", 5484 "dm_hs_phy_irq", 5485 "ss_phy_irq"; 5486 5487 power-domains = <&gcc USB30_PRIM_GDSC>; 5488 5489 resets = <&gcc GCC_USB30_PRIM_BCR>; 5490 5491 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 5492 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 5493 interconnect-names = "usb-ddr", "apps-usb"; 5494 5495 iommus = <&apps_smmu 0x0 0x0>; 5496 snps,dis_u2_susphy_quirk; 5497 snps,dis_u3_susphy_quirk; 5498 snps,dis_enblslpm_quirk; 5499 snps,dis-u1-entry-quirk; 5500 snps,dis-u2-entry-quirk; 5501 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 5502 phy-names = "usb2-phy", "usb3-phy"; 5503 usb-role-switch; 5504 5505 ports { 5506 #address-cells = <1>; 5507 #size-cells = <0>; 5508 5509 port@0 { 5510 reg = <0>; 5511 5512 usb_1_dwc3_hs: endpoint { 5513 }; 5514 }; 5515 5516 port@1 { 5517 reg = <1>; 5518 5519 usb_1_dwc3_ss: endpoint { 5520 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 5521 }; 5522 }; 5523 }; 5524 }; 5525 5526 nsp_noc: interconnect@320c0000 { 5527 compatible = "qcom,sm8450-nsp-noc"; 5528 reg = <0 0x320c0000 0 0x10000>; 5529 #interconnect-cells = <2>; 5530 qcom,bcm-voters = <&apps_bcm_voter>; 5531 }; 5532 5533 lpass_ag_noc: interconnect@3c40000 { 5534 compatible = "qcom,sm8450-lpass-ag-noc"; 5535 reg = <0 0x03c40000 0 0x17200>; 5536 #interconnect-cells = <2>; 5537 qcom,bcm-voters = <&apps_bcm_voter>; 5538 }; 5539 }; 5540 5541 sound: sound { 5542 }; 5543 5544 thermal-zones { 5545 aoss0-thermal { 5546 thermal-sensors = <&tsens0 0>; 5547 5548 trips { 5549 thermal-engine-config { 5550 temperature = <125000>; 5551 hysteresis = <1000>; 5552 type = "passive"; 5553 }; 5554 5555 reset-mon-cfg { 5556 temperature = <115000>; 5557 hysteresis = <5000>; 5558 type = "passive"; 5559 }; 5560 }; 5561 }; 5562 5563 cpuss0-thermal { 5564 thermal-sensors = <&tsens0 1>; 5565 5566 trips { 5567 thermal-engine-config { 5568 temperature = <125000>; 5569 hysteresis = <1000>; 5570 type = "passive"; 5571 }; 5572 5573 reset-mon-cfg { 5574 temperature = <115000>; 5575 hysteresis = <5000>; 5576 type = "passive"; 5577 }; 5578 }; 5579 }; 5580 5581 cpuss1-thermal { 5582 thermal-sensors = <&tsens0 2>; 5583 5584 trips { 5585 thermal-engine-config { 5586 temperature = <125000>; 5587 hysteresis = <1000>; 5588 type = "passive"; 5589 }; 5590 5591 reset-mon-cfg { 5592 temperature = <115000>; 5593 hysteresis = <5000>; 5594 type = "passive"; 5595 }; 5596 }; 5597 }; 5598 5599 cpuss3-thermal { 5600 thermal-sensors = <&tsens0 3>; 5601 5602 trips { 5603 thermal-engine-config { 5604 temperature = <125000>; 5605 hysteresis = <1000>; 5606 type = "passive"; 5607 }; 5608 5609 reset-mon-cfg { 5610 temperature = <115000>; 5611 hysteresis = <5000>; 5612 type = "passive"; 5613 }; 5614 }; 5615 }; 5616 5617 cpuss4-thermal { 5618 thermal-sensors = <&tsens0 4>; 5619 5620 trips { 5621 thermal-engine-config { 5622 temperature = <125000>; 5623 hysteresis = <1000>; 5624 type = "passive"; 5625 }; 5626 5627 reset-mon-cfg { 5628 temperature = <115000>; 5629 hysteresis = <5000>; 5630 type = "passive"; 5631 }; 5632 }; 5633 }; 5634 5635 cpu4-top-thermal { 5636 thermal-sensors = <&tsens0 5>; 5637 5638 trips { 5639 cpu4_top_alert0: trip-point0 { 5640 temperature = <90000>; 5641 hysteresis = <2000>; 5642 type = "passive"; 5643 }; 5644 5645 cpu4_top_alert1: trip-point1 { 5646 temperature = <95000>; 5647 hysteresis = <2000>; 5648 type = "passive"; 5649 }; 5650 5651 cpu4_top_crit: cpu-crit { 5652 temperature = <110000>; 5653 hysteresis = <1000>; 5654 type = "critical"; 5655 }; 5656 }; 5657 }; 5658 5659 cpu4-bottom-thermal { 5660 thermal-sensors = <&tsens0 6>; 5661 5662 trips { 5663 cpu4_bottom_alert0: trip-point0 { 5664 temperature = <90000>; 5665 hysteresis = <2000>; 5666 type = "passive"; 5667 }; 5668 5669 cpu4_bottom_alert1: trip-point1 { 5670 temperature = <95000>; 5671 hysteresis = <2000>; 5672 type = "passive"; 5673 }; 5674 5675 cpu4_bottom_crit: cpu-crit { 5676 temperature = <110000>; 5677 hysteresis = <1000>; 5678 type = "critical"; 5679 }; 5680 }; 5681 }; 5682 5683 cpu5-top-thermal { 5684 thermal-sensors = <&tsens0 7>; 5685 5686 trips { 5687 cpu5_top_alert0: trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "passive"; 5691 }; 5692 5693 cpu5_top_alert1: trip-point1 { 5694 temperature = <95000>; 5695 hysteresis = <2000>; 5696 type = "passive"; 5697 }; 5698 5699 cpu5_top_crit: cpu-crit { 5700 temperature = <110000>; 5701 hysteresis = <1000>; 5702 type = "critical"; 5703 }; 5704 }; 5705 }; 5706 5707 cpu5-bottom-thermal { 5708 thermal-sensors = <&tsens0 8>; 5709 5710 trips { 5711 cpu5_bottom_alert0: trip-point0 { 5712 temperature = <90000>; 5713 hysteresis = <2000>; 5714 type = "passive"; 5715 }; 5716 5717 cpu5_bottom_alert1: trip-point1 { 5718 temperature = <95000>; 5719 hysteresis = <2000>; 5720 type = "passive"; 5721 }; 5722 5723 cpu5_bottom_crit: cpu-crit { 5724 temperature = <110000>; 5725 hysteresis = <1000>; 5726 type = "critical"; 5727 }; 5728 }; 5729 }; 5730 5731 cpu6-top-thermal { 5732 thermal-sensors = <&tsens0 9>; 5733 5734 trips { 5735 cpu6_top_alert0: trip-point0 { 5736 temperature = <90000>; 5737 hysteresis = <2000>; 5738 type = "passive"; 5739 }; 5740 5741 cpu6_top_alert1: trip-point1 { 5742 temperature = <95000>; 5743 hysteresis = <2000>; 5744 type = "passive"; 5745 }; 5746 5747 cpu6_top_crit: cpu-crit { 5748 temperature = <110000>; 5749 hysteresis = <1000>; 5750 type = "critical"; 5751 }; 5752 }; 5753 }; 5754 5755 cpu6-bottom-thermal { 5756 thermal-sensors = <&tsens0 10>; 5757 5758 trips { 5759 cpu6_bottom_alert0: trip-point0 { 5760 temperature = <90000>; 5761 hysteresis = <2000>; 5762 type = "passive"; 5763 }; 5764 5765 cpu6_bottom_alert1: trip-point1 { 5766 temperature = <95000>; 5767 hysteresis = <2000>; 5768 type = "passive"; 5769 }; 5770 5771 cpu6_bottom_crit: cpu-crit { 5772 temperature = <110000>; 5773 hysteresis = <1000>; 5774 type = "critical"; 5775 }; 5776 }; 5777 }; 5778 5779 cpu7-top-thermal { 5780 thermal-sensors = <&tsens0 11>; 5781 5782 trips { 5783 cpu7_top_alert0: trip-point0 { 5784 temperature = <90000>; 5785 hysteresis = <2000>; 5786 type = "passive"; 5787 }; 5788 5789 cpu7_top_alert1: trip-point1 { 5790 temperature = <95000>; 5791 hysteresis = <2000>; 5792 type = "passive"; 5793 }; 5794 5795 cpu7_top_crit: cpu-crit { 5796 temperature = <110000>; 5797 hysteresis = <1000>; 5798 type = "critical"; 5799 }; 5800 }; 5801 }; 5802 5803 cpu7-middle-thermal { 5804 thermal-sensors = <&tsens0 12>; 5805 5806 trips { 5807 cpu7_middle_alert0: trip-point0 { 5808 temperature = <90000>; 5809 hysteresis = <2000>; 5810 type = "passive"; 5811 }; 5812 5813 cpu7_middle_alert1: trip-point1 { 5814 temperature = <95000>; 5815 hysteresis = <2000>; 5816 type = "passive"; 5817 }; 5818 5819 cpu7_middle_crit: cpu-crit { 5820 temperature = <110000>; 5821 hysteresis = <1000>; 5822 type = "critical"; 5823 }; 5824 }; 5825 }; 5826 5827 cpu7-bottom-thermal { 5828 thermal-sensors = <&tsens0 13>; 5829 5830 trips { 5831 cpu7_bottom_alert0: trip-point0 { 5832 temperature = <90000>; 5833 hysteresis = <2000>; 5834 type = "passive"; 5835 }; 5836 5837 cpu7_bottom_alert1: trip-point1 { 5838 temperature = <95000>; 5839 hysteresis = <2000>; 5840 type = "passive"; 5841 }; 5842 5843 cpu7_bottom_crit: cpu-crit { 5844 temperature = <110000>; 5845 hysteresis = <1000>; 5846 type = "critical"; 5847 }; 5848 }; 5849 }; 5850 5851 gpu-top-thermal { 5852 polling-delay-passive = <10>; 5853 5854 thermal-sensors = <&tsens0 14>; 5855 5856 cooling-maps { 5857 map0 { 5858 trip = <&gpu_top_alert0>; 5859 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5860 }; 5861 }; 5862 5863 trips { 5864 gpu_top_alert0: trip-point0 { 5865 temperature = <85000>; 5866 hysteresis = <1000>; 5867 type = "passive"; 5868 }; 5869 5870 trip-point1 { 5871 temperature = <90000>; 5872 hysteresis = <1000>; 5873 type = "hot"; 5874 }; 5875 5876 trip-point2 { 5877 temperature = <110000>; 5878 hysteresis = <1000>; 5879 type = "critical"; 5880 }; 5881 }; 5882 }; 5883 5884 gpu-bottom-thermal { 5885 polling-delay-passive = <10>; 5886 5887 thermal-sensors = <&tsens0 15>; 5888 5889 cooling-maps { 5890 map0 { 5891 trip = <&gpu_bottom_alert0>; 5892 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5893 }; 5894 }; 5895 5896 trips { 5897 gpu_bottom_alert0: trip-point0 { 5898 temperature = <85000>; 5899 hysteresis = <1000>; 5900 type = "passive"; 5901 }; 5902 5903 trip-point1 { 5904 temperature = <90000>; 5905 hysteresis = <1000>; 5906 type = "hot"; 5907 }; 5908 5909 trip-point2 { 5910 temperature = <110000>; 5911 hysteresis = <1000>; 5912 type = "critical"; 5913 }; 5914 }; 5915 }; 5916 5917 aoss1-thermal { 5918 thermal-sensors = <&tsens1 0>; 5919 5920 trips { 5921 thermal-engine-config { 5922 temperature = <125000>; 5923 hysteresis = <1000>; 5924 type = "passive"; 5925 }; 5926 5927 reset-mon-cfg { 5928 temperature = <115000>; 5929 hysteresis = <5000>; 5930 type = "passive"; 5931 }; 5932 }; 5933 }; 5934 5935 cpu0-thermal { 5936 thermal-sensors = <&tsens1 1>; 5937 5938 trips { 5939 cpu0_alert0: trip-point0 { 5940 temperature = <90000>; 5941 hysteresis = <2000>; 5942 type = "passive"; 5943 }; 5944 5945 cpu0_alert1: trip-point1 { 5946 temperature = <95000>; 5947 hysteresis = <2000>; 5948 type = "passive"; 5949 }; 5950 5951 cpu0_crit: cpu-crit { 5952 temperature = <110000>; 5953 hysteresis = <1000>; 5954 type = "critical"; 5955 }; 5956 }; 5957 }; 5958 5959 cpu1-thermal { 5960 thermal-sensors = <&tsens1 2>; 5961 5962 trips { 5963 cpu1_alert0: trip-point0 { 5964 temperature = <90000>; 5965 hysteresis = <2000>; 5966 type = "passive"; 5967 }; 5968 5969 cpu1_alert1: trip-point1 { 5970 temperature = <95000>; 5971 hysteresis = <2000>; 5972 type = "passive"; 5973 }; 5974 5975 cpu1_crit: cpu-crit { 5976 temperature = <110000>; 5977 hysteresis = <1000>; 5978 type = "critical"; 5979 }; 5980 }; 5981 }; 5982 5983 cpu2-thermal { 5984 thermal-sensors = <&tsens1 3>; 5985 5986 trips { 5987 cpu2_alert0: trip-point0 { 5988 temperature = <90000>; 5989 hysteresis = <2000>; 5990 type = "passive"; 5991 }; 5992 5993 cpu2_alert1: trip-point1 { 5994 temperature = <95000>; 5995 hysteresis = <2000>; 5996 type = "passive"; 5997 }; 5998 5999 cpu2_crit: cpu-crit { 6000 temperature = <110000>; 6001 hysteresis = <1000>; 6002 type = "critical"; 6003 }; 6004 }; 6005 }; 6006 6007 cpu3-thermal { 6008 thermal-sensors = <&tsens1 4>; 6009 6010 trips { 6011 cpu3_alert0: trip-point0 { 6012 temperature = <90000>; 6013 hysteresis = <2000>; 6014 type = "passive"; 6015 }; 6016 6017 cpu3_alert1: trip-point1 { 6018 temperature = <95000>; 6019 hysteresis = <2000>; 6020 type = "passive"; 6021 }; 6022 6023 cpu3_crit: cpu-crit { 6024 temperature = <110000>; 6025 hysteresis = <1000>; 6026 type = "critical"; 6027 }; 6028 }; 6029 }; 6030 6031 cdsp0-thermal { 6032 polling-delay-passive = <10>; 6033 6034 thermal-sensors = <&tsens1 5>; 6035 6036 trips { 6037 thermal-engine-config { 6038 temperature = <125000>; 6039 hysteresis = <1000>; 6040 type = "passive"; 6041 }; 6042 6043 thermal-hal-config { 6044 temperature = <125000>; 6045 hysteresis = <1000>; 6046 type = "passive"; 6047 }; 6048 6049 reset-mon-cfg { 6050 temperature = <115000>; 6051 hysteresis = <5000>; 6052 type = "passive"; 6053 }; 6054 6055 cdsp_0_config: junction-config { 6056 temperature = <95000>; 6057 hysteresis = <5000>; 6058 type = "passive"; 6059 }; 6060 }; 6061 }; 6062 6063 cdsp1-thermal { 6064 polling-delay-passive = <10>; 6065 6066 thermal-sensors = <&tsens1 6>; 6067 6068 trips { 6069 thermal-engine-config { 6070 temperature = <125000>; 6071 hysteresis = <1000>; 6072 type = "passive"; 6073 }; 6074 6075 thermal-hal-config { 6076 temperature = <125000>; 6077 hysteresis = <1000>; 6078 type = "passive"; 6079 }; 6080 6081 reset-mon-cfg { 6082 temperature = <115000>; 6083 hysteresis = <5000>; 6084 type = "passive"; 6085 }; 6086 6087 cdsp_1_config: junction-config { 6088 temperature = <95000>; 6089 hysteresis = <5000>; 6090 type = "passive"; 6091 }; 6092 }; 6093 }; 6094 6095 cdsp2-thermal { 6096 polling-delay-passive = <10>; 6097 6098 thermal-sensors = <&tsens1 7>; 6099 6100 trips { 6101 thermal-engine-config { 6102 temperature = <125000>; 6103 hysteresis = <1000>; 6104 type = "passive"; 6105 }; 6106 6107 thermal-hal-config { 6108 temperature = <125000>; 6109 hysteresis = <1000>; 6110 type = "passive"; 6111 }; 6112 6113 reset-mon-cfg { 6114 temperature = <115000>; 6115 hysteresis = <5000>; 6116 type = "passive"; 6117 }; 6118 6119 cdsp_2_config: junction-config { 6120 temperature = <95000>; 6121 hysteresis = <5000>; 6122 type = "passive"; 6123 }; 6124 }; 6125 }; 6126 6127 video-thermal { 6128 thermal-sensors = <&tsens1 8>; 6129 6130 trips { 6131 thermal-engine-config { 6132 temperature = <125000>; 6133 hysteresis = <1000>; 6134 type = "passive"; 6135 }; 6136 6137 reset-mon-cfg { 6138 temperature = <115000>; 6139 hysteresis = <5000>; 6140 type = "passive"; 6141 }; 6142 }; 6143 }; 6144 6145 mem-thermal { 6146 polling-delay-passive = <10>; 6147 6148 thermal-sensors = <&tsens1 9>; 6149 6150 trips { 6151 thermal-engine-config { 6152 temperature = <125000>; 6153 hysteresis = <1000>; 6154 type = "passive"; 6155 }; 6156 6157 ddr_config0: ddr0-config { 6158 temperature = <90000>; 6159 hysteresis = <5000>; 6160 type = "passive"; 6161 }; 6162 6163 reset-mon-cfg { 6164 temperature = <115000>; 6165 hysteresis = <5000>; 6166 type = "passive"; 6167 }; 6168 }; 6169 }; 6170 6171 modem0-thermal { 6172 thermal-sensors = <&tsens1 10>; 6173 6174 trips { 6175 thermal-engine-config { 6176 temperature = <125000>; 6177 hysteresis = <1000>; 6178 type = "passive"; 6179 }; 6180 6181 mdmss0_config0: mdmss0-config0 { 6182 temperature = <102000>; 6183 hysteresis = <3000>; 6184 type = "passive"; 6185 }; 6186 6187 mdmss0_config1: mdmss0-config1 { 6188 temperature = <105000>; 6189 hysteresis = <3000>; 6190 type = "passive"; 6191 }; 6192 6193 reset-mon-cfg { 6194 temperature = <115000>; 6195 hysteresis = <5000>; 6196 type = "passive"; 6197 }; 6198 }; 6199 }; 6200 6201 modem1-thermal { 6202 thermal-sensors = <&tsens1 11>; 6203 6204 trips { 6205 thermal-engine-config { 6206 temperature = <125000>; 6207 hysteresis = <1000>; 6208 type = "passive"; 6209 }; 6210 6211 mdmss1_config0: mdmss1-config0 { 6212 temperature = <102000>; 6213 hysteresis = <3000>; 6214 type = "passive"; 6215 }; 6216 6217 mdmss1_config1: mdmss1-config1 { 6218 temperature = <105000>; 6219 hysteresis = <3000>; 6220 type = "passive"; 6221 }; 6222 6223 reset-mon-cfg { 6224 temperature = <115000>; 6225 hysteresis = <5000>; 6226 type = "passive"; 6227 }; 6228 }; 6229 }; 6230 6231 modem2-thermal { 6232 thermal-sensors = <&tsens1 12>; 6233 6234 trips { 6235 thermal-engine-config { 6236 temperature = <125000>; 6237 hysteresis = <1000>; 6238 type = "passive"; 6239 }; 6240 6241 mdmss2_config0: mdmss2-config0 { 6242 temperature = <102000>; 6243 hysteresis = <3000>; 6244 type = "passive"; 6245 }; 6246 6247 mdmss2_config1: mdmss2-config1 { 6248 temperature = <105000>; 6249 hysteresis = <3000>; 6250 type = "passive"; 6251 }; 6252 6253 reset-mon-cfg { 6254 temperature = <115000>; 6255 hysteresis = <5000>; 6256 type = "passive"; 6257 }; 6258 }; 6259 }; 6260 6261 modem3-thermal { 6262 thermal-sensors = <&tsens1 13>; 6263 6264 trips { 6265 thermal-engine-config { 6266 temperature = <125000>; 6267 hysteresis = <1000>; 6268 type = "passive"; 6269 }; 6270 6271 mdmss3_config0: mdmss3-config0 { 6272 temperature = <102000>; 6273 hysteresis = <3000>; 6274 type = "passive"; 6275 }; 6276 6277 mdmss3_config1: mdmss3-config1 { 6278 temperature = <105000>; 6279 hysteresis = <3000>; 6280 type = "passive"; 6281 }; 6282 6283 reset-mon-cfg { 6284 temperature = <115000>; 6285 hysteresis = <5000>; 6286 type = "passive"; 6287 }; 6288 }; 6289 }; 6290 6291 camera0-thermal { 6292 thermal-sensors = <&tsens1 14>; 6293 6294 trips { 6295 thermal-engine-config { 6296 temperature = <125000>; 6297 hysteresis = <1000>; 6298 type = "passive"; 6299 }; 6300 6301 reset-mon-cfg { 6302 temperature = <115000>; 6303 hysteresis = <5000>; 6304 type = "passive"; 6305 }; 6306 }; 6307 }; 6308 6309 camera1-thermal { 6310 thermal-sensors = <&tsens1 15>; 6311 6312 trips { 6313 thermal-engine-config { 6314 temperature = <125000>; 6315 hysteresis = <1000>; 6316 type = "passive"; 6317 }; 6318 6319 reset-mon-cfg { 6320 temperature = <115000>; 6321 hysteresis = <5000>; 6322 type = "passive"; 6323 }; 6324 }; 6325 }; 6326 }; 6327 6328 timer { 6329 compatible = "arm,armv8-timer"; 6330 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6331 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6332 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6333 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6334 clock-frequency = <19200000>; 6335 }; 6336}; 6337