1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Product Link: https://www.ti.com/tool/J721EXCPXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e-som-p0.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14#include <dt-bindings/phy/phy-cadence.h> 15 16/ { 17 compatible = "ti,j721e-evm", "ti,j721e"; 18 model = "Texas Instruments J721e EVM"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 serial6 = &main_uart4; 27 ethernet0 = &cpsw_port1; 28 mmc0 = &main_sdhci0; 29 mmc1 = &main_sdhci1; 30 }; 31 32 chosen { 33 stdout-path = "serial2:115200n8"; 34 }; 35 36 gpio_keys: gpio-keys { 37 compatible = "gpio-keys"; 38 autorepeat; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; 41 42 sw10: switch-10 { 43 label = "GPIO Key USER1"; 44 linux,code = <BTN_0>; 45 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 46 }; 47 48 sw11: switch-11 { 49 label = "GPIO Key USER2"; 50 linux,code = <BTN_1>; 51 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 52 }; 53 }; 54 55 evm_12v0: fixedregulator-evm12v0 { 56 /* main supply */ 57 compatible = "regulator-fixed"; 58 regulator-name = "evm_12v0"; 59 regulator-min-microvolt = <12000000>; 60 regulator-max-microvolt = <12000000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 vsys_3v3: fixedregulator-vsys3v3 { 66 /* Output of LMS140 */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vsys_3v3"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&evm_12v0>; 72 regulator-always-on; 73 regulator-boot-on; 74 }; 75 76 vsys_5v0: fixedregulator-vsys5v0 { 77 /* Output of LM5140 */ 78 compatible = "regulator-fixed"; 79 regulator-name = "vsys_5v0"; 80 regulator-min-microvolt = <5000000>; 81 regulator-max-microvolt = <5000000>; 82 vin-supply = <&evm_12v0>; 83 regulator-always-on; 84 regulator-boot-on; 85 }; 86 87 vdd_mmc1: fixedregulator-sd { 88 compatible = "regulator-fixed"; 89 regulator-name = "vdd_mmc1"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-boot-on; 93 enable-active-high; 94 vin-supply = <&vsys_3v3>; 95 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 96 }; 97 98 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 99 compatible = "regulator-gpio"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 102 regulator-name = "tlv71033"; 103 regulator-min-microvolt = <1800000>; 104 regulator-max-microvolt = <3300000>; 105 regulator-boot-on; 106 vin-supply = <&vsys_5v0>; 107 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 108 states = <1800000 0x0>, 109 <3300000 0x1>; 110 }; 111 112 sound0: sound-0 { 113 compatible = "ti,j721e-cpb-audio"; 114 model = "j721e-cpb"; 115 116 ti,cpb-mcasp = <&mcasp10>; 117 ti,cpb-codec = <&pcm3168a_1>; 118 119 clocks = <&k3_clks 184 1>, 120 <&k3_clks 184 2>, <&k3_clks 184 4>, 121 <&k3_clks 157 371>, 122 <&k3_clks 157 400>, <&k3_clks 157 401>; 123 clock-names = "cpb-mcasp-auxclk", 124 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 125 "cpb-codec-scki", 126 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 127 }; 128 129 transceiver1: can-phy0 { 130 compatible = "ti,tcan1043"; 131 #phy-cells = <0>; 132 max-bitrate = <5000000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 135 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; 136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 137 }; 138 139 transceiver2: can-phy1 { 140 compatible = "ti,tcan1042"; 141 #phy-cells = <0>; 142 max-bitrate = <5000000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 145 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 146 }; 147 148 transceiver3: can-phy2 { 149 compatible = "ti,tcan1043"; 150 #phy-cells = <0>; 151 max-bitrate = <5000000>; 152 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 153 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 154 }; 155 156 transceiver4: can-phy3 { 157 compatible = "ti,tcan1042"; 158 #phy-cells = <0>; 159 max-bitrate = <5000000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&main_mcan2_gpio_pins_default>; 162 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; 163 }; 164 165 dp_pwr_3v3: regulator-dp-pwr { 166 compatible = "regulator-fixed"; 167 regulator-name = "dp-pwr"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ 171 enable-active-high; 172 }; 173 174 dp0: connector { 175 compatible = "dp-connector"; 176 label = "DP0"; 177 type = "full-size"; 178 dp-pwr-supply = <&dp_pwr_3v3>; 179 180 port { 181 dp_connector_in: endpoint { 182 remote-endpoint = <&dp0_out>; 183 }; 184 }; 185 }; 186}; 187 188&main_pmx0 { 189 main_uart0_pins_default: main-uart0-default-pins { 190 pinctrl-single,pins = < 191 J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ 192 J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ 193 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 194 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 195 >; 196 bootph-all; 197 }; 198 199 main_uart1_pins_default: main-uart1-default-pins { 200 pinctrl-single,pins = < 201 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 202 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 203 >; 204 }; 205 206 main_uart2_pins_default: main-uart2-default-pins { 207 pinctrl-single,pins = < 208 J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ 209 J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ 210 >; 211 }; 212 213 main_uart4_pins_default: main-uart4-default-pins { 214 pinctrl-single,pins = < 215 J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ 216 J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ 217 >; 218 }; 219 220 sw10_button_pins_default: sw10-button-default-pins { 221 pinctrl-single,pins = < 222 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 223 >; 224 }; 225 226 main_mmc1_pins_default: main-mmc1-default-pins { 227 pinctrl-single,pins = < 228 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 229 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 230 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 231 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 232 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 233 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 234 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 235 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 236 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 237 >; 238 bootph-all; 239 }; 240 241 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 242 pinctrl-single,pins = < 243 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 244 >; 245 }; 246 247 main_usbss0_pins_default: main-usbss0-default-pins { 248 pinctrl-single,pins = < 249 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 250 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 251 >; 252 bootph-all; 253 }; 254 255 main_usbss1_pins_default: main-usbss1-default-pins { 256 pinctrl-single,pins = < 257 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 258 >; 259 }; 260 261 dp0_pins_default: dp0-default-pins { 262 pinctrl-single,pins = < 263 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 264 >; 265 }; 266 267 main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { 268 pinctrl-single,pins = < 269 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 270 >; 271 }; 272 273 main_i2c0_pins_default: main-i2c0-default-pins { 274 pinctrl-single,pins = < 275 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 276 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 277 >; 278 }; 279 280 main_i2c1_pins_default: main-i2c1-default-pins { 281 pinctrl-single,pins = < 282 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 283 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 284 >; 285 }; 286 287 main_i2c3_pins_default: main-i2c3-default-pins { 288 pinctrl-single,pins = < 289 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 290 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 291 >; 292 }; 293 294 main_i2c6_pins_default: main-i2c6-default-pins { 295 pinctrl-single,pins = < 296 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 297 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 298 >; 299 }; 300 301 mcasp10_pins_default: mcasp10-default-pins { 302 pinctrl-single,pins = < 303 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 304 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 305 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 306 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 307 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 308 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 309 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 310 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 311 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 312 >; 313 }; 314 315 audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { 316 pinctrl-single,pins = < 317 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 318 >; 319 }; 320 321 main_mcan0_pins_default: main-mcan0-default-pins { 322 pinctrl-single,pins = < 323 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 324 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 325 >; 326 }; 327 328 main_mcan2_pins_default: main-mcan2-default-pins { 329 pinctrl-single,pins = < 330 J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ 331 J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ 332 >; 333 }; 334 335 main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { 336 pinctrl-single,pins = < 337 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 338 >; 339 }; 340}; 341 342&wkup_pmx0 { 343 wkup_uart0_pins_default: wkup-uart0-default-pins { 344 pinctrl-single,pins = < 345 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 346 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 347 >; 348 bootph-all; 349 }; 350 351 mcu_uart0_pins_default: mcu-uart0-default-pins { 352 pinctrl-single,pins = < 353 J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ 354 J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ 355 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 356 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 357 >; 358 bootph-all; 359 }; 360 361 sw11_button_pins_default: sw11-button-default-pins { 362 pinctrl-single,pins = < 363 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 364 >; 365 }; 366 367 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 368 pinctrl-single,pins = < 369 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 370 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 371 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 372 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 373 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 374 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 375 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 376 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 377 >; 378 bootph-all; 379 }; 380 381 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 382 pinctrl-single,pins = < 383 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 384 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 385 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 386 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 387 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 388 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 389 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 390 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 391 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 392 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 393 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 394 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 395 >; 396 }; 397 398 mcu_mdio_pins_default: mcu-mdio1-default-pins { 399 pinctrl-single,pins = < 400 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 401 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 402 >; 403 }; 404 405 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 406 pinctrl-single,pins = < 407 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 408 J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 409 >; 410 }; 411 412 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 413 pinctrl-single,pins = < 414 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ 415 J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ 416 >; 417 }; 418 419 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 420 pinctrl-single,pins = < 421 J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ 422 J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ 423 >; 424 }; 425 426 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 427 pinctrl-single,pins = < 428 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ 429 >; 430 }; 431 432 wkup_gpio_pins_default: wkup-gpio-default-pins { 433 pinctrl-single,pins = < 434 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ 435 >; 436 }; 437}; 438 439&wkup_uart0 { 440 /* Wakeup UART is used by System firmware */ 441 status = "reserved"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&wkup_uart0_pins_default>; 444 bootph-all; 445}; 446 447&mcu_uart0 { 448 status = "okay"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&mcu_uart0_pins_default>; 451 bootph-all; 452}; 453 454&main_uart0 { 455 status = "okay"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&main_uart0_pins_default>; 458 /* Shared with ATF on this platform */ 459 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 460 bootph-all; 461}; 462 463&main_uart1 { 464 status = "okay"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&main_uart1_pins_default>; 467}; 468 469&main_uart2 { 470 status = "okay"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&main_uart2_pins_default>; 473}; 474 475&main_uart4 { 476 status = "okay"; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&main_uart4_pins_default>; 479}; 480 481&wkup_gpio0 { 482 status = "okay"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&wkup_gpio_pins_default>; 485}; 486 487&main_gpio0 { 488 status = "okay"; 489}; 490 491&main_gpio1 { 492 status = "okay"; 493}; 494 495&main_sdhci0 { 496 /* eMMC */ 497 status = "okay"; 498 non-removable; 499 bootph-all; 500 ti,driver-strength-ohm = <50>; 501 disable-wp; 502}; 503 504&main_sdhci1 { 505 /* SD/MMC */ 506 status = "okay"; 507 vmmc-supply = <&vdd_mmc1>; 508 vqmmc-supply = <&vdd_sd_dv_alt>; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&main_mmc1_pins_default>; 511 bootph-all; 512 ti,driver-strength-ohm = <50>; 513 disable-wp; 514}; 515 516&usb_serdes_mux { 517 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 518 bootph-all; 519}; 520 521&serdes_ln_ctrl { 522 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 523 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 524 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 525 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 526 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 527 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 528 bootph-all; 529}; 530 531&serdes_wiz3 { 532 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 533 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 534}; 535 536&serdes3 { 537 serdes3_usb_link: phy@0 { 538 reg = <0>; 539 cdns,num-lanes = <2>; 540 #phy-cells = <0>; 541 cdns,phy-type = <PHY_TYPE_USB3>; 542 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 543 bootph-all; 544 }; 545}; 546 547&usbss0 { 548 pinctrl-names = "default"; 549 pinctrl-0 = <&main_usbss0_pins_default>; 550 bootph-all; 551 ti,vbus-divider; 552}; 553 554&usb0 { 555 dr_mode = "otg"; 556 maximum-speed = "super-speed"; 557 phys = <&serdes3_usb_link>; 558 phy-names = "cdns3,usb3-phy"; 559 bootph-all; 560}; 561 562&usbss1 { 563 pinctrl-names = "default"; 564 pinctrl-0 = <&main_usbss1_pins_default>; 565 ti,usb2-only; 566}; 567 568&usb1 { 569 dr_mode = "host"; 570 maximum-speed = "high-speed"; 571}; 572 573&ospi1 { 574 pinctrl-names = "default"; 575 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 576 status = "okay"; 577 578 flash@0 { 579 compatible = "jedec,spi-nor"; 580 reg = <0x0>; 581 spi-tx-bus-width = <1>; 582 spi-rx-bus-width = <4>; 583 spi-max-frequency = <40000000>; 584 cdns,tshsl-ns = <60>; 585 cdns,tsd2d-ns = <60>; 586 cdns,tchsh-ns = <60>; 587 cdns,tslch-ns = <60>; 588 cdns,read-delay = <2>; 589 590 partitions { 591 compatible = "fixed-partitions"; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 595 partition@0 { 596 label = "qspi.tiboot3"; 597 reg = <0x0 0x80000>; 598 }; 599 600 partition@80000 { 601 label = "qspi.tispl"; 602 reg = <0x80000 0x200000>; 603 }; 604 605 partition@280000 { 606 label = "qspi.u-boot"; 607 reg = <0x280000 0x400000>; 608 }; 609 610 partition@680000 { 611 label = "qspi.env"; 612 reg = <0x680000 0x20000>; 613 }; 614 615 partition@6a0000 { 616 label = "qspi.env.backup"; 617 reg = <0x6a0000 0x20000>; 618 }; 619 620 partition@6c0000 { 621 label = "qspi.sysfw"; 622 reg = <0x6c0000 0x100000>; 623 }; 624 625 partition@800000 { 626 label = "qspi.rootfs"; 627 reg = <0x800000 0x37c0000>; 628 }; 629 630 partition@3fe0000 { 631 label = "qspi.phypattern"; 632 reg = <0x3fe0000 0x20000>; 633 bootph-all; 634 }; 635 }; 636 }; 637}; 638 639&tscadc0 { 640 status = "okay"; 641 adc { 642 ti,adc-channels = <0 1 2 3 4 5 6 7>; 643 }; 644}; 645 646&tscadc1 { 647 status = "okay"; 648 adc { 649 ti,adc-channels = <0 1 2 3 4 5 6 7>; 650 }; 651}; 652 653&main_i2c0 { 654 status = "okay"; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&main_i2c0_pins_default>; 657 clock-frequency = <400000>; 658 659 exp1: gpio@20 { 660 compatible = "ti,tca6416"; 661 reg = <0x20>; 662 gpio-controller; 663 #gpio-cells = <2>; 664 }; 665 666 exp2: gpio@22 { 667 compatible = "ti,tca6424"; 668 reg = <0x22>; 669 gpio-controller; 670 #gpio-cells = <2>; 671 672 p09-hog { 673 /* P11 - MCASP/TRACE_MUX_S0 */ 674 gpio-hog; 675 gpios = <9 GPIO_ACTIVE_HIGH>; 676 output-low; 677 line-name = "MCASP/TRACE_MUX_S0"; 678 }; 679 680 p10-hog { 681 /* P12 - MCASP/TRACE_MUX_S1 */ 682 gpio-hog; 683 gpios = <10 GPIO_ACTIVE_HIGH>; 684 output-high; 685 line-name = "MCASP/TRACE_MUX_S1"; 686 }; 687 }; 688}; 689 690&main_i2c1 { 691 status = "okay"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&main_i2c1_pins_default>; 694 clock-frequency = <400000>; 695 696 exp4: gpio@20 { 697 compatible = "ti,tca6408"; 698 reg = <0x20>; 699 gpio-controller; 700 #gpio-cells = <2>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 703 interrupt-parent = <&main_gpio1>; 704 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 705 interrupt-controller; 706 #interrupt-cells = <2>; 707 }; 708}; 709 710&k3_clks { 711 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 712 pinctrl-names = "default"; 713 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 714}; 715 716&main_i2c3 { 717 status = "okay"; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&main_i2c3_pins_default>; 720 clock-frequency = <400000>; 721 722 exp3: gpio@20 { 723 compatible = "ti,tca6408"; 724 reg = <0x20>; 725 gpio-controller; 726 #gpio-cells = <2>; 727 }; 728 729 pcm3168a_1: audio-codec@44 { 730 compatible = "ti,pcm3168a"; 731 reg = <0x44>; 732 733 #sound-dai-cells = <1>; 734 735 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 736 737 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 738 clocks = <&k3_clks 157 371>; 739 clock-names = "scki"; 740 741 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 742 assigned-clocks = <&k3_clks 157 371>; 743 assigned-clock-parents = <&k3_clks 157 400>; 744 assigned-clock-rates = <24576000>; /* for 48KHz */ 745 746 VDD1-supply = <&vsys_3v3>; 747 VDD2-supply = <&vsys_3v3>; 748 VCCAD1-supply = <&vsys_5v0>; 749 VCCAD2-supply = <&vsys_5v0>; 750 VCCDA1-supply = <&vsys_5v0>; 751 VCCDA2-supply = <&vsys_5v0>; 752 }; 753}; 754 755&main_i2c6 { 756 status = "okay"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&main_i2c6_pins_default>; 759 clock-frequency = <400000>; 760 761 exp5: gpio@20 { 762 compatible = "ti,tca6408"; 763 reg = <0x20>; 764 gpio-controller; 765 #gpio-cells = <2>; 766 }; 767}; 768 769&mcu_cpsw { 770 pinctrl-names = "default"; 771 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 772}; 773 774&davinci_mdio { 775 phy0: ethernet-phy@0 { 776 reg = <0>; 777 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 778 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 779 }; 780}; 781 782&cpsw_port1 { 783 phy-mode = "rgmii-rxid"; 784 phy-handle = <&phy0>; 785}; 786 787&dss { 788 /* 789 * These clock assignments are chosen to enable the following outputs: 790 * 791 * VP0 - DisplayPort SST 792 * VP1 - DPI0 793 * VP2 - DSI 794 * VP3 - DPI1 795 */ 796 797 assigned-clocks = <&k3_clks 152 1>, 798 <&k3_clks 152 4>, 799 <&k3_clks 152 9>, 800 <&k3_clks 152 13>; 801 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 802 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 803 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 804 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 805}; 806 807&dss_ports { 808 #address-cells = <1>; 809 #size-cells = <0>; 810 811 port@0 { 812 reg = <0>; 813 dpi0_out: endpoint { 814 remote-endpoint = <&dp0_in>; 815 }; 816 }; 817}; 818 819&dp0_ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 port@0 { 824 reg = <0>; 825 dp0_in: endpoint { 826 remote-endpoint = <&dpi0_out>; 827 }; 828 }; 829 830 port@4 { 831 reg = <4>; 832 dp0_out: endpoint { 833 remote-endpoint = <&dp_connector_in>; 834 }; 835 }; 836}; 837 838&mcasp10 { 839 status = "okay"; 840 #sound-dai-cells = <0>; 841 842 pinctrl-names = "default"; 843 pinctrl-0 = <&mcasp10_pins_default>; 844 845 op-mode = <0>; /* MCASP_IIS_MODE */ 846 tdm-slots = <2>; 847 auxclk-fs-ratio = <256>; 848 849 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 850 1 1 1 1 851 2 2 2 0 852 >; 853 tx-num-evt = <0>; 854 rx-num-evt = <0>; 855}; 856 857&cmn_refclk1 { 858 clock-frequency = <100000000>; 859}; 860 861&wiz0_pll1_refclk { 862 assigned-clocks = <&wiz0_pll1_refclk>; 863 assigned-clock-parents = <&cmn_refclk1>; 864}; 865 866&wiz0_refclk_dig { 867 assigned-clocks = <&wiz0_refclk_dig>; 868 assigned-clock-parents = <&cmn_refclk1>; 869}; 870 871&wiz1_pll1_refclk { 872 assigned-clocks = <&wiz1_pll1_refclk>; 873 assigned-clock-parents = <&cmn_refclk1>; 874}; 875 876&wiz1_refclk_dig { 877 assigned-clocks = <&wiz1_refclk_dig>; 878 assigned-clock-parents = <&cmn_refclk1>; 879}; 880 881&wiz2_pll1_refclk { 882 assigned-clocks = <&wiz2_pll1_refclk>; 883 assigned-clock-parents = <&cmn_refclk1>; 884}; 885 886&wiz2_refclk_dig { 887 assigned-clocks = <&wiz2_refclk_dig>; 888 assigned-clock-parents = <&cmn_refclk1>; 889}; 890 891&serdes0 { 892 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; 893 assigned-clock-parents = <&wiz0_pll1_refclk>; 894 895 serdes0_pcie_link: phy@0 { 896 reg = <0>; 897 cdns,num-lanes = <1>; 898 #phy-cells = <0>; 899 cdns,phy-type = <PHY_TYPE_PCIE>; 900 resets = <&serdes_wiz0 1>; 901 }; 902}; 903 904&serdes1 { 905 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; 906 assigned-clock-parents = <&wiz1_pll1_refclk>; 907 908 serdes1_pcie_link: phy@0 { 909 reg = <0>; 910 cdns,num-lanes = <2>; 911 #phy-cells = <0>; 912 cdns,phy-type = <PHY_TYPE_PCIE>; 913 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 914 }; 915}; 916 917&serdes2 { 918 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; 919 assigned-clock-parents = <&wiz2_pll1_refclk>; 920 921 serdes2_pcie_link: phy@0 { 922 reg = <0>; 923 cdns,num-lanes = <2>; 924 #phy-cells = <0>; 925 cdns,phy-type = <PHY_TYPE_PCIE>; 926 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 927 }; 928}; 929 930&serdes4 { 931 torrent_phy_dp: phy@0 { 932 reg = <0>; 933 resets = <&serdes_wiz4 1>; 934 cdns,phy-type = <PHY_TYPE_DP>; 935 cdns,num-lanes = <4>; 936 cdns,max-bit-rate = <5400>; 937 #phy-cells = <0>; 938 }; 939}; 940 941&mhdp { 942 phys = <&torrent_phy_dp>; 943 phy-names = "dpphy"; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&dp0_pins_default>; 946}; 947 948&pcie0_rc { 949 status = "okay"; 950 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 951 phys = <&serdes0_pcie_link>; 952 phy-names = "pcie-phy"; 953 num-lanes = <1>; 954}; 955 956&pcie1_rc { 957 status = "okay"; 958 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 959 phys = <&serdes1_pcie_link>; 960 phy-names = "pcie-phy"; 961 num-lanes = <2>; 962}; 963 964&pcie2_rc { 965 status = "okay"; 966 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 967 phys = <&serdes2_pcie_link>; 968 phy-names = "pcie-phy"; 969 num-lanes = <2>; 970}; 971 972&mcu_mcan0 { 973 status = "okay"; 974 pinctrl-names = "default"; 975 pinctrl-0 = <&mcu_mcan0_pins_default>; 976 phys = <&transceiver1>; 977}; 978 979&mcu_mcan1 { 980 status = "okay"; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&mcu_mcan1_pins_default>; 983 phys = <&transceiver2>; 984}; 985 986&main_mcan0 { 987 status = "okay"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&main_mcan0_pins_default>; 990 phys = <&transceiver3>; 991}; 992 993&main_mcan2 { 994 status = "okay"; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&main_mcan2_pins_default>; 997 phys = <&transceiver4>; 998}; 999