1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3
4 #include <linux/sched/clock.h>
5
6 #include "hclge_err.h"
7
8 static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
9 {
10 .int_msk = BIT(1),
11 .msg = "imp_itcm0_ecc_mbit_err",
12 .reset_level = HNAE3_NONE_RESET
13 }, {
14 .int_msk = BIT(3),
15 .msg = "imp_itcm1_ecc_mbit_err",
16 .reset_level = HNAE3_NONE_RESET
17 }, {
18 .int_msk = BIT(5),
19 .msg = "imp_itcm2_ecc_mbit_err",
20 .reset_level = HNAE3_NONE_RESET
21 }, {
22 .int_msk = BIT(7),
23 .msg = "imp_itcm3_ecc_mbit_err",
24 .reset_level = HNAE3_NONE_RESET
25 }, {
26 .int_msk = BIT(9),
27 .msg = "imp_dtcm0_mem0_ecc_mbit_err",
28 .reset_level = HNAE3_NONE_RESET
29 }, {
30 .int_msk = BIT(11),
31 .msg = "imp_dtcm0_mem1_ecc_mbit_err",
32 .reset_level = HNAE3_NONE_RESET
33 }, {
34 .int_msk = BIT(13),
35 .msg = "imp_dtcm1_mem0_ecc_mbit_err",
36 .reset_level = HNAE3_NONE_RESET
37 }, {
38 .int_msk = BIT(15),
39 .msg = "imp_dtcm1_mem1_ecc_mbit_err",
40 .reset_level = HNAE3_NONE_RESET
41 }, {
42 .int_msk = BIT(17),
43 .msg = "imp_itcm4_ecc_mbit_err",
44 .reset_level = HNAE3_NONE_RESET
45 }, {
46 /* sentinel */
47 }
48 };
49
50 static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
51 {
52 .int_msk = BIT(1),
53 .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
54 .reset_level = HNAE3_NONE_RESET
55 }, {
56 .int_msk = BIT(3),
57 .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
58 .reset_level = HNAE3_NONE_RESET
59 }, {
60 .int_msk = BIT(5),
61 .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
62 .reset_level = HNAE3_NONE_RESET
63 }, {
64 .int_msk = BIT(7),
65 .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
66 .reset_level = HNAE3_NONE_RESET
67 }, {
68 .int_msk = BIT(9),
69 .msg = "cmdq_nic_rx_head_ecc_mbit_err",
70 .reset_level = HNAE3_NONE_RESET
71 }, {
72 .int_msk = BIT(11),
73 .msg = "cmdq_nic_tx_head_ecc_mbit_err",
74 .reset_level = HNAE3_NONE_RESET
75 }, {
76 .int_msk = BIT(13),
77 .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
78 .reset_level = HNAE3_NONE_RESET
79 }, {
80 .int_msk = BIT(15),
81 .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
82 .reset_level = HNAE3_NONE_RESET
83 }, {
84 .int_msk = BIT(17),
85 .msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
86 .reset_level = HNAE3_NONE_RESET
87 }, {
88 .int_msk = BIT(19),
89 .msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
90 .reset_level = HNAE3_NONE_RESET
91 }, {
92 .int_msk = BIT(21),
93 .msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
94 .reset_level = HNAE3_NONE_RESET
95 }, {
96 .int_msk = BIT(23),
97 .msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
98 .reset_level = HNAE3_NONE_RESET
99 }, {
100 .int_msk = BIT(25),
101 .msg = "cmdq_rocee_rx_head_ecc_mbit_err",
102 .reset_level = HNAE3_NONE_RESET
103 }, {
104 .int_msk = BIT(27),
105 .msg = "cmdq_rocee_tx_head_ecc_mbit_err",
106 .reset_level = HNAE3_NONE_RESET
107 }, {
108 .int_msk = BIT(29),
109 .msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
110 .reset_level = HNAE3_NONE_RESET
111 }, {
112 .int_msk = BIT(31),
113 .msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
114 .reset_level = HNAE3_NONE_RESET
115 }, {
116 /* sentinel */
117 }
118 };
119
120 static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
121 {
122 .int_msk = BIT(6),
123 .msg = "tqp_int_cfg_even_ecc_mbit_err",
124 .reset_level = HNAE3_NONE_RESET
125 }, {
126 .int_msk = BIT(7),
127 .msg = "tqp_int_cfg_odd_ecc_mbit_err",
128 .reset_level = HNAE3_NONE_RESET
129 }, {
130 .int_msk = BIT(8),
131 .msg = "tqp_int_ctrl_even_ecc_mbit_err",
132 .reset_level = HNAE3_NONE_RESET
133 }, {
134 .int_msk = BIT(9),
135 .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
136 .reset_level = HNAE3_NONE_RESET
137 }, {
138 .int_msk = BIT(10),
139 .msg = "tx_que_scan_int_ecc_mbit_err",
140 .reset_level = HNAE3_NONE_RESET
141 }, {
142 .int_msk = BIT(11),
143 .msg = "rx_que_scan_int_ecc_mbit_err",
144 .reset_level = HNAE3_NONE_RESET
145 }, {
146 /* sentinel */
147 }
148 };
149
150 static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
151 {
152 .int_msk = BIT(1),
153 .msg = "msix_nic_ecc_mbit_err",
154 .reset_level = HNAE3_NONE_RESET
155 }, {
156 .int_msk = BIT(3),
157 .msg = "msix_rocee_ecc_mbit_err",
158 .reset_level = HNAE3_NONE_RESET
159 }, {
160 /* sentinel */
161 }
162 };
163
164 static const struct hclge_hw_error hclge_igu_int[] = {
165 {
166 .int_msk = BIT(0),
167 .msg = "igu_rx_buf0_ecc_mbit_err",
168 .reset_level = HNAE3_GLOBAL_RESET
169 }, {
170 .int_msk = BIT(2),
171 .msg = "igu_rx_buf1_ecc_mbit_err",
172 .reset_level = HNAE3_GLOBAL_RESET
173 }, {
174 /* sentinel */
175 }
176 };
177
178 static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
179 {
180 .int_msk = BIT(0),
181 .msg = "rx_buf_overflow",
182 .reset_level = HNAE3_GLOBAL_RESET
183 }, {
184 .int_msk = BIT(1),
185 .msg = "rx_stp_fifo_overflow",
186 .reset_level = HNAE3_GLOBAL_RESET
187 }, {
188 .int_msk = BIT(2),
189 .msg = "rx_stp_fifo_underflow",
190 .reset_level = HNAE3_GLOBAL_RESET
191 }, {
192 .int_msk = BIT(3),
193 .msg = "tx_buf_overflow",
194 .reset_level = HNAE3_GLOBAL_RESET
195 }, {
196 .int_msk = BIT(4),
197 .msg = "tx_buf_underrun",
198 .reset_level = HNAE3_GLOBAL_RESET
199 }, {
200 .int_msk = BIT(5),
201 .msg = "rx_stp_buf_overflow",
202 .reset_level = HNAE3_GLOBAL_RESET
203 }, {
204 /* sentinel */
205 }
206 };
207
208 static const struct hclge_hw_error hclge_ncsi_err_int[] = {
209 {
210 .int_msk = BIT(1),
211 .msg = "ncsi_tx_ecc_mbit_err",
212 .reset_level = HNAE3_NONE_RESET
213 }, {
214 /* sentinel */
215 }
216 };
217
218 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = {
219 {
220 .int_msk = BIT(0),
221 .msg = "vf_vlan_ad_mem_ecc_mbit_err",
222 .reset_level = HNAE3_GLOBAL_RESET
223 }, {
224 .int_msk = BIT(1),
225 .msg = "umv_mcast_group_mem_ecc_mbit_err",
226 .reset_level = HNAE3_GLOBAL_RESET
227 }, {
228 .int_msk = BIT(2),
229 .msg = "umv_key_mem0_ecc_mbit_err",
230 .reset_level = HNAE3_GLOBAL_RESET
231 }, {
232 .int_msk = BIT(3),
233 .msg = "umv_key_mem1_ecc_mbit_err",
234 .reset_level = HNAE3_GLOBAL_RESET
235 }, {
236 .int_msk = BIT(4),
237 .msg = "umv_key_mem2_ecc_mbit_err",
238 .reset_level = HNAE3_GLOBAL_RESET
239 }, {
240 .int_msk = BIT(5),
241 .msg = "umv_key_mem3_ecc_mbit_err",
242 .reset_level = HNAE3_GLOBAL_RESET
243 }, {
244 .int_msk = BIT(6),
245 .msg = "umv_ad_mem_ecc_mbit_err",
246 .reset_level = HNAE3_GLOBAL_RESET
247 }, {
248 .int_msk = BIT(7),
249 .msg = "rss_tc_mode_mem_ecc_mbit_err",
250 .reset_level = HNAE3_GLOBAL_RESET
251 }, {
252 .int_msk = BIT(8),
253 .msg = "rss_idt_mem0_ecc_mbit_err",
254 .reset_level = HNAE3_GLOBAL_RESET
255 }, {
256 .int_msk = BIT(9),
257 .msg = "rss_idt_mem1_ecc_mbit_err",
258 .reset_level = HNAE3_GLOBAL_RESET
259 }, {
260 .int_msk = BIT(10),
261 .msg = "rss_idt_mem2_ecc_mbit_err",
262 .reset_level = HNAE3_GLOBAL_RESET
263 }, {
264 .int_msk = BIT(11),
265 .msg = "rss_idt_mem3_ecc_mbit_err",
266 .reset_level = HNAE3_GLOBAL_RESET
267 }, {
268 .int_msk = BIT(12),
269 .msg = "rss_idt_mem4_ecc_mbit_err",
270 .reset_level = HNAE3_GLOBAL_RESET
271 }, {
272 .int_msk = BIT(13),
273 .msg = "rss_idt_mem5_ecc_mbit_err",
274 .reset_level = HNAE3_GLOBAL_RESET
275 }, {
276 .int_msk = BIT(14),
277 .msg = "rss_idt_mem6_ecc_mbit_err",
278 .reset_level = HNAE3_GLOBAL_RESET
279 }, {
280 .int_msk = BIT(15),
281 .msg = "rss_idt_mem7_ecc_mbit_err",
282 .reset_level = HNAE3_GLOBAL_RESET
283 }, {
284 .int_msk = BIT(16),
285 .msg = "rss_idt_mem8_ecc_mbit_err",
286 .reset_level = HNAE3_GLOBAL_RESET
287 }, {
288 .int_msk = BIT(17),
289 .msg = "rss_idt_mem9_ecc_mbit_err",
290 .reset_level = HNAE3_GLOBAL_RESET
291 }, {
292 .int_msk = BIT(18),
293 .msg = "rss_idt_mem10_ecc_mbit_err",
294 .reset_level = HNAE3_GLOBAL_RESET
295 }, {
296 .int_msk = BIT(19),
297 .msg = "rss_idt_mem11_ecc_mbit_err",
298 .reset_level = HNAE3_GLOBAL_RESET
299 }, {
300 .int_msk = BIT(20),
301 .msg = "rss_idt_mem12_ecc_mbit_err",
302 .reset_level = HNAE3_GLOBAL_RESET
303 }, {
304 .int_msk = BIT(21),
305 .msg = "rss_idt_mem13_ecc_mbit_err",
306 .reset_level = HNAE3_GLOBAL_RESET
307 }, {
308 .int_msk = BIT(22),
309 .msg = "rss_idt_mem14_ecc_mbit_err",
310 .reset_level = HNAE3_GLOBAL_RESET
311 }, {
312 .int_msk = BIT(23),
313 .msg = "rss_idt_mem15_ecc_mbit_err",
314 .reset_level = HNAE3_GLOBAL_RESET
315 }, {
316 .int_msk = BIT(24),
317 .msg = "port_vlan_mem_ecc_mbit_err",
318 .reset_level = HNAE3_GLOBAL_RESET
319 }, {
320 .int_msk = BIT(25),
321 .msg = "mcast_linear_table_mem_ecc_mbit_err",
322 .reset_level = HNAE3_GLOBAL_RESET
323 }, {
324 .int_msk = BIT(26),
325 .msg = "mcast_result_mem_ecc_mbit_err",
326 .reset_level = HNAE3_GLOBAL_RESET
327 }, {
328 .int_msk = BIT(27),
329 .msg = "flow_director_ad_mem0_ecc_mbit_err",
330 .reset_level = HNAE3_GLOBAL_RESET
331 }, {
332 .int_msk = BIT(28),
333 .msg = "flow_director_ad_mem1_ecc_mbit_err",
334 .reset_level = HNAE3_GLOBAL_RESET
335 }, {
336 .int_msk = BIT(29),
337 .msg = "rx_vlan_tag_memory_ecc_mbit_err",
338 .reset_level = HNAE3_GLOBAL_RESET
339 }, {
340 .int_msk = BIT(30),
341 .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
342 .reset_level = HNAE3_GLOBAL_RESET
343 }, {
344 /* sentinel */
345 }
346 };
347
348 static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = {
349 {
350 .int_msk = BIT(0),
351 .msg = "tx_vlan_tag_err",
352 .reset_level = HNAE3_NONE_RESET
353 }, {
354 .int_msk = BIT(1),
355 .msg = "rss_list_tc_unassigned_queue_err",
356 .reset_level = HNAE3_NONE_RESET
357 }, {
358 /* sentinel */
359 }
360 };
361
362 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = {
363 {
364 .int_msk = BIT(0),
365 .msg = "hfs_fifo_mem_ecc_mbit_err",
366 .reset_level = HNAE3_GLOBAL_RESET
367 }, {
368 .int_msk = BIT(1),
369 .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
370 .reset_level = HNAE3_GLOBAL_RESET
371 }, {
372 .int_msk = BIT(2),
373 .msg = "tx_vlan_tag_mem_ecc_mbit_err",
374 .reset_level = HNAE3_GLOBAL_RESET
375 }, {
376 .int_msk = BIT(3),
377 .msg = "FD_CN0_memory_ecc_mbit_err",
378 .reset_level = HNAE3_GLOBAL_RESET
379 }, {
380 .int_msk = BIT(4),
381 .msg = "FD_CN1_memory_ecc_mbit_err",
382 .reset_level = HNAE3_GLOBAL_RESET
383 }, {
384 .int_msk = BIT(5),
385 .msg = "GRO_AD_memory_ecc_mbit_err",
386 .reset_level = HNAE3_GLOBAL_RESET
387 }, {
388 /* sentinel */
389 }
390 };
391
392 static const struct hclge_hw_error hclge_tm_sch_rint[] = {
393 {
394 .int_msk = BIT(1),
395 .msg = "tm_sch_ecc_mbit_err",
396 .reset_level = HNAE3_GLOBAL_RESET
397 }, {
398 .int_msk = BIT(2),
399 .msg = "tm_sch_port_shap_sub_fifo_wr_err",
400 .reset_level = HNAE3_GLOBAL_RESET
401 }, {
402 .int_msk = BIT(3),
403 .msg = "tm_sch_port_shap_sub_fifo_rd_err",
404 .reset_level = HNAE3_GLOBAL_RESET
405 }, {
406 .int_msk = BIT(4),
407 .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
408 .reset_level = HNAE3_GLOBAL_RESET
409 }, {
410 .int_msk = BIT(5),
411 .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
412 .reset_level = HNAE3_GLOBAL_RESET
413 }, {
414 .int_msk = BIT(6),
415 .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
416 .reset_level = HNAE3_GLOBAL_RESET
417 }, {
418 .int_msk = BIT(7),
419 .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
420 .reset_level = HNAE3_GLOBAL_RESET
421 }, {
422 .int_msk = BIT(8),
423 .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
424 .reset_level = HNAE3_GLOBAL_RESET
425 }, {
426 .int_msk = BIT(9),
427 .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
428 .reset_level = HNAE3_GLOBAL_RESET
429 }, {
430 .int_msk = BIT(10),
431 .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
432 .reset_level = HNAE3_GLOBAL_RESET
433 }, {
434 .int_msk = BIT(11),
435 .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
436 .reset_level = HNAE3_GLOBAL_RESET
437 }, {
438 .int_msk = BIT(12),
439 .msg = "tm_sch_port_shap_offset_fifo_wr_err",
440 .reset_level = HNAE3_GLOBAL_RESET
441 }, {
442 .int_msk = BIT(13),
443 .msg = "tm_sch_port_shap_offset_fifo_rd_err",
444 .reset_level = HNAE3_GLOBAL_RESET
445 }, {
446 .int_msk = BIT(14),
447 .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
448 .reset_level = HNAE3_GLOBAL_RESET
449 }, {
450 .int_msk = BIT(15),
451 .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
452 .reset_level = HNAE3_GLOBAL_RESET
453 }, {
454 .int_msk = BIT(16),
455 .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
456 .reset_level = HNAE3_GLOBAL_RESET
457 }, {
458 .int_msk = BIT(17),
459 .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
460 .reset_level = HNAE3_GLOBAL_RESET
461 }, {
462 .int_msk = BIT(18),
463 .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
464 .reset_level = HNAE3_GLOBAL_RESET
465 }, {
466 .int_msk = BIT(19),
467 .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
468 .reset_level = HNAE3_GLOBAL_RESET
469 }, {
470 .int_msk = BIT(20),
471 .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
472 .reset_level = HNAE3_GLOBAL_RESET
473 }, {
474 .int_msk = BIT(21),
475 .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
476 .reset_level = HNAE3_GLOBAL_RESET
477 }, {
478 .int_msk = BIT(22),
479 .msg = "tm_sch_rq_fifo_wr_err",
480 .reset_level = HNAE3_GLOBAL_RESET
481 }, {
482 .int_msk = BIT(23),
483 .msg = "tm_sch_rq_fifo_rd_err",
484 .reset_level = HNAE3_GLOBAL_RESET
485 }, {
486 .int_msk = BIT(24),
487 .msg = "tm_sch_nq_fifo_wr_err",
488 .reset_level = HNAE3_GLOBAL_RESET
489 }, {
490 .int_msk = BIT(25),
491 .msg = "tm_sch_nq_fifo_rd_err",
492 .reset_level = HNAE3_GLOBAL_RESET
493 }, {
494 .int_msk = BIT(26),
495 .msg = "tm_sch_roce_up_fifo_wr_err",
496 .reset_level = HNAE3_GLOBAL_RESET
497 }, {
498 .int_msk = BIT(27),
499 .msg = "tm_sch_roce_up_fifo_rd_err",
500 .reset_level = HNAE3_GLOBAL_RESET
501 }, {
502 .int_msk = BIT(28),
503 .msg = "tm_sch_rcb_byte_fifo_wr_err",
504 .reset_level = HNAE3_GLOBAL_RESET
505 }, {
506 .int_msk = BIT(29),
507 .msg = "tm_sch_rcb_byte_fifo_rd_err",
508 .reset_level = HNAE3_GLOBAL_RESET
509 }, {
510 .int_msk = BIT(30),
511 .msg = "tm_sch_ssu_byte_fifo_wr_err",
512 .reset_level = HNAE3_GLOBAL_RESET
513 }, {
514 .int_msk = BIT(31),
515 .msg = "tm_sch_ssu_byte_fifo_rd_err",
516 .reset_level = HNAE3_GLOBAL_RESET
517 }, {
518 /* sentinel */
519 }
520 };
521
522 static const struct hclge_hw_error hclge_qcn_fifo_rint[] = {
523 {
524 .int_msk = BIT(0),
525 .msg = "qcn_shap_gp0_sch_fifo_rd_err",
526 .reset_level = HNAE3_GLOBAL_RESET
527 }, {
528 .int_msk = BIT(1),
529 .msg = "qcn_shap_gp0_sch_fifo_wr_err",
530 .reset_level = HNAE3_GLOBAL_RESET
531 }, {
532 .int_msk = BIT(2),
533 .msg = "qcn_shap_gp1_sch_fifo_rd_err",
534 .reset_level = HNAE3_GLOBAL_RESET
535 }, {
536 .int_msk = BIT(3),
537 .msg = "qcn_shap_gp1_sch_fifo_wr_err",
538 .reset_level = HNAE3_GLOBAL_RESET
539 }, {
540 .int_msk = BIT(4),
541 .msg = "qcn_shap_gp2_sch_fifo_rd_err",
542 .reset_level = HNAE3_GLOBAL_RESET
543 }, {
544 .int_msk = BIT(5),
545 .msg = "qcn_shap_gp2_sch_fifo_wr_err",
546 .reset_level = HNAE3_GLOBAL_RESET
547 }, {
548 .int_msk = BIT(6),
549 .msg = "qcn_shap_gp3_sch_fifo_rd_err",
550 .reset_level = HNAE3_GLOBAL_RESET
551 }, {
552 .int_msk = BIT(7),
553 .msg = "qcn_shap_gp3_sch_fifo_wr_err",
554 .reset_level = HNAE3_GLOBAL_RESET
555 }, {
556 .int_msk = BIT(8),
557 .msg = "qcn_shap_gp0_offset_fifo_rd_err",
558 .reset_level = HNAE3_GLOBAL_RESET
559 }, {
560 .int_msk = BIT(9),
561 .msg = "qcn_shap_gp0_offset_fifo_wr_err",
562 .reset_level = HNAE3_GLOBAL_RESET
563 }, {
564 .int_msk = BIT(10),
565 .msg = "qcn_shap_gp1_offset_fifo_rd_err",
566 .reset_level = HNAE3_GLOBAL_RESET
567 }, {
568 .int_msk = BIT(11),
569 .msg = "qcn_shap_gp1_offset_fifo_wr_err",
570 .reset_level = HNAE3_GLOBAL_RESET
571 }, {
572 .int_msk = BIT(12),
573 .msg = "qcn_shap_gp2_offset_fifo_rd_err",
574 .reset_level = HNAE3_GLOBAL_RESET
575 }, {
576 .int_msk = BIT(13),
577 .msg = "qcn_shap_gp2_offset_fifo_wr_err",
578 .reset_level = HNAE3_GLOBAL_RESET
579 }, {
580 .int_msk = BIT(14),
581 .msg = "qcn_shap_gp3_offset_fifo_rd_err",
582 .reset_level = HNAE3_GLOBAL_RESET
583 }, {
584 .int_msk = BIT(15),
585 .msg = "qcn_shap_gp3_offset_fifo_wr_err",
586 .reset_level = HNAE3_GLOBAL_RESET
587 }, {
588 .int_msk = BIT(16),
589 .msg = "qcn_byte_info_fifo_rd_err",
590 .reset_level = HNAE3_GLOBAL_RESET
591 }, {
592 .int_msk = BIT(17),
593 .msg = "qcn_byte_info_fifo_wr_err",
594 .reset_level = HNAE3_GLOBAL_RESET
595 }, {
596 /* sentinel */
597 }
598 };
599
600 static const struct hclge_hw_error hclge_qcn_ecc_rint[] = {
601 {
602 .int_msk = BIT(1),
603 .msg = "qcn_byte_mem_ecc_mbit_err",
604 .reset_level = HNAE3_GLOBAL_RESET
605 }, {
606 .int_msk = BIT(3),
607 .msg = "qcn_time_mem_ecc_mbit_err",
608 .reset_level = HNAE3_GLOBAL_RESET
609 }, {
610 .int_msk = BIT(5),
611 .msg = "qcn_fb_mem_ecc_mbit_err",
612 .reset_level = HNAE3_GLOBAL_RESET
613 }, {
614 .int_msk = BIT(7),
615 .msg = "qcn_link_mem_ecc_mbit_err",
616 .reset_level = HNAE3_GLOBAL_RESET
617 }, {
618 .int_msk = BIT(9),
619 .msg = "qcn_rate_mem_ecc_mbit_err",
620 .reset_level = HNAE3_GLOBAL_RESET
621 }, {
622 .int_msk = BIT(11),
623 .msg = "qcn_tmplt_mem_ecc_mbit_err",
624 .reset_level = HNAE3_GLOBAL_RESET
625 }, {
626 .int_msk = BIT(13),
627 .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
628 .reset_level = HNAE3_GLOBAL_RESET
629 }, {
630 .int_msk = BIT(15),
631 .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
632 .reset_level = HNAE3_GLOBAL_RESET
633 }, {
634 .int_msk = BIT(17),
635 .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
636 .reset_level = HNAE3_GLOBAL_RESET
637 }, {
638 .int_msk = BIT(19),
639 .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
640 .reset_level = HNAE3_GLOBAL_RESET
641 }, {
642 .int_msk = BIT(21),
643 .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
644 .reset_level = HNAE3_GLOBAL_RESET
645 }, {
646 /* sentinel */
647 }
648 };
649
650 static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
651 {
652 .int_msk = BIT(0),
653 .msg = "egu_cge_afifo_ecc_1bit_err",
654 .reset_level = HNAE3_NONE_RESET
655 }, {
656 .int_msk = BIT(1),
657 .msg = "egu_cge_afifo_ecc_mbit_err",
658 .reset_level = HNAE3_GLOBAL_RESET
659 }, {
660 .int_msk = BIT(2),
661 .msg = "egu_lge_afifo_ecc_1bit_err",
662 .reset_level = HNAE3_NONE_RESET
663 }, {
664 .int_msk = BIT(3),
665 .msg = "egu_lge_afifo_ecc_mbit_err",
666 .reset_level = HNAE3_GLOBAL_RESET
667 }, {
668 .int_msk = BIT(4),
669 .msg = "cge_igu_afifo_ecc_1bit_err",
670 .reset_level = HNAE3_NONE_RESET
671 }, {
672 .int_msk = BIT(5),
673 .msg = "cge_igu_afifo_ecc_mbit_err",
674 .reset_level = HNAE3_GLOBAL_RESET
675 }, {
676 .int_msk = BIT(6),
677 .msg = "lge_igu_afifo_ecc_1bit_err",
678 .reset_level = HNAE3_NONE_RESET
679 }, {
680 .int_msk = BIT(7),
681 .msg = "lge_igu_afifo_ecc_mbit_err",
682 .reset_level = HNAE3_GLOBAL_RESET
683 }, {
684 .int_msk = BIT(8),
685 .msg = "cge_igu_afifo_overflow_err",
686 .reset_level = HNAE3_GLOBAL_RESET
687 }, {
688 .int_msk = BIT(9),
689 .msg = "lge_igu_afifo_overflow_err",
690 .reset_level = HNAE3_GLOBAL_RESET
691 }, {
692 .int_msk = BIT(10),
693 .msg = "egu_cge_afifo_underrun_err",
694 .reset_level = HNAE3_GLOBAL_RESET
695 }, {
696 .int_msk = BIT(11),
697 .msg = "egu_lge_afifo_underrun_err",
698 .reset_level = HNAE3_GLOBAL_RESET
699 }, {
700 .int_msk = BIT(12),
701 .msg = "egu_ge_afifo_underrun_err",
702 .reset_level = HNAE3_GLOBAL_RESET
703 }, {
704 .int_msk = BIT(13),
705 .msg = "ge_igu_afifo_overflow_err",
706 .reset_level = HNAE3_GLOBAL_RESET
707 }, {
708 /* sentinel */
709 }
710 };
711
712 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
713 {
714 .int_msk = BIT(13),
715 .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
716 .reset_level = HNAE3_GLOBAL_RESET
717 }, {
718 .int_msk = BIT(14),
719 .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
720 .reset_level = HNAE3_GLOBAL_RESET
721 }, {
722 .int_msk = BIT(15),
723 .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
724 .reset_level = HNAE3_GLOBAL_RESET
725 }, {
726 .int_msk = BIT(16),
727 .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
728 .reset_level = HNAE3_GLOBAL_RESET
729 }, {
730 .int_msk = BIT(17),
731 .msg = "rcb_tx_ring_ecc_mbit_err",
732 .reset_level = HNAE3_GLOBAL_RESET
733 }, {
734 .int_msk = BIT(18),
735 .msg = "rcb_rx_ring_ecc_mbit_err",
736 .reset_level = HNAE3_GLOBAL_RESET
737 }, {
738 .int_msk = BIT(19),
739 .msg = "rcb_tx_fbd_ecc_mbit_err",
740 .reset_level = HNAE3_GLOBAL_RESET
741 }, {
742 .int_msk = BIT(20),
743 .msg = "rcb_rx_ebd_ecc_mbit_err",
744 .reset_level = HNAE3_GLOBAL_RESET
745 }, {
746 .int_msk = BIT(21),
747 .msg = "rcb_tso_info_ecc_mbit_err",
748 .reset_level = HNAE3_GLOBAL_RESET
749 }, {
750 .int_msk = BIT(22),
751 .msg = "rcb_tx_int_info_ecc_mbit_err",
752 .reset_level = HNAE3_GLOBAL_RESET
753 }, {
754 .int_msk = BIT(23),
755 .msg = "rcb_rx_int_info_ecc_mbit_err",
756 .reset_level = HNAE3_GLOBAL_RESET
757 }, {
758 .int_msk = BIT(24),
759 .msg = "tpu_tx_pkt_0_ecc_mbit_err",
760 .reset_level = HNAE3_GLOBAL_RESET
761 }, {
762 .int_msk = BIT(25),
763 .msg = "tpu_tx_pkt_1_ecc_mbit_err",
764 .reset_level = HNAE3_GLOBAL_RESET
765 }, {
766 .int_msk = BIT(26),
767 .msg = "rd_bus_err",
768 .reset_level = HNAE3_GLOBAL_RESET
769 }, {
770 .int_msk = BIT(27),
771 .msg = "wr_bus_err",
772 .reset_level = HNAE3_GLOBAL_RESET
773 }, {
774 .int_msk = BIT(28),
775 .msg = "reg_search_miss",
776 .reset_level = HNAE3_GLOBAL_RESET
777 }, {
778 .int_msk = BIT(29),
779 .msg = "rx_q_search_miss",
780 .reset_level = HNAE3_NONE_RESET
781 }, {
782 .int_msk = BIT(30),
783 .msg = "ooo_ecc_err_detect",
784 .reset_level = HNAE3_NONE_RESET
785 }, {
786 .int_msk = BIT(31),
787 .msg = "ooo_ecc_err_multpl",
788 .reset_level = HNAE3_GLOBAL_RESET
789 }, {
790 /* sentinel */
791 }
792 };
793
794 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
795 {
796 .int_msk = BIT(4),
797 .msg = "gro_bd_ecc_mbit_err",
798 .reset_level = HNAE3_GLOBAL_RESET
799 }, {
800 .int_msk = BIT(5),
801 .msg = "gro_context_ecc_mbit_err",
802 .reset_level = HNAE3_GLOBAL_RESET
803 }, {
804 .int_msk = BIT(6),
805 .msg = "rx_stash_cfg_ecc_mbit_err",
806 .reset_level = HNAE3_GLOBAL_RESET
807 }, {
808 .int_msk = BIT(7),
809 .msg = "axi_rd_fbd_ecc_mbit_err",
810 .reset_level = HNAE3_GLOBAL_RESET
811 }, {
812 /* sentinel */
813 }
814 };
815
816 static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
817 {
818 .int_msk = BIT(0),
819 .msg = "over_8bd_no_fe",
820 .reset_level = HNAE3_FUNC_RESET
821 }, {
822 .int_msk = BIT(1),
823 .msg = "tso_mss_cmp_min_err",
824 .reset_level = HNAE3_NONE_RESET
825 }, {
826 .int_msk = BIT(2),
827 .msg = "tso_mss_cmp_max_err",
828 .reset_level = HNAE3_NONE_RESET
829 }, {
830 .int_msk = BIT(3),
831 .msg = "tx_rd_fbd_poison",
832 .reset_level = HNAE3_FUNC_RESET
833 }, {
834 .int_msk = BIT(4),
835 .msg = "rx_rd_ebd_poison",
836 .reset_level = HNAE3_FUNC_RESET
837 }, {
838 .int_msk = BIT(5),
839 .msg = "buf_wait_timeout",
840 .reset_level = HNAE3_NONE_RESET
841 }, {
842 /* sentinel */
843 }
844 };
845
846 static const struct hclge_hw_error hclge_ssu_com_err_int[] = {
847 {
848 .int_msk = BIT(0),
849 .msg = "buf_sum_err",
850 .reset_level = HNAE3_NONE_RESET
851 }, {
852 .int_msk = BIT(1),
853 .msg = "ppp_mb_num_err",
854 .reset_level = HNAE3_NONE_RESET
855 }, {
856 .int_msk = BIT(2),
857 .msg = "ppp_mbid_err",
858 .reset_level = HNAE3_GLOBAL_RESET
859 }, {
860 .int_msk = BIT(3),
861 .msg = "ppp_rlt_mac_err",
862 .reset_level = HNAE3_GLOBAL_RESET
863 }, {
864 .int_msk = BIT(4),
865 .msg = "ppp_rlt_host_err",
866 .reset_level = HNAE3_GLOBAL_RESET
867 }, {
868 .int_msk = BIT(5),
869 .msg = "cks_edit_position_err",
870 .reset_level = HNAE3_GLOBAL_RESET
871 }, {
872 .int_msk = BIT(6),
873 .msg = "cks_edit_condition_err",
874 .reset_level = HNAE3_GLOBAL_RESET
875 }, {
876 .int_msk = BIT(7),
877 .msg = "vlan_edit_condition_err",
878 .reset_level = HNAE3_GLOBAL_RESET
879 }, {
880 .int_msk = BIT(8),
881 .msg = "vlan_num_ot_err",
882 .reset_level = HNAE3_GLOBAL_RESET
883 }, {
884 .int_msk = BIT(9),
885 .msg = "vlan_num_in_err",
886 .reset_level = HNAE3_GLOBAL_RESET
887 }, {
888 /* sentinel */
889 }
890 };
891
892 #define HCLGE_SSU_MEM_ECC_ERR(x) \
893 { \
894 .int_msk = BIT(x), \
895 .msg = "ssu_mem" #x "_ecc_mbit_err", \
896 .reset_level = HNAE3_GLOBAL_RESET \
897 }
898
899 static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
900 HCLGE_SSU_MEM_ECC_ERR(0),
901 HCLGE_SSU_MEM_ECC_ERR(1),
902 HCLGE_SSU_MEM_ECC_ERR(2),
903 HCLGE_SSU_MEM_ECC_ERR(3),
904 HCLGE_SSU_MEM_ECC_ERR(4),
905 HCLGE_SSU_MEM_ECC_ERR(5),
906 HCLGE_SSU_MEM_ECC_ERR(6),
907 HCLGE_SSU_MEM_ECC_ERR(7),
908 HCLGE_SSU_MEM_ECC_ERR(8),
909 HCLGE_SSU_MEM_ECC_ERR(9),
910 HCLGE_SSU_MEM_ECC_ERR(10),
911 HCLGE_SSU_MEM_ECC_ERR(11),
912 HCLGE_SSU_MEM_ECC_ERR(12),
913 HCLGE_SSU_MEM_ECC_ERR(13),
914 HCLGE_SSU_MEM_ECC_ERR(14),
915 HCLGE_SSU_MEM_ECC_ERR(15),
916 HCLGE_SSU_MEM_ECC_ERR(16),
917 HCLGE_SSU_MEM_ECC_ERR(17),
918 HCLGE_SSU_MEM_ECC_ERR(18),
919 HCLGE_SSU_MEM_ECC_ERR(19),
920 HCLGE_SSU_MEM_ECC_ERR(20),
921 HCLGE_SSU_MEM_ECC_ERR(21),
922 HCLGE_SSU_MEM_ECC_ERR(22),
923 HCLGE_SSU_MEM_ECC_ERR(23),
924 HCLGE_SSU_MEM_ECC_ERR(24),
925 HCLGE_SSU_MEM_ECC_ERR(25),
926 HCLGE_SSU_MEM_ECC_ERR(26),
927 HCLGE_SSU_MEM_ECC_ERR(27),
928 HCLGE_SSU_MEM_ECC_ERR(28),
929 HCLGE_SSU_MEM_ECC_ERR(29),
930 HCLGE_SSU_MEM_ECC_ERR(30),
931 HCLGE_SSU_MEM_ECC_ERR(31),
932 { /* sentinel */ }
933 };
934
935 static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
936 {
937 .int_msk = BIT(0),
938 .msg = "roc_pkt_without_key_port",
939 .reset_level = HNAE3_FUNC_RESET
940 }, {
941 .int_msk = BIT(1),
942 .msg = "tpu_pkt_without_key_port",
943 .reset_level = HNAE3_GLOBAL_RESET
944 }, {
945 .int_msk = BIT(2),
946 .msg = "igu_pkt_without_key_port",
947 .reset_level = HNAE3_GLOBAL_RESET
948 }, {
949 .int_msk = BIT(3),
950 .msg = "roc_eof_mis_match_port",
951 .reset_level = HNAE3_GLOBAL_RESET
952 }, {
953 .int_msk = BIT(4),
954 .msg = "tpu_eof_mis_match_port",
955 .reset_level = HNAE3_GLOBAL_RESET
956 }, {
957 .int_msk = BIT(5),
958 .msg = "igu_eof_mis_match_port",
959 .reset_level = HNAE3_GLOBAL_RESET
960 }, {
961 .int_msk = BIT(6),
962 .msg = "roc_sof_mis_match_port",
963 .reset_level = HNAE3_GLOBAL_RESET
964 }, {
965 .int_msk = BIT(7),
966 .msg = "tpu_sof_mis_match_port",
967 .reset_level = HNAE3_GLOBAL_RESET
968 }, {
969 .int_msk = BIT(8),
970 .msg = "igu_sof_mis_match_port",
971 .reset_level = HNAE3_GLOBAL_RESET
972 }, {
973 .int_msk = BIT(11),
974 .msg = "ets_rd_int_rx_port",
975 .reset_level = HNAE3_GLOBAL_RESET
976 }, {
977 .int_msk = BIT(12),
978 .msg = "ets_wr_int_rx_port",
979 .reset_level = HNAE3_GLOBAL_RESET
980 }, {
981 .int_msk = BIT(13),
982 .msg = "ets_rd_int_tx_port",
983 .reset_level = HNAE3_GLOBAL_RESET
984 }, {
985 .int_msk = BIT(14),
986 .msg = "ets_wr_int_tx_port",
987 .reset_level = HNAE3_GLOBAL_RESET
988 }, {
989 /* sentinel */
990 }
991 };
992
993 static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
994 {
995 .int_msk = BIT(0),
996 .msg = "ig_mac_inf_int",
997 .reset_level = HNAE3_GLOBAL_RESET
998 }, {
999 .int_msk = BIT(1),
1000 .msg = "ig_host_inf_int",
1001 .reset_level = HNAE3_GLOBAL_RESET
1002 }, {
1003 .int_msk = BIT(2),
1004 .msg = "ig_roc_buf_int",
1005 .reset_level = HNAE3_GLOBAL_RESET
1006 }, {
1007 .int_msk = BIT(3),
1008 .msg = "ig_host_data_fifo_int",
1009 .reset_level = HNAE3_GLOBAL_RESET
1010 }, {
1011 .int_msk = BIT(4),
1012 .msg = "ig_host_key_fifo_int",
1013 .reset_level = HNAE3_GLOBAL_RESET
1014 }, {
1015 .int_msk = BIT(5),
1016 .msg = "tx_qcn_fifo_int",
1017 .reset_level = HNAE3_GLOBAL_RESET
1018 }, {
1019 .int_msk = BIT(6),
1020 .msg = "rx_qcn_fifo_int",
1021 .reset_level = HNAE3_GLOBAL_RESET
1022 }, {
1023 .int_msk = BIT(7),
1024 .msg = "tx_pf_rd_fifo_int",
1025 .reset_level = HNAE3_GLOBAL_RESET
1026 }, {
1027 .int_msk = BIT(8),
1028 .msg = "rx_pf_rd_fifo_int",
1029 .reset_level = HNAE3_GLOBAL_RESET
1030 }, {
1031 .int_msk = BIT(9),
1032 .msg = "qm_eof_fifo_int",
1033 .reset_level = HNAE3_GLOBAL_RESET
1034 }, {
1035 .int_msk = BIT(10),
1036 .msg = "mb_rlt_fifo_int",
1037 .reset_level = HNAE3_GLOBAL_RESET
1038 }, {
1039 .int_msk = BIT(11),
1040 .msg = "dup_uncopy_fifo_int",
1041 .reset_level = HNAE3_GLOBAL_RESET
1042 }, {
1043 .int_msk = BIT(12),
1044 .msg = "dup_cnt_rd_fifo_int",
1045 .reset_level = HNAE3_GLOBAL_RESET
1046 }, {
1047 .int_msk = BIT(13),
1048 .msg = "dup_cnt_drop_fifo_int",
1049 .reset_level = HNAE3_GLOBAL_RESET
1050 }, {
1051 .int_msk = BIT(14),
1052 .msg = "dup_cnt_wrb_fifo_int",
1053 .reset_level = HNAE3_GLOBAL_RESET
1054 }, {
1055 .int_msk = BIT(15),
1056 .msg = "host_cmd_fifo_int",
1057 .reset_level = HNAE3_GLOBAL_RESET
1058 }, {
1059 .int_msk = BIT(16),
1060 .msg = "mac_cmd_fifo_int",
1061 .reset_level = HNAE3_GLOBAL_RESET
1062 }, {
1063 .int_msk = BIT(17),
1064 .msg = "host_cmd_bitmap_empty_int",
1065 .reset_level = HNAE3_GLOBAL_RESET
1066 }, {
1067 .int_msk = BIT(18),
1068 .msg = "mac_cmd_bitmap_empty_int",
1069 .reset_level = HNAE3_GLOBAL_RESET
1070 }, {
1071 .int_msk = BIT(19),
1072 .msg = "dup_bitmap_empty_int",
1073 .reset_level = HNAE3_GLOBAL_RESET
1074 }, {
1075 .int_msk = BIT(20),
1076 .msg = "out_queue_bitmap_empty_int",
1077 .reset_level = HNAE3_GLOBAL_RESET
1078 }, {
1079 .int_msk = BIT(21),
1080 .msg = "bank2_bitmap_empty_int",
1081 .reset_level = HNAE3_GLOBAL_RESET
1082 }, {
1083 .int_msk = BIT(22),
1084 .msg = "bank1_bitmap_empty_int",
1085 .reset_level = HNAE3_GLOBAL_RESET
1086 }, {
1087 .int_msk = BIT(23),
1088 .msg = "bank0_bitmap_empty_int",
1089 .reset_level = HNAE3_GLOBAL_RESET
1090 }, {
1091 /* sentinel */
1092 }
1093 };
1094
1095 static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
1096 {
1097 .int_msk = BIT(0),
1098 .msg = "ets_rd_int_rx_tcg",
1099 .reset_level = HNAE3_GLOBAL_RESET
1100 }, {
1101 .int_msk = BIT(1),
1102 .msg = "ets_wr_int_rx_tcg",
1103 .reset_level = HNAE3_GLOBAL_RESET
1104 }, {
1105 .int_msk = BIT(2),
1106 .msg = "ets_rd_int_tx_tcg",
1107 .reset_level = HNAE3_GLOBAL_RESET
1108 }, {
1109 .int_msk = BIT(3),
1110 .msg = "ets_wr_int_tx_tcg",
1111 .reset_level = HNAE3_GLOBAL_RESET
1112 }, {
1113 /* sentinel */
1114 }
1115 };
1116
1117 static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
1118 {
1119 .int_msk = BIT(0),
1120 .msg = "roc_pkt_without_key_port",
1121 .reset_level = HNAE3_FUNC_RESET
1122 }, {
1123 .int_msk = BIT(9),
1124 .msg = "low_water_line_err_port",
1125 .reset_level = HNAE3_NONE_RESET
1126 }, {
1127 .int_msk = BIT(10),
1128 .msg = "hi_water_line_err_port",
1129 .reset_level = HNAE3_GLOBAL_RESET
1130 }, {
1131 /* sentinel */
1132 }
1133 };
1134
1135 static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
1136 {
1137 .int_msk = 0,
1138 .msg = "rocee qmm ovf: sgid invalid err"
1139 }, {
1140 .int_msk = 0x4,
1141 .msg = "rocee qmm ovf: sgid ovf err"
1142 }, {
1143 .int_msk = 0x8,
1144 .msg = "rocee qmm ovf: smac invalid err"
1145 }, {
1146 .int_msk = 0xC,
1147 .msg = "rocee qmm ovf: smac ovf err"
1148 }, {
1149 .int_msk = 0x10,
1150 .msg = "rocee qmm ovf: cqc invalid err"
1151 }, {
1152 .int_msk = 0x11,
1153 .msg = "rocee qmm ovf: cqc ovf err"
1154 }, {
1155 .int_msk = 0x12,
1156 .msg = "rocee qmm ovf: cqc hopnum err"
1157 }, {
1158 .int_msk = 0x13,
1159 .msg = "rocee qmm ovf: cqc ba0 err"
1160 }, {
1161 .int_msk = 0x14,
1162 .msg = "rocee qmm ovf: srqc invalid err"
1163 }, {
1164 .int_msk = 0x15,
1165 .msg = "rocee qmm ovf: srqc ovf err"
1166 }, {
1167 .int_msk = 0x16,
1168 .msg = "rocee qmm ovf: srqc hopnum err"
1169 }, {
1170 .int_msk = 0x17,
1171 .msg = "rocee qmm ovf: srqc ba0 err"
1172 }, {
1173 .int_msk = 0x18,
1174 .msg = "rocee qmm ovf: mpt invalid err"
1175 }, {
1176 .int_msk = 0x19,
1177 .msg = "rocee qmm ovf: mpt ovf err"
1178 }, {
1179 .int_msk = 0x1A,
1180 .msg = "rocee qmm ovf: mpt hopnum err"
1181 }, {
1182 .int_msk = 0x1B,
1183 .msg = "rocee qmm ovf: mpt ba0 err"
1184 }, {
1185 .int_msk = 0x1C,
1186 .msg = "rocee qmm ovf: qpc invalid err"
1187 }, {
1188 .int_msk = 0x1D,
1189 .msg = "rocee qmm ovf: qpc ovf err"
1190 }, {
1191 .int_msk = 0x1E,
1192 .msg = "rocee qmm ovf: qpc hopnum err"
1193 }, {
1194 .int_msk = 0x1F,
1195 .msg = "rocee qmm ovf: qpc ba0 err"
1196 }, {
1197 /* sentinel */
1198 }
1199 };
1200
1201 static const struct hclge_mod_reg_info hclge_ssu_reg_0_info[] = {
1202 {
1203 .reg_name = "SSU_BP_STATUS_0~5",
1204 .reg_offset_group = { 5, 6, 7, 8, 9, 10},
1205 .group_size = 6
1206 }, {
1207 .reg_name = "LO_PRI_UNICAST_CUR_CNT",
1208 .reg_offset_group = {54},
1209 .group_size = 1
1210 }, {
1211 .reg_name = "HI/LO_PRI_MULTICAST_CUR_CNT",
1212 .reg_offset_group = {55, 56},
1213 .group_size = 2
1214 }, {
1215 .reg_name = "SSU_MB_RD_RLT_DROP_CNT",
1216 .reg_offset_group = {29},
1217 .group_size = 1
1218 }, {
1219 .reg_name = "SSU_PPP_MAC_KEY_NUM",
1220 .reg_offset_group = {31, 30},
1221 .group_size = 2
1222 }, {
1223 .reg_name = "SSU_PPP_HOST_KEY_NUM",
1224 .reg_offset_group = {33, 32},
1225 .group_size = 2
1226 }, {
1227 .reg_name = "PPP_SSU_MAC/HOST_RLT_NUM",
1228 .reg_offset_group = {35, 34, 37, 36},
1229 .group_size = 4
1230 }, {
1231 .reg_name = "FULL/PART_DROP_NUM",
1232 .reg_offset_group = {18, 19},
1233 .group_size = 2
1234 }, {
1235 .reg_name = "PPP_KEY/RLT_DROP_NUM",
1236 .reg_offset_group = {20, 21},
1237 .group_size = 2
1238 }, {
1239 .reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT",
1240 .reg_offset_group = {48, 49},
1241 .group_size = 2
1242 }, {
1243 .reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT_RX",
1244 .reg_offset_group = {50, 51},
1245 .group_size = 2
1246 },
1247 };
1248
1249 static const struct hclge_mod_reg_info hclge_ssu_reg_1_info[] = {
1250 {
1251 .reg_name = "RX_PACKET_IN/OUT_CNT",
1252 .reg_offset_group = {13, 12, 15, 14},
1253 .group_size = 4
1254 }, {
1255 .reg_name = "TX_PACKET_IN/OUT_CNT",
1256 .reg_offset_group = {17, 16, 19, 18},
1257 .group_size = 4
1258 }, {
1259 .reg_name = "RX_PACKET_TC0_IN/OUT_CNT",
1260 .reg_offset_group = {25, 24, 41, 40},
1261 .group_size = 4
1262 }, {
1263 .reg_name = "RX_PACKET_TC1_IN/OUT_CNT",
1264 .reg_offset_group = {27, 26, 43, 42},
1265 .group_size = 4
1266 }, {
1267 .reg_name = "RX_PACKET_TC2_IN/OUT_CNT",
1268 .reg_offset_group = {29, 28, 45, 44},
1269 .group_size = 4
1270 }, {
1271 .reg_name = "RX_PACKET_TC3_IN/OUT_CNT",
1272 .reg_offset_group = {31, 30, 47, 46},
1273 .group_size = 4
1274 }, {
1275 .reg_name = "RX_PACKET_TC4_IN/OUT_CNT",
1276 .reg_offset_group = {33, 32, 49, 48},
1277 .group_size = 4
1278 }, {
1279 .reg_name = "RX_PACKET_TC5_IN/OUT_CNT",
1280 .reg_offset_group = {35, 34, 51, 50},
1281 .group_size = 4
1282 }, {
1283 .reg_name = "RX_PACKET_TC6_IN/OUT_CNT",
1284 .reg_offset_group = {37, 36, 53, 52},
1285 .group_size = 4
1286 }, {
1287 .reg_name = "RX_PACKET_TC7_IN/OUT_CNT",
1288 .reg_offset_group = {39, 38, 55, 54},
1289 .group_size = 4
1290 }, {
1291 .reg_name = "TX_PACKET_TC0_IN/OUT_CNT",
1292 .reg_offset_group = {57, 56, 73, 72},
1293 .group_size = 4
1294 }, {
1295 .reg_name = "TX_PACKET_TC1_IN/OUT_CNT",
1296 .reg_offset_group = {59, 58, 75, 74},
1297 .group_size = 4
1298 }, {
1299 .reg_name = "TX_PACKET_TC2_IN/OUT_CNT",
1300 .reg_offset_group = {61, 60, 77, 76},
1301 .group_size = 4
1302 }, {
1303 .reg_name = "TX_PACKET_TC3_IN/OUT_CNT",
1304 .reg_offset_group = {63, 62, 79, 78},
1305 .group_size = 4
1306 }, {
1307 .reg_name = "TX_PACKET_TC4_IN/OUT_CNT",
1308 .reg_offset_group = {65, 64, 81, 80},
1309 .group_size = 4
1310 }, {
1311 .reg_name = "TX_PACKET_TC5_IN/OUT_CNT",
1312 .reg_offset_group = {67, 66, 83, 82},
1313 .group_size = 4
1314 }, {
1315 .reg_name = "TX_PACKET_TC6_IN/OUT_CNT",
1316 .reg_offset_group = {69, 68, 85, 84},
1317 .group_size = 4
1318 }, {
1319 .reg_name = "TX_PACKET_TC7_IN/OUT_CNT",
1320 .reg_offset_group = {71, 70, 87, 86},
1321 .group_size = 4
1322 }, {
1323 .reg_name = "PACKET_TC0~3_CURR_BUFFER_CNT",
1324 .reg_offset_group = {1, 2, 3, 4},
1325 .group_size = 4
1326 }, {
1327 .reg_name = "PACKET_TC4~7_CURR_BUFFER_CNT",
1328 .reg_offset_group = {5, 6, 7, 8},
1329 .group_size = 4
1330 }, {
1331 .reg_name = "ROC_RX_PACKET_IN_CNT",
1332 .reg_offset_group = {21, 20},
1333 .group_size = 2
1334 }, {
1335 .reg_name = "ROC_TX_PACKET_OUT_CNT",
1336 .reg_offset_group = {23, 22},
1337 .group_size = 2
1338 }
1339 };
1340
1341 static const struct hclge_mod_reg_info hclge_rpu_reg_0_info[] = {
1342 {
1343 .reg_name = "RPU_FSM_DFX_ST0/ST1_TNL",
1344 .has_suffix = true,
1345 .reg_offset_group = {1, 2},
1346 .group_size = 2
1347 }, {
1348 .reg_name = "RPU_RX_PKT_DROP_CNT_TNL",
1349 .has_suffix = true,
1350 .reg_offset_group = {3},
1351 .group_size = 1
1352 }
1353 };
1354
1355 static const struct hclge_mod_reg_info hclge_rpu_reg_1_info[] = {
1356 {
1357 .reg_name = "FIFO_DFX_ST0_1_2_4",
1358 .reg_offset_group = {1, 2, 3, 5},
1359 .group_size = 4
1360 }
1361 };
1362
1363 static const struct hclge_mod_reg_info hclge_igu_egu_reg_info[] = {
1364 {
1365 .reg_name = "IGU_RX_ERR_PKT",
1366 .reg_offset_group = {1},
1367 .group_size = 1
1368 }, {
1369 .reg_name = "IGU_RX_OUT_ALL_PKT",
1370 .reg_offset_group = {29, 28},
1371 .group_size = 2
1372 }, {
1373 .reg_name = "EGU_TX_OUT_ALL_PKT",
1374 .reg_offset_group = {39, 38},
1375 .group_size = 2
1376 }, {
1377 .reg_name = "EGU_TX_ERR_PKT",
1378 .reg_offset_group = {5},
1379 .group_size = 1
1380 }
1381 };
1382
1383 static const struct hclge_mod_reg_info hclge_gen_reg_info_tnl[] = {
1384 {
1385 .reg_name = "SSU2RPU_TNL_WR_PKT_CNT_TNL",
1386 .has_suffix = true,
1387 .reg_offset_group = {1},
1388 .group_size = 1
1389 }, {
1390 .reg_name = "RPU2HST_TNL_WR_PKT_CNT_TNL",
1391 .has_suffix = true,
1392 .reg_offset_group = {12},
1393 .group_size = 1
1394 }
1395 };
1396
1397 static const struct hclge_mod_reg_info hclge_gen_reg_info[] = {
1398 {
1399 .reg_name = "SSU_OVERSIZE_DROP_CNT",
1400 .reg_offset_group = {12},
1401 .group_size = 1
1402 }, {
1403 .reg_name = "ROCE_RX_BYPASS_5NS_DROP_NUM",
1404 .reg_offset_group = {13},
1405 .group_size = 1
1406 }, {
1407 .reg_name = "RX_PKT_IN/OUT_ERR_CNT",
1408 .reg_offset_group = {15, 14, 19, 18},
1409 .group_size = 4
1410 }, {
1411 .reg_name = "TX_PKT_IN/OUT_ERR_CNT",
1412 .reg_offset_group = {17, 16, 21, 20},
1413 .group_size = 4
1414 }, {
1415 .reg_name = "ETS_TC_READY",
1416 .reg_offset_group = {22},
1417 .group_size = 1
1418 }, {
1419 .reg_name = "MIB_TX/RX_BAD_PKTS",
1420 .reg_offset_group = {19, 18, 29, 28},
1421 .group_size = 4
1422 }, {
1423 .reg_name = "MIB_TX/RX_GOOD_PKTS",
1424 .reg_offset_group = {21, 20, 31, 30},
1425 .group_size = 4
1426 }, {
1427 .reg_name = "MIB_TX/RX_TOTAL_PKTS",
1428 .reg_offset_group = {23, 22, 33, 32},
1429 .group_size = 4
1430 }, {
1431 .reg_name = "MIB_TX/RX_PAUSE_PKTS",
1432 .reg_offset_group = {25, 24, 35, 34},
1433 .group_size = 4
1434 }, {
1435 .reg_name = "MIB_TX_ERR_ALL_PKTS",
1436 .reg_offset_group = {27, 26},
1437 .group_size = 2
1438 }, {
1439 .reg_name = "MIB_RX_FCS_ERR_PKTS",
1440 .reg_offset_group = {37, 36},
1441 .group_size = 2
1442 }, {
1443 .reg_name = "IGU_EGU_AUTO_GATE_EN",
1444 .reg_offset_group = {42},
1445 .group_size = 1
1446 }, {
1447 .reg_name = "IGU_EGU_INT_SRC",
1448 .reg_offset_group = {43},
1449 .group_size = 1
1450 }, {
1451 .reg_name = "EGU_READY_NUM_CFG",
1452 .reg_offset_group = {44},
1453 .group_size = 1
1454 }, {
1455 .reg_name = "IGU_EGU_TNL_DFX",
1456 .reg_offset_group = {45},
1457 .group_size = 1
1458 }, {
1459 .reg_name = "TX_TNL_NOTE_PKT",
1460 .reg_offset_group = {46},
1461 .group_size = 1
1462 }
1463 };
1464
1465 static const struct hclge_mod_reg_common_msg hclge_ssu_reg_common_msg[] = {
1466 {
1467 .cmd = HCLGE_OPC_DFX_SSU_REG_0,
1468 .result_regs = hclge_ssu_reg_0_info,
1469 .bd_num = HCLGE_BD_NUM_SSU_REG_0,
1470 .result_regs_size = ARRAY_SIZE(hclge_ssu_reg_0_info)
1471 }, {
1472 .cmd = HCLGE_OPC_DFX_SSU_REG_1,
1473 .result_regs = hclge_ssu_reg_1_info,
1474 .bd_num = HCLGE_BD_NUM_SSU_REG_1,
1475 .result_regs_size = ARRAY_SIZE(hclge_ssu_reg_1_info)
1476 }, {
1477 .cmd = HCLGE_OPC_DFX_RPU_REG_0,
1478 .result_regs = hclge_rpu_reg_0_info,
1479 .bd_num = HCLGE_BD_NUM_RPU_REG_0,
1480 .result_regs_size = ARRAY_SIZE(hclge_rpu_reg_0_info),
1481 .need_para = true
1482 }, {
1483 .cmd = HCLGE_OPC_DFX_RPU_REG_1,
1484 .result_regs = hclge_rpu_reg_1_info,
1485 .bd_num = HCLGE_BD_NUM_RPU_REG_1,
1486 .result_regs_size = ARRAY_SIZE(hclge_rpu_reg_1_info)
1487 }, {
1488 .cmd = HCLGE_OPC_DFX_IGU_EGU_REG,
1489 .result_regs = hclge_igu_egu_reg_info,
1490 .bd_num = HCLGE_BD_NUM_IGU_EGU_REG,
1491 .result_regs_size = ARRAY_SIZE(hclge_igu_egu_reg_info)
1492 }, {
1493 .cmd = HCLGE_OPC_DFX_GEN_REG,
1494 .result_regs = hclge_gen_reg_info_tnl,
1495 .bd_num = HCLGE_BD_NUM_GEN_REG,
1496 .result_regs_size = ARRAY_SIZE(hclge_gen_reg_info_tnl),
1497 .need_para = true
1498 }, {
1499 .cmd = HCLGE_OPC_DFX_GEN_REG,
1500 .result_regs = hclge_gen_reg_info,
1501 .bd_num = HCLGE_BD_NUM_GEN_REG,
1502 .result_regs_size = ARRAY_SIZE(hclge_gen_reg_info)
1503 }
1504 };
1505
1506 static int
hclge_print_mod_reg_info(struct device * dev,struct hclge_desc * desc,const struct hclge_mod_reg_info * reg_info,int size)1507 hclge_print_mod_reg_info(struct device *dev, struct hclge_desc *desc,
1508 const struct hclge_mod_reg_info *reg_info, int size)
1509 {
1510 int i, j, pos, actual_len;
1511 u8 offset, bd_idx, index;
1512 char *buf;
1513
1514 buf = kzalloc(HCLGE_MOD_REG_INFO_LEN_MAX, GFP_KERNEL);
1515 if (!buf)
1516 return -ENOMEM;
1517
1518 for (i = 0; i < size; i++) {
1519 actual_len = strlen(reg_info[i].reg_name) +
1520 HCLGE_MOD_REG_EXTRA_LEN +
1521 HCLGE_MOD_REG_VALUE_LEN * reg_info[i].group_size;
1522 if (actual_len > HCLGE_MOD_REG_INFO_LEN_MAX) {
1523 dev_info(dev, "length of reg(%s) is invalid, len=%d\n",
1524 reg_info[i].reg_name, actual_len);
1525 continue;
1526 }
1527
1528 pos = scnprintf(buf, HCLGE_MOD_REG_INFO_LEN_MAX, "%s",
1529 reg_info[i].reg_name);
1530 if (reg_info[i].has_suffix)
1531 pos += scnprintf(buf + pos,
1532 HCLGE_MOD_REG_INFO_LEN_MAX - pos, "%u",
1533 le32_to_cpu(desc->data[0]));
1534 pos += scnprintf(buf + pos,
1535 HCLGE_MOD_REG_INFO_LEN_MAX - pos,
1536 ":");
1537 for (j = 0; j < reg_info[i].group_size; j++) {
1538 offset = reg_info[i].reg_offset_group[j];
1539 index = offset % HCLGE_DESC_DATA_LEN;
1540 bd_idx = offset / HCLGE_DESC_DATA_LEN;
1541 pos += scnprintf(buf + pos,
1542 HCLGE_MOD_REG_INFO_LEN_MAX - pos,
1543 " %08x",
1544 le32_to_cpu(desc[bd_idx].data[index]));
1545 }
1546 dev_info(dev, "%s\n", buf);
1547 }
1548
1549 kfree(buf);
1550 return 0;
1551 }
1552
hclge_err_mod_check_support_cmd(enum hclge_opcode_type opcode,struct hclge_dev * hdev)1553 static bool hclge_err_mod_check_support_cmd(enum hclge_opcode_type opcode,
1554 struct hclge_dev *hdev)
1555 {
1556 if (opcode == HCLGE_OPC_DFX_GEN_REG &&
1557 !hnae3_ae_dev_gen_reg_dfx_supported(hdev))
1558 return false;
1559 return true;
1560 }
1561
1562 /* For each common msg, send cmdq to IMP and print result reg info.
1563 * If there is a parameter, loop it and request.
1564 */
1565 static void
hclge_query_reg_info(struct hclge_dev * hdev,struct hclge_mod_reg_common_msg * msg,u32 loop_time,u32 * loop_para)1566 hclge_query_reg_info(struct hclge_dev *hdev,
1567 struct hclge_mod_reg_common_msg *msg, u32 loop_time,
1568 u32 *loop_para)
1569 {
1570 int desc_len, i, ret;
1571
1572 desc_len = msg->bd_num * sizeof(struct hclge_desc);
1573 msg->desc = kzalloc(desc_len, GFP_KERNEL);
1574 if (!msg->desc) {
1575 dev_err(&hdev->pdev->dev, "failed to query reg info, ret=%d",
1576 -ENOMEM);
1577 return;
1578 }
1579
1580 for (i = 0; i < loop_time; i++) {
1581 ret = hclge_dbg_cmd_send(hdev, msg->desc, *loop_para,
1582 msg->bd_num, msg->cmd);
1583 loop_para++;
1584 if (ret)
1585 continue;
1586 ret = hclge_print_mod_reg_info(&hdev->pdev->dev, msg->desc,
1587 msg->result_regs,
1588 msg->result_regs_size);
1589 if (ret)
1590 dev_err(&hdev->pdev->dev, "failed to print mod reg info, ret=%d\n",
1591 ret);
1592 }
1593
1594 kfree(msg->desc);
1595 msg->desc = NULL;
1596 }
1597
hclge_query_reg_info_of_ssu(struct hclge_dev * hdev)1598 static void hclge_query_reg_info_of_ssu(struct hclge_dev *hdev)
1599 {
1600 u32 loop_para[HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE] = {0};
1601 struct hclge_mod_reg_common_msg msg;
1602 u8 i, j, num, loop_time;
1603
1604 num = ARRAY_SIZE(hclge_ssu_reg_common_msg);
1605 for (i = 0; i < num; i++) {
1606 msg = hclge_ssu_reg_common_msg[i];
1607 if (!hclge_err_mod_check_support_cmd(msg.cmd, hdev))
1608 continue;
1609 loop_time = 1;
1610 loop_para[0] = 0;
1611 if (msg.need_para) {
1612 loop_time = min(hdev->ae_dev->dev_specs.tnl_num,
1613 HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE);
1614 for (j = 0; j < loop_time; j++)
1615 loop_para[j] = j + 1;
1616 }
1617 hclge_query_reg_info(hdev, &msg, loop_time, loop_para);
1618 }
1619 }
1620
1621 static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
1622 {
1623 .module_id = MODULE_NONE,
1624 .msg = "MODULE_NONE"
1625 }, {
1626 .module_id = MODULE_BIOS_COMMON,
1627 .msg = "MODULE_BIOS_COMMON"
1628 }, {
1629 .module_id = MODULE_GE,
1630 .msg = "MODULE_GE"
1631 }, {
1632 .module_id = MODULE_IGU_EGU,
1633 .msg = "MODULE_IGU_EGU",
1634 .query_reg_info = hclge_query_reg_info_of_ssu
1635 }, {
1636 .module_id = MODULE_LGE,
1637 .msg = "MODULE_LGE"
1638 }, {
1639 .module_id = MODULE_NCSI,
1640 .msg = "MODULE_NCSI"
1641 }, {
1642 .module_id = MODULE_PPP,
1643 .msg = "MODULE_PPP"
1644 }, {
1645 .module_id = MODULE_QCN,
1646 .msg = "MODULE_QCN"
1647 }, {
1648 .module_id = MODULE_RCB_RX,
1649 .msg = "MODULE_RCB_RX"
1650 }, {
1651 .module_id = MODULE_RTC,
1652 .msg = "MODULE_RTC"
1653 }, {
1654 .module_id = MODULE_SSU,
1655 .msg = "MODULE_SSU",
1656 .query_reg_info = hclge_query_reg_info_of_ssu
1657 }, {
1658 .module_id = MODULE_TM,
1659 .msg = "MODULE_TM"
1660 }, {
1661 .module_id = MODULE_RCB_TX,
1662 .msg = "MODULE_RCB_TX"
1663 }, {
1664 .module_id = MODULE_TXDMA,
1665 .msg = "MODULE_TXDMA"
1666 }, {
1667 .module_id = MODULE_MASTER,
1668 .msg = "MODULE_MASTER"
1669 }, {
1670 .module_id = MODULE_HIMAC,
1671 .msg = "MODULE_HIMAC"
1672 }, {
1673 .module_id = MODULE_ROCEE_TOP,
1674 .msg = "MODULE_ROCEE_TOP"
1675 }, {
1676 .module_id = MODULE_ROCEE_TIMER,
1677 .msg = "MODULE_ROCEE_TIMER"
1678 }, {
1679 .module_id = MODULE_ROCEE_MDB,
1680 .msg = "MODULE_ROCEE_MDB"
1681 }, {
1682 .module_id = MODULE_ROCEE_TSP,
1683 .msg = "MODULE_ROCEE_TSP"
1684 }, {
1685 .module_id = MODULE_ROCEE_TRP,
1686 .msg = "MODULE_ROCEE_TRP"
1687 }, {
1688 .module_id = MODULE_ROCEE_SCC,
1689 .msg = "MODULE_ROCEE_SCC"
1690 }, {
1691 .module_id = MODULE_ROCEE_CAEP,
1692 .msg = "MODULE_ROCEE_CAEP"
1693 }, {
1694 .module_id = MODULE_ROCEE_GEN_AC,
1695 .msg = "MODULE_ROCEE_GEN_AC"
1696 }, {
1697 .module_id = MODULE_ROCEE_QMM,
1698 .msg = "MODULE_ROCEE_QMM"
1699 }, {
1700 .module_id = MODULE_ROCEE_LSAN,
1701 .msg = "MODULE_ROCEE_LSAN"
1702 }
1703 };
1704
1705 static const struct hclge_hw_type_id hclge_hw_type_id_st[] = {
1706 {
1707 .type_id = NONE_ERROR,
1708 .msg = "none_error"
1709 }, {
1710 .type_id = FIFO_ERROR,
1711 .msg = "fifo_error"
1712 }, {
1713 .type_id = MEMORY_ERROR,
1714 .msg = "memory_error"
1715 }, {
1716 .type_id = POISON_ERROR,
1717 .msg = "poison_error"
1718 }, {
1719 .type_id = MSIX_ECC_ERROR,
1720 .msg = "msix_ecc_error"
1721 }, {
1722 .type_id = TQP_INT_ECC_ERROR,
1723 .msg = "tqp_int_ecc_error"
1724 }, {
1725 .type_id = PF_ABNORMAL_INT_ERROR,
1726 .msg = "pf_abnormal_int_error",
1727 .cause_by_vf = true
1728 }, {
1729 .type_id = MPF_ABNORMAL_INT_ERROR,
1730 .msg = "mpf_abnormal_int_error",
1731 .cause_by_vf = true
1732 }, {
1733 .type_id = COMMON_ERROR,
1734 .msg = "common_error"
1735 }, {
1736 .type_id = PORT_ERROR,
1737 .msg = "port_error"
1738 }, {
1739 .type_id = ETS_ERROR,
1740 .msg = "ets_error"
1741 }, {
1742 .type_id = NCSI_ERROR,
1743 .msg = "ncsi_error"
1744 }, {
1745 .type_id = GLB_ERROR,
1746 .msg = "glb_error"
1747 }, {
1748 .type_id = LINK_ERROR,
1749 .msg = "link_error"
1750 }, {
1751 .type_id = PTP_ERROR,
1752 .msg = "ptp_error"
1753 }, {
1754 .type_id = ROCEE_NORMAL_ERR,
1755 .msg = "rocee_normal_error"
1756 }, {
1757 .type_id = ROCEE_OVF_ERR,
1758 .msg = "rocee_ovf_error"
1759 }, {
1760 .type_id = ROCEE_BUS_ERR,
1761 .msg = "rocee_bus_error"
1762 },
1763 };
1764
hclge_log_error(struct device * dev,const char * reg,const struct hclge_hw_error * err,u32 err_sts,unsigned long * reset_requests)1765 static void hclge_log_error(struct device *dev, const char *reg,
1766 const struct hclge_hw_error *err,
1767 u32 err_sts, unsigned long *reset_requests)
1768 {
1769 while (err->msg) {
1770 if (err->int_msk & err_sts) {
1771 dev_err(dev, "%s %s found [error status=0x%x]\n",
1772 reg, err->msg, err_sts);
1773 if (err->reset_level &&
1774 err->reset_level != HNAE3_NONE_RESET)
1775 set_bit(err->reset_level, reset_requests);
1776 }
1777 err++;
1778 }
1779 }
1780
1781 /* hclge_cmd_query_error: read the error information
1782 * @hdev: pointer to struct hclge_dev
1783 * @desc: descriptor for describing the command
1784 * @cmd: command opcode
1785 * @flag: flag for extended command structure
1786 *
1787 * This function query the error info from hw register/s using command
1788 */
hclge_cmd_query_error(struct hclge_dev * hdev,struct hclge_desc * desc,u32 cmd,u16 flag)1789 static int hclge_cmd_query_error(struct hclge_dev *hdev,
1790 struct hclge_desc *desc, u32 cmd, u16 flag)
1791 {
1792 struct device *dev = &hdev->pdev->dev;
1793 int desc_num = 1;
1794 int ret;
1795
1796 hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
1797 if (flag) {
1798 desc[0].flag |= cpu_to_le16(flag);
1799 hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
1800 desc_num = 2;
1801 }
1802
1803 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num);
1804 if (ret)
1805 dev_err(dev, "query error cmd failed (%d)\n", ret);
1806
1807 return ret;
1808 }
1809
hclge_clear_mac_tnl_int(struct hclge_dev * hdev)1810 static int hclge_clear_mac_tnl_int(struct hclge_dev *hdev)
1811 {
1812 struct hclge_desc desc;
1813
1814 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_MAC_TNL_INT, false);
1815 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_CLR);
1816
1817 return hclge_cmd_send(&hdev->hw, &desc, 1);
1818 }
1819
hclge_config_common_hw_err_int(struct hclge_dev * hdev,bool en)1820 static int hclge_config_common_hw_err_int(struct hclge_dev *hdev, bool en)
1821 {
1822 struct device *dev = &hdev->pdev->dev;
1823 struct hclge_desc desc[2];
1824 int ret;
1825
1826 /* configure common error interrupts */
1827 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_COMMON_ECC_INT_CFG, false);
1828 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1829 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_COMMON_ECC_INT_CFG, false);
1830
1831 if (en) {
1832 desc[0].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN);
1833 desc[0].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN |
1834 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN);
1835 desc[0].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN);
1836 desc[0].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN |
1837 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN);
1838 desc[0].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN);
1839 }
1840
1841 desc[1].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK);
1842 desc[1].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK |
1843 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK);
1844 desc[1].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK);
1845 desc[1].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN_MASK |
1846 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1847 desc[1].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1848
1849 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
1850 if (ret)
1851 dev_err(dev,
1852 "fail(%d) to configure common err interrupts\n", ret);
1853
1854 return ret;
1855 }
1856
hclge_config_ncsi_hw_err_int(struct hclge_dev * hdev,bool en)1857 static int hclge_config_ncsi_hw_err_int(struct hclge_dev *hdev, bool en)
1858 {
1859 struct device *dev = &hdev->pdev->dev;
1860 struct hclge_desc desc;
1861 int ret;
1862
1863 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
1864 return 0;
1865
1866 /* configure NCSI error interrupts */
1867 hclge_cmd_setup_basic_desc(&desc, HCLGE_NCSI_INT_EN, false);
1868 if (en)
1869 desc.data[0] = cpu_to_le32(HCLGE_NCSI_ERR_INT_EN);
1870
1871 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1872 if (ret)
1873 dev_err(dev,
1874 "fail(%d) to configure NCSI error interrupts\n", ret);
1875
1876 return ret;
1877 }
1878
hclge_config_igu_egu_hw_err_int(struct hclge_dev * hdev,bool en)1879 static int hclge_config_igu_egu_hw_err_int(struct hclge_dev *hdev, bool en)
1880 {
1881 struct device *dev = &hdev->pdev->dev;
1882 struct hclge_desc desc;
1883 int ret;
1884
1885 /* configure IGU,EGU error interrupts */
1886 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false);
1887 desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_TYPE);
1888 if (en)
1889 desc.data[0] |= cpu_to_le32(HCLGE_IGU_ERR_INT_EN);
1890
1891 desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK);
1892
1893 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1894 if (ret) {
1895 dev_err(dev,
1896 "fail(%d) to configure IGU common interrupts\n", ret);
1897 return ret;
1898 }
1899
1900 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_EGU_TNL_INT_EN, false);
1901 if (en)
1902 desc.data[0] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN);
1903
1904 desc.data[1] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN_MASK);
1905
1906 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1907 if (ret) {
1908 dev_err(dev,
1909 "fail(%d) to configure IGU-EGU TNL interrupts\n", ret);
1910 return ret;
1911 }
1912
1913 ret = hclge_config_ncsi_hw_err_int(hdev, en);
1914
1915 return ret;
1916 }
1917
hclge_config_ppp_error_interrupt(struct hclge_dev * hdev,u32 cmd,bool en)1918 static int hclge_config_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd,
1919 bool en)
1920 {
1921 struct device *dev = &hdev->pdev->dev;
1922 struct hclge_desc desc[2];
1923 int ret;
1924
1925 /* configure PPP error interrupts */
1926 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
1927 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1928 hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
1929
1930 if (cmd == HCLGE_PPP_CMD0_INT_CMD) {
1931 if (en) {
1932 desc[0].data[0] =
1933 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN);
1934 desc[0].data[1] =
1935 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN);
1936 desc[0].data[4] = cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN);
1937 }
1938
1939 desc[1].data[0] =
1940 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK);
1941 desc[1].data[1] =
1942 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK);
1943 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
1944 desc[1].data[2] =
1945 cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN_MASK);
1946 } else if (cmd == HCLGE_PPP_CMD1_INT_CMD) {
1947 if (en) {
1948 desc[0].data[0] =
1949 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN);
1950 desc[0].data[1] =
1951 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN);
1952 }
1953
1954 desc[1].data[0] =
1955 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK);
1956 desc[1].data[1] =
1957 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK);
1958 }
1959
1960 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
1961 if (ret)
1962 dev_err(dev, "fail(%d) to configure PPP error intr\n", ret);
1963
1964 return ret;
1965 }
1966
hclge_config_ppp_hw_err_int(struct hclge_dev * hdev,bool en)1967 static int hclge_config_ppp_hw_err_int(struct hclge_dev *hdev, bool en)
1968 {
1969 int ret;
1970
1971 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD0_INT_CMD,
1972 en);
1973 if (ret)
1974 return ret;
1975
1976 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD1_INT_CMD,
1977 en);
1978
1979 return ret;
1980 }
1981
hclge_config_tm_hw_err_int(struct hclge_dev * hdev,bool en)1982 static int hclge_config_tm_hw_err_int(struct hclge_dev *hdev, bool en)
1983 {
1984 struct device *dev = &hdev->pdev->dev;
1985 struct hclge_desc desc;
1986 int ret;
1987
1988 /* configure TM SCH hw errors */
1989 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_SCH_ECC_INT_EN, false);
1990 if (en)
1991 desc.data[0] = cpu_to_le32(HCLGE_TM_SCH_ECC_ERR_INT_EN);
1992
1993 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1994 if (ret) {
1995 dev_err(dev, "fail(%d) to configure TM SCH errors\n", ret);
1996 return ret;
1997 }
1998
1999 /* configure TM QCN hw errors */
2000 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_QCN_MEM_INT_CFG, false);
2001 desc.data[0] = cpu_to_le32(HCLGE_TM_QCN_ERR_INT_TYPE);
2002 if (en) {
2003 desc.data[0] |= cpu_to_le32(HCLGE_TM_QCN_FIFO_INT_EN);
2004 desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN);
2005 }
2006
2007 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2008 if (ret)
2009 dev_err(dev,
2010 "fail(%d) to configure TM QCN mem errors\n", ret);
2011
2012 return ret;
2013 }
2014
hclge_config_mac_err_int(struct hclge_dev * hdev,bool en)2015 static int hclge_config_mac_err_int(struct hclge_dev *hdev, bool en)
2016 {
2017 struct device *dev = &hdev->pdev->dev;
2018 struct hclge_desc desc;
2019 int ret;
2020
2021 /* configure MAC common error interrupts */
2022 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_COMMON_INT_EN, false);
2023 if (en)
2024 desc.data[0] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN);
2025
2026 desc.data[1] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN_MASK);
2027
2028 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2029 if (ret)
2030 dev_err(dev,
2031 "fail(%d) to configure MAC COMMON error intr\n", ret);
2032
2033 return ret;
2034 }
2035
hclge_config_mac_tnl_int(struct hclge_dev * hdev,bool en)2036 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en)
2037 {
2038 struct hclge_desc desc;
2039
2040 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_TNL_INT_EN, false);
2041 if (en)
2042 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN);
2043 else
2044 desc.data[0] = 0;
2045
2046 desc.data[1] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN_MASK);
2047
2048 return hclge_cmd_send(&hdev->hw, &desc, 1);
2049 }
2050
hclge_config_ppu_error_interrupts(struct hclge_dev * hdev,u32 cmd,bool en)2051 static int hclge_config_ppu_error_interrupts(struct hclge_dev *hdev, u32 cmd,
2052 bool en)
2053 {
2054 struct device *dev = &hdev->pdev->dev;
2055 struct hclge_desc desc[2];
2056 int desc_num = 1;
2057 int ret;
2058
2059 /* configure PPU error interrupts */
2060 if (cmd == HCLGE_PPU_MPF_ECC_INT_CMD) {
2061 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
2062 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2063 hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
2064 if (en) {
2065 desc[0].data[0] =
2066 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT0_EN);
2067 desc[0].data[1] =
2068 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT1_EN);
2069 desc[1].data[3] =
2070 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT3_EN);
2071 desc[1].data[4] =
2072 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN);
2073 }
2074
2075 desc[1].data[0] =
2076 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK);
2077 desc[1].data[1] =
2078 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK);
2079 desc[1].data[2] =
2080 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK);
2081 desc[1].data[3] |=
2082 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK);
2083 desc_num = 2;
2084 } else if (cmd == HCLGE_PPU_MPF_OTHER_INT_CMD) {
2085 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
2086 if (en)
2087 desc[0].data[0] =
2088 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN2);
2089
2090 desc[0].data[2] =
2091 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK);
2092 } else if (cmd == HCLGE_PPU_PF_OTHER_INT_CMD) {
2093 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
2094 if (en)
2095 desc[0].data[0] =
2096 cpu_to_le32(HCLGE_PPU_PF_ABNORMAL_INT_EN);
2097
2098 desc[0].data[2] =
2099 cpu_to_le32(HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK);
2100 } else {
2101 dev_err(dev, "Invalid cmd to configure PPU error interrupts\n");
2102 return -EINVAL;
2103 }
2104
2105 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num);
2106
2107 return ret;
2108 }
2109
hclge_config_ppu_hw_err_int(struct hclge_dev * hdev,bool en)2110 static int hclge_config_ppu_hw_err_int(struct hclge_dev *hdev, bool en)
2111 {
2112 struct device *dev = &hdev->pdev->dev;
2113 int ret;
2114
2115 ret = hclge_config_ppu_error_interrupts(hdev, HCLGE_PPU_MPF_ECC_INT_CMD,
2116 en);
2117 if (ret) {
2118 dev_err(dev, "fail(%d) to configure PPU MPF ECC error intr\n",
2119 ret);
2120 return ret;
2121 }
2122
2123 ret = hclge_config_ppu_error_interrupts(hdev,
2124 HCLGE_PPU_MPF_OTHER_INT_CMD,
2125 en);
2126 if (ret) {
2127 dev_err(dev, "fail(%d) to configure PPU MPF other intr\n", ret);
2128 return ret;
2129 }
2130
2131 ret = hclge_config_ppu_error_interrupts(hdev,
2132 HCLGE_PPU_PF_OTHER_INT_CMD, en);
2133 if (ret)
2134 dev_err(dev, "fail(%d) to configure PPU PF error interrupts\n",
2135 ret);
2136 return ret;
2137 }
2138
hclge_config_ssu_hw_err_int(struct hclge_dev * hdev,bool en)2139 static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
2140 {
2141 struct device *dev = &hdev->pdev->dev;
2142 struct hclge_desc desc[2];
2143 int ret;
2144
2145 /* configure SSU ecc error interrupts */
2146 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_ECC_INT_CMD, false);
2147 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2148 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_ECC_INT_CMD, false);
2149 if (en) {
2150 desc[0].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN);
2151 desc[0].data[1] =
2152 cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN);
2153 desc[0].data[4] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN);
2154 }
2155
2156 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK);
2157 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
2158 desc[1].data[2] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK);
2159
2160 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
2161 if (ret) {
2162 dev_err(dev,
2163 "fail(%d) to configure SSU ECC error interrupt\n", ret);
2164 return ret;
2165 }
2166
2167 /* configure SSU common error interrupts */
2168 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_COMMON_INT_CMD, false);
2169 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2170 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false);
2171
2172 if (en) {
2173 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
2174 desc[0].data[0] =
2175 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN);
2176 else
2177 desc[0].data[0] =
2178 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN & ~BIT(5));
2179 desc[0].data[1] = cpu_to_le32(HCLGE_SSU_PORT_BASED_ERR_INT_EN);
2180 desc[0].data[2] =
2181 cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN);
2182 }
2183
2184 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_COMMON_INT_EN_MASK |
2185 HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK);
2186 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
2187
2188 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
2189 if (ret)
2190 dev_err(dev,
2191 "fail(%d) to configure SSU COMMON error intr\n", ret);
2192
2193 return ret;
2194 }
2195
2196 /* hclge_query_bd_num: query number of buffer descriptors
2197 * @hdev: pointer to struct hclge_dev
2198 * @is_ras: true for ras, false for msix
2199 * @mpf_bd_num: number of main PF interrupt buffer descriptors
2200 * @pf_bd_num: number of not main PF interrupt buffer descriptors
2201 *
2202 * This function querys number of mpf and pf buffer descriptors.
2203 */
hclge_query_bd_num(struct hclge_dev * hdev,bool is_ras,u32 * mpf_bd_num,u32 * pf_bd_num)2204 static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras,
2205 u32 *mpf_bd_num, u32 *pf_bd_num)
2206 {
2207 struct device *dev = &hdev->pdev->dev;
2208 u32 mpf_min_bd_num, pf_min_bd_num;
2209 enum hclge_opcode_type opcode;
2210 struct hclge_desc desc_bd;
2211 int ret;
2212
2213 if (is_ras) {
2214 opcode = HCLGE_QUERY_RAS_INT_STS_BD_NUM;
2215 mpf_min_bd_num = HCLGE_MPF_RAS_INT_MIN_BD_NUM;
2216 pf_min_bd_num = HCLGE_PF_RAS_INT_MIN_BD_NUM;
2217 } else {
2218 opcode = HCLGE_QUERY_MSIX_INT_STS_BD_NUM;
2219 mpf_min_bd_num = HCLGE_MPF_MSIX_INT_MIN_BD_NUM;
2220 pf_min_bd_num = HCLGE_PF_MSIX_INT_MIN_BD_NUM;
2221 }
2222
2223 hclge_cmd_setup_basic_desc(&desc_bd, opcode, true);
2224 ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1);
2225 if (ret) {
2226 dev_err(dev, "fail(%d) to query msix int status bd num\n",
2227 ret);
2228 return ret;
2229 }
2230
2231 *mpf_bd_num = le32_to_cpu(desc_bd.data[0]);
2232 *pf_bd_num = le32_to_cpu(desc_bd.data[1]);
2233 if (*mpf_bd_num < mpf_min_bd_num || *pf_bd_num < pf_min_bd_num) {
2234 dev_err(dev, "Invalid bd num: mpf(%u), pf(%u)\n",
2235 *mpf_bd_num, *pf_bd_num);
2236 return -EINVAL;
2237 }
2238
2239 return 0;
2240 }
2241
2242 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors
2243 * @hdev: pointer to struct hclge_dev
2244 * @desc: descriptor for describing the command
2245 * @num: number of extended command structures
2246 *
2247 * This function handles all the main PF RAS errors in the
2248 * hw register/s using command.
2249 */
hclge_handle_mpf_ras_error(struct hclge_dev * hdev,struct hclge_desc * desc,int num)2250 static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
2251 struct hclge_desc *desc,
2252 int num)
2253 {
2254 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
2255 struct device *dev = &hdev->pdev->dev;
2256 __le32 *desc_data;
2257 u32 status;
2258 int ret;
2259
2260 /* query all main PF RAS errors */
2261 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_MPF_RAS_INT,
2262 true);
2263 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
2264 if (ret) {
2265 dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret);
2266 return ret;
2267 }
2268
2269 /* log HNS common errors */
2270 status = le32_to_cpu(desc[0].data[0]);
2271 if (status)
2272 hclge_log_error(dev, "IMP_TCM_ECC_INT_STS",
2273 &hclge_imp_tcm_ecc_int[0], status,
2274 &ae_dev->hw_err_reset_req);
2275
2276 status = le32_to_cpu(desc[0].data[1]);
2277 if (status)
2278 hclge_log_error(dev, "CMDQ_MEM_ECC_INT_STS",
2279 &hclge_cmdq_nic_mem_ecc_int[0], status,
2280 &ae_dev->hw_err_reset_req);
2281
2282 if ((le32_to_cpu(desc[0].data[2])) & BIT(0))
2283 dev_warn(dev, "imp_rd_data_poison_err found\n");
2284
2285 status = le32_to_cpu(desc[0].data[3]);
2286 if (status)
2287 hclge_log_error(dev, "TQP_INT_ECC_INT_STS",
2288 &hclge_tqp_int_ecc_int[0], status,
2289 &ae_dev->hw_err_reset_req);
2290
2291 status = le32_to_cpu(desc[0].data[4]);
2292 if (status)
2293 hclge_log_error(dev, "MSIX_ECC_INT_STS",
2294 &hclge_msix_sram_ecc_int[0], status,
2295 &ae_dev->hw_err_reset_req);
2296
2297 /* log SSU(Storage Switch Unit) errors */
2298 desc_data = (__le32 *)&desc[2];
2299 status = le32_to_cpu(*(desc_data + 2));
2300 if (status)
2301 hclge_log_error(dev, "SSU_ECC_MULTI_BIT_INT_0",
2302 &hclge_ssu_mem_ecc_err_int[0], status,
2303 &ae_dev->hw_err_reset_req);
2304
2305 status = le32_to_cpu(*(desc_data + 3)) & BIT(0);
2306 if (status) {
2307 dev_err(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n",
2308 status);
2309 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);
2310 }
2311
2312 status = le32_to_cpu(*(desc_data + 4)) & HCLGE_SSU_COMMON_ERR_INT_MASK;
2313 if (status)
2314 hclge_log_error(dev, "SSU_COMMON_ERR_INT",
2315 &hclge_ssu_com_err_int[0], status,
2316 &ae_dev->hw_err_reset_req);
2317
2318 /* log IGU(Ingress Unit) errors */
2319 desc_data = (__le32 *)&desc[3];
2320 status = le32_to_cpu(*desc_data) & HCLGE_IGU_INT_MASK;
2321 if (status)
2322 hclge_log_error(dev, "IGU_INT_STS",
2323 &hclge_igu_int[0], status,
2324 &ae_dev->hw_err_reset_req);
2325
2326 /* log PPP(Programmable Packet Process) errors */
2327 desc_data = (__le32 *)&desc[4];
2328 status = le32_to_cpu(*(desc_data + 1));
2329 if (status)
2330 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST1",
2331 &hclge_ppp_mpf_abnormal_int_st1[0], status,
2332 &ae_dev->hw_err_reset_req);
2333
2334 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPP_MPF_INT_ST3_MASK;
2335 if (status)
2336 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST3",
2337 &hclge_ppp_mpf_abnormal_int_st3[0], status,
2338 &ae_dev->hw_err_reset_req);
2339
2340 /* log PPU(RCB) errors */
2341 desc_data = (__le32 *)&desc[5];
2342 status = le32_to_cpu(*(desc_data + 1));
2343 if (status) {
2344 dev_err(dev,
2345 "PPU_MPF_ABNORMAL_INT_ST1 rpu_rx_pkt_ecc_mbit_err found\n");
2346 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);
2347 }
2348
2349 status = le32_to_cpu(*(desc_data + 2));
2350 if (status)
2351 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2",
2352 &hclge_ppu_mpf_abnormal_int_st2[0], status,
2353 &ae_dev->hw_err_reset_req);
2354
2355 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPU_MPF_INT_ST3_MASK;
2356 if (status)
2357 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST3",
2358 &hclge_ppu_mpf_abnormal_int_st3[0], status,
2359 &ae_dev->hw_err_reset_req);
2360
2361 /* log TM(Traffic Manager) errors */
2362 desc_data = (__le32 *)&desc[6];
2363 status = le32_to_cpu(*desc_data);
2364 if (status)
2365 hclge_log_error(dev, "TM_SCH_RINT",
2366 &hclge_tm_sch_rint[0], status,
2367 &ae_dev->hw_err_reset_req);
2368
2369 /* log QCN(Quantized Congestion Control) errors */
2370 desc_data = (__le32 *)&desc[7];
2371 status = le32_to_cpu(*desc_data) & HCLGE_QCN_FIFO_INT_MASK;
2372 if (status)
2373 hclge_log_error(dev, "QCN_FIFO_RINT",
2374 &hclge_qcn_fifo_rint[0], status,
2375 &ae_dev->hw_err_reset_req);
2376
2377 status = le32_to_cpu(*(desc_data + 1)) & HCLGE_QCN_ECC_INT_MASK;
2378 if (status)
2379 hclge_log_error(dev, "QCN_ECC_RINT",
2380 &hclge_qcn_ecc_rint[0], status,
2381 &ae_dev->hw_err_reset_req);
2382
2383 /* log NCSI errors */
2384 desc_data = (__le32 *)&desc[9];
2385 status = le32_to_cpu(*desc_data) & HCLGE_NCSI_ECC_INT_MASK;
2386 if (status)
2387 hclge_log_error(dev, "NCSI_ECC_INT_RPT",
2388 &hclge_ncsi_err_int[0], status,
2389 &ae_dev->hw_err_reset_req);
2390
2391 /* clear all main PF RAS errors */
2392 hclge_comm_cmd_reuse_desc(&desc[0], false);
2393 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
2394 if (ret)
2395 dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret);
2396
2397 return ret;
2398 }
2399
2400 /* hclge_handle_pf_ras_error: handle all PF RAS errors
2401 * @hdev: pointer to struct hclge_dev
2402 * @desc: descriptor for describing the command
2403 * @num: number of extended command structures
2404 *
2405 * This function handles all the PF RAS errors in the
2406 * hw registers using command.
2407 */
hclge_handle_pf_ras_error(struct hclge_dev * hdev,struct hclge_desc * desc,int num)2408 static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
2409 struct hclge_desc *desc,
2410 int num)
2411 {
2412 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
2413 struct device *dev = &hdev->pdev->dev;
2414 __le32 *desc_data;
2415 u32 status;
2416 int ret;
2417
2418 /* query all PF RAS errors */
2419 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_PF_RAS_INT,
2420 true);
2421 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
2422 if (ret) {
2423 dev_err(dev, "query all pf ras int cmd failed (%d)\n", ret);
2424 return ret;
2425 }
2426
2427 /* log SSU(Storage Switch Unit) errors */
2428 status = le32_to_cpu(desc[0].data[0]);
2429 if (status)
2430 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT",
2431 &hclge_ssu_port_based_err_int[0], status,
2432 &ae_dev->hw_err_reset_req);
2433
2434 status = le32_to_cpu(desc[0].data[1]);
2435 if (status)
2436 hclge_log_error(dev, "SSU_FIFO_OVERFLOW_INT",
2437 &hclge_ssu_fifo_overflow_int[0], status,
2438 &ae_dev->hw_err_reset_req);
2439
2440 status = le32_to_cpu(desc[0].data[2]);
2441 if (status)
2442 hclge_log_error(dev, "SSU_ETS_TCG_INT",
2443 &hclge_ssu_ets_tcg_int[0], status,
2444 &ae_dev->hw_err_reset_req);
2445
2446 /* log IGU(Ingress Unit) EGU(Egress Unit) TNL errors */
2447 desc_data = (__le32 *)&desc[1];
2448 status = le32_to_cpu(*desc_data) & HCLGE_IGU_EGU_TNL_INT_MASK;
2449 if (status)
2450 hclge_log_error(dev, "IGU_EGU_TNL_INT_STS",
2451 &hclge_igu_egu_tnl_int[0], status,
2452 &ae_dev->hw_err_reset_req);
2453
2454 /* log PPU(RCB) errors */
2455 desc_data = (__le32 *)&desc[3];
2456 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_RAS_MASK;
2457 if (status) {
2458 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST0",
2459 &hclge_ppu_pf_abnormal_int[0], status,
2460 &ae_dev->hw_err_reset_req);
2461 hclge_report_hw_error(hdev, HNAE3_PPU_POISON_ERROR);
2462 }
2463
2464 /* clear all PF RAS errors */
2465 hclge_comm_cmd_reuse_desc(&desc[0], false);
2466 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
2467 if (ret)
2468 dev_err(dev, "clear all pf ras int cmd failed (%d)\n", ret);
2469
2470 return ret;
2471 }
2472
hclge_handle_all_ras_errors(struct hclge_dev * hdev)2473 static int hclge_handle_all_ras_errors(struct hclge_dev *hdev)
2474 {
2475 u32 mpf_bd_num, pf_bd_num, bd_num;
2476 struct hclge_desc *desc;
2477 int ret;
2478
2479 /* query the number of registers in the RAS int status */
2480 ret = hclge_query_bd_num(hdev, true, &mpf_bd_num, &pf_bd_num);
2481 if (ret)
2482 return ret;
2483
2484 bd_num = max_t(u32, mpf_bd_num, pf_bd_num);
2485 desc = kzalloc_objs(struct hclge_desc, bd_num);
2486 if (!desc)
2487 return -ENOMEM;
2488
2489 /* handle all main PF RAS errors */
2490 ret = hclge_handle_mpf_ras_error(hdev, desc, mpf_bd_num);
2491 if (ret) {
2492 kfree(desc);
2493 return ret;
2494 }
2495 memset(desc, 0, bd_num * sizeof(struct hclge_desc));
2496
2497 /* handle all PF RAS errors */
2498 ret = hclge_handle_pf_ras_error(hdev, desc, pf_bd_num);
2499 kfree(desc);
2500
2501 return ret;
2502 }
2503
hclge_log_rocee_axi_error(struct hclge_dev * hdev)2504 static int hclge_log_rocee_axi_error(struct hclge_dev *hdev)
2505 {
2506 struct device *dev = &hdev->pdev->dev;
2507 struct hclge_desc desc[3];
2508 int ret;
2509
2510 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
2511 true);
2512 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
2513 true);
2514 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
2515 true);
2516 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2517 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2518
2519 ret = hclge_cmd_send(&hdev->hw, &desc[0], 3);
2520 if (ret) {
2521 dev_err(dev, "failed(%d) to query ROCEE AXI error sts\n", ret);
2522 return ret;
2523 }
2524
2525 dev_err(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n",
2526 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
2527 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
2528 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
2529 dev_err(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n",
2530 le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]),
2531 le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]),
2532 le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5]));
2533 dev_err(dev, "AXI3: %08X %08X %08X %08X\n",
2534 le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]),
2535 le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3]));
2536
2537 return 0;
2538 }
2539
hclge_log_rocee_ecc_error(struct hclge_dev * hdev)2540 static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev)
2541 {
2542 struct device *dev = &hdev->pdev->dev;
2543 struct hclge_desc desc[2];
2544 int ret;
2545
2546 ret = hclge_cmd_query_error(hdev, &desc[0],
2547 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD,
2548 HCLGE_COMM_CMD_FLAG_NEXT);
2549 if (ret) {
2550 dev_err(dev, "failed(%d) to query ROCEE ECC error sts\n", ret);
2551 return ret;
2552 }
2553
2554 dev_err(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n",
2555 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
2556 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
2557 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
2558 dev_err(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]),
2559 le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2]));
2560
2561 return 0;
2562 }
2563
hclge_log_rocee_ovf_error(struct hclge_dev * hdev)2564 static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev)
2565 {
2566 struct device *dev = &hdev->pdev->dev;
2567 struct hclge_desc desc[2];
2568 int ret;
2569
2570 /* read overflow error status */
2571 ret = hclge_cmd_query_error(hdev, &desc[0], HCLGE_ROCEE_PF_RAS_INT_CMD,
2572 0);
2573 if (ret) {
2574 dev_err(dev, "failed(%d) to query ROCEE OVF error sts\n", ret);
2575 return ret;
2576 }
2577
2578 /* log overflow error */
2579 if (le32_to_cpu(desc[0].data[0]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
2580 const struct hclge_hw_error *err;
2581 u32 err_sts;
2582
2583 err = &hclge_rocee_qmm_ovf_err_int[0];
2584 err_sts = HCLGE_ROCEE_OVF_ERR_TYPE_MASK &
2585 le32_to_cpu(desc[0].data[0]);
2586 while (err->msg) {
2587 if (err->int_msk == err_sts) {
2588 dev_err(dev, "%s [error status=0x%x] found\n",
2589 err->msg,
2590 le32_to_cpu(desc[0].data[0]));
2591 break;
2592 }
2593 err++;
2594 }
2595 }
2596
2597 if (le32_to_cpu(desc[0].data[1]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
2598 dev_err(dev, "ROCEE TSP OVF [error status=0x%x] found\n",
2599 le32_to_cpu(desc[0].data[1]));
2600 }
2601
2602 if (le32_to_cpu(desc[0].data[2]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
2603 dev_err(dev, "ROCEE SCC OVF [error status=0x%x] found\n",
2604 le32_to_cpu(desc[0].data[2]));
2605 }
2606
2607 return 0;
2608 }
2609
2610 static enum hnae3_reset_type
hclge_log_and_clear_rocee_ras_error(struct hclge_dev * hdev)2611 hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
2612 {
2613 enum hnae3_reset_type reset_type = HNAE3_NONE_RESET;
2614 struct device *dev = &hdev->pdev->dev;
2615 struct hclge_desc desc[2];
2616 unsigned int status;
2617 int ret;
2618
2619 /* read RAS error interrupt status */
2620 ret = hclge_cmd_query_error(hdev, &desc[0],
2621 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT, 0);
2622 if (ret) {
2623 dev_err(dev, "failed(%d) to query ROCEE RAS INT SRC\n", ret);
2624 /* reset everything for now */
2625 return HNAE3_GLOBAL_RESET;
2626 }
2627
2628 status = le32_to_cpu(desc[0].data[0]);
2629 if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) {
2630 if (status & HCLGE_ROCEE_RERR_INT_MASK)
2631 dev_err(dev, "ROCEE RAS AXI rresp error\n");
2632
2633 if (status & HCLGE_ROCEE_BERR_INT_MASK)
2634 dev_err(dev, "ROCEE RAS AXI bresp error\n");
2635
2636 reset_type = HNAE3_FUNC_RESET;
2637
2638 hclge_report_hw_error(hdev, HNAE3_ROCEE_AXI_RESP_ERROR);
2639
2640 ret = hclge_log_rocee_axi_error(hdev);
2641 if (ret)
2642 return HNAE3_GLOBAL_RESET;
2643 }
2644
2645 if (status & HCLGE_ROCEE_ECC_INT_MASK) {
2646 dev_err(dev, "ROCEE RAS 2bit ECC error\n");
2647 reset_type = HNAE3_GLOBAL_RESET;
2648
2649 ret = hclge_log_rocee_ecc_error(hdev);
2650 if (ret)
2651 return HNAE3_GLOBAL_RESET;
2652 }
2653
2654 if (status & HCLGE_ROCEE_OVF_INT_MASK) {
2655 ret = hclge_log_rocee_ovf_error(hdev);
2656 if (ret) {
2657 dev_err(dev, "failed(%d) to process ovf error\n", ret);
2658 /* reset everything for now */
2659 return HNAE3_GLOBAL_RESET;
2660 }
2661 }
2662
2663 /* clear error status */
2664 hclge_comm_cmd_reuse_desc(&desc[0], false);
2665 ret = hclge_cmd_send(&hdev->hw, &desc[0], 1);
2666 if (ret) {
2667 dev_err(dev, "failed(%d) to clear ROCEE RAS error\n", ret);
2668 /* reset everything for now */
2669 return HNAE3_GLOBAL_RESET;
2670 }
2671
2672 return reset_type;
2673 }
2674
hclge_config_rocee_ras_interrupt(struct hclge_dev * hdev,bool en)2675 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en)
2676 {
2677 struct device *dev = &hdev->pdev->dev;
2678 struct hclge_desc desc;
2679 int ret;
2680
2681 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||
2682 !hnae3_dev_roce_supported(hdev))
2683 return 0;
2684
2685 hclge_cmd_setup_basic_desc(&desc, HCLGE_CONFIG_ROCEE_RAS_INT_EN, false);
2686 if (en) {
2687 /* enable ROCEE hw error interrupts */
2688 desc.data[0] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN);
2689 desc.data[1] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN);
2690
2691 hclge_log_and_clear_rocee_ras_error(hdev);
2692 }
2693 desc.data[2] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN_MASK);
2694 desc.data[3] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN_MASK);
2695
2696 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2697 if (ret)
2698 dev_err(dev, "failed(%d) to config ROCEE RAS interrupt\n", ret);
2699
2700 return ret;
2701 }
2702
hclge_handle_rocee_ras_error(struct hnae3_ae_dev * ae_dev)2703 static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)
2704 {
2705 struct hclge_dev *hdev = ae_dev->priv;
2706 enum hnae3_reset_type reset_type;
2707
2708 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2709 return;
2710
2711 reset_type = hclge_log_and_clear_rocee_ras_error(hdev);
2712 if (reset_type != HNAE3_NONE_RESET)
2713 set_bit(reset_type, &ae_dev->hw_err_reset_req);
2714 }
2715
2716 static const struct hclge_hw_blk hw_blk[] = {
2717 {
2718 .msk = BIT(0),
2719 .name = "IGU_EGU",
2720 .config_err_int = hclge_config_igu_egu_hw_err_int,
2721 }, {
2722 .msk = BIT(1),
2723 .name = "PPP",
2724 .config_err_int = hclge_config_ppp_hw_err_int,
2725 }, {
2726 .msk = BIT(2),
2727 .name = "SSU",
2728 .config_err_int = hclge_config_ssu_hw_err_int,
2729 }, {
2730 .msk = BIT(3),
2731 .name = "PPU",
2732 .config_err_int = hclge_config_ppu_hw_err_int,
2733 }, {
2734 .msk = BIT(4),
2735 .name = "TM",
2736 .config_err_int = hclge_config_tm_hw_err_int,
2737 }, {
2738 .msk = BIT(5),
2739 .name = "COMMON",
2740 .config_err_int = hclge_config_common_hw_err_int,
2741 }, {
2742 .msk = BIT(8),
2743 .name = "MAC",
2744 .config_err_int = hclge_config_mac_err_int,
2745 }, {
2746 /* sentinel */
2747 }
2748 };
2749
hclge_config_all_msix_error(struct hclge_dev * hdev,bool enable)2750 static void hclge_config_all_msix_error(struct hclge_dev *hdev, bool enable)
2751 {
2752 u32 reg_val;
2753
2754 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2755
2756 if (enable)
2757 reg_val |= BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);
2758 else
2759 reg_val &= ~BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);
2760
2761 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
2762 }
2763
hclge_config_nic_hw_error(struct hclge_dev * hdev,bool state)2764 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state)
2765 {
2766 const struct hclge_hw_blk *module = hw_blk;
2767 int ret = 0;
2768
2769 hclge_config_all_msix_error(hdev, state);
2770
2771 while (module->name) {
2772 if (module->config_err_int) {
2773 ret = module->config_err_int(hdev, state);
2774 if (ret)
2775 return ret;
2776 }
2777 module++;
2778 }
2779
2780 return ret;
2781 }
2782
hclge_handle_hw_ras_error(struct hnae3_ae_dev * ae_dev)2783 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
2784 {
2785 struct hclge_dev *hdev = ae_dev->priv;
2786 struct device *dev = &hdev->pdev->dev;
2787 u32 status;
2788
2789 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) {
2790 dev_err(dev,
2791 "Can't recover - RAS error reported during dev init\n");
2792 return PCI_ERS_RESULT_NONE;
2793 }
2794
2795 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
2796 if (status & HCLGE_RAS_REG_NFE_MASK ||
2797 status & HCLGE_RAS_REG_ROCEE_ERR_MASK)
2798 ae_dev->hw_err_reset_req = 0;
2799 else
2800 goto out;
2801
2802 /* Handling Non-fatal HNS RAS errors */
2803 if (status & HCLGE_RAS_REG_NFE_MASK) {
2804 dev_err(dev,
2805 "HNS Non-Fatal RAS error(status=0x%x) identified\n",
2806 status);
2807 hclge_handle_all_ras_errors(hdev);
2808 }
2809
2810 /* Handling Non-fatal Rocee RAS errors */
2811 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 &&
2812 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {
2813 dev_err(dev, "ROCEE Non-Fatal RAS error identified\n");
2814 hclge_handle_rocee_ras_error(ae_dev);
2815 }
2816
2817 if (ae_dev->hw_err_reset_req)
2818 return PCI_ERS_RESULT_NEED_RESET;
2819
2820 out:
2821 return PCI_ERS_RESULT_RECOVERED;
2822 }
2823
hclge_clear_hw_msix_error(struct hclge_dev * hdev,struct hclge_desc * desc,bool is_mpf,u32 bd_num)2824 static int hclge_clear_hw_msix_error(struct hclge_dev *hdev,
2825 struct hclge_desc *desc, bool is_mpf,
2826 u32 bd_num)
2827 {
2828 if (is_mpf)
2829 desc[0].opcode =
2830 cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT);
2831 else
2832 desc[0].opcode = cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT);
2833
2834 desc[0].flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
2835 HCLGE_COMM_CMD_FLAG_IN);
2836
2837 return hclge_cmd_send(&hdev->hw, &desc[0], bd_num);
2838 }
2839
2840 /* hclge_query_8bd_info: query information about over_8bd_nfe_err
2841 * @hdev: pointer to struct hclge_dev
2842 * @vf_id: Index of the virtual function with error
2843 * @q_id: Physical index of the queue with error
2844 *
2845 * This function get specific index of queue and function which causes
2846 * over_8bd_nfe_err by using command. If vf_id is 0, it means error is
2847 * caused by PF instead of VF.
2848 */
hclge_query_over_8bd_err_info(struct hclge_dev * hdev,u16 * vf_id,u16 * q_id)2849 static int hclge_query_over_8bd_err_info(struct hclge_dev *hdev, u16 *vf_id,
2850 u16 *q_id)
2851 {
2852 struct hclge_query_ppu_pf_other_int_dfx_cmd *req;
2853 struct hclge_desc desc;
2854 int ret;
2855
2856 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PPU_PF_OTHER_INT_DFX, true);
2857 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2858 if (ret)
2859 return ret;
2860
2861 req = (struct hclge_query_ppu_pf_other_int_dfx_cmd *)desc.data;
2862 *vf_id = le16_to_cpu(req->over_8bd_no_fe_vf_id);
2863 *q_id = le16_to_cpu(req->over_8bd_no_fe_qid);
2864
2865 return 0;
2866 }
2867
2868 /* hclge_handle_over_8bd_err: handle MSI-X error named over_8bd_nfe_err
2869 * @hdev: pointer to struct hclge_dev
2870 * @reset_requests: reset level that we need to trigger later
2871 *
2872 * over_8bd_nfe_err is a special MSI-X because it may caused by a VF, in
2873 * that case, we need to trigger VF reset. Otherwise, a PF reset is needed.
2874 */
hclge_handle_over_8bd_err(struct hclge_dev * hdev,unsigned long * reset_requests)2875 static void hclge_handle_over_8bd_err(struct hclge_dev *hdev,
2876 unsigned long *reset_requests)
2877 {
2878 struct device *dev = &hdev->pdev->dev;
2879 u16 vf_id;
2880 u16 q_id;
2881 int ret;
2882
2883 ret = hclge_query_over_8bd_err_info(hdev, &vf_id, &q_id);
2884 if (ret) {
2885 dev_err(dev, "fail(%d) to query over_8bd_no_fe info\n",
2886 ret);
2887 return;
2888 }
2889
2890 dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vport(%u), queue_id(%u)\n",
2891 vf_id, q_id);
2892
2893 if (vf_id) {
2894 if (vf_id >= hdev->num_alloc_vport) {
2895 dev_err(dev, "invalid vport(%u)\n", vf_id);
2896 return;
2897 }
2898
2899 /* If we need to trigger other reset whose level is higher
2900 * than HNAE3_VF_FUNC_RESET, no need to trigger a VF reset
2901 * here.
2902 */
2903 if (*reset_requests != 0)
2904 return;
2905
2906 ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]);
2907 if (ret)
2908 dev_err(dev, "inform reset to vport(%u) failed %d!\n",
2909 vf_id, ret);
2910 } else {
2911 set_bit(HNAE3_FUNC_RESET, reset_requests);
2912 }
2913 }
2914
2915 /* hclge_handle_mpf_msix_error: handle all main PF MSI-X errors
2916 * @hdev: pointer to struct hclge_dev
2917 * @desc: descriptor for describing the command
2918 * @mpf_bd_num: number of extended command structures
2919 * @reset_requests: record of the reset level that we need
2920 *
2921 * This function handles all the main PF MSI-X errors in the hw register/s
2922 * using command.
2923 */
hclge_handle_mpf_msix_error(struct hclge_dev * hdev,struct hclge_desc * desc,int mpf_bd_num,unsigned long * reset_requests)2924 static int hclge_handle_mpf_msix_error(struct hclge_dev *hdev,
2925 struct hclge_desc *desc,
2926 int mpf_bd_num,
2927 unsigned long *reset_requests)
2928 {
2929 struct device *dev = &hdev->pdev->dev;
2930 __le32 *desc_data;
2931 u32 status;
2932 int ret;
2933 /* query all main PF MSIx errors */
2934 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
2935 true);
2936 ret = hclge_cmd_send(&hdev->hw, &desc[0], mpf_bd_num);
2937 if (ret) {
2938 dev_err(dev, "query all mpf msix int cmd failed (%d)\n", ret);
2939 return ret;
2940 }
2941
2942 /* log MAC errors */
2943 desc_data = (__le32 *)&desc[1];
2944 status = le32_to_cpu(*desc_data);
2945 if (status)
2946 hclge_log_error(dev, "MAC_AFIFO_TNL_INT_R",
2947 &hclge_mac_afifo_tnl_int[0], status,
2948 reset_requests);
2949
2950 /* log PPU(RCB) MPF errors */
2951 desc_data = (__le32 *)&desc[5];
2952 status = le32_to_cpu(*(desc_data + 2)) &
2953 HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;
2954 if (status)
2955 dev_err(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",
2956 status);
2957
2958 /* clear all main PF MSIx errors */
2959 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num);
2960 if (ret)
2961 dev_err(dev, "clear all mpf msix int cmd failed (%d)\n", ret);
2962
2963 return ret;
2964 }
2965
2966 /* hclge_handle_pf_msix_error: handle all PF MSI-X errors
2967 * @hdev: pointer to struct hclge_dev
2968 * @desc: descriptor for describing the command
2969 * @mpf_bd_num: number of extended command structures
2970 * @reset_requests: record of the reset level that we need
2971 *
2972 * This function handles all the PF MSI-X errors in the hw register/s using
2973 * command.
2974 */
hclge_handle_pf_msix_error(struct hclge_dev * hdev,struct hclge_desc * desc,int pf_bd_num,unsigned long * reset_requests)2975 static int hclge_handle_pf_msix_error(struct hclge_dev *hdev,
2976 struct hclge_desc *desc,
2977 int pf_bd_num,
2978 unsigned long *reset_requests)
2979 {
2980 struct device *dev = &hdev->pdev->dev;
2981 __le32 *desc_data;
2982 u32 status;
2983 int ret;
2984
2985 /* query all PF MSIx errors */
2986 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
2987 true);
2988 ret = hclge_cmd_send(&hdev->hw, &desc[0], pf_bd_num);
2989 if (ret) {
2990 dev_err(dev, "query all pf msix int cmd failed (%d)\n", ret);
2991 return ret;
2992 }
2993
2994 /* log SSU PF errors */
2995 status = le32_to_cpu(desc[0].data[0]) & HCLGE_SSU_PORT_INT_MSIX_MASK;
2996 if (status)
2997 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT",
2998 &hclge_ssu_port_based_pf_int[0],
2999 status, reset_requests);
3000
3001 /* read and log PPP PF errors */
3002 desc_data = (__le32 *)&desc[2];
3003 status = le32_to_cpu(*desc_data);
3004 if (status)
3005 hclge_log_error(dev, "PPP_PF_ABNORMAL_INT_ST0",
3006 &hclge_ppp_pf_abnormal_int[0],
3007 status, reset_requests);
3008
3009 /* log PPU(RCB) PF errors */
3010 desc_data = (__le32 *)&desc[3];
3011 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_MSIX_MASK;
3012 if (status)
3013 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST",
3014 &hclge_ppu_pf_abnormal_int[0],
3015 status, reset_requests);
3016
3017 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_OVER_8BD_ERR_MASK;
3018 if (status)
3019 hclge_handle_over_8bd_err(hdev, reset_requests);
3020
3021 /* clear all PF MSIx errors */
3022 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num);
3023 if (ret)
3024 dev_err(dev, "clear all pf msix int cmd failed (%d)\n", ret);
3025
3026 return ret;
3027 }
3028
hclge_handle_all_hw_msix_error(struct hclge_dev * hdev,unsigned long * reset_requests)3029 static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev,
3030 unsigned long *reset_requests)
3031 {
3032 u32 mpf_bd_num, pf_bd_num, bd_num;
3033 struct hclge_desc *desc;
3034 int ret;
3035
3036 /* query the number of bds for the MSIx int status */
3037 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num);
3038 if (ret)
3039 goto out;
3040
3041 bd_num = max_t(u32, mpf_bd_num, pf_bd_num);
3042 desc = kzalloc_objs(struct hclge_desc, bd_num);
3043 if (!desc)
3044 return -ENOMEM;
3045
3046 ret = hclge_handle_mpf_msix_error(hdev, desc, mpf_bd_num,
3047 reset_requests);
3048 if (ret)
3049 goto msi_error;
3050
3051 memset(desc, 0, bd_num * sizeof(struct hclge_desc));
3052 ret = hclge_handle_pf_msix_error(hdev, desc, pf_bd_num, reset_requests);
3053 if (ret)
3054 goto msi_error;
3055
3056 ret = hclge_handle_mac_tnl(hdev);
3057
3058 msi_error:
3059 kfree(desc);
3060 out:
3061 return ret;
3062 }
3063
hclge_handle_hw_msix_error(struct hclge_dev * hdev,unsigned long * reset_requests)3064 int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
3065 unsigned long *reset_requests)
3066 {
3067 struct device *dev = &hdev->pdev->dev;
3068
3069 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) {
3070 dev_err(dev,
3071 "failed to handle msix error during dev init\n");
3072 return -EAGAIN;
3073 }
3074
3075 return hclge_handle_all_hw_msix_error(hdev, reset_requests);
3076 }
3077
hclge_handle_mac_tnl(struct hclge_dev * hdev)3078 int hclge_handle_mac_tnl(struct hclge_dev *hdev)
3079 {
3080 struct hclge_mac_tnl_stats mac_tnl_stats;
3081 struct device *dev = &hdev->pdev->dev;
3082 struct hclge_desc desc;
3083 u32 status;
3084 int ret;
3085
3086 /* query and clear mac tnl interruptions */
3087 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_TNL_INT, true);
3088 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3089 if (ret) {
3090 dev_err(dev, "failed to query mac tnl int, ret = %d.\n", ret);
3091 return ret;
3092 }
3093
3094 status = le32_to_cpu(desc.data[0]);
3095 if (status) {
3096 /* When mac tnl interrupt occurs, we record current time and
3097 * register status here in a fifo, then clear the status. So
3098 * that if link status changes suddenly at some time, we can
3099 * query them by debugfs.
3100 */
3101 mac_tnl_stats.time = local_clock();
3102 mac_tnl_stats.status = status;
3103 kfifo_put(&hdev->mac_tnl_log, mac_tnl_stats);
3104 ret = hclge_clear_mac_tnl_int(hdev);
3105 if (ret)
3106 dev_err(dev, "failed to clear mac tnl int, ret = %d.\n",
3107 ret);
3108 }
3109
3110 return ret;
3111 }
3112
hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev * ae_dev)3113 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
3114 {
3115 struct hclge_dev *hdev = ae_dev->priv;
3116 struct device *dev = &hdev->pdev->dev;
3117 u32 mpf_bd_num, pf_bd_num, bd_num;
3118 struct hclge_desc *desc;
3119 u32 status;
3120 int ret;
3121
3122 ae_dev->hw_err_reset_req = 0;
3123 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
3124
3125 /* query the number of bds for the MSIx int status */
3126 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num);
3127 if (ret)
3128 return;
3129
3130 bd_num = max_t(u32, mpf_bd_num, pf_bd_num);
3131 desc = kzalloc_objs(struct hclge_desc, bd_num);
3132 if (!desc)
3133 return;
3134
3135 /* Clear HNS hw errors reported through msix */
3136 memset(&desc[0].data[0], 0xFF, mpf_bd_num * sizeof(struct hclge_desc) -
3137 HCLGE_DESC_NO_DATA_LEN);
3138 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num);
3139 if (ret) {
3140 dev_err(dev, "fail(%d) to clear mpf msix int during init\n",
3141 ret);
3142 goto msi_error;
3143 }
3144
3145 memset(&desc[0].data[0], 0xFF, pf_bd_num * sizeof(struct hclge_desc) -
3146 HCLGE_DESC_NO_DATA_LEN);
3147 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num);
3148 if (ret) {
3149 dev_err(dev, "fail(%d) to clear pf msix int during init\n",
3150 ret);
3151 goto msi_error;
3152 }
3153
3154 /* Handle Non-fatal HNS RAS errors */
3155 if (status & HCLGE_RAS_REG_NFE_MASK) {
3156 dev_err(dev, "HNS hw error(RAS) identified during init\n");
3157 hclge_handle_all_ras_errors(hdev);
3158 }
3159
3160 msi_error:
3161 kfree(desc);
3162 }
3163
hclge_find_error_source(struct hclge_dev * hdev)3164 bool hclge_find_error_source(struct hclge_dev *hdev)
3165 {
3166 u32 msix_src_flag, hw_err_src_flag;
3167
3168 msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
3169 HCLGE_VECTOR0_REG_MSIX_MASK;
3170
3171 hw_err_src_flag = hclge_read_dev(&hdev->hw,
3172 HCLGE_RAS_PF_OTHER_INT_STS_REG) &
3173 HCLGE_RAS_REG_ERR_MASK;
3174
3175 return msix_src_flag || hw_err_src_flag;
3176 }
3177
hclge_handle_occurred_error(struct hclge_dev * hdev)3178 void hclge_handle_occurred_error(struct hclge_dev *hdev)
3179 {
3180 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3181
3182 if (hclge_find_error_source(hdev))
3183 hclge_handle_error_info_log(ae_dev);
3184 }
3185
3186 static bool
hclge_handle_error_type_reg_log(struct hclge_dev * hdev,struct hclge_mod_err_info * mod_info,struct hclge_type_reg_err_info * type_reg_info)3187 hclge_handle_error_type_reg_log(struct hclge_dev *hdev,
3188 struct hclge_mod_err_info *mod_info,
3189 struct hclge_type_reg_err_info *type_reg_info)
3190 {
3191 #define HCLGE_ERR_TYPE_MASK 0x7F
3192 #define HCLGE_ERR_TYPE_IS_RAS_OFFSET 7
3193
3194 u8 mod_id, total_module, type_id, total_type, i, is_ras;
3195 struct device *dev = &hdev->pdev->dev;
3196 u8 index_module = MODULE_NONE;
3197 u8 index_type = NONE_ERROR;
3198 bool cause_by_vf = false;
3199
3200 mod_id = mod_info->mod_id;
3201 type_id = type_reg_info->type_id & HCLGE_ERR_TYPE_MASK;
3202 is_ras = type_reg_info->type_id >> HCLGE_ERR_TYPE_IS_RAS_OFFSET;
3203
3204 total_module = ARRAY_SIZE(hclge_hw_module_id_st);
3205 total_type = ARRAY_SIZE(hclge_hw_type_id_st);
3206
3207 for (i = 0; i < total_module; i++) {
3208 if (mod_id == hclge_hw_module_id_st[i].module_id) {
3209 index_module = i;
3210 break;
3211 }
3212 }
3213
3214 for (i = 0; i < total_type; i++) {
3215 if (type_id == hclge_hw_type_id_st[i].type_id) {
3216 index_type = i;
3217 cause_by_vf = hclge_hw_type_id_st[i].cause_by_vf;
3218 break;
3219 }
3220 }
3221
3222 if (index_module != MODULE_NONE && index_type != NONE_ERROR)
3223 dev_err(dev,
3224 "found %s %s, is %s error.\n",
3225 hclge_hw_module_id_st[index_module].msg,
3226 hclge_hw_type_id_st[index_type].msg,
3227 is_ras ? "ras" : "msix");
3228 else
3229 dev_err(dev,
3230 "unknown module[%u] or type[%u].\n", mod_id, type_id);
3231
3232 dev_err(dev, "reg_value:\n");
3233 for (i = 0; i < type_reg_info->reg_num; i++)
3234 dev_err(dev, "0x%08x\n", type_reg_info->hclge_reg[i]);
3235
3236 if (hclge_hw_module_id_st[index_module].query_reg_info)
3237 hclge_hw_module_id_st[index_module].query_reg_info(hdev);
3238
3239 return cause_by_vf;
3240 }
3241
hclge_handle_error_module_log(struct hnae3_ae_dev * ae_dev,const u32 * buf,u32 buf_size)3242 static void hclge_handle_error_module_log(struct hnae3_ae_dev *ae_dev,
3243 const u32 *buf, u32 buf_size)
3244 {
3245 struct hclge_type_reg_err_info *type_reg_info;
3246 struct hclge_dev *hdev = ae_dev->priv;
3247 struct device *dev = &hdev->pdev->dev;
3248 struct hclge_mod_err_info *mod_info;
3249 struct hclge_sum_err_info *sum_info;
3250 bool cause_by_vf = false;
3251 u8 mod_num, err_num, i;
3252 u32 offset = 0;
3253
3254 sum_info = (struct hclge_sum_err_info *)&buf[offset++];
3255 if (sum_info->reset_type &&
3256 sum_info->reset_type != HNAE3_NONE_RESET)
3257 set_bit(sum_info->reset_type, &ae_dev->hw_err_reset_req);
3258 mod_num = sum_info->mod_num;
3259
3260 while (mod_num--) {
3261 if (offset >= buf_size) {
3262 dev_err(dev, "The offset(%u) exceeds buf's size(%u).\n",
3263 offset, buf_size);
3264 return;
3265 }
3266 mod_info = (struct hclge_mod_err_info *)&buf[offset++];
3267 err_num = mod_info->err_num;
3268
3269 for (i = 0; i < err_num; i++) {
3270 if (offset >= buf_size) {
3271 dev_err(dev,
3272 "The offset(%u) exceeds buf size(%u).\n",
3273 offset, buf_size);
3274 return;
3275 }
3276
3277 type_reg_info = (struct hclge_type_reg_err_info *)
3278 &buf[offset++];
3279 if (hclge_handle_error_type_reg_log(hdev, mod_info,
3280 type_reg_info))
3281 cause_by_vf = true;
3282
3283 offset += type_reg_info->reg_num;
3284 }
3285 }
3286
3287 if (hnae3_ae_dev_vf_fault_supported(hdev->ae_dev) && cause_by_vf)
3288 set_bit(HNAE3_VF_EXP_RESET, &ae_dev->hw_err_reset_req);
3289 }
3290
hclge_query_all_err_bd_num(struct hclge_dev * hdev,u32 * bd_num)3291 static int hclge_query_all_err_bd_num(struct hclge_dev *hdev, u32 *bd_num)
3292 {
3293 struct device *dev = &hdev->pdev->dev;
3294 struct hclge_desc desc_bd;
3295 int ret;
3296
3297 hclge_cmd_setup_basic_desc(&desc_bd, HCLGE_QUERY_ALL_ERR_BD_NUM, true);
3298 ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1);
3299 if (ret) {
3300 dev_err(dev, "failed to query error bd_num, ret = %d.\n", ret);
3301 return ret;
3302 }
3303
3304 *bd_num = le32_to_cpu(desc_bd.data[0]);
3305 if (!(*bd_num)) {
3306 dev_err(dev, "The value of bd_num is 0!\n");
3307 return -EINVAL;
3308 }
3309
3310 return 0;
3311 }
3312
hclge_query_all_err_info(struct hclge_dev * hdev,struct hclge_desc * desc,u32 bd_num)3313 static int hclge_query_all_err_info(struct hclge_dev *hdev,
3314 struct hclge_desc *desc, u32 bd_num)
3315 {
3316 struct device *dev = &hdev->pdev->dev;
3317 int ret;
3318
3319 hclge_cmd_setup_basic_desc(desc, HCLGE_QUERY_ALL_ERR_INFO, true);
3320 ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
3321 if (ret)
3322 dev_err(dev, "failed to query error info, ret = %d.\n", ret);
3323
3324 return ret;
3325 }
3326
hclge_handle_error_info_log(struct hnae3_ae_dev * ae_dev)3327 int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev)
3328 {
3329 u32 bd_num, desc_len, buf_len, buf_size, i;
3330 struct hclge_dev *hdev = ae_dev->priv;
3331 struct hclge_desc *desc;
3332 __le32 *desc_data;
3333 u32 *buf;
3334 int ret;
3335
3336 ret = hclge_query_all_err_bd_num(hdev, &bd_num);
3337 if (ret)
3338 goto out;
3339
3340 desc_len = bd_num * sizeof(struct hclge_desc);
3341 desc = kzalloc(desc_len, GFP_KERNEL);
3342 if (!desc) {
3343 ret = -ENOMEM;
3344 goto out;
3345 }
3346
3347 ret = hclge_query_all_err_info(hdev, desc, bd_num);
3348 if (ret)
3349 goto err_desc;
3350
3351 buf_len = bd_num * sizeof(struct hclge_desc) - HCLGE_DESC_NO_DATA_LEN;
3352 buf_size = buf_len / sizeof(u32);
3353
3354 desc_data = kzalloc(buf_len, GFP_KERNEL);
3355 if (!desc_data) {
3356 ret = -ENOMEM;
3357 goto err_desc;
3358 }
3359
3360 buf = kzalloc(buf_len, GFP_KERNEL);
3361 if (!buf) {
3362 ret = -ENOMEM;
3363 goto err_buf_alloc;
3364 }
3365
3366 memcpy(desc_data, &desc[0].data[0], buf_len);
3367 for (i = 0; i < buf_size; i++)
3368 buf[i] = le32_to_cpu(desc_data[i]);
3369
3370 hclge_handle_error_module_log(ae_dev, buf, buf_size);
3371 kfree(buf);
3372
3373 err_buf_alloc:
3374 kfree(desc_data);
3375 err_desc:
3376 kfree(desc);
3377 out:
3378 return ret;
3379 }
3380
hclge_reset_vf_in_bitmap(struct hclge_dev * hdev,unsigned long * bitmap)3381 static bool hclge_reset_vf_in_bitmap(struct hclge_dev *hdev,
3382 unsigned long *bitmap)
3383 {
3384 struct hclge_vport *vport;
3385 bool exist_set = false;
3386 int func_id;
3387 int ret;
3388
3389 func_id = find_first_bit(bitmap, HCLGE_VPORT_NUM);
3390 if (func_id == PF_VPORT_ID)
3391 return false;
3392
3393 while (func_id != HCLGE_VPORT_NUM) {
3394 vport = hclge_get_vf_vport(hdev,
3395 func_id - HCLGE_VF_VPORT_START_NUM);
3396 if (!vport) {
3397 dev_err(&hdev->pdev->dev, "invalid func id(%d)\n",
3398 func_id);
3399 return false;
3400 }
3401
3402 dev_info(&hdev->pdev->dev, "do function %d recovery.", func_id);
3403
3404 ret = hclge_reset_tqp(&vport->nic);
3405 if (ret) {
3406 dev_err(&hdev->pdev->dev,
3407 "failed to reset tqp, ret = %d.", ret);
3408 return false;
3409 }
3410
3411 ret = hclge_inform_vf_reset(vport, HNAE3_VF_FUNC_RESET);
3412 if (ret) {
3413 dev_err(&hdev->pdev->dev,
3414 "failed to reset func %d, ret = %d.",
3415 func_id, ret);
3416 return false;
3417 }
3418
3419 exist_set = true;
3420 clear_bit(func_id, bitmap);
3421 func_id = find_first_bit(bitmap, HCLGE_VPORT_NUM);
3422 }
3423
3424 return exist_set;
3425 }
3426
hclge_get_vf_fault_bitmap(struct hclge_desc * desc,unsigned long * bitmap)3427 static void hclge_get_vf_fault_bitmap(struct hclge_desc *desc,
3428 unsigned long *bitmap)
3429 {
3430 #define HCLGE_FIR_FAULT_BYTES 24
3431 #define HCLGE_SEC_FAULT_BYTES 8
3432
3433 u8 *buff;
3434
3435 BUILD_BUG_ON(HCLGE_FIR_FAULT_BYTES + HCLGE_SEC_FAULT_BYTES !=
3436 BITS_TO_BYTES(HCLGE_VPORT_NUM));
3437
3438 memcpy(bitmap, desc[0].data, HCLGE_FIR_FAULT_BYTES);
3439 buff = (u8 *)bitmap + HCLGE_FIR_FAULT_BYTES;
3440 memcpy(buff, desc[1].data, HCLGE_SEC_FAULT_BYTES);
3441 }
3442
hclge_handle_vf_queue_err_ras(struct hclge_dev * hdev)3443 int hclge_handle_vf_queue_err_ras(struct hclge_dev *hdev)
3444 {
3445 unsigned long vf_fault_bitmap[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
3446 struct hclge_desc desc[2];
3447 bool cause_by_vf = false;
3448 int ret;
3449
3450 if (!test_and_clear_bit(HNAE3_VF_EXP_RESET,
3451 &hdev->ae_dev->hw_err_reset_req) ||
3452 !hnae3_ae_dev_vf_fault_supported(hdev->ae_dev))
3453 return 0;
3454
3455 hclge_comm_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_GET_QUEUE_ERR_VF,
3456 true);
3457 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3458 hclge_comm_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_GET_QUEUE_ERR_VF,
3459 true);
3460
3461 ret = hclge_comm_cmd_send(&hdev->hw.hw, desc, 2);
3462 if (ret) {
3463 dev_err(&hdev->pdev->dev,
3464 "failed to get vf bitmap, ret = %d.\n", ret);
3465 return ret;
3466 }
3467 hclge_get_vf_fault_bitmap(desc, vf_fault_bitmap);
3468
3469 cause_by_vf = hclge_reset_vf_in_bitmap(hdev, vf_fault_bitmap);
3470 if (cause_by_vf)
3471 hdev->ae_dev->hw_err_reset_req = 0;
3472
3473 return 0;
3474 }
3475