1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 28 #include "core_types.h" 29 #include "link_encoder.h" 30 #include "dce_link_encoder.h" 31 #include "stream_encoder.h" 32 #include "dc_bios_types.h" 33 34 #include "gpio_service_interface.h" 35 36 #include "dce/dce_11_0_d.h" 37 #include "dce/dce_11_0_sh_mask.h" 38 #include "dce/dce_11_0_enum.h" 39 40 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 41 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa 42 #endif 43 44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L 46 #endif 47 48 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 49 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L 50 #endif 51 52 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 53 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c 54 #endif 55 56 #define CTX \ 57 enc110->base.ctx 58 #define DC_LOGGER \ 59 enc110->base.ctx->logger 60 61 #define REG(reg)\ 62 (enc110->link_regs->reg) 63 64 #define AUX_REG(reg)\ 65 (enc110->aux_regs->reg) 66 67 #define HPD_REG(reg)\ 68 (enc110->hpd_regs->reg) 69 70 #define DEFAULT_AUX_MAX_DATA_SIZE 16 71 #define AUX_MAX_DEFER_WRITE_RETRY 20 72 /* 73 * @brief 74 * Trigger Source Select 75 * ASIC-dependent, actual values for register programming 76 */ 77 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0 78 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1 79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2 80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4 81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08 82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10 83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 85 86 enum { 87 DP_MST_UPDATE_MAX_RETRY = 50 88 }; 89 90 #define DIG_REG(reg)\ 91 (reg + enc110->offsets.dig) 92 93 #define DP_REG(reg)\ 94 (reg + enc110->offsets.dp) 95 96 static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 97 .validate_output_with_stream = 98 dce110_link_encoder_validate_output_with_stream, 99 .hw_init = dce110_link_encoder_hw_init, 100 .setup = dce110_link_encoder_setup, 101 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 102 .enable_dp_output = dce110_link_encoder_enable_dp_output, 103 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 104 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 105 .enable_analog_output = dce110_link_encoder_enable_analog_output, 106 .disable_output = dce110_link_encoder_disable_output, 107 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 108 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 109 .update_mst_stream_allocation_table = 110 dce110_link_encoder_update_mst_stream_allocation_table, 111 .psr_program_dp_dphy_fast_training = 112 dce110_psr_program_dp_dphy_fast_training, 113 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 114 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 115 .enable_hpd = dce110_link_encoder_enable_hpd, 116 .disable_hpd = dce110_link_encoder_disable_hpd, 117 .is_dig_enabled = dce110_is_dig_enabled, 118 .destroy = dce110_link_encoder_destroy, 119 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 120 .get_dig_frontend = dce110_get_dig_frontend, 121 .get_hpd_state = dce110_get_hpd_state, 122 .program_hpd_filter = dce110_program_hpd_filter, 123 }; 124 125 static const struct link_encoder_funcs dce110_lnk_enc_funcs_no_hpd = { 126 .validate_output_with_stream = 127 dce110_link_encoder_validate_output_with_stream, 128 .hw_init = dce110_link_encoder_hw_init, 129 .setup = dce110_link_encoder_setup, 130 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 131 .enable_dp_output = dce110_link_encoder_enable_dp_output, 132 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 133 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 134 .enable_analog_output = dce110_link_encoder_enable_analog_output, 135 .disable_output = dce110_link_encoder_disable_output, 136 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 137 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 138 .update_mst_stream_allocation_table = 139 dce110_link_encoder_update_mst_stream_allocation_table, 140 .psr_program_dp_dphy_fast_training = 141 dce110_psr_program_dp_dphy_fast_training, 142 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 143 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 144 .is_dig_enabled = dce110_is_dig_enabled, 145 .destroy = dce110_link_encoder_destroy, 146 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 147 .get_dig_frontend = dce110_get_dig_frontend, 148 .get_hpd_state = dce110_get_hpd_state, 149 .program_hpd_filter = dce110_program_hpd_filter, 150 }; 151 152 static enum bp_result link_transmitter_control( 153 struct dce110_link_encoder *enc110, 154 struct bp_transmitter_control *cntl) 155 { 156 enum bp_result result; 157 struct dc_bios *bp = enc110->base.ctx->dc_bios; 158 159 result = bp->funcs->transmitter_control(bp, cntl); 160 161 return result; 162 } 163 164 static enum bp_result link_dac_encoder_control( 165 struct dce110_link_encoder *link_enc, 166 enum bp_encoder_control_action action, 167 uint32_t pix_clk_100hz) 168 { 169 struct dc_bios *bios = link_enc->base.ctx->dc_bios; 170 struct bp_encoder_control encoder_control = {0}; 171 172 encoder_control.action = action; 173 encoder_control.engine_id = link_enc->base.analog_engine; 174 encoder_control.pixel_clock = pix_clk_100hz / 10; 175 176 return bios->funcs->encoder_control(bios, &encoder_control); 177 } 178 179 static void enable_phy_bypass_mode( 180 struct dce110_link_encoder *enc110, 181 bool enable) 182 { 183 /* This register resides in DP back end block; 184 * transmitter is used for the offset */ 185 186 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 187 188 } 189 190 static void disable_prbs_symbols( 191 struct dce110_link_encoder *enc110, 192 bool disable) 193 { 194 /* This register resides in DP back end block; 195 * transmitter is used for the offset */ 196 197 REG_UPDATE_4(DP_DPHY_CNTL, 198 DPHY_ATEST_SEL_LANE0, disable, 199 DPHY_ATEST_SEL_LANE1, disable, 200 DPHY_ATEST_SEL_LANE2, disable, 201 DPHY_ATEST_SEL_LANE3, disable); 202 } 203 204 static void disable_prbs_mode( 205 struct dce110_link_encoder *enc110) 206 { 207 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 208 } 209 210 static void program_pattern_symbols( 211 struct dce110_link_encoder *enc110, 212 uint16_t pattern_symbols[8]) 213 { 214 /* This register resides in DP back end block; 215 * transmitter is used for the offset */ 216 217 REG_SET_3(DP_DPHY_SYM0, 0, 218 DPHY_SYM1, pattern_symbols[0], 219 DPHY_SYM2, pattern_symbols[1], 220 DPHY_SYM3, pattern_symbols[2]); 221 222 /* This register resides in DP back end block; 223 * transmitter is used for the offset */ 224 225 REG_SET_3(DP_DPHY_SYM1, 0, 226 DPHY_SYM4, pattern_symbols[3], 227 DPHY_SYM5, pattern_symbols[4], 228 DPHY_SYM6, pattern_symbols[5]); 229 230 /* This register resides in DP back end block; 231 * transmitter is used for the offset */ 232 233 REG_SET_2(DP_DPHY_SYM2, 0, 234 DPHY_SYM7, pattern_symbols[6], 235 DPHY_SYM8, pattern_symbols[7]); 236 } 237 238 static void set_dp_phy_pattern_d102( 239 struct dce110_link_encoder *enc110) 240 { 241 /* Disable PHY Bypass mode to setup the test pattern */ 242 enable_phy_bypass_mode(enc110, false); 243 244 /* For 10-bit PRBS or debug symbols 245 * please use the following sequence: */ 246 247 /* Enable debug symbols on the lanes */ 248 249 disable_prbs_symbols(enc110, true); 250 251 /* Disable PRBS mode */ 252 disable_prbs_mode(enc110); 253 254 /* Program debug symbols to be output */ 255 { 256 uint16_t pattern_symbols[8] = { 257 0x2AA, 0x2AA, 0x2AA, 0x2AA, 258 0x2AA, 0x2AA, 0x2AA, 0x2AA 259 }; 260 261 program_pattern_symbols(enc110, pattern_symbols); 262 } 263 264 /* Enable phy bypass mode to enable the test pattern */ 265 266 enable_phy_bypass_mode(enc110, true); 267 } 268 269 static void set_link_training_complete( 270 struct dce110_link_encoder *enc110, 271 bool complete) 272 { 273 /* This register resides in DP back end block; 274 * transmitter is used for the offset */ 275 276 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 277 278 } 279 280 unsigned int dce110_get_dig_frontend(struct link_encoder *enc) 281 { 282 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 283 u32 value; 284 enum engine_id result; 285 286 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); 287 288 switch (value) { 289 case DCE110_DIG_FE_SOURCE_SELECT_DIGA: 290 result = ENGINE_ID_DIGA; 291 break; 292 case DCE110_DIG_FE_SOURCE_SELECT_DIGB: 293 result = ENGINE_ID_DIGB; 294 break; 295 case DCE110_DIG_FE_SOURCE_SELECT_DIGC: 296 result = ENGINE_ID_DIGC; 297 break; 298 case DCE110_DIG_FE_SOURCE_SELECT_DIGD: 299 result = ENGINE_ID_DIGD; 300 break; 301 case DCE110_DIG_FE_SOURCE_SELECT_DIGE: 302 result = ENGINE_ID_DIGE; 303 break; 304 case DCE110_DIG_FE_SOURCE_SELECT_DIGF: 305 result = ENGINE_ID_DIGF; 306 break; 307 case DCE110_DIG_FE_SOURCE_SELECT_DIGG: 308 result = ENGINE_ID_DIGG; 309 break; 310 default: 311 // invalid source select DIG 312 result = ENGINE_ID_UNKNOWN; 313 } 314 315 return result; 316 } 317 318 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 319 struct link_encoder *enc, 320 uint32_t index) 321 { 322 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 323 /* Write Training Pattern */ 324 325 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 326 327 /* Set HW Register Training Complete to false */ 328 329 set_link_training_complete(enc110, false); 330 331 /* Disable PHY Bypass mode to output Training Pattern */ 332 333 enable_phy_bypass_mode(enc110, false); 334 335 /* Disable PRBS mode */ 336 disable_prbs_mode(enc110); 337 } 338 339 static void setup_panel_mode( 340 struct dce110_link_encoder *enc110, 341 enum dp_panel_mode panel_mode) 342 { 343 uint32_t value; 344 struct dc_context *ctx = enc110->base.ctx; 345 346 /* if psp set panel mode, dal should be program it */ 347 if (ctx->dc->caps.psp_setup_panel_mode) 348 return; 349 350 /* The code below is only applicable to encoders with a digital transmitter. */ 351 if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) 352 return; 353 354 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 355 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 356 357 switch (panel_mode) { 358 case DP_PANEL_MODE_EDP: 359 value = 0x1; 360 break; 361 case DP_PANEL_MODE_SPECIAL: 362 value = 0x11; 363 break; 364 default: 365 value = 0x0; 366 break; 367 } 368 369 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 370 } 371 372 static void set_dp_phy_pattern_symbol_error( 373 struct dce110_link_encoder *enc110) 374 { 375 /* Disable PHY Bypass mode to setup the test pattern */ 376 enable_phy_bypass_mode(enc110, false); 377 378 /* program correct panel mode*/ 379 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 380 381 /* A PRBS23 pattern is used for most DP electrical measurements. */ 382 383 /* Enable PRBS symbols on the lanes */ 384 disable_prbs_symbols(enc110, false); 385 386 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 387 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 388 DPHY_PRBS_SEL, 1, 389 DPHY_PRBS_EN, 1); 390 391 /* Enable phy bypass mode to enable the test pattern */ 392 enable_phy_bypass_mode(enc110, true); 393 } 394 395 static void set_dp_phy_pattern_prbs7( 396 struct dce110_link_encoder *enc110) 397 { 398 /* Disable PHY Bypass mode to setup the test pattern */ 399 enable_phy_bypass_mode(enc110, false); 400 401 /* A PRBS7 pattern is used for most DP electrical measurements. */ 402 403 /* Enable PRBS symbols on the lanes */ 404 disable_prbs_symbols(enc110, false); 405 406 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 407 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 408 DPHY_PRBS_SEL, 0, 409 DPHY_PRBS_EN, 1); 410 411 /* Enable phy bypass mode to enable the test pattern */ 412 enable_phy_bypass_mode(enc110, true); 413 } 414 415 static void set_dp_phy_pattern_80bit_custom( 416 struct dce110_link_encoder *enc110, 417 const uint8_t *pattern) 418 { 419 /* Disable PHY Bypass mode to setup the test pattern */ 420 enable_phy_bypass_mode(enc110, false); 421 422 /* Enable debug symbols on the lanes */ 423 424 disable_prbs_symbols(enc110, true); 425 426 /* Enable PHY bypass mode to enable the test pattern */ 427 /* TODO is it really needed ? */ 428 429 enable_phy_bypass_mode(enc110, true); 430 431 /* Program 80 bit custom pattern */ 432 { 433 uint16_t pattern_symbols[8]; 434 435 pattern_symbols[0] = 436 ((pattern[1] & 0x03) << 8) | pattern[0]; 437 pattern_symbols[1] = 438 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 439 pattern_symbols[2] = 440 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 441 pattern_symbols[3] = 442 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 443 pattern_symbols[4] = 444 ((pattern[6] & 0x03) << 8) | pattern[5]; 445 pattern_symbols[5] = 446 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 447 pattern_symbols[6] = 448 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 449 pattern_symbols[7] = 450 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 451 452 program_pattern_symbols(enc110, pattern_symbols); 453 } 454 455 /* Enable phy bypass mode to enable the test pattern */ 456 457 enable_phy_bypass_mode(enc110, true); 458 } 459 460 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 461 struct dce110_link_encoder *enc110, 462 unsigned int cp2520_pattern) 463 { 464 465 /* previously there is a register DP_HBR2_EYE_PATTERN 466 * that is enabled to get the pattern. 467 * But it does not work with the latest spec change, 468 * so we are programming the following registers manually. 469 * 470 * The following settings have been confirmed 471 * by Nick Chorney and Sandra Liu */ 472 473 /* Disable PHY Bypass mode to setup the test pattern */ 474 475 enable_phy_bypass_mode(enc110, false); 476 477 /* Setup DIG encoder in DP SST mode */ 478 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 479 480 /* ensure normal panel mode. */ 481 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 482 483 /* no vbid after BS (SR) 484 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 485 * 11000260 / 11000104 / 110000FC */ 486 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 487 DP_IDLE_BS_INTERVAL, 0xFC, 488 DP_VBID_DISABLE, 1, 489 DP_VID_ENHANCED_FRAME_MODE, 1); 490 491 /* swap every BS with SR */ 492 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 493 494 /* select cp2520 patterns */ 495 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 496 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 497 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 498 else 499 /* pre-DCE11 can only generate CP2520 pattern 2 */ 500 ASSERT(cp2520_pattern == 2); 501 502 /* set link training complete */ 503 set_link_training_complete(enc110, true); 504 505 /* disable video stream */ 506 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 507 508 /* Disable PHY Bypass mode to setup the test pattern */ 509 enable_phy_bypass_mode(enc110, false); 510 } 511 512 #if defined(CONFIG_DRM_AMD_DC_SI) 513 static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2( 514 struct dce110_link_encoder *enc110, 515 unsigned int cp2520_pattern) 516 { 517 518 /* previously there is a register DP_HBR2_EYE_PATTERN 519 * that is enabled to get the pattern. 520 * But it does not work with the latest spec change, 521 * so we are programming the following registers manually. 522 * 523 * The following settings have been confirmed 524 * by Nick Chorney and Sandra Liu */ 525 526 /* Disable PHY Bypass mode to setup the test pattern */ 527 528 enable_phy_bypass_mode(enc110, false); 529 530 /* Setup DIG encoder in DP SST mode */ 531 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 532 533 /* ensure normal panel mode. */ 534 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 535 536 /* no vbid after BS (SR) 537 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 538 * 11000260 / 11000104 / 110000FC */ 539 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 540 DP_IDLE_BS_INTERVAL, 0xFC, 541 DP_VBID_DISABLE, 1, 542 DP_VID_ENHANCED_FRAME_MODE, 1); 543 544 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */ 545 546 /* select cp2520 patterns */ 547 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 548 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 549 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 550 else 551 /* pre-DCE11 can only generate CP2520 pattern 2 */ 552 ASSERT(cp2520_pattern == 2); 553 554 /* set link training complete */ 555 set_link_training_complete(enc110, true); 556 557 /* disable video stream */ 558 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 559 560 /* Disable PHY Bypass mode to setup the test pattern */ 561 enable_phy_bypass_mode(enc110, false); 562 } 563 #endif 564 565 static void set_dp_phy_pattern_passthrough_mode( 566 struct dce110_link_encoder *enc110, 567 enum dp_panel_mode panel_mode) 568 { 569 /* program correct panel mode */ 570 setup_panel_mode(enc110, panel_mode); 571 572 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 573 * in case we were doing HBR2 compliance pattern before 574 */ 575 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 576 DP_IDLE_BS_INTERVAL, 0x2000, 577 DP_VBID_DISABLE, 0, 578 DP_VID_ENHANCED_FRAME_MODE, 1); 579 580 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 581 582 /* set link training complete */ 583 set_link_training_complete(enc110, true); 584 585 /* Disable PHY Bypass mode to setup the test pattern */ 586 enable_phy_bypass_mode(enc110, false); 587 588 /* Disable PRBS mode */ 589 disable_prbs_mode(enc110); 590 } 591 592 #if defined(CONFIG_DRM_AMD_DC_SI) 593 static void dce60_set_dp_phy_pattern_passthrough_mode( 594 struct dce110_link_encoder *enc110, 595 enum dp_panel_mode panel_mode) 596 { 597 /* program correct panel mode */ 598 setup_panel_mode(enc110, panel_mode); 599 600 /* restore LINK_FRAMING_CNTL 601 * in case we were doing HBR2 compliance pattern before 602 */ 603 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 604 DP_IDLE_BS_INTERVAL, 0x2000, 605 DP_VBID_DISABLE, 0, 606 DP_VID_ENHANCED_FRAME_MODE, 1); 607 608 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip DPHY_SCRAMBLER_BS_COUNT restore */ 609 610 /* set link training complete */ 611 set_link_training_complete(enc110, true); 612 613 /* Disable PHY Bypass mode to setup the test pattern */ 614 enable_phy_bypass_mode(enc110, false); 615 616 /* Disable PRBS mode */ 617 disable_prbs_mode(enc110); 618 } 619 #endif 620 621 /* return value is bit-vector */ 622 static uint8_t get_frontend_source( 623 enum engine_id engine) 624 { 625 switch (engine) { 626 case ENGINE_ID_DIGA: 627 return DCE110_DIG_FE_SOURCE_SELECT_DIGA; 628 case ENGINE_ID_DIGB: 629 return DCE110_DIG_FE_SOURCE_SELECT_DIGB; 630 case ENGINE_ID_DIGC: 631 return DCE110_DIG_FE_SOURCE_SELECT_DIGC; 632 case ENGINE_ID_DIGD: 633 return DCE110_DIG_FE_SOURCE_SELECT_DIGD; 634 case ENGINE_ID_DIGE: 635 return DCE110_DIG_FE_SOURCE_SELECT_DIGE; 636 case ENGINE_ID_DIGF: 637 return DCE110_DIG_FE_SOURCE_SELECT_DIGF; 638 case ENGINE_ID_DIGG: 639 return DCE110_DIG_FE_SOURCE_SELECT_DIGG; 640 default: 641 ASSERT_CRITICAL(false); 642 return DCE110_DIG_FE_SOURCE_SELECT_INVALID; 643 } 644 } 645 646 static void configure_encoder( 647 struct dce110_link_encoder *enc110, 648 const struct dc_link_settings *link_settings) 649 { 650 /* set number of lanes */ 651 652 REG_SET(DP_CONFIG, 0, 653 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 654 655 /* setup scrambler */ 656 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 657 } 658 659 #if defined(CONFIG_DRM_AMD_DC_SI) 660 static void dce60_configure_encoder( 661 struct dce110_link_encoder *enc110, 662 const struct dc_link_settings *link_settings) 663 { 664 /* set number of lanes */ 665 666 REG_SET(DP_CONFIG, 0, 667 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 668 669 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip setup scrambler */ 670 } 671 #endif 672 673 static void aux_initialize( 674 struct dce110_link_encoder *enc110) 675 { 676 struct dc_context *ctx = enc110->base.ctx; 677 enum hpd_source_id hpd_source = enc110->base.hpd_source; 678 uint32_t addr = AUX_REG(AUX_CONTROL); 679 uint32_t value = dm_read_reg(ctx, addr); 680 681 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 682 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 683 dm_write_reg(ctx, addr, value); 684 685 addr = AUX_REG(AUX_DPHY_RX_CONTROL0); 686 value = dm_read_reg(ctx, addr); 687 688 /* 1/4 window (the maximum allowed) */ 689 set_reg_field_value(value, 1, 690 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW); 691 dm_write_reg(ctx, addr, value); 692 693 } 694 695 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 696 bool exit_link_training_required) 697 { 698 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 699 700 if (exit_link_training_required) 701 REG_UPDATE(DP_DPHY_FAST_TRAINING, 702 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 703 else { 704 REG_UPDATE(DP_DPHY_FAST_TRAINING, 705 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 706 /*In DCE 11, we are able to pre-program a Force SR register 707 * to be able to trigger SR symbol after 5 idle patterns 708 * transmitted. Upon PSR Exit, DMCU can trigger 709 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 710 * DPHY_LOAD_BS_COUNT_START and the internal counter 711 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 712 * replaced by SR symbol once. 713 */ 714 715 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 716 } 717 } 718 719 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 720 unsigned int sdp_transmit_line_num_deadline) 721 { 722 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 723 724 REG_UPDATE_2(DP_SEC_CNTL1, 725 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 726 DP_SEC_GSP0_PRIORITY, 1); 727 } 728 729 bool dce110_is_dig_enabled(struct link_encoder *enc) 730 { 731 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 732 uint32_t value; 733 734 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 735 return value; 736 } 737 738 static void link_encoder_disable(struct dce110_link_encoder *enc110) 739 { 740 /* reset training pattern */ 741 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 742 DPHY_TRAINING_PATTERN_SEL, 0); 743 744 /* reset training complete */ 745 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 746 747 /* reset panel mode */ 748 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 749 } 750 751 static void hpd_initialize( 752 struct dce110_link_encoder *enc110) 753 { 754 /* Associate HPD with DIG_BE */ 755 enum hpd_source_id hpd_source = enc110->base.hpd_source; 756 757 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 758 } 759 760 bool dce110_link_encoder_validate_dvi_output( 761 const struct dce110_link_encoder *enc110, 762 enum signal_type connector_signal, 763 enum signal_type signal, 764 const struct dc_crtc_timing *crtc_timing) 765 { 766 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 767 768 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 769 max_pixel_clock *= 2; 770 771 /* This handles the case of HDMI downgrade to DVI we don't want to 772 * we don't want to cap the pixel clock if the DDI is not DVI. 773 */ 774 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 775 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 776 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; 777 778 /* DVI only support RGB pixel encoding */ 779 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 780 return false; 781 782 /*connect DVI via adpater's HDMI connector*/ 783 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 784 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 785 signal != SIGNAL_TYPE_HDMI_TYPE_A && 786 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) 787 return false; 788 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 789 return false; 790 791 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) 792 return false; 793 794 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 795 switch (crtc_timing->display_color_depth) { 796 case COLOR_DEPTH_666: 797 case COLOR_DEPTH_888: 798 break; 799 case COLOR_DEPTH_101010: 800 case COLOR_DEPTH_161616: 801 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 802 return false; 803 break; 804 default: 805 return false; 806 } 807 808 return true; 809 } 810 811 static bool dce110_link_encoder_validate_hdmi_output( 812 const struct dce110_link_encoder *enc110, 813 const struct dc_crtc_timing *crtc_timing, 814 int adjusted_pix_clk_khz) 815 { 816 enum dc_color_depth max_deep_color = 817 enc110->base.features.max_hdmi_deep_color; 818 819 if (max_deep_color < crtc_timing->display_color_depth) 820 return false; 821 822 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 823 return false; 824 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 825 return false; 826 827 if ((adjusted_pix_clk_khz == 0) || 828 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) 829 return false; 830 831 /* DCE11 HW does not support 420 */ 832 if (!enc110->base.features.hdmi_ycbcr420_supported && 833 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 834 return false; 835 836 if ((!enc110->base.features.flags.bits.HDMI_6GB_EN || 837 enc110->base.ctx->dc->debug.hdmi20_disable) && 838 adjusted_pix_clk_khz >= 300000) 839 return false; 840 if (enc110->base.ctx->dc->debug.hdmi20_disable && 841 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 842 return false; 843 return true; 844 } 845 846 bool dce110_link_encoder_validate_dp_output( 847 const struct dce110_link_encoder *enc110, 848 const struct dc_crtc_timing *crtc_timing) 849 { 850 (void)enc110; 851 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 852 return false; 853 854 return true; 855 } 856 857 static bool dce110_link_encoder_validate_rgb_output( 858 const struct dce110_link_encoder *enc110, 859 const struct dc_crtc_timing *crtc_timing) 860 { 861 /* When the VBIOS doesn't specify any limits, use 400 MHz. 862 * The value comes from amdgpu_atombios_get_clock_info. 863 */ 864 uint32_t max_pixel_clock_khz = 400000; 865 866 if (enc110->base.ctx->dc_bios->fw_info_valid && 867 enc110->base.ctx->dc_bios->fw_info.max_pixel_clock) { 868 max_pixel_clock_khz = 869 enc110->base.ctx->dc_bios->fw_info.max_pixel_clock; 870 } 871 872 if (crtc_timing->pix_clk_100hz > max_pixel_clock_khz * 10) 873 return false; 874 875 if (crtc_timing->display_color_depth != COLOR_DEPTH_888) 876 return false; 877 878 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 879 return false; 880 881 return true; 882 } 883 884 void dce110_link_encoder_construct( 885 struct dce110_link_encoder *enc110, 886 const struct encoder_init_data *init_data, 887 const struct encoder_feature_support *enc_features, 888 const struct dce110_link_enc_registers *link_regs, 889 const struct dce110_link_enc_aux_registers *aux_regs, 890 const struct dce110_link_enc_hpd_registers *hpd_regs) 891 { 892 struct bp_encoder_cap_info bp_cap_info = {0}; 893 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 894 enum bp_result result = BP_RESULT_OK; 895 896 if (hpd_regs) 897 enc110->base.funcs = &dce110_lnk_enc_funcs; 898 else 899 enc110->base.funcs = &dce110_lnk_enc_funcs_no_hpd; 900 enc110->base.ctx = init_data->ctx; 901 enc110->base.id = init_data->encoder; 902 enc110->base.analog_id = init_data->analog_encoder; 903 904 enc110->base.hpd_gpio = init_data->hpd_gpio; 905 enc110->base.hpd_source = init_data->hpd_source; 906 enc110->base.connector = init_data->connector; 907 908 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 909 enc110->base.analog_engine = init_data->analog_engine; 910 911 enc110->base.features = *enc_features; 912 913 enc110->base.transmitter = init_data->transmitter; 914 915 /* set the flag to indicate whether driver poll the I2C data pin 916 * while doing the DP sink detect 917 */ 918 919 /* if (dal_adapter_service_is_feature_supported(as, 920 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 921 enc110->base.features.flags.bits. 922 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 923 924 enc110->base.output_signals = 925 SIGNAL_TYPE_DVI_SINGLE_LINK | 926 SIGNAL_TYPE_DVI_DUAL_LINK | 927 SIGNAL_TYPE_LVDS | 928 SIGNAL_TYPE_DISPLAY_PORT | 929 SIGNAL_TYPE_DISPLAY_PORT_MST | 930 SIGNAL_TYPE_EDP | 931 SIGNAL_TYPE_HDMI_TYPE_A; 932 933 if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || 934 enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 935 enc110->base.analog_engine != ENGINE_ID_UNKNOWN) 936 enc110->base.output_signals |= SIGNAL_TYPE_RGB; 937 938 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 939 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 940 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 941 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 942 * Prefer DIG assignment is decided by board design. 943 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 944 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 945 * By this, adding DIGG should not hurt DCE 8.0. 946 * This will let DCE 8.1 share DCE 8.0 as much as possible 947 */ 948 949 enc110->link_regs = link_regs; 950 enc110->aux_regs = aux_regs; 951 enc110->hpd_regs = hpd_regs; 952 953 switch (enc110->base.transmitter) { 954 case TRANSMITTER_UNIPHY_A: 955 enc110->base.preferred_engine = ENGINE_ID_DIGA; 956 break; 957 case TRANSMITTER_UNIPHY_B: 958 enc110->base.preferred_engine = ENGINE_ID_DIGB; 959 break; 960 case TRANSMITTER_UNIPHY_C: 961 enc110->base.preferred_engine = ENGINE_ID_DIGC; 962 break; 963 case TRANSMITTER_UNIPHY_D: 964 enc110->base.preferred_engine = ENGINE_ID_DIGD; 965 break; 966 case TRANSMITTER_UNIPHY_E: 967 enc110->base.preferred_engine = ENGINE_ID_DIGE; 968 break; 969 case TRANSMITTER_UNIPHY_F: 970 enc110->base.preferred_engine = ENGINE_ID_DIGF; 971 break; 972 case TRANSMITTER_UNIPHY_G: 973 enc110->base.preferred_engine = ENGINE_ID_DIGG; 974 break; 975 default: 976 if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { 977 /* The connector is analog-only, ie. VGA */ 978 enc110->base.preferred_engine = init_data->analog_engine; 979 enc110->base.output_signals = SIGNAL_TYPE_RGB; 980 enc110->base.transmitter = TRANSMITTER_UNKNOWN; 981 break; 982 } 983 ASSERT_CRITICAL(false); 984 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 985 } 986 987 /* default to one to mirror Windows behavior */ 988 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 989 990 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 991 enc110->base.id, &bp_cap_info); 992 993 /* Override features with DCE-specific values */ 994 if (result == BP_RESULT_OK) { 995 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 996 bp_cap_info.DP_HBR2_EN; 997 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 998 bp_cap_info.DP_HBR3_EN; 999 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 1000 } else if (result != BP_RESULT_NORECORD) { 1001 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 1002 __func__, 1003 result); 1004 } 1005 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 1006 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 1007 } 1008 } 1009 1010 bool dce110_link_encoder_validate_output_with_stream( 1011 struct link_encoder *enc, 1012 const struct dc_stream_state *stream) 1013 { 1014 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1015 bool is_valid; 1016 1017 switch (stream->signal) { 1018 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1019 case SIGNAL_TYPE_DVI_DUAL_LINK: 1020 is_valid = dce110_link_encoder_validate_dvi_output( 1021 enc110, 1022 stream->link->connector_signal, 1023 stream->signal, 1024 &stream->timing); 1025 break; 1026 case SIGNAL_TYPE_HDMI_TYPE_A: 1027 is_valid = dce110_link_encoder_validate_hdmi_output( 1028 enc110, 1029 &stream->timing, 1030 stream->phy_pix_clk); 1031 break; 1032 case SIGNAL_TYPE_DISPLAY_PORT: 1033 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1034 is_valid = dce110_link_encoder_validate_dp_output( 1035 enc110, &stream->timing); 1036 break; 1037 case SIGNAL_TYPE_RGB: 1038 is_valid = dce110_link_encoder_validate_rgb_output( 1039 enc110, &stream->timing); 1040 break; 1041 case SIGNAL_TYPE_EDP: 1042 case SIGNAL_TYPE_LVDS: 1043 is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB; 1044 break; 1045 case SIGNAL_TYPE_VIRTUAL: 1046 is_valid = true; 1047 break; 1048 default: 1049 is_valid = false; 1050 break; 1051 } 1052 1053 return is_valid; 1054 } 1055 1056 void dce110_link_encoder_hw_init( 1057 struct link_encoder *enc) 1058 { 1059 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1060 struct bp_transmitter_control cntl = { 0 }; 1061 enum bp_result result; 1062 1063 cntl.action = TRANSMITTER_CONTROL_INIT; 1064 cntl.engine_id = ENGINE_ID_UNKNOWN; 1065 cntl.transmitter = enc110->base.transmitter; 1066 cntl.connector_obj_id = enc110->base.connector; 1067 cntl.lanes_number = LANE_COUNT_FOUR; 1068 cntl.coherent = false; 1069 cntl.hpd_sel = enc110->base.hpd_source; 1070 1071 if (enc110->base.analog_engine != ENGINE_ID_UNKNOWN) { 1072 result = link_dac_encoder_control(enc110, ENCODER_CONTROL_INIT, 0); 1073 if (result != BP_RESULT_OK) { 1074 DC_LOG_ERROR("%s: Failed to execute VBIOS command table for DAC!\n", 1075 __func__); 1076 BREAK_TO_DEBUGGER(); 1077 return; 1078 } 1079 } 1080 1081 /* The code below is only applicable to encoders with a digital transmitter. */ 1082 if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) 1083 return; 1084 1085 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 1086 cntl.signal = SIGNAL_TYPE_EDP; 1087 1088 result = link_transmitter_control(enc110, &cntl); 1089 1090 if (result != BP_RESULT_OK) { 1091 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1092 __func__); 1093 BREAK_TO_DEBUGGER(); 1094 return; 1095 } 1096 1097 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { 1098 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 1099 1100 result = link_transmitter_control(enc110, &cntl); 1101 1102 ASSERT(result == BP_RESULT_OK); 1103 1104 } 1105 aux_initialize(enc110); 1106 1107 /* reinitialize HPD. 1108 * hpd_initialize() will pass DIG_FE id to HW context. 1109 * All other routine within HW context will use fe_engine_offset 1110 * as DIG_FE id even caller pass DIG_FE id. 1111 * So this routine must be called first. */ 1112 hpd_initialize(enc110); 1113 } 1114 1115 void dce110_link_encoder_destroy(struct link_encoder **enc) 1116 { 1117 if ((*enc)->hpd_gpio) { 1118 dal_gpio_destroy_irq(&(*enc)->hpd_gpio); 1119 (*enc)->hpd_gpio = NULL; 1120 } 1121 1122 kfree(TO_DCE110_LINK_ENC(*enc)); 1123 *enc = NULL; 1124 } 1125 1126 void dce110_link_encoder_setup( 1127 struct link_encoder *enc, 1128 enum signal_type signal) 1129 { 1130 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1131 1132 switch (signal) { 1133 case SIGNAL_TYPE_EDP: 1134 case SIGNAL_TYPE_DISPLAY_PORT: 1135 /* DP SST */ 1136 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 1137 break; 1138 case SIGNAL_TYPE_LVDS: 1139 /* LVDS */ 1140 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 1141 break; 1142 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1143 case SIGNAL_TYPE_DVI_DUAL_LINK: 1144 /* TMDS-DVI */ 1145 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 1146 break; 1147 case SIGNAL_TYPE_HDMI_TYPE_A: 1148 /* TMDS-HDMI */ 1149 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 1150 break; 1151 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1152 /* DP MST */ 1153 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 1154 break; 1155 case SIGNAL_TYPE_RGB: 1156 break; 1157 default: 1158 ASSERT_CRITICAL(false); 1159 /* invalid mode ! */ 1160 break; 1161 } 1162 1163 } 1164 1165 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1166 void dce110_link_encoder_enable_tmds_output( 1167 struct link_encoder *enc, 1168 enum clock_source_id clock_source, 1169 enum dc_color_depth color_depth, 1170 enum signal_type signal, 1171 uint32_t pixel_clock) 1172 { 1173 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1174 struct bp_transmitter_control cntl = { 0 }; 1175 enum bp_result result; 1176 1177 /* Enable the PHY */ 1178 cntl.connector_obj_id = enc110->base.connector; 1179 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1180 cntl.engine_id = enc->preferred_engine; 1181 cntl.transmitter = enc110->base.transmitter; 1182 cntl.pll_id = clock_source; 1183 cntl.signal = signal; 1184 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) 1185 cntl.lanes_number = 8; 1186 else 1187 cntl.lanes_number = 4; 1188 1189 cntl.hpd_sel = enc110->base.hpd_source; 1190 1191 cntl.pixel_clock = pixel_clock; 1192 cntl.color_depth = color_depth; 1193 1194 result = link_transmitter_control(enc110, &cntl); 1195 1196 if (result != BP_RESULT_OK) { 1197 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1198 __func__); 1199 BREAK_TO_DEBUGGER(); 1200 } 1201 } 1202 1203 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1204 void dce110_link_encoder_enable_lvds_output( 1205 struct link_encoder *enc, 1206 enum clock_source_id clock_source, 1207 uint32_t pixel_clock) 1208 { 1209 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1210 struct bp_transmitter_control cntl = { 0 }; 1211 enum bp_result result; 1212 1213 /* Enable the PHY */ 1214 cntl.connector_obj_id = enc110->base.connector; 1215 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1216 cntl.engine_id = enc->preferred_engine; 1217 cntl.transmitter = enc110->base.transmitter; 1218 cntl.pll_id = clock_source; 1219 cntl.signal = SIGNAL_TYPE_LVDS; 1220 cntl.lanes_number = 4; 1221 1222 cntl.hpd_sel = enc110->base.hpd_source; 1223 1224 cntl.pixel_clock = pixel_clock; 1225 1226 result = link_transmitter_control(enc110, &cntl); 1227 1228 if (result != BP_RESULT_OK) { 1229 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1230 __func__); 1231 BREAK_TO_DEBUGGER(); 1232 } 1233 } 1234 1235 void dce110_link_encoder_enable_analog_output( 1236 struct link_encoder *enc, 1237 uint32_t pixel_clock) 1238 { 1239 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1240 enum bp_result result; 1241 1242 result = link_dac_encoder_control(enc110, ENCODER_CONTROL_ENABLE, pixel_clock); 1243 1244 if (result != BP_RESULT_OK) { 1245 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1246 __func__); 1247 BREAK_TO_DEBUGGER(); 1248 } 1249 } 1250 1251 /* enables DP PHY output */ 1252 void dce110_link_encoder_enable_dp_output( 1253 struct link_encoder *enc, 1254 const struct dc_link_settings *link_settings, 1255 enum clock_source_id clock_source) 1256 { 1257 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1258 struct bp_transmitter_control cntl = { 0 }; 1259 enum bp_result result; 1260 1261 /* Enable the PHY */ 1262 1263 /* number_of_lanes is used for pixel clock adjust, 1264 * but it's not passed to asic_control. 1265 * We need to set number of lanes manually. 1266 */ 1267 configure_encoder(enc110, link_settings); 1268 cntl.connector_obj_id = enc110->base.connector; 1269 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1270 cntl.engine_id = enc->preferred_engine; 1271 cntl.transmitter = enc110->base.transmitter; 1272 cntl.pll_id = clock_source; 1273 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1274 cntl.lanes_number = link_settings->lane_count; 1275 cntl.hpd_sel = enc110->base.hpd_source; 1276 cntl.pixel_clock = link_settings->link_rate 1277 * LINK_RATE_REF_FREQ_IN_KHZ; 1278 /* TODO: check if undefined works */ 1279 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1280 1281 result = link_transmitter_control(enc110, &cntl); 1282 1283 if (result != BP_RESULT_OK) { 1284 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1285 __func__); 1286 BREAK_TO_DEBUGGER(); 1287 } 1288 } 1289 1290 /* enables DP PHY output in MST mode */ 1291 void dce110_link_encoder_enable_dp_mst_output( 1292 struct link_encoder *enc, 1293 const struct dc_link_settings *link_settings, 1294 enum clock_source_id clock_source) 1295 { 1296 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1297 struct bp_transmitter_control cntl = { 0 }; 1298 enum bp_result result; 1299 1300 /* Enable the PHY */ 1301 1302 /* number_of_lanes is used for pixel clock adjust, 1303 * but it's not passed to asic_control. 1304 * We need to set number of lanes manually. 1305 */ 1306 configure_encoder(enc110, link_settings); 1307 1308 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1309 cntl.engine_id = ENGINE_ID_UNKNOWN; 1310 cntl.transmitter = enc110->base.transmitter; 1311 cntl.pll_id = clock_source; 1312 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1313 cntl.lanes_number = link_settings->lane_count; 1314 cntl.hpd_sel = enc110->base.hpd_source; 1315 cntl.pixel_clock = link_settings->link_rate 1316 * LINK_RATE_REF_FREQ_IN_KHZ; 1317 /* TODO: check if undefined works */ 1318 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1319 1320 result = link_transmitter_control(enc110, &cntl); 1321 1322 if (result != BP_RESULT_OK) { 1323 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1324 __func__); 1325 BREAK_TO_DEBUGGER(); 1326 } 1327 } 1328 1329 #if defined(CONFIG_DRM_AMD_DC_SI) 1330 /* enables DP PHY output */ 1331 static void dce60_link_encoder_enable_dp_output( 1332 struct link_encoder *enc, 1333 const struct dc_link_settings *link_settings, 1334 enum clock_source_id clock_source) 1335 { 1336 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1337 struct bp_transmitter_control cntl = { 0 }; 1338 enum bp_result result; 1339 1340 /* Enable the PHY */ 1341 1342 /* number_of_lanes is used for pixel clock adjust, 1343 * but it's not passed to asic_control. 1344 * We need to set number of lanes manually. 1345 */ 1346 dce60_configure_encoder(enc110, link_settings); 1347 cntl.connector_obj_id = enc110->base.connector; 1348 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1349 cntl.engine_id = enc->preferred_engine; 1350 cntl.transmitter = enc110->base.transmitter; 1351 cntl.pll_id = clock_source; 1352 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1353 cntl.lanes_number = link_settings->lane_count; 1354 cntl.hpd_sel = enc110->base.hpd_source; 1355 cntl.pixel_clock = link_settings->link_rate 1356 * LINK_RATE_REF_FREQ_IN_KHZ; 1357 /* TODO: check if undefined works */ 1358 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1359 1360 result = link_transmitter_control(enc110, &cntl); 1361 1362 if (result != BP_RESULT_OK) { 1363 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1364 __func__); 1365 BREAK_TO_DEBUGGER(); 1366 } 1367 } 1368 1369 /* enables DP PHY output in MST mode */ 1370 static void dce60_link_encoder_enable_dp_mst_output( 1371 struct link_encoder *enc, 1372 const struct dc_link_settings *link_settings, 1373 enum clock_source_id clock_source) 1374 { 1375 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1376 struct bp_transmitter_control cntl = { 0 }; 1377 enum bp_result result; 1378 1379 /* Enable the PHY */ 1380 1381 /* number_of_lanes is used for pixel clock adjust, 1382 * but it's not passed to asic_control. 1383 * We need to set number of lanes manually. 1384 */ 1385 dce60_configure_encoder(enc110, link_settings); 1386 1387 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1388 cntl.engine_id = ENGINE_ID_UNKNOWN; 1389 cntl.transmitter = enc110->base.transmitter; 1390 cntl.pll_id = clock_source; 1391 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1392 cntl.lanes_number = link_settings->lane_count; 1393 cntl.hpd_sel = enc110->base.hpd_source; 1394 cntl.pixel_clock = link_settings->link_rate 1395 * LINK_RATE_REF_FREQ_IN_KHZ; 1396 /* TODO: check if undefined works */ 1397 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1398 1399 result = link_transmitter_control(enc110, &cntl); 1400 1401 if (result != BP_RESULT_OK) { 1402 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1403 __func__); 1404 BREAK_TO_DEBUGGER(); 1405 } 1406 } 1407 #endif 1408 1409 /* 1410 * @brief 1411 * Disable transmitter and its encoder 1412 */ 1413 void dce110_link_encoder_disable_output( 1414 struct link_encoder *enc, 1415 enum signal_type signal) 1416 { 1417 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1418 struct bp_transmitter_control cntl = { 0 }; 1419 enum bp_result result; 1420 1421 if (enc->analog_engine != ENGINE_ID_UNKNOWN) 1422 link_dac_encoder_control(enc110, ENCODER_CONTROL_DISABLE, 0); 1423 1424 /* The code below only applies to connectors that support digital signals. */ 1425 if (enc->transmitter == TRANSMITTER_UNKNOWN) 1426 return; 1427 1428 if (!dce110_is_dig_enabled(enc)) { 1429 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1430 return; 1431 } 1432 /* Power-down RX and disable GPU PHY should be paired. 1433 * Disabling PHY without powering down RX may cause 1434 * symbol lock loss, on which we will get DP Sink interrupt. */ 1435 1436 /* There is a case for the DP active dongles 1437 * where we want to disable the PHY but keep RX powered, 1438 * for those we need to ignore DP Sink interrupt 1439 * by checking lane count that has been set 1440 * on the last do_enable_output(). */ 1441 1442 /* disable transmitter */ 1443 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1444 cntl.transmitter = enc110->base.transmitter; 1445 cntl.hpd_sel = enc110->base.hpd_source; 1446 cntl.signal = signal; 1447 cntl.connector_obj_id = enc110->base.connector; 1448 1449 result = link_transmitter_control(enc110, &cntl); 1450 1451 if (result != BP_RESULT_OK) { 1452 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1453 __func__); 1454 BREAK_TO_DEBUGGER(); 1455 return; 1456 } 1457 1458 /* disable encoder */ 1459 if (dc_is_dp_signal(signal)) 1460 link_encoder_disable(enc110); 1461 } 1462 1463 void dce110_link_encoder_dp_set_lane_settings( 1464 struct link_encoder *enc, 1465 const struct dc_link_settings *link_settings, 1466 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 1467 { 1468 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1469 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1470 int32_t lane = 0; 1471 struct bp_transmitter_control cntl = { 0 }; 1472 1473 if (!link_settings) { 1474 BREAK_TO_DEBUGGER(); 1475 return; 1476 } 1477 1478 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1479 cntl.transmitter = enc110->base.transmitter; 1480 cntl.connector_obj_id = enc110->base.connector; 1481 cntl.lanes_number = link_settings->lane_count; 1482 cntl.hpd_sel = enc110->base.hpd_source; 1483 cntl.pixel_clock = link_settings->link_rate * 1484 LINK_RATE_REF_FREQ_IN_KHZ; 1485 1486 for (lane = 0; lane < link_settings->lane_count; lane++) { 1487 /* translate lane settings */ 1488 1489 training_lane_set.bits.VOLTAGE_SWING_SET = 1490 lane_settings[lane].VOLTAGE_SWING; 1491 training_lane_set.bits.PRE_EMPHASIS_SET = 1492 lane_settings[lane].PRE_EMPHASIS; 1493 1494 /* post cursor 2 setting only applies to HBR2 link rate */ 1495 if (link_settings->link_rate == LINK_RATE_HIGH2) { 1496 /* this is passed to VBIOS 1497 * to program post cursor 2 level */ 1498 1499 training_lane_set.bits.POST_CURSOR2_SET = 1500 lane_settings[lane].POST_CURSOR2; 1501 } 1502 1503 cntl.lane_select = lane; 1504 cntl.lane_settings = training_lane_set.raw; 1505 1506 /* call VBIOS table to set voltage swing and pre-emphasis */ 1507 if (link_transmitter_control(enc110, &cntl) != BP_RESULT_OK) { 1508 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", __func__); 1509 BREAK_TO_DEBUGGER(); 1510 } 1511 } 1512 } 1513 1514 /* set DP PHY test and training patterns */ 1515 void dce110_link_encoder_dp_set_phy_pattern( 1516 struct link_encoder *enc, 1517 const struct encoder_set_dp_phy_pattern_param *param) 1518 { 1519 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1520 1521 switch (param->dp_phy_pattern) { 1522 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1523 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1524 break; 1525 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1526 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1527 break; 1528 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1529 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1530 break; 1531 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1532 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1533 break; 1534 case DP_TEST_PATTERN_D102: 1535 set_dp_phy_pattern_d102(enc110); 1536 break; 1537 case DP_TEST_PATTERN_SYMBOL_ERROR: 1538 set_dp_phy_pattern_symbol_error(enc110); 1539 break; 1540 case DP_TEST_PATTERN_PRBS7: 1541 set_dp_phy_pattern_prbs7(enc110); 1542 break; 1543 case DP_TEST_PATTERN_80BIT_CUSTOM: 1544 set_dp_phy_pattern_80bit_custom( 1545 enc110, param->custom_pattern); 1546 break; 1547 case DP_TEST_PATTERN_CP2520_1: 1548 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1549 break; 1550 case DP_TEST_PATTERN_CP2520_2: 1551 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1552 break; 1553 case DP_TEST_PATTERN_CP2520_3: 1554 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1555 break; 1556 case DP_TEST_PATTERN_VIDEO_MODE: { 1557 set_dp_phy_pattern_passthrough_mode( 1558 enc110, param->dp_panel_mode); 1559 break; 1560 } 1561 1562 default: 1563 /* invalid phy pattern */ 1564 ASSERT_CRITICAL(false); 1565 break; 1566 } 1567 } 1568 1569 #if defined(CONFIG_DRM_AMD_DC_SI) 1570 /* set DP PHY test and training patterns */ 1571 static void dce60_link_encoder_dp_set_phy_pattern( 1572 struct link_encoder *enc, 1573 const struct encoder_set_dp_phy_pattern_param *param) 1574 { 1575 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1576 1577 switch (param->dp_phy_pattern) { 1578 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1579 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1580 break; 1581 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1582 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1583 break; 1584 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1585 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1586 break; 1587 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1588 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1589 break; 1590 case DP_TEST_PATTERN_D102: 1591 set_dp_phy_pattern_d102(enc110); 1592 break; 1593 case DP_TEST_PATTERN_SYMBOL_ERROR: 1594 set_dp_phy_pattern_symbol_error(enc110); 1595 break; 1596 case DP_TEST_PATTERN_PRBS7: 1597 set_dp_phy_pattern_prbs7(enc110); 1598 break; 1599 case DP_TEST_PATTERN_80BIT_CUSTOM: 1600 set_dp_phy_pattern_80bit_custom( 1601 enc110, param->custom_pattern); 1602 break; 1603 case DP_TEST_PATTERN_CP2520_1: 1604 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1605 break; 1606 case DP_TEST_PATTERN_CP2520_2: 1607 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1608 break; 1609 case DP_TEST_PATTERN_CP2520_3: 1610 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1611 break; 1612 case DP_TEST_PATTERN_VIDEO_MODE: { 1613 dce60_set_dp_phy_pattern_passthrough_mode( 1614 enc110, param->dp_panel_mode); 1615 break; 1616 } 1617 1618 default: 1619 /* invalid phy pattern */ 1620 ASSERT_CRITICAL(false); 1621 break; 1622 } 1623 } 1624 #endif 1625 1626 static void fill_stream_allocation_row_info( 1627 const struct link_mst_stream_allocation *stream_allocation, 1628 uint32_t *src, 1629 uint32_t *slots) 1630 { 1631 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1632 1633 if (stream_enc) { 1634 *src = stream_enc->id; 1635 *slots = stream_allocation->slot_count; 1636 } else { 1637 *src = 0; 1638 *slots = 0; 1639 } 1640 } 1641 1642 /* programs DP MST VC payload allocation */ 1643 void dce110_link_encoder_update_mst_stream_allocation_table( 1644 struct link_encoder *enc, 1645 const struct link_mst_stream_allocation_table *table) 1646 { 1647 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1648 uint32_t value1 = 0; 1649 uint32_t value2 = 0; 1650 uint32_t slots = 0; 1651 uint32_t src = 0; 1652 uint32_t retries = 0; 1653 1654 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1655 1656 /* --- Set MSE Stream Attribute - 1657 * Setup VC Payload Table on Tx Side, 1658 * Issue allocation change trigger 1659 * to commit payload on both tx and rx side */ 1660 1661 /* we should clean-up table each time */ 1662 1663 if (table->stream_count >= 1) { 1664 fill_stream_allocation_row_info( 1665 &table->stream_allocations[0], 1666 &src, 1667 &slots); 1668 } else { 1669 src = 0; 1670 slots = 0; 1671 } 1672 1673 REG_UPDATE_2(DP_MSE_SAT0, 1674 DP_MSE_SAT_SRC0, src, 1675 DP_MSE_SAT_SLOT_COUNT0, slots); 1676 1677 if (table->stream_count >= 2) { 1678 fill_stream_allocation_row_info( 1679 &table->stream_allocations[1], 1680 &src, 1681 &slots); 1682 } else { 1683 src = 0; 1684 slots = 0; 1685 } 1686 1687 REG_UPDATE_2(DP_MSE_SAT0, 1688 DP_MSE_SAT_SRC1, src, 1689 DP_MSE_SAT_SLOT_COUNT1, slots); 1690 1691 if (table->stream_count >= 3) { 1692 fill_stream_allocation_row_info( 1693 &table->stream_allocations[2], 1694 &src, 1695 &slots); 1696 } else { 1697 src = 0; 1698 slots = 0; 1699 } 1700 1701 REG_UPDATE_2(DP_MSE_SAT1, 1702 DP_MSE_SAT_SRC2, src, 1703 DP_MSE_SAT_SLOT_COUNT2, slots); 1704 1705 if (table->stream_count >= 4) { 1706 fill_stream_allocation_row_info( 1707 &table->stream_allocations[3], 1708 &src, 1709 &slots); 1710 } else { 1711 src = 0; 1712 slots = 0; 1713 } 1714 1715 REG_UPDATE_2(DP_MSE_SAT1, 1716 DP_MSE_SAT_SRC3, src, 1717 DP_MSE_SAT_SLOT_COUNT3, slots); 1718 1719 /* --- wait for transaction finish */ 1720 1721 /* send allocation change trigger (ACT) ? 1722 * this step first sends the ACT, 1723 * then double buffers the SAT into the hardware 1724 * making the new allocation active on the DP MST mode link */ 1725 1726 1727 /* DP_MSE_SAT_UPDATE: 1728 * 0 - No Action 1729 * 1 - Update SAT with trigger 1730 * 2 - Update SAT without trigger */ 1731 1732 REG_UPDATE(DP_MSE_SAT_UPDATE, 1733 DP_MSE_SAT_UPDATE, 1); 1734 1735 /* wait for update to complete 1736 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1737 * then wait for the transmission 1738 * of at least 16 MTP headers on immediate local link. 1739 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1740 * a value of 1 indicates that DP MST mode 1741 * is in the 16 MTP keepout region after a VC has been added. 1742 * MST stream bandwidth (VC rate) can be configured 1743 * after this bit is cleared */ 1744 1745 do { 1746 udelay(10); 1747 1748 REG_READ(DP_MSE_SAT_UPDATE); 1749 1750 REG_GET(DP_MSE_SAT_UPDATE, 1751 DP_MSE_SAT_UPDATE, &value1); 1752 1753 REG_GET(DP_MSE_SAT_UPDATE, 1754 DP_MSE_16_MTP_KEEPOUT, &value2); 1755 1756 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1757 if (!value1 && !value2) 1758 break; 1759 ++retries; 1760 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1761 } 1762 1763 void dce110_link_encoder_connect_dig_be_to_fe( 1764 struct link_encoder *enc, 1765 enum engine_id engine, 1766 bool connect) 1767 { 1768 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1769 uint32_t field; 1770 1771 if (engine != ENGINE_ID_UNKNOWN) { 1772 1773 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1774 1775 if (connect) 1776 field |= get_frontend_source(engine); 1777 else 1778 field &= ~get_frontend_source(engine); 1779 1780 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1781 } 1782 } 1783 1784 void dce110_link_encoder_enable_hpd(struct link_encoder *enc) 1785 { 1786 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1787 struct dc_context *ctx = enc110->base.ctx; 1788 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1789 uint32_t hpd_enable = 0; 1790 uint32_t value = dm_read_reg(ctx, addr); 1791 1792 hpd_enable = get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); 1793 1794 if (hpd_enable == 0) 1795 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1796 } 1797 1798 void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 1799 { 1800 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1801 struct dc_context *ctx = enc110->base.ctx; 1802 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1803 uint32_t value = dm_read_reg(ctx, addr); 1804 1805 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); 1806 } 1807 1808 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, 1809 struct dc_link_settings *link_settings) 1810 { 1811 /* Set Default link settings */ 1812 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, 1813 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; 1814 1815 /* Higher link settings based on feature supported */ 1816 if (enc->features.flags.bits.IS_HBR2_CAPABLE) 1817 max_link_cap.link_rate = LINK_RATE_HIGH2; 1818 1819 if (enc->features.flags.bits.IS_HBR3_CAPABLE) 1820 max_link_cap.link_rate = LINK_RATE_HIGH3; 1821 1822 *link_settings = max_link_cap; 1823 } 1824 1825 bool dce110_get_hpd_state(struct link_encoder *enc) 1826 { 1827 uint32_t state = 0; 1828 1829 if (!enc->hpd_gpio) 1830 return false; 1831 1832 dal_gpio_lock_pin(enc->hpd_gpio); 1833 dal_gpio_get_value(enc->hpd_gpio, &state); 1834 dal_gpio_unlock_pin(enc->hpd_gpio); 1835 1836 return state; 1837 } 1838 1839 bool dce110_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms) 1840 { 1841 /* Setup HPD filtering */ 1842 if (enc->hpd_gpio && dal_gpio_lock_pin(enc->hpd_gpio) == GPIO_RESULT_OK) { 1843 struct gpio_hpd_config config; 1844 1845 config.delay_on_connect = delay_on_connect_in_ms; 1846 config.delay_on_disconnect = delay_on_disconnect_in_ms; 1847 1848 dal_irq_setup_hpd_filter(enc->hpd_gpio, &config); 1849 1850 dal_gpio_unlock_pin(enc->hpd_gpio); 1851 1852 return true; 1853 } else { 1854 ASSERT(0); 1855 return false; 1856 } 1857 } 1858 1859 #if defined(CONFIG_DRM_AMD_DC_SI) 1860 static const struct link_encoder_funcs dce60_lnk_enc_funcs = { 1861 .validate_output_with_stream = 1862 dce110_link_encoder_validate_output_with_stream, 1863 .hw_init = dce110_link_encoder_hw_init, 1864 .setup = dce110_link_encoder_setup, 1865 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 1866 .enable_dp_output = dce60_link_encoder_enable_dp_output, 1867 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, 1868 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 1869 .enable_analog_output = dce110_link_encoder_enable_analog_output, 1870 .disable_output = dce110_link_encoder_disable_output, 1871 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 1872 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, 1873 .update_mst_stream_allocation_table = 1874 dce110_link_encoder_update_mst_stream_allocation_table, 1875 .psr_program_dp_dphy_fast_training = 1876 dce110_psr_program_dp_dphy_fast_training, 1877 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 1878 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 1879 .enable_hpd = dce110_link_encoder_enable_hpd, 1880 .disable_hpd = dce110_link_encoder_disable_hpd, 1881 .is_dig_enabled = dce110_is_dig_enabled, 1882 .destroy = dce110_link_encoder_destroy, 1883 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 1884 .get_dig_frontend = dce110_get_dig_frontend, 1885 .get_hpd_state = dce110_get_hpd_state, 1886 .program_hpd_filter = dce110_program_hpd_filter, 1887 }; 1888 1889 static const struct link_encoder_funcs dce60_lnk_enc_funcs_no_hpd = { 1890 .validate_output_with_stream = 1891 dce110_link_encoder_validate_output_with_stream, 1892 .hw_init = dce110_link_encoder_hw_init, 1893 .setup = dce110_link_encoder_setup, 1894 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 1895 .enable_dp_output = dce60_link_encoder_enable_dp_output, 1896 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, 1897 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 1898 .enable_analog_output = dce110_link_encoder_enable_analog_output, 1899 .disable_output = dce110_link_encoder_disable_output, 1900 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 1901 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, 1902 .update_mst_stream_allocation_table = 1903 dce110_link_encoder_update_mst_stream_allocation_table, 1904 .psr_program_dp_dphy_fast_training = 1905 dce110_psr_program_dp_dphy_fast_training, 1906 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 1907 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 1908 .is_dig_enabled = dce110_is_dig_enabled, 1909 .destroy = dce110_link_encoder_destroy, 1910 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 1911 .get_dig_frontend = dce110_get_dig_frontend, 1912 .get_hpd_state = dce110_get_hpd_state, 1913 .program_hpd_filter = dce110_program_hpd_filter, 1914 }; 1915 1916 void dce60_link_encoder_construct( 1917 struct dce110_link_encoder *enc110, 1918 const struct encoder_init_data *init_data, 1919 const struct encoder_feature_support *enc_features, 1920 const struct dce110_link_enc_registers *link_regs, 1921 const struct dce110_link_enc_aux_registers *aux_regs, 1922 const struct dce110_link_enc_hpd_registers *hpd_regs) 1923 { 1924 struct bp_encoder_cap_info bp_cap_info = {0}; 1925 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 1926 enum bp_result result = BP_RESULT_OK; 1927 1928 if (hpd_regs) 1929 enc110->base.funcs = &dce60_lnk_enc_funcs; 1930 else 1931 enc110->base.funcs = &dce60_lnk_enc_funcs_no_hpd; 1932 enc110->base.ctx = init_data->ctx; 1933 enc110->base.id = init_data->encoder; 1934 enc110->base.analog_id = init_data->analog_encoder; 1935 1936 enc110->base.hpd_gpio = init_data->hpd_gpio; 1937 enc110->base.hpd_source = init_data->hpd_source; 1938 enc110->base.connector = init_data->connector; 1939 1940 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1941 enc110->base.analog_engine = init_data->analog_engine; 1942 1943 enc110->base.features = *enc_features; 1944 1945 enc110->base.transmitter = init_data->transmitter; 1946 1947 /* set the flag to indicate whether driver poll the I2C data pin 1948 * while doing the DP sink detect 1949 */ 1950 1951 /* if (dal_adapter_service_is_feature_supported(as, 1952 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 1953 enc110->base.features.flags.bits. 1954 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 1955 1956 enc110->base.output_signals = 1957 SIGNAL_TYPE_DVI_SINGLE_LINK | 1958 SIGNAL_TYPE_DVI_DUAL_LINK | 1959 SIGNAL_TYPE_LVDS | 1960 SIGNAL_TYPE_DISPLAY_PORT | 1961 SIGNAL_TYPE_DISPLAY_PORT_MST | 1962 SIGNAL_TYPE_EDP | 1963 SIGNAL_TYPE_HDMI_TYPE_A; 1964 1965 if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || 1966 enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 1967 enc110->base.analog_engine != ENGINE_ID_UNKNOWN) 1968 enc110->base.output_signals |= SIGNAL_TYPE_RGB; 1969 1970 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 1971 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 1972 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 1973 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 1974 * Prefer DIG assignment is decided by board design. 1975 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 1976 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 1977 * By this, adding DIGG should not hurt DCE 8.0. 1978 * This will let DCE 8.1 share DCE 8.0 as much as possible 1979 */ 1980 1981 enc110->link_regs = link_regs; 1982 enc110->aux_regs = aux_regs; 1983 enc110->hpd_regs = hpd_regs; 1984 1985 switch (enc110->base.transmitter) { 1986 case TRANSMITTER_UNIPHY_A: 1987 enc110->base.preferred_engine = ENGINE_ID_DIGA; 1988 break; 1989 case TRANSMITTER_UNIPHY_B: 1990 enc110->base.preferred_engine = ENGINE_ID_DIGB; 1991 break; 1992 case TRANSMITTER_UNIPHY_C: 1993 enc110->base.preferred_engine = ENGINE_ID_DIGC; 1994 break; 1995 case TRANSMITTER_UNIPHY_D: 1996 enc110->base.preferred_engine = ENGINE_ID_DIGD; 1997 break; 1998 case TRANSMITTER_UNIPHY_E: 1999 enc110->base.preferred_engine = ENGINE_ID_DIGE; 2000 break; 2001 case TRANSMITTER_UNIPHY_F: 2002 enc110->base.preferred_engine = ENGINE_ID_DIGF; 2003 break; 2004 case TRANSMITTER_UNIPHY_G: 2005 enc110->base.preferred_engine = ENGINE_ID_DIGG; 2006 break; 2007 default: 2008 if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { 2009 /* The connector is analog-only, ie. VGA */ 2010 enc110->base.preferred_engine = init_data->analog_engine; 2011 enc110->base.output_signals = SIGNAL_TYPE_RGB; 2012 enc110->base.transmitter = TRANSMITTER_UNKNOWN; 2013 break; 2014 } 2015 ASSERT_CRITICAL(false); 2016 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 2017 } 2018 2019 /* default to one to mirror Windows behavior */ 2020 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 2021 2022 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 2023 enc110->base.id, &bp_cap_info); 2024 2025 /* Override features with DCE-specific values */ 2026 if (result == BP_RESULT_OK) { 2027 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 2028 bp_cap_info.DP_HBR2_EN; 2029 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 2030 bp_cap_info.DP_HBR3_EN; 2031 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 2032 } else if (result != BP_RESULT_NORECORD) { 2033 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 2034 __func__, 2035 result); 2036 } 2037 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 2038 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 2039 } 2040 } 2041 #endif 2042