1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
37
38 #include "i2c-stm32.h"
39
40 /* STM32F7 I2C registers */
41 #define STM32F7_I2C_CR1 0x00
42 #define STM32F7_I2C_CR2 0x04
43 #define STM32F7_I2C_OAR1 0x08
44 #define STM32F7_I2C_OAR2 0x0C
45 #define STM32F7_I2C_PECR 0x20
46 #define STM32F7_I2C_TIMINGR 0x10
47 #define STM32F7_I2C_ISR 0x18
48 #define STM32F7_I2C_ICR 0x1C
49 #define STM32F7_I2C_RXDR 0x24
50 #define STM32F7_I2C_TXDR 0x28
51
52 /* STM32F7 I2C control 1 */
53 #define STM32_I2C_CR1_FMP BIT(24)
54 #define STM32F7_I2C_CR1_PECEN BIT(23)
55 #define STM32F7_I2C_CR1_ALERTEN BIT(22)
56 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
57 #define STM32F7_I2C_CR1_WUPEN BIT(18)
58 #define STM32F7_I2C_CR1_SBC BIT(16)
59 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
60 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
61 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
62 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
63 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
64 #define STM32F7_I2C_CR1_ERRIE BIT(7)
65 #define STM32F7_I2C_CR1_TCIE BIT(6)
66 #define STM32F7_I2C_CR1_STOPIE BIT(5)
67 #define STM32F7_I2C_CR1_NACKIE BIT(4)
68 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
69 #define STM32F7_I2C_CR1_RXIE BIT(2)
70 #define STM32F7_I2C_CR1_TXIE BIT(1)
71 #define STM32F7_I2C_CR1_PE BIT(0)
72 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
73 | STM32F7_I2C_CR1_TCIE \
74 | STM32F7_I2C_CR1_STOPIE \
75 | STM32F7_I2C_CR1_NACKIE \
76 | STM32F7_I2C_CR1_RXIE \
77 | STM32F7_I2C_CR1_TXIE)
78 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
79 | STM32F7_I2C_CR1_STOPIE \
80 | STM32F7_I2C_CR1_NACKIE \
81 | STM32F7_I2C_CR1_RXIE \
82 | STM32F7_I2C_CR1_TXIE)
83
84 /* STM32F7 I2C control 2 */
85 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
86 #define STM32F7_I2C_CR2_RELOAD BIT(24)
87 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
88 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
89 #define STM32F7_I2C_CR2_NACK BIT(15)
90 #define STM32F7_I2C_CR2_STOP BIT(14)
91 #define STM32F7_I2C_CR2_START BIT(13)
92 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
93 #define STM32F7_I2C_CR2_ADD10 BIT(11)
94 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
95 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
96 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
97 STM32F7_I2C_CR2_SADD10_MASK))
98 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
99 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
100
101 /* STM32F7 I2C Own Address 1 */
102 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
103 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
104 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
105 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
106 STM32F7_I2C_OAR1_OA1_10_MASK))
107 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
108 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
109 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
110 | STM32F7_I2C_OAR1_OA1_10_MASK \
111 | STM32F7_I2C_OAR1_OA1EN \
112 | STM32F7_I2C_OAR1_OA1MODE)
113
114 /* STM32F7 I2C Own Address 2 */
115 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
116 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
117 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
118 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
119 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
120 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
121 | STM32F7_I2C_OAR2_OA2_7_MASK \
122 | STM32F7_I2C_OAR2_OA2EN)
123
124 /* STM32F7 I2C Interrupt Status */
125 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
126 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
127 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
128 #define STM32F7_I2C_ISR_DIR BIT(16)
129 #define STM32F7_I2C_ISR_BUSY BIT(15)
130 #define STM32F7_I2C_ISR_ALERT BIT(13)
131 #define STM32F7_I2C_ISR_PECERR BIT(11)
132 #define STM32F7_I2C_ISR_ARLO BIT(9)
133 #define STM32F7_I2C_ISR_BERR BIT(8)
134 #define STM32F7_I2C_ISR_TCR BIT(7)
135 #define STM32F7_I2C_ISR_TC BIT(6)
136 #define STM32F7_I2C_ISR_STOPF BIT(5)
137 #define STM32F7_I2C_ISR_NACKF BIT(4)
138 #define STM32F7_I2C_ISR_ADDR BIT(3)
139 #define STM32F7_I2C_ISR_RXNE BIT(2)
140 #define STM32F7_I2C_ISR_TXIS BIT(1)
141 #define STM32F7_I2C_ISR_TXE BIT(0)
142
143 /* STM32F7 I2C Interrupt Clear */
144 #define STM32F7_I2C_ICR_ALERTCF BIT(13)
145 #define STM32F7_I2C_ICR_PECCF BIT(11)
146 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
147 #define STM32F7_I2C_ICR_BERRCF BIT(8)
148 #define STM32F7_I2C_ICR_STOPCF BIT(5)
149 #define STM32F7_I2C_ICR_NACKCF BIT(4)
150 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
151
152 /* STM32F7 I2C Timing */
153 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
154 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
155 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
156 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
157 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
158
159 #define STM32F7_I2C_MAX_LEN 0xff
160 #define STM32F7_I2C_DMA_LEN_MIN 0x16
161 enum {
162 STM32F7_SLAVE_HOSTNOTIFY,
163 STM32F7_SLAVE_7_10_BITS_ADDR,
164 STM32F7_SLAVE_7_BITS_ADDR,
165 STM32F7_I2C_MAX_SLAVE
166 };
167
168 #define STM32F7_I2C_DNF_DEFAULT 0
169 #define STM32F7_I2C_DNF_MAX 15
170
171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
172 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
173
174 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
175 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
176
177 #define STM32F7_PRESC_MAX BIT(4)
178 #define STM32F7_SCLDEL_MAX BIT(4)
179 #define STM32F7_SDADEL_MAX BIT(4)
180 #define STM32F7_SCLH_MAX BIT(8)
181 #define STM32F7_SCLL_MAX BIT(8)
182
183 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
184
185 /**
186 * struct stm32f7_i2c_regs - i2c f7 registers backup
187 * @cr1: Control register 1
188 * @cr2: Control register 2
189 * @oar1: Own address 1 register
190 * @oar2: Own address 2 register
191 * @tmgr: Timing register
192 */
193 struct stm32f7_i2c_regs {
194 u32 cr1;
195 u32 cr2;
196 u32 oar1;
197 u32 oar2;
198 u32 tmgr;
199 };
200
201 /**
202 * struct stm32f7_i2c_spec - private i2c specification timing
203 * @rate: I2C bus speed (Hz)
204 * @fall_max: Max fall time of both SDA and SCL signals (ns)
205 * @rise_max: Max rise time of both SDA and SCL signals (ns)
206 * @hddat_min: Min data hold time (ns)
207 * @vddat_max: Max data valid time (ns)
208 * @sudat_min: Min data setup time (ns)
209 * @l_min: Min low period of the SCL clock (ns)
210 * @h_min: Min high period of the SCL clock (ns)
211 */
212 struct stm32f7_i2c_spec {
213 u32 rate;
214 u32 fall_max;
215 u32 rise_max;
216 u32 hddat_min;
217 u32 vddat_max;
218 u32 sudat_min;
219 u32 l_min;
220 u32 h_min;
221 };
222
223 /**
224 * struct stm32f7_i2c_setup - private I2C timing setup parameters
225 * @speed_freq: I2C speed frequency (Hz)
226 * @clock_src: I2C clock source frequency (Hz)
227 * @rise_time: Rise time (ns)
228 * @fall_time: Fall time (ns)
229 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
230 * @single_it_line: Only a single IT line is used for both events/errors
231 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1
232 */
233 struct stm32f7_i2c_setup {
234 u32 speed_freq;
235 u32 clock_src;
236 u32 rise_time;
237 u32 fall_time;
238 u32 fmp_clr_offset;
239 bool single_it_line;
240 bool fmp_cr1_bit;
241 };
242
243 /**
244 * struct stm32f7_i2c_timings - private I2C output parameters
245 * @node: List entry
246 * @presc: Prescaler value
247 * @scldel: Data setup time
248 * @sdadel: Data hold time
249 * @sclh: SCL high period (master mode)
250 * @scll: SCL low period (master mode)
251 */
252 struct stm32f7_i2c_timings {
253 struct list_head node;
254 u8 presc;
255 u8 scldel;
256 u8 sdadel;
257 u8 sclh;
258 u8 scll;
259 };
260
261 /**
262 * struct stm32f7_i2c_msg - client specific data
263 * @addr: 8-bit or 10-bit slave addr, including r/w bit
264 * @count: number of bytes to be transferred
265 * @buf: data buffer
266 * @result: result of the transfer
267 * @stop: last I2C msg to be sent, i.e. STOP to be generated
268 * @smbus: boolean to know if the I2C IP is used in SMBus mode
269 * @size: type of SMBus protocol
270 * @read_write: direction of SMBus protocol
271 * SMBus block read and SMBus block write - block read process call protocols
272 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
273 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
274 * This buffer has to be 32-bit aligned to be compliant with memory address
275 * register in DMA mode.
276 */
277 struct stm32f7_i2c_msg {
278 u16 addr;
279 u32 count;
280 u8 *buf;
281 int result;
282 bool stop;
283 bool smbus;
284 int size;
285 char read_write;
286 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
287 };
288
289 /**
290 * struct stm32f7_i2c_alert - SMBus alert specific data
291 * @setup: platform data for the smbus_alert i2c client
292 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
293 * Response Address
294 */
295 struct stm32f7_i2c_alert {
296 struct i2c_smbus_alert_setup setup;
297 struct i2c_client *ara;
298 };
299
300 /**
301 * struct stm32f7_i2c_dev - private data of the controller
302 * @adap: I2C adapter for this controller
303 * @dev: device for this controller
304 * @base: virtual memory area
305 * @complete: completion of I2C message
306 * @clk: hw i2c clock
307 * @bus_rate: I2C clock frequency of the controller
308 * @msg: Pointer to data to be written
309 * @msg_num: number of I2C messages to be executed
310 * @msg_id: message identifiant
311 * @f7_msg: customized i2c msg for driver usage
312 * @setup: I2C timing input setup
313 * @timing: I2C computed timings
314 * @slave: list of slave devices registered on the I2C bus
315 * @slave_running: slave device currently used
316 * @backup_regs: backup of i2c controller registers (for suspend/resume)
317 * @slave_dir: transfer direction for the current slave device
318 * @master_mode: boolean to know in which mode the I2C is running (master or
319 * slave)
320 * @dma: dma data
321 * @use_dma: boolean to know if dma is used in the current transfer
322 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
323 * @fmp_sreg: register address for setting Fast Mode Plus bits
324 * @fmp_creg: register address for clearing Fast Mode Plus bits
325 * @fmp_mask: mask for Fast Mode Plus bits in set register
326 * @wakeup_src: boolean to know if the device is a wakeup source
327 * @smbus_mode: states that the controller is configured in SMBus mode
328 * @host_notify_client: SMBus host-notify client
329 * @analog_filter: boolean to indicate enabling of the analog filter
330 * @dnf_dt: value of digital filter requested via dt
331 * @dnf: value of digital filter to apply
332 * @alert: SMBus alert specific data
333 * @atomic: boolean indicating that current transfer is atomic
334 */
335 struct stm32f7_i2c_dev {
336 struct i2c_adapter adap;
337 struct device *dev;
338 void __iomem *base;
339 struct completion complete;
340 struct clk *clk;
341 unsigned int bus_rate;
342 struct i2c_msg *msg;
343 unsigned int msg_num;
344 unsigned int msg_id;
345 struct stm32f7_i2c_msg f7_msg;
346 struct stm32f7_i2c_setup setup;
347 struct stm32f7_i2c_timings timing;
348 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
349 struct i2c_client *slave_running;
350 struct stm32f7_i2c_regs backup_regs;
351 u32 slave_dir;
352 bool master_mode;
353 struct stm32_i2c_dma *dma;
354 bool use_dma;
355 struct regmap *regmap;
356 u32 fmp_sreg;
357 u32 fmp_creg;
358 u32 fmp_mask;
359 bool wakeup_src;
360 bool smbus_mode;
361 struct i2c_client *host_notify_client;
362 bool analog_filter;
363 u32 dnf_dt;
364 u32 dnf;
365 struct stm32f7_i2c_alert *alert;
366 bool atomic;
367 };
368
369 /*
370 * All these values are coming from I2C Specification, Version 6.0, 4th of
371 * April 2014.
372 *
373 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
374 * and Fast-mode Plus I2C-bus devices
375 */
376 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
377 {
378 .rate = I2C_MAX_STANDARD_MODE_FREQ,
379 .fall_max = 300,
380 .rise_max = 1000,
381 .hddat_min = 0,
382 .vddat_max = 3450,
383 .sudat_min = 250,
384 .l_min = 4700,
385 .h_min = 4000,
386 },
387 {
388 .rate = I2C_MAX_FAST_MODE_FREQ,
389 .fall_max = 300,
390 .rise_max = 300,
391 .hddat_min = 0,
392 .vddat_max = 900,
393 .sudat_min = 100,
394 .l_min = 1300,
395 .h_min = 600,
396 },
397 {
398 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
399 .fall_max = 100,
400 .rise_max = 120,
401 .hddat_min = 0,
402 .vddat_max = 450,
403 .sudat_min = 50,
404 .l_min = 500,
405 .h_min = 260,
406 },
407 };
408
409 static const struct stm32f7_i2c_setup stm32f7_setup = {
410 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
411 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
412 };
413
414 static const struct stm32f7_i2c_setup stm32mp15_setup = {
415 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
416 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
417 .fmp_clr_offset = 0x40,
418 };
419
420 static const struct stm32f7_i2c_setup stm32mp13_setup = {
421 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
422 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
423 .fmp_clr_offset = 0x4,
424 };
425
426 static const struct stm32f7_i2c_setup stm32mp25_setup = {
427 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
428 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
429 .single_it_line = true,
430 .fmp_cr1_bit = true,
431 };
432
stm32f7_i2c_set_bits(void __iomem * reg,u32 mask)433 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
434 {
435 writel_relaxed(readl_relaxed(reg) | mask, reg);
436 }
437
stm32f7_i2c_clr_bits(void __iomem * reg,u32 mask)438 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
439 {
440 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
441 }
442
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev * i2c_dev,u32 mask)443 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
444 {
445 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
446 }
447
stm32f7_get_specs(u32 rate)448 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
449 {
450 int i;
451
452 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
453 if (rate <= stm32f7_i2c_specs[i].rate)
454 return &stm32f7_i2c_specs[i];
455
456 return ERR_PTR(-EINVAL);
457 }
458
459 #define RATE_MIN(rate) ((rate) * 8 / 10)
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup,struct stm32f7_i2c_timings * output)460 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
461 struct stm32f7_i2c_setup *setup,
462 struct stm32f7_i2c_timings *output)
463 {
464 struct stm32f7_i2c_spec *specs;
465 u32 p_prev = STM32F7_PRESC_MAX;
466 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
467 setup->clock_src);
468 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
469 setup->speed_freq);
470 u32 clk_error_prev = i2cbus;
471 u32 tsync;
472 u32 af_delay_min, af_delay_max;
473 u32 dnf_delay;
474 u32 clk_min, clk_max;
475 int sdadel_min, sdadel_max;
476 int scldel_min;
477 struct stm32f7_i2c_timings *v, *_v, *s;
478 struct list_head solutions;
479 u16 p, l, a, h;
480 int ret = 0;
481
482 specs = stm32f7_get_specs(setup->speed_freq);
483 if (specs == ERR_PTR(-EINVAL)) {
484 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
485 setup->speed_freq);
486 return -EINVAL;
487 }
488
489 if ((setup->rise_time > specs->rise_max) ||
490 (setup->fall_time > specs->fall_max)) {
491 dev_err(i2c_dev->dev,
492 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
493 setup->rise_time, specs->rise_max,
494 setup->fall_time, specs->fall_max);
495 return -EINVAL;
496 }
497
498 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
499 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
500 dev_err(i2c_dev->dev,
501 "DNF out of bound %d/%d\n",
502 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
503 return -EINVAL;
504 }
505
506 /* Analog and Digital Filters */
507 af_delay_min =
508 (i2c_dev->analog_filter ?
509 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
510 af_delay_max =
511 (i2c_dev->analog_filter ?
512 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
513 dnf_delay = i2c_dev->dnf * i2cclk;
514
515 sdadel_min = specs->hddat_min + setup->fall_time -
516 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
517
518 sdadel_max = specs->vddat_max - setup->rise_time -
519 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
520
521 scldel_min = setup->rise_time + specs->sudat_min;
522
523 if (sdadel_min < 0)
524 sdadel_min = 0;
525 if (sdadel_max < 0)
526 sdadel_max = 0;
527
528 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
529 sdadel_min, sdadel_max, scldel_min);
530
531 INIT_LIST_HEAD(&solutions);
532 /* Compute possible values for PRESC, SCLDEL and SDADEL */
533 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
534 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
535 u32 scldel = (l + 1) * (p + 1) * i2cclk;
536
537 if (scldel < scldel_min)
538 continue;
539
540 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
541 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
542
543 if (((sdadel >= sdadel_min) &&
544 (sdadel <= sdadel_max)) &&
545 (p != p_prev)) {
546 v = kmalloc(sizeof(*v), GFP_KERNEL);
547 if (!v) {
548 ret = -ENOMEM;
549 goto exit;
550 }
551
552 v->presc = p;
553 v->scldel = l;
554 v->sdadel = a;
555 p_prev = p;
556
557 list_add_tail(&v->node,
558 &solutions);
559 break;
560 }
561 }
562
563 if (p_prev == p)
564 break;
565 }
566 }
567
568 if (list_empty(&solutions)) {
569 dev_err(i2c_dev->dev, "no Prescaler solution\n");
570 ret = -EPERM;
571 goto exit;
572 }
573
574 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
575 s = NULL;
576 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
577 clk_min = NSEC_PER_SEC / setup->speed_freq;
578
579 /*
580 * Among Prescaler possibilities discovered above figures out SCL Low
581 * and High Period. Provided:
582 * - SCL Low Period has to be higher than SCL Clock Low Period
583 * defined by I2C Specification. I2C Clock has to be lower than
584 * (SCL Low Period - Analog/Digital filters) / 4.
585 * - SCL High Period has to be lower than SCL Clock High Period
586 * defined by I2C Specification
587 * - I2C Clock has to be lower than SCL High Period
588 */
589 list_for_each_entry(v, &solutions, node) {
590 u32 prescaler = (v->presc + 1) * i2cclk;
591
592 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
593 u32 tscl_l = (l + 1) * prescaler + tsync;
594
595 if ((tscl_l < specs->l_min) ||
596 (i2cclk >=
597 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
598 continue;
599 }
600
601 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
602 u32 tscl_h = (h + 1) * prescaler + tsync;
603 u32 tscl = tscl_l + tscl_h +
604 setup->rise_time + setup->fall_time;
605
606 if ((tscl >= clk_min) && (tscl <= clk_max) &&
607 (tscl_h >= specs->h_min) &&
608 (i2cclk < tscl_h)) {
609 int clk_error = tscl - i2cbus;
610
611 if (clk_error < 0)
612 clk_error = -clk_error;
613
614 if (clk_error < clk_error_prev) {
615 clk_error_prev = clk_error;
616 v->scll = l;
617 v->sclh = h;
618 s = v;
619 }
620 }
621 }
622 }
623 }
624
625 if (!s) {
626 dev_err(i2c_dev->dev, "no solution at all\n");
627 ret = -EPERM;
628 goto exit;
629 }
630
631 output->presc = s->presc;
632 output->scldel = s->scldel;
633 output->sdadel = s->sdadel;
634 output->scll = s->scll;
635 output->sclh = s->sclh;
636
637 dev_dbg(i2c_dev->dev,
638 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
639 output->presc,
640 output->scldel, output->sdadel,
641 output->scll, output->sclh);
642
643 exit:
644 /* Release list and memory */
645 list_for_each_entry_safe(v, _v, &solutions, node) {
646 list_del(&v->node);
647 kfree(v);
648 }
649
650 return ret;
651 }
652
stm32f7_get_lower_rate(u32 rate)653 static u32 stm32f7_get_lower_rate(u32 rate)
654 {
655 int i = ARRAY_SIZE(stm32f7_i2c_specs);
656
657 while (--i)
658 if (stm32f7_i2c_specs[i].rate < rate)
659 break;
660
661 return stm32f7_i2c_specs[i].rate;
662 }
663
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup)664 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
665 struct stm32f7_i2c_setup *setup)
666 {
667 struct i2c_timings timings, *t = &timings;
668 int ret = 0;
669
670 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
671 t->scl_rise_ns = i2c_dev->setup.rise_time;
672 t->scl_fall_ns = i2c_dev->setup.fall_time;
673
674 i2c_parse_fw_timings(i2c_dev->dev, t, false);
675
676 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
677 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
678 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
679 return -EINVAL;
680 }
681
682 setup->speed_freq = t->bus_freq_hz;
683 i2c_dev->setup.rise_time = t->scl_rise_ns;
684 i2c_dev->setup.fall_time = t->scl_fall_ns;
685 i2c_dev->dnf_dt = t->digital_filter_width_ns;
686 setup->clock_src = clk_get_rate(i2c_dev->clk);
687
688 if (!setup->clock_src) {
689 dev_err(i2c_dev->dev, "clock rate is 0\n");
690 return -EINVAL;
691 }
692
693 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
694 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
695
696 do {
697 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
698 &i2c_dev->timing);
699 if (ret) {
700 dev_err(i2c_dev->dev,
701 "failed to compute I2C timings.\n");
702 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
703 break;
704 setup->speed_freq =
705 stm32f7_get_lower_rate(setup->speed_freq);
706 dev_warn(i2c_dev->dev,
707 "downgrade I2C Speed Freq to (%i)\n",
708 setup->speed_freq);
709 }
710 } while (ret);
711
712 if (ret) {
713 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
714 return ret;
715 }
716
717 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
718 "i2c-analog-filter");
719
720 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
721 setup->speed_freq, setup->clock_src);
722 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
723 setup->rise_time, setup->fall_time);
724 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
725 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
726
727 i2c_dev->bus_rate = setup->speed_freq;
728
729 return 0;
730 }
731
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev * i2c_dev)732 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
733 {
734 void __iomem *base = i2c_dev->base;
735 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
736
737 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
738 }
739
stm32f7_i2c_dma_callback(void * arg)740 static void stm32f7_i2c_dma_callback(void *arg)
741 {
742 struct stm32f7_i2c_dev *i2c_dev = arg;
743 struct stm32_i2c_dma *dma = i2c_dev->dma;
744
745 stm32f7_i2c_disable_dma_req(i2c_dev);
746 dmaengine_terminate_async(dma->chan_using);
747 dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len,
748 dma->dma_data_dir);
749 complete(&dma->dma_complete);
750 }
751
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev * i2c_dev)752 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
753 {
754 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
755 u32 timing = 0;
756
757 /* Timing settings */
758 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
759 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
760 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
761 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
762 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
763 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
764
765 /* Configure the Analog Filter */
766 if (i2c_dev->analog_filter)
767 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
768 STM32F7_I2C_CR1_ANFOFF);
769 else
770 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
771 STM32F7_I2C_CR1_ANFOFF);
772
773 /* Program the Digital Filter */
774 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
775 STM32F7_I2C_CR1_DNF_MASK);
776 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
777 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
778
779 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
780 STM32F7_I2C_CR1_PE);
781 }
782
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev * i2c_dev)783 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
784 {
785 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
786 void __iomem *base = i2c_dev->base;
787
788 if (f7_msg->count) {
789 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
790 f7_msg->count--;
791 }
792 }
793
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev * i2c_dev)794 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
795 {
796 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
797 void __iomem *base = i2c_dev->base;
798
799 if (f7_msg->count) {
800 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
801 f7_msg->count--;
802 } else {
803 /* Flush RX buffer has no data is expected */
804 readb_relaxed(base + STM32F7_I2C_RXDR);
805 }
806 }
807
stm32f7_i2c_reload(struct stm32f7_i2c_dev * i2c_dev)808 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
809 {
810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
811 u32 cr2;
812
813 if (i2c_dev->use_dma)
814 f7_msg->count -= STM32F7_I2C_MAX_LEN;
815
816 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
817
818 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
819 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
820 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
821 } else {
822 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
823 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
824 }
825
826 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
827 }
828
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev * i2c_dev)829 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
830 {
831 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
832 u32 cr2;
833 u8 *val;
834
835 /*
836 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
837 * data received inform us how many data will follow.
838 */
839 stm32f7_i2c_read_rx_data(i2c_dev);
840
841 /*
842 * Update NBYTES with the value read to continue the transfer
843 */
844 val = f7_msg->buf - sizeof(u8);
845 f7_msg->count = *val;
846 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
847 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
848 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
849 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
850 }
851
stm32f7_i2c_release_bus(struct i2c_adapter * i2c_adap)852 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
853 {
854 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
855
856 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
857 STM32F7_I2C_CR1_PE);
858
859 stm32f7_i2c_hw_config(i2c_dev);
860 }
861
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev * i2c_dev)862 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
863 {
864 u32 status;
865 int ret;
866
867 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
868 status,
869 !(status & STM32F7_I2C_ISR_BUSY),
870 10, 1000);
871 if (!ret)
872 return 0;
873
874 stm32f7_i2c_release_bus(&i2c_dev->adap);
875
876 return -EBUSY;
877 }
878
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,struct i2c_msg * msg)879 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
880 struct i2c_msg *msg)
881 {
882 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
883 void __iomem *base = i2c_dev->base;
884 u32 cr1, cr2;
885 int ret;
886
887 f7_msg->addr = msg->addr;
888 f7_msg->buf = msg->buf;
889 f7_msg->count = msg->len;
890 f7_msg->result = 0;
891 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
892
893 reinit_completion(&i2c_dev->complete);
894
895 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
896 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
897
898 /* Set transfer direction */
899 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
900 if (msg->flags & I2C_M_RD)
901 cr2 |= STM32F7_I2C_CR2_RD_WRN;
902
903 /* Set slave address */
904 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
905 if (msg->flags & I2C_M_TEN) {
906 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
907 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
908 cr2 |= STM32F7_I2C_CR2_ADD10;
909 } else {
910 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
911 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
912 }
913
914 /* Set nb bytes to transfer and reload if needed */
915 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
916 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
917 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
918 cr2 |= STM32F7_I2C_CR2_RELOAD;
919 } else {
920 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
921 }
922
923 /* Enable NACK, STOP, error and transfer complete interrupts */
924 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
925 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
926
927 /* Clear DMA req and TX/RX interrupt */
928 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
929 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
930
931 /* Configure DMA or enable RX/TX interrupt */
932 i2c_dev->use_dma = false;
933 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN
934 && !i2c_dev->atomic) {
935 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
936 msg->flags & I2C_M_RD,
937 f7_msg->count, f7_msg->buf,
938 stm32f7_i2c_dma_callback,
939 i2c_dev);
940 if (!ret)
941 i2c_dev->use_dma = true;
942 else
943 dev_warn(i2c_dev->dev, "can't use DMA\n");
944 }
945
946 if (!i2c_dev->use_dma) {
947 if (msg->flags & I2C_M_RD)
948 cr1 |= STM32F7_I2C_CR1_RXIE;
949 else
950 cr1 |= STM32F7_I2C_CR1_TXIE;
951 } else {
952 if (msg->flags & I2C_M_RD)
953 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
954 else
955 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
956 }
957
958 if (i2c_dev->atomic)
959 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */
960
961 /* Configure Start/Repeated Start */
962 cr2 |= STM32F7_I2C_CR2_START;
963
964 i2c_dev->master_mode = true;
965
966 /* Write configurations registers */
967 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
968 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
969 }
970
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,unsigned short flags,u8 command,union i2c_smbus_data * data)971 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
972 unsigned short flags, u8 command,
973 union i2c_smbus_data *data)
974 {
975 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
976 struct device *dev = i2c_dev->dev;
977 void __iomem *base = i2c_dev->base;
978 u32 cr1, cr2;
979 int i, ret;
980
981 f7_msg->result = 0;
982 reinit_completion(&i2c_dev->complete);
983
984 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
985 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
986
987 /* Set transfer direction */
988 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
989 if (f7_msg->read_write)
990 cr2 |= STM32F7_I2C_CR2_RD_WRN;
991
992 /* Set slave address */
993 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
994 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
995
996 f7_msg->smbus_buf[0] = command;
997 switch (f7_msg->size) {
998 case I2C_SMBUS_QUICK:
999 f7_msg->stop = true;
1000 f7_msg->count = 0;
1001 break;
1002 case I2C_SMBUS_BYTE:
1003 f7_msg->stop = true;
1004 f7_msg->count = 1;
1005 break;
1006 case I2C_SMBUS_BYTE_DATA:
1007 if (f7_msg->read_write) {
1008 f7_msg->stop = false;
1009 f7_msg->count = 1;
1010 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1011 } else {
1012 f7_msg->stop = true;
1013 f7_msg->count = 2;
1014 f7_msg->smbus_buf[1] = data->byte;
1015 }
1016 break;
1017 case I2C_SMBUS_WORD_DATA:
1018 if (f7_msg->read_write) {
1019 f7_msg->stop = false;
1020 f7_msg->count = 1;
1021 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1022 } else {
1023 f7_msg->stop = true;
1024 f7_msg->count = 3;
1025 f7_msg->smbus_buf[1] = data->word & 0xff;
1026 f7_msg->smbus_buf[2] = data->word >> 8;
1027 }
1028 break;
1029 case I2C_SMBUS_BLOCK_DATA:
1030 if (f7_msg->read_write) {
1031 f7_msg->stop = false;
1032 f7_msg->count = 1;
1033 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1034 } else {
1035 f7_msg->stop = true;
1036 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1037 !data->block[0]) {
1038 dev_err(dev, "Invalid block write size %d\n",
1039 data->block[0]);
1040 return -EINVAL;
1041 }
1042 f7_msg->count = data->block[0] + 2;
1043 for (i = 1; i < f7_msg->count; i++)
1044 f7_msg->smbus_buf[i] = data->block[i - 1];
1045 }
1046 break;
1047 case I2C_SMBUS_PROC_CALL:
1048 f7_msg->stop = false;
1049 f7_msg->count = 3;
1050 f7_msg->smbus_buf[1] = data->word & 0xff;
1051 f7_msg->smbus_buf[2] = data->word >> 8;
1052 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1053 f7_msg->read_write = I2C_SMBUS_READ;
1054 break;
1055 case I2C_SMBUS_BLOCK_PROC_CALL:
1056 f7_msg->stop = false;
1057 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1058 dev_err(dev, "Invalid block write size %d\n",
1059 data->block[0]);
1060 return -EINVAL;
1061 }
1062 f7_msg->count = data->block[0] + 2;
1063 for (i = 1; i < f7_msg->count; i++)
1064 f7_msg->smbus_buf[i] = data->block[i - 1];
1065 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1066 f7_msg->read_write = I2C_SMBUS_READ;
1067 break;
1068 case I2C_SMBUS_I2C_BLOCK_DATA:
1069 /* Rely on emulated i2c transfer (through master_xfer) */
1070 return -EOPNOTSUPP;
1071 default:
1072 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1073 return -EOPNOTSUPP;
1074 }
1075
1076 f7_msg->buf = f7_msg->smbus_buf;
1077
1078 /* Configure PEC */
1079 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1080 cr1 |= STM32F7_I2C_CR1_PECEN;
1081 if (!f7_msg->read_write) {
1082 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1083 f7_msg->count++;
1084 }
1085 } else {
1086 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1087 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1088 }
1089
1090 /* Set number of bytes to be transferred */
1091 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1092 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1093
1094 /* Enable NACK, STOP, error and transfer complete interrupts */
1095 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1096 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1097
1098 /* Clear DMA req and TX/RX interrupt */
1099 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1100 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1101
1102 /* Configure DMA or enable RX/TX interrupt */
1103 i2c_dev->use_dma = false;
1104 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1105 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1106 cr2 & STM32F7_I2C_CR2_RD_WRN,
1107 f7_msg->count, f7_msg->buf,
1108 stm32f7_i2c_dma_callback,
1109 i2c_dev);
1110 if (!ret)
1111 i2c_dev->use_dma = true;
1112 else
1113 dev_warn(i2c_dev->dev, "can't use DMA\n");
1114 }
1115
1116 if (!i2c_dev->use_dma) {
1117 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1118 cr1 |= STM32F7_I2C_CR1_RXIE;
1119 else
1120 cr1 |= STM32F7_I2C_CR1_TXIE;
1121 } else {
1122 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1123 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1124 else
1125 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1126 }
1127
1128 /* Set Start bit */
1129 cr2 |= STM32F7_I2C_CR2_START;
1130
1131 i2c_dev->master_mode = true;
1132
1133 /* Write configurations registers */
1134 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1135 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1136
1137 return 0;
1138 }
1139
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev * i2c_dev)1140 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1141 {
1142 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1143 void __iomem *base = i2c_dev->base;
1144 u32 cr1, cr2;
1145 int ret;
1146
1147 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1148 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1149
1150 /* Set transfer direction */
1151 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1152
1153 switch (f7_msg->size) {
1154 case I2C_SMBUS_BYTE_DATA:
1155 f7_msg->count = 1;
1156 break;
1157 case I2C_SMBUS_WORD_DATA:
1158 case I2C_SMBUS_PROC_CALL:
1159 f7_msg->count = 2;
1160 break;
1161 case I2C_SMBUS_BLOCK_DATA:
1162 case I2C_SMBUS_BLOCK_PROC_CALL:
1163 f7_msg->count = 1;
1164 cr2 |= STM32F7_I2C_CR2_RELOAD;
1165 break;
1166 }
1167
1168 f7_msg->buf = f7_msg->smbus_buf;
1169 f7_msg->stop = true;
1170
1171 /* Add one byte for PEC if needed */
1172 if (cr1 & STM32F7_I2C_CR1_PECEN) {
1173 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1174 f7_msg->count++;
1175 }
1176
1177 /* Set number of bytes to be transferred */
1178 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1179 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1180
1181 /*
1182 * Configure RX/TX interrupt:
1183 */
1184 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1185 cr1 |= STM32F7_I2C_CR1_RXIE;
1186
1187 /*
1188 * Configure DMA or enable RX/TX interrupt:
1189 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1190 * dma as we don't know in advance how many data will be received
1191 */
1192 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1193 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1194
1195 i2c_dev->use_dma = false;
1196 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1197 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1198 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1199 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1200 cr2 & STM32F7_I2C_CR2_RD_WRN,
1201 f7_msg->count, f7_msg->buf,
1202 stm32f7_i2c_dma_callback,
1203 i2c_dev);
1204
1205 if (!ret)
1206 i2c_dev->use_dma = true;
1207 else
1208 dev_warn(i2c_dev->dev, "can't use DMA\n");
1209 }
1210
1211 if (!i2c_dev->use_dma)
1212 cr1 |= STM32F7_I2C_CR1_RXIE;
1213 else
1214 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1215
1216 /* Configure Repeated Start */
1217 cr2 |= STM32F7_I2C_CR2_START;
1218
1219 /* Write configurations registers */
1220 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1221 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1222 }
1223
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev * i2c_dev)1224 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1225 {
1226 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1227 u8 count, internal_pec, received_pec;
1228
1229 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1230
1231 switch (f7_msg->size) {
1232 case I2C_SMBUS_BYTE:
1233 case I2C_SMBUS_BYTE_DATA:
1234 received_pec = f7_msg->smbus_buf[1];
1235 break;
1236 case I2C_SMBUS_WORD_DATA:
1237 case I2C_SMBUS_PROC_CALL:
1238 received_pec = f7_msg->smbus_buf[2];
1239 break;
1240 case I2C_SMBUS_BLOCK_DATA:
1241 case I2C_SMBUS_BLOCK_PROC_CALL:
1242 count = f7_msg->smbus_buf[0];
1243 received_pec = f7_msg->smbus_buf[count];
1244 break;
1245 default:
1246 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1247 return -EINVAL;
1248 }
1249
1250 if (internal_pec != received_pec) {
1251 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1252 internal_pec, received_pec);
1253 return -EBADMSG;
1254 }
1255
1256 return 0;
1257 }
1258
stm32f7_i2c_is_addr_match(struct i2c_client * slave,u32 addcode)1259 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1260 {
1261 u32 addr;
1262
1263 if (!slave)
1264 return false;
1265
1266 if (slave->flags & I2C_CLIENT_TEN) {
1267 /*
1268 * For 10-bit addr, addcode = 11110XY with
1269 * X = Bit 9 of slave address
1270 * Y = Bit 8 of slave address
1271 */
1272 addr = slave->addr >> 8;
1273 addr |= 0x78;
1274 if (addr == addcode)
1275 return true;
1276 } else {
1277 addr = slave->addr & 0x7f;
1278 if (addr == addcode)
1279 return true;
1280 }
1281
1282 return false;
1283 }
1284
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev * i2c_dev)1285 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1286 {
1287 struct i2c_client *slave = i2c_dev->slave_running;
1288 void __iomem *base = i2c_dev->base;
1289 u32 mask;
1290 u8 value = 0;
1291
1292 if (i2c_dev->slave_dir) {
1293 /* Notify i2c slave that new read transfer is starting */
1294 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1295
1296 /*
1297 * Disable slave TX config in case of I2C combined message
1298 * (I2C Write followed by I2C Read)
1299 */
1300 mask = STM32F7_I2C_CR2_RELOAD;
1301 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1302 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1303 STM32F7_I2C_CR1_TCIE;
1304 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1305
1306 /* Enable TX empty, STOP, NACK interrupts */
1307 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1308 STM32F7_I2C_CR1_TXIE;
1309 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1310
1311 /* Write 1st data byte */
1312 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1313 } else {
1314 /* Notify i2c slave that new write transfer is starting */
1315 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1316
1317 /* Set reload mode to be able to ACK/NACK each received byte */
1318 mask = STM32F7_I2C_CR2_RELOAD;
1319 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1320
1321 /*
1322 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1323 * Set Slave Byte Control to be able to ACK/NACK each data
1324 * byte received
1325 */
1326 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1327 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1328 STM32F7_I2C_CR1_TCIE;
1329 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1330 }
1331 }
1332
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev * i2c_dev)1333 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1334 {
1335 void __iomem *base = i2c_dev->base;
1336 u32 isr, addcode, dir, mask;
1337 int i;
1338
1339 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1340 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1341 dir = isr & STM32F7_I2C_ISR_DIR;
1342
1343 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1344 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1345 i2c_dev->slave_running = i2c_dev->slave[i];
1346 i2c_dev->slave_dir = dir;
1347
1348 /* Start I2C slave processing */
1349 stm32f7_i2c_slave_start(i2c_dev);
1350
1351 /* Clear ADDR flag */
1352 mask = STM32F7_I2C_ICR_ADDRCF;
1353 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1354 break;
1355 }
1356 }
1357 }
1358
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1359 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1360 struct i2c_client *slave, int *id)
1361 {
1362 int i;
1363
1364 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1365 if (i2c_dev->slave[i] == slave) {
1366 *id = i;
1367 return 0;
1368 }
1369 }
1370
1371 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1372
1373 return -ENODEV;
1374 }
1375
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1376 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1377 struct i2c_client *slave, int *id)
1378 {
1379 struct device *dev = i2c_dev->dev;
1380 int i;
1381
1382 /*
1383 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1384 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1385 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1386 */
1387 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1388 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1389 goto fail;
1390 *id = STM32F7_SLAVE_HOSTNOTIFY;
1391 return 0;
1392 }
1393
1394 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1395 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1396 (slave->flags & I2C_CLIENT_TEN))
1397 continue;
1398 if (!i2c_dev->slave[i]) {
1399 *id = i;
1400 return 0;
1401 }
1402 }
1403
1404 fail:
1405 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1406
1407 return -EINVAL;
1408 }
1409
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev * i2c_dev)1410 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1411 {
1412 int i;
1413
1414 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1415 if (i2c_dev->slave[i])
1416 return true;
1417 }
1418
1419 return false;
1420 }
1421
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev * i2c_dev)1422 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1423 {
1424 int i, busy;
1425
1426 busy = 0;
1427 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1428 if (i2c_dev->slave[i])
1429 busy++;
1430 }
1431
1432 return i == busy;
1433 }
1434
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev * i2c_dev,u32 status)1435 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1436 {
1437 void __iomem *base = i2c_dev->base;
1438 u32 cr2, mask;
1439 u8 val;
1440 int ret;
1441
1442 /* Slave transmitter mode */
1443 if (status & STM32F7_I2C_ISR_TXIS) {
1444 i2c_slave_event(i2c_dev->slave_running,
1445 I2C_SLAVE_READ_PROCESSED,
1446 &val);
1447
1448 /* Write data byte */
1449 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1450 }
1451
1452 /* Transfer Complete Reload for Slave receiver mode */
1453 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1454 /*
1455 * Read data byte then set NBYTES to receive next byte or NACK
1456 * the current received byte
1457 */
1458 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1459 ret = i2c_slave_event(i2c_dev->slave_running,
1460 I2C_SLAVE_WRITE_RECEIVED,
1461 &val);
1462 if (!ret) {
1463 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1464 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1465 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1466 } else {
1467 mask = STM32F7_I2C_CR2_NACK;
1468 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1469 }
1470 }
1471
1472 /* NACK received */
1473 if (status & STM32F7_I2C_ISR_NACKF) {
1474 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1475 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1476 }
1477
1478 /* STOP received */
1479 if (status & STM32F7_I2C_ISR_STOPF) {
1480 /* Disable interrupts */
1481 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1482
1483 if (i2c_dev->slave_dir) {
1484 /*
1485 * Flush TX buffer in order to not used the byte in
1486 * TXDR for the next transfer
1487 */
1488 mask = STM32F7_I2C_ISR_TXE;
1489 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1490 }
1491
1492 /* Clear STOP flag */
1493 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1494
1495 /* Notify i2c slave that a STOP flag has been detected */
1496 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1497
1498 i2c_dev->slave_running = NULL;
1499 }
1500
1501 /* Address match received */
1502 if (status & STM32F7_I2C_ISR_ADDR)
1503 stm32f7_i2c_slave_addr(i2c_dev);
1504
1505 return IRQ_HANDLED;
1506 }
1507
stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev * i2c_dev,u32 status)1508 static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1509 {
1510 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1511 u16 addr = f7_msg->addr;
1512 void __iomem *base = i2c_dev->base;
1513 struct device *dev = i2c_dev->dev;
1514
1515 /* Bus error */
1516 if (status & STM32F7_I2C_ISR_BERR) {
1517 dev_err(dev, "Bus error accessing addr 0x%x\n", addr);
1518 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1519 stm32f7_i2c_release_bus(&i2c_dev->adap);
1520 f7_msg->result = -EIO;
1521 }
1522
1523 /* Arbitration loss */
1524 if (status & STM32F7_I2C_ISR_ARLO) {
1525 dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr);
1526 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1527 f7_msg->result = -EAGAIN;
1528 }
1529
1530 if (status & STM32F7_I2C_ISR_PECERR) {
1531 dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr);
1532 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1533 f7_msg->result = -EINVAL;
1534 }
1535
1536 if (status & STM32F7_I2C_ISR_ALERT) {
1537 dev_dbg(dev, "SMBus alert received\n");
1538 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1539 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1540 return IRQ_HANDLED;
1541 }
1542
1543 if (!i2c_dev->slave_running) {
1544 u32 mask;
1545 /* Disable interrupts */
1546 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1547 mask = STM32F7_I2C_XFER_IRQ_MASK;
1548 else
1549 mask = STM32F7_I2C_ALL_IRQ_MASK;
1550 stm32f7_i2c_disable_irq(i2c_dev, mask);
1551 }
1552
1553 /* Disable dma */
1554 if (i2c_dev->use_dma)
1555 stm32f7_i2c_dma_callback(i2c_dev);
1556
1557 i2c_dev->master_mode = false;
1558 complete(&i2c_dev->complete);
1559
1560 return IRQ_HANDLED;
1561 }
1562
1563 #define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\
1564 STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT)
stm32f7_i2c_isr_event(int irq,void * data)1565 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1566 {
1567 struct stm32f7_i2c_dev *i2c_dev = data;
1568 u32 status;
1569
1570 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1571
1572 /*
1573 * Check if the interrupt is for a slave device or related
1574 * to errors flags (in case of single it line mode)
1575 */
1576 if (!i2c_dev->master_mode ||
1577 (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)))
1578 return IRQ_WAKE_THREAD;
1579
1580 /* Tx empty */
1581 if (status & STM32F7_I2C_ISR_TXIS)
1582 stm32f7_i2c_write_tx_data(i2c_dev);
1583
1584 /* RX not empty */
1585 if (status & STM32F7_I2C_ISR_RXNE)
1586 stm32f7_i2c_read_rx_data(i2c_dev);
1587
1588 /* Wake up the thread if other flags are raised */
1589 if (status &
1590 (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF |
1591 STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR))
1592 return IRQ_WAKE_THREAD;
1593
1594 return IRQ_HANDLED;
1595 }
1596
stm32f7_i2c_isr_event_thread(int irq,void * data)1597 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1598 {
1599 struct stm32f7_i2c_dev *i2c_dev = data;
1600 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1601 void __iomem *base = i2c_dev->base;
1602 u32 status, mask;
1603 int ret;
1604
1605 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1606
1607 if (!i2c_dev->master_mode)
1608 return stm32f7_i2c_slave_isr_event(i2c_dev, status);
1609
1610 /* Handle errors in case of this handler is used for events/errors */
1611 if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))
1612 return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1613
1614 /* NACK received */
1615 if (status & STM32F7_I2C_ISR_NACKF) {
1616 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1617 __func__, f7_msg->addr);
1618 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1619 if (i2c_dev->use_dma)
1620 stm32f7_i2c_dma_callback(i2c_dev);
1621 f7_msg->result = -ENXIO;
1622 }
1623
1624 if (status & STM32F7_I2C_ISR_TCR) {
1625 if (f7_msg->smbus)
1626 stm32f7_i2c_smbus_reload(i2c_dev);
1627 else
1628 stm32f7_i2c_reload(i2c_dev);
1629 }
1630
1631 /* Transfer complete */
1632 if (status & STM32F7_I2C_ISR_TC) {
1633 /* Wait for dma transfer completion before sending next message */
1634 if (i2c_dev->use_dma && !f7_msg->result) {
1635 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1636 if (!ret) {
1637 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1638 stm32f7_i2c_dma_callback(i2c_dev);
1639 f7_msg->result = -ETIMEDOUT;
1640 }
1641 }
1642 if (f7_msg->stop) {
1643 mask = STM32F7_I2C_CR2_STOP;
1644 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1645 } else if (f7_msg->smbus) {
1646 stm32f7_i2c_smbus_rep_start(i2c_dev);
1647 } else {
1648 i2c_dev->msg_id++;
1649 i2c_dev->msg++;
1650 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1651 }
1652 }
1653
1654 /* STOP detection flag */
1655 if (status & STM32F7_I2C_ISR_STOPF) {
1656 /* Disable interrupts */
1657 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1658 mask = STM32F7_I2C_XFER_IRQ_MASK;
1659 else
1660 mask = STM32F7_I2C_ALL_IRQ_MASK;
1661 stm32f7_i2c_disable_irq(i2c_dev, mask);
1662
1663 /* Clear STOP flag */
1664 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1665
1666 i2c_dev->master_mode = false;
1667 complete(&i2c_dev->complete);
1668 }
1669
1670 return IRQ_HANDLED;
1671 }
1672
stm32f7_i2c_isr_error_thread(int irq,void * data)1673 static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data)
1674 {
1675 struct stm32f7_i2c_dev *i2c_dev = data;
1676 u32 status;
1677
1678 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1679
1680 return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1681 }
1682
stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev * i2c_dev)1683 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev)
1684 {
1685 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout);
1686
1687 while (ktime_compare(ktime_get(), timeout) < 0) {
1688 udelay(5);
1689 stm32f7_i2c_isr_event(0, i2c_dev);
1690
1691 if (completion_done(&i2c_dev->complete))
1692 return 1;
1693 }
1694
1695 return 0;
1696 }
1697
stm32f7_i2c_xfer_core(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1698 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap,
1699 struct i2c_msg msgs[], int num)
1700 {
1701 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1702 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1703 struct stm32_i2c_dma *dma = i2c_dev->dma;
1704 unsigned long time_left;
1705 int ret;
1706
1707 i2c_dev->msg = msgs;
1708 i2c_dev->msg_num = num;
1709 i2c_dev->msg_id = 0;
1710 f7_msg->smbus = false;
1711
1712 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1713 if (ret < 0)
1714 return ret;
1715
1716 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1717 if (ret)
1718 goto pm_free;
1719
1720 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1721
1722 if (!i2c_dev->atomic)
1723 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1724 i2c_dev->adap.timeout);
1725 else
1726 time_left = stm32f7_i2c_wait_polling(i2c_dev);
1727
1728 ret = f7_msg->result;
1729 if (ret) {
1730 if (i2c_dev->use_dma)
1731 dmaengine_synchronize(dma->chan_using);
1732
1733 /*
1734 * It is possible that some unsent data have already been
1735 * written into TXDR. To avoid sending old data in a
1736 * further transfer, flush TXDR in case of any error
1737 */
1738 writel_relaxed(STM32F7_I2C_ISR_TXE,
1739 i2c_dev->base + STM32F7_I2C_ISR);
1740 goto pm_free;
1741 }
1742
1743 if (!time_left) {
1744 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1745 i2c_dev->msg->addr);
1746 if (i2c_dev->use_dma)
1747 dmaengine_terminate_sync(dma->chan_using);
1748 stm32f7_i2c_wait_free_bus(i2c_dev);
1749 ret = -ETIMEDOUT;
1750 }
1751
1752 pm_free:
1753 pm_runtime_mark_last_busy(i2c_dev->dev);
1754 pm_runtime_put_autosuspend(i2c_dev->dev);
1755
1756 return (ret < 0) ? ret : num;
1757 }
1758
stm32f7_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1759 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1760 struct i2c_msg msgs[], int num)
1761 {
1762 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1763
1764 i2c_dev->atomic = false;
1765 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1766 }
1767
stm32f7_i2c_xfer_atomic(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1768 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap,
1769 struct i2c_msg msgs[], int num)
1770 {
1771 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1772
1773 i2c_dev->atomic = true;
1774 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1775 }
1776
stm32f7_i2c_smbus_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)1777 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1778 unsigned short flags, char read_write,
1779 u8 command, int size,
1780 union i2c_smbus_data *data)
1781 {
1782 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1783 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1784 struct stm32_i2c_dma *dma = i2c_dev->dma;
1785 struct device *dev = i2c_dev->dev;
1786 unsigned long time_left;
1787 int i, ret;
1788
1789 f7_msg->addr = addr;
1790 f7_msg->size = size;
1791 f7_msg->read_write = read_write;
1792 f7_msg->smbus = true;
1793
1794 ret = pm_runtime_resume_and_get(dev);
1795 if (ret < 0)
1796 return ret;
1797
1798 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1799 if (ret)
1800 goto pm_free;
1801
1802 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1803 if (ret)
1804 goto pm_free;
1805
1806 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1807 i2c_dev->adap.timeout);
1808 ret = f7_msg->result;
1809 if (ret) {
1810 if (i2c_dev->use_dma)
1811 dmaengine_synchronize(dma->chan_using);
1812
1813 /*
1814 * It is possible that some unsent data have already been
1815 * written into TXDR. To avoid sending old data in a
1816 * further transfer, flush TXDR in case of any error
1817 */
1818 writel_relaxed(STM32F7_I2C_ISR_TXE,
1819 i2c_dev->base + STM32F7_I2C_ISR);
1820 goto pm_free;
1821 }
1822
1823 if (!time_left) {
1824 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1825 if (i2c_dev->use_dma)
1826 dmaengine_terminate_sync(dma->chan_using);
1827 stm32f7_i2c_wait_free_bus(i2c_dev);
1828 ret = -ETIMEDOUT;
1829 goto pm_free;
1830 }
1831
1832 /* Check PEC */
1833 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1834 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1835 if (ret)
1836 goto pm_free;
1837 }
1838
1839 if (read_write && size != I2C_SMBUS_QUICK) {
1840 switch (size) {
1841 case I2C_SMBUS_BYTE:
1842 case I2C_SMBUS_BYTE_DATA:
1843 data->byte = f7_msg->smbus_buf[0];
1844 break;
1845 case I2C_SMBUS_WORD_DATA:
1846 case I2C_SMBUS_PROC_CALL:
1847 data->word = f7_msg->smbus_buf[0] |
1848 (f7_msg->smbus_buf[1] << 8);
1849 break;
1850 case I2C_SMBUS_BLOCK_DATA:
1851 case I2C_SMBUS_BLOCK_PROC_CALL:
1852 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1853 data->block[i] = f7_msg->smbus_buf[i];
1854 break;
1855 default:
1856 dev_err(dev, "Unsupported smbus transaction\n");
1857 ret = -EINVAL;
1858 }
1859 }
1860
1861 pm_free:
1862 pm_runtime_mark_last_busy(dev);
1863 pm_runtime_put_autosuspend(dev);
1864 return ret;
1865 }
1866
stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev * i2c_dev,bool enable)1867 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1868 bool enable)
1869 {
1870 void __iomem *base = i2c_dev->base;
1871 u32 mask = STM32F7_I2C_CR1_WUPEN;
1872
1873 if (!i2c_dev->wakeup_src)
1874 return;
1875
1876 if (enable) {
1877 device_set_wakeup_enable(i2c_dev->dev, true);
1878 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1879 } else {
1880 device_set_wakeup_enable(i2c_dev->dev, false);
1881 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1882 }
1883 }
1884
stm32f7_i2c_reg_slave(struct i2c_client * slave)1885 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1886 {
1887 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1888 void __iomem *base = i2c_dev->base;
1889 struct device *dev = i2c_dev->dev;
1890 u32 oar1, oar2, mask;
1891 int id, ret;
1892
1893 if (slave->flags & I2C_CLIENT_PEC) {
1894 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1895 return -EINVAL;
1896 }
1897
1898 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1899 dev_err(dev, "Too much slave registered\n");
1900 return -EBUSY;
1901 }
1902
1903 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1904 if (ret)
1905 return ret;
1906
1907 ret = pm_runtime_resume_and_get(dev);
1908 if (ret < 0)
1909 return ret;
1910
1911 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1912 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1913
1914 switch (id) {
1915 case 0:
1916 /* Slave SMBus Host */
1917 i2c_dev->slave[id] = slave;
1918 break;
1919
1920 case 1:
1921 /* Configure Own Address 1 */
1922 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1923 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1924 if (slave->flags & I2C_CLIENT_TEN) {
1925 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1926 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1927 } else {
1928 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1929 }
1930 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1931 i2c_dev->slave[id] = slave;
1932 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1933 break;
1934
1935 case 2:
1936 /* Configure Own Address 2 */
1937 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1938 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1939 if (slave->flags & I2C_CLIENT_TEN) {
1940 ret = -EOPNOTSUPP;
1941 goto pm_free;
1942 }
1943
1944 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1945 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1946 i2c_dev->slave[id] = slave;
1947 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1948 break;
1949
1950 default:
1951 dev_err(dev, "I2C slave id not supported\n");
1952 ret = -ENODEV;
1953 goto pm_free;
1954 }
1955
1956 /* Enable ACK */
1957 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1958
1959 /* Enable Address match interrupt, error interrupt and enable I2C */
1960 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1961 STM32F7_I2C_CR1_PE;
1962 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1963
1964 ret = 0;
1965 pm_free:
1966 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1967 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1968
1969 pm_runtime_mark_last_busy(dev);
1970 pm_runtime_put_autosuspend(dev);
1971
1972 return ret;
1973 }
1974
stm32f7_i2c_unreg_slave(struct i2c_client * slave)1975 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1976 {
1977 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1978 void __iomem *base = i2c_dev->base;
1979 u32 mask;
1980 int id, ret;
1981
1982 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1983 if (ret)
1984 return ret;
1985
1986 WARN_ON(!i2c_dev->slave[id]);
1987
1988 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1989 if (ret < 0)
1990 return ret;
1991
1992 if (id == 1) {
1993 mask = STM32F7_I2C_OAR1_OA1EN;
1994 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1995 } else if (id == 2) {
1996 mask = STM32F7_I2C_OAR2_OA2EN;
1997 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1998 }
1999
2000 i2c_dev->slave[id] = NULL;
2001
2002 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2003 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
2004 stm32f7_i2c_enable_wakeup(i2c_dev, false);
2005 }
2006
2007 pm_runtime_mark_last_busy(i2c_dev->dev);
2008 pm_runtime_put_autosuspend(i2c_dev->dev);
2009
2010 return 0;
2011 }
2012
stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev * i2c_dev,bool enable)2013 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
2014 bool enable)
2015 {
2016 int ret = 0;
2017
2018 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
2019 (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap)))
2020 /* Optional */
2021 return 0;
2022
2023 if (i2c_dev->setup.fmp_cr1_bit) {
2024 if (enable)
2025 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2026 else
2027 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2028 } else {
2029 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
2030 ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg,
2031 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0);
2032 else
2033 ret = regmap_write(i2c_dev->regmap,
2034 enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg,
2035 i2c_dev->fmp_mask);
2036 }
2037
2038 return ret;
2039 }
2040
stm32f7_i2c_setup_fm_plus_bits(struct platform_device * pdev,struct stm32f7_i2c_dev * i2c_dev)2041 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
2042 struct stm32f7_i2c_dev *i2c_dev)
2043 {
2044 struct device_node *np = pdev->dev.of_node;
2045 int ret;
2046
2047 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
2048 if (IS_ERR(i2c_dev->regmap))
2049 /* Optional */
2050 return 0;
2051
2052 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2053 &i2c_dev->fmp_sreg);
2054 if (ret)
2055 return ret;
2056
2057 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2058 i2c_dev->setup.fmp_clr_offset;
2059
2060 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2061 &i2c_dev->fmp_mask);
2062 }
2063
stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2064 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2065 {
2066 struct i2c_adapter *adap = &i2c_dev->adap;
2067 void __iomem *base = i2c_dev->base;
2068 struct i2c_client *client;
2069
2070 client = i2c_new_slave_host_notify_device(adap);
2071 if (IS_ERR(client))
2072 return PTR_ERR(client);
2073
2074 i2c_dev->host_notify_client = client;
2075
2076 /* Enable SMBus Host address */
2077 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2078
2079 return 0;
2080 }
2081
stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2082 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2083 {
2084 void __iomem *base = i2c_dev->base;
2085
2086 if (i2c_dev->host_notify_client) {
2087 /* Disable SMBus Host address */
2088 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2089 STM32F7_I2C_CR1_SMBHEN);
2090 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2091 }
2092 }
2093
stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2094 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2095 {
2096 struct stm32f7_i2c_alert *alert;
2097 struct i2c_adapter *adap = &i2c_dev->adap;
2098 struct device *dev = i2c_dev->dev;
2099 void __iomem *base = i2c_dev->base;
2100
2101 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2102 if (!alert)
2103 return -ENOMEM;
2104
2105 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2106 if (IS_ERR(alert->ara))
2107 return PTR_ERR(alert->ara);
2108
2109 i2c_dev->alert = alert;
2110
2111 /* Enable SMBus Alert */
2112 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2113
2114 return 0;
2115 }
2116
stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2117 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2118 {
2119 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2120 void __iomem *base = i2c_dev->base;
2121
2122 if (alert) {
2123 /* Disable SMBus Alert */
2124 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2125 STM32F7_I2C_CR1_ALERTEN);
2126 i2c_unregister_device(alert->ara);
2127 }
2128 }
2129
stm32f7_i2c_func(struct i2c_adapter * adap)2130 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2131 {
2132 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2133
2134 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2135 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2136 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2137 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2138 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2139 I2C_FUNC_SMBUS_I2C_BLOCK;
2140
2141 if (i2c_dev->smbus_mode)
2142 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2143
2144 return func;
2145 }
2146
2147 static const struct i2c_algorithm stm32f7_i2c_algo = {
2148 .xfer = stm32f7_i2c_xfer,
2149 .xfer_atomic = stm32f7_i2c_xfer_atomic,
2150 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2151 .functionality = stm32f7_i2c_func,
2152 .reg_slave = stm32f7_i2c_reg_slave,
2153 .unreg_slave = stm32f7_i2c_unreg_slave,
2154 };
2155
stm32f7_i2c_probe(struct platform_device * pdev)2156 static int stm32f7_i2c_probe(struct platform_device *pdev)
2157 {
2158 struct stm32f7_i2c_dev *i2c_dev;
2159 const struct stm32f7_i2c_setup *setup;
2160 struct resource *res;
2161 struct i2c_adapter *adap;
2162 struct reset_control *rst;
2163 dma_addr_t phy_addr;
2164 int irq_error, irq_event, ret;
2165
2166 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2167 if (!i2c_dev)
2168 return -ENOMEM;
2169
2170 setup = of_device_get_match_data(&pdev->dev);
2171 if (!setup) {
2172 dev_err(&pdev->dev, "Can't get device data\n");
2173 return -ENODEV;
2174 }
2175 i2c_dev->setup = *setup;
2176
2177 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2178 if (IS_ERR(i2c_dev->base))
2179 return PTR_ERR(i2c_dev->base);
2180 phy_addr = (dma_addr_t)res->start;
2181
2182 irq_event = platform_get_irq(pdev, 0);
2183 if (irq_event < 0)
2184 return irq_event;
2185
2186 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2187 "wakeup-source");
2188
2189 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2190 if (IS_ERR(i2c_dev->clk))
2191 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2192 "Failed to enable controller clock\n");
2193
2194 rst = devm_reset_control_get(&pdev->dev, NULL);
2195 if (IS_ERR(rst))
2196 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
2197 "Error: Missing reset ctrl\n");
2198
2199 reset_control_assert(rst);
2200 udelay(2);
2201 reset_control_deassert(rst);
2202
2203 i2c_dev->dev = &pdev->dev;
2204
2205 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2206 stm32f7_i2c_isr_event,
2207 stm32f7_i2c_isr_event_thread,
2208 IRQF_ONESHOT,
2209 pdev->name, i2c_dev);
2210 if (ret)
2211 return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n");
2212
2213 if (!i2c_dev->setup.single_it_line) {
2214 irq_error = platform_get_irq(pdev, 1);
2215 if (irq_error < 0)
2216 return irq_error;
2217
2218 ret = devm_request_threaded_irq(&pdev->dev, irq_error,
2219 NULL,
2220 stm32f7_i2c_isr_error_thread,
2221 IRQF_ONESHOT,
2222 pdev->name, i2c_dev);
2223 if (ret)
2224 return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n");
2225 }
2226
2227 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2228 if (ret)
2229 return ret;
2230
2231 /* Setup Fast mode plus if necessary */
2232 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2233 if (!i2c_dev->setup.fmp_cr1_bit) {
2234 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2235 if (ret)
2236 return ret;
2237 }
2238
2239 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2240 if (ret)
2241 return ret;
2242 }
2243
2244 adap = &i2c_dev->adap;
2245 i2c_set_adapdata(adap, i2c_dev);
2246 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2247 &res->start);
2248 adap->owner = THIS_MODULE;
2249 adap->timeout = 2 * HZ;
2250 adap->retries = 3;
2251 adap->algo = &stm32f7_i2c_algo;
2252 adap->dev.parent = &pdev->dev;
2253 adap->dev.of_node = pdev->dev.of_node;
2254
2255 init_completion(&i2c_dev->complete);
2256
2257 /* Init DMA config if supported */
2258 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2259 STM32F7_I2C_TXDR,
2260 STM32F7_I2C_RXDR);
2261 if (IS_ERR(i2c_dev->dma)) {
2262 ret = PTR_ERR(i2c_dev->dma);
2263 /* DMA support is optional, only report other errors */
2264 if (ret != -ENODEV)
2265 goto fmp_clear;
2266 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2267 i2c_dev->dma = NULL;
2268 }
2269
2270 if (i2c_dev->wakeup_src) {
2271 device_set_wakeup_capable(i2c_dev->dev, true);
2272
2273 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2274 if (ret) {
2275 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2276 goto clr_wakeup_capable;
2277 }
2278 }
2279
2280 platform_set_drvdata(pdev, i2c_dev);
2281
2282 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2283 STM32F7_AUTOSUSPEND_DELAY);
2284 pm_runtime_use_autosuspend(i2c_dev->dev);
2285 pm_runtime_set_active(i2c_dev->dev);
2286 pm_runtime_enable(i2c_dev->dev);
2287
2288 pm_runtime_get_noresume(&pdev->dev);
2289
2290 stm32f7_i2c_hw_config(i2c_dev);
2291
2292 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2293
2294 ret = i2c_add_adapter(adap);
2295 if (ret)
2296 goto pm_disable;
2297
2298 if (i2c_dev->smbus_mode) {
2299 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2300 if (ret) {
2301 dev_err(i2c_dev->dev,
2302 "failed to enable SMBus Host-Notify protocol (%d)\n",
2303 ret);
2304 goto i2c_adapter_remove;
2305 }
2306 }
2307
2308 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2309 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2310 if (ret) {
2311 dev_err(i2c_dev->dev,
2312 "failed to enable SMBus alert protocol (%d)\n",
2313 ret);
2314 goto i2c_disable_smbus_host;
2315 }
2316 }
2317
2318 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2319
2320 pm_runtime_mark_last_busy(i2c_dev->dev);
2321 pm_runtime_put_autosuspend(i2c_dev->dev);
2322
2323 return 0;
2324
2325 i2c_disable_smbus_host:
2326 stm32f7_i2c_disable_smbus_host(i2c_dev);
2327
2328 i2c_adapter_remove:
2329 i2c_del_adapter(adap);
2330
2331 pm_disable:
2332 pm_runtime_put_noidle(i2c_dev->dev);
2333 pm_runtime_disable(i2c_dev->dev);
2334 pm_runtime_set_suspended(i2c_dev->dev);
2335 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2336
2337 if (i2c_dev->wakeup_src)
2338 dev_pm_clear_wake_irq(i2c_dev->dev);
2339
2340 clr_wakeup_capable:
2341 if (i2c_dev->wakeup_src)
2342 device_set_wakeup_capable(i2c_dev->dev, false);
2343
2344 if (i2c_dev->dma) {
2345 stm32_i2c_dma_free(i2c_dev->dma);
2346 i2c_dev->dma = NULL;
2347 }
2348
2349 fmp_clear:
2350 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2351
2352 return ret;
2353 }
2354
stm32f7_i2c_remove(struct platform_device * pdev)2355 static void stm32f7_i2c_remove(struct platform_device *pdev)
2356 {
2357 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2358
2359 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2360 stm32f7_i2c_disable_smbus_host(i2c_dev);
2361
2362 i2c_del_adapter(&i2c_dev->adap);
2363 pm_runtime_get_sync(i2c_dev->dev);
2364
2365 if (i2c_dev->wakeup_src) {
2366 dev_pm_clear_wake_irq(i2c_dev->dev);
2367 /*
2368 * enforce that wakeup is disabled and that the device
2369 * is marked as non wakeup capable
2370 */
2371 device_init_wakeup(i2c_dev->dev, false);
2372 }
2373
2374 pm_runtime_put_noidle(i2c_dev->dev);
2375 pm_runtime_disable(i2c_dev->dev);
2376 pm_runtime_set_suspended(i2c_dev->dev);
2377 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2378
2379 if (i2c_dev->dma) {
2380 stm32_i2c_dma_free(i2c_dev->dma);
2381 i2c_dev->dma = NULL;
2382 }
2383
2384 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2385 }
2386
stm32f7_i2c_runtime_suspend(struct device * dev)2387 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2388 {
2389 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2390
2391 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2392 clk_disable(i2c_dev->clk);
2393
2394 return 0;
2395 }
2396
stm32f7_i2c_runtime_resume(struct device * dev)2397 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2398 {
2399 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2400 int ret;
2401
2402 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2403 ret = clk_enable(i2c_dev->clk);
2404 if (ret) {
2405 dev_err(dev, "failed to enable clock\n");
2406 return ret;
2407 }
2408 }
2409
2410 return 0;
2411 }
2412
stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev * i2c_dev)2413 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2414 {
2415 int ret;
2416 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2417
2418 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2419 if (ret < 0)
2420 return ret;
2421
2422 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2423 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2424 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2425 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2426 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2427 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2428
2429 pm_runtime_put_sync(i2c_dev->dev);
2430
2431 return ret;
2432 }
2433
stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev * i2c_dev)2434 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2435 {
2436 u32 cr1;
2437 int ret;
2438 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2439
2440 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2441 if (ret < 0)
2442 return ret;
2443
2444 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2445 if (cr1 & STM32F7_I2C_CR1_PE)
2446 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2447 STM32F7_I2C_CR1_PE);
2448
2449 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2450 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2451 i2c_dev->base + STM32F7_I2C_CR1);
2452 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2453 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2454 STM32F7_I2C_CR1_PE);
2455 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2456 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2457 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2458 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2459
2460 pm_runtime_put_sync(i2c_dev->dev);
2461
2462 return ret;
2463 }
2464
stm32f7_i2c_suspend(struct device * dev)2465 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2466 {
2467 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2468 int ret;
2469
2470 i2c_mark_adapter_suspended(&i2c_dev->adap);
2471
2472 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2473 ret = stm32f7_i2c_regs_backup(i2c_dev);
2474 if (ret < 0) {
2475 i2c_mark_adapter_resumed(&i2c_dev->adap);
2476 return ret;
2477 }
2478
2479 pinctrl_pm_select_sleep_state(dev);
2480 pm_runtime_force_suspend(dev);
2481 }
2482
2483 return 0;
2484 }
2485
stm32f7_i2c_resume(struct device * dev)2486 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2487 {
2488 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2489 int ret;
2490
2491 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2492 ret = pm_runtime_force_resume(dev);
2493 if (ret < 0)
2494 return ret;
2495 pinctrl_pm_select_default_state(dev);
2496
2497 ret = stm32f7_i2c_regs_restore(i2c_dev);
2498 if (ret < 0)
2499 return ret;
2500 }
2501
2502 i2c_mark_adapter_resumed(&i2c_dev->adap);
2503
2504 return 0;
2505 }
2506
2507 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2508 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2509 stm32f7_i2c_runtime_resume, NULL)
2510 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2511 };
2512
2513 static const struct of_device_id stm32f7_i2c_match[] = {
2514 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2515 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2516 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2517 { .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup},
2518 {},
2519 };
2520 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2521
2522 static struct platform_driver stm32f7_i2c_driver = {
2523 .driver = {
2524 .name = "stm32f7-i2c",
2525 .of_match_table = stm32f7_i2c_match,
2526 .pm = &stm32f7_i2c_pm_ops,
2527 },
2528 .probe = stm32f7_i2c_probe,
2529 .remove = stm32f7_i2c_remove,
2530 };
2531
2532 module_platform_driver(stm32f7_i2c_driver);
2533
2534 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2535 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2536 MODULE_LICENSE("GPL v2");
2537