1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
37 #include <linux/string_choices.h>
38
39 #include "i2c-stm32.h"
40
41 /* STM32F7 I2C registers */
42 #define STM32F7_I2C_CR1 0x00
43 #define STM32F7_I2C_CR2 0x04
44 #define STM32F7_I2C_OAR1 0x08
45 #define STM32F7_I2C_OAR2 0x0C
46 #define STM32F7_I2C_PECR 0x20
47 #define STM32F7_I2C_TIMINGR 0x10
48 #define STM32F7_I2C_ISR 0x18
49 #define STM32F7_I2C_ICR 0x1C
50 #define STM32F7_I2C_RXDR 0x24
51 #define STM32F7_I2C_TXDR 0x28
52
53 /* STM32F7 I2C control 1 */
54 #define STM32_I2C_CR1_FMP BIT(24)
55 #define STM32F7_I2C_CR1_PECEN BIT(23)
56 #define STM32F7_I2C_CR1_ALERTEN BIT(22)
57 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
58 #define STM32F7_I2C_CR1_WUPEN BIT(18)
59 #define STM32F7_I2C_CR1_SBC BIT(16)
60 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
61 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
62 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
63 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
64 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
65 #define STM32F7_I2C_CR1_ERRIE BIT(7)
66 #define STM32F7_I2C_CR1_TCIE BIT(6)
67 #define STM32F7_I2C_CR1_STOPIE BIT(5)
68 #define STM32F7_I2C_CR1_NACKIE BIT(4)
69 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
70 #define STM32F7_I2C_CR1_RXIE BIT(2)
71 #define STM32F7_I2C_CR1_TXIE BIT(1)
72 #define STM32F7_I2C_CR1_PE BIT(0)
73 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
74 | STM32F7_I2C_CR1_TCIE \
75 | STM32F7_I2C_CR1_STOPIE \
76 | STM32F7_I2C_CR1_NACKIE \
77 | STM32F7_I2C_CR1_RXIE \
78 | STM32F7_I2C_CR1_TXIE)
79 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
80 | STM32F7_I2C_CR1_STOPIE \
81 | STM32F7_I2C_CR1_NACKIE \
82 | STM32F7_I2C_CR1_RXIE \
83 | STM32F7_I2C_CR1_TXIE)
84
85 /* STM32F7 I2C control 2 */
86 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
87 #define STM32F7_I2C_CR2_RELOAD BIT(24)
88 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
89 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
90 #define STM32F7_I2C_CR2_NACK BIT(15)
91 #define STM32F7_I2C_CR2_STOP BIT(14)
92 #define STM32F7_I2C_CR2_START BIT(13)
93 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
94 #define STM32F7_I2C_CR2_ADD10 BIT(11)
95 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
96 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
97 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
98 STM32F7_I2C_CR2_SADD10_MASK))
99 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
100 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
101
102 /* STM32F7 I2C Own Address 1 */
103 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
104 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
105 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
106 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
107 STM32F7_I2C_OAR1_OA1_10_MASK))
108 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
109 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
110 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
111 | STM32F7_I2C_OAR1_OA1_10_MASK \
112 | STM32F7_I2C_OAR1_OA1EN \
113 | STM32F7_I2C_OAR1_OA1MODE)
114
115 /* STM32F7 I2C Own Address 2 */
116 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
117 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
118 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
119 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
120 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
121 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
122 | STM32F7_I2C_OAR2_OA2_7_MASK \
123 | STM32F7_I2C_OAR2_OA2EN)
124
125 /* STM32F7 I2C Interrupt Status */
126 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
127 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
128 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
129 #define STM32F7_I2C_ISR_DIR BIT(16)
130 #define STM32F7_I2C_ISR_BUSY BIT(15)
131 #define STM32F7_I2C_ISR_ALERT BIT(13)
132 #define STM32F7_I2C_ISR_PECERR BIT(11)
133 #define STM32F7_I2C_ISR_ARLO BIT(9)
134 #define STM32F7_I2C_ISR_BERR BIT(8)
135 #define STM32F7_I2C_ISR_TCR BIT(7)
136 #define STM32F7_I2C_ISR_TC BIT(6)
137 #define STM32F7_I2C_ISR_STOPF BIT(5)
138 #define STM32F7_I2C_ISR_NACKF BIT(4)
139 #define STM32F7_I2C_ISR_ADDR BIT(3)
140 #define STM32F7_I2C_ISR_RXNE BIT(2)
141 #define STM32F7_I2C_ISR_TXIS BIT(1)
142 #define STM32F7_I2C_ISR_TXE BIT(0)
143
144 /* STM32F7 I2C Interrupt Clear */
145 #define STM32F7_I2C_ICR_ALERTCF BIT(13)
146 #define STM32F7_I2C_ICR_PECCF BIT(11)
147 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
148 #define STM32F7_I2C_ICR_BERRCF BIT(8)
149 #define STM32F7_I2C_ICR_STOPCF BIT(5)
150 #define STM32F7_I2C_ICR_NACKCF BIT(4)
151 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
152
153 /* STM32F7 I2C Timing */
154 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
155 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
156 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
157 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
158 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
159
160 #define STM32F7_I2C_MAX_LEN 0xff
161 #define STM32F7_I2C_DMA_LEN_MIN 0x16
162 enum {
163 STM32F7_SLAVE_HOSTNOTIFY,
164 STM32F7_SLAVE_7_10_BITS_ADDR,
165 STM32F7_SLAVE_7_BITS_ADDR,
166 STM32F7_I2C_MAX_SLAVE
167 };
168
169 #define STM32F7_I2C_DNF_DEFAULT 0
170 #define STM32F7_I2C_DNF_MAX 15
171
172 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
173 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
174
175 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
176 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
177
178 #define STM32F7_PRESC_MAX BIT(4)
179 #define STM32F7_SCLDEL_MAX BIT(4)
180 #define STM32F7_SDADEL_MAX BIT(4)
181 #define STM32F7_SCLH_MAX BIT(8)
182 #define STM32F7_SCLL_MAX BIT(8)
183
184 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
185
186 /**
187 * struct stm32f7_i2c_regs - i2c f7 registers backup
188 * @cr1: Control register 1
189 * @cr2: Control register 2
190 * @oar1: Own address 1 register
191 * @oar2: Own address 2 register
192 * @tmgr: Timing register
193 */
194 struct stm32f7_i2c_regs {
195 u32 cr1;
196 u32 cr2;
197 u32 oar1;
198 u32 oar2;
199 u32 tmgr;
200 };
201
202 /**
203 * struct stm32f7_i2c_spec - private i2c specification timing
204 * @rate: I2C bus speed (Hz)
205 * @fall_max: Max fall time of both SDA and SCL signals (ns)
206 * @rise_max: Max rise time of both SDA and SCL signals (ns)
207 * @hddat_min: Min data hold time (ns)
208 * @vddat_max: Max data valid time (ns)
209 * @sudat_min: Min data setup time (ns)
210 * @l_min: Min low period of the SCL clock (ns)
211 * @h_min: Min high period of the SCL clock (ns)
212 */
213 struct stm32f7_i2c_spec {
214 u32 rate;
215 u32 fall_max;
216 u32 rise_max;
217 u32 hddat_min;
218 u32 vddat_max;
219 u32 sudat_min;
220 u32 l_min;
221 u32 h_min;
222 };
223
224 /**
225 * struct stm32f7_i2c_setup - private I2C timing setup parameters
226 * @speed_freq: I2C speed frequency (Hz)
227 * @clock_src: I2C clock source frequency (Hz)
228 * @rise_time: Rise time (ns)
229 * @fall_time: Fall time (ns)
230 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
231 * @single_it_line: Only a single IT line is used for both events/errors
232 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1
233 */
234 struct stm32f7_i2c_setup {
235 u32 speed_freq;
236 u32 clock_src;
237 u32 rise_time;
238 u32 fall_time;
239 u32 fmp_clr_offset;
240 bool single_it_line;
241 bool fmp_cr1_bit;
242 };
243
244 /**
245 * struct stm32f7_i2c_timings - private I2C output parameters
246 * @node: List entry
247 * @presc: Prescaler value
248 * @scldel: Data setup time
249 * @sdadel: Data hold time
250 * @sclh: SCL high period (master mode)
251 * @scll: SCL low period (master mode)
252 */
253 struct stm32f7_i2c_timings {
254 struct list_head node;
255 u8 presc;
256 u8 scldel;
257 u8 sdadel;
258 u8 sclh;
259 u8 scll;
260 };
261
262 /**
263 * struct stm32f7_i2c_msg - client specific data
264 * @addr: 8-bit or 10-bit slave addr, including r/w bit
265 * @count: number of bytes to be transferred
266 * @buf: data buffer
267 * @result: result of the transfer
268 * @stop: last I2C msg to be sent, i.e. STOP to be generated
269 * @smbus: boolean to know if the I2C IP is used in SMBus mode
270 * @size: type of SMBus protocol
271 * @read_write: direction of SMBus protocol
272 * SMBus block read and SMBus block write - block read process call protocols
273 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
274 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
275 * This buffer has to be 32-bit aligned to be compliant with memory address
276 * register in DMA mode.
277 */
278 struct stm32f7_i2c_msg {
279 u16 addr;
280 u32 count;
281 u8 *buf;
282 int result;
283 bool stop;
284 bool smbus;
285 int size;
286 char read_write;
287 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
288 };
289
290 /**
291 * struct stm32f7_i2c_alert - SMBus alert specific data
292 * @setup: platform data for the smbus_alert i2c client
293 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
294 * Response Address
295 */
296 struct stm32f7_i2c_alert {
297 struct i2c_smbus_alert_setup setup;
298 struct i2c_client *ara;
299 };
300
301 /**
302 * struct stm32f7_i2c_dev - private data of the controller
303 * @adap: I2C adapter for this controller
304 * @dev: device for this controller
305 * @base: virtual memory area
306 * @complete: completion of I2C message
307 * @clk: hw i2c clock
308 * @bus_rate: I2C clock frequency of the controller
309 * @msg: Pointer to data to be written
310 * @msg_num: number of I2C messages to be executed
311 * @msg_id: message identifiant
312 * @f7_msg: customized i2c msg for driver usage
313 * @setup: I2C timing input setup
314 * @timing: I2C computed timings
315 * @slave: list of slave devices registered on the I2C bus
316 * @slave_running: slave device currently used
317 * @backup_regs: backup of i2c controller registers (for suspend/resume)
318 * @slave_dir: transfer direction for the current slave device
319 * @master_mode: boolean to know in which mode the I2C is running (master or
320 * slave)
321 * @dma: dma data
322 * @use_dma: boolean to know if dma is used in the current transfer
323 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
324 * @fmp_sreg: register address for setting Fast Mode Plus bits
325 * @fmp_creg: register address for clearing Fast Mode Plus bits
326 * @fmp_mask: mask for Fast Mode Plus bits in set register
327 * @wakeup_src: boolean to know if the device is a wakeup source
328 * @smbus_mode: states that the controller is configured in SMBus mode
329 * @host_notify_client: SMBus host-notify client
330 * @analog_filter: boolean to indicate enabling of the analog filter
331 * @dnf_dt: value of digital filter requested via dt
332 * @dnf: value of digital filter to apply
333 * @alert: SMBus alert specific data
334 * @atomic: boolean indicating that current transfer is atomic
335 */
336 struct stm32f7_i2c_dev {
337 struct i2c_adapter adap;
338 struct device *dev;
339 void __iomem *base;
340 struct completion complete;
341 struct clk *clk;
342 unsigned int bus_rate;
343 struct i2c_msg *msg;
344 unsigned int msg_num;
345 unsigned int msg_id;
346 struct stm32f7_i2c_msg f7_msg;
347 struct stm32f7_i2c_setup setup;
348 struct stm32f7_i2c_timings timing;
349 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
350 struct i2c_client *slave_running;
351 struct stm32f7_i2c_regs backup_regs;
352 u32 slave_dir;
353 bool master_mode;
354 struct stm32_i2c_dma *dma;
355 bool use_dma;
356 struct regmap *regmap;
357 u32 fmp_sreg;
358 u32 fmp_creg;
359 u32 fmp_mask;
360 bool wakeup_src;
361 bool smbus_mode;
362 struct i2c_client *host_notify_client;
363 bool analog_filter;
364 u32 dnf_dt;
365 u32 dnf;
366 struct stm32f7_i2c_alert *alert;
367 bool atomic;
368 };
369
370 /*
371 * All these values are coming from I2C Specification, Version 6.0, 4th of
372 * April 2014.
373 *
374 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
375 * and Fast-mode Plus I2C-bus devices
376 */
377 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
378 {
379 .rate = I2C_MAX_STANDARD_MODE_FREQ,
380 .fall_max = 300,
381 .rise_max = 1000,
382 .hddat_min = 0,
383 .vddat_max = 3450,
384 .sudat_min = 250,
385 .l_min = 4700,
386 .h_min = 4000,
387 },
388 {
389 .rate = I2C_MAX_FAST_MODE_FREQ,
390 .fall_max = 300,
391 .rise_max = 300,
392 .hddat_min = 0,
393 .vddat_max = 900,
394 .sudat_min = 100,
395 .l_min = 1300,
396 .h_min = 600,
397 },
398 {
399 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
400 .fall_max = 100,
401 .rise_max = 120,
402 .hddat_min = 0,
403 .vddat_max = 450,
404 .sudat_min = 50,
405 .l_min = 500,
406 .h_min = 260,
407 },
408 };
409
410 static const struct stm32f7_i2c_setup stm32f7_setup = {
411 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
412 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
413 };
414
415 static const struct stm32f7_i2c_setup stm32mp15_setup = {
416 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
417 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
418 .fmp_clr_offset = 0x40,
419 };
420
421 static const struct stm32f7_i2c_setup stm32mp13_setup = {
422 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
423 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
424 .fmp_clr_offset = 0x4,
425 };
426
427 static const struct stm32f7_i2c_setup stm32mp25_setup = {
428 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
429 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
430 .single_it_line = true,
431 .fmp_cr1_bit = true,
432 };
433
stm32f7_i2c_set_bits(void __iomem * reg,u32 mask)434 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
435 {
436 writel_relaxed(readl_relaxed(reg) | mask, reg);
437 }
438
stm32f7_i2c_clr_bits(void __iomem * reg,u32 mask)439 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
440 {
441 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
442 }
443
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev * i2c_dev,u32 mask)444 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
445 {
446 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
447 }
448
stm32f7_get_specs(u32 rate)449 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
450 {
451 int i;
452
453 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
454 if (rate <= stm32f7_i2c_specs[i].rate)
455 return &stm32f7_i2c_specs[i];
456
457 return ERR_PTR(-EINVAL);
458 }
459
460 #define RATE_MIN(rate) ((rate) * 8 / 10)
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup,struct stm32f7_i2c_timings * output)461 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
462 struct stm32f7_i2c_setup *setup,
463 struct stm32f7_i2c_timings *output)
464 {
465 struct stm32f7_i2c_spec *specs;
466 u32 p_prev = STM32F7_PRESC_MAX;
467 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
468 setup->clock_src);
469 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
470 setup->speed_freq);
471 u32 clk_error_prev = i2cbus;
472 u32 tsync;
473 u32 af_delay_min, af_delay_max;
474 u32 dnf_delay;
475 u32 clk_min, clk_max;
476 int sdadel_min, sdadel_max;
477 int scldel_min;
478 struct stm32f7_i2c_timings *v, *_v, *s;
479 struct list_head solutions;
480 u16 p, l, a, h;
481 int ret = 0;
482
483 specs = stm32f7_get_specs(setup->speed_freq);
484 if (specs == ERR_PTR(-EINVAL)) {
485 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
486 setup->speed_freq);
487 return -EINVAL;
488 }
489
490 if ((setup->rise_time > specs->rise_max) ||
491 (setup->fall_time > specs->fall_max)) {
492 dev_err(i2c_dev->dev,
493 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
494 setup->rise_time, specs->rise_max,
495 setup->fall_time, specs->fall_max);
496 return -EINVAL;
497 }
498
499 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
500 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
501 dev_err(i2c_dev->dev,
502 "DNF out of bound %d/%d\n",
503 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
504 return -EINVAL;
505 }
506
507 /* Analog and Digital Filters */
508 af_delay_min =
509 (i2c_dev->analog_filter ?
510 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
511 af_delay_max =
512 (i2c_dev->analog_filter ?
513 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
514 dnf_delay = i2c_dev->dnf * i2cclk;
515
516 sdadel_min = specs->hddat_min + setup->fall_time -
517 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
518
519 sdadel_max = specs->vddat_max - setup->rise_time -
520 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
521
522 scldel_min = setup->rise_time + specs->sudat_min;
523
524 if (sdadel_min < 0)
525 sdadel_min = 0;
526 if (sdadel_max < 0)
527 sdadel_max = 0;
528
529 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
530 sdadel_min, sdadel_max, scldel_min);
531
532 INIT_LIST_HEAD(&solutions);
533 /* Compute possible values for PRESC, SCLDEL and SDADEL */
534 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
535 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
536 u32 scldel = (l + 1) * (p + 1) * i2cclk;
537
538 if (scldel < scldel_min)
539 continue;
540
541 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
542 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
543
544 if (((sdadel >= sdadel_min) &&
545 (sdadel <= sdadel_max)) &&
546 (p != p_prev)) {
547 v = kmalloc(sizeof(*v), GFP_KERNEL);
548 if (!v) {
549 ret = -ENOMEM;
550 goto exit;
551 }
552
553 v->presc = p;
554 v->scldel = l;
555 v->sdadel = a;
556 p_prev = p;
557
558 list_add_tail(&v->node,
559 &solutions);
560 break;
561 }
562 }
563
564 if (p_prev == p)
565 break;
566 }
567 }
568
569 if (list_empty(&solutions)) {
570 dev_err(i2c_dev->dev, "no Prescaler solution\n");
571 ret = -EPERM;
572 goto exit;
573 }
574
575 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
576 s = NULL;
577 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
578 clk_min = NSEC_PER_SEC / setup->speed_freq;
579
580 /*
581 * Among Prescaler possibilities discovered above figures out SCL Low
582 * and High Period. Provided:
583 * - SCL Low Period has to be higher than SCL Clock Low Period
584 * defined by I2C Specification. I2C Clock has to be lower than
585 * (SCL Low Period - Analog/Digital filters) / 4.
586 * - SCL High Period has to be lower than SCL Clock High Period
587 * defined by I2C Specification
588 * - I2C Clock has to be lower than SCL High Period
589 */
590 list_for_each_entry(v, &solutions, node) {
591 u32 prescaler = (v->presc + 1) * i2cclk;
592
593 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
594 u32 tscl_l = (l + 1) * prescaler + tsync;
595
596 if ((tscl_l < specs->l_min) ||
597 (i2cclk >=
598 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
599 continue;
600 }
601
602 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
603 u32 tscl_h = (h + 1) * prescaler + tsync;
604 u32 tscl = tscl_l + tscl_h +
605 setup->rise_time + setup->fall_time;
606
607 if ((tscl >= clk_min) && (tscl <= clk_max) &&
608 (tscl_h >= specs->h_min) &&
609 (i2cclk < tscl_h)) {
610 int clk_error = tscl - i2cbus;
611
612 if (clk_error < 0)
613 clk_error = -clk_error;
614
615 if (clk_error < clk_error_prev) {
616 clk_error_prev = clk_error;
617 v->scll = l;
618 v->sclh = h;
619 s = v;
620 }
621 }
622 }
623 }
624 }
625
626 if (!s) {
627 dev_err(i2c_dev->dev, "no solution at all\n");
628 ret = -EPERM;
629 goto exit;
630 }
631
632 output->presc = s->presc;
633 output->scldel = s->scldel;
634 output->sdadel = s->sdadel;
635 output->scll = s->scll;
636 output->sclh = s->sclh;
637
638 dev_dbg(i2c_dev->dev,
639 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
640 output->presc,
641 output->scldel, output->sdadel,
642 output->scll, output->sclh);
643
644 exit:
645 /* Release list and memory */
646 list_for_each_entry_safe(v, _v, &solutions, node) {
647 list_del(&v->node);
648 kfree(v);
649 }
650
651 return ret;
652 }
653
stm32f7_get_lower_rate(u32 rate)654 static u32 stm32f7_get_lower_rate(u32 rate)
655 {
656 int i = ARRAY_SIZE(stm32f7_i2c_specs);
657
658 while (--i)
659 if (stm32f7_i2c_specs[i].rate < rate)
660 break;
661
662 return stm32f7_i2c_specs[i].rate;
663 }
664
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup)665 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
666 struct stm32f7_i2c_setup *setup)
667 {
668 struct i2c_timings timings, *t = &timings;
669 int ret = 0;
670
671 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
672 t->scl_rise_ns = i2c_dev->setup.rise_time;
673 t->scl_fall_ns = i2c_dev->setup.fall_time;
674
675 i2c_parse_fw_timings(i2c_dev->dev, t, false);
676
677 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
678 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
679 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
680 return -EINVAL;
681 }
682
683 setup->speed_freq = t->bus_freq_hz;
684 i2c_dev->setup.rise_time = t->scl_rise_ns;
685 i2c_dev->setup.fall_time = t->scl_fall_ns;
686 i2c_dev->dnf_dt = t->digital_filter_width_ns;
687 setup->clock_src = clk_get_rate(i2c_dev->clk);
688
689 if (!setup->clock_src) {
690 dev_err(i2c_dev->dev, "clock rate is 0\n");
691 return -EINVAL;
692 }
693
694 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
695 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
696
697 do {
698 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
699 &i2c_dev->timing);
700 if (ret) {
701 dev_err(i2c_dev->dev,
702 "failed to compute I2C timings.\n");
703 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
704 break;
705 setup->speed_freq =
706 stm32f7_get_lower_rate(setup->speed_freq);
707 dev_warn(i2c_dev->dev,
708 "downgrade I2C Speed Freq to (%i)\n",
709 setup->speed_freq);
710 }
711 } while (ret);
712
713 if (ret) {
714 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
715 return ret;
716 }
717
718 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
719 "i2c-analog-filter");
720
721 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
722 setup->speed_freq, setup->clock_src);
723 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
724 setup->rise_time, setup->fall_time);
725 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
726 str_on_off(i2c_dev->analog_filter), i2c_dev->dnf);
727
728 i2c_dev->bus_rate = setup->speed_freq;
729
730 return 0;
731 }
732
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev * i2c_dev)733 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
734 {
735 void __iomem *base = i2c_dev->base;
736 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
737
738 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
739 }
740
stm32f7_i2c_dma_callback(void * arg)741 static void stm32f7_i2c_dma_callback(void *arg)
742 {
743 struct stm32f7_i2c_dev *i2c_dev = arg;
744 struct stm32_i2c_dma *dma = i2c_dev->dma;
745
746 stm32f7_i2c_disable_dma_req(i2c_dev);
747 dmaengine_terminate_async(dma->chan_using);
748 dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len,
749 dma->dma_data_dir);
750 complete(&dma->dma_complete);
751 }
752
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev * i2c_dev)753 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
754 {
755 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
756 u32 timing = 0;
757
758 /* Timing settings */
759 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
760 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
761 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
762 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
763 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
764 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
765
766 /* Configure the Analog Filter */
767 if (i2c_dev->analog_filter)
768 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
769 STM32F7_I2C_CR1_ANFOFF);
770 else
771 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
772 STM32F7_I2C_CR1_ANFOFF);
773
774 /* Program the Digital Filter */
775 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
776 STM32F7_I2C_CR1_DNF_MASK);
777 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
778 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
779
780 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
781 STM32F7_I2C_CR1_PE);
782 }
783
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev * i2c_dev)784 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
785 {
786 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
787 void __iomem *base = i2c_dev->base;
788
789 if (f7_msg->count) {
790 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
791 f7_msg->count--;
792 }
793 }
794
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev * i2c_dev)795 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
796 {
797 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
798 void __iomem *base = i2c_dev->base;
799
800 if (f7_msg->count) {
801 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
802 f7_msg->count--;
803 } else {
804 /* Flush RX buffer has no data is expected */
805 readb_relaxed(base + STM32F7_I2C_RXDR);
806 }
807 }
808
stm32f7_i2c_reload(struct stm32f7_i2c_dev * i2c_dev)809 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
810 {
811 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
812 u32 cr2;
813
814 if (i2c_dev->use_dma)
815 f7_msg->count -= STM32F7_I2C_MAX_LEN;
816
817 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
818
819 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
820 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
821 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
822 } else {
823 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
824 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
825 }
826
827 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
828 }
829
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev * i2c_dev)830 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
831 {
832 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
833 u32 cr2;
834 u8 *val;
835
836 /*
837 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
838 * data received inform us how many data will follow.
839 */
840 stm32f7_i2c_read_rx_data(i2c_dev);
841
842 /*
843 * Update NBYTES with the value read to continue the transfer
844 */
845 val = f7_msg->buf - sizeof(u8);
846 f7_msg->count = *val;
847 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
848 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
849 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
850 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
851 }
852
stm32f7_i2c_release_bus(struct i2c_adapter * i2c_adap)853 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
854 {
855 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
856
857 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
858 STM32F7_I2C_CR1_PE);
859
860 stm32f7_i2c_hw_config(i2c_dev);
861 }
862
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev * i2c_dev)863 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
864 {
865 u32 status;
866 int ret;
867
868 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
869 status,
870 !(status & STM32F7_I2C_ISR_BUSY),
871 10, 1000);
872 if (!ret)
873 return 0;
874
875 stm32f7_i2c_release_bus(&i2c_dev->adap);
876
877 return -EBUSY;
878 }
879
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,struct i2c_msg * msg)880 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
881 struct i2c_msg *msg)
882 {
883 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
884 void __iomem *base = i2c_dev->base;
885 u32 cr1, cr2;
886 int ret;
887
888 f7_msg->addr = msg->addr;
889 f7_msg->buf = msg->buf;
890 f7_msg->count = msg->len;
891 f7_msg->result = 0;
892 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
893
894 reinit_completion(&i2c_dev->complete);
895
896 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
897 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
898
899 /* Set transfer direction */
900 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
901 if (msg->flags & I2C_M_RD)
902 cr2 |= STM32F7_I2C_CR2_RD_WRN;
903
904 /* Set slave address */
905 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
906 if (msg->flags & I2C_M_TEN) {
907 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
908 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
909 cr2 |= STM32F7_I2C_CR2_ADD10;
910 } else {
911 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
912 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
913 }
914
915 /* Set nb bytes to transfer and reload if needed */
916 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
917 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
918 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
919 cr2 |= STM32F7_I2C_CR2_RELOAD;
920 } else {
921 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
922 }
923
924 /* Enable NACK, STOP, error and transfer complete interrupts */
925 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
926 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
927
928 /* Clear DMA req and TX/RX interrupt */
929 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
930 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
931
932 /* Configure DMA or enable RX/TX interrupt */
933 i2c_dev->use_dma = false;
934 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN
935 && !i2c_dev->atomic) {
936 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
937 msg->flags & I2C_M_RD,
938 f7_msg->count, f7_msg->buf,
939 stm32f7_i2c_dma_callback,
940 i2c_dev);
941 if (!ret)
942 i2c_dev->use_dma = true;
943 else
944 dev_warn(i2c_dev->dev, "can't use DMA\n");
945 }
946
947 if (!i2c_dev->use_dma) {
948 if (msg->flags & I2C_M_RD)
949 cr1 |= STM32F7_I2C_CR1_RXIE;
950 else
951 cr1 |= STM32F7_I2C_CR1_TXIE;
952 } else {
953 if (msg->flags & I2C_M_RD)
954 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
955 else
956 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
957 }
958
959 if (i2c_dev->atomic)
960 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */
961
962 /* Configure Start/Repeated Start */
963 cr2 |= STM32F7_I2C_CR2_START;
964
965 i2c_dev->master_mode = true;
966
967 /* Write configurations registers */
968 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
969 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
970 }
971
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,unsigned short flags,u8 command,union i2c_smbus_data * data)972 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
973 unsigned short flags, u8 command,
974 union i2c_smbus_data *data)
975 {
976 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
977 struct device *dev = i2c_dev->dev;
978 void __iomem *base = i2c_dev->base;
979 u32 cr1, cr2;
980 int i, ret;
981
982 f7_msg->result = 0;
983 reinit_completion(&i2c_dev->complete);
984
985 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
986 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
987
988 /* Set transfer direction */
989 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
990 if (f7_msg->read_write)
991 cr2 |= STM32F7_I2C_CR2_RD_WRN;
992
993 /* Set slave address */
994 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
995 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
996
997 f7_msg->smbus_buf[0] = command;
998 switch (f7_msg->size) {
999 case I2C_SMBUS_QUICK:
1000 f7_msg->stop = true;
1001 f7_msg->count = 0;
1002 break;
1003 case I2C_SMBUS_BYTE:
1004 f7_msg->stop = true;
1005 f7_msg->count = 1;
1006 break;
1007 case I2C_SMBUS_BYTE_DATA:
1008 if (f7_msg->read_write) {
1009 f7_msg->stop = false;
1010 f7_msg->count = 1;
1011 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1012 } else {
1013 f7_msg->stop = true;
1014 f7_msg->count = 2;
1015 f7_msg->smbus_buf[1] = data->byte;
1016 }
1017 break;
1018 case I2C_SMBUS_WORD_DATA:
1019 if (f7_msg->read_write) {
1020 f7_msg->stop = false;
1021 f7_msg->count = 1;
1022 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1023 } else {
1024 f7_msg->stop = true;
1025 f7_msg->count = 3;
1026 f7_msg->smbus_buf[1] = data->word & 0xff;
1027 f7_msg->smbus_buf[2] = data->word >> 8;
1028 }
1029 break;
1030 case I2C_SMBUS_BLOCK_DATA:
1031 if (f7_msg->read_write) {
1032 f7_msg->stop = false;
1033 f7_msg->count = 1;
1034 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1035 } else {
1036 f7_msg->stop = true;
1037 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1038 !data->block[0]) {
1039 dev_err(dev, "Invalid block write size %d\n",
1040 data->block[0]);
1041 return -EINVAL;
1042 }
1043 f7_msg->count = data->block[0] + 2;
1044 for (i = 1; i < f7_msg->count; i++)
1045 f7_msg->smbus_buf[i] = data->block[i - 1];
1046 }
1047 break;
1048 case I2C_SMBUS_PROC_CALL:
1049 f7_msg->stop = false;
1050 f7_msg->count = 3;
1051 f7_msg->smbus_buf[1] = data->word & 0xff;
1052 f7_msg->smbus_buf[2] = data->word >> 8;
1053 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1054 f7_msg->read_write = I2C_SMBUS_READ;
1055 break;
1056 case I2C_SMBUS_BLOCK_PROC_CALL:
1057 f7_msg->stop = false;
1058 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1059 dev_err(dev, "Invalid block write size %d\n",
1060 data->block[0]);
1061 return -EINVAL;
1062 }
1063 f7_msg->count = data->block[0] + 2;
1064 for (i = 1; i < f7_msg->count; i++)
1065 f7_msg->smbus_buf[i] = data->block[i - 1];
1066 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1067 f7_msg->read_write = I2C_SMBUS_READ;
1068 break;
1069 case I2C_SMBUS_I2C_BLOCK_DATA:
1070 /* Rely on emulated i2c transfer (through master_xfer) */
1071 return -EOPNOTSUPP;
1072 default:
1073 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1074 return -EOPNOTSUPP;
1075 }
1076
1077 f7_msg->buf = f7_msg->smbus_buf;
1078
1079 /* Configure PEC */
1080 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1081 cr1 |= STM32F7_I2C_CR1_PECEN;
1082 if (!f7_msg->read_write) {
1083 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1084 f7_msg->count++;
1085 }
1086 } else {
1087 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1088 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1089 }
1090
1091 /* Set number of bytes to be transferred */
1092 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1093 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1094
1095 /* Enable NACK, STOP, error and transfer complete interrupts */
1096 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1097 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1098
1099 /* Clear DMA req and TX/RX interrupt */
1100 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1101 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1102
1103 /* Configure DMA or enable RX/TX interrupt */
1104 i2c_dev->use_dma = false;
1105 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1106 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1107 cr2 & STM32F7_I2C_CR2_RD_WRN,
1108 f7_msg->count, f7_msg->buf,
1109 stm32f7_i2c_dma_callback,
1110 i2c_dev);
1111 if (!ret)
1112 i2c_dev->use_dma = true;
1113 else
1114 dev_warn(i2c_dev->dev, "can't use DMA\n");
1115 }
1116
1117 if (!i2c_dev->use_dma) {
1118 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1119 cr1 |= STM32F7_I2C_CR1_RXIE;
1120 else
1121 cr1 |= STM32F7_I2C_CR1_TXIE;
1122 } else {
1123 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1124 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1125 else
1126 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1127 }
1128
1129 /* Set Start bit */
1130 cr2 |= STM32F7_I2C_CR2_START;
1131
1132 i2c_dev->master_mode = true;
1133
1134 /* Write configurations registers */
1135 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1136 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1137
1138 return 0;
1139 }
1140
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev * i2c_dev)1141 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1142 {
1143 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1144 void __iomem *base = i2c_dev->base;
1145 u32 cr1, cr2;
1146 int ret;
1147
1148 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1149 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1150
1151 /* Set transfer direction */
1152 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1153
1154 switch (f7_msg->size) {
1155 case I2C_SMBUS_BYTE_DATA:
1156 f7_msg->count = 1;
1157 break;
1158 case I2C_SMBUS_WORD_DATA:
1159 case I2C_SMBUS_PROC_CALL:
1160 f7_msg->count = 2;
1161 break;
1162 case I2C_SMBUS_BLOCK_DATA:
1163 case I2C_SMBUS_BLOCK_PROC_CALL:
1164 f7_msg->count = 1;
1165 cr2 |= STM32F7_I2C_CR2_RELOAD;
1166 break;
1167 }
1168
1169 f7_msg->buf = f7_msg->smbus_buf;
1170 f7_msg->stop = true;
1171
1172 /* Add one byte for PEC if needed */
1173 if (cr1 & STM32F7_I2C_CR1_PECEN) {
1174 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1175 f7_msg->count++;
1176 }
1177
1178 /* Set number of bytes to be transferred */
1179 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1180 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1181
1182 /*
1183 * Configure RX/TX interrupt:
1184 */
1185 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1186 cr1 |= STM32F7_I2C_CR1_RXIE;
1187
1188 /*
1189 * Configure DMA or enable RX/TX interrupt:
1190 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1191 * dma as we don't know in advance how many data will be received
1192 */
1193 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1194 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1195
1196 i2c_dev->use_dma = false;
1197 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1198 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1199 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1200 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1201 cr2 & STM32F7_I2C_CR2_RD_WRN,
1202 f7_msg->count, f7_msg->buf,
1203 stm32f7_i2c_dma_callback,
1204 i2c_dev);
1205
1206 if (!ret)
1207 i2c_dev->use_dma = true;
1208 else
1209 dev_warn(i2c_dev->dev, "can't use DMA\n");
1210 }
1211
1212 if (!i2c_dev->use_dma)
1213 cr1 |= STM32F7_I2C_CR1_RXIE;
1214 else
1215 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1216
1217 /* Configure Repeated Start */
1218 cr2 |= STM32F7_I2C_CR2_START;
1219
1220 /* Write configurations registers */
1221 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1222 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1223 }
1224
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev * i2c_dev)1225 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1226 {
1227 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1228 u8 count, internal_pec, received_pec;
1229
1230 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1231
1232 switch (f7_msg->size) {
1233 case I2C_SMBUS_BYTE:
1234 case I2C_SMBUS_BYTE_DATA:
1235 received_pec = f7_msg->smbus_buf[1];
1236 break;
1237 case I2C_SMBUS_WORD_DATA:
1238 case I2C_SMBUS_PROC_CALL:
1239 received_pec = f7_msg->smbus_buf[2];
1240 break;
1241 case I2C_SMBUS_BLOCK_DATA:
1242 case I2C_SMBUS_BLOCK_PROC_CALL:
1243 count = f7_msg->smbus_buf[0];
1244 received_pec = f7_msg->smbus_buf[count];
1245 break;
1246 default:
1247 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1248 return -EINVAL;
1249 }
1250
1251 if (internal_pec != received_pec) {
1252 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1253 internal_pec, received_pec);
1254 return -EBADMSG;
1255 }
1256
1257 return 0;
1258 }
1259
stm32f7_i2c_is_addr_match(struct i2c_client * slave,u32 addcode)1260 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1261 {
1262 u32 addr;
1263
1264 if (!slave)
1265 return false;
1266
1267 if (slave->flags & I2C_CLIENT_TEN) {
1268 /*
1269 * For 10-bit addr, addcode = 11110XY with
1270 * X = Bit 9 of slave address
1271 * Y = Bit 8 of slave address
1272 */
1273 addr = slave->addr >> 8;
1274 addr |= 0x78;
1275 if (addr == addcode)
1276 return true;
1277 } else {
1278 addr = slave->addr & 0x7f;
1279 if (addr == addcode)
1280 return true;
1281 }
1282
1283 return false;
1284 }
1285
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev * i2c_dev)1286 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1287 {
1288 struct i2c_client *slave = i2c_dev->slave_running;
1289 void __iomem *base = i2c_dev->base;
1290 u32 mask;
1291 u8 value = 0;
1292
1293 if (i2c_dev->slave_dir) {
1294 /* Notify i2c slave that new read transfer is starting */
1295 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1296
1297 /*
1298 * Disable slave TX config in case of I2C combined message
1299 * (I2C Write followed by I2C Read)
1300 */
1301 mask = STM32F7_I2C_CR2_RELOAD;
1302 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1303 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1304 STM32F7_I2C_CR1_TCIE;
1305 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1306
1307 /* Enable TX empty, STOP, NACK interrupts */
1308 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1309 STM32F7_I2C_CR1_TXIE;
1310 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1311
1312 /* Write 1st data byte */
1313 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1314 } else {
1315 /* Notify i2c slave that new write transfer is starting */
1316 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1317
1318 /* Set reload mode to be able to ACK/NACK each received byte */
1319 mask = STM32F7_I2C_CR2_RELOAD;
1320 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1321
1322 /*
1323 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1324 * Set Slave Byte Control to be able to ACK/NACK each data
1325 * byte received
1326 */
1327 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1328 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1329 STM32F7_I2C_CR1_TCIE;
1330 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1331 }
1332 }
1333
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev * i2c_dev)1334 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1335 {
1336 void __iomem *base = i2c_dev->base;
1337 u32 isr, addcode, dir, mask;
1338 int i;
1339
1340 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1341 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1342 dir = isr & STM32F7_I2C_ISR_DIR;
1343
1344 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1345 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1346 i2c_dev->slave_running = i2c_dev->slave[i];
1347 i2c_dev->slave_dir = dir;
1348
1349 /* Start I2C slave processing */
1350 stm32f7_i2c_slave_start(i2c_dev);
1351
1352 /* Clear ADDR flag */
1353 mask = STM32F7_I2C_ICR_ADDRCF;
1354 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1355 break;
1356 }
1357 }
1358 }
1359
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1360 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1361 struct i2c_client *slave, int *id)
1362 {
1363 int i;
1364
1365 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1366 if (i2c_dev->slave[i] == slave) {
1367 *id = i;
1368 return 0;
1369 }
1370 }
1371
1372 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1373
1374 return -ENODEV;
1375 }
1376
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1377 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1378 struct i2c_client *slave, int *id)
1379 {
1380 struct device *dev = i2c_dev->dev;
1381 int i;
1382
1383 /*
1384 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1385 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1386 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1387 */
1388 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1389 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1390 goto fail;
1391 *id = STM32F7_SLAVE_HOSTNOTIFY;
1392 return 0;
1393 }
1394
1395 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1396 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1397 (slave->flags & I2C_CLIENT_TEN))
1398 continue;
1399 if (!i2c_dev->slave[i]) {
1400 *id = i;
1401 return 0;
1402 }
1403 }
1404
1405 fail:
1406 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1407
1408 return -EINVAL;
1409 }
1410
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev * i2c_dev)1411 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1412 {
1413 int i;
1414
1415 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1416 if (i2c_dev->slave[i])
1417 return true;
1418 }
1419
1420 return false;
1421 }
1422
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev * i2c_dev)1423 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1424 {
1425 int i, busy;
1426
1427 busy = 0;
1428 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1429 if (i2c_dev->slave[i])
1430 busy++;
1431 }
1432
1433 return i == busy;
1434 }
1435
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev * i2c_dev,u32 status)1436 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1437 {
1438 void __iomem *base = i2c_dev->base;
1439 u32 cr2, mask;
1440 u8 val;
1441 int ret;
1442
1443 /* Slave transmitter mode */
1444 if (status & STM32F7_I2C_ISR_TXIS) {
1445 i2c_slave_event(i2c_dev->slave_running,
1446 I2C_SLAVE_READ_PROCESSED,
1447 &val);
1448
1449 /* Write data byte */
1450 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1451 }
1452
1453 /* Transfer Complete Reload for Slave receiver mode */
1454 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1455 /*
1456 * Read data byte then set NBYTES to receive next byte or NACK
1457 * the current received byte
1458 */
1459 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1460 ret = i2c_slave_event(i2c_dev->slave_running,
1461 I2C_SLAVE_WRITE_RECEIVED,
1462 &val);
1463 if (!ret) {
1464 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1465 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1466 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1467 } else {
1468 mask = STM32F7_I2C_CR2_NACK;
1469 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1470 }
1471 }
1472
1473 /* NACK received */
1474 if (status & STM32F7_I2C_ISR_NACKF) {
1475 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1476 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1477 }
1478
1479 /* STOP received */
1480 if (status & STM32F7_I2C_ISR_STOPF) {
1481 /* Disable interrupts */
1482 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1483
1484 if (i2c_dev->slave_dir) {
1485 /*
1486 * Flush TX buffer in order to not used the byte in
1487 * TXDR for the next transfer
1488 */
1489 mask = STM32F7_I2C_ISR_TXE;
1490 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1491 }
1492
1493 /* Clear STOP flag */
1494 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1495
1496 /* Notify i2c slave that a STOP flag has been detected */
1497 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1498
1499 i2c_dev->slave_running = NULL;
1500 }
1501
1502 /* Address match received */
1503 if (status & STM32F7_I2C_ISR_ADDR)
1504 stm32f7_i2c_slave_addr(i2c_dev);
1505
1506 return IRQ_HANDLED;
1507 }
1508
stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev * i2c_dev,u32 status)1509 static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1510 {
1511 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1512 u16 addr = f7_msg->addr;
1513 void __iomem *base = i2c_dev->base;
1514 struct device *dev = i2c_dev->dev;
1515
1516 /* Bus error */
1517 if (status & STM32F7_I2C_ISR_BERR) {
1518 dev_err(dev, "Bus error accessing addr 0x%x\n", addr);
1519 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1520 stm32f7_i2c_release_bus(&i2c_dev->adap);
1521 f7_msg->result = -EIO;
1522 }
1523
1524 /* Arbitration loss */
1525 if (status & STM32F7_I2C_ISR_ARLO) {
1526 dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr);
1527 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1528 f7_msg->result = -EAGAIN;
1529 }
1530
1531 if (status & STM32F7_I2C_ISR_PECERR) {
1532 dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr);
1533 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1534 f7_msg->result = -EINVAL;
1535 }
1536
1537 if (status & STM32F7_I2C_ISR_ALERT) {
1538 dev_dbg(dev, "SMBus alert received\n");
1539 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1540 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1541 return IRQ_HANDLED;
1542 }
1543
1544 if (!i2c_dev->slave_running) {
1545 u32 mask;
1546 /* Disable interrupts */
1547 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1548 mask = STM32F7_I2C_XFER_IRQ_MASK;
1549 else
1550 mask = STM32F7_I2C_ALL_IRQ_MASK;
1551 stm32f7_i2c_disable_irq(i2c_dev, mask);
1552 }
1553
1554 /* Disable dma */
1555 if (i2c_dev->use_dma)
1556 stm32f7_i2c_dma_callback(i2c_dev);
1557
1558 i2c_dev->master_mode = false;
1559 complete(&i2c_dev->complete);
1560
1561 return IRQ_HANDLED;
1562 }
1563
1564 #define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\
1565 STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT)
stm32f7_i2c_isr_event(int irq,void * data)1566 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1567 {
1568 struct stm32f7_i2c_dev *i2c_dev = data;
1569 u32 status;
1570
1571 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1572
1573 /*
1574 * Check if the interrupt is for a slave device or related
1575 * to errors flags (in case of single it line mode)
1576 */
1577 if (!i2c_dev->master_mode ||
1578 (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)))
1579 return IRQ_WAKE_THREAD;
1580
1581 /* Tx empty */
1582 if (status & STM32F7_I2C_ISR_TXIS)
1583 stm32f7_i2c_write_tx_data(i2c_dev);
1584
1585 /* RX not empty */
1586 if (status & STM32F7_I2C_ISR_RXNE)
1587 stm32f7_i2c_read_rx_data(i2c_dev);
1588
1589 /* Wake up the thread if other flags are raised */
1590 if (status &
1591 (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF |
1592 STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR))
1593 return IRQ_WAKE_THREAD;
1594
1595 return IRQ_HANDLED;
1596 }
1597
stm32f7_i2c_isr_event_thread(int irq,void * data)1598 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1599 {
1600 struct stm32f7_i2c_dev *i2c_dev = data;
1601 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1602 void __iomem *base = i2c_dev->base;
1603 u32 status, mask;
1604 int ret;
1605
1606 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1607
1608 if (!i2c_dev->master_mode)
1609 return stm32f7_i2c_slave_isr_event(i2c_dev, status);
1610
1611 /* Handle errors in case of this handler is used for events/errors */
1612 if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))
1613 return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1614
1615 /* NACK received */
1616 if (status & STM32F7_I2C_ISR_NACKF) {
1617 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1618 __func__, f7_msg->addr);
1619 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1620 if (i2c_dev->use_dma)
1621 stm32f7_i2c_dma_callback(i2c_dev);
1622 f7_msg->result = -ENXIO;
1623 }
1624
1625 if (status & STM32F7_I2C_ISR_TCR) {
1626 if (f7_msg->smbus)
1627 stm32f7_i2c_smbus_reload(i2c_dev);
1628 else
1629 stm32f7_i2c_reload(i2c_dev);
1630 }
1631
1632 /* Transfer complete */
1633 if (status & STM32F7_I2C_ISR_TC) {
1634 /* Wait for dma transfer completion before sending next message */
1635 if (i2c_dev->use_dma && !f7_msg->result) {
1636 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1637 if (!ret) {
1638 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1639 stm32f7_i2c_dma_callback(i2c_dev);
1640 f7_msg->result = -ETIMEDOUT;
1641 }
1642 }
1643 if (f7_msg->stop) {
1644 mask = STM32F7_I2C_CR2_STOP;
1645 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1646 } else if (f7_msg->smbus) {
1647 stm32f7_i2c_smbus_rep_start(i2c_dev);
1648 } else {
1649 i2c_dev->msg_id++;
1650 i2c_dev->msg++;
1651 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1652 }
1653 }
1654
1655 /* STOP detection flag */
1656 if (status & STM32F7_I2C_ISR_STOPF) {
1657 /* Disable interrupts */
1658 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1659 mask = STM32F7_I2C_XFER_IRQ_MASK;
1660 else
1661 mask = STM32F7_I2C_ALL_IRQ_MASK;
1662 stm32f7_i2c_disable_irq(i2c_dev, mask);
1663
1664 /* Clear STOP flag */
1665 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1666
1667 i2c_dev->master_mode = false;
1668 complete(&i2c_dev->complete);
1669 }
1670
1671 return IRQ_HANDLED;
1672 }
1673
stm32f7_i2c_isr_error_thread(int irq,void * data)1674 static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data)
1675 {
1676 struct stm32f7_i2c_dev *i2c_dev = data;
1677 u32 status;
1678
1679 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1680
1681 return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1682 }
1683
stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev * i2c_dev)1684 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev)
1685 {
1686 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout);
1687
1688 while (ktime_compare(ktime_get(), timeout) < 0) {
1689 udelay(5);
1690 stm32f7_i2c_isr_event(0, i2c_dev);
1691
1692 if (completion_done(&i2c_dev->complete))
1693 return 1;
1694 }
1695
1696 return 0;
1697 }
1698
stm32f7_i2c_xfer_core(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1699 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap,
1700 struct i2c_msg msgs[], int num)
1701 {
1702 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1703 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1704 struct stm32_i2c_dma *dma = i2c_dev->dma;
1705 unsigned long time_left;
1706 int ret;
1707
1708 i2c_dev->msg = msgs;
1709 i2c_dev->msg_num = num;
1710 i2c_dev->msg_id = 0;
1711 f7_msg->smbus = false;
1712
1713 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1714 if (ret < 0)
1715 return ret;
1716
1717 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1718 if (ret)
1719 goto pm_free;
1720
1721 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1722
1723 if (!i2c_dev->atomic)
1724 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1725 i2c_dev->adap.timeout);
1726 else
1727 time_left = stm32f7_i2c_wait_polling(i2c_dev);
1728
1729 ret = f7_msg->result;
1730 if (ret) {
1731 if (i2c_dev->use_dma)
1732 dmaengine_synchronize(dma->chan_using);
1733
1734 /*
1735 * It is possible that some unsent data have already been
1736 * written into TXDR. To avoid sending old data in a
1737 * further transfer, flush TXDR in case of any error
1738 */
1739 writel_relaxed(STM32F7_I2C_ISR_TXE,
1740 i2c_dev->base + STM32F7_I2C_ISR);
1741 goto pm_free;
1742 }
1743
1744 if (!time_left) {
1745 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1746 i2c_dev->msg->addr);
1747 if (i2c_dev->use_dma)
1748 dmaengine_terminate_sync(dma->chan_using);
1749 stm32f7_i2c_wait_free_bus(i2c_dev);
1750 ret = -ETIMEDOUT;
1751 }
1752
1753 pm_free:
1754 pm_runtime_mark_last_busy(i2c_dev->dev);
1755 pm_runtime_put_autosuspend(i2c_dev->dev);
1756
1757 return (ret < 0) ? ret : num;
1758 }
1759
stm32f7_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1760 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1761 struct i2c_msg msgs[], int num)
1762 {
1763 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1764
1765 i2c_dev->atomic = false;
1766 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1767 }
1768
stm32f7_i2c_xfer_atomic(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1769 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap,
1770 struct i2c_msg msgs[], int num)
1771 {
1772 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1773
1774 i2c_dev->atomic = true;
1775 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1776 }
1777
stm32f7_i2c_smbus_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)1778 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1779 unsigned short flags, char read_write,
1780 u8 command, int size,
1781 union i2c_smbus_data *data)
1782 {
1783 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1784 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1785 struct stm32_i2c_dma *dma = i2c_dev->dma;
1786 struct device *dev = i2c_dev->dev;
1787 unsigned long time_left;
1788 int i, ret;
1789
1790 f7_msg->addr = addr;
1791 f7_msg->size = size;
1792 f7_msg->read_write = read_write;
1793 f7_msg->smbus = true;
1794
1795 ret = pm_runtime_resume_and_get(dev);
1796 if (ret < 0)
1797 return ret;
1798
1799 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1800 if (ret)
1801 goto pm_free;
1802
1803 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1804 if (ret)
1805 goto pm_free;
1806
1807 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1808 i2c_dev->adap.timeout);
1809 ret = f7_msg->result;
1810 if (ret) {
1811 if (i2c_dev->use_dma)
1812 dmaengine_synchronize(dma->chan_using);
1813
1814 /*
1815 * It is possible that some unsent data have already been
1816 * written into TXDR. To avoid sending old data in a
1817 * further transfer, flush TXDR in case of any error
1818 */
1819 writel_relaxed(STM32F7_I2C_ISR_TXE,
1820 i2c_dev->base + STM32F7_I2C_ISR);
1821 goto pm_free;
1822 }
1823
1824 if (!time_left) {
1825 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1826 if (i2c_dev->use_dma)
1827 dmaengine_terminate_sync(dma->chan_using);
1828 stm32f7_i2c_wait_free_bus(i2c_dev);
1829 ret = -ETIMEDOUT;
1830 goto pm_free;
1831 }
1832
1833 /* Check PEC */
1834 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1835 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1836 if (ret)
1837 goto pm_free;
1838 }
1839
1840 if (read_write && size != I2C_SMBUS_QUICK) {
1841 switch (size) {
1842 case I2C_SMBUS_BYTE:
1843 case I2C_SMBUS_BYTE_DATA:
1844 data->byte = f7_msg->smbus_buf[0];
1845 break;
1846 case I2C_SMBUS_WORD_DATA:
1847 case I2C_SMBUS_PROC_CALL:
1848 data->word = f7_msg->smbus_buf[0] |
1849 (f7_msg->smbus_buf[1] << 8);
1850 break;
1851 case I2C_SMBUS_BLOCK_DATA:
1852 case I2C_SMBUS_BLOCK_PROC_CALL:
1853 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1854 data->block[i] = f7_msg->smbus_buf[i];
1855 break;
1856 default:
1857 dev_err(dev, "Unsupported smbus transaction\n");
1858 ret = -EINVAL;
1859 }
1860 }
1861
1862 pm_free:
1863 pm_runtime_mark_last_busy(dev);
1864 pm_runtime_put_autosuspend(dev);
1865 return ret;
1866 }
1867
stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev * i2c_dev,bool enable)1868 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1869 bool enable)
1870 {
1871 void __iomem *base = i2c_dev->base;
1872 u32 mask = STM32F7_I2C_CR1_WUPEN;
1873
1874 if (!i2c_dev->wakeup_src)
1875 return;
1876
1877 if (enable) {
1878 device_set_wakeup_enable(i2c_dev->dev, true);
1879 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1880 } else {
1881 device_set_wakeup_enable(i2c_dev->dev, false);
1882 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1883 }
1884 }
1885
stm32f7_i2c_reg_slave(struct i2c_client * slave)1886 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1887 {
1888 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1889 void __iomem *base = i2c_dev->base;
1890 struct device *dev = i2c_dev->dev;
1891 u32 oar1, oar2, mask;
1892 int id, ret;
1893
1894 if (slave->flags & I2C_CLIENT_PEC) {
1895 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1896 return -EINVAL;
1897 }
1898
1899 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1900 dev_err(dev, "Too much slave registered\n");
1901 return -EBUSY;
1902 }
1903
1904 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1905 if (ret)
1906 return ret;
1907
1908 ret = pm_runtime_resume_and_get(dev);
1909 if (ret < 0)
1910 return ret;
1911
1912 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1913 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1914
1915 switch (id) {
1916 case 0:
1917 /* Slave SMBus Host */
1918 i2c_dev->slave[id] = slave;
1919 break;
1920
1921 case 1:
1922 /* Configure Own Address 1 */
1923 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1924 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1925 if (slave->flags & I2C_CLIENT_TEN) {
1926 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1927 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1928 } else {
1929 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1930 }
1931 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1932 i2c_dev->slave[id] = slave;
1933 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1934 break;
1935
1936 case 2:
1937 /* Configure Own Address 2 */
1938 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1939 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1940 if (slave->flags & I2C_CLIENT_TEN) {
1941 ret = -EOPNOTSUPP;
1942 goto pm_free;
1943 }
1944
1945 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1946 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1947 i2c_dev->slave[id] = slave;
1948 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1949 break;
1950
1951 default:
1952 dev_err(dev, "I2C slave id not supported\n");
1953 ret = -ENODEV;
1954 goto pm_free;
1955 }
1956
1957 /* Enable ACK */
1958 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1959
1960 /* Enable Address match interrupt, error interrupt and enable I2C */
1961 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1962 STM32F7_I2C_CR1_PE;
1963 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1964
1965 ret = 0;
1966 pm_free:
1967 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1968 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1969
1970 pm_runtime_mark_last_busy(dev);
1971 pm_runtime_put_autosuspend(dev);
1972
1973 return ret;
1974 }
1975
stm32f7_i2c_unreg_slave(struct i2c_client * slave)1976 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1977 {
1978 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1979 void __iomem *base = i2c_dev->base;
1980 u32 mask;
1981 int id, ret;
1982
1983 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1984 if (ret)
1985 return ret;
1986
1987 WARN_ON(!i2c_dev->slave[id]);
1988
1989 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1990 if (ret < 0)
1991 return ret;
1992
1993 if (id == 1) {
1994 mask = STM32F7_I2C_OAR1_OA1EN;
1995 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1996 } else if (id == 2) {
1997 mask = STM32F7_I2C_OAR2_OA2EN;
1998 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1999 }
2000
2001 i2c_dev->slave[id] = NULL;
2002
2003 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2004 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
2005 stm32f7_i2c_enable_wakeup(i2c_dev, false);
2006 }
2007
2008 pm_runtime_mark_last_busy(i2c_dev->dev);
2009 pm_runtime_put_autosuspend(i2c_dev->dev);
2010
2011 return 0;
2012 }
2013
stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev * i2c_dev,bool enable)2014 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
2015 bool enable)
2016 {
2017 int ret = 0;
2018
2019 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
2020 (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap)))
2021 /* Optional */
2022 return 0;
2023
2024 if (i2c_dev->setup.fmp_cr1_bit) {
2025 if (enable)
2026 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2027 else
2028 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2029 } else {
2030 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
2031 ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg,
2032 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0);
2033 else
2034 ret = regmap_write(i2c_dev->regmap,
2035 enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg,
2036 i2c_dev->fmp_mask);
2037 }
2038
2039 return ret;
2040 }
2041
stm32f7_i2c_setup_fm_plus_bits(struct platform_device * pdev,struct stm32f7_i2c_dev * i2c_dev)2042 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
2043 struct stm32f7_i2c_dev *i2c_dev)
2044 {
2045 struct device_node *np = pdev->dev.of_node;
2046 int ret;
2047
2048 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
2049 if (IS_ERR(i2c_dev->regmap))
2050 /* Optional */
2051 return 0;
2052
2053 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2054 &i2c_dev->fmp_sreg);
2055 if (ret)
2056 return ret;
2057
2058 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2059 i2c_dev->setup.fmp_clr_offset;
2060
2061 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2062 &i2c_dev->fmp_mask);
2063 }
2064
stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2065 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2066 {
2067 struct i2c_adapter *adap = &i2c_dev->adap;
2068 void __iomem *base = i2c_dev->base;
2069 struct i2c_client *client;
2070
2071 client = i2c_new_slave_host_notify_device(adap);
2072 if (IS_ERR(client))
2073 return PTR_ERR(client);
2074
2075 i2c_dev->host_notify_client = client;
2076
2077 /* Enable SMBus Host address */
2078 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2079
2080 return 0;
2081 }
2082
stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2083 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2084 {
2085 void __iomem *base = i2c_dev->base;
2086
2087 if (i2c_dev->host_notify_client) {
2088 /* Disable SMBus Host address */
2089 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2090 STM32F7_I2C_CR1_SMBHEN);
2091 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2092 }
2093 }
2094
stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2095 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2096 {
2097 struct stm32f7_i2c_alert *alert;
2098 struct i2c_adapter *adap = &i2c_dev->adap;
2099 struct device *dev = i2c_dev->dev;
2100 void __iomem *base = i2c_dev->base;
2101
2102 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2103 if (!alert)
2104 return -ENOMEM;
2105
2106 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2107 if (IS_ERR(alert->ara))
2108 return PTR_ERR(alert->ara);
2109
2110 i2c_dev->alert = alert;
2111
2112 /* Enable SMBus Alert */
2113 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2114
2115 return 0;
2116 }
2117
stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2118 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2119 {
2120 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2121 void __iomem *base = i2c_dev->base;
2122
2123 if (alert) {
2124 /* Disable SMBus Alert */
2125 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2126 STM32F7_I2C_CR1_ALERTEN);
2127 i2c_unregister_device(alert->ara);
2128 }
2129 }
2130
stm32f7_i2c_func(struct i2c_adapter * adap)2131 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2132 {
2133 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2134
2135 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2136 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2137 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2138 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2139 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2140 I2C_FUNC_SMBUS_I2C_BLOCK;
2141
2142 if (i2c_dev->smbus_mode)
2143 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2144
2145 return func;
2146 }
2147
2148 static const struct i2c_algorithm stm32f7_i2c_algo = {
2149 .xfer = stm32f7_i2c_xfer,
2150 .xfer_atomic = stm32f7_i2c_xfer_atomic,
2151 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2152 .functionality = stm32f7_i2c_func,
2153 .reg_slave = stm32f7_i2c_reg_slave,
2154 .unreg_slave = stm32f7_i2c_unreg_slave,
2155 };
2156
stm32f7_i2c_probe(struct platform_device * pdev)2157 static int stm32f7_i2c_probe(struct platform_device *pdev)
2158 {
2159 struct stm32f7_i2c_dev *i2c_dev;
2160 const struct stm32f7_i2c_setup *setup;
2161 struct resource *res;
2162 struct i2c_adapter *adap;
2163 struct reset_control *rst;
2164 dma_addr_t phy_addr;
2165 int irq_error, irq_event, ret;
2166
2167 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2168 if (!i2c_dev)
2169 return -ENOMEM;
2170
2171 setup = of_device_get_match_data(&pdev->dev);
2172 if (!setup) {
2173 dev_err(&pdev->dev, "Can't get device data\n");
2174 return -ENODEV;
2175 }
2176 i2c_dev->setup = *setup;
2177
2178 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2179 if (IS_ERR(i2c_dev->base))
2180 return PTR_ERR(i2c_dev->base);
2181 phy_addr = (dma_addr_t)res->start;
2182
2183 irq_event = platform_get_irq(pdev, 0);
2184 if (irq_event < 0)
2185 return irq_event;
2186
2187 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2188 "wakeup-source");
2189
2190 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2191 if (IS_ERR(i2c_dev->clk))
2192 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2193 "Failed to enable controller clock\n");
2194
2195 rst = devm_reset_control_get(&pdev->dev, NULL);
2196 if (IS_ERR(rst))
2197 return dev_err_probe(&pdev->dev, PTR_ERR(rst),
2198 "Error: Missing reset ctrl\n");
2199
2200 reset_control_assert(rst);
2201 udelay(2);
2202 reset_control_deassert(rst);
2203
2204 i2c_dev->dev = &pdev->dev;
2205
2206 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2207 stm32f7_i2c_isr_event,
2208 stm32f7_i2c_isr_event_thread,
2209 IRQF_ONESHOT,
2210 pdev->name, i2c_dev);
2211 if (ret)
2212 return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n");
2213
2214 if (!i2c_dev->setup.single_it_line) {
2215 irq_error = platform_get_irq(pdev, 1);
2216 if (irq_error < 0)
2217 return irq_error;
2218
2219 ret = devm_request_threaded_irq(&pdev->dev, irq_error,
2220 NULL,
2221 stm32f7_i2c_isr_error_thread,
2222 IRQF_ONESHOT,
2223 pdev->name, i2c_dev);
2224 if (ret)
2225 return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n");
2226 }
2227
2228 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2229 if (ret)
2230 return ret;
2231
2232 /* Setup Fast mode plus if necessary */
2233 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2234 if (!i2c_dev->setup.fmp_cr1_bit) {
2235 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2236 if (ret)
2237 return ret;
2238 }
2239
2240 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2241 if (ret)
2242 return ret;
2243 }
2244
2245 adap = &i2c_dev->adap;
2246 i2c_set_adapdata(adap, i2c_dev);
2247 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2248 &res->start);
2249 adap->owner = THIS_MODULE;
2250 adap->timeout = 2 * HZ;
2251 adap->retries = 3;
2252 adap->algo = &stm32f7_i2c_algo;
2253 adap->dev.parent = &pdev->dev;
2254 adap->dev.of_node = pdev->dev.of_node;
2255
2256 init_completion(&i2c_dev->complete);
2257
2258 /* Init DMA config if supported */
2259 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2260 STM32F7_I2C_TXDR,
2261 STM32F7_I2C_RXDR);
2262 if (IS_ERR(i2c_dev->dma)) {
2263 ret = PTR_ERR(i2c_dev->dma);
2264 /* DMA support is optional, only report other errors */
2265 if (ret != -ENODEV)
2266 goto fmp_clear;
2267 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2268 i2c_dev->dma = NULL;
2269 }
2270
2271 if (i2c_dev->wakeup_src) {
2272 device_set_wakeup_capable(i2c_dev->dev, true);
2273
2274 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2275 if (ret) {
2276 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2277 goto clr_wakeup_capable;
2278 }
2279 }
2280
2281 platform_set_drvdata(pdev, i2c_dev);
2282
2283 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2284 STM32F7_AUTOSUSPEND_DELAY);
2285 pm_runtime_use_autosuspend(i2c_dev->dev);
2286 pm_runtime_set_active(i2c_dev->dev);
2287 pm_runtime_enable(i2c_dev->dev);
2288
2289 pm_runtime_get_noresume(&pdev->dev);
2290
2291 stm32f7_i2c_hw_config(i2c_dev);
2292
2293 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2294
2295 ret = i2c_add_adapter(adap);
2296 if (ret)
2297 goto pm_disable;
2298
2299 if (i2c_dev->smbus_mode) {
2300 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2301 if (ret) {
2302 dev_err(i2c_dev->dev,
2303 "failed to enable SMBus Host-Notify protocol (%d)\n",
2304 ret);
2305 goto i2c_adapter_remove;
2306 }
2307 }
2308
2309 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2310 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2311 if (ret) {
2312 dev_err(i2c_dev->dev,
2313 "failed to enable SMBus alert protocol (%d)\n",
2314 ret);
2315 goto i2c_disable_smbus_host;
2316 }
2317 }
2318
2319 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2320
2321 pm_runtime_mark_last_busy(i2c_dev->dev);
2322 pm_runtime_put_autosuspend(i2c_dev->dev);
2323
2324 return 0;
2325
2326 i2c_disable_smbus_host:
2327 stm32f7_i2c_disable_smbus_host(i2c_dev);
2328
2329 i2c_adapter_remove:
2330 i2c_del_adapter(adap);
2331
2332 pm_disable:
2333 pm_runtime_put_noidle(i2c_dev->dev);
2334 pm_runtime_disable(i2c_dev->dev);
2335 pm_runtime_set_suspended(i2c_dev->dev);
2336 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2337
2338 if (i2c_dev->wakeup_src)
2339 dev_pm_clear_wake_irq(i2c_dev->dev);
2340
2341 clr_wakeup_capable:
2342 if (i2c_dev->wakeup_src)
2343 device_set_wakeup_capable(i2c_dev->dev, false);
2344
2345 if (i2c_dev->dma) {
2346 stm32_i2c_dma_free(i2c_dev->dma);
2347 i2c_dev->dma = NULL;
2348 }
2349
2350 fmp_clear:
2351 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2352
2353 return ret;
2354 }
2355
stm32f7_i2c_remove(struct platform_device * pdev)2356 static void stm32f7_i2c_remove(struct platform_device *pdev)
2357 {
2358 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2359
2360 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2361 stm32f7_i2c_disable_smbus_host(i2c_dev);
2362
2363 i2c_del_adapter(&i2c_dev->adap);
2364 pm_runtime_get_sync(i2c_dev->dev);
2365
2366 if (i2c_dev->wakeup_src) {
2367 dev_pm_clear_wake_irq(i2c_dev->dev);
2368 /*
2369 * enforce that wakeup is disabled and that the device
2370 * is marked as non wakeup capable
2371 */
2372 device_init_wakeup(i2c_dev->dev, false);
2373 }
2374
2375 pm_runtime_put_noidle(i2c_dev->dev);
2376 pm_runtime_disable(i2c_dev->dev);
2377 pm_runtime_set_suspended(i2c_dev->dev);
2378 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2379
2380 if (i2c_dev->dma) {
2381 stm32_i2c_dma_free(i2c_dev->dma);
2382 i2c_dev->dma = NULL;
2383 }
2384
2385 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2386 }
2387
stm32f7_i2c_runtime_suspend(struct device * dev)2388 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2389 {
2390 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2391
2392 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2393 clk_disable(i2c_dev->clk);
2394
2395 return 0;
2396 }
2397
stm32f7_i2c_runtime_resume(struct device * dev)2398 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2399 {
2400 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2401 int ret;
2402
2403 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2404 ret = clk_enable(i2c_dev->clk);
2405 if (ret) {
2406 dev_err(dev, "failed to enable clock\n");
2407 return ret;
2408 }
2409 }
2410
2411 return 0;
2412 }
2413
stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev * i2c_dev)2414 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2415 {
2416 int ret;
2417 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2418
2419 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2420 if (ret < 0)
2421 return ret;
2422
2423 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2424 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2425 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2426 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2427 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2428 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2429
2430 pm_runtime_put_sync(i2c_dev->dev);
2431
2432 return ret;
2433 }
2434
stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev * i2c_dev)2435 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2436 {
2437 u32 cr1;
2438 int ret;
2439 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2440
2441 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2442 if (ret < 0)
2443 return ret;
2444
2445 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2446 if (cr1 & STM32F7_I2C_CR1_PE)
2447 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2448 STM32F7_I2C_CR1_PE);
2449
2450 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2451 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2452 i2c_dev->base + STM32F7_I2C_CR1);
2453 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2454 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2455 STM32F7_I2C_CR1_PE);
2456 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2457 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2458 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2459 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2460
2461 pm_runtime_put_sync(i2c_dev->dev);
2462
2463 return ret;
2464 }
2465
stm32f7_i2c_suspend(struct device * dev)2466 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2467 {
2468 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2469 int ret;
2470
2471 i2c_mark_adapter_suspended(&i2c_dev->adap);
2472
2473 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2474 ret = stm32f7_i2c_regs_backup(i2c_dev);
2475 if (ret < 0) {
2476 i2c_mark_adapter_resumed(&i2c_dev->adap);
2477 return ret;
2478 }
2479
2480 pinctrl_pm_select_sleep_state(dev);
2481 pm_runtime_force_suspend(dev);
2482 }
2483
2484 return 0;
2485 }
2486
stm32f7_i2c_resume(struct device * dev)2487 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2488 {
2489 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2490 int ret;
2491
2492 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2493 ret = pm_runtime_force_resume(dev);
2494 if (ret < 0)
2495 return ret;
2496 pinctrl_pm_select_default_state(dev);
2497
2498 ret = stm32f7_i2c_regs_restore(i2c_dev);
2499 if (ret < 0)
2500 return ret;
2501 }
2502
2503 i2c_mark_adapter_resumed(&i2c_dev->adap);
2504
2505 return 0;
2506 }
2507
2508 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2509 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2510 stm32f7_i2c_runtime_resume, NULL)
2511 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2512 };
2513
2514 static const struct of_device_id stm32f7_i2c_match[] = {
2515 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2516 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2517 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2518 { .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup},
2519 {},
2520 };
2521 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2522
2523 static struct platform_driver stm32f7_i2c_driver = {
2524 .driver = {
2525 .name = "stm32f7-i2c",
2526 .of_match_table = stm32f7_i2c_match,
2527 .pm = &stm32f7_i2c_pm_ops,
2528 },
2529 .probe = stm32f7_i2c_probe,
2530 .remove = stm32f7_i2c_remove,
2531 };
2532
2533 module_platform_driver(stm32f7_i2c_driver);
2534
2535 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2536 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2537 MODULE_LICENSE("GPL v2");
2538