1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g047"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 audio_extal_clk: audio-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 audio_clkb: audio-b-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 /* This value must be overridden by the board */ 28 clock-frequency = <0>; 29 }; 30 31 audio_clkc: audio-c-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 /* This value must be overridden by the board */ 35 clock-frequency = <0>; 36 }; 37 38 /* 39 * The default cluster table is based on the assumption that the PLLCA55 clock 40 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 41 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 42 * clocked to 1.8GHz as well). The table below should be overridden in the board 43 * DTS based on the PLLCA55 clock frequency. 44 */ 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 48 opp-1700000000 { 49 opp-hz = /bits/ 64 <1700000000>; 50 opp-microvolt = <900000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-850000000 { 54 opp-hz = /bits/ 64 <850000000>; 55 opp-microvolt = <800000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-425000000 { 59 opp-hz = /bits/ 64 <425000000>; 60 opp-microvolt = <800000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-212500000 { 64 opp-hz = /bits/ 64 <212500000>; 65 opp-microvolt = <800000>; 66 clock-latency-ns = <300000>; 67 opp-suspend; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu0: cpu@0 { 76 compatible = "arm,cortex-a55"; 77 reg = <0>; 78 device_type = "cpu"; 79 next-level-cache = <&L3_CA55>; 80 enable-method = "psci"; 81 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; 82 #cooling-cells = <2>; 83 operating-points-v2 = <&cluster0_opp>; 84 }; 85 86 cpu1: cpu@100 { 87 compatible = "arm,cortex-a55"; 88 reg = <0x100>; 89 device_type = "cpu"; 90 next-level-cache = <&L3_CA55>; 91 enable-method = "psci"; 92 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; 93 #cooling-cells = <2>; 94 operating-points-v2 = <&cluster0_opp>; 95 }; 96 97 cpu2: cpu@200 { 98 compatible = "arm,cortex-a55"; 99 reg = <0x200>; 100 device_type = "cpu"; 101 next-level-cache = <&L3_CA55>; 102 enable-method = "psci"; 103 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; 104 #cooling-cells = <2>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu3: cpu@300 { 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 device_type = "cpu"; 112 next-level-cache = <&L3_CA55>; 113 enable-method = "psci"; 114 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; 115 #cooling-cells = <2>; 116 operating-points-v2 = <&cluster0_opp>; 117 }; 118 119 L3_CA55: cache-controller-0 { 120 compatible = "cache"; 121 cache-unified; 122 cache-size = <0x100000>; 123 cache-level = <3>; 124 }; 125 }; 126 127 gpu_opp_table: opp-table-1 { 128 compatible = "operating-points-v2"; 129 130 opp-630000000 { 131 opp-hz = /bits/ 64 <630000000>; 132 opp-microvolt = <800000>; 133 }; 134 135 opp-315000000 { 136 opp-hz = /bits/ 64 <315000000>; 137 opp-microvolt = <800000>; 138 }; 139 140 opp-157500000 { 141 opp-hz = /bits/ 64 <157500000>; 142 opp-microvolt = <800000>; 143 }; 144 145 opp-78750000 { 146 opp-hz = /bits/ 64 <78750000>; 147 opp-microvolt = <800000>; 148 }; 149 150 opp-19687500 { 151 opp-hz = /bits/ 64 <19687500>; 152 opp-microvolt = <800000>; 153 }; 154 }; 155 156 psci { 157 compatible = "arm,psci-1.0", "arm,psci-0.2"; 158 method = "smc"; 159 }; 160 161 qextal_clk: qextal-clk { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 /* This value must be overridden by the board */ 165 clock-frequency = <0>; 166 }; 167 168 rtxin_clk: rtxin-clk { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 /* This value must be overridden by the board */ 172 clock-frequency = <0>; 173 }; 174 175 soc: soc { 176 compatible = "simple-bus"; 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 icu: interrupt-controller@10400000 { 182 compatible = "renesas,r9a09g047-icu"; 183 reg = <0 0x10400000 0 0x10000>; 184 #interrupt-cells = <2>; 185 #address-cells = <0>; 186 interrupt-controller; 187 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 239 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 240 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 245 interrupt-names = "nmi", 246 "port_irq0", "port_irq1", "port_irq2", 247 "port_irq3", "port_irq4", "port_irq5", 248 "port_irq6", "port_irq7", "port_irq8", 249 "port_irq9", "port_irq10", "port_irq11", 250 "port_irq12", "port_irq13", "port_irq14", 251 "port_irq15", 252 "tint0", "tint1", "tint2", "tint3", 253 "tint4", "tint5", "tint6", "tint7", 254 "tint8", "tint9", "tint10", "tint11", 255 "tint12", "tint13", "tint14", "tint15", 256 "tint16", "tint17", "tint18", "tint19", 257 "tint20", "tint21", "tint22", "tint23", 258 "tint24", "tint25", "tint26", "tint27", 259 "tint28", "tint29", "tint30", "tint31", 260 "int-ca55-0", "int-ca55-1", 261 "int-ca55-2", "int-ca55-3", 262 "icu-error-ca55", 263 "gpt-u0-gtciada", "gpt-u0-gtciadb", 264 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 265 clocks = <&cpg CPG_MOD 0x5>; 266 power-domains = <&cpg>; 267 resets = <&cpg 0x36>; 268 }; 269 270 pinctrl: pinctrl@10410000 { 271 compatible = "renesas,r9a09g047-pinctrl"; 272 reg = <0 0x10410000 0 0x10000>; 273 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; 274 gpio-controller; 275 #gpio-cells = <2>; 276 gpio-ranges = <&pinctrl 0 0 232>; 277 #interrupt-cells = <2>; 278 interrupt-controller; 279 interrupt-parent = <&icu>; 280 power-domains = <&cpg>; 281 resets = <&cpg 0xa5>, <&cpg 0xa6>; 282 reset-names = "main", "error"; 283 }; 284 285 cpg: clock-controller@10420000 { 286 compatible = "renesas,r9a09g047-cpg"; 287 reg = <0 0x10420000 0 0x10000>; 288 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, 289 <&audio_clkb>, <&audio_clkc>; 290 clock-names = "audio_extal", "rtxin", "qextal", 291 "audio_clkb", "audio_clkc"; 292 #clock-cells = <2>; 293 #reset-cells = <1>; 294 #power-domain-cells = <0>; 295 }; 296 297 sys: system-controller@10430000 { 298 compatible = "renesas,r9a09g047-sys"; 299 reg = <0 0x10430000 0 0x10000>; 300 clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; 301 resets = <&cpg 0x30>; 302 }; 303 304 xspi: spi@11030000 { 305 compatible = "renesas,r9a09g047-xspi"; 306 reg = <0 0x11030000 0 0x10000>, 307 <0 0x20000000 0 0x10000000>; 308 reg-names = "regs", "dirmap"; 309 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 311 interrupt-names = "pulse", "err_pulse"; 312 clocks = <&cpg CPG_MOD 0x9f>, 313 <&cpg CPG_MOD 0xa0>, 314 <&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>, 315 <&cpg CPG_MOD 0xa1>; 316 clock-names = "ahb", "axi", "spi", "spix2"; 317 resets = <&cpg 0xa3>, <&cpg 0xa4>; 318 reset-names = "hresetn", "aresetn"; 319 power-domains = <&cpg>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 status = "disabled"; 323 }; 324 325 dmac0: dma-controller@11400000 { 326 compatible = "renesas,r9a09g047-dmac", 327 "renesas,r9a09g057-dmac"; 328 reg = <0 0x11400000 0 0x10000>; 329 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 332 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 333 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 334 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 335 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 336 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 337 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 338 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 339 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 340 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 341 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 342 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 346 interrupt-names = "error", 347 "ch0", "ch1", "ch2", "ch3", 348 "ch4", "ch5", "ch6", "ch7", 349 "ch8", "ch9", "ch10", "ch11", 350 "ch12", "ch13", "ch14", "ch15"; 351 clocks = <&cpg CPG_MOD 0x0>; 352 power-domains = <&cpg>; 353 resets = <&cpg 0x31>; 354 #dma-cells = <1>; 355 dma-channels = <16>; 356 renesas,icu = <&icu 4>; 357 }; 358 359 dmac1: dma-controller@14830000 { 360 compatible = "renesas,r9a09g047-dmac", 361 "renesas,r9a09g057-dmac"; 362 reg = <0 0x14830000 0 0x10000>; 363 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 364 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 365 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 366 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 369 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 370 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 371 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 372 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 373 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 374 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 375 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 380 interrupt-names = "error", 381 "ch0", "ch1", "ch2", "ch3", 382 "ch4", "ch5", "ch6", "ch7", 383 "ch8", "ch9", "ch10", "ch11", 384 "ch12", "ch13", "ch14", "ch15"; 385 clocks = <&cpg CPG_MOD 0x1>; 386 power-domains = <&cpg>; 387 resets = <&cpg 0x32>; 388 #dma-cells = <1>; 389 dma-channels = <16>; 390 renesas,icu = <&icu 0>; 391 }; 392 393 dmac2: dma-controller@14840000 { 394 compatible = "renesas,r9a09g047-dmac", 395 "renesas,r9a09g057-dmac"; 396 reg = <0 0x14840000 0 0x10000>; 397 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 399 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 400 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 401 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 402 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 403 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 406 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 407 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 408 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 414 interrupt-names = "error", 415 "ch0", "ch1", "ch2", "ch3", 416 "ch4", "ch5", "ch6", "ch7", 417 "ch8", "ch9", "ch10", "ch11", 418 "ch12", "ch13", "ch14", "ch15"; 419 clocks = <&cpg CPG_MOD 0x2>; 420 power-domains = <&cpg>; 421 resets = <&cpg 0x33>; 422 #dma-cells = <1>; 423 dma-channels = <16>; 424 renesas,icu = <&icu 1>; 425 }; 426 427 dmac3: dma-controller@12000000 { 428 compatible = "renesas,r9a09g047-dmac", 429 "renesas,r9a09g057-dmac"; 430 reg = <0 0x12000000 0 0x10000>; 431 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 432 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 433 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 435 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 436 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 437 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 438 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 439 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 440 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 448 interrupt-names = "error", 449 "ch0", "ch1", "ch2", "ch3", 450 "ch4", "ch5", "ch6", "ch7", 451 "ch8", "ch9", "ch10", "ch11", 452 "ch12", "ch13", "ch14", "ch15"; 453 clocks = <&cpg CPG_MOD 0x3>; 454 power-domains = <&cpg>; 455 resets = <&cpg 0x34>; 456 #dma-cells = <1>; 457 dma-channels = <16>; 458 renesas,icu = <&icu 2>; 459 }; 460 461 dmac4: dma-controller@12010000 { 462 compatible = "renesas,r9a09g047-dmac", 463 "renesas,r9a09g057-dmac"; 464 reg = <0 0x12010000 0 0x10000>; 465 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 466 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 467 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 468 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 469 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 470 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 471 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 472 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 473 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 474 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 482 interrupt-names = "error", 483 "ch0", "ch1", "ch2", "ch3", 484 "ch4", "ch5", "ch6", "ch7", 485 "ch8", "ch9", "ch10", "ch11", 486 "ch12", "ch13", "ch14", "ch15"; 487 clocks = <&cpg CPG_MOD 0x4>; 488 power-domains = <&cpg>; 489 resets = <&cpg 0x35>; 490 #dma-cells = <1>; 491 dma-channels = <16>; 492 renesas,icu = <&icu 3>; 493 }; 494 495 scif0: serial@11c01400 { 496 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 497 reg = <0 0x11c01400 0 0x400>; 498 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 506 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 507 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 508 "tei", "tei-dri", "rxi-edge", "txi-edge"; 509 clocks = <&cpg CPG_MOD 0x8f>; 510 clock-names = "fck"; 511 power-domains = <&cpg>; 512 resets = <&cpg 0x95>; 513 status = "disabled"; 514 }; 515 516 i3c: i3c@12400000 { 517 compatible = "renesas,r9a09g047-i3c"; 518 reg = <0 0x12400000 0 0x10000>; 519 clocks = <&cpg CPG_MOD 0x91>, 520 <&cpg CPG_MOD 0x92>, 521 <&cpg CPG_MOD 0x90>; 522 clock-names = "pclk", "tclk", "pclkrw"; 523 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "ierr", "terr", "abort", "resp", 540 "cmd", "ibi", "rx", "tx", "rcv", 541 "st", "sp", "tend", "nack", "al", 542 "tmo", "wu"; 543 resets = <&cpg 0x96>, <&cpg 0x97>; 544 reset-names = "presetn", "tresetn"; 545 power-domains = <&cpg>; 546 #address-cells = <3>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 canfd: can@12440000 { 552 compatible = "renesas,r9a09g047-canfd"; 553 reg = <0 0x12440000 0 0x40000>; 554 interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "g_err", "g_recc", 575 "ch0_err", "ch0_rec", "ch0_trx", 576 "ch1_err", "ch1_rec", "ch1_trx", 577 "ch2_err", "ch2_rec", "ch2_trx", 578 "ch3_err", "ch3_rec", "ch3_trx", 579 "ch4_err", "ch4_rec", "ch4_trx", 580 "ch5_err", "ch5_rec", "ch5_trx"; 581 clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, 582 <&cpg CPG_MOD 0x9e>; 583 clock-names = "fck", "ram_clk", "can_clk"; 584 assigned-clocks = <&cpg CPG_MOD 0x9e>; 585 assigned-clock-rates = <80000000>; 586 resets = <&cpg 0xa1>, <&cpg 0xa2>; 587 reset-names = "rstp_n", "rstc_n"; 588 power-domains = <&cpg>; 589 status = "disabled"; 590 591 channel0 { 592 status = "disabled"; 593 }; 594 channel1 { 595 status = "disabled"; 596 }; 597 channel2 { 598 status = "disabled"; 599 }; 600 channel3 { 601 status = "disabled"; 602 }; 603 channel4 { 604 status = "disabled"; 605 }; 606 channel5 { 607 status = "disabled"; 608 }; 609 }; 610 611 rspi0: spi@12800000 { 612 compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi"; 613 reg = <0x0 0x12800000 0x0 0x400>; 614 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 617 <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 618 <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 619 interrupt-names = "idle", "error", "end", "rx", "tx"; 620 clocks = <&cpg CPG_MOD 0x54>, 621 <&cpg CPG_MOD 0x55>, 622 <&cpg CPG_MOD 0x56>; 623 clock-names = "pclk", "pclk_sfr", "tclk"; 624 resets = <&cpg 0x7b>, <&cpg 0x7c>; 625 reset-names = "presetn", "tresetn"; 626 dmas = <&dmac0 0x448c>, <&dmac0 0x448d>, 627 <&dmac1 0x448c>, <&dmac1 0x448d>, 628 <&dmac2 0x448c>, <&dmac2 0x448d>, 629 <&dmac3 0x448c>, <&dmac3 0x448d>, 630 <&dmac4 0x448c>, <&dmac4 0x448d>; 631 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", 632 "rx", "tx", "rx", "tx"; 633 power-domains = <&cpg>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 status = "disabled"; 637 }; 638 639 rspi1: spi@12800400 { 640 compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi"; 641 reg = <0x0 0x12800400 0x0 0x400>; 642 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 645 <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 646 <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 647 interrupt-names = "idle", "error", "end", "rx", "tx"; 648 clocks = <&cpg CPG_MOD 0x57>, 649 <&cpg CPG_MOD 0x58>, 650 <&cpg CPG_MOD 0x59>; 651 clock-names = "pclk", "pclk_sfr", "tclk"; 652 resets = <&cpg 0x7d>, <&cpg 0x7e>; 653 reset-names = "presetn", "tresetn"; 654 dmas = <&dmac0 0x448e>, <&dmac0 0x448f>, 655 <&dmac1 0x448e>, <&dmac1 0x448f>, 656 <&dmac2 0x448e>, <&dmac2 0x448f>, 657 <&dmac3 0x448e>, <&dmac3 0x448f>, 658 <&dmac4 0x448e>, <&dmac4 0x448f>; 659 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", 660 "rx", "tx", "rx", "tx"; 661 power-domains = <&cpg>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 667 rspi2: spi@12800800 { 668 compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi"; 669 reg = <0x0 0x12800800 0x0 0x400>; 670 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 673 <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 674 <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 675 interrupt-names = "idle", "error", "end", "rx", "tx"; 676 clocks = <&cpg CPG_MOD 0x5a>, 677 <&cpg CPG_MOD 0x5b>, 678 <&cpg CPG_MOD 0x5c>; 679 clock-names = "pclk", "pclk_sfr", "tclk"; 680 resets = <&cpg 0x7f>, <&cpg 0x80>; 681 reset-names = "presetn", "tresetn"; 682 dmas = <&dmac0 0x4490>, <&dmac0 0x4491>, 683 <&dmac1 0x4490>, <&dmac1 0x4491>, 684 <&dmac2 0x4490>, <&dmac2 0x4491>, 685 <&dmac3 0x4490>, <&dmac3 0x4491>, 686 <&dmac4 0x4490>, <&dmac4 0x4491>; 687 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", 688 "rx", "tx", "rx", "tx"; 689 power-domains = <&cpg>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 status = "disabled"; 693 }; 694 695 rsci0: serial@12800c00 { 696 compatible = "renesas,r9a09g047-rsci"; 697 reg = <0 0x12800c00 0 0x400>; 698 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 700 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 701 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 703 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 704 interrupt-names = "eri", "rxi", "txi", "tei", 705 "aed", "bfd"; 706 clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, 707 <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, 708 <&cpg CPG_MOD 0x5f>; 709 clock-names = "pclk", "tclk", "tclk_div4", 710 "tclk_div16", "tclk_div64"; 711 power-domains = <&cpg>; 712 resets = <&cpg 0x81>, <&cpg 0x82>; 713 reset-names = "presetn", "tresetn"; 714 status = "disabled"; 715 }; 716 717 rsci1: serial@12801000 { 718 compatible = "renesas,r9a09g047-rsci"; 719 reg = <0 0x12801000 0 0x400>; 720 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 722 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 723 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 725 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-names = "eri", "rxi", "txi", "tei", 727 "aed", "bfd"; 728 clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, 729 <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, 730 <&cpg CPG_MOD 0x64>; 731 clock-names = "pclk", "tclk", "tclk_div4", 732 "tclk_div16", "tclk_div64"; 733 power-domains = <&cpg>; 734 resets = <&cpg 0x83>, <&cpg 0x84>; 735 reset-names = "presetn", "tresetn"; 736 status = "disabled"; 737 }; 738 739 rsci2: serial@12801400 { 740 compatible = "renesas,r9a09g047-rsci"; 741 reg = <0 0x12801400 0 0x400>; 742 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 744 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 745 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 747 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 748 interrupt-names = "eri", "rxi", "txi", "tei", 749 "aed", "bfd"; 750 clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, 751 <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, 752 <&cpg CPG_MOD 0x69>; 753 clock-names = "pclk", "tclk", "tclk_div4", 754 "tclk_div16", "tclk_div64"; 755 power-domains = <&cpg>; 756 resets = <&cpg 0x85>, <&cpg 0x86>; 757 reset-names = "presetn", "tresetn"; 758 status = "disabled"; 759 }; 760 761 rsci3: serial@12801800 { 762 compatible = "renesas,r9a09g047-rsci"; 763 reg = <0 0x12801800 0 0x400>; 764 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 766 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 767 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 769 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 770 interrupt-names = "eri", "rxi", "txi", "tei", 771 "aed", "bfd"; 772 clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, 773 <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, 774 <&cpg CPG_MOD 0x6e>; 775 clock-names = "pclk", "tclk", "tclk_div4", 776 "tclk_div16", "tclk_div64"; 777 power-domains = <&cpg>; 778 resets = <&cpg 0x87>, <&cpg 0x88>; 779 reset-names = "presetn", "tresetn"; 780 status = "disabled"; 781 }; 782 783 rsci4: serial@12801c00 { 784 compatible = "renesas,r9a09g047-rsci"; 785 reg = <0 0x12801c00 0 0x400>; 786 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 788 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 789 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 791 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 792 interrupt-names = "eri", "rxi", "txi", "tei", 793 "aed", "bfd"; 794 clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, 795 <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, 796 <&cpg CPG_MOD 0x73>; 797 clock-names = "pclk", "tclk", "tclk_div4", 798 "tclk_div16", "tclk_div64"; 799 power-domains = <&cpg>; 800 resets = <&cpg 0x89>, <&cpg 0x8a>; 801 reset-names = "presetn", "tresetn"; 802 status = "disabled"; 803 }; 804 805 rsci5: serial@12802000 { 806 compatible = "renesas,r9a09g047-rsci"; 807 reg = <0 0x12802000 0 0x400>; 808 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 810 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 811 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 813 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-names = "eri", "rxi", "txi", "tei", 815 "aed", "bfd"; 816 clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, 817 <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, 818 <&cpg CPG_MOD 0x78>; 819 clock-names = "pclk", "tclk", "tclk_div4", 820 "tclk_div16", "tclk_div64"; 821 power-domains = <&cpg>; 822 resets = <&cpg 0x8b>, <&cpg 0x8c>; 823 reset-names = "presetn", "tresetn"; 824 status = "disabled"; 825 }; 826 827 rsci6: serial@12802400 { 828 compatible = "renesas,r9a09g047-rsci"; 829 reg = <0 0x12802400 0 0x400>; 830 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, 832 <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, 833 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, 835 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "eri", "rxi", "txi", "tei", 837 "aed", "bfd"; 838 clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, 839 <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, 840 <&cpg CPG_MOD 0x7d>; 841 clock-names = "pclk", "tclk", "tclk_div4", 842 "tclk_div16", "tclk_div64"; 843 power-domains = <&cpg>; 844 resets = <&cpg 0x8d>, <&cpg 0x8e>; 845 reset-names = "presetn", "tresetn"; 846 status = "disabled"; 847 }; 848 849 rsci7: serial@12802800 { 850 compatible = "renesas,r9a09g047-rsci"; 851 reg = <0 0x12802800 0 0x400>; 852 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, 854 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 855 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, 857 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 858 interrupt-names = "eri", "rxi", "txi", "tei", 859 "aed", "bfd"; 860 clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, 861 <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, 862 <&cpg CPG_MOD 0x82>; 863 clock-names = "pclk", "tclk", "tclk_div4", 864 "tclk_div16", "tclk_div64"; 865 power-domains = <&cpg>; 866 resets = <&cpg 0x8f>, <&cpg 0x90>; 867 reset-names = "presetn", "tresetn"; 868 status = "disabled"; 869 }; 870 871 rsci8: serial@12802c00 { 872 compatible = "renesas,r9a09g047-rsci"; 873 reg = <0 0x12802c00 0 0x400>; 874 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, 876 <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, 877 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 879 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "eri", "rxi", "txi", "tei", 881 "aed", "bfd"; 882 clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, 883 <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, 884 <&cpg CPG_MOD 0x87>; 885 clock-names = "pclk", "tclk", "tclk_div4", 886 "tclk_div16", "tclk_div64"; 887 power-domains = <&cpg>; 888 resets = <&cpg 0x91>, <&cpg 0x92>; 889 reset-names = "presetn", "tresetn"; 890 status = "disabled"; 891 }; 892 893 rsci9: serial@12803000 { 894 compatible = "renesas,r9a09g047-rsci"; 895 reg = <0 0x12803000 0 0x400>; 896 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, 898 <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 902 interrupt-names = "eri", "rxi", "txi", "tei", 903 "aed", "bfd"; 904 clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, 905 <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, 906 <&cpg CPG_MOD 0x8c>; 907 clock-names = "pclk", "tclk", "tclk_div4", 908 "tclk_div16", "tclk_div64"; 909 power-domains = <&cpg>; 910 resets = <&cpg 0x93>, <&cpg 0x94>; 911 reset-names = "presetn", "tresetn"; 912 status = "disabled"; 913 }; 914 915 snd_rzg3e: sound@13c00000 { 916 compatible = "renesas,r9a09g047-sound"; 917 reg = <0 0x13c00000 0 0x20000>, /* SCU */ 918 <0 0x13c20000 0 0x10000>, /* ADG */ 919 <0 0x13c30000 0 0x1000>, /* SSIU */ 920 <0 0x13c31000 0 0x1f000>, /* SSI */ 921 <0 0x13c50000 0 0x10000>; /* Audio DMAC peri peri */ 922 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 923 clocks = <&cpg CPG_MOD 0xf5>, 924 <&cpg CPG_MOD 0x181>, <&cpg CPG_MOD 0x182>, 925 <&cpg CPG_MOD 0x183>, <&cpg CPG_MOD 0x184>, 926 <&cpg CPG_MOD 0x185>, <&cpg CPG_MOD 0x186>, 927 <&cpg CPG_MOD 0x187>, <&cpg CPG_MOD 0x188>, 928 <&cpg CPG_MOD 0x189>, <&cpg CPG_MOD 0x18a>, 929 <&cpg CPG_MOD 0x174>, <&cpg CPG_MOD 0x175>, 930 <&cpg CPG_MOD 0x176>, <&cpg CPG_MOD 0x177>, 931 <&cpg CPG_MOD 0x178>, <&cpg CPG_MOD 0x179>, 932 <&cpg CPG_MOD 0x17a>, <&cpg CPG_MOD 0x17b>, 933 <&cpg CPG_MOD 0x17c>, <&cpg CPG_MOD 0x17d>, 934 <&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>, 935 <&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>, 936 <&cpg CPG_MOD 0x170>, <&cpg CPG_MOD 0x171>, 937 <&cpg CPG_MOD 0xfb>, <&cpg CPG_MOD 0xfc>, 938 <&cpg CPG_MOD 0xfd>, <&cpg CPG_MOD 0xfa>, 939 <&cpg CPG_MOD 0x180>, 940 <&cpg CPG_MOD 0xf6>, <&cpg CPG_MOD 0xf7>, 941 <&cpg CPG_MOD 0x17e>, 942 <&cpg CPG_MOD 0x160>, <&cpg CPG_MOD 0x161>, 943 <&cpg CPG_MOD 0x162>, <&cpg CPG_MOD 0x163>, 944 <&cpg CPG_MOD 0x164>, <&cpg CPG_MOD 0x165>, 945 <&cpg CPG_MOD 0x166>, <&cpg CPG_MOD 0x167>, 946 <&cpg CPG_MOD 0x168>, <&cpg CPG_MOD 0x169>, 947 <&cpg CPG_MOD 0xf8>, <&cpg CPG_MOD 0xf9>; 948 clock-names = "ssi-all", 949 "ssi-0", "ssi-1", 950 "ssi-2", "ssi-3", 951 "ssi-4", "ssi-5", 952 "ssi-6", "ssi-7", 953 "ssi-8", "ssi-9", 954 "src-0", "src-1", 955 "src-2", "src-3", 956 "src-4", "src-5", 957 "src-6", "src-7", 958 "src-8", "src-9", 959 "mix-0", "mix-1", 960 "ctu-0", "ctu-1", 961 "dvc-0", "dvc-1", 962 "audio-clka", "audio-clkb", 963 "audio-clkc", "audio-clki", 964 "ssif_supply", 965 "scu", "scu_x2", 966 "scu_supply", 967 "adg-ssi-0", "adg-ssi-1", 968 "adg-ssi-2", "adg-ssi-3", 969 "adg-ssi-4", "adg-ssi-5", 970 "adg-ssi-6", "adg-ssi-7", 971 "adg-ssi-8", "adg-ssi-9", 972 "audmapp", "adg"; 973 power-domains = <&cpg>; 974 resets = <&cpg 0xe1>, 975 <&cpg 0xe2>, <&cpg 0xe3>, 976 <&cpg 0xe4>, <&cpg 0xe5>, 977 <&cpg 0xe6>, <&cpg 0xe7>, 978 <&cpg 0xe8>, <&cpg 0xe9>, 979 <&cpg 0xea>, <&cpg 0xeb>, 980 <&cpg 0xec>, <&cpg 0xee>, 981 <&cpg 0xed>; 982 reset-names = "ssi-all", 983 "ssi-0", "ssi-1", 984 "ssi-2", "ssi-3", 985 "ssi-4", "ssi-5", 986 "ssi-6", "ssi-7", 987 "ssi-8", "ssi-9", 988 "scu", "adg", 989 "audmapp"; 990 status = "disabled"; 991 992 ctu { 993 ctu00: ctu-0 { }; 994 ctu01: ctu-1 { }; 995 ctu02: ctu-2 { }; 996 ctu03: ctu-3 { }; 997 ctu10: ctu-4 { }; 998 ctu11: ctu-5 { }; 999 ctu12: ctu-6 { }; 1000 ctu13: ctu-7 { }; 1001 }; 1002 1003 dvc { 1004 dvc0: dvc-0 { 1005 dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>, 1006 <&dmac2 0x1db3>, <&dmac3 0x1db3>, 1007 <&dmac4 0x1db3>; 1008 dma-names = "tx", "tx", "tx", "tx", "tx"; 1009 }; 1010 dvc1: dvc-1 { 1011 dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>, 1012 <&dmac2 0x1db4>, <&dmac3 0x1db4>, 1013 <&dmac4 0x1db4>; 1014 dma-names = "tx", "tx", "tx", "tx", "tx"; 1015 }; 1016 }; 1017 1018 mix { 1019 mix0: mix-0 { }; 1020 mix1: mix-1 { }; 1021 }; 1022 1023 src { 1024 src0: src-0 { 1025 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 1026 dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>, 1027 <&dmac1 0x1d9f>, <&dmac1 0x1da9>, 1028 <&dmac2 0x1d9f>, <&dmac2 0x1da9>, 1029 <&dmac3 0x1d9f>, <&dmac3 0x1da9>, 1030 <&dmac4 0x1d9f>, <&dmac4 0x1da9>; 1031 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1032 "rx", "tx"; 1033 }; 1034 src1: src-1 { 1035 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 1036 dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>, 1037 <&dmac1 0x1da0>, <&dmac1 0x1daa>, 1038 <&dmac2 0x1da0>, <&dmac2 0x1daa>, 1039 <&dmac3 0x1da0>, <&dmac3 0x1daa>, 1040 <&dmac4 0x1da0>, <&dmac4 0x1daa>; 1041 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1042 "rx", "tx"; 1043 }; 1044 src2: src-2 { 1045 interrupts = <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>; 1046 dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>, 1047 <&dmac1 0x1da1>, <&dmac1 0x1dab>, 1048 <&dmac2 0x1da1>, <&dmac2 0x1dab>, 1049 <&dmac3 0x1da1>, <&dmac3 0x1dab>, 1050 <&dmac4 0x1da1>, <&dmac4 0x1dab>; 1051 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1052 "rx", "tx"; 1053 }; 1054 src3: src-3 { 1055 interrupts = <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>; 1056 dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>, 1057 <&dmac1 0x1da2>, <&dmac1 0x1dac>, 1058 <&dmac2 0x1da2>, <&dmac2 0x1dac>, 1059 <&dmac3 0x1da2>, <&dmac3 0x1dac>, 1060 <&dmac4 0x1da2>, <&dmac4 0x1dac>; 1061 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1062 "rx", "tx"; 1063 }; 1064 src4: src-4 { 1065 interrupts = <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>; 1066 dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>, 1067 <&dmac1 0x1da3>, <&dmac1 0x1dad>, 1068 <&dmac2 0x1da3>, <&dmac2 0x1dad>, 1069 <&dmac3 0x1da3>, <&dmac3 0x1dad>, 1070 <&dmac4 0x1da3>, <&dmac4 0x1dad>; 1071 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1072 "rx", "tx"; 1073 }; 1074 src5: src-5 { 1075 interrupts = <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>; 1076 dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>, 1077 <&dmac1 0x1da4>, <&dmac1 0x1dae>, 1078 <&dmac2 0x1da4>, <&dmac2 0x1dae>, 1079 <&dmac3 0x1da4>, <&dmac3 0x1dae>, 1080 <&dmac4 0x1da4>, <&dmac4 0x1dae>; 1081 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1082 "rx", "tx"; 1083 }; 1084 src6: src-6 { 1085 interrupts = <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>; 1086 dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>, 1087 <&dmac1 0x1da5>, <&dmac1 0x1daf>, 1088 <&dmac2 0x1da5>, <&dmac2 0x1daf>, 1089 <&dmac3 0x1da5>, <&dmac3 0x1daf>, 1090 <&dmac4 0x1da5>, <&dmac4 0x1daf>; 1091 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1092 "rx", "tx"; 1093 }; 1094 src7: src-7 { 1095 interrupts = <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>; 1096 dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>, 1097 <&dmac1 0x1da6>, <&dmac1 0x1db0>, 1098 <&dmac2 0x1da6>, <&dmac2 0x1db0>, 1099 <&dmac3 0x1da6>, <&dmac3 0x1db0>, 1100 <&dmac4 0x1da6>, <&dmac4 0x1db0>; 1101 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1102 "rx", "tx"; 1103 }; 1104 src8: src-8 { 1105 interrupts = <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>; 1106 dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>, 1107 <&dmac1 0x1da7>, <&dmac1 0x1db1>, 1108 <&dmac2 0x1da7>, <&dmac2 0x1db1>, 1109 <&dmac3 0x1da7>, <&dmac3 0x1db1>, 1110 <&dmac4 0x1da7>, <&dmac4 0x1db1>; 1111 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1112 "rx", "tx"; 1113 }; 1114 src9: src-9 { 1115 interrupts = <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>; 1116 dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>, 1117 <&dmac1 0x1da8>, <&dmac1 0x1db2>, 1118 <&dmac2 0x1da8>, <&dmac2 0x1db2>, 1119 <&dmac3 0x1da8>, <&dmac3 0x1db2>, 1120 <&dmac4 0x1da8>, <&dmac4 0x1db2>; 1121 dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", 1122 "rx", "tx"; 1123 }; 1124 }; 1125 1126 ssi { 1127 ssi0: ssi-0 { 1128 interrupts = <GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>; 1129 }; 1130 ssi1: ssi-1 { 1131 interrupts = <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 1132 }; 1133 ssi2: ssi-2 { 1134 interrupts = <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 1135 }; 1136 ssi3: ssi-3 { 1137 interrupts = <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>; 1138 }; 1139 ssi4: ssi-4 { 1140 interrupts = <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>; 1141 }; 1142 ssi5: ssi-5 { 1143 interrupts = <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>; 1144 }; 1145 ssi6: ssi-6 { 1146 interrupts = <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 1147 }; 1148 ssi7: ssi-7 { 1149 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 1150 }; 1151 ssi8: ssi-8 { 1152 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 1153 }; 1154 ssi9: ssi-9 { 1155 interrupts = <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>; 1156 }; 1157 }; 1158 1159 ssiu { 1160 ssiu00: ssiu-0 { 1161 dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>, 1162 <&dmac1 0x1d61>, <&dmac1 0x1d62>, 1163 <&dmac2 0x1d61>, <&dmac2 0x1d62>, 1164 <&dmac3 0x1d61>, <&dmac3 0x1d62>, 1165 <&dmac4 0x1d61>, <&dmac4 0x1d62>; 1166 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1167 "tx", "rx"; 1168 }; 1169 ssiu01: ssiu-1 { 1170 dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>, 1171 <&dmac1 0x1d63>, <&dmac1 0x1d64>, 1172 <&dmac2 0x1d63>, <&dmac2 0x1d64>, 1173 <&dmac3 0x1d63>, <&dmac3 0x1d64>, 1174 <&dmac4 0x1d63>, <&dmac4 0x1d64>; 1175 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1176 "tx", "rx"; 1177 }; 1178 ssiu02: ssiu-2 { 1179 dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>, 1180 <&dmac1 0x1d65>, <&dmac1 0x1d66>, 1181 <&dmac2 0x1d65>, <&dmac2 0x1d66>, 1182 <&dmac3 0x1d65>, <&dmac3 0x1d66>, 1183 <&dmac4 0x1d65>, <&dmac4 0x1d66>; 1184 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1185 "tx", "rx"; 1186 }; 1187 ssiu03: ssiu-3 { 1188 dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>, 1189 <&dmac1 0x1d67>, <&dmac1 0x1d68>, 1190 <&dmac2 0x1d67>, <&dmac2 0x1d68>, 1191 <&dmac3 0x1d67>, <&dmac3 0x1d68>, 1192 <&dmac4 0x1d67>, <&dmac4 0x1d68>; 1193 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1194 "tx", "rx"; 1195 }; 1196 ssiu10: ssiu-4 { 1197 dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>, 1198 <&dmac1 0x1d69>, <&dmac1 0x1d6a>, 1199 <&dmac2 0x1d69>, <&dmac2 0x1d6a>, 1200 <&dmac3 0x1d69>, <&dmac3 0x1d6a>, 1201 <&dmac4 0x1d69>, <&dmac4 0x1d6a>; 1202 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1203 "tx", "rx"; 1204 }; 1205 ssiu11: ssiu-5 { 1206 dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>, 1207 <&dmac1 0x1d6b>, <&dmac1 0x1d6c>, 1208 <&dmac2 0x1d6b>, <&dmac2 0x1d6c>, 1209 <&dmac3 0x1d6b>, <&dmac3 0x1d6c>, 1210 <&dmac4 0x1d6b>, <&dmac4 0x1d6c>; 1211 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1212 "tx", "rx"; 1213 }; 1214 ssiu12: ssiu-6 { 1215 dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>, 1216 <&dmac1 0x1d6d>, <&dmac1 0x1d6e>, 1217 <&dmac2 0x1d6d>, <&dmac2 0x1d6e>, 1218 <&dmac3 0x1d6d>, <&dmac3 0x1d6e>, 1219 <&dmac4 0x1d6d>, <&dmac4 0x1d6e>; 1220 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1221 "tx", "rx"; 1222 }; 1223 ssiu13: ssiu-7 { 1224 dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>, 1225 <&dmac1 0x1d6f>, <&dmac1 0x1d70>, 1226 <&dmac2 0x1d6f>, <&dmac2 0x1d70>, 1227 <&dmac3 0x1d6f>, <&dmac3 0x1d70>, 1228 <&dmac4 0x1d6f>, <&dmac4 0x1d70>; 1229 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1230 "tx", "rx"; 1231 }; 1232 ssiu20: ssiu-8 { 1233 dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>, 1234 <&dmac1 0x1d71>, <&dmac1 0x1d72>, 1235 <&dmac2 0x1d71>, <&dmac2 0x1d72>, 1236 <&dmac3 0x1d71>, <&dmac3 0x1d72>, 1237 <&dmac4 0x1d71>, <&dmac4 0x1d72>; 1238 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1239 "tx", "rx"; 1240 }; 1241 ssiu21: ssiu-9 { 1242 dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>, 1243 <&dmac1 0x1d73>, <&dmac1 0x1d74>, 1244 <&dmac2 0x1d73>, <&dmac2 0x1d74>, 1245 <&dmac3 0x1d73>, <&dmac3 0x1d74>, 1246 <&dmac4 0x1d73>, <&dmac4 0x1d74>; 1247 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1248 "tx", "rx"; 1249 }; 1250 ssiu22: ssiu-10 { 1251 dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>, 1252 <&dmac1 0x1d75>, <&dmac1 0x1d76>, 1253 <&dmac2 0x1d75>, <&dmac2 0x1d76>, 1254 <&dmac3 0x1d75>, <&dmac3 0x1d76>, 1255 <&dmac4 0x1d75>, <&dmac4 0x1d76>; 1256 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1257 "tx", "rx"; 1258 }; 1259 ssiu23: ssiu-11 { 1260 dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>, 1261 <&dmac1 0x1d77>, <&dmac1 0x1d78>, 1262 <&dmac2 0x1d77>, <&dmac2 0x1d78>, 1263 <&dmac3 0x1d77>, <&dmac3 0x1d78>, 1264 <&dmac4 0x1d77>, <&dmac4 0x1d78>; 1265 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1266 "tx", "rx"; 1267 }; 1268 ssiu30: ssiu-12 { 1269 dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>, 1270 <&dmac1 0x1d79>, <&dmac1 0x1d7a>, 1271 <&dmac2 0x1d79>, <&dmac2 0x1d7a>, 1272 <&dmac3 0x1d79>, <&dmac3 0x1d7a>, 1273 <&dmac4 0x1d79>, <&dmac4 0x1d7a>; 1274 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1275 "tx", "rx"; 1276 }; 1277 ssiu31: ssiu-13 { 1278 dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>, 1279 <&dmac1 0x1d7b>, <&dmac1 0x1d7c>, 1280 <&dmac2 0x1d7b>, <&dmac2 0x1d7c>, 1281 <&dmac3 0x1d7b>, <&dmac3 0x1d7c>, 1282 <&dmac4 0x1d7b>, <&dmac4 0x1d7c>; 1283 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1284 "tx", "rx"; 1285 }; 1286 ssiu32: ssiu-14 { 1287 dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>, 1288 <&dmac1 0x1d7d>, <&dmac1 0x1d7e>, 1289 <&dmac2 0x1d7d>, <&dmac2 0x1d7e>, 1290 <&dmac3 0x1d7d>, <&dmac3 0x1d7e>, 1291 <&dmac4 0x1d7d>, <&dmac4 0x1d7e>; 1292 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1293 "tx", "rx"; 1294 }; 1295 ssiu33: ssiu-15 { 1296 dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>, 1297 <&dmac1 0x1d7f>, <&dmac1 0x1d80>, 1298 <&dmac2 0x1d7f>, <&dmac2 0x1d80>, 1299 <&dmac3 0x1d7f>, <&dmac3 0x1d80>, 1300 <&dmac4 0x1d7f>, <&dmac4 0x1d80>; 1301 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1302 "tx", "rx"; 1303 }; 1304 ssiu40: ssiu-16 { 1305 dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>, 1306 <&dmac1 0x1d81>, <&dmac1 0x1d82>, 1307 <&dmac2 0x1d81>, <&dmac2 0x1d82>, 1308 <&dmac3 0x1d81>, <&dmac3 0x1d82>, 1309 <&dmac4 0x1d81>, <&dmac4 0x1d82>; 1310 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1311 "tx", "rx"; 1312 }; 1313 ssiu41: ssiu-17 { 1314 dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>, 1315 <&dmac1 0x1d83>, <&dmac1 0x1d84>, 1316 <&dmac2 0x1d83>, <&dmac2 0x1d84>, 1317 <&dmac3 0x1d83>, <&dmac3 0x1d84>, 1318 <&dmac4 0x1d83>, <&dmac4 0x1d84>; 1319 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1320 "tx", "rx"; 1321 }; 1322 ssiu42: ssiu-18 { 1323 dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>, 1324 <&dmac1 0x1d85>, <&dmac1 0x1d86>, 1325 <&dmac2 0x1d85>, <&dmac2 0x1d86>, 1326 <&dmac3 0x1d85>, <&dmac3 0x1d86>, 1327 <&dmac4 0x1d85>, <&dmac4 0x1d86>; 1328 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1329 "tx", "rx"; 1330 }; 1331 ssiu43: ssiu-19 { 1332 dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>, 1333 <&dmac1 0x1d87>, <&dmac1 0x1d88>, 1334 <&dmac2 0x1d87>, <&dmac2 0x1d88>, 1335 <&dmac3 0x1d87>, <&dmac3 0x1d88>, 1336 <&dmac4 0x1d87>, <&dmac4 0x1d88>; 1337 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1338 "tx", "rx"; 1339 }; 1340 ssiu50: ssiu-20 { 1341 dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>, 1342 <&dmac1 0x1d89>, <&dmac1 0x1d8a>, 1343 <&dmac2 0x1d89>, <&dmac2 0x1d8a>, 1344 <&dmac3 0x1d89>, <&dmac3 0x1d8a>, 1345 <&dmac4 0x1d89>, <&dmac4 0x1d8a>; 1346 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1347 "tx", "rx"; 1348 }; 1349 ssiu60: ssiu-21 { 1350 dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>, 1351 <&dmac1 0x1d8b>, <&dmac1 0x1d8c>, 1352 <&dmac2 0x1d8b>, <&dmac2 0x1d8c>, 1353 <&dmac3 0x1d8b>, <&dmac3 0x1d8c>, 1354 <&dmac4 0x1d8b>, <&dmac4 0x1d8c>; 1355 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1356 "tx", "rx"; 1357 }; 1358 ssiu70: ssiu-22 { 1359 dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>, 1360 <&dmac1 0x1d8d>, <&dmac1 0x1d8e>, 1361 <&dmac2 0x1d8d>, <&dmac2 0x1d8e>, 1362 <&dmac3 0x1d8d>, <&dmac3 0x1d8e>, 1363 <&dmac4 0x1d8d>, <&dmac4 0x1d8e>; 1364 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1365 "tx", "rx"; 1366 }; 1367 ssiu80: ssiu-23 { 1368 dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>, 1369 <&dmac1 0x1d8f>, <&dmac1 0x1d90>, 1370 <&dmac2 0x1d8f>, <&dmac2 0x1d90>, 1371 <&dmac3 0x1d8f>, <&dmac3 0x1d90>, 1372 <&dmac4 0x1d8f>, <&dmac4 0x1d90>; 1373 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1374 "tx", "rx"; 1375 }; 1376 ssiu90: ssiu-24 { 1377 dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>, 1378 <&dmac1 0x1d91>, <&dmac1 0x1d92>, 1379 <&dmac2 0x1d91>, <&dmac2 0x1d92>, 1380 <&dmac3 0x1d91>, <&dmac3 0x1d92>, 1381 <&dmac4 0x1d91>, <&dmac4 0x1d92>; 1382 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1383 "tx", "rx"; 1384 }; 1385 ssiu91: ssiu-25 { 1386 dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>, 1387 <&dmac1 0x1d93>, <&dmac1 0x1d94>, 1388 <&dmac2 0x1d93>, <&dmac2 0x1d94>, 1389 <&dmac3 0x1d93>, <&dmac3 0x1d94>, 1390 <&dmac4 0x1d93>, <&dmac4 0x1d94>; 1391 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1392 "tx", "rx"; 1393 }; 1394 ssiu92: ssiu-26 { 1395 dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>, 1396 <&dmac1 0x1d95>, <&dmac1 0x1d96>, 1397 <&dmac2 0x1d95>, <&dmac2 0x1d96>, 1398 <&dmac3 0x1d95>, <&dmac3 0x1d96>, 1399 <&dmac4 0x1d95>, <&dmac4 0x1d96>; 1400 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1401 "tx", "rx"; 1402 }; 1403 ssiu93: ssiu-27 { 1404 dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>, 1405 <&dmac1 0x1d97>, <&dmac1 0x1d98>, 1406 <&dmac2 0x1d97>, <&dmac2 0x1d98>, 1407 <&dmac3 0x1d97>, <&dmac3 0x1d98>, 1408 <&dmac4 0x1d97>, <&dmac4 0x1d98>; 1409 dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", 1410 "tx", "rx"; 1411 }; 1412 }; 1413 }; 1414 1415 wdt1: watchdog@14400000 { 1416 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 1417 reg = <0 0x14400000 0 0x400>; 1418 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 1419 clock-names = "pclk", "oscclk"; 1420 resets = <&cpg 0x76>; 1421 power-domains = <&cpg>; 1422 status = "disabled"; 1423 }; 1424 1425 wdt2: watchdog@13000000 { 1426 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 1427 reg = <0 0x13000000 0 0x400>; 1428 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 1429 clock-names = "pclk", "oscclk"; 1430 resets = <&cpg 0x77>; 1431 power-domains = <&cpg>; 1432 status = "disabled"; 1433 }; 1434 1435 wdt3: watchdog@13000400 { 1436 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 1437 reg = <0 0x13000400 0 0x400>; 1438 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 1439 clock-names = "pclk", "oscclk"; 1440 resets = <&cpg 0x78>; 1441 power-domains = <&cpg>; 1442 status = "disabled"; 1443 }; 1444 1445 pcie: pcie@13400000 { 1446 compatible = "renesas,r9a09g047-pcie"; 1447 reg = <0 0x13400000 0 0x10000>; 1448 ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1449 <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; 1450 dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>; 1451 bus-range = <0x0 0xff>; 1452 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1475 interrupt-names = "serr", "serr_cor", "serr_nonfatal", 1476 "serr_fatal", "axi_err", "inta", 1477 "intb", "intc", "intd", "msi", 1478 "link_bandwidth", "pm_pme", "dma", 1479 "pcie_evt", "msg", "all", 1480 "link_equalization_request", 1481 "turn_off_event", "pmu_poweroff", 1482 "d3_event_f0", "d3_event_f1", 1483 "cfg_pmcsr_writeclear_f0", 1484 "cfg_pmcsr_writeclear_f1"; 1485 #interrupt-cells = <1>; 1486 interrupt-controller; 1487 interrupt-map-mask = <0 0 0 7>; 1488 interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ 1489 <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ 1490 <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ 1491 <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ 1492 clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; 1493 clock-names = "aclk", "pmu"; 1494 resets = <&cpg 0xb2>; 1495 reset-names = "aresetn"; 1496 power-domains = <&cpg>; 1497 device_type = "pci"; 1498 #address-cells = <3>; 1499 #size-cells = <2>; 1500 renesas,sysc = <&sys>; 1501 status = "disabled"; 1502 1503 pcie_port0: pcie@0,0 { 1504 reg = <0x0 0x0 0x0 0x0 0x0>; 1505 ranges; 1506 device_type = "pci"; 1507 vendor-id = <0x1912>; 1508 device-id = <0x0039>; 1509 #address-cells = <3>; 1510 #size-cells = <2>; 1511 }; 1512 }; 1513 1514 tsu: thermal@14002000 { 1515 compatible = "renesas,r9a09g047-tsu"; 1516 reg = <0 0x14002000 0 0x1000>; 1517 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 1518 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1519 interrupt-names = "adi", "adcmpi"; 1520 clocks = <&cpg CPG_MOD 0x10a>; 1521 resets = <&cpg 0xf8>; 1522 power-domains = <&cpg>; 1523 #thermal-sensor-cells = <0>; 1524 renesas,tsu-trim = <&sys 0x330>; 1525 }; 1526 1527 i2c0: i2c@14400400 { 1528 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1529 reg = <0 0x14400400 0 0x400>; 1530 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 1532 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 1533 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1538 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1539 "naki", "ali", "tmoi"; 1540 clocks = <&cpg CPG_MOD 0x94>; 1541 resets = <&cpg 0x98>; 1542 power-domains = <&cpg>; 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 status = "disabled"; 1546 }; 1547 1548 i2c1: i2c@14400800 { 1549 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1550 reg = <0 0x14400800 0 0x400>; 1551 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 1553 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 1554 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1559 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1560 "naki", "ali", "tmoi"; 1561 clocks = <&cpg CPG_MOD 0x95>; 1562 resets = <&cpg 0x99>; 1563 power-domains = <&cpg>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 status = "disabled"; 1567 }; 1568 1569 i2c2: i2c@14400c00 { 1570 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1571 reg = <0 0x14400c00 0 0x400>; 1572 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 1574 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 1575 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1580 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1581 "naki", "ali", "tmoi"; 1582 clocks = <&cpg CPG_MOD 0x96>; 1583 resets = <&cpg 0x9a>; 1584 power-domains = <&cpg>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 status = "disabled"; 1588 }; 1589 1590 i2c3: i2c@14401000 { 1591 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1592 reg = <0 0x14401000 0 0x400>; 1593 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 1595 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 1596 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1601 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1602 "naki", "ali", "tmoi"; 1603 clocks = <&cpg CPG_MOD 0x97>; 1604 resets = <&cpg 0x9b>; 1605 power-domains = <&cpg>; 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 status = "disabled"; 1609 }; 1610 1611 i2c4: i2c@14401400 { 1612 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1613 reg = <0 0x14401400 0 0x400>; 1614 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 1616 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 1617 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1622 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1623 "naki", "ali", "tmoi"; 1624 clocks = <&cpg CPG_MOD 0x98>; 1625 resets = <&cpg 0x9c>; 1626 power-domains = <&cpg>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c5: i2c@14401800 { 1633 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1634 reg = <0 0x14401800 0 0x400>; 1635 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 1637 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 1638 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1643 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1644 "naki", "ali", "tmoi"; 1645 clocks = <&cpg CPG_MOD 0x99>; 1646 resets = <&cpg 0x9d>; 1647 power-domains = <&cpg>; 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 status = "disabled"; 1651 }; 1652 1653 i2c6: i2c@14401c00 { 1654 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1655 reg = <0 0x14401c00 0 0x400>; 1656 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 1658 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 1659 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1664 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1665 "naki", "ali", "tmoi"; 1666 clocks = <&cpg CPG_MOD 0x9a>; 1667 resets = <&cpg 0x9e>; 1668 power-domains = <&cpg>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 status = "disabled"; 1672 }; 1673 1674 i2c7: i2c@14402000 { 1675 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1676 reg = <0 0x14402000 0 0x400>; 1677 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 1679 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 1680 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1685 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1686 "naki", "ali", "tmoi"; 1687 clocks = <&cpg CPG_MOD 0x9b>; 1688 resets = <&cpg 0x9f>; 1689 power-domains = <&cpg>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 i2c8: i2c@11c01000 { 1696 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 1697 reg = <0 0x11c01000 0 0x400>; 1698 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 1700 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 1701 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1706 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1707 "naki", "ali", "tmoi"; 1708 clocks = <&cpg CPG_MOD 0x93>; 1709 resets = <&cpg 0xa0>; 1710 power-domains = <&cpg>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 gpu: gpu@14850000 { 1717 compatible = "renesas,r9a09g047-mali", 1718 "arm,mali-bifrost"; 1719 reg = <0x0 0x14850000 0x0 0x10000>; 1720 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 1724 interrupt-names = "job", "mmu", "gpu", "event"; 1725 clocks = <&cpg CPG_MOD 0xf0>, 1726 <&cpg CPG_MOD 0xf1>, 1727 <&cpg CPG_MOD 0xf2>; 1728 clock-names = "gpu", "bus", "bus_ace"; 1729 power-domains = <&cpg>; 1730 resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>; 1731 reset-names = "rst", "axi_rst", "ace_rst"; 1732 operating-points-v2 = <&gpu_opp_table>; 1733 status = "disabled"; 1734 }; 1735 1736 gic: interrupt-controller@14900000 { 1737 compatible = "arm,gic-v3"; 1738 reg = <0x0 0x14900000 0 0x20000>, 1739 <0x0 0x14940000 0 0x80000>; 1740 #interrupt-cells = <3>; 1741 #address-cells = <0>; 1742 interrupt-controller; 1743 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1744 }; 1745 1746 xhci: usb@15850000 { 1747 compatible = "renesas,r9a09g047-xhci"; 1748 reg = <0 0x15850000 0 0x10000>; 1749 interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1754 interrupt-names = "all", "smi", "hse", "pme", "xhc"; 1755 clocks = <&cpg CPG_MOD 0xaf>; 1756 power-domains = <&cpg>; 1757 resets = <&cpg 0xaa>; 1758 phys = <&usb3_phy>, <&usb3_phy>; 1759 phy-names = "usb2-phy", "usb3-phy"; 1760 status = "disabled"; 1761 }; 1762 1763 usb3_phy: usb-phy@15870000 { 1764 compatible = "renesas,r9a09g047-usb3-phy"; 1765 reg = <0 0x15870000 0 0x10000>; 1766 clocks = <&cpg CPG_MOD 0xb0>, 1767 <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>, 1768 <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>; 1769 clock-names = "pclk", "core", "ref_alt_clk_p"; 1770 power-domains = <&cpg>; 1771 resets = <&cpg 0xaa>; 1772 #phy-cells = <0>; 1773 status = "disabled"; 1774 }; 1775 1776 sdhi0: mmc@15c00000 { 1777 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 1778 reg = <0x0 0x15c00000 0 0x10000>; 1779 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 1781 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 1782 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 1783 clock-names = "core", "clkh", "cd", "aclk"; 1784 max-frequency = <200000000>; 1785 resets = <&cpg 0xa7>; 1786 power-domains = <&cpg>; 1787 status = "disabled"; 1788 1789 sdhi0_vqmmc: vqmmc-regulator { 1790 regulator-name = "SDHI0-VQMMC"; 1791 regulator-min-microvolt = <1800000>; 1792 regulator-max-microvolt = <3300000>; 1793 status = "disabled"; 1794 }; 1795 }; 1796 1797 sdhi1: mmc@15c10000 { 1798 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 1799 reg = <0x0 0x15c10000 0 0x10000>; 1800 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 1802 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 1803 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 1804 clock-names = "core", "clkh", "cd", "aclk"; 1805 max-frequency = <200000000>; 1806 resets = <&cpg 0xa8>; 1807 power-domains = <&cpg>; 1808 status = "disabled"; 1809 1810 sdhi1_vqmmc: vqmmc-regulator { 1811 regulator-name = "SDHI1-VQMMC"; 1812 regulator-min-microvolt = <1800000>; 1813 regulator-max-microvolt = <3300000>; 1814 status = "disabled"; 1815 }; 1816 }; 1817 1818 sdhi2: mmc@15c20000 { 1819 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 1820 reg = <0x0 0x15c20000 0 0x10000>; 1821 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 1823 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 1824 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 1825 clock-names = "core", "clkh", "cd", "aclk"; 1826 max-frequency = <200000000>; 1827 resets = <&cpg 0xa9>; 1828 power-domains = <&cpg>; 1829 status = "disabled"; 1830 1831 sdhi2_vqmmc: vqmmc-regulator { 1832 regulator-name = "SDHI2-VQMMC"; 1833 regulator-min-microvolt = <1800000>; 1834 regulator-max-microvolt = <3300000>; 1835 status = "disabled"; 1836 }; 1837 }; 1838 1839 eth0: ethernet@15c30000 { 1840 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 1841 "snps,dwmac-5.20"; 1842 reg = <0 0x15c30000 0 0x10000>; 1843 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1844 <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, 1845 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1846 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1847 clock-names = "stmmaceth", "pclk", "ptp_ref", 1848 "tx", "rx", "tx-180", "rx-180"; 1849 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1861 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1862 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1863 "tx-queue-2", "tx-queue-3"; 1864 resets = <&cpg 0xb0>; 1865 power-domains = <&cpg>; 1866 snps,multicast-filter-bins = <256>; 1867 snps,perfect-filter-entries = <128>; 1868 rx-fifo-depth = <8192>; 1869 tx-fifo-depth = <8192>; 1870 snps,mixed-burst; 1871 snps,force_sf_dma_mode; 1872 snps,axi-config = <&stmmac_axi_setup>; 1873 snps,mtl-rx-config = <&mtl_rx_setup0>; 1874 snps,mtl-tx-config = <&mtl_tx_setup0>; 1875 snps,txpbl = <32>; 1876 snps,rxpbl = <32>; 1877 status = "disabled"; 1878 1879 mdio0: mdio { 1880 compatible = "snps,dwmac-mdio"; 1881 #address-cells = <1>; 1882 #size-cells = <0>; 1883 }; 1884 1885 mtl_rx_setup0: rx-queues-config { 1886 snps,rx-queues-to-use = <4>; 1887 snps,rx-sched-sp; 1888 1889 queue0 { 1890 snps,dcb-algorithm; 1891 snps,priority = <0x1>; 1892 snps,map-to-dma-channel = <0>; 1893 }; 1894 1895 queue1 { 1896 snps,dcb-algorithm; 1897 snps,priority = <0x2>; 1898 snps,map-to-dma-channel = <1>; 1899 }; 1900 1901 queue2 { 1902 snps,dcb-algorithm; 1903 snps,priority = <0x4>; 1904 snps,map-to-dma-channel = <2>; 1905 }; 1906 1907 queue3 { 1908 snps,dcb-algorithm; 1909 snps,priority = <0x8>; 1910 snps,map-to-dma-channel = <3>; 1911 }; 1912 }; 1913 1914 mtl_tx_setup0: tx-queues-config { 1915 snps,tx-queues-to-use = <4>; 1916 snps,tx-sched-wrr; 1917 1918 queue0 { 1919 snps,weight = <0x10>; 1920 snps,dcb-algorithm; 1921 snps,priority = <0x1>; 1922 }; 1923 1924 queue1 { 1925 snps,weight = <0x12>; 1926 snps,dcb-algorithm; 1927 snps,priority = <0x2>; 1928 }; 1929 1930 queue2 { 1931 snps,weight = <0x14>; 1932 snps,dcb-algorithm; 1933 snps,priority = <0x4>; 1934 }; 1935 1936 queue3 { 1937 snps,weight = <0x18>; 1938 snps,dcb-algorithm; 1939 snps,priority = <0x8>; 1940 }; 1941 }; 1942 }; 1943 1944 eth1: ethernet@15c40000 { 1945 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 1946 "snps,dwmac-5.20"; 1947 reg = <0 0x15c40000 0 0x10000>; 1948 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1949 <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, 1950 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1951 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1952 clock-names = "stmmaceth", "pclk", "ptp_ref", 1953 "tx", "rx", "tx-180", "rx-180"; 1954 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1966 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1967 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1968 "tx-queue-2", "tx-queue-3"; 1969 resets = <&cpg 0xb1>; 1970 power-domains = <&cpg>; 1971 snps,multicast-filter-bins = <256>; 1972 snps,perfect-filter-entries = <128>; 1973 rx-fifo-depth = <8192>; 1974 tx-fifo-depth = <8192>; 1975 snps,mixed-burst; 1976 snps,force_sf_dma_mode; 1977 snps,axi-config = <&stmmac_axi_setup>; 1978 snps,mtl-rx-config = <&mtl_rx_setup1>; 1979 snps,mtl-tx-config = <&mtl_tx_setup1>; 1980 snps,txpbl = <32>; 1981 snps,rxpbl = <32>; 1982 status = "disabled"; 1983 1984 mdio1: mdio { 1985 compatible = "snps,dwmac-mdio"; 1986 #address-cells = <1>; 1987 #size-cells = <0>; 1988 }; 1989 1990 mtl_rx_setup1: rx-queues-config { 1991 snps,rx-queues-to-use = <4>; 1992 snps,rx-sched-sp; 1993 1994 queue0 { 1995 snps,dcb-algorithm; 1996 snps,priority = <0x1>; 1997 snps,map-to-dma-channel = <0>; 1998 }; 1999 2000 queue1 { 2001 snps,dcb-algorithm; 2002 snps,priority = <0x2>; 2003 snps,map-to-dma-channel = <1>; 2004 }; 2005 2006 queue2 { 2007 snps,dcb-algorithm; 2008 snps,priority = <0x4>; 2009 snps,map-to-dma-channel = <2>; 2010 }; 2011 2012 queue3 { 2013 snps,dcb-algorithm; 2014 snps,priority = <0x8>; 2015 snps,map-to-dma-channel = <3>; 2016 }; 2017 }; 2018 2019 mtl_tx_setup1: tx-queues-config { 2020 snps,tx-queues-to-use = <4>; 2021 snps,tx-sched-wrr; 2022 2023 queue0 { 2024 snps,weight = <0x10>; 2025 snps,dcb-algorithm; 2026 snps,priority = <0x1>; 2027 }; 2028 2029 queue1 { 2030 snps,weight = <0x12>; 2031 snps,dcb-algorithm; 2032 snps,priority = <0x2>; 2033 }; 2034 2035 queue2 { 2036 snps,weight = <0x14>; 2037 snps,dcb-algorithm; 2038 snps,priority = <0x4>; 2039 }; 2040 2041 queue3 { 2042 snps,weight = <0x18>; 2043 snps,dcb-algorithm; 2044 snps,priority = <0x8>; 2045 }; 2046 }; 2047 }; 2048 2049 cru: video@16000000 { 2050 compatible = "renesas,r9a09g047-cru"; 2051 reg = <0 0x16000000 0 0x400>; 2052 clocks = <&cpg CPG_MOD 0xd3>, 2053 <&cpg CPG_MOD 0xd4>, 2054 <&cpg CPG_MOD 0xd2>; 2055 clock-names = "video", "apb", "axi"; 2056 interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 2061 interrupt-names = "image_conv", "axi_mst_err", 2062 "vd_addr_wend", "sd_addr_wend", 2063 "vsd_addr_wend"; 2064 resets = <&cpg 0xc5>, <&cpg 0xc6>; 2065 reset-names = "presetn", "aresetn"; 2066 power-domains = <&cpg>; 2067 status = "disabled"; 2068 2069 ports { 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 2073 port@1 { 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 2077 reg = <1>; 2078 crucsi2: endpoint@0 { 2079 reg = <0>; 2080 remote-endpoint = <&csi2cru>; 2081 }; 2082 }; 2083 }; 2084 }; 2085 2086 csi2: csi2@16000400 { 2087 compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2"; 2088 reg = <0 0x16000400 0 0xc00>; 2089 interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>; 2090 clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>; 2091 clock-names = "video", "apb"; 2092 resets = <&cpg 0xc5>, <&cpg 0xc7>; 2093 reset-names = "presetn", "cmn-rstb"; 2094 power-domains = <&cpg>; 2095 status = "disabled"; 2096 2097 ports { 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 port@0 { 2102 reg = <0>; 2103 }; 2104 2105 port@1 { 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 reg = <1>; 2109 2110 csi2cru: endpoint@0 { 2111 reg = <0>; 2112 remote-endpoint = <&crucsi2>; 2113 }; 2114 }; 2115 }; 2116 }; 2117 2118 fcpvd0: fcp@16470000 { 2119 compatible = "renesas,r9a09g047-fcpvd", 2120 "renesas,fcpv"; 2121 reg = <0 0x16470000 0 0x10000>; 2122 clocks = <&cpg CPG_MOD 0xed>, 2123 <&cpg CPG_MOD 0xee>, 2124 <&cpg CPG_MOD 0xef>; 2125 clock-names = "aclk", "pclk", "vclk"; 2126 resets = <&cpg 0xdc>; 2127 power-domains = <&cpg>; 2128 }; 2129 2130 fcpvd1: fcp@164a0000 { 2131 compatible = "renesas,r9a09g047-fcpvd", 2132 "renesas,fcpv"; 2133 reg = <0 0x164a0000 0 0x10000>; 2134 clocks = <&cpg CPG_MOD 0x1a8>, 2135 <&cpg CPG_MOD 0x1a9>, 2136 <&cpg CPG_MOD 0x1aa>; 2137 clock-names = "aclk", "pclk", "vclk"; 2138 resets = <&cpg 0x11e>; 2139 power-domains = <&cpg>; 2140 }; 2141 2142 vspd0: vsp@16480000 { 2143 compatible = "renesas,r9a09g047-vsp2", 2144 "renesas,r9a07g044-vsp2"; 2145 reg = <0 0x16480000 0 0x10000>; 2146 interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>; 2147 clocks = <&cpg CPG_MOD 0xed>, 2148 <&cpg CPG_MOD 0xee>, 2149 <&cpg CPG_MOD 0xef>; 2150 clock-names = "aclk", "pclk", "vclk"; 2151 resets = <&cpg 0xdc>; 2152 power-domains = <&cpg>; 2153 renesas,fcp = <&fcpvd0>; 2154 }; 2155 2156 vspd1: vsp@164b0000 { 2157 compatible = "renesas,r9a09g047-vsp2", 2158 "renesas,r9a07g044-vsp2"; 2159 reg = <0 0x164b0000 0 0x10000>; 2160 interrupts = <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>; 2161 clocks = <&cpg CPG_MOD 0x1a8>, 2162 <&cpg CPG_MOD 0x1a9>, 2163 <&cpg CPG_MOD 0x1aa>; 2164 clock-names = "aclk", "pclk", "vclk"; 2165 resets = <&cpg 0x11e>; 2166 power-domains = <&cpg>; 2167 renesas,fcp = <&fcpvd1>; 2168 }; 2169 }; 2170 2171 stmmac_axi_setup: stmmac-axi-config { 2172 snps,lpi_en; 2173 snps,wr_osr_lmt = <0xf>; 2174 snps,rd_osr_lmt = <0xf>; 2175 snps,blen = <16 8 4 0 0 0 0>; 2176 }; 2177 2178 thermal-zones { 2179 cpu-thermal { 2180 polling-delay = <1000>; 2181 polling-delay-passive = <250>; 2182 thermal-sensors = <&tsu>; 2183 2184 cooling-maps { 2185 map0 { 2186 trip = <&target>; 2187 cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, 2188 <&cpu2 0 3>, <&cpu3 0 3>; 2189 contribution = <1024>; 2190 }; 2191 }; 2192 2193 trips { 2194 target: trip-point { 2195 temperature = <95000>; 2196 hysteresis = <1000>; 2197 type = "passive"; 2198 }; 2199 2200 sensor_crit: sensor-crit { 2201 temperature = <120000>; 2202 hysteresis = <1000>; 2203 type = "critical"; 2204 }; 2205 }; 2206 }; 2207 }; 2208 2209 timer { 2210 compatible = "arm,armv8-timer"; 2211 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2212 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2213 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2214 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 2215 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 2216 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 2217 }; 2218}; 2219