1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_CORE_SHARED_TYPES_H__ 6 #define __DML2_CORE_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_display_cfg_types.h" 10 #include "dml_top_types.h" 11 12 #define __DML_VBA_DEBUG__ 13 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling 14 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling 15 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit 16 17 #define __DML2_CALCS_DPP_INVALID__ 0 18 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation 19 #define __DML2_CALCS_PIPE_NO_PLANE__ 99 20 21 struct dml2_core_ip_params { 22 unsigned int vblank_nom_default_us; 23 unsigned int remote_iommu_outstanding_translations; 24 unsigned int rob_buffer_size_kbytes; 25 unsigned int config_return_buffer_size_in_kbytes; 26 unsigned int config_return_buffer_segment_size_in_kbytes; 27 unsigned int compressed_buffer_segment_size_in_kbytes; 28 unsigned int meta_fifo_size_in_kentries; 29 unsigned int dpte_buffer_size_in_pte_reqs_luma; 30 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 31 unsigned int pixel_chunk_size_kbytes; 32 unsigned int alpha_pixel_chunk_size_kbytes; 33 unsigned int min_pixel_chunk_size_bytes; 34 unsigned int writeback_chunk_size_kbytes; 35 unsigned int line_buffer_size_bits; 36 unsigned int max_line_buffer_lines; 37 unsigned int writeback_interface_buffer_size_kbytes; 38 unsigned int max_num_dpp; 39 unsigned int max_num_opp; 40 unsigned int max_num_otg; 41 unsigned int TDLUT_33cube_count; 42 unsigned int max_num_wb; 43 unsigned int max_dchub_pscl_bw_pix_per_clk; 44 unsigned int max_pscl_lb_bw_pix_per_clk; 45 unsigned int max_lb_vscl_bw_pix_per_clk; 46 unsigned int max_vscl_hscl_bw_pix_per_clk; 47 double max_hscl_ratio; 48 double max_vscl_ratio; 49 unsigned int max_hscl_taps; 50 unsigned int max_vscl_taps; 51 unsigned int odm_combine_support_mask; 52 unsigned int num_dsc; 53 unsigned int maximum_dsc_bits_per_component; 54 unsigned int maximum_pixels_per_line_per_dsc_unit; 55 bool dsc422_native_support; 56 bool cursor_64bpp_support; 57 double dispclk_ramp_margin_percent; 58 unsigned int dppclk_delay_subtotal; 59 unsigned int dppclk_delay_scl; 60 unsigned int dppclk_delay_scl_lb_only; 61 unsigned int dppclk_delay_cnvc_formatter; 62 unsigned int dppclk_delay_cnvc_cursor; 63 unsigned int cursor_buffer_size; 64 unsigned int cursor_chunk_size; 65 unsigned int dispclk_delay_subtotal; 66 bool dynamic_metadata_vm_enabled; 67 unsigned int max_inter_dcn_tile_repeaters; 68 unsigned int max_num_hdmi_frl_outputs; 69 unsigned int max_num_dp2p0_outputs; 70 unsigned int max_num_dp2p0_streams; 71 bool dcc_supported; 72 bool ptoi_supported; 73 double writeback_max_hscl_ratio; 74 double writeback_max_vscl_ratio; 75 double writeback_min_hscl_ratio; 76 double writeback_min_vscl_ratio; 77 unsigned int writeback_max_hscl_taps; 78 unsigned int writeback_max_vscl_taps; 79 unsigned int writeback_line_buffer_buffer_size; 80 81 unsigned int words_per_channel; 82 bool imall_supported; 83 unsigned int max_flip_time_us; 84 unsigned int max_flip_time_lines; 85 unsigned int subvp_swath_height_margin_lines; 86 unsigned int subvp_fw_processing_delay_us; 87 unsigned int subvp_pstate_allow_width_us; 88 // MRQ 89 bool dcn_mrq_present; 90 unsigned int zero_size_buffer_entries; 91 unsigned int compbuf_reserved_space_zs; 92 unsigned int dcc_meta_buffer_size_bytes; 93 unsigned int meta_chunk_size_kbytes; 94 unsigned int min_meta_chunk_size_bytes; 95 96 unsigned int dchub_arb_to_ret_delay; // num of dcfclk 97 unsigned int hostvm_mode; 98 }; 99 100 struct dml2_core_internal_DmlPipe { 101 double Dppclk; 102 double Dispclk; 103 double PixelClock; 104 double DCFClkDeepSleep; 105 unsigned int DPPPerSurface; 106 bool ScalerEnabled; 107 bool UPSPEnabled; 108 unsigned int UPSPVTaps; 109 enum dml2_sample_positioning UPSPSamplePositioning; 110 enum dml2_rotation_angle RotationAngle; 111 bool mirrored; 112 unsigned int ViewportHeight; 113 unsigned int ViewportHeightC; 114 unsigned int BlockWidth256BytesY; 115 unsigned int BlockHeight256BytesY; 116 unsigned int BlockWidth256BytesC; 117 unsigned int BlockHeight256BytesC; 118 unsigned int BlockWidthY; 119 unsigned int BlockHeightY; 120 unsigned int BlockWidthC; 121 unsigned int BlockHeightC; 122 unsigned int InterlaceEnable; 123 unsigned int NumberOfCursors; 124 unsigned int VBlank; 125 unsigned int HTotal; 126 unsigned int HActive; 127 bool DCCEnable; 128 enum dml2_odm_mode ODMMode; 129 enum dml2_source_format_class SourcePixelFormat; 130 enum dml2_swizzle_mode SurfaceTiling; 131 unsigned int BytePerPixelY; 132 unsigned int BytePerPixelC; 133 bool ProgressiveToInterlaceUnitInOPP; 134 double VRatio; 135 double VRatioChroma; 136 unsigned int VTaps; 137 unsigned int VTapsChroma; 138 unsigned int PitchY; 139 unsigned int PitchC; 140 bool ViewportStationary; 141 unsigned int ViewportXStart; 142 unsigned int ViewportYStart; 143 unsigned int ViewportXStartC; 144 unsigned int ViewportYStartC; 145 bool FORCE_ONE_ROW_FOR_FRAME; 146 unsigned int SwathHeightY; 147 unsigned int SwathHeightC; 148 149 unsigned int DCCMetaPitchY; 150 unsigned int DCCMetaPitchC; 151 }; 152 153 enum dml2_core_internal_request_type { 154 dml2_core_internal_request_type_256_bytes = 0, 155 dml2_core_internal_request_type_128_bytes_non_contiguous = 1, 156 dml2_core_internal_request_type_128_bytes_contiguous = 2, 157 dml2_core_internal_request_type_na = 3 158 }; 159 enum dml2_core_internal_bw_type { 160 dml2_core_internal_bw_sdp = 0, 161 dml2_core_internal_bw_dram = 1, 162 dml2_core_internal_bw_max 163 }; 164 165 enum dml2_core_internal_soc_state_type { 166 dml2_core_internal_soc_state_sys_active = 0, 167 dml2_core_internal_soc_state_svp_prefetch = 1, 168 dml2_core_internal_soc_state_sys_idle = 2, 169 dml2_core_internal_soc_state_max 170 }; 171 172 enum dml2_core_internal_output_type { 173 dml2_core_internal_output_type_unknown = 0, 174 dml2_core_internal_output_type_dp = 1, 175 dml2_core_internal_output_type_edp = 2, 176 dml2_core_internal_output_type_dp2p0 = 3, 177 dml2_core_internal_output_type_hdmi = 4, 178 dml2_core_internal_output_type_hdmifrl = 5 179 }; 180 181 enum dml2_core_internal_output_type_rate { 182 dml2_core_internal_output_rate_unknown = 0, 183 dml2_core_internal_output_rate_dp_rate_hbr = 1, 184 dml2_core_internal_output_rate_dp_rate_hbr2 = 2, 185 dml2_core_internal_output_rate_dp_rate_hbr3 = 3, 186 dml2_core_internal_output_rate_dp_rate_uhbr10 = 4, 187 dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5, 188 dml2_core_internal_output_rate_dp_rate_uhbr20 = 6, 189 dml2_core_internal_output_rate_hdmi_rate_3x3 = 7, 190 dml2_core_internal_output_rate_hdmi_rate_6x3 = 8, 191 dml2_core_internal_output_rate_hdmi_rate_6x4 = 9, 192 dml2_core_internal_output_rate_hdmi_rate_8x4 = 10, 193 dml2_core_internal_output_rate_hdmi_rate_10x4 = 11, 194 dml2_core_internal_output_rate_hdmi_rate_12x4 = 12, 195 dml2_core_internal_output_rate_hdmi_rate_16x4 = 13, 196 dml2_core_internal_output_rate_hdmi_rate_20x4 = 14 197 }; 198 199 struct dml2_core_internal_watermarks { 200 double UrgentWatermark; 201 double WritebackUrgentWatermark; 202 double DRAMClockChangeWatermark; 203 double FCLKChangeWatermark; 204 double WritebackDRAMClockChangeWatermark; 205 double WritebackFCLKChangeWatermark; 206 double StutterExitWatermark; 207 double StutterEnterPlusExitWatermark; 208 double LowPowerStutterExitWatermark; 209 double LowPowerStutterEnterPlusExitWatermark; 210 double Z8StutterExitWatermark; 211 double Z8StutterEnterPlusExitWatermark; 212 double USRRetrainingWatermark; 213 double temp_read_or_ppt_watermark_us; 214 }; 215 216 struct dml2_core_internal_mode_support_info { 217 //----------------- 218 // Mode Support Information 219 //----------------- 220 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 221 222 // Mode Support Reason/ 223 bool WritebackLatencySupport; 224 bool ScaleRatioAndTapsSupport; 225 bool SourceFormatPixelAndScanSupport; 226 bool P2IWith420; 227 bool DSCSlicesODMModeSupported; 228 bool DSCOnlyIfNecessaryWithBPP; 229 bool DSC422NativeNotSupported; 230 bool LinkRateDoesNotMatchDPVersion; 231 bool LinkRateForMultistreamNotIndicated; 232 bool BPPForMultistreamNotIndicated; 233 bool MultistreamWithHDMIOreDP; 234 bool MSOOrODMSplitWithNonDPLink; 235 bool NotEnoughLanesForMSO; 236 bool NumberOfOTGSupport; 237 bool NumberOfTDLUT33cubeSupport; 238 bool NumberOfHDMIFRLSupport; 239 bool NumberOfDP2p0Support; 240 bool WritebackScaleRatioAndTapsSupport; 241 bool CursorSupport; 242 bool PitchSupport; 243 bool ViewportExceedsSurface; 244 //bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 245 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 246 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 247 bool InvalidCombinationOfMALLUseForPState; 248 bool ExceededMALLSize; 249 bool EnoughWritebackUnits; 250 251 bool ExceededMultistreamSlots; 252 bool NotEnoughDSCUnits; 253 bool NotEnoughDSCSlices; 254 bool PixelsPerLinePerDSCUnitSupport; 255 bool DSCCLKRequiredMoreThanSupported; 256 bool DTBCLKRequiredMoreThanSupported; 257 bool LinkCapacitySupport; 258 259 bool ROBSupport; 260 bool OutstandingRequestsSupport; 261 bool OutstandingRequestsUrgencyAvoidance; 262 263 bool PTEBufferSizeNotExceeded; 264 bool DCCMetaBufferSizeNotExceeded; 265 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 266 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 267 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 268 bool global_dram_clock_change_support_required; 269 bool global_dram_clock_change_supported; 270 bool global_fclk_change_supported; 271 bool global_temp_read_or_ppt_supported; 272 bool fclk_pstate_schedule_admissible; 273 bool temp_read_pstate_schedule_admissible; 274 bool ppt_pstate_schedule_admissible; 275 bool USRRetrainingSupport; 276 bool AvgBandwidthSupport; 277 bool UrgVactiveBandwidthSupport; 278 bool EnoughUrgentLatencyHidingSupport; 279 bool PrefetchScheduleSupported; 280 bool PrefetchSupported; 281 bool PrefetchBandwidthSupported; 282 bool DynamicMetadataSupported; 283 bool VRatioInPrefetchSupported; 284 bool DISPCLK_DPPCLK_Support; 285 bool TotalAvailablePipesSupport; 286 bool ODMSupport; 287 bool ModeSupport; 288 bool ViewportSizeSupport; 289 290 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 291 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 292 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 293 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 294 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 295 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 296 297 double OutputBpp[DML2_MAX_PLANES]; 298 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 299 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 300 301 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 302 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 303 304 unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES]; 305 unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES]; 306 307 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 308 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 309 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 310 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 311 312 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 313 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 314 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 315 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 316 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 317 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 318 319 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 320 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 321 double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation 322 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 323 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 324 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc. 325 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 326 327 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 328 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 329 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 330 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 331 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 332 333 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 334 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 335 bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 336 double max_urgent_latency_us; 337 double max_non_urgent_latency_us; 338 double avg_non_urgent_latency_us; 339 double avg_urgent_latency_us; 340 double df_response_time_us; 341 342 bool incorrect_imall_usage; 343 344 bool g6_temp_read_support; 345 346 struct dml2_core_internal_watermarks watermarks; 347 bool dcfclk_support; 348 bool qos_bandwidth_support; 349 }; 350 351 struct dml2_core_internal_mode_support { 352 // Physical info; only using for programming 353 unsigned int state_idx; // <brief min clk state table index for mode support call 354 unsigned int qos_param_index; // to access the uclk dependent qos_parameters table 355 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 356 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 357 358 // Calculated Clocks 359 double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 360 double RequiredDPPCLK[DML2_MAX_PLANES]; 361 double RequiredDISPCLKPerSurface[DML2_MAX_PLANES]; 362 double RequiredDTBCLK[DML2_MAX_PLANES]; 363 364 double required_dscclk_freq_mhz[DML2_MAX_PLANES]; 365 366 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 367 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 368 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 369 double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 370 double GlobalDTBCLK; /// <brief the Max DTBCLK freq out of all pipes 371 double uclk_freq_mhz; 372 double dram_bw_mbps; 373 double max_dram_bw_mbps; 374 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 375 376 double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state 377 double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 378 double max_dispclk_freq_mhz; 379 double max_dppclk_freq_mhz; 380 double max_dscclk_freq_mhz; 381 382 bool NoTimeForPrefetch[DML2_MAX_PLANES]; 383 bool NoTimeForDynamicMetadata[DML2_MAX_PLANES]; 384 385 // ---------------------------------- 386 // Mode Support Info and fail reason 387 // ---------------------------------- 388 struct dml2_core_internal_mode_support_info support; 389 390 // These are calculated before the ModeSupport and ModeProgram step 391 // They represent the bound for the return buffer sizing 392 unsigned int MaxTotalDETInKByte; 393 unsigned int NomDETInKByte; 394 unsigned int MinCompressedBufferSizeInKByte; 395 396 // Info obtained at the end of mode support calculations 397 // The reported info is at the "optimal" state and combine setting 398 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 399 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 400 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 401 unsigned int SwathHeightY[DML2_MAX_PLANES]; 402 unsigned int SwathHeightC[DML2_MAX_PLANES]; 403 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 404 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 405 406 // ---------------------------------- 407 // Intermediates/Informational 408 // ---------------------------------- 409 unsigned int TotImmediateFlipBytes; 410 bool DCCEnabledInAnySurface; 411 double WritebackRequiredDISPCLK; 412 double TimeCalc; 413 double TWait[DML2_MAX_PLANES]; 414 415 bool UnboundedRequestEnabled; 416 unsigned int compbuf_reserved_space_64b; 417 bool hw_debug5; 418 unsigned int CompressedBufferSizeInkByte; 419 double VRatioPreY[DML2_MAX_PLANES]; 420 double VRatioPreC[DML2_MAX_PLANES]; 421 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 422 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 423 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 424 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 425 unsigned int RequiredSlots[DML2_MAX_PLANES]; 426 unsigned int vm_bytes[DML2_MAX_PLANES]; 427 unsigned int DPTEBytesPerRow[DML2_MAX_PLANES]; 428 unsigned int PrefetchLinesY[DML2_MAX_PLANES]; 429 unsigned int PrefetchLinesC[DML2_MAX_PLANES]; 430 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 431 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 432 unsigned int PrefillY[DML2_MAX_PLANES]; 433 unsigned int PrefillC[DML2_MAX_PLANES]; 434 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 435 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 436 437 bool use_one_row_for_frame[DML2_MAX_PLANES]; 438 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 439 440 double dst_y_prefetch[DML2_MAX_PLANES]; 441 double LinesForVM[DML2_MAX_PLANES]; 442 double LinesForDPTERow[DML2_MAX_PLANES]; 443 unsigned int SwathWidthYSingleDPP[DML2_MAX_PLANES]; 444 unsigned int SwathWidthCSingleDPP[DML2_MAX_PLANES]; 445 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 446 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 447 double BytePerPixelInDETY[DML2_MAX_PLANES]; 448 double BytePerPixelInDETC[DML2_MAX_PLANES]; 449 450 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 451 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 452 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 453 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 454 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 455 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 456 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 457 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 458 459 bool surf_linear128_l[DML2_MAX_PLANES]; 460 bool surf_linear128_c[DML2_MAX_PLANES]; 461 462 double PSCL_FACTOR[DML2_MAX_PLANES]; 463 double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES]; 464 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 465 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 466 double Tno_bw[DML2_MAX_PLANES]; 467 double Tno_bw_flip[DML2_MAX_PLANES]; 468 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 469 double dst_y_per_row_flip[DML2_MAX_PLANES]; 470 double WritebackDelayTime[DML2_MAX_PLANES]; 471 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 472 unsigned int dpte_row_height[DML2_MAX_PLANES]; 473 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 474 double UrgLatency; 475 double TripToMemory; 476 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 477 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 478 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 479 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 480 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 481 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 482 double MaximumSwathWidthInLineBufferLuma; 483 double MaximumSwathWidthInLineBufferChroma; 484 double ExtraLatency; 485 double ExtraLatency_sr; 486 double ExtraLatencyPrefetch; 487 488 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 489 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 490 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 491 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 492 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe 493 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 494 495 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 496 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 497 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 498 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 499 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 500 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 501 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 502 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 503 unsigned int meta_req_width[DML2_MAX_PLANES]; 504 unsigned int meta_row_width[DML2_MAX_PLANES]; 505 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 506 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 507 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 508 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 509 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 510 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 511 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 512 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 513 unsigned int meta_req_height[DML2_MAX_PLANES]; 514 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 515 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 516 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 517 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 518 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 519 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 520 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 521 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 522 double TSetup[DML2_MAX_PLANES]; 523 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 524 double Tdmdl_raw[DML2_MAX_PLANES]; 525 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 526 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 527 double MaxActiveFCLKChangeLatencySupported; 528 529 // Backend 530 bool RequiresDSC[DML2_MAX_PLANES]; 531 bool RequiresFEC[DML2_MAX_PLANES]; 532 double OutputBpp[DML2_MAX_PLANES]; 533 double DesiredOutputBpp[DML2_MAX_PLANES]; 534 double PixelClockBackEnd[DML2_MAX_PLANES]; 535 unsigned int DSCDelay[DML2_MAX_PLANES]; 536 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 537 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 538 bool TotalAvailablePipesSupportNoDSC; 539 bool TotalAvailablePipesSupportDSC; 540 unsigned int NumberOfDPPNoDSC; 541 unsigned int NumberOfDPPDSC; 542 enum dml2_odm_mode ODMModeNoDSC; 543 enum dml2_odm_mode ODMModeDSC; 544 double RequiredDISPCLKPerSurfaceNoDSC; 545 double RequiredDISPCLKPerSurfaceDSC; 546 unsigned int EstimatedNumberOfDSCSlices[DML2_MAX_PLANES]; 547 548 // Bandwidth Related Info 549 double BandwidthAvailableForImmediateFlip; 550 double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane 551 double vactive_sw_bw_c[DML2_MAX_PLANES]; 552 double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK]; 553 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 554 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 555 /* Max bandwidth calculated from prefetch schedule should be considered in addition to the pixel data bw to avoid ms/mp mismatches. 556 * 1. oto bw should also be considered when calculating peak urgent bw to avoid situations oto/equ mismatches between ms and mp 557 * 558 * 2. equ bandwidth needs to be considered for calculating peak urgent bw when equ schedule is used in mode support. 559 * Some slight difference in variables may cause the pixel data bandwidth to be higher 560 * even though overall equ prefetch bandwidths can be lower going from ms to mp 561 */ 562 double RequiredPrefetchBWMax[DML2_MAX_PLANES]; 563 double cursor_bw[DML2_MAX_PLANES]; 564 double prefetch_cursor_bw[DML2_MAX_PLANES]; 565 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 566 double final_flip_bw[DML2_MAX_PLANES]; 567 double meta_row_bw[DML2_MAX_PLANES]; 568 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 569 double dpte_row_bw[DML2_MAX_PLANES]; 570 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 571 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 572 double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 573 double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 574 575 // Something that should be feedback to caller 576 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 577 unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; 578 unsigned int NoOfDPP[DML2_MAX_PLANES]; 579 unsigned int NoOfOPP[DML2_MAX_PLANES]; 580 bool MPCCombine[DML2_MAX_PLANES]; 581 double dcfclk_deepsleep; 582 double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 583 bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES]; 584 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 585 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 586 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 587 bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; 588 bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; 589 unsigned int TotalNumberOfActiveDPP; 590 unsigned int TotalNumberOfActiveOPP; 591 unsigned int TotalNumberOfSingleDPPSurfaces; 592 unsigned int TotalNumberOfDCCActiveDPP; 593 unsigned int Total3dlutActive; 594 595 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 596 double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; 597 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 598 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; 599 double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES]; 600 601 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 602 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 603 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 604 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 605 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 606 607 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 608 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 609 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 610 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 611 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 612 613 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 614 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 615 bool lc_comb_mcache[DML2_MAX_PLANES]; 616 617 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 618 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 619 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 620 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 621 622 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 623 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 624 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 625 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 626 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 627 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 628 629 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 630 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 631 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 632 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 633 634 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 635 636 double HostVMInefficiencyFactor; 637 double HostVMInefficiencyFactorPrefetch; 638 639 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 640 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 641 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 642 double tdlut_opt_time[DML2_MAX_PLANES]; 643 double tdlut_drain_time[DML2_MAX_PLANES]; 644 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 645 646 double Tvm_trips_flip[DML2_MAX_PLANES]; 647 double Tr0_trips_flip[DML2_MAX_PLANES]; 648 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 649 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 650 651 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 652 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 653 654 enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 655 }; 656 657 /// @brief A mega structure that houses various info for model programming step. 658 struct dml2_core_internal_mode_program { 659 unsigned int qos_param_index; // to access the uclk dependent dpm table 660 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 661 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 662 //double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 663 double dram_bw_mbps; 664 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 665 double uclk_freq_mhz; 666 unsigned int NoOfDPP[DML2_MAX_PLANES]; 667 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 668 669 //------------- 670 // Intermediate/Informational 671 //------------- 672 double UrgentLatency; 673 double TripToMemory; 674 double MetaTripToMemory; 675 unsigned int VInitPreFillY[DML2_MAX_PLANES]; 676 unsigned int VInitPreFillC[DML2_MAX_PLANES]; 677 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; 678 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; 679 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 680 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 681 682 double BytePerPixelInDETY[DML2_MAX_PLANES]; 683 double BytePerPixelInDETC[DML2_MAX_PLANES]; 684 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 685 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 686 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 687 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 688 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 689 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 690 unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES]; 691 unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES]; 692 double vactive_sw_bw_l[DML2_MAX_PLANES]; 693 double vactive_sw_bw_c[DML2_MAX_PLANES]; 694 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 695 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 696 697 unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES]; 698 unsigned int vm_bytes[DML2_MAX_PLANES]; 699 unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES]; 700 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 701 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 702 unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES]; 703 double PSCL_THROUGHPUT[DML2_MAX_PLANES]; 704 double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES]; 705 unsigned int DSCDelay[DML2_MAX_PLANES]; 706 double DPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 707 708 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 709 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 710 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 711 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 712 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 713 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 714 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 715 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 716 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 717 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 718 719 bool surf_linear128_l[DML2_MAX_PLANES]; 720 bool surf_linear128_c[DML2_MAX_PLANES]; 721 722 unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES]; 723 double VRatioPrefetchY[DML2_MAX_PLANES]; 724 double VRatioPrefetchC[DML2_MAX_PLANES]; 725 double Tno_bw[DML2_MAX_PLANES]; 726 double Tno_bw_flip[DML2_MAX_PLANES]; 727 double final_flip_bw[DML2_MAX_PLANES]; 728 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 729 double cursor_bw[DML2_MAX_PLANES]; 730 double prefetch_cursor_bw[DML2_MAX_PLANES]; 731 double WritebackDelay[DML2_MAX_PLANES]; 732 unsigned int dpte_row_height[DML2_MAX_PLANES]; 733 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 734 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 735 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 736 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 737 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 738 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 739 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 740 741 double dpte_row_bw[DML2_MAX_PLANES]; 742 double time_per_tdlut_group[DML2_MAX_PLANES]; 743 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 744 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 745 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 746 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 747 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 748 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 749 750 double MaximumSwathWidthInLineBufferLuma; 751 double MaximumSwathWidthInLineBufferChroma; 752 753 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 754 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 755 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 756 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 757 758 double meta_row_bw[DML2_MAX_PLANES]; 759 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 760 unsigned int meta_req_width[DML2_MAX_PLANES]; 761 unsigned int meta_req_height[DML2_MAX_PLANES]; 762 unsigned int meta_row_width[DML2_MAX_PLANES]; 763 unsigned int meta_row_height[DML2_MAX_PLANES]; 764 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 765 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 766 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 767 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 768 769 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 770 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 771 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 772 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 773 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 774 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 775 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 776 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 777 778 double TWait[DML2_MAX_PLANES]; 779 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 780 double Tdmdl_vm[DML2_MAX_PLANES]; 781 double Tdmdl_raw[DML2_MAX_PLANES]; 782 double Tdmdl[DML2_MAX_PLANES]; 783 double TSetup[DML2_MAX_PLANES]; 784 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 785 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 786 787 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 788 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 789 790 bool UnboundedRequestEnabled; 791 unsigned int CompressedBufferSizeInkByte; 792 unsigned int compbuf_reserved_space_64b; 793 bool hw_debug5; 794 unsigned int dcfclk_deep_sleep_hysteresis; 795 unsigned int min_return_latency_in_dcfclk; 796 797 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 798 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 799 double ExtraLatency; 800 double ExtraLatency_sr; 801 double ExtraLatencyPrefetch; 802 bool PrefetchAndImmediateFlipSupported; 803 double TotalDataReadBandwidth; 804 double BandwidthAvailableForImmediateFlip; 805 bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES]; 806 807 bool use_one_row_for_frame[DML2_MAX_PLANES]; 808 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 809 810 double TCalc; 811 unsigned int TotImmediateFlipBytes; 812 813 unsigned int MaxTotalDETInKByte; 814 unsigned int NomDETInKByte; 815 unsigned int MinCompressedBufferSizeInKByte; 816 double PixelClockBackEnd[DML2_MAX_PLANES]; 817 double OutputBpp[DML2_MAX_PLANES]; 818 bool dsc_enable[DML2_MAX_PLANES]; 819 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 820 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 821 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 822 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 823 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 824 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 825 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 826 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 827 double HostVMInefficiencyFactor; 828 double HostVMInefficiencyFactorPrefetch; 829 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 830 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 831 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 832 double tdlut_opt_time[DML2_MAX_PLANES]; 833 double tdlut_drain_time[DML2_MAX_PLANES]; 834 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 835 double Tvm_trips_flip[DML2_MAX_PLANES]; 836 double Tr0_trips_flip[DML2_MAX_PLANES]; 837 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 838 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 839 bool immediate_flip_required; // any pipes need immediate flip 840 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 841 double TotalWRBandwidth; 842 double max_urgent_latency_us; 843 double df_response_time_us; 844 845 enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 846 // ------------------- 847 // Output 848 // ------------------- 849 unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 850 unsigned int num_active_pipes; 851 852 bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result 853 854 // Support 855 bool UrgVactiveBandwidthSupport; 856 bool PrefetchScheduleSupported; 857 bool UrgentBandwidthSupport; 858 bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported 859 bool ImmediateFlipSupported; 860 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 861 bool dcfclk_support; 862 863 // Clock 864 double Dcfclk; 865 double Dispclk; // <brief dispclk being used in mode programming 866 double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming 867 double GlobalDPPCLK; 868 869 double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 870 double DCFCLKDeepSleep; 871 872 // ARB reg 873 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 874 struct dml2_core_internal_watermarks Watermark; 875 876 // DCC compression control 877 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 878 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 879 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 880 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 881 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 882 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 883 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 884 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 885 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 886 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 887 888 // Stutter Efficiency 889 double StutterEfficiency; 890 double StutterEfficiencyNotIncludingVBlank; 891 unsigned int NumberOfStutterBurstsPerFrame; 892 double Z8StutterEfficiency; 893 unsigned int Z8NumberOfStutterBurstsPerFrame; 894 double Z8StutterEfficiencyNotIncludingVBlank; 895 double LowPowerStutterEfficiency; 896 double LowPowerStutterEfficiencyNotIncludingVBlank; 897 unsigned int LowPowerNumberOfStutterBurstsPerFrame; 898 double StutterPeriod; 899 double Z8StutterEfficiencyBestCase; 900 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; 901 double Z8StutterEfficiencyNotIncludingVBlankBestCase; 902 double StutterPeriodBestCase; 903 904 // DLG TTU reg 905 double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES]; 906 bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES]; 907 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 908 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 909 double dst_y_prefetch[DML2_MAX_PLANES]; 910 double dst_y_per_vm_vblank[DML2_MAX_PLANES]; 911 double dst_y_per_row_vblank[DML2_MAX_PLANES]; 912 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 913 double dst_y_per_row_flip[DML2_MAX_PLANES]; 914 double MinTTUVBlank[DML2_MAX_PLANES]; 915 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 916 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 917 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 918 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 919 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 920 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 921 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 922 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 923 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 924 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 925 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 926 927 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 928 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 929 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 930 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 931 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 932 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 933 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 934 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 935 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 936 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 937 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 938 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 939 940 double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES]; 941 double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES]; 942 double TimePerMetaChunkNominal[DML2_MAX_PLANES]; 943 double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES]; 944 double TimePerMetaChunkVBlank[DML2_MAX_PLANES]; 945 double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES]; 946 double TimePerMetaChunkFlip[DML2_MAX_PLANES]; 947 double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES]; 948 949 double FractionOfUrgentBandwidth; 950 double FractionOfUrgentBandwidthImmediateFlip; 951 double FractionOfUrgentBandwidthMALL; 952 953 // RQ registers 954 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 955 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 956 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 957 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 958 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 959 960 // OTG 961 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 962 unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 963 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 964 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 965 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 966 unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES]; 967 968 // Latency and Support 969 double MaxActiveFCLKChangeLatencySupported; 970 bool USRRetrainingSupport; 971 bool g6_temp_read_support; 972 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 973 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 974 enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 975 bool global_dram_clock_change_supported; 976 bool global_fclk_change_supported; 977 bool global_temp_read_or_ppt_supported; 978 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 979 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 980 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 981 982 // buffer sizing 983 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 984 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 985 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 986 unsigned int SwathHeightY[DML2_MAX_PLANES]; 987 unsigned int SwathHeightC[DML2_MAX_PLANES]; 988 989 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 990 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 991 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 992 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 993 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 994 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 995 996 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 997 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 998 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 999 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1000 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc. 1001 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 1002 1003 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; 1004 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 1005 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; 1006 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 1007 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; 1008 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 1009 1010 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 1011 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 1012 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 1013 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1014 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 1015 1016 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 1017 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 1018 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 1019 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1020 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 1021 1022 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 1023 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 1024 bool lc_comb_mcache[DML2_MAX_PLANES]; 1025 1026 double impacted_prefetch_margin_us[DML2_MAX_PLANES]; 1027 }; 1028 1029 struct dml2_core_internal_SOCParametersList { 1030 double UrgentLatency; 1031 double ExtraLatency_sr; 1032 double ExtraLatency; 1033 double WritebackLatency; 1034 double DRAMClockChangeLatency; 1035 double FCLKChangeLatency; 1036 double SRExitTime; 1037 double SREnterPlusExitTime; 1038 double SRExitTimeLowPower; 1039 double SREnterPlusExitTimeLowPower; 1040 double SRExitZ8Time; 1041 double SREnterPlusExitZ8Time; 1042 double USRRetrainingLatency; 1043 double SMNLatency; 1044 double g6_temp_read_blackout_us; 1045 double temp_read_or_ppt_blackout_us; 1046 double max_urgent_latency_us; 1047 double df_response_time_us; 1048 enum dml2_qos_param_type qos_type; 1049 }; 1050 1051 struct dml2_core_calcs_mode_support_locals { 1052 double PixelClockBackEnd[DML2_MAX_PLANES]; 1053 double OutputBpp[DML2_MAX_PLANES]; 1054 1055 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 1056 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 1057 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1058 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1059 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1060 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1061 1062 bool dummy_boolean[3]; 1063 unsigned int dummy_integer[3]; 1064 unsigned int dummy_integer_array[36][DML2_MAX_PLANES]; 1065 enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES]; 1066 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1067 double dummy_single[3]; 1068 double dummy_single_array[DML2_MAX_PLANES]; 1069 double dummy_double_array[3][DML2_MAX_PLANES]; 1070 enum dml2_pstate_method dummy_pstate_method_array[DML2_MAX_PLANES]; 1071 struct dml2_core_internal_watermarks dummy_watermark; 1072 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1073 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1074 1075 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 1076 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 1077 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 1078 struct dml2_core_internal_SOCParametersList mSOCParameters; 1079 struct dml2_core_internal_DmlPipe myPipe; 1080 struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES]; 1081 unsigned int TotalNumberOfActiveWriteback; 1082 unsigned int MaximumSwathWidthSupportLuma; 1083 unsigned int MaximumSwathWidthSupportChroma; 1084 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; 1085 bool MPCCombineMethodAsPossible; 1086 bool TotalAvailablePipesSupportNoDSC; 1087 unsigned int NumberOfDPPNoDSC; 1088 enum dml2_odm_mode ODMModeNoDSC; 1089 double RequiredDISPCLKPerSurfaceNoDSC; 1090 bool TotalAvailablePipesSupportDSC; 1091 unsigned int NumberOfDPPDSC; 1092 enum dml2_odm_mode ODMModeDSC; 1093 double RequiredDISPCLKPerSurfaceDSC; 1094 double BWOfNonCombinedSurfaceOfMaximumBandwidth; 1095 unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; 1096 unsigned int TotalNumberOfActiveOTG; 1097 unsigned int TotalNumberOfActiveHDMIFRL; 1098 unsigned int TotalNumberOfActiveDP2p0; 1099 unsigned int TotalNumberOfActiveDP2p0Outputs; 1100 unsigned int TotalSlots; 1101 unsigned int DSCFormatFactor; 1102 unsigned int TotalDSCUnitsRequired; 1103 unsigned int ReorderingBytes; 1104 bool ImmediateFlipRequired; 1105 bool FullFrameMALLPStateMethod; 1106 bool SubViewportMALLPStateMethod; 1107 bool PhantomPipeMALLPStateMethod; 1108 bool SubViewportMALLRefreshGreaterThan120Hz; 1109 1110 double HostVMInefficiencyFactor; 1111 double HostVMInefficiencyFactorPrefetch; 1112 unsigned int MaxVStartup; 1113 double PixelClockBackEndFactor; 1114 unsigned int NumDSCUnitRequired; 1115 1116 double Tvm_trips[DML2_MAX_PLANES]; 1117 double Tr0_trips[DML2_MAX_PLANES]; 1118 double Tvm_trips_flip[DML2_MAX_PLANES]; 1119 double Tr0_trips_flip[DML2_MAX_PLANES]; 1120 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1121 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1122 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1123 1124 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1125 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1126 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1127 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1128 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1129 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1130 1131 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1132 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1133 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1134 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1135 double tdlut_opt_time[DML2_MAX_PLANES]; 1136 double tdlut_drain_time[DML2_MAX_PLANES]; 1137 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1138 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1139 1140 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1141 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1142 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1143 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1144 bool stream_visited[DML2_MAX_PLANES]; 1145 1146 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1147 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1148 1149 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1150 double Tpre_rounded[DML2_MAX_PLANES]; 1151 double Tpre_oto[DML2_MAX_PLANES]; 1152 bool recalc_prefetch_schedule; 1153 bool recalc_prefetch_done; 1154 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1155 double line_times[DML2_MAX_PLANES]; 1156 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1157 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1158 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1159 double prefetch_swath_time_us[DML2_MAX_PLANES]; 1160 }; 1161 1162 struct dml2_core_calcs_mode_programming_locals { 1163 double PixelClockBackEnd[DML2_MAX_PLANES]; 1164 double OutputBpp[DML2_MAX_PLANES]; 1165 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 1166 unsigned int MaxTotalDETInKByte; 1167 unsigned int NomDETInKByte; 1168 unsigned int MinCompressedBufferSizeInKByte; 1169 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 1170 1171 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1172 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1173 double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1174 unsigned int dummy_integer_array[4][DML2_MAX_PLANES]; 1175 enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES]; 1176 double dummy_single_array[2][DML2_MAX_PLANES]; 1177 unsigned int dummy_long_array[8][DML2_MAX_PLANES]; 1178 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1179 bool dummy_boolean[2]; 1180 double dummy_single[2]; 1181 struct dml2_core_internal_watermarks dummy_watermark; 1182 1183 unsigned int DSCFormatFactor; 1184 struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES]; 1185 unsigned int ReorderingBytes; 1186 double HostVMInefficiencyFactor; 1187 double HostVMInefficiencyFactorPrefetch; 1188 unsigned int TotalDCCActiveDPP; 1189 unsigned int TotalActiveDPP; 1190 unsigned int Total3dlutActive; 1191 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 1192 bool immediate_flip_required; // any pipes need immediate flip 1193 bool DestinationLineTimesForPrefetchLessThan2; 1194 bool VRatioPrefetchMoreThanMax; 1195 double MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1196 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1197 double Tvstartup_margin; 1198 double dlg_vblank_start; 1199 double LSetup; 1200 double blank_lines_remaining; 1201 double WRBandwidth; 1202 struct dml2_core_internal_DmlPipe myPipe; 1203 double PixelClockBackEndFactor; 1204 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1205 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1206 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1207 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1208 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1209 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1210 1211 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1212 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1213 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1214 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1215 1216 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1217 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1218 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1219 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1220 double tdlut_opt_time[DML2_MAX_PLANES]; 1221 double tdlut_drain_time[DML2_MAX_PLANES]; 1222 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1223 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1224 1225 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1226 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1227 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1228 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1229 1230 double Tvm_trips[DML2_MAX_PLANES]; 1231 double Tr0_trips[DML2_MAX_PLANES]; 1232 double Tvm_trips_flip[DML2_MAX_PLANES]; 1233 double Tr0_trips_flip[DML2_MAX_PLANES]; 1234 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1235 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1236 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1237 1238 unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1239 unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1240 1241 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1242 double Tpre_rounded[DML2_MAX_PLANES]; 1243 double Tpre_oto[DML2_MAX_PLANES]; 1244 bool recalc_prefetch_schedule; 1245 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1246 double line_times[DML2_MAX_PLANES]; 1247 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1248 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1249 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1250 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 1251 bool dsc_enable[DML2_MAX_PLANES]; 1252 }; 1253 1254 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals { 1255 double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES]; 1256 double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES]; 1257 double USRRetrainingLatencyMargin[DML2_MAX_PLANES]; 1258 double g6_temp_read_latency_margin[DML2_MAX_PLANES]; 1259 double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES]; 1260 1261 double EffectiveLBLatencyHidingY; 1262 double EffectiveLBLatencyHidingC; 1263 double LinesInDETY[DML2_MAX_PLANES]; 1264 double LinesInDETC[DML2_MAX_PLANES]; 1265 unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES]; 1266 unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES]; 1267 double FullDETBufferingTimeY; 1268 double FullDETBufferingTimeC; 1269 double WritebackDRAMClockChangeLatencyMargin; 1270 double WritebackFCLKChangeLatencyMargin; 1271 double WritebackLatencyHiding; 1272 1273 unsigned int TotalActiveWriteback; 1274 unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES]; 1275 unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES]; 1276 double TotalPixelBW; 1277 double EffectiveDETBufferSizeY; 1278 double ActiveClockChangeLatencyHidingY; 1279 double ActiveClockChangeLatencyHidingC; 1280 double ActiveClockChangeLatencyHiding; 1281 unsigned int dst_y_pstate; 1282 unsigned int src_y_pstate_l; 1283 unsigned int src_y_pstate_c; 1284 unsigned int src_y_ahead_l; 1285 unsigned int src_y_ahead_c; 1286 unsigned int sub_vp_lines_l; 1287 unsigned int sub_vp_lines_c; 1288 1289 }; 1290 1291 struct dml2_core_calcs_CalculateVMRowAndSwath_locals { 1292 unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES]; 1293 unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES]; 1294 unsigned int vm_bytes_l; 1295 unsigned int vm_bytes_c; 1296 unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES]; 1297 unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES]; 1298 unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES]; 1299 unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES]; 1300 unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES]; 1301 unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES]; 1302 unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1303 unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES]; 1304 unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1305 unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES]; 1306 bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES]; 1307 unsigned int HostVMDynamicLevels; 1308 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1309 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1310 }; 1311 1312 struct dml2_core_calcs_CalculateVMRowAndSwath_params { 1313 const struct dml2_display_cfg *display_cfg; 1314 unsigned int NumberOfActiveSurfaces; 1315 struct dml2_core_internal_DmlPipe *myPipe; 1316 unsigned int *SurfaceSizeInMALL; 1317 unsigned int PTEBufferSizeInRequestsLuma; 1318 unsigned int PTEBufferSizeInRequestsChroma; 1319 unsigned int MALLAllocatedForDCN; 1320 unsigned int *SwathWidthY; 1321 unsigned int *SwathWidthC; 1322 unsigned int HostVMMinPageSize; 1323 unsigned int DCCMetaBufferSizeBytes; 1324 bool mrq_present; 1325 enum dml2_pstate_method *uclk_pstate_switch_modes; 1326 1327 // Output 1328 bool *PTEBufferSizeNotExceeded; 1329 bool *DCCMetaBufferSizeNotExceeded; 1330 1331 unsigned int *dpte_row_width_luma_ub; 1332 unsigned int *dpte_row_width_chroma_ub; 1333 unsigned int *dpte_row_height_luma; 1334 unsigned int *dpte_row_height_chroma; 1335 unsigned int *dpte_row_height_linear_luma; // VBA_DELTA 1336 unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA 1337 1338 unsigned int *vm_group_bytes; 1339 unsigned int *dpte_group_bytes; 1340 unsigned int *PixelPTEReqWidthY; 1341 unsigned int *PixelPTEReqHeightY; 1342 unsigned int *PTERequestSizeY; 1343 unsigned int *vmpg_width_y; 1344 unsigned int *vmpg_height_y; 1345 1346 unsigned int *PixelPTEReqWidthC; 1347 unsigned int *PixelPTEReqHeightC; 1348 unsigned int *PTERequestSizeC; 1349 unsigned int *vmpg_width_c; 1350 unsigned int *vmpg_height_c; 1351 1352 unsigned int *dpde0_bytes_per_frame_ub_l; 1353 unsigned int *dpde0_bytes_per_frame_ub_c; 1354 1355 unsigned int *PrefetchSourceLinesY; 1356 unsigned int *PrefetchSourceLinesC; 1357 unsigned int *VInitPreFillY; 1358 unsigned int *VInitPreFillC; 1359 unsigned int *MaxNumSwathY; 1360 unsigned int *MaxNumSwathC; 1361 double *dpte_row_bw; 1362 unsigned int *PixelPTEBytesPerRow; 1363 unsigned int *dpte_row_bytes_per_row_l; 1364 unsigned int *dpte_row_bytes_per_row_c; 1365 unsigned int *vm_bytes; 1366 bool *use_one_row_for_frame; 1367 bool *use_one_row_for_frame_flip; 1368 bool *is_using_mall_for_ss; 1369 bool *PTE_BUFFER_MODE; 1370 unsigned int *BIGK_FRAGMENT_SIZE; 1371 1372 // MRQ 1373 unsigned int *meta_req_width_luma; 1374 unsigned int *meta_req_height_luma; 1375 unsigned int *meta_row_width_luma; 1376 unsigned int *meta_row_height_luma; 1377 unsigned int *meta_pte_bytes_per_frame_ub_l; 1378 1379 unsigned int *meta_req_width_chroma; 1380 unsigned int *meta_req_height_chroma; 1381 unsigned int *meta_row_width_chroma; 1382 unsigned int *meta_row_height_chroma; 1383 unsigned int *meta_pte_bytes_per_frame_ub_c; 1384 double *meta_row_bw; 1385 unsigned int *meta_row_bytes; 1386 unsigned int *meta_row_bytes_per_row_ub_l; 1387 unsigned int *meta_row_bytes_per_row_ub_c; 1388 }; 1389 1390 struct dml2_core_calcs_CalculatePrefetchSchedule_locals { 1391 bool NoTimeToPrefetch; 1392 unsigned int DPPCycles; 1393 unsigned int DISPCLKCycles; 1394 double DSTTotalPixelsAfterScaler; 1395 double LineTime; 1396 double dst_y_prefetch_equ; 1397 double prefetch_bw_oto; 1398 double per_pipe_vactive_sw_bw; 1399 double Tvm_oto; 1400 double Tr0_oto; 1401 double Tvm_oto_lines; 1402 double Tr0_oto_lines; 1403 double dst_y_prefetch_oto; 1404 double TimeForFetchingVM; 1405 double TimeForFetchingRowInVBlank; 1406 double LinesToRequestPrefetchPixelData; 1407 unsigned int HostVMDynamicLevelsTrips; 1408 double trip_to_mem; 1409 double Tvm_trips_rounded; 1410 double Tr0_trips_rounded; 1411 double max_Tsw; 1412 double Lsw_oto; 1413 double prefetch_bw_equ; 1414 double Tvm_equ; 1415 double Tr0_equ; 1416 double Tdmbf; 1417 double Tdmec; 1418 double Tdmsks; 1419 double total_row_bytes; 1420 double prefetch_bw_pr; 1421 double bytes_pp; 1422 double dep_bytes; 1423 double min_Lsw_oto; 1424 double min_Lsw_equ; 1425 double Tsw_est1; 1426 double Tsw_est2; 1427 double Tsw_est3; 1428 double prefetch_bw1; 1429 double prefetch_bw2; 1430 double prefetch_bw3; 1431 double prefetch_bw4; 1432 double dst_y_prefetch_equ_impacted; 1433 1434 double TWait_p; 1435 unsigned int cursor_prefetch_bytes; 1436 }; 1437 1438 struct dml2_core_shared_calculate_det_buffer_size_params { 1439 const struct dml2_display_cfg *display_cfg; 1440 bool ForceSingleDPP; 1441 unsigned int NumberOfActiveSurfaces; 1442 bool UnboundedRequestEnabled; 1443 unsigned int nomDETInKByte; 1444 unsigned int MaxTotalDETInKByte; 1445 unsigned int ConfigReturnBufferSizeInKByte; 1446 unsigned int MinCompressedBufferSizeInKByte; 1447 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1448 unsigned int CompressedBufferSegmentSizeInkByte; 1449 double *ReadBandwidthLuma; 1450 double *ReadBandwidthChroma; 1451 unsigned int *full_swath_bytes_l; 1452 unsigned int *full_swath_bytes_c; 1453 unsigned int *swath_time_value_us; 1454 unsigned int *DPPPerSurface; 1455 bool TryToAllocateForWriteLatency; 1456 unsigned int bestEffortMinActiveLatencyHidingUs; 1457 1458 // Output 1459 unsigned int *DETBufferSizeInKByte; 1460 unsigned int *CompressedBufferSizeInkByte; 1461 }; 1462 1463 struct dml2_core_shared_calculate_vm_and_row_bytes_params { 1464 bool ViewportStationary; 1465 bool DCCEnable; 1466 unsigned int NumberOfDPPs; 1467 unsigned int BlockHeight256Bytes; 1468 unsigned int BlockWidth256Bytes; 1469 enum dml2_source_format_class SourcePixelFormat; 1470 unsigned int SurfaceTiling; 1471 unsigned int BytePerPixel; 1472 enum dml2_rotation_angle RotationAngle; 1473 unsigned int SwathWidth; // per pipe 1474 unsigned int ViewportHeight; 1475 unsigned int ViewportXStart; 1476 unsigned int ViewportYStart; 1477 bool GPUVMEnable; 1478 unsigned int GPUVMMaxPageTableLevels; 1479 unsigned int GPUVMMinPageSizeKBytes; 1480 unsigned int PTEBufferSizeInRequests; 1481 unsigned int Pitch; 1482 unsigned int MacroTileWidth; 1483 unsigned int MacroTileHeight; 1484 bool is_phantom; 1485 unsigned int DCCMetaPitch; 1486 bool mrq_present; 1487 1488 // Output 1489 unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation 1490 unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check 1491 unsigned int *dpte_row_width_ub; 1492 unsigned int *dpte_row_height; 1493 unsigned int *dpte_row_height_linear; 1494 unsigned int *PixelPTEBytesPerRow_one_row_per_frame; 1495 unsigned int *dpte_row_width_ub_one_row_per_frame; 1496 unsigned int *dpte_row_height_one_row_per_frame; 1497 unsigned int *vmpg_width; 1498 unsigned int *vmpg_height; 1499 unsigned int *PixelPTEReqWidth; 1500 unsigned int *PixelPTEReqHeight; 1501 unsigned int *PTERequestSize; 1502 unsigned int *dpde0_bytes_per_frame_ub; 1503 1504 unsigned int *meta_row_bytes; 1505 unsigned int *MetaRequestWidth; 1506 unsigned int *MetaRequestHeight; 1507 unsigned int *meta_row_width; 1508 unsigned int *meta_row_height; 1509 unsigned int *meta_pte_bytes_per_frame_ub; 1510 }; 1511 1512 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals { 1513 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES]; 1514 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES]; 1515 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES]; 1516 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES]; 1517 unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES]; 1518 unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES]; 1519 unsigned int SwathTimeValueUs[DML2_MAX_PLANES]; 1520 1521 struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params; 1522 }; 1523 1524 struct dml2_core_shared_TruncToValidBPP_locals { 1525 }; 1526 1527 struct dml2_core_shared_CalculateDETBufferSize_locals { 1528 unsigned int DETBufferSizePoolInKByte; 1529 unsigned int NextDETBufferPieceInKByte; 1530 unsigned int NextSurfaceToAssignDETPiece; 1531 double TotalBandwidth; 1532 double BandwidthOfSurfacesNotAssignedDETPiece; 1533 unsigned int max_minDET; 1534 unsigned int minDET; 1535 unsigned int minDET_pipe; 1536 unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES]; 1537 unsigned int TotalPixelRate; 1538 unsigned int DETBudgetPerStream[DML2_MAX_PLANES]; 1539 unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES]; 1540 unsigned int IdealDETBudget, DeltaDETBudget; 1541 unsigned int ResidualDETAfterRounding; 1542 }; 1543 1544 struct dml2_core_shared_get_urgent_bandwidth_required_locals { 1545 double required_bandwidth_mbps; 1546 double required_bandwidth_mbps_this_surface; 1547 double adj_factor_p0; 1548 double adj_factor_p1; 1549 double adj_factor_cur; 1550 double adj_factor_p0_pre; 1551 double adj_factor_p1_pre; 1552 double adj_factor_cur_pre; 1553 double per_plane_flip_bw[DML2_MAX_PLANES]; 1554 double mall_svp_prefetch_factor; 1555 double tmp_nom_adj_factor_p0; 1556 double tmp_nom_adj_factor_p1; 1557 double tmp_pref_adj_factor_p0; 1558 double tmp_pref_adj_factor_p1; 1559 double vm_row_bw; 1560 double flip_and_active_bw; 1561 double flip_and_prefetch_bw; 1562 double flip_and_prefetch_bw_max; 1563 double active_and_excess_bw; 1564 }; 1565 1566 struct dml2_core_shared_calculate_peak_bandwidth_required_locals { 1567 double unity_array[DML2_MAX_PLANES]; 1568 double zero_array[DML2_MAX_PLANES]; 1569 double surface_dummy_bw[DML2_MAX_PLANES]; 1570 }; 1571 1572 struct dml2_core_shared_CalculateFlipSchedule_locals { 1573 double min_row_time; 1574 double Tvm_flip; 1575 double Tr0_flip; 1576 double ImmediateFlipBW; 1577 double dpte_row_bytes; 1578 double min_row_height; 1579 double min_row_height_chroma; 1580 double max_flip_time; 1581 double lb_flip_bw; 1582 double hvm_scaled_vm_bytes; 1583 double num_rows; 1584 double hvm_scaled_row_bytes; 1585 double hvm_scaled_vm_row_bytes; 1586 bool dual_plane; 1587 }; 1588 1589 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals { 1590 unsigned int plane_idx; 1591 unsigned int stream_idx; 1592 enum dml2_source_format_class source_format; 1593 const struct dml2_timing_cfg *timing; 1594 bool dual_plane; 1595 enum dml2_odm_mode odm_mode; 1596 1597 unsigned int htotal; 1598 unsigned int hactive; 1599 unsigned int hblank_end; 1600 unsigned int vblank_end; 1601 bool interlaced; 1602 double pclk_freq_in_mhz; 1603 double refclk_freq_in_mhz; 1604 double ref_freq_to_pix_freq; 1605 1606 unsigned int num_active_pipes; 1607 unsigned int first_pipe_idx_in_plane; 1608 unsigned int pipe_idx_in_combine; 1609 unsigned int odm_combine_factor; 1610 1611 double min_ttu_vblank; 1612 unsigned int min_dst_y_next_start; 1613 1614 unsigned int vready_after_vcount0; 1615 1616 unsigned int dst_x_after_scaler; 1617 unsigned int dst_y_after_scaler; 1618 1619 double dst_y_prefetch; 1620 double dst_y_per_vm_vblank; 1621 double dst_y_per_row_vblank; 1622 double dst_y_per_vm_flip; 1623 double dst_y_per_row_flip; 1624 1625 double max_dst_y_per_vm_vblank; 1626 double max_dst_y_per_row_vblank; 1627 1628 double vratio_pre_l; 1629 double vratio_pre_c; 1630 1631 double refcyc_per_line_delivery_pre_l; 1632 double refcyc_per_line_delivery_l; 1633 1634 double refcyc_per_line_delivery_pre_c; 1635 double refcyc_per_line_delivery_c; 1636 1637 double refcyc_per_req_delivery_pre_l; 1638 double refcyc_per_req_delivery_l; 1639 1640 double refcyc_per_req_delivery_pre_c; 1641 double refcyc_per_req_delivery_c; 1642 1643 double dst_y_per_pte_row_nom_l; 1644 double dst_y_per_pte_row_nom_c; 1645 double refcyc_per_pte_group_nom_l; 1646 double refcyc_per_pte_group_nom_c; 1647 double refcyc_per_pte_group_vblank_l; 1648 double refcyc_per_pte_group_vblank_c; 1649 double refcyc_per_pte_group_flip_l; 1650 double refcyc_per_pte_group_flip_c; 1651 double refcyc_per_tdlut_group; 1652 1653 double dst_y_per_meta_row_nom_l; 1654 double dst_y_per_meta_row_nom_c; 1655 double refcyc_per_meta_chunk_nom_l; 1656 double refcyc_per_meta_chunk_nom_c; 1657 double refcyc_per_meta_chunk_vblank_l; 1658 double refcyc_per_meta_chunk_vblank_c; 1659 double refcyc_per_meta_chunk_flip_l; 1660 double refcyc_per_meta_chunk_flip_c; 1661 }; 1662 1663 struct dml2_core_shared_CalculateMetaAndPTETimes_params { 1664 struct dml2_core_internal_scratch *scratch; 1665 const struct dml2_display_cfg *display_cfg; 1666 unsigned int NumberOfActiveSurfaces; 1667 bool *use_one_row_for_frame; 1668 double *dst_y_per_row_vblank; 1669 double *dst_y_per_row_flip; 1670 unsigned int *BytePerPixelY; 1671 unsigned int *BytePerPixelC; 1672 unsigned int *dpte_row_height; 1673 unsigned int *dpte_row_height_chroma; 1674 unsigned int *dpte_group_bytes; 1675 unsigned int *PTERequestSizeY; 1676 unsigned int *PTERequestSizeC; 1677 unsigned int *PixelPTEReqWidthY; 1678 unsigned int *PixelPTEReqHeightY; 1679 unsigned int *PixelPTEReqWidthC; 1680 unsigned int *PixelPTEReqHeightC; 1681 unsigned int *dpte_row_width_luma_ub; 1682 unsigned int *dpte_row_width_chroma_ub; 1683 unsigned int *tdlut_groups_per_2row_ub; 1684 bool mrq_present; 1685 unsigned int MetaChunkSize; 1686 unsigned int MinMetaChunkSizeBytes; 1687 unsigned int *meta_row_width; 1688 unsigned int *meta_row_width_chroma; 1689 unsigned int *meta_row_height; 1690 unsigned int *meta_row_height_chroma; 1691 unsigned int *meta_req_width; 1692 unsigned int *meta_req_width_chroma; 1693 unsigned int *meta_req_height; 1694 unsigned int *meta_req_height_chroma; 1695 1696 // Output 1697 double *time_per_tdlut_group; 1698 double *DST_Y_PER_PTE_ROW_NOM_L; 1699 double *DST_Y_PER_PTE_ROW_NOM_C; 1700 double *time_per_pte_group_nom_luma; 1701 double *time_per_pte_group_vblank_luma; 1702 double *time_per_pte_group_flip_luma; 1703 double *time_per_pte_group_nom_chroma; 1704 double *time_per_pte_group_vblank_chroma; 1705 double *time_per_pte_group_flip_chroma; 1706 1707 double *DST_Y_PER_META_ROW_NOM_L; 1708 double *DST_Y_PER_META_ROW_NOM_C; 1709 1710 double *TimePerMetaChunkNominal; 1711 double *TimePerChromaMetaChunkNominal; 1712 double *TimePerMetaChunkVBlank; 1713 double *TimePerChromaMetaChunkVBlank; 1714 double *TimePerMetaChunkFlip; 1715 double *TimePerChromaMetaChunkFlip; 1716 }; 1717 1718 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params { 1719 const struct dml2_display_cfg *display_cfg; 1720 bool USRRetrainingRequired; 1721 unsigned int NumberOfActiveSurfaces; 1722 unsigned int MaxLineBufferLines; 1723 unsigned int LineBufferSize; 1724 unsigned int WritebackInterfaceBufferSize; 1725 double DCFCLK; 1726 double ReturnBW; 1727 bool SynchronizeTimings; 1728 bool SynchronizeDRRDisplaysForUCLKPStateChange; 1729 const unsigned int *dpte_group_bytes; 1730 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1731 unsigned int WritebackChunkSize; 1732 double SOCCLK; 1733 double DCFClkDeepSleep; 1734 const unsigned int *DETBufferSizeY; 1735 const unsigned int *DETBufferSizeC; 1736 const unsigned int *SwathHeightY; 1737 const unsigned int *SwathHeightC; 1738 const unsigned int *SwathWidthY; 1739 const unsigned int *SwathWidthC; 1740 const unsigned int *DPPPerSurface; 1741 const double *BytePerPixelDETY; 1742 const double *BytePerPixelDETC; 1743 const unsigned int *DSTXAfterScaler; 1744 const unsigned int *DSTYAfterScaler; 1745 bool UnboundedRequestEnabled; 1746 unsigned int CompressedBufferSizeInkByte; 1747 bool max_outstanding_when_urgent_expected; 1748 const unsigned int max_outstanding_requests; 1749 const unsigned int max_request_size_bytes; 1750 const unsigned int *meta_row_height_l; 1751 const unsigned int *meta_row_height_c; 1752 const enum dml2_pstate_method *uclk_pstate_switch_modes; 1753 1754 // Output 1755 struct dml2_core_internal_watermarks *Watermark; 1756 enum dml2_pstate_change_support *DRAMClockChangeSupport; 1757 bool *global_dram_clock_change_support_required; 1758 bool *global_dram_clock_change_supported; 1759 double *MaxActiveDRAMClockChangeLatencySupported; 1760 unsigned int *SubViewportLinesNeededInMALL; 1761 enum dml2_pstate_change_support *FCLKChangeSupport; 1762 bool *global_fclk_change_supported; 1763 double *MaxActiveFCLKChangeLatencySupported; 1764 bool *USRRetrainingSupport; 1765 double *VActiveLatencyHidingMargin; 1766 double *VActiveLatencyHidingUs; 1767 bool *g6_temp_read_support; 1768 enum dml2_pstate_change_support *temp_read_or_ppt_support; 1769 bool *global_temp_read_or_ppt_supported; 1770 }; 1771 1772 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { 1773 const struct dml2_display_cfg *display_cfg; 1774 unsigned int ConfigReturnBufferSizeInKByte; 1775 unsigned int MaxTotalDETInKByte; 1776 unsigned int MinCompressedBufferSizeInKByte; 1777 unsigned int rob_buffer_size_kbytes; 1778 unsigned int pixel_chunk_size_kbytes; 1779 bool ForceSingleDPP; 1780 unsigned int NumberOfActiveSurfaces; 1781 unsigned int nomDETInKByte; 1782 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1783 unsigned int CompressedBufferSegmentSizeInkByte; 1784 double *ReadBandwidthLuma; 1785 double *ReadBandwidthChroma; 1786 double *MaximumSwathWidthLuma; 1787 double *MaximumSwathWidthChroma; 1788 unsigned int *Read256BytesBlockHeightY; 1789 unsigned int *Read256BytesBlockHeightC; 1790 unsigned int *Read256BytesBlockWidthY; 1791 unsigned int *Read256BytesBlockWidthC; 1792 bool *surf_linear128_l; 1793 bool *surf_linear128_c; 1794 enum dml2_odm_mode *ODMMode; 1795 unsigned int *BytePerPixY; 1796 unsigned int *BytePerPixC; 1797 double *BytePerPixDETY; 1798 double *BytePerPixDETC; 1799 unsigned int *DPPPerSurface; 1800 bool mrq_present; 1801 unsigned int dummy[2][DML2_MAX_PLANES]; 1802 unsigned int swath_width_luma_ub_single_dpp[DML2_MAX_PLANES]; 1803 unsigned int swath_width_chroma_ub_single_dpp[DML2_MAX_PLANES]; 1804 1805 // output 1806 unsigned int *req_per_swath_ub_l; 1807 unsigned int *req_per_swath_ub_c; 1808 unsigned int *swath_width_luma_ub; 1809 unsigned int *swath_width_chroma_ub; 1810 unsigned int *SwathWidth; 1811 unsigned int *SwathWidthChroma; 1812 unsigned int *SwathHeightY; 1813 unsigned int *SwathHeightC; 1814 unsigned int *request_size_bytes_luma; 1815 unsigned int *request_size_bytes_chroma; 1816 unsigned int *DETBufferSizeInKByte; 1817 unsigned int *DETBufferSizeY; 1818 unsigned int *DETBufferSizeC; 1819 unsigned int *full_swath_bytes_l; 1820 unsigned int *full_swath_bytes_c; 1821 unsigned int *full_swath_bytes_single_dpp_l; 1822 unsigned int *full_swath_bytes_single_dpp_c; 1823 bool *UnboundedRequestEnabled; 1824 unsigned int *compbuf_reserved_space_64b; 1825 unsigned int *CompressedBufferSizeInkByte; 1826 bool *ViewportSizeSupportPerSurface; 1827 bool *ViewportSizeSupport; 1828 bool *hw_debug5; 1829 1830 struct dml2_core_shared_calculation_funcs *funcs; 1831 }; 1832 1833 struct dml2_core_calcs_CalculateStutterEfficiency_locals { 1834 double DETBufferingTimeY; 1835 double SwathWidthYCriticalSurface; 1836 double SwathHeightYCriticalSurface; 1837 double VActiveTimeCriticalSurface; 1838 double FrameTimeCriticalSurface; 1839 unsigned int BytePerPixelYCriticalSurface; 1840 unsigned int DETBufferSizeYCriticalSurface; 1841 double MinTTUVBlankCriticalSurface; 1842 unsigned int BlockWidth256BytesYCriticalSurface; 1843 bool SinglePlaneCriticalSurface; 1844 bool SinglePipeCriticalSurface; 1845 double TotalCompressedReadBandwidth; 1846 double TotalRowReadBandwidth; 1847 double AverageDCCCompressionRate; 1848 double EffectiveCompressedBufferSize; 1849 double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; 1850 double StutterBurstTime; 1851 unsigned int TotalActiveWriteback; 1852 double LinesInDETY; 1853 double LinesInDETYRoundedDownToSwath; 1854 double MaximumEffectiveCompressionLuma; 1855 double MaximumEffectiveCompressionChroma; 1856 double TotalZeroSizeRequestReadBandwidth; 1857 double TotalZeroSizeCompressedReadBandwidth; 1858 double AverageDCCZeroSizeFraction; 1859 double AverageZeroSizeCompressionRate; 1860 bool stream_visited[DML2_MAX_PLANES]; 1861 }; 1862 1863 struct dml2_core_calcs_CalculateStutterEfficiency_params { 1864 const struct dml2_display_cfg *display_cfg; 1865 unsigned int CompressedBufferSizeInkByte; 1866 bool UnboundedRequestEnabled; 1867 unsigned int MetaFIFOSizeInKEntries; 1868 unsigned int ZeroSizeBufferEntries; 1869 unsigned int PixelChunkSizeInKByte; 1870 unsigned int NumberOfActiveSurfaces; 1871 unsigned int ROBBufferSizeInKByte; 1872 double TotalDataReadBandwidth; 1873 double DCFCLK; 1874 double ReturnBW; 1875 unsigned int CompbufReservedSpace64B; 1876 unsigned int CompbufReservedSpaceZs; 1877 bool hw_debug5; 1878 double SRExitTime; 1879 double SRExitTimeLowPower; 1880 double SRExitZ8Time; 1881 bool SynchronizeTimings; 1882 double StutterEnterPlusExitWatermark; 1883 double LowPowerStutterEnterPlusExitWatermark; 1884 double Z8StutterEnterPlusExitWatermark; 1885 bool ProgressiveToInterlaceUnitInOPP; 1886 double *MinTTUVBlank; 1887 unsigned int *DPPPerSurface; 1888 unsigned int *DETBufferSizeY; 1889 unsigned int *BytePerPixelY; 1890 double *BytePerPixelDETY; 1891 unsigned int *SwathWidthY; 1892 unsigned int *SwathHeightY; 1893 unsigned int *SwathHeightC; 1894 unsigned int *BlockHeight256BytesY; 1895 unsigned int *BlockWidth256BytesY; 1896 unsigned int *BlockHeight256BytesC; 1897 unsigned int *BlockWidth256BytesC; 1898 unsigned int *DCCYMaxUncompressedBlock; 1899 unsigned int *DCCCMaxUncompressedBlock; 1900 double *ReadBandwidthSurfaceLuma; 1901 double *ReadBandwidthSurfaceChroma; 1902 double *meta_row_bw; 1903 double *dpte_row_bw; 1904 bool rob_alloc_compressed; 1905 1906 // output 1907 double *StutterEfficiencyNotIncludingVBlank; 1908 double *StutterEfficiency; 1909 double *LowPowerStutterEfficiencyNotIncludingVBlank; 1910 double *LowPowerStutterEfficiency; 1911 unsigned int *NumberOfStutterBurstsPerFrame; 1912 unsigned int *LowPowerNumberOfStutterBurstsPerFrame; 1913 double *Z8StutterEfficiencyNotIncludingVBlank; 1914 double *Z8StutterEfficiency; 1915 unsigned int *Z8NumberOfStutterBurstsPerFrame; 1916 double *StutterPeriod; 1917 bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1918 }; 1919 1920 struct dml2_core_calcs_CalculatePrefetchSchedule_params { 1921 const struct dml2_display_cfg *display_cfg; 1922 double HostVMInefficiencyFactor; 1923 struct dml2_core_internal_DmlPipe *myPipe; 1924 unsigned int DSCDelay; 1925 double DPPCLKDelaySubtotalPlusCNVCFormater; 1926 double DPPCLKDelaySCL; 1927 double DPPCLKDelaySCLLBOnly; 1928 double DPPCLKDelayCNVCCursor; 1929 double DISPCLKDelaySubtotal; 1930 unsigned int DPP_RECOUT_WIDTH; 1931 enum dml2_output_format_class OutputFormat; 1932 unsigned int MaxInterDCNTileRepeaters; 1933 unsigned int VStartup; 1934 unsigned int HostVMMinPageSize; 1935 bool DynamicMetadataEnable; 1936 bool DynamicMetadataVMEnabled; 1937 unsigned int DynamicMetadataLinesBeforeActiveRequired; 1938 unsigned int DynamicMetadataTransmittedBytes; 1939 double ExtraLatencyPrefetch; 1940 double TCalc; 1941 unsigned int vm_bytes; 1942 unsigned int PixelPTEBytesPerRow; 1943 double PrefetchSourceLinesY; 1944 unsigned int VInitPreFillY; 1945 unsigned int MaxNumSwathY; 1946 double PrefetchSourceLinesC; 1947 unsigned int VInitPreFillC; 1948 unsigned int MaxNumSwathC; 1949 unsigned int swath_width_luma_ub; // per-pipe 1950 unsigned int swath_width_chroma_ub; // per-pipe 1951 unsigned int SwathHeightY; 1952 unsigned int SwathHeightC; 1953 double TWait; 1954 double Ttrip; 1955 double Turg; 1956 bool setup_for_tdlut; 1957 bool use_max_lsw; 1958 unsigned int tdlut_pte_bytes_per_frame; 1959 unsigned int tdlut_bytes_per_frame; 1960 double tdlut_opt_time; 1961 double tdlut_drain_time; 1962 1963 unsigned int num_cursors; 1964 unsigned int cursor_bytes_per_chunk; 1965 unsigned int cursor_bytes_per_line; 1966 1967 // MRQ 1968 bool dcc_enable; 1969 bool mrq_present; 1970 unsigned int meta_row_bytes; 1971 double mall_prefetch_sdp_overhead_factor; 1972 1973 double impacted_dst_y_pre; 1974 double vactive_sw_bw_l; // per surface bw 1975 double vactive_sw_bw_c; // per surface bw 1976 1977 // output 1978 unsigned int *DSTXAfterScaler; 1979 unsigned int *DSTYAfterScaler; 1980 double *dst_y_prefetch; 1981 double *dst_y_per_vm_vblank; 1982 double *dst_y_per_row_vblank; 1983 double *VRatioPrefetchY; 1984 double *VRatioPrefetchC; 1985 double *RequiredPrefetchPixelDataBWLuma; 1986 double *RequiredPrefetchPixelDataBWChroma; 1987 double *RequiredPrefetchBWMax; 1988 bool *NotEnoughTimeForDynamicMetadata; 1989 double *Tno_bw; 1990 double *Tno_bw_flip; 1991 double *prefetch_vmrow_bw; 1992 double *Tdmdl_vm; 1993 double *Tdmdl; 1994 double *TSetup; 1995 double *Tpre_rounded; 1996 double *Tpre_oto; 1997 double *Tvm_trips; 1998 double *Tr0_trips; 1999 double *Tvm_trips_flip; 2000 double *Tr0_trips_flip; 2001 double *Tvm_trips_flip_rounded; 2002 double *Tr0_trips_flip_rounded; 2003 unsigned int *VUpdateOffsetPix; 2004 unsigned int *VUpdateWidthPix; 2005 unsigned int *VReadyOffsetPix; 2006 double *prefetch_cursor_bw; 2007 double *prefetch_sw_bytes; 2008 double *prefetch_swath_time_us; 2009 }; 2010 2011 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params { 2012 unsigned int num_active_planes; 2013 enum dml2_source_format_class *pixel_format; 2014 unsigned int rob_buffer_size_kbytes; 2015 unsigned int compressed_buffer_size_kbytes; 2016 unsigned int chunk_bytes_l; // same for all planes 2017 unsigned int chunk_bytes_c; 2018 unsigned int *detile_buffer_size_bytes_l; 2019 unsigned int *detile_buffer_size_bytes_c; 2020 unsigned int *full_swath_bytes_l; 2021 unsigned int *full_swath_bytes_c; 2022 unsigned int *lb_source_lines_l; 2023 unsigned int *lb_source_lines_c; 2024 unsigned int *swath_height_l; 2025 unsigned int *swath_height_c; 2026 double *prefetch_sw_bytes; 2027 double *Tpre_rounded; 2028 double *Tpre_oto; 2029 double estimated_dcfclk_mhz; 2030 double estimated_urg_bandwidth_required_mbps; 2031 double *line_time; 2032 double *dst_y_prefetch; 2033 2034 // output 2035 bool *recalc_prefetch_schedule; 2036 double *impacted_dst_y_pre; 2037 }; 2038 2039 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals { 2040 unsigned int max_Trpd_dcfclk_cycles; 2041 unsigned int burst_bytes_to_fill_det; 2042 double time_to_fill_det_us; 2043 unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES]; 2044 bool prefetch_global_check_passed; 2045 unsigned int src_swath_bytes_l[DML2_MAX_PLANES]; 2046 unsigned int src_swath_bytes_c[DML2_MAX_PLANES]; 2047 unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES]; 2048 unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES]; 2049 }; 2050 2051 struct dml2_core_calcs_calculate_mcache_row_bytes_params { 2052 unsigned int num_chans; 2053 unsigned int mem_word_bytes; 2054 unsigned int mcache_size_bytes; 2055 unsigned int mcache_line_size_bytes; 2056 unsigned int gpuvm_enable; 2057 unsigned int gpuvm_page_size_kbytes; 2058 2059 //enum dml_rotation_angle rotation_angle; 2060 bool surf_vert; 2061 unsigned int vp_stationary; 2062 unsigned int tiling_mode; 2063 bool imall_enable; 2064 2065 unsigned int vp_start_x; 2066 unsigned int vp_start_y; 2067 unsigned int full_vp_width; 2068 unsigned int full_vp_height; 2069 unsigned int blk_width; 2070 unsigned int blk_height; 2071 unsigned int vmpg_width; 2072 unsigned int vmpg_height; 2073 unsigned int full_swath_bytes; 2074 unsigned int bytes_per_pixel; 2075 2076 // output 2077 unsigned int *num_mcaches; 2078 unsigned int *mcache_row_bytes; 2079 unsigned int *mcache_row_bytes_per_channel; 2080 unsigned int *meta_row_width_ub; 2081 double *dcc_dram_bw_nom_overhead_factor; 2082 double *dcc_dram_bw_pref_overhead_factor; 2083 unsigned int *mvmpg_width; 2084 unsigned int *mvmpg_height; 2085 unsigned int *full_vp_access_width_mvmpg_aligned; 2086 unsigned int *mvmpg_per_mcache_lb; 2087 }; 2088 2089 struct dml2_core_shared_calculate_mcache_setting_locals { 2090 struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p; 2091 struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p; 2092 2093 bool is_dual_plane; 2094 unsigned int mvmpg_width_l; 2095 unsigned int mvmpg_height_l; 2096 unsigned int full_vp_access_width_mvmpg_aligned_l; 2097 unsigned int mvmpg_per_mcache_lb_l; 2098 unsigned int meta_row_width_l; 2099 2100 unsigned int mvmpg_width_c; 2101 unsigned int mvmpg_height_c; 2102 unsigned int full_vp_access_width_mvmpg_aligned_c; 2103 unsigned int mvmpg_per_mcache_lb_c; 2104 unsigned int meta_row_width_c; 2105 2106 unsigned int lc_comb_last_mcache_size; 2107 double luma_time_factor; 2108 double mcache_remainder_l; 2109 double mcache_remainder_c; 2110 unsigned int mvmpg_access_width_l; 2111 unsigned int mvmpg_access_width_c; 2112 unsigned int avg_mcache_element_size_l; 2113 unsigned int avg_mcache_element_size_c; 2114 2115 unsigned int full_vp_access_width_l; 2116 unsigned int full_vp_access_width_c; 2117 }; 2118 2119 struct dml2_core_calcs_calculate_mcache_setting_params { 2120 bool dcc_enable; 2121 unsigned int num_chans; 2122 unsigned int mem_word_bytes; 2123 unsigned int mcache_size_bytes; 2124 unsigned int mcache_line_size_bytes; 2125 unsigned int gpuvm_enable; 2126 unsigned int gpuvm_page_size_kbytes; 2127 2128 enum dml2_source_format_class source_format; 2129 bool surf_vert; 2130 unsigned int vp_stationary; 2131 unsigned int tiling_mode; 2132 bool imall_enable; 2133 2134 unsigned int vp_start_x_l; 2135 unsigned int vp_start_y_l; 2136 unsigned int full_vp_width_l; 2137 unsigned int full_vp_height_l; 2138 unsigned int blk_width_l; 2139 unsigned int blk_height_l; 2140 unsigned int vmpg_width_l; 2141 unsigned int vmpg_height_l; 2142 unsigned int full_swath_bytes_l; 2143 unsigned int bytes_per_pixel_l; 2144 2145 unsigned int vp_start_x_c; 2146 unsigned int vp_start_y_c; 2147 unsigned int full_vp_width_c; 2148 unsigned int full_vp_height_c; 2149 unsigned int blk_width_c; 2150 unsigned int blk_height_c; 2151 unsigned int vmpg_width_c; 2152 unsigned int vmpg_height_c; 2153 unsigned int full_swath_bytes_c; 2154 unsigned int bytes_per_pixel_c; 2155 2156 // output 2157 unsigned int *num_mcaches_l; 2158 unsigned int *mcache_row_bytes_l; 2159 unsigned int *mcache_row_bytes_per_channel_l; 2160 unsigned int *mcache_offsets_l; 2161 unsigned int *mcache_shift_granularity_l; 2162 double *dcc_dram_bw_nom_overhead_factor_l; 2163 double *dcc_dram_bw_pref_overhead_factor_l; 2164 2165 unsigned int *num_mcaches_c; 2166 unsigned int *mcache_row_bytes_c; 2167 unsigned int *mcache_row_bytes_per_channel_c; 2168 unsigned int *mcache_offsets_c; 2169 unsigned int *mcache_shift_granularity_c; 2170 double *dcc_dram_bw_nom_overhead_factor_c; 2171 double *dcc_dram_bw_pref_overhead_factor_c; 2172 2173 bool *mall_comb_mcache_l; 2174 bool *mall_comb_mcache_c; 2175 bool *lc_comb_mcache; 2176 }; 2177 2178 struct dml2_core_calcs_calculate_tdlut_setting_params { 2179 // input params 2180 double dispclk_mhz; 2181 bool setup_for_tdlut; 2182 enum dml2_tdlut_width_mode tdlut_width_mode; 2183 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 2184 unsigned int cursor_buffer_size; 2185 bool gpuvm_enable; 2186 unsigned int gpuvm_page_size_kbytes; 2187 bool is_gfx11; 2188 bool tdlut_mpc_width_flag; 2189 2190 // output param 2191 unsigned int *tdlut_pte_bytes_per_frame; 2192 unsigned int *tdlut_bytes_per_frame; 2193 unsigned int *tdlut_groups_per_2row_ub; 2194 double *tdlut_opt_time; 2195 double *tdlut_drain_time; 2196 unsigned int *tdlut_bytes_to_deliver; 2197 unsigned int *tdlut_bytes_per_group; 2198 }; 2199 2200 struct dml2_core_calcs_calculate_peak_bandwidth_required_params { 2201 // output 2202 double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max]; 2203 double (*urg_bandwidth_required)[dml2_core_internal_bw_max]; 2204 double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max]; 2205 double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max]; 2206 double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2207 double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2208 2209 // input 2210 const struct dml2_display_cfg *display_cfg; 2211 bool inc_flip_bw; 2212 unsigned int num_active_planes; 2213 unsigned int *num_of_dpp; 2214 double *dcc_dram_bw_nom_overhead_factor_p0; 2215 double *dcc_dram_bw_nom_overhead_factor_p1; 2216 double *dcc_dram_bw_pref_overhead_factor_p0; 2217 double *dcc_dram_bw_pref_overhead_factor_p1; 2218 double *mall_prefetch_sdp_overhead_factor; 2219 double *mall_prefetch_dram_overhead_factor; 2220 double *surface_read_bandwidth_l; 2221 double *surface_read_bandwidth_c; 2222 double *prefetch_bandwidth_l; 2223 double *prefetch_bandwidth_c; 2224 double *prefetch_bandwidth_max; 2225 double *excess_vactive_fill_bw_l; 2226 double *excess_vactive_fill_bw_c; 2227 double *cursor_bw; 2228 double *dpte_row_bw; 2229 double *meta_row_bw; 2230 double *prefetch_cursor_bw; 2231 double *prefetch_vmrow_bw; 2232 double *flip_bw; 2233 double *urgent_burst_factor_l; 2234 double *urgent_burst_factor_c; 2235 double *urgent_burst_factor_cursor; 2236 double *urgent_burst_factor_prefetch_l; 2237 double *urgent_burst_factor_prefetch_c; 2238 double *urgent_burst_factor_prefetch_cursor; 2239 }; 2240 2241 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params { 2242 /* inputs */ 2243 const struct dml2_display_cfg *display_cfg; 2244 bool mrq_present; 2245 unsigned int num_active_planes; 2246 unsigned int *num_of_dpp; 2247 unsigned int *meta_row_height_l; 2248 unsigned int *meta_row_height_c; 2249 unsigned int *meta_row_bytes_per_row_ub_l; 2250 unsigned int *meta_row_bytes_per_row_ub_c; 2251 unsigned int *dpte_row_height_l; 2252 unsigned int *dpte_row_height_c; 2253 unsigned int *dpte_bytes_per_row_l; 2254 unsigned int *dpte_bytes_per_row_c; 2255 unsigned int *byte_per_pix_l; 2256 unsigned int *byte_per_pix_c; 2257 unsigned int *swath_width_l; 2258 unsigned int *swath_width_c; 2259 unsigned int *swath_height_l; 2260 unsigned int *swath_height_c; 2261 double latency_to_hide_us[DML2_MAX_PLANES]; 2262 2263 /* outputs */ 2264 unsigned int *bytes_required_l; 2265 unsigned int *bytes_required_c; 2266 }; 2267 2268 // A list of overridable function pointers in the core 2269 // shared calculation library. 2270 struct dml2_core_shared_calculation_funcs { 2271 void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p); 2272 }; 2273 2274 struct dml2_core_internal_scratch { 2275 // Scratch space for function locals 2276 struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals; 2277 struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals; 2278 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 2279 struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals; 2280 struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals; 2281 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals; 2282 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals; 2283 struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals; 2284 struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals; 2285 struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals; 2286 struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals; 2287 struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals; 2288 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals; 2289 struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals; 2290 2291 // Scratch space for function params 2292 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 2293 struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params; 2294 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params; 2295 struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params; 2296 struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params; 2297 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params; 2298 struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params; 2299 struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params; 2300 struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params; 2301 struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals; 2302 struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params; 2303 struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params; 2304 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params; 2305 }; 2306 2307 //struct dml2_svp_mode_override; 2308 struct dml2_core_internal_display_mode_lib { 2309 struct dml2_core_ip_params ip; 2310 struct dml2_soc_bb soc; 2311 struct dml2_ip_capabilities ip_caps; 2312 2313 //@brief Mode Support and Mode programming struct 2314 // Used to hold input; intermediate and output of the calculations 2315 struct dml2_core_internal_mode_support ms; // struct for mode support 2316 struct dml2_core_internal_mode_program mp; // struct for mode programming 2317 // Available overridable calculators for core_shared. 2318 // if null, core_shared will use default calculators. 2319 struct dml2_core_shared_calculation_funcs funcs; 2320 2321 struct dml2_core_internal_scratch scratch; 2322 }; 2323 2324 struct dml2_core_calcs_mode_support_ex { 2325 struct dml2_core_internal_display_mode_lib *mode_lib; 2326 const struct dml2_display_cfg *in_display_cfg; 2327 const struct dml2_mcg_min_clock_table *min_clk_table; 2328 int min_clk_index; 2329 enum dml2_project_id project_id; 2330 //unsigned int in_state_index; 2331 struct dml2_core_internal_mode_support_info *out_evaluation_info; 2332 }; 2333 2334 struct core_display_cfg_support_info; 2335 2336 struct dml2_core_calcs_mode_programming_ex { 2337 struct dml2_core_internal_display_mode_lib *mode_lib; 2338 const struct dml2_display_cfg *in_display_cfg; 2339 const struct dml2_mcg_min_clock_table *min_clk_table; 2340 const struct core_display_cfg_support_info *cfg_support_info; 2341 int min_clk_index; 2342 enum dml2_project_id project_id; 2343 struct dml2_display_cfg_programming *programming; 2344 }; 2345 2346 #endif 2347