1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 2008 Cavium Networks 8 * 9 * Some parts of the code were originally released under BSD license: 10 * 11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 12 * reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: 17 * 18 * * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * * Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials provided 24 * with the distribution. 25 * 26 * * Neither the name of Cavium Networks nor the names of 27 * its contributors may be used to endorse or promote products 28 * derived from this software without specific prior written 29 * permission. 30 * 31 * This Software, including technical data, may be subject to U.S. export 32 * control laws, including the U.S. Export Administration Act and its associated 33 * regulations, and may be subject to export or import regulations in other 34 * countries. 35 * 36 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 37 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 38 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 39 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION 40 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 41 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 42 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 43 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 44 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 45 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 46 */ 47 48 #include <linux/usb.h> 49 #include <linux/slab.h> 50 #include <linux/module.h> 51 #include <linux/usb/hcd.h> 52 #include <linux/prefetch.h> 53 #include <linux/irqdomain.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/platform_device.h> 56 #include <linux/of.h> 57 58 #include <asm/octeon/octeon.h> 59 60 #include "octeon-hcd.h" 61 62 /** 63 * enum cvmx_usb_speed - the possible USB device speeds 64 * 65 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps 66 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps 67 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps 68 */ 69 enum cvmx_usb_speed { 70 CVMX_USB_SPEED_HIGH = 0, 71 CVMX_USB_SPEED_FULL = 1, 72 CVMX_USB_SPEED_LOW = 2, 73 }; 74 75 /** 76 * enum cvmx_usb_transfer - the possible USB transfer types 77 * 78 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status 79 * transfers 80 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low 81 * priority periodic transfers 82 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority 83 * transfers 84 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority 85 * periodic transfers 86 */ 87 enum cvmx_usb_transfer { 88 CVMX_USB_TRANSFER_CONTROL = 0, 89 CVMX_USB_TRANSFER_ISOCHRONOUS = 1, 90 CVMX_USB_TRANSFER_BULK = 2, 91 CVMX_USB_TRANSFER_INTERRUPT = 3, 92 }; 93 94 /** 95 * enum cvmx_usb_direction - the transfer directions 96 * 97 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host 98 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon 99 */ 100 enum cvmx_usb_direction { 101 CVMX_USB_DIRECTION_OUT, 102 CVMX_USB_DIRECTION_IN, 103 }; 104 105 /** 106 * enum cvmx_usb_status - possible callback function status codes 107 * 108 * @CVMX_USB_STATUS_OK: The transaction / operation finished without 109 * any errors 110 * @CVMX_USB_STATUS_SHORT: FIXME: This is currently not implemented 111 * @CVMX_USB_STATUS_CANCEL: The transaction was canceled while in flight 112 * by a user call to cvmx_usb_cancel 113 * @CVMX_USB_STATUS_ERROR: The transaction aborted with an unexpected 114 * error status 115 * @CVMX_USB_STATUS_STALL: The transaction received a USB STALL response 116 * from the device 117 * @CVMX_USB_STATUS_XACTERR: The transaction failed with an error from the 118 * device even after a number of retries 119 * @CVMX_USB_STATUS_DATATGLERR: The transaction failed with a data toggle 120 * error even after a number of retries 121 * @CVMX_USB_STATUS_BABBLEERR: The transaction failed with a babble error 122 * @CVMX_USB_STATUS_FRAMEERR: The transaction failed with a frame error 123 * even after a number of retries 124 */ 125 enum cvmx_usb_status { 126 CVMX_USB_STATUS_OK, 127 CVMX_USB_STATUS_SHORT, 128 CVMX_USB_STATUS_CANCEL, 129 CVMX_USB_STATUS_ERROR, 130 CVMX_USB_STATUS_STALL, 131 CVMX_USB_STATUS_XACTERR, 132 CVMX_USB_STATUS_DATATGLERR, 133 CVMX_USB_STATUS_BABBLEERR, 134 CVMX_USB_STATUS_FRAMEERR, 135 }; 136 137 /** 138 * struct cvmx_usb_port_status - the USB port status information 139 * 140 * @port_enabled: 1 = Usb port is enabled, 0 = disabled 141 * @port_over_current: 1 = Over current detected, 0 = Over current not 142 * detected. Octeon doesn't support over current detection. 143 * @port_powered: 1 = Port power is being supplied to the device, 0 = 144 * power is off. Octeon doesn't support turning port power 145 * off. 146 * @port_speed: Current port speed. 147 * @connected: 1 = A device is connected to the port, 0 = No device is 148 * connected. 149 * @connect_change: 1 = Device connected state changed since the last set 150 * status call. 151 */ 152 struct cvmx_usb_port_status { 153 u32 reserved : 25; 154 u32 port_enabled : 1; 155 u32 port_over_current : 1; 156 u32 port_powered : 1; 157 enum cvmx_usb_speed port_speed : 2; 158 u32 connected : 1; 159 u32 connect_change : 1; 160 }; 161 162 /** 163 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets 164 * 165 * @offset: This is the offset in bytes into the main buffer where this data 166 * is stored. 167 * @length: This is the length in bytes of the data. 168 * @status: This is the status of this individual packet transfer. 169 */ 170 struct cvmx_usb_iso_packet { 171 int offset; 172 int length; 173 enum cvmx_usb_status status; 174 }; 175 176 /** 177 * enum cvmx_usb_initialize_flags - flags used by the initialization function 178 * 179 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal 180 * as clock source at USB_XO and 181 * USB_XI. 182 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V 183 * board clock source at USB_XO. 184 * USB_XI should be tied to GND. 185 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field 186 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or 187 * crystal 188 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock 189 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock 190 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for 191 * data transfer use for the USB 192 */ 193 enum cvmx_usb_initialize_flags { 194 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0, 195 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1, 196 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3, 197 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3, 198 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3, 199 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3, 200 /* Bits 3-4 used to encode the clock frequency */ 201 CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5, 202 }; 203 204 /** 205 * enum cvmx_usb_pipe_flags - internal flags for a pipe. 206 * 207 * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is 208 * actively using hardware. 209 * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed 210 * pipe is in the ping state. 211 */ 212 enum cvmx_usb_pipe_flags { 213 CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17, 214 CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18, 215 }; 216 217 /* Maximum number of times to retry failed transactions */ 218 #define MAX_RETRIES 3 219 220 /* Maximum number of hardware channels supported by the USB block */ 221 #define MAX_CHANNELS 8 222 223 /* 224 * The low level hardware can transfer a maximum of this number of bytes in each 225 * transfer. The field is 19 bits wide 226 */ 227 #define MAX_TRANSFER_BYTES ((1 << 19) - 1) 228 229 /* 230 * The low level hardware can transfer a maximum of this number of packets in 231 * each transfer. The field is 10 bits wide 232 */ 233 #define MAX_TRANSFER_PACKETS ((1 << 10) - 1) 234 235 /** 236 * Logical transactions may take numerous low level 237 * transactions, especially when splits are concerned. This 238 * enum represents all of the possible stages a transaction can 239 * be in. Note that split completes are always even. This is so 240 * the NAK handler can backup to the previous low level 241 * transaction with a simple clearing of bit 0. 242 */ 243 enum cvmx_usb_stage { 244 CVMX_USB_STAGE_NON_CONTROL, 245 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE, 246 CVMX_USB_STAGE_SETUP, 247 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE, 248 CVMX_USB_STAGE_DATA, 249 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE, 250 CVMX_USB_STAGE_STATUS, 251 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE, 252 }; 253 254 /** 255 * struct cvmx_usb_transaction - describes each pending USB transaction 256 * regardless of type. These are linked together 257 * to form a list of pending requests for a pipe. 258 * 259 * @node: List node for transactions in the pipe. 260 * @type: Type of transaction, duplicated of the pipe. 261 * @flags: State flags for this transaction. 262 * @buffer: User's physical buffer address to read/write. 263 * @buffer_length: Size of the user's buffer in bytes. 264 * @control_header: For control transactions, physical address of the 8 265 * byte standard header. 266 * @iso_start_frame: For ISO transactions, the starting frame number. 267 * @iso_number_packets: For ISO transactions, the number of packets in the 268 * request. 269 * @iso_packets: For ISO transactions, the sub packets in the request. 270 * @actual_bytes: Actual bytes transfer for this transaction. 271 * @stage: For control transactions, the current stage. 272 * @urb: URB. 273 */ 274 struct cvmx_usb_transaction { 275 struct list_head node; 276 enum cvmx_usb_transfer type; 277 u64 buffer; 278 int buffer_length; 279 u64 control_header; 280 int iso_start_frame; 281 int iso_number_packets; 282 struct cvmx_usb_iso_packet *iso_packets; 283 int xfersize; 284 int pktcnt; 285 int retries; 286 int actual_bytes; 287 enum cvmx_usb_stage stage; 288 struct urb *urb; 289 }; 290 291 /** 292 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon 293 * and some USB device. It contains a list of pending 294 * request to the device. 295 * 296 * @node: List node for pipe list 297 * @next: Pipe after this one in the list 298 * @transactions: List of pending transactions 299 * @interval: For periodic pipes, the interval between packets in 300 * frames 301 * @next_tx_frame: The next frame this pipe is allowed to transmit on 302 * @flags: State flags for this pipe 303 * @device_speed: Speed of device connected to this pipe 304 * @transfer_type: Type of transaction supported by this pipe 305 * @transfer_dir: IN or OUT. Ignored for Control 306 * @multi_count: Max packet in a row for the device 307 * @max_packet: The device's maximum packet size in bytes 308 * @device_addr: USB device address at other end of pipe 309 * @endpoint_num: USB endpoint number at other end of pipe 310 * @hub_device_addr: Hub address this device is connected to 311 * @hub_port: Hub port this device is connected to 312 * @pid_toggle: This toggles between 0/1 on every packet send to track 313 * the data pid needed 314 * @channel: Hardware DMA channel for this pipe 315 * @split_sc_frame: The low order bits of the frame number the split 316 * complete should be sent on 317 */ 318 struct cvmx_usb_pipe { 319 struct list_head node; 320 struct list_head transactions; 321 u64 interval; 322 u64 next_tx_frame; 323 enum cvmx_usb_pipe_flags flags; 324 enum cvmx_usb_speed device_speed; 325 enum cvmx_usb_transfer transfer_type; 326 enum cvmx_usb_direction transfer_dir; 327 int multi_count; 328 u16 max_packet; 329 u8 device_addr; 330 u8 endpoint_num; 331 u8 hub_device_addr; 332 u8 hub_port; 333 u8 pid_toggle; 334 u8 channel; 335 s8 split_sc_frame; 336 }; 337 338 struct cvmx_usb_tx_fifo { 339 struct { 340 int channel; 341 int size; 342 u64 address; 343 } entry[MAX_CHANNELS + 1]; 344 int head; 345 int tail; 346 }; 347 348 /** 349 * struct octeon_hcd - the state of the USB block 350 * 351 * lock: Serialization lock. 352 * init_flags: Flags passed to initialize. 353 * index: Which USB block this is for. 354 * idle_hardware_channels: Bit set for every idle hardware channel. 355 * usbcx_hprt: Stored port status so we don't need to read a CSR to 356 * determine splits. 357 * pipe_for_channel: Map channels to pipes. 358 * pipe: Storage for pipes. 359 * indent: Used by debug output to indent functions. 360 * port_status: Last port status used for change notification. 361 * idle_pipes: List of open pipes that have no transactions. 362 * active_pipes: Active pipes indexed by transfer type. 363 * frame_number: Increments every SOF interrupt for time keeping. 364 * active_split: Points to the current active split, or NULL. 365 */ 366 struct octeon_hcd { 367 spinlock_t lock; /* serialization lock */ 368 int init_flags; 369 int index; 370 int idle_hardware_channels; 371 union cvmx_usbcx_hprt usbcx_hprt; 372 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS]; 373 int indent; 374 struct cvmx_usb_port_status port_status; 375 struct list_head idle_pipes; 376 struct list_head active_pipes[4]; 377 u64 frame_number; 378 struct cvmx_usb_transaction *active_split; 379 struct cvmx_usb_tx_fifo periodic; 380 struct cvmx_usb_tx_fifo nonperiodic; 381 struct hrtimer sof_timer; 382 }; 383 384 static int cvmx_usb_poll(struct octeon_hcd *usb); 385 386 static enum hrtimer_restart octeon_usb_sof_timer(struct hrtimer *t) 387 { 388 struct octeon_hcd *usb = container_of(t, struct octeon_hcd, sof_timer); 389 unsigned long flags; 390 391 spin_lock_irqsave(&usb->lock, flags); 392 cvmx_usb_poll(usb); 393 spin_unlock_irqrestore(&usb->lock, flags); 394 return HRTIMER_NORESTART; 395 } 396 397 /* 398 * This macro logically sets a single field in a CSR. It does the sequence 399 * read, modify, and write 400 */ 401 #define USB_SET_FIELD32(address, _union, field, value) \ 402 do { \ 403 union _union c; \ 404 \ 405 c.u32 = cvmx_usb_read_csr32(usb, address); \ 406 c.s.field = value; \ 407 cvmx_usb_write_csr32(usb, address, c.u32); \ 408 } while (0) 409 410 /* Returns the IO address to push/pop stuff data from the FIFOs */ 411 #define USB_FIFO_ADDRESS(channel, usb_index) \ 412 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel) + 1) * 0x1000) 413 414 /** 415 * struct octeon_temp_buffer - a bounce buffer for USB transfers 416 * @orig_buffer: the original buffer passed by the USB stack 417 * @data: the newly allocated temporary buffer (excluding meta-data) 418 * 419 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If 420 * the buffer is too short, we need to allocate a temporary one, and this struct 421 * represents it. 422 */ 423 struct octeon_temp_buffer { 424 void *orig_buffer; 425 u8 data[]; 426 }; 427 428 static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p) 429 { 430 return container_of((void *)p, struct usb_hcd, hcd_priv); 431 } 432 433 /** 434 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer 435 * (if needed) 436 * @urb: URB. 437 * @mem_flags: Memory allocation flags. 438 * 439 * This function allocates a temporary bounce buffer whenever it's needed 440 * due to HW limitations. 441 */ 442 static int octeon_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 443 { 444 struct octeon_temp_buffer *temp; 445 446 if (urb->num_sgs || urb->sg || 447 (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) || 448 !(urb->transfer_buffer_length % sizeof(u32))) 449 return 0; 450 451 temp = kmalloc(ALIGN(urb->transfer_buffer_length, sizeof(u32)) + 452 sizeof(*temp), mem_flags); 453 if (!temp) 454 return -ENOMEM; 455 456 temp->orig_buffer = urb->transfer_buffer; 457 if (usb_urb_dir_out(urb)) 458 memcpy(temp->data, urb->transfer_buffer, 459 urb->transfer_buffer_length); 460 urb->transfer_buffer = temp->data; 461 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 462 463 return 0; 464 } 465 466 /** 467 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers. 468 * @urb: URB. 469 * 470 * Frees a buffer allocated by octeon_alloc_temp_buffer(). 471 */ 472 static void octeon_free_temp_buffer(struct urb *urb) 473 { 474 struct octeon_temp_buffer *temp; 475 size_t length; 476 477 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 478 return; 479 480 temp = container_of(urb->transfer_buffer, struct octeon_temp_buffer, 481 data); 482 if (usb_urb_dir_in(urb)) { 483 if (usb_pipeisoc(urb->pipe)) 484 length = urb->transfer_buffer_length; 485 else 486 length = urb->actual_length; 487 488 memcpy(temp->orig_buffer, urb->transfer_buffer, length); 489 } 490 urb->transfer_buffer = temp->orig_buffer; 491 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 492 kfree(temp); 493 } 494 495 /** 496 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma(). 497 * @hcd: USB HCD structure. 498 * @urb: URB. 499 * @mem_flags: Memory allocation flags. 500 */ 501 static int octeon_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 502 gfp_t mem_flags) 503 { 504 int ret; 505 506 ret = octeon_alloc_temp_buffer(urb, mem_flags); 507 if (ret) 508 return ret; 509 510 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 511 if (ret) 512 octeon_free_temp_buffer(urb); 513 514 return ret; 515 } 516 517 /** 518 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma() 519 * @hcd: USB HCD structure. 520 * @urb: URB. 521 */ 522 static void octeon_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 523 { 524 usb_hcd_unmap_urb_for_dma(hcd, urb); 525 octeon_free_temp_buffer(urb); 526 } 527 528 /** 529 * Read a USB 32bit CSR. It performs the necessary address swizzle 530 * for 32bit CSRs and logs the value in a readable format if 531 * debugging is on. 532 * 533 * @usb: USB block this access is for 534 * @address: 64bit address to read 535 * 536 * Returns: Result of the read 537 */ 538 static inline u32 cvmx_usb_read_csr32(struct octeon_hcd *usb, u64 address) 539 { 540 return cvmx_read64_uint32(address ^ 4); 541 } 542 543 /** 544 * Write a USB 32bit CSR. It performs the necessary address 545 * swizzle for 32bit CSRs and logs the value in a readable format 546 * if debugging is on. 547 * 548 * @usb: USB block this access is for 549 * @address: 64bit address to write 550 * @value: Value to write 551 */ 552 static inline void cvmx_usb_write_csr32(struct octeon_hcd *usb, 553 u64 address, u32 value) 554 { 555 cvmx_write64_uint32(address ^ 4, value); 556 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); 557 } 558 559 /** 560 * Return non zero if this pipe connects to a non HIGH speed 561 * device through a high speed hub. 562 * 563 * @usb: USB block this access is for 564 * @pipe: Pipe to check 565 * 566 * Returns: Non zero if we need to do split transactions 567 */ 568 static inline int cvmx_usb_pipe_needs_split(struct octeon_hcd *usb, 569 struct cvmx_usb_pipe *pipe) 570 { 571 return pipe->device_speed != CVMX_USB_SPEED_HIGH && 572 usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH; 573 } 574 575 /** 576 * Trivial utility function to return the correct PID for a pipe 577 * 578 * @pipe: pipe to check 579 * 580 * Returns: PID for pipe 581 */ 582 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe) 583 { 584 if (pipe->pid_toggle) 585 return 2; /* Data1 */ 586 return 0; /* Data0 */ 587 } 588 589 /* Loops through register until txfflsh or rxfflsh become zero.*/ 590 static int cvmx_wait_tx_rx(struct octeon_hcd *usb, int fflsh_type) 591 { 592 int result; 593 u64 address = CVMX_USBCX_GRSTCTL(usb->index); 594 u64 done = cvmx_get_cycle() + 100 * 595 (u64)octeon_get_clock_rate() / 1000000; 596 union cvmx_usbcx_grstctl c; 597 598 while (1) { 599 c.u32 = cvmx_usb_read_csr32(usb, address); 600 if (fflsh_type == 0 && c.s.txfflsh == 0) { 601 result = 0; 602 break; 603 } else if (fflsh_type == 1 && c.s.rxfflsh == 0) { 604 result = 0; 605 break; 606 } else if (cvmx_get_cycle() > done) { 607 result = -1; 608 break; 609 } 610 611 __delay(100); 612 } 613 return result; 614 } 615 616 static void cvmx_fifo_setup(struct octeon_hcd *usb) 617 { 618 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3; 619 union cvmx_usbcx_gnptxfsiz npsiz; 620 union cvmx_usbcx_hptxfsiz psiz; 621 622 usbcx_ghwcfg3.u32 = cvmx_usb_read_csr32(usb, 623 CVMX_USBCX_GHWCFG3(usb->index)); 624 625 /* 626 * Program the USBC_GRXFSIZ register to select the size of the receive 627 * FIFO (25%). 628 */ 629 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz, 630 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4); 631 632 /* 633 * Program the USBC_GNPTXFSIZ register to select the size and the start 634 * address of the non-periodic transmit FIFO for nonperiodic 635 * transactions (50%). 636 */ 637 npsiz.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index)); 638 npsiz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2; 639 npsiz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4; 640 cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), npsiz.u32); 641 642 /* 643 * Program the USBC_HPTXFSIZ register to select the size and start 644 * address of the periodic transmit FIFO for periodic transactions 645 * (25%). 646 */ 647 psiz.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index)); 648 psiz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4; 649 psiz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4; 650 cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), psiz.u32); 651 652 /* Flush all FIFOs */ 653 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), 654 cvmx_usbcx_grstctl, txfnum, 0x10); 655 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), 656 cvmx_usbcx_grstctl, txfflsh, 1); 657 cvmx_wait_tx_rx(usb, 0); 658 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), 659 cvmx_usbcx_grstctl, rxfflsh, 1); 660 cvmx_wait_tx_rx(usb, 1); 661 } 662 663 /** 664 * Shutdown a USB port after a call to cvmx_usb_initialize(). 665 * The port should be disabled with all pipes closed when this 666 * function is called. 667 * 668 * @usb: USB device state populated by cvmx_usb_initialize(). 669 * 670 * Returns: 0 or a negative error code. 671 */ 672 static int cvmx_usb_shutdown(struct octeon_hcd *usb) 673 { 674 union cvmx_usbnx_clk_ctl usbn_clk_ctl; 675 676 /* Make sure all pipes are closed */ 677 if (!list_empty(&usb->idle_pipes) || 678 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) || 679 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) || 680 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) || 681 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK])) 682 return -EBUSY; 683 684 /* Disable the clocks and put them in power on reset */ 685 usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index)); 686 usbn_clk_ctl.s.enable = 1; 687 usbn_clk_ctl.s.por = 1; 688 usbn_clk_ctl.s.hclk_rst = 1; 689 usbn_clk_ctl.s.prst = 0; 690 usbn_clk_ctl.s.hrst = 0; 691 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 692 return 0; 693 } 694 695 /** 696 * Initialize a USB port for use. This must be called before any 697 * other access to the Octeon USB port is made. The port starts 698 * off in the disabled state. 699 * 700 * @dev: Pointer to struct device for logging purposes. 701 * @usb: Pointer to struct octeon_hcd. 702 * 703 * Returns: 0 or a negative error code. 704 */ 705 static int cvmx_usb_initialize(struct device *dev, 706 struct octeon_hcd *usb) 707 { 708 int channel; 709 int divisor; 710 int retries = 0; 711 union cvmx_usbcx_hcfg usbcx_hcfg; 712 union cvmx_usbnx_clk_ctl usbn_clk_ctl; 713 union cvmx_usbcx_gintsts usbc_gintsts; 714 union cvmx_usbcx_gahbcfg usbcx_gahbcfg; 715 union cvmx_usbcx_gintmsk usbcx_gintmsk; 716 union cvmx_usbcx_gusbcfg usbcx_gusbcfg; 717 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status; 718 719 retry: 720 /* 721 * Power On Reset and PHY Initialization 722 * 723 * 1. Wait for DCOK to assert (nothing to do) 724 * 725 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and 726 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 727 */ 728 usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index)); 729 usbn_clk_ctl.s.por = 1; 730 usbn_clk_ctl.s.hrst = 0; 731 usbn_clk_ctl.s.prst = 0; 732 usbn_clk_ctl.s.hclk_rst = 0; 733 usbn_clk_ctl.s.enable = 0; 734 /* 735 * 2b. Select the USB reference clock/crystal parameters by writing 736 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] 737 */ 738 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) { 739 /* 740 * The USB port uses 12/24/48MHz 2.5V board clock 741 * source at USB_XO. USB_XI should be tied to GND. 742 * Most Octeon evaluation boards require this setting 743 */ 744 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || 745 OCTEON_IS_MODEL(OCTEON_CN56XX) || 746 OCTEON_IS_MODEL(OCTEON_CN50XX)) 747 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */ 748 usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */ 749 else 750 /* From CN52XX manual */ 751 usbn_clk_ctl.s.p_rtype = 1; 752 753 switch (usb->init_flags & 754 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) { 755 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: 756 usbn_clk_ctl.s.p_c_sel = 0; 757 break; 758 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: 759 usbn_clk_ctl.s.p_c_sel = 1; 760 break; 761 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: 762 usbn_clk_ctl.s.p_c_sel = 2; 763 break; 764 } 765 } else { 766 /* 767 * The USB port uses a 12MHz crystal as clock source 768 * at USB_XO and USB_XI 769 */ 770 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) 771 /* From CN31XX,CN30XX manual */ 772 usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */ 773 else 774 /* From CN56XX,CN52XX,CN50XX manuals. */ 775 usbn_clk_ctl.s.p_rtype = 0; 776 777 usbn_clk_ctl.s.p_c_sel = 0; 778 } 779 /* 780 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and 781 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down 782 * such that USB is as close as possible to 125Mhz 783 */ 784 divisor = DIV_ROUND_UP(octeon_get_clock_rate(), 125000000); 785 /* Lower than 4 doesn't seem to work properly */ 786 if (divisor < 4) 787 divisor = 4; 788 usbn_clk_ctl.s.divide = divisor; 789 usbn_clk_ctl.s.divide2 = 0; 790 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 791 792 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */ 793 usbn_clk_ctl.s.hclk_rst = 1; 794 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 795 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */ 796 __delay(64); 797 /* 798 * 3. Program the power-on reset field in the USBN clock-control 799 * register: 800 * USBN_CLK_CTL[POR] = 0 801 */ 802 usbn_clk_ctl.s.por = 0; 803 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 804 /* 4. Wait 1 ms for PHY clock to start */ 805 mdelay(1); 806 /* 807 * 5. Program the Reset input from automatic test equipment field in the 808 * USBP control and status register: 809 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1 810 */ 811 usbn_usbp_ctl_status.u64 = 812 cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index)); 813 usbn_usbp_ctl_status.s.ate_reset = 1; 814 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), 815 usbn_usbp_ctl_status.u64); 816 /* 6. Wait 10 cycles */ 817 __delay(10); 818 /* 819 * 7. Clear ATE_RESET field in the USBN clock-control register: 820 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0 821 */ 822 usbn_usbp_ctl_status.s.ate_reset = 0; 823 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), 824 usbn_usbp_ctl_status.u64); 825 /* 826 * 8. Program the PHY reset field in the USBN clock-control register: 827 * USBN_CLK_CTL[PRST] = 1 828 */ 829 usbn_clk_ctl.s.prst = 1; 830 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 831 /* 832 * 9. Program the USBP control and status register to select host or 833 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for 834 * device 835 */ 836 usbn_usbp_ctl_status.s.hst_mode = 0; 837 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index), 838 usbn_usbp_ctl_status.u64); 839 /* 10. Wait 1 us */ 840 udelay(1); 841 /* 842 * 11. Program the hreset_n field in the USBN clock-control register: 843 * USBN_CLK_CTL[HRST] = 1 844 */ 845 usbn_clk_ctl.s.hrst = 1; 846 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 847 /* 12. Proceed to USB core initialization */ 848 usbn_clk_ctl.s.enable = 1; 849 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); 850 udelay(1); 851 852 /* 853 * USB Core Initialization 854 * 855 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to 856 * determine USB core configuration parameters. 857 * 858 * Nothing needed 859 * 860 * 2. Program the following fields in the global AHB configuration 861 * register (USBC_GAHBCFG) 862 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode 863 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0 864 * Nonperiodic TxFIFO empty level (slave mode only), 865 * USBC_GAHBCFG[NPTXFEMPLVL] 866 * Periodic TxFIFO empty level (slave mode only), 867 * USBC_GAHBCFG[PTXFEMPLVL] 868 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 869 */ 870 usbcx_gahbcfg.u32 = cvmx_usb_read_csr32(usb, 871 CVMX_USBCX_GHWCFG3(usb->index)); 872 if (usbcx_gahbcfg.u32 == 0xffffffff || usbcx_gahbcfg.u32 == 0) { 873 dev_err(dev, "USB core is not responding (GHWCFG3=0x%08x)\n", 874 usbcx_gahbcfg.u32); 875 return -ENODEV; 876 } 877 878 usbcx_gahbcfg.u32 = 0; 879 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & 880 CVMX_USB_INITIALIZE_FLAGS_NO_DMA); 881 usbcx_gahbcfg.s.hbstlen = 0; 882 usbcx_gahbcfg.s.nptxfemplvl = 1; 883 usbcx_gahbcfg.s.ptxfemplvl = 1; 884 usbcx_gahbcfg.s.glblintrmsk = 1; 885 cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index), 886 usbcx_gahbcfg.u32); 887 888 /* 889 * 3. Program the following fields in USBC_GUSBCFG register. 890 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0 891 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0 892 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5 893 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 894 */ 895 usbcx_gusbcfg.u32 = cvmx_usb_read_csr32(usb, 896 CVMX_USBCX_GUSBCFG(usb->index)); 897 usbcx_gusbcfg.s.toutcal = 0; 898 usbcx_gusbcfg.s.ddrsel = 0; 899 usbcx_gusbcfg.s.usbtrdtim = 0x5; 900 usbcx_gusbcfg.s.phylpwrclksel = 0; 901 cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index), 902 usbcx_gusbcfg.u32); 903 904 /* 905 * 4. The software must unmask the following bits in the USBC_GINTMSK 906 * register. 907 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1 908 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 909 */ 910 usbcx_gintmsk.u32 = cvmx_usb_read_csr32(usb, 911 CVMX_USBCX_GINTMSK(usb->index)); 912 usbcx_gintmsk.s.otgintmsk = 1; 913 usbcx_gintmsk.s.modemismsk = 1; 914 usbcx_gintmsk.s.hchintmsk = 1; 915 usbcx_gintmsk.s.sofmsk = 0; 916 /* We need RX FIFO interrupts if we don't have DMA */ 917 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) 918 usbcx_gintmsk.s.rxflvlmsk = 1; 919 cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index), 920 usbcx_gintmsk.u32); 921 922 /* 923 * Disable all channel interrupts. We'll enable them per channel later. 924 */ 925 for (channel = 0; channel < 8; channel++) 926 cvmx_usb_write_csr32(usb, 927 CVMX_USBCX_HCINTMSKX(channel, usb->index), 928 0); 929 930 /* 931 * Host Port Initialization 932 * 933 * 1. Program the host-port interrupt-mask field to unmask, 934 * USBC_GINTMSK[PRTINT] = 1 935 */ 936 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 937 cvmx_usbcx_gintmsk, prtintmsk, 1); 938 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 939 cvmx_usbcx_gintmsk, disconnintmsk, 1); 940 941 /* 942 * 2. Program the USBC_HCFG register to select full-speed host 943 * or high-speed host. 944 */ 945 usbcx_hcfg.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index)); 946 usbcx_hcfg.s.fslssupp = 0; 947 usbcx_hcfg.s.fslspclksel = 0; 948 cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32); 949 950 cvmx_fifo_setup(usb); 951 952 /* 953 * If the controller is getting port events right after the reset, it 954 * means the initialization failed. Try resetting the controller again 955 * in such case. This is seen to happen after cold boot on DSR-1000N. 956 */ 957 usbc_gintsts.u32 = cvmx_usb_read_csr32(usb, 958 CVMX_USBCX_GINTSTS(usb->index)); 959 cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), 960 usbc_gintsts.u32); 961 dev_dbg(dev, "gintsts after reset: 0x%x\n", (int)usbc_gintsts.u32); 962 if (!usbc_gintsts.s.disconnint && !usbc_gintsts.s.prtint) 963 return 0; 964 if (retries++ >= 5) 965 return -EAGAIN; 966 dev_info(dev, "controller reset failed (gintsts=0x%x) - retrying\n", 967 (int)usbc_gintsts.u32); 968 msleep(50); 969 cvmx_usb_shutdown(usb); 970 msleep(50); 971 goto retry; 972 } 973 974 /** 975 * Reset a USB port. After this call succeeds, the USB port is 976 * online and servicing requests. 977 * 978 * @usb: USB device state populated by cvmx_usb_initialize(). 979 */ 980 static void cvmx_usb_reset_port(struct octeon_hcd *usb) 981 { 982 usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb, 983 CVMX_USBCX_HPRT(usb->index)); 984 985 /* Program the port reset bit to start the reset process */ 986 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt, 987 prtrst, 1); 988 989 /* 990 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset 991 * process to complete. 992 */ 993 mdelay(50); 994 995 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */ 996 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt, 997 prtrst, 0); 998 999 /* 1000 * Read the port speed field to get the enumerated speed, 1001 * USBC_HPRT[PRTSPD]. 1002 */ 1003 usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb, 1004 CVMX_USBCX_HPRT(usb->index)); 1005 } 1006 1007 /** 1008 * Disable a USB port. After this call the USB port will not 1009 * generate data transfers and will not generate events. 1010 * Transactions in process will fail and call their 1011 * associated callbacks. 1012 * 1013 * @usb: USB device state populated by cvmx_usb_initialize(). 1014 * 1015 * Returns: 0 or a negative error code. 1016 */ 1017 static int cvmx_usb_disable(struct octeon_hcd *usb) 1018 { 1019 /* Disable the port */ 1020 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt, 1021 prtena, 1); 1022 return 0; 1023 } 1024 1025 /** 1026 * Get the current state of the USB port. Use this call to 1027 * determine if the usb port has anything connected, is enabled, 1028 * or has some sort of error condition. The return value of this 1029 * call has "changed" bits to signal of the value of some fields 1030 * have changed between calls. 1031 * 1032 * @usb: USB device state populated by cvmx_usb_initialize(). 1033 * 1034 * Returns: Port status information 1035 */ 1036 static struct cvmx_usb_port_status cvmx_usb_get_status(struct octeon_hcd *usb) 1037 { 1038 union cvmx_usbcx_hprt usbc_hprt; 1039 struct cvmx_usb_port_status result; 1040 1041 memset(&result, 0, sizeof(result)); 1042 1043 usbc_hprt.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index)); 1044 result.port_enabled = usbc_hprt.s.prtena; 1045 result.port_over_current = usbc_hprt.s.prtovrcurract; 1046 result.port_powered = usbc_hprt.s.prtpwr; 1047 result.port_speed = usbc_hprt.s.prtspd; 1048 result.connected = usbc_hprt.s.prtconnsts; 1049 result.connect_change = 1050 result.connected != usb->port_status.connected; 1051 1052 return result; 1053 } 1054 1055 /** 1056 * Open a virtual pipe between the host and a USB device. A pipe 1057 * must be opened before data can be transferred between a device 1058 * and Octeon. 1059 * 1060 * @usb: USB device state populated by cvmx_usb_initialize(). 1061 * @device_addr: 1062 * USB device address to open the pipe to 1063 * (0-127). 1064 * @endpoint_num: 1065 * USB endpoint number to open the pipe to 1066 * (0-15). 1067 * @device_speed: 1068 * The speed of the device the pipe is going 1069 * to. This must match the device's speed, 1070 * which may be different than the port speed. 1071 * @max_packet: The maximum packet length the device can 1072 * transmit/receive (low speed=0-8, full 1073 * speed=0-1023, high speed=0-1024). This value 1074 * comes from the standard endpoint descriptor 1075 * field wMaxPacketSize bits <10:0>. 1076 * @transfer_type: 1077 * The type of transfer this pipe is for. 1078 * @transfer_dir: 1079 * The direction the pipe is in. This is not 1080 * used for control pipes. 1081 * @interval: For ISOCHRONOUS and INTERRUPT transfers, 1082 * this is how often the transfer is scheduled 1083 * for. All other transfers should specify 1084 * zero. The units are in frames (8000/sec at 1085 * high speed, 1000/sec for full speed). 1086 * @multi_count: 1087 * For high speed devices, this is the maximum 1088 * allowed number of packet per microframe. 1089 * Specify zero for non high speed devices. This 1090 * value comes from the standard endpoint descriptor 1091 * field wMaxPacketSize bits <12:11>. 1092 * @hub_device_addr: 1093 * Hub device address this device is connected 1094 * to. Devices connected directly to Octeon 1095 * use zero. This is only used when the device 1096 * is full/low speed behind a high speed hub. 1097 * The address will be of the high speed hub, 1098 * not and full speed hubs after it. 1099 * @hub_port: Which port on the hub the device is 1100 * connected. Use zero for devices connected 1101 * directly to Octeon. Like hub_device_addr, 1102 * this is only used for full/low speed 1103 * devices behind a high speed hub. 1104 * 1105 * Returns: A non-NULL value is a pipe. NULL means an error. 1106 */ 1107 static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct octeon_hcd *usb, 1108 int device_addr, 1109 int endpoint_num, 1110 enum cvmx_usb_speed 1111 device_speed, 1112 int max_packet, 1113 enum cvmx_usb_transfer 1114 transfer_type, 1115 enum cvmx_usb_direction 1116 transfer_dir, 1117 int interval, int multi_count, 1118 int hub_device_addr, 1119 int hub_port) 1120 { 1121 struct cvmx_usb_pipe *pipe; 1122 1123 pipe = kzalloc_obj(*pipe, GFP_ATOMIC); 1124 if (!pipe) 1125 return NULL; 1126 if ((device_speed == CVMX_USB_SPEED_HIGH) && 1127 (transfer_dir == CVMX_USB_DIRECTION_OUT) && 1128 (transfer_type == CVMX_USB_TRANSFER_BULK)) 1129 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; 1130 pipe->device_addr = device_addr; 1131 pipe->endpoint_num = endpoint_num; 1132 pipe->device_speed = device_speed; 1133 pipe->max_packet = max_packet; 1134 pipe->transfer_type = transfer_type; 1135 pipe->transfer_dir = transfer_dir; 1136 INIT_LIST_HEAD(&pipe->transactions); 1137 1138 /* 1139 * All pipes use interval to rate limit NAK processing. Force an 1140 * interval if one wasn't supplied 1141 */ 1142 if (!interval) 1143 interval = 1; 1144 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 1145 pipe->interval = interval * 8; 1146 /* Force start splits to be schedule on uFrame 0 */ 1147 pipe->next_tx_frame = ((usb->frame_number + 7) & ~7) + 1148 pipe->interval; 1149 } else { 1150 pipe->interval = interval; 1151 pipe->next_tx_frame = usb->frame_number + pipe->interval; 1152 } 1153 pipe->multi_count = multi_count; 1154 pipe->hub_device_addr = hub_device_addr; 1155 pipe->hub_port = hub_port; 1156 pipe->pid_toggle = 0; 1157 pipe->split_sc_frame = -1; 1158 list_add_tail(&pipe->node, &usb->idle_pipes); 1159 1160 /* 1161 * We don't need to tell the hardware about this pipe yet since 1162 * it doesn't have any submitted requests 1163 */ 1164 1165 return pipe; 1166 } 1167 1168 /** 1169 * Poll the RX FIFOs and remove data as needed. This function is only used 1170 * in non DMA mode. It is very important that this function be called quickly 1171 * enough to prevent FIFO overflow. 1172 * 1173 * @usb: USB device state populated by cvmx_usb_initialize(). 1174 */ 1175 static void cvmx_usb_poll_rx_fifo(struct octeon_hcd *usb) 1176 { 1177 union cvmx_usbcx_grxstsph rx_status; 1178 int channel; 1179 int bytes; 1180 u64 address; 1181 u32 *ptr; 1182 1183 rx_status.u32 = cvmx_usb_read_csr32(usb, 1184 CVMX_USBCX_GRXSTSPH(usb->index)); 1185 /* Only read data if IN data is there */ 1186 if (rx_status.s.pktsts != 2) 1187 return; 1188 /* Check if no data is available */ 1189 if (!rx_status.s.bcnt) 1190 return; 1191 1192 channel = rx_status.s.chnum; 1193 bytes = rx_status.s.bcnt; 1194 if (!bytes) 1195 return; 1196 1197 /* Get where the DMA engine would have written this data */ 1198 address = cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + 1199 channel * 8); 1200 1201 ptr = cvmx_phys_to_ptr(address); 1202 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel * 8, 1203 address + bytes); 1204 1205 /* Loop writing the FIFO data for this packet into memory */ 1206 while (bytes > 0) { 1207 *ptr++ = cvmx_usb_read_csr32(usb, 1208 USB_FIFO_ADDRESS(channel, usb->index)); 1209 bytes -= 4; 1210 } 1211 CVMX_SYNCW; 1212 } 1213 1214 /** 1215 * Fill the TX hardware fifo with data out of the software 1216 * fifos 1217 * 1218 * @usb: USB device state populated by cvmx_usb_initialize(). 1219 * @fifo: Software fifo to use 1220 * @available: Amount of space in the hardware fifo 1221 * 1222 * Returns: Non zero if the hardware fifo was too small and needs 1223 * to be serviced again. 1224 */ 1225 static int cvmx_usb_fill_tx_hw(struct octeon_hcd *usb, 1226 struct cvmx_usb_tx_fifo *fifo, int available) 1227 { 1228 /* 1229 * We're done either when there isn't anymore space or the software FIFO 1230 * is empty 1231 */ 1232 while (available && (fifo->head != fifo->tail)) { 1233 int i = fifo->tail; 1234 const u32 *ptr = cvmx_phys_to_ptr(fifo->entry[i].address); 1235 u64 csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, 1236 usb->index) ^ 4; 1237 int words = available; 1238 1239 /* Limit the amount of data to what the SW fifo has */ 1240 if (fifo->entry[i].size <= available) { 1241 words = fifo->entry[i].size; 1242 fifo->tail++; 1243 if (fifo->tail > MAX_CHANNELS) 1244 fifo->tail = 0; 1245 } 1246 1247 /* Update the next locations and counts */ 1248 available -= words; 1249 fifo->entry[i].address += words * 4; 1250 fifo->entry[i].size -= words; 1251 1252 /* 1253 * Write the HW fifo data. The read every three writes is due 1254 * to an errata on CN3XXX chips 1255 */ 1256 while (words > 3) { 1257 cvmx_write64_uint32(csr_address, *ptr++); 1258 cvmx_write64_uint32(csr_address, *ptr++); 1259 cvmx_write64_uint32(csr_address, *ptr++); 1260 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); 1261 words -= 3; 1262 } 1263 cvmx_write64_uint32(csr_address, *ptr++); 1264 if (--words) { 1265 cvmx_write64_uint32(csr_address, *ptr++); 1266 if (--words) 1267 cvmx_write64_uint32(csr_address, *ptr++); 1268 } 1269 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index)); 1270 } 1271 return fifo->head != fifo->tail; 1272 } 1273 1274 /** 1275 * Check the hardware FIFOs and fill them as needed 1276 * 1277 * @usb: USB device state populated by cvmx_usb_initialize(). 1278 */ 1279 static void cvmx_usb_poll_tx_fifo(struct octeon_hcd *usb) 1280 { 1281 if (usb->periodic.head != usb->periodic.tail) { 1282 union cvmx_usbcx_hptxsts tx_status; 1283 1284 tx_status.u32 = cvmx_usb_read_csr32(usb, 1285 CVMX_USBCX_HPTXSTS(usb->index)); 1286 if (cvmx_usb_fill_tx_hw(usb, &usb->periodic, 1287 tx_status.s.ptxfspcavail)) 1288 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 1289 cvmx_usbcx_gintmsk, ptxfempmsk, 1); 1290 else 1291 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 1292 cvmx_usbcx_gintmsk, ptxfempmsk, 0); 1293 } 1294 1295 if (usb->nonperiodic.head != usb->nonperiodic.tail) { 1296 union cvmx_usbcx_gnptxsts tx_status; 1297 1298 tx_status.u32 = cvmx_usb_read_csr32(usb, 1299 CVMX_USBCX_GNPTXSTS(usb->index)); 1300 if (cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, 1301 tx_status.s.nptxfspcavail)) 1302 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 1303 cvmx_usbcx_gintmsk, nptxfempmsk, 1); 1304 else 1305 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 1306 cvmx_usbcx_gintmsk, nptxfempmsk, 0); 1307 } 1308 } 1309 1310 /** 1311 * Fill the TX FIFO with an outgoing packet 1312 * 1313 * @usb: USB device state populated by cvmx_usb_initialize(). 1314 * @channel: Channel number to get packet from 1315 */ 1316 static void cvmx_usb_fill_tx_fifo(struct octeon_hcd *usb, int channel) 1317 { 1318 union cvmx_usbcx_hccharx hcchar; 1319 union cvmx_usbcx_hcspltx usbc_hcsplt; 1320 union cvmx_usbcx_hctsizx usbc_hctsiz; 1321 struct cvmx_usb_tx_fifo *fifo; 1322 1323 /* We only need to fill data on outbound channels */ 1324 hcchar.u32 = cvmx_usb_read_csr32(usb, 1325 CVMX_USBCX_HCCHARX(channel, usb->index)); 1326 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT) 1327 return; 1328 1329 /* OUT Splits only have data on the start and not the complete */ 1330 usbc_hcsplt.u32 = cvmx_usb_read_csr32(usb, 1331 CVMX_USBCX_HCSPLTX(channel, usb->index)); 1332 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt) 1333 return; 1334 1335 /* 1336 * Find out how many bytes we need to fill and convert it into 32bit 1337 * words. 1338 */ 1339 usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, 1340 CVMX_USBCX_HCTSIZX(channel, usb->index)); 1341 if (!usbc_hctsiz.s.xfersize) 1342 return; 1343 1344 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) || 1345 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS)) 1346 fifo = &usb->periodic; 1347 else 1348 fifo = &usb->nonperiodic; 1349 1350 fifo->entry[fifo->head].channel = channel; 1351 fifo->entry[fifo->head].address = 1352 cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + 1353 channel * 8); 1354 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize + 3) >> 2; 1355 fifo->head++; 1356 if (fifo->head > MAX_CHANNELS) 1357 fifo->head = 0; 1358 1359 cvmx_usb_poll_tx_fifo(usb); 1360 } 1361 1362 /** 1363 * Perform channel specific setup for Control transactions. All 1364 * the generic stuff will already have been done in cvmx_usb_start_channel(). 1365 * 1366 * @usb: USB device state populated by cvmx_usb_initialize(). 1367 * @channel: Channel to setup 1368 * @pipe: Pipe for control transaction 1369 */ 1370 static void cvmx_usb_start_channel_control(struct octeon_hcd *usb, 1371 int channel, 1372 struct cvmx_usb_pipe *pipe) 1373 { 1374 struct usb_hcd *hcd = octeon_to_hcd(usb); 1375 struct device *dev = hcd->self.controller; 1376 struct cvmx_usb_transaction *transaction = 1377 list_first_entry(&pipe->transactions, typeof(*transaction), 1378 node); 1379 struct usb_ctrlrequest *header = 1380 cvmx_phys_to_ptr(transaction->control_header); 1381 int bytes_to_transfer = transaction->buffer_length - 1382 transaction->actual_bytes; 1383 int packets_to_transfer; 1384 union cvmx_usbcx_hctsizx usbc_hctsiz; 1385 1386 usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, 1387 CVMX_USBCX_HCTSIZX(channel, usb->index)); 1388 1389 switch (transaction->stage) { 1390 case CVMX_USB_STAGE_NON_CONTROL: 1391 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE: 1392 dev_err(dev, "%s: ERROR - Non control stage\n", __func__); 1393 break; 1394 case CVMX_USB_STAGE_SETUP: 1395 usbc_hctsiz.s.pid = 3; /* Setup */ 1396 bytes_to_transfer = sizeof(*header); 1397 /* All Control operations start with a setup going OUT */ 1398 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1399 cvmx_usbcx_hccharx, epdir, 1400 CVMX_USB_DIRECTION_OUT); 1401 /* 1402 * Setup send the control header instead of the buffer data. The 1403 * buffer data will be used in the next stage 1404 */ 1405 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + 1406 channel * 8, 1407 transaction->control_header); 1408 break; 1409 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE: 1410 usbc_hctsiz.s.pid = 3; /* Setup */ 1411 bytes_to_transfer = 0; 1412 /* All Control operations start with a setup going OUT */ 1413 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1414 cvmx_usbcx_hccharx, epdir, 1415 CVMX_USB_DIRECTION_OUT); 1416 1417 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), 1418 cvmx_usbcx_hcspltx, compsplt, 1); 1419 break; 1420 case CVMX_USB_STAGE_DATA: 1421 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); 1422 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 1423 if (header->bRequestType & USB_DIR_IN) 1424 bytes_to_transfer = 0; 1425 else if (bytes_to_transfer > pipe->max_packet) 1426 bytes_to_transfer = pipe->max_packet; 1427 } 1428 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1429 cvmx_usbcx_hccharx, epdir, 1430 ((header->bRequestType & USB_DIR_IN) ? 1431 CVMX_USB_DIRECTION_IN : 1432 CVMX_USB_DIRECTION_OUT)); 1433 break; 1434 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE: 1435 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); 1436 if (!(header->bRequestType & USB_DIR_IN)) 1437 bytes_to_transfer = 0; 1438 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1439 cvmx_usbcx_hccharx, epdir, 1440 ((header->bRequestType & USB_DIR_IN) ? 1441 CVMX_USB_DIRECTION_IN : 1442 CVMX_USB_DIRECTION_OUT)); 1443 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), 1444 cvmx_usbcx_hcspltx, compsplt, 1); 1445 break; 1446 case CVMX_USB_STAGE_STATUS: 1447 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); 1448 bytes_to_transfer = 0; 1449 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1450 cvmx_usbcx_hccharx, epdir, 1451 ((header->bRequestType & USB_DIR_IN) ? 1452 CVMX_USB_DIRECTION_OUT : 1453 CVMX_USB_DIRECTION_IN)); 1454 break; 1455 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE: 1456 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); 1457 bytes_to_transfer = 0; 1458 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1459 cvmx_usbcx_hccharx, epdir, 1460 ((header->bRequestType & USB_DIR_IN) ? 1461 CVMX_USB_DIRECTION_OUT : 1462 CVMX_USB_DIRECTION_IN)); 1463 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), 1464 cvmx_usbcx_hcspltx, compsplt, 1); 1465 break; 1466 } 1467 1468 /* 1469 * Make sure the transfer never exceeds the byte limit of the hardware. 1470 * Further bytes will be sent as continued transactions 1471 */ 1472 if (bytes_to_transfer > MAX_TRANSFER_BYTES) { 1473 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */ 1474 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet; 1475 bytes_to_transfer *= pipe->max_packet; 1476 } 1477 1478 /* 1479 * Calculate the number of packets to transfer. If the length is zero 1480 * we still need to transfer one packet 1481 */ 1482 packets_to_transfer = DIV_ROUND_UP(bytes_to_transfer, 1483 pipe->max_packet); 1484 if (packets_to_transfer == 0) { 1485 packets_to_transfer = 1; 1486 } else if ((packets_to_transfer > 1) && 1487 (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { 1488 /* 1489 * Limit to one packet when not using DMA. Channels must be 1490 * restarted between every packet for IN transactions, so there 1491 * is no reason to do multiple packets in a row 1492 */ 1493 packets_to_transfer = 1; 1494 bytes_to_transfer = packets_to_transfer * pipe->max_packet; 1495 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) { 1496 /* 1497 * Limit the number of packet and data transferred to what the 1498 * hardware can handle 1499 */ 1500 packets_to_transfer = MAX_TRANSFER_PACKETS; 1501 bytes_to_transfer = packets_to_transfer * pipe->max_packet; 1502 } 1503 1504 usbc_hctsiz.s.xfersize = bytes_to_transfer; 1505 usbc_hctsiz.s.pktcnt = packets_to_transfer; 1506 1507 cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), 1508 usbc_hctsiz.u32); 1509 } 1510 1511 /** 1512 * Start a channel to perform the pipe's head transaction 1513 * 1514 * @usb: USB device state populated by cvmx_usb_initialize(). 1515 * @channel: Channel to setup 1516 * @pipe: Pipe to start 1517 */ 1518 static void cvmx_usb_start_channel(struct octeon_hcd *usb, int channel, 1519 struct cvmx_usb_pipe *pipe) 1520 { 1521 struct cvmx_usb_transaction *transaction = 1522 list_first_entry(&pipe->transactions, typeof(*transaction), 1523 node); 1524 1525 /* Make sure all writes to the DMA region get flushed */ 1526 CVMX_SYNCW; 1527 1528 /* Attach the channel to the pipe */ 1529 usb->pipe_for_channel[channel] = pipe; 1530 pipe->channel = channel; 1531 pipe->flags |= CVMX_USB_PIPE_FLAGS_SCHEDULED; 1532 1533 /* Mark this channel as in use */ 1534 usb->idle_hardware_channels &= ~(1 << channel); 1535 1536 /* Enable the channel interrupt bits */ 1537 { 1538 union cvmx_usbcx_hcintx usbc_hcint; 1539 union cvmx_usbcx_hcintmskx usbc_hcintmsk; 1540 union cvmx_usbcx_haintmsk usbc_haintmsk; 1541 1542 /* Clear all channel status bits */ 1543 usbc_hcint.u32 = cvmx_usb_read_csr32(usb, 1544 CVMX_USBCX_HCINTX(channel, usb->index)); 1545 1546 cvmx_usb_write_csr32(usb, 1547 CVMX_USBCX_HCINTX(channel, usb->index), 1548 usbc_hcint.u32); 1549 1550 usbc_hcintmsk.u32 = 0; 1551 usbc_hcintmsk.s.chhltdmsk = 1; 1552 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { 1553 /* 1554 * Channels need these extra interrupts when we aren't 1555 * in DMA mode. 1556 */ 1557 usbc_hcintmsk.s.datatglerrmsk = 1; 1558 usbc_hcintmsk.s.frmovrunmsk = 1; 1559 usbc_hcintmsk.s.bblerrmsk = 1; 1560 usbc_hcintmsk.s.xacterrmsk = 1; 1561 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 1562 /* 1563 * Splits don't generate xfercompl, so we need 1564 * ACK and NYET. 1565 */ 1566 usbc_hcintmsk.s.nyetmsk = 1; 1567 usbc_hcintmsk.s.ackmsk = 1; 1568 } 1569 usbc_hcintmsk.s.nakmsk = 1; 1570 usbc_hcintmsk.s.stallmsk = 1; 1571 usbc_hcintmsk.s.xfercomplmsk = 1; 1572 } 1573 cvmx_usb_write_csr32(usb, 1574 CVMX_USBCX_HCINTMSKX(channel, usb->index), 1575 usbc_hcintmsk.u32); 1576 1577 /* Enable the channel interrupt to propagate */ 1578 usbc_haintmsk.u32 = cvmx_usb_read_csr32(usb, 1579 CVMX_USBCX_HAINTMSK(usb->index)); 1580 usbc_haintmsk.s.haintmsk |= 1 << channel; 1581 cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), 1582 usbc_haintmsk.u32); 1583 } 1584 1585 /* Setup the location the DMA engine uses. */ 1586 { 1587 u64 reg; 1588 u64 dma_address = transaction->buffer + 1589 transaction->actual_bytes; 1590 1591 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) 1592 dma_address = transaction->buffer + 1593 transaction->iso_packets[0].offset + 1594 transaction->actual_bytes; 1595 1596 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) 1597 reg = CVMX_USBNX_DMA0_OUTB_CHN0(usb->index); 1598 else 1599 reg = CVMX_USBNX_DMA0_INB_CHN0(usb->index); 1600 cvmx_write64_uint64(reg + channel * 8, dma_address); 1601 } 1602 1603 /* Setup both the size of the transfer and the SPLIT characteristics */ 1604 { 1605 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0}; 1606 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0}; 1607 int packets_to_transfer; 1608 int bytes_to_transfer = transaction->buffer_length - 1609 transaction->actual_bytes; 1610 1611 /* 1612 * ISOCHRONOUS transactions store each individual transfer size 1613 * in the packet structure, not the global buffer_length 1614 */ 1615 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) 1616 bytes_to_transfer = 1617 transaction->iso_packets[0].length - 1618 transaction->actual_bytes; 1619 1620 /* 1621 * We need to do split transactions when we are talking to non 1622 * high speed devices that are behind a high speed hub 1623 */ 1624 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 1625 /* 1626 * On the start split phase (stage is even) record the 1627 * frame number we will need to send the split complete. 1628 * We only store the lower two bits since the time ahead 1629 * can only be two frames 1630 */ 1631 if ((transaction->stage & 1) == 0) { 1632 if (transaction->type == CVMX_USB_TRANSFER_BULK) 1633 pipe->split_sc_frame = 1634 (usb->frame_number + 1) & 0x7f; 1635 else 1636 pipe->split_sc_frame = 1637 (usb->frame_number + 2) & 0x7f; 1638 } else { 1639 pipe->split_sc_frame = -1; 1640 } 1641 1642 usbc_hcsplt.s.spltena = 1; 1643 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr; 1644 usbc_hcsplt.s.prtaddr = pipe->hub_port; 1645 usbc_hcsplt.s.compsplt = (transaction->stage == 1646 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE); 1647 1648 /* 1649 * SPLIT transactions can only ever transmit one data 1650 * packet so limit the transfer size to the max packet 1651 * size 1652 */ 1653 if (bytes_to_transfer > pipe->max_packet) 1654 bytes_to_transfer = pipe->max_packet; 1655 1656 /* 1657 * ISOCHRONOUS OUT splits are unique in that they limit 1658 * data transfers to 188 byte chunks representing the 1659 * begin/middle/end of the data or all 1660 */ 1661 if (!usbc_hcsplt.s.compsplt && 1662 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) && 1663 (pipe->transfer_type == 1664 CVMX_USB_TRANSFER_ISOCHRONOUS)) { 1665 /* 1666 * Clear the split complete frame number as 1667 * there isn't going to be a split complete 1668 */ 1669 pipe->split_sc_frame = -1; 1670 /* 1671 * See if we've started this transfer and sent 1672 * data 1673 */ 1674 if (transaction->actual_bytes == 0) { 1675 /* 1676 * Nothing sent yet, this is either a 1677 * begin or the entire payload 1678 */ 1679 if (bytes_to_transfer <= 188) 1680 /* Entire payload in one go */ 1681 usbc_hcsplt.s.xactpos = 3; 1682 else 1683 /* First part of payload */ 1684 usbc_hcsplt.s.xactpos = 2; 1685 } else { 1686 /* 1687 * Continuing the previous data, we must 1688 * either be in the middle or at the end 1689 */ 1690 if (bytes_to_transfer <= 188) 1691 /* End of payload */ 1692 usbc_hcsplt.s.xactpos = 1; 1693 else 1694 /* Middle of payload */ 1695 usbc_hcsplt.s.xactpos = 0; 1696 } 1697 /* 1698 * Again, the transfer size is limited to 188 1699 * bytes 1700 */ 1701 if (bytes_to_transfer > 188) 1702 bytes_to_transfer = 188; 1703 } 1704 } 1705 1706 /* 1707 * Make sure the transfer never exceeds the byte limit of the 1708 * hardware. Further bytes will be sent as continued 1709 * transactions 1710 */ 1711 if (bytes_to_transfer > MAX_TRANSFER_BYTES) { 1712 /* 1713 * Round MAX_TRANSFER_BYTES to a multiple of out packet 1714 * size 1715 */ 1716 bytes_to_transfer = MAX_TRANSFER_BYTES / 1717 pipe->max_packet; 1718 bytes_to_transfer *= pipe->max_packet; 1719 } 1720 1721 /* 1722 * Calculate the number of packets to transfer. If the length is 1723 * zero we still need to transfer one packet 1724 */ 1725 packets_to_transfer = 1726 DIV_ROUND_UP(bytes_to_transfer, pipe->max_packet); 1727 if (packets_to_transfer == 0) { 1728 packets_to_transfer = 1; 1729 } else if ((packets_to_transfer > 1) && 1730 (usb->init_flags & 1731 CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { 1732 /* 1733 * Limit to one packet when not using DMA. Channels must 1734 * be restarted between every packet for IN 1735 * transactions, so there is no reason to do multiple 1736 * packets in a row 1737 */ 1738 packets_to_transfer = 1; 1739 bytes_to_transfer = packets_to_transfer * 1740 pipe->max_packet; 1741 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) { 1742 /* 1743 * Limit the number of packet and data transferred to 1744 * what the hardware can handle 1745 */ 1746 packets_to_transfer = MAX_TRANSFER_PACKETS; 1747 bytes_to_transfer = packets_to_transfer * 1748 pipe->max_packet; 1749 } 1750 1751 usbc_hctsiz.s.xfersize = bytes_to_transfer; 1752 usbc_hctsiz.s.pktcnt = packets_to_transfer; 1753 1754 /* Update the DATA0/DATA1 toggle */ 1755 usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); 1756 /* 1757 * High speed pipes may need a hardware ping before they start 1758 */ 1759 if (pipe->flags & CVMX_USB_PIPE_FLAGS_NEED_PING) 1760 usbc_hctsiz.s.dopng = 1; 1761 1762 cvmx_usb_write_csr32(usb, 1763 CVMX_USBCX_HCSPLTX(channel, usb->index), 1764 usbc_hcsplt.u32); 1765 cvmx_usb_write_csr32(usb, 1766 CVMX_USBCX_HCTSIZX(channel, usb->index), 1767 usbc_hctsiz.u32); 1768 } 1769 1770 /* Setup the Host Channel Characteristics Register */ 1771 { 1772 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0}; 1773 1774 /* 1775 * Set the startframe odd/even properly. This is only used for 1776 * periodic 1777 */ 1778 usbc_hcchar.s.oddfrm = usb->frame_number & 1; 1779 1780 /* 1781 * Set the number of back to back packets allowed by this 1782 * endpoint. Split transactions interpret "ec" as the number of 1783 * immediate retries of failure. These retries happen too 1784 * quickly, so we disable these entirely for splits 1785 */ 1786 if (cvmx_usb_pipe_needs_split(usb, pipe)) 1787 usbc_hcchar.s.ec = 1; 1788 else if (pipe->multi_count < 1) 1789 usbc_hcchar.s.ec = 1; 1790 else if (pipe->multi_count > 3) 1791 usbc_hcchar.s.ec = 3; 1792 else 1793 usbc_hcchar.s.ec = pipe->multi_count; 1794 1795 /* Set the rest of the endpoint specific settings */ 1796 usbc_hcchar.s.devaddr = pipe->device_addr; 1797 usbc_hcchar.s.eptype = transaction->type; 1798 usbc_hcchar.s.lspddev = 1799 (pipe->device_speed == CVMX_USB_SPEED_LOW); 1800 usbc_hcchar.s.epdir = pipe->transfer_dir; 1801 usbc_hcchar.s.epnum = pipe->endpoint_num; 1802 usbc_hcchar.s.mps = pipe->max_packet; 1803 cvmx_usb_write_csr32(usb, 1804 CVMX_USBCX_HCCHARX(channel, usb->index), 1805 usbc_hcchar.u32); 1806 } 1807 1808 /* Do transaction type specific fixups as needed */ 1809 switch (transaction->type) { 1810 case CVMX_USB_TRANSFER_CONTROL: 1811 cvmx_usb_start_channel_control(usb, channel, pipe); 1812 break; 1813 case CVMX_USB_TRANSFER_BULK: 1814 case CVMX_USB_TRANSFER_INTERRUPT: 1815 break; 1816 case CVMX_USB_TRANSFER_ISOCHRONOUS: 1817 if (!cvmx_usb_pipe_needs_split(usb, pipe)) { 1818 /* 1819 * ISO transactions require different PIDs depending on 1820 * direction and how many packets are needed 1821 */ 1822 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) { 1823 if (pipe->multi_count < 2) /* Need DATA0 */ 1824 USB_SET_FIELD32( 1825 CVMX_USBCX_HCTSIZX(channel, 1826 usb->index), 1827 cvmx_usbcx_hctsizx, pid, 0); 1828 else /* Need MDATA */ 1829 USB_SET_FIELD32( 1830 CVMX_USBCX_HCTSIZX(channel, 1831 usb->index), 1832 cvmx_usbcx_hctsizx, pid, 3); 1833 } 1834 } 1835 break; 1836 } 1837 { 1838 union cvmx_usbcx_hctsizx usbc_hctsiz = { .u32 = 1839 cvmx_usb_read_csr32(usb, 1840 CVMX_USBCX_HCTSIZX(channel, 1841 usb->index)) 1842 }; 1843 transaction->xfersize = usbc_hctsiz.s.xfersize; 1844 transaction->pktcnt = usbc_hctsiz.s.pktcnt; 1845 } 1846 /* Remember when we start a split transaction */ 1847 if (cvmx_usb_pipe_needs_split(usb, pipe)) 1848 usb->active_split = transaction; 1849 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), 1850 cvmx_usbcx_hccharx, chena, 1); 1851 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) 1852 cvmx_usb_fill_tx_fifo(usb, channel); 1853 } 1854 1855 /** 1856 * Find a pipe that is ready to be scheduled to hardware. 1857 * @usb: USB device state populated by cvmx_usb_initialize(). 1858 * @xfer_type: Transfer type 1859 * 1860 * Returns: Pipe or NULL if none are ready 1861 */ 1862 static struct cvmx_usb_pipe *cvmx_usb_find_ready_pipe(struct octeon_hcd *usb, 1863 enum cvmx_usb_transfer xfer_type) 1864 { 1865 struct list_head *list = usb->active_pipes + xfer_type; 1866 u64 current_frame = usb->frame_number; 1867 struct cvmx_usb_pipe *pipe; 1868 1869 list_for_each_entry(pipe, list, node) { 1870 struct cvmx_usb_transaction *t = 1871 list_first_entry(&pipe->transactions, typeof(*t), 1872 node); 1873 if (!(pipe->flags & CVMX_USB_PIPE_FLAGS_SCHEDULED) && t && 1874 (pipe->next_tx_frame <= current_frame) && 1875 ((pipe->split_sc_frame == -1) || 1876 ((((int)current_frame - pipe->split_sc_frame) & 0x7f) < 1877 0x40)) && 1878 (!usb->active_split || (usb->active_split == t))) { 1879 prefetch(t); 1880 return pipe; 1881 } 1882 } 1883 return NULL; 1884 } 1885 1886 static struct cvmx_usb_pipe *cvmx_usb_next_pipe(struct octeon_hcd *usb, 1887 int is_sof) 1888 { 1889 struct cvmx_usb_pipe *pipe; 1890 1891 /* Find a pipe needing service. */ 1892 if (is_sof) { 1893 /* 1894 * Only process periodic pipes on SOF interrupts. This way we 1895 * are sure that the periodic data is sent in the beginning of 1896 * the frame. 1897 */ 1898 pipe = cvmx_usb_find_ready_pipe(usb, 1899 CVMX_USB_TRANSFER_ISOCHRONOUS); 1900 if (pipe) 1901 return pipe; 1902 pipe = cvmx_usb_find_ready_pipe(usb, 1903 CVMX_USB_TRANSFER_INTERRUPT); 1904 if (pipe) 1905 return pipe; 1906 } 1907 pipe = cvmx_usb_find_ready_pipe(usb, CVMX_USB_TRANSFER_CONTROL); 1908 if (pipe) 1909 return pipe; 1910 return cvmx_usb_find_ready_pipe(usb, CVMX_USB_TRANSFER_BULK); 1911 } 1912 1913 /** 1914 * Called whenever a pipe might need to be scheduled to the 1915 * hardware. 1916 * 1917 * @usb: USB device state populated by cvmx_usb_initialize(). 1918 * @is_sof: True if this schedule was called on a SOF interrupt. 1919 */ 1920 static void cvmx_usb_schedule(struct octeon_hcd *usb, int is_sof) 1921 { 1922 int channel; 1923 struct cvmx_usb_pipe *pipe; 1924 int need_sof; 1925 u64 min_due; 1926 enum cvmx_usb_transfer ttype; 1927 1928 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { 1929 /* 1930 * Without DMA we need to be careful to not schedule something 1931 * at the end of a frame and cause an overrun. 1932 */ 1933 union cvmx_usbcx_hfnum hfnum = { 1934 .u32 = cvmx_usb_read_csr32(usb, 1935 CVMX_USBCX_HFNUM(usb->index)) 1936 }; 1937 1938 union cvmx_usbcx_hfir hfir = { 1939 .u32 = cvmx_usb_read_csr32(usb, 1940 CVMX_USBCX_HFIR(usb->index)) 1941 }; 1942 1943 if (hfnum.s.frrem < hfir.s.frint / 4) 1944 goto done; 1945 } 1946 1947 while (usb->idle_hardware_channels) { 1948 /* Find an idle channel */ 1949 channel = __fls(usb->idle_hardware_channels); 1950 if (unlikely(channel > 7)) 1951 break; 1952 1953 pipe = cvmx_usb_next_pipe(usb, is_sof); 1954 if (!pipe) 1955 break; 1956 1957 cvmx_usb_start_channel(usb, channel, pipe); 1958 } 1959 1960 done: 1961 /* 1962 * Only enable SOF interrupts when we have transactions pending in the 1963 * future that might need to be scheduled 1964 */ 1965 need_sof = 0; 1966 min_due = ~0ull; 1967 for (ttype = CVMX_USB_TRANSFER_CONTROL; 1968 ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) { 1969 list_for_each_entry(pipe, &usb->active_pipes[ttype], node) { 1970 if (pipe->next_tx_frame > usb->frame_number && 1971 pipe->next_tx_frame < min_due) 1972 min_due = pipe->next_tx_frame; 1973 } 1974 } 1975 if (min_due != ~0ull) { 1976 u64 delta = min_due - usb->frame_number; 1977 1978 /* 1979 * frame_number is resynced from HFNUM on every poll, so a 1980 * deadline that is many frames away does not need an 1981 * interrupt on every SOF to count them down - sleep on the 1982 * timer instead and keep SOF interrupts for deadlines within 1983 * a few frames. Stay well below the 16383-frame wrap of 1984 * HFNUM. One (micro)frame is 125us in high-speed mode. 1985 */ 1986 if (delta <= 4 || delta > 8000) 1987 need_sof = 1; 1988 else 1989 hrtimer_start(&usb->sof_timer, 1990 ns_to_ktime((delta - 2) * 125000), 1991 HRTIMER_MODE_REL); 1992 } 1993 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), 1994 cvmx_usbcx_gintmsk, sofmsk, need_sof); 1995 } 1996 1997 static void octeon_usb_urb_complete_callback(struct octeon_hcd *usb, 1998 enum cvmx_usb_status status, 1999 struct cvmx_usb_pipe *pipe, 2000 struct cvmx_usb_transaction 2001 *transaction, 2002 int bytes_transferred, 2003 struct urb *urb) 2004 { 2005 struct usb_hcd *hcd = octeon_to_hcd(usb); 2006 struct device *dev = hcd->self.controller; 2007 2008 if (likely(status == CVMX_USB_STATUS_OK)) 2009 urb->actual_length = bytes_transferred; 2010 else 2011 urb->actual_length = 0; 2012 2013 urb->hcpriv = NULL; 2014 2015 /* For Isochronous transactions we need to update the URB packet status 2016 * list from data in our private copy 2017 */ 2018 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2019 int i; 2020 /* 2021 * The pointer to the private list is stored in the setup_packet 2022 * field. 2023 */ 2024 struct cvmx_usb_iso_packet *iso_packet = 2025 (struct cvmx_usb_iso_packet *)urb->setup_packet; 2026 /* Recalculate the transfer size by adding up each packet */ 2027 urb->actual_length = 0; 2028 for (i = 0; i < urb->number_of_packets; i++) { 2029 if (iso_packet[i].status == CVMX_USB_STATUS_OK) { 2030 urb->iso_frame_desc[i].status = 0; 2031 urb->iso_frame_desc[i].actual_length = 2032 iso_packet[i].length; 2033 urb->actual_length += 2034 urb->iso_frame_desc[i].actual_length; 2035 } else { 2036 dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n", 2037 i, urb->number_of_packets, 2038 iso_packet[i].status, pipe, 2039 transaction, iso_packet[i].length); 2040 urb->iso_frame_desc[i].status = -EREMOTEIO; 2041 } 2042 } 2043 /* Free the private list now that we don't need it anymore */ 2044 kfree(iso_packet); 2045 urb->setup_packet = NULL; 2046 } 2047 2048 switch (status) { 2049 case CVMX_USB_STATUS_OK: 2050 urb->status = 0; 2051 break; 2052 case CVMX_USB_STATUS_CANCEL: 2053 if (urb->status == 0) 2054 urb->status = -ENOENT; 2055 break; 2056 case CVMX_USB_STATUS_STALL: 2057 dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n", 2058 pipe, transaction, bytes_transferred); 2059 urb->status = -EPIPE; 2060 break; 2061 case CVMX_USB_STATUS_BABBLEERR: 2062 dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n", 2063 pipe, transaction, bytes_transferred); 2064 urb->status = -EPIPE; 2065 break; 2066 case CVMX_USB_STATUS_SHORT: 2067 dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n", 2068 pipe, transaction, bytes_transferred); 2069 urb->status = -EREMOTEIO; 2070 break; 2071 case CVMX_USB_STATUS_ERROR: 2072 case CVMX_USB_STATUS_XACTERR: 2073 case CVMX_USB_STATUS_DATATGLERR: 2074 case CVMX_USB_STATUS_FRAMEERR: 2075 dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n", 2076 status, pipe, transaction, bytes_transferred); 2077 urb->status = -EPROTO; 2078 break; 2079 } 2080 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(usb), urb); 2081 spin_unlock(&usb->lock); 2082 usb_hcd_giveback_urb(octeon_to_hcd(usb), urb, urb->status); 2083 spin_lock(&usb->lock); 2084 } 2085 2086 /** 2087 * Signal the completion of a transaction and free it. The 2088 * transaction will be removed from the pipe transaction list. 2089 * 2090 * @usb: USB device state populated by cvmx_usb_initialize(). 2091 * @pipe: Pipe the transaction is on 2092 * @transaction: 2093 * Transaction that completed 2094 * @complete_code: 2095 * Completion code 2096 */ 2097 static void cvmx_usb_complete(struct octeon_hcd *usb, 2098 struct cvmx_usb_pipe *pipe, 2099 struct cvmx_usb_transaction *transaction, 2100 enum cvmx_usb_status complete_code) 2101 { 2102 /* If this was a split then clear our split in progress marker */ 2103 if (usb->active_split == transaction) 2104 usb->active_split = NULL; 2105 2106 /* 2107 * Isochronous transactions need extra processing as they might not be 2108 * done after a single data transfer 2109 */ 2110 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) { 2111 /* Update the number of bytes transferred in this ISO packet */ 2112 transaction->iso_packets[0].length = transaction->actual_bytes; 2113 transaction->iso_packets[0].status = complete_code; 2114 2115 /* 2116 * If there are more ISOs pending and we succeeded, schedule the 2117 * next one 2118 */ 2119 if ((transaction->iso_number_packets > 1) && 2120 (complete_code == CVMX_USB_STATUS_OK)) { 2121 /* No bytes transferred for this packet as of yet */ 2122 transaction->actual_bytes = 0; 2123 /* One less ISO waiting to transfer */ 2124 transaction->iso_number_packets--; 2125 /* Increment to the next location in our packet array */ 2126 transaction->iso_packets++; 2127 transaction->stage = CVMX_USB_STAGE_NON_CONTROL; 2128 return; 2129 } 2130 } 2131 2132 /* Remove the transaction from the pipe list */ 2133 list_del(&transaction->node); 2134 if (list_empty(&pipe->transactions)) 2135 list_move_tail(&pipe->node, &usb->idle_pipes); 2136 octeon_usb_urb_complete_callback(usb, complete_code, pipe, 2137 transaction, 2138 transaction->actual_bytes, 2139 transaction->urb); 2140 kfree(transaction); 2141 } 2142 2143 /** 2144 * Submit a usb transaction to a pipe. Called for all types 2145 * of transactions. 2146 * 2147 * @usb: 2148 * @pipe: Which pipe to submit to. 2149 * @type: Transaction type 2150 * @buffer: User buffer for the transaction 2151 * @buffer_length: 2152 * User buffer's length in bytes 2153 * @control_header: 2154 * For control transactions, the 8 byte standard header 2155 * @iso_start_frame: 2156 * For ISO transactions, the start frame 2157 * @iso_number_packets: 2158 * For ISO, the number of packet in the transaction. 2159 * @iso_packets: 2160 * A description of each ISO packet 2161 * @urb: URB for the callback 2162 * 2163 * Returns: Transaction or NULL on failure. 2164 */ 2165 static struct cvmx_usb_transaction *cvmx_usb_submit_transaction( 2166 struct octeon_hcd *usb, 2167 struct cvmx_usb_pipe *pipe, 2168 enum cvmx_usb_transfer type, 2169 u64 buffer, 2170 int buffer_length, 2171 u64 control_header, 2172 int iso_start_frame, 2173 int iso_number_packets, 2174 struct cvmx_usb_iso_packet *iso_packets, 2175 struct urb *urb) 2176 { 2177 struct cvmx_usb_transaction *transaction; 2178 2179 if (unlikely(pipe->transfer_type != type)) 2180 return NULL; 2181 2182 transaction = kzalloc_obj(*transaction, GFP_ATOMIC); 2183 if (unlikely(!transaction)) 2184 return NULL; 2185 2186 transaction->type = type; 2187 transaction->buffer = buffer; 2188 transaction->buffer_length = buffer_length; 2189 transaction->control_header = control_header; 2190 /* FIXME: This is not used, implement it. */ 2191 transaction->iso_start_frame = iso_start_frame; 2192 transaction->iso_number_packets = iso_number_packets; 2193 transaction->iso_packets = iso_packets; 2194 transaction->urb = urb; 2195 if (transaction->type == CVMX_USB_TRANSFER_CONTROL) 2196 transaction->stage = CVMX_USB_STAGE_SETUP; 2197 else 2198 transaction->stage = CVMX_USB_STAGE_NON_CONTROL; 2199 2200 if (!list_empty(&pipe->transactions)) { 2201 list_add_tail(&transaction->node, &pipe->transactions); 2202 } else { 2203 list_add_tail(&transaction->node, &pipe->transactions); 2204 list_move_tail(&pipe->node, 2205 &usb->active_pipes[pipe->transfer_type]); 2206 2207 /* 2208 * We may need to schedule the pipe if this was the head of the 2209 * pipe. 2210 */ 2211 cvmx_usb_schedule(usb, 0); 2212 } 2213 2214 return transaction; 2215 } 2216 2217 /** 2218 * Call to submit a USB Bulk transfer to a pipe. 2219 * 2220 * @usb: USB device state populated by cvmx_usb_initialize(). 2221 * @pipe: Handle to the pipe for the transfer. 2222 * @urb: URB. 2223 * 2224 * Returns: A submitted transaction or NULL on failure. 2225 */ 2226 static struct cvmx_usb_transaction *cvmx_usb_submit_bulk( 2227 struct octeon_hcd *usb, 2228 struct cvmx_usb_pipe *pipe, 2229 struct urb *urb) 2230 { 2231 return cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK, 2232 urb->transfer_dma, 2233 urb->transfer_buffer_length, 2234 0, /* control_header */ 2235 0, /* iso_start_frame */ 2236 0, /* iso_number_packets */ 2237 NULL, /* iso_packets */ 2238 urb); 2239 } 2240 2241 /** 2242 * Call to submit a USB Interrupt transfer to a pipe. 2243 * 2244 * @usb: USB device state populated by cvmx_usb_initialize(). 2245 * @pipe: Handle to the pipe for the transfer. 2246 * @urb: URB returned when the callback is called. 2247 * 2248 * Returns: A submitted transaction or NULL on failure. 2249 */ 2250 static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt( 2251 struct octeon_hcd *usb, 2252 struct cvmx_usb_pipe *pipe, 2253 struct urb *urb) 2254 { 2255 return cvmx_usb_submit_transaction(usb, pipe, 2256 CVMX_USB_TRANSFER_INTERRUPT, 2257 urb->transfer_dma, 2258 urb->transfer_buffer_length, 2259 0, /* control_header */ 2260 0, /* iso_start_frame */ 2261 0, /* iso_number_packets */ 2262 NULL, /* iso_packets */ 2263 urb); 2264 } 2265 2266 /** 2267 * Call to submit a USB Control transfer to a pipe. 2268 * 2269 * @usb: USB device state populated by cvmx_usb_initialize(). 2270 * @pipe: Handle to the pipe for the transfer. 2271 * @urb: URB. 2272 * 2273 * Returns: A submitted transaction or NULL on failure. 2274 */ 2275 static struct cvmx_usb_transaction *cvmx_usb_submit_control( 2276 struct octeon_hcd *usb, 2277 struct cvmx_usb_pipe *pipe, 2278 struct urb *urb) 2279 { 2280 int buffer_length = urb->transfer_buffer_length; 2281 u64 control_header = urb->setup_dma; 2282 struct usb_ctrlrequest *header = cvmx_phys_to_ptr(control_header); 2283 2284 if ((header->bRequestType & USB_DIR_IN) == 0) 2285 buffer_length = le16_to_cpu(header->wLength); 2286 2287 return cvmx_usb_submit_transaction(usb, pipe, 2288 CVMX_USB_TRANSFER_CONTROL, 2289 urb->transfer_dma, buffer_length, 2290 control_header, 2291 0, /* iso_start_frame */ 2292 0, /* iso_number_packets */ 2293 NULL, /* iso_packets */ 2294 urb); 2295 } 2296 2297 /** 2298 * Call to submit a USB Isochronous transfer to a pipe. 2299 * 2300 * @usb: USB device state populated by cvmx_usb_initialize(). 2301 * @pipe: Handle to the pipe for the transfer. 2302 * @urb: URB returned when the callback is called. 2303 * 2304 * Returns: A submitted transaction or NULL on failure. 2305 */ 2306 static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous( 2307 struct octeon_hcd *usb, 2308 struct cvmx_usb_pipe *pipe, 2309 struct urb *urb) 2310 { 2311 struct cvmx_usb_iso_packet *packets; 2312 2313 packets = (struct cvmx_usb_iso_packet *)urb->setup_packet; 2314 return cvmx_usb_submit_transaction(usb, pipe, 2315 CVMX_USB_TRANSFER_ISOCHRONOUS, 2316 urb->transfer_dma, 2317 urb->transfer_buffer_length, 2318 0, /* control_header */ 2319 urb->start_frame, 2320 urb->number_of_packets, 2321 packets, urb); 2322 } 2323 2324 /** 2325 * Cancel one outstanding request in a pipe. Canceling a request 2326 * can fail if the transaction has already completed before cancel 2327 * is called. Even after a successful cancel call, it may take 2328 * a frame or two for the cvmx_usb_poll() function to call the 2329 * associated callback. 2330 * 2331 * @usb: USB device state populated by cvmx_usb_initialize(). 2332 * @pipe: Pipe to cancel requests in. 2333 * @transaction: Transaction to cancel, returned by the submit function. 2334 * 2335 * Returns: 0 or a negative error code. 2336 */ 2337 static int cvmx_usb_cancel(struct octeon_hcd *usb, 2338 struct cvmx_usb_pipe *pipe, 2339 struct cvmx_usb_transaction *transaction) 2340 { 2341 /* 2342 * If the transaction is the HEAD of the queue and scheduled. We need to 2343 * treat it special 2344 */ 2345 if (list_first_entry(&pipe->transactions, typeof(*transaction), node) == 2346 transaction && (pipe->flags & CVMX_USB_PIPE_FLAGS_SCHEDULED)) { 2347 union cvmx_usbcx_hccharx usbc_hcchar; 2348 2349 usb->pipe_for_channel[pipe->channel] = NULL; 2350 pipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED; 2351 2352 CVMX_SYNCW; 2353 2354 usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, 2355 CVMX_USBCX_HCCHARX(pipe->channel, 2356 usb->index)); 2357 /* 2358 * If the channel isn't enabled then the transaction already 2359 * completed. 2360 */ 2361 if (usbc_hcchar.s.chena) { 2362 usbc_hcchar.s.chdis = 1; 2363 cvmx_usb_write_csr32(usb, 2364 CVMX_USBCX_HCCHARX(pipe->channel, 2365 usb->index), 2366 usbc_hcchar.u32); 2367 } 2368 } 2369 cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_CANCEL); 2370 return 0; 2371 } 2372 2373 /** 2374 * Cancel all outstanding requests in a pipe. Logically all this 2375 * does is call cvmx_usb_cancel() in a loop. 2376 * 2377 * @usb: USB device state populated by cvmx_usb_initialize(). 2378 * @pipe: Pipe to cancel requests in. 2379 * 2380 * Returns: 0 or a negative error code. 2381 */ 2382 static int cvmx_usb_cancel_all(struct octeon_hcd *usb, 2383 struct cvmx_usb_pipe *pipe) 2384 { 2385 struct cvmx_usb_transaction *transaction, *next; 2386 2387 /* Simply loop through and attempt to cancel each transaction */ 2388 list_for_each_entry_safe(transaction, next, &pipe->transactions, node) { 2389 int result = cvmx_usb_cancel(usb, pipe, transaction); 2390 2391 if (unlikely(result != 0)) 2392 return result; 2393 } 2394 return 0; 2395 } 2396 2397 /** 2398 * Close a pipe created with cvmx_usb_open_pipe(). 2399 * 2400 * @usb: USB device state populated by cvmx_usb_initialize(). 2401 * @pipe: Pipe to close. 2402 * 2403 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has 2404 * outstanding transfers. 2405 */ 2406 static int cvmx_usb_close_pipe(struct octeon_hcd *usb, 2407 struct cvmx_usb_pipe *pipe) 2408 { 2409 /* Fail if the pipe has pending transactions */ 2410 if (!list_empty(&pipe->transactions)) 2411 return -EBUSY; 2412 2413 list_del(&pipe->node); 2414 kfree(pipe); 2415 2416 return 0; 2417 } 2418 2419 /** 2420 * Get the current USB protocol level frame number. The frame 2421 * number is always in the range of 0-0x7ff. 2422 * 2423 * @usb: USB device state populated by cvmx_usb_initialize(). 2424 * 2425 * Returns: USB frame number 2426 */ 2427 static int cvmx_usb_get_frame_number(struct octeon_hcd *usb) 2428 { 2429 union cvmx_usbcx_hfnum usbc_hfnum; 2430 2431 usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index)); 2432 2433 return usbc_hfnum.s.frnum; 2434 } 2435 2436 static void cvmx_usb_transfer_control(struct octeon_hcd *usb, 2437 struct cvmx_usb_pipe *pipe, 2438 struct cvmx_usb_transaction *transaction, 2439 union cvmx_usbcx_hccharx usbc_hcchar, 2440 int buffer_space_left, 2441 int bytes_in_last_packet) 2442 { 2443 switch (transaction->stage) { 2444 case CVMX_USB_STAGE_NON_CONTROL: 2445 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE: 2446 /* This should be impossible */ 2447 cvmx_usb_complete(usb, pipe, transaction, 2448 CVMX_USB_STATUS_ERROR); 2449 break; 2450 case CVMX_USB_STAGE_SETUP: 2451 pipe->pid_toggle = 1; 2452 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 2453 transaction->stage = 2454 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE; 2455 } else { 2456 struct usb_ctrlrequest *header = 2457 cvmx_phys_to_ptr(transaction->control_header); 2458 if (header->wLength) 2459 transaction->stage = CVMX_USB_STAGE_DATA; 2460 else 2461 transaction->stage = CVMX_USB_STAGE_STATUS; 2462 } 2463 break; 2464 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE: 2465 { 2466 struct usb_ctrlrequest *header = 2467 cvmx_phys_to_ptr(transaction->control_header); 2468 if (header->wLength) 2469 transaction->stage = CVMX_USB_STAGE_DATA; 2470 else 2471 transaction->stage = CVMX_USB_STAGE_STATUS; 2472 } 2473 break; 2474 case CVMX_USB_STAGE_DATA: 2475 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 2476 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE; 2477 /* 2478 * For setup OUT data that are splits, 2479 * the hardware doesn't appear to count 2480 * transferred data. Here we manually 2481 * update the data transferred 2482 */ 2483 if (!usbc_hcchar.s.epdir) { 2484 if (buffer_space_left < pipe->max_packet) 2485 transaction->actual_bytes += 2486 buffer_space_left; 2487 else 2488 transaction->actual_bytes += 2489 pipe->max_packet; 2490 } 2491 } else if ((buffer_space_left == 0) || 2492 (bytes_in_last_packet < pipe->max_packet)) { 2493 pipe->pid_toggle = 1; 2494 transaction->stage = CVMX_USB_STAGE_STATUS; 2495 } 2496 break; 2497 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE: 2498 if ((buffer_space_left == 0) || 2499 (bytes_in_last_packet < pipe->max_packet)) { 2500 pipe->pid_toggle = 1; 2501 transaction->stage = CVMX_USB_STAGE_STATUS; 2502 } else { 2503 transaction->stage = CVMX_USB_STAGE_DATA; 2504 } 2505 break; 2506 case CVMX_USB_STAGE_STATUS: 2507 if (cvmx_usb_pipe_needs_split(usb, pipe)) 2508 transaction->stage = 2509 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE; 2510 else 2511 cvmx_usb_complete(usb, pipe, transaction, 2512 CVMX_USB_STATUS_OK); 2513 break; 2514 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE: 2515 cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_OK); 2516 break; 2517 } 2518 } 2519 2520 static void cvmx_usb_transfer_bulk(struct octeon_hcd *usb, 2521 struct cvmx_usb_pipe *pipe, 2522 struct cvmx_usb_transaction *transaction, 2523 union cvmx_usbcx_hcintx usbc_hcint, 2524 int buffer_space_left, 2525 int bytes_in_last_packet) 2526 { 2527 /* 2528 * The only time a bulk transfer isn't complete when it finishes with 2529 * an ACK is during a split transaction. For splits we need to continue 2530 * the transfer if more data is needed. 2531 */ 2532 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 2533 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL) 2534 transaction->stage = 2535 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; 2536 else if (buffer_space_left && 2537 (bytes_in_last_packet == pipe->max_packet)) 2538 transaction->stage = CVMX_USB_STAGE_NON_CONTROL; 2539 else 2540 cvmx_usb_complete(usb, pipe, transaction, 2541 CVMX_USB_STATUS_OK); 2542 } else { 2543 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) && 2544 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) && 2545 (usbc_hcint.s.nak)) 2546 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; 2547 if (!buffer_space_left || 2548 (bytes_in_last_packet < pipe->max_packet)) 2549 cvmx_usb_complete(usb, pipe, transaction, 2550 CVMX_USB_STATUS_OK); 2551 } 2552 } 2553 2554 static void cvmx_usb_transfer_intr(struct octeon_hcd *usb, 2555 struct cvmx_usb_pipe *pipe, 2556 struct cvmx_usb_transaction *transaction, 2557 int buffer_space_left, 2558 int bytes_in_last_packet) 2559 { 2560 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 2561 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL) { 2562 transaction->stage = 2563 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; 2564 } else if (buffer_space_left && 2565 (bytes_in_last_packet == pipe->max_packet)) { 2566 transaction->stage = CVMX_USB_STAGE_NON_CONTROL; 2567 } else { 2568 pipe->next_tx_frame += pipe->interval; 2569 cvmx_usb_complete(usb, pipe, transaction, 2570 CVMX_USB_STATUS_OK); 2571 } 2572 } else if (!buffer_space_left || 2573 (bytes_in_last_packet < pipe->max_packet)) { 2574 pipe->next_tx_frame += pipe->interval; 2575 cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_OK); 2576 } 2577 } 2578 2579 static void cvmx_usb_transfer_isoc(struct octeon_hcd *usb, 2580 struct cvmx_usb_pipe *pipe, 2581 struct cvmx_usb_transaction *transaction, 2582 int buffer_space_left, 2583 int bytes_in_last_packet, 2584 int bytes_this_transfer) 2585 { 2586 if (cvmx_usb_pipe_needs_split(usb, pipe)) { 2587 /* 2588 * ISOCHRONOUS OUT splits don't require a complete split stage. 2589 * Instead they use a sequence of begin OUT splits to transfer 2590 * the data 188 bytes at a time. Once the transfer is complete, 2591 * the pipe sleeps until the next schedule interval. 2592 */ 2593 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) { 2594 /* 2595 * If no space left or this wasn't a max size packet 2596 * then this transfer is complete. Otherwise start it 2597 * again to send the next 188 bytes 2598 */ 2599 if (!buffer_space_left || (bytes_this_transfer < 188)) { 2600 pipe->next_tx_frame += pipe->interval; 2601 cvmx_usb_complete(usb, pipe, transaction, 2602 CVMX_USB_STATUS_OK); 2603 } 2604 return; 2605 } 2606 if (transaction->stage == 2607 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) { 2608 /* 2609 * We are in the incoming data phase. Keep getting data 2610 * until we run out of space or get a small packet 2611 */ 2612 if ((buffer_space_left == 0) || 2613 (bytes_in_last_packet < pipe->max_packet)) { 2614 pipe->next_tx_frame += pipe->interval; 2615 cvmx_usb_complete(usb, pipe, transaction, 2616 CVMX_USB_STATUS_OK); 2617 } 2618 } else { 2619 transaction->stage = 2620 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE; 2621 } 2622 } else { 2623 pipe->next_tx_frame += pipe->interval; 2624 cvmx_usb_complete(usb, pipe, transaction, CVMX_USB_STATUS_OK); 2625 } 2626 } 2627 2628 /** 2629 * Poll a channel for status 2630 * 2631 * @usb: USB device 2632 * @channel: Channel to poll 2633 * 2634 * Returns: Zero on success 2635 */ 2636 static int cvmx_usb_poll_channel(struct octeon_hcd *usb, int channel) 2637 { 2638 struct usb_hcd *hcd = octeon_to_hcd(usb); 2639 struct device *dev = hcd->self.controller; 2640 union cvmx_usbcx_hcintx usbc_hcint; 2641 union cvmx_usbcx_hctsizx usbc_hctsiz; 2642 union cvmx_usbcx_hccharx usbc_hcchar; 2643 struct cvmx_usb_pipe *pipe; 2644 struct cvmx_usb_transaction *transaction; 2645 int bytes_this_transfer; 2646 int bytes_in_last_packet; 2647 int packets_processed; 2648 int buffer_space_left; 2649 2650 /* Read the interrupt status bits for the channel */ 2651 usbc_hcint.u32 = cvmx_usb_read_csr32(usb, 2652 CVMX_USBCX_HCINTX(channel, usb->index)); 2653 2654 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { 2655 usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, 2656 CVMX_USBCX_HCCHARX(channel, 2657 usb->index)); 2658 2659 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) { 2660 /* 2661 * There seems to be a bug in CN31XX which can cause 2662 * interrupt IN transfers to get stuck until we do a 2663 * write of HCCHARX without changing things 2664 */ 2665 cvmx_usb_write_csr32(usb, 2666 CVMX_USBCX_HCCHARX(channel, 2667 usb->index), 2668 usbc_hcchar.u32); 2669 return 0; 2670 } 2671 2672 /* 2673 * In non DMA mode the channels don't halt themselves. We need 2674 * to manually disable channels that are left running 2675 */ 2676 if (!usbc_hcint.s.chhltd) { 2677 if (usbc_hcchar.s.chena) { 2678 union cvmx_usbcx_hcintmskx hcintmsk; 2679 /* Disable all interrupts except CHHLTD */ 2680 hcintmsk.u32 = 0; 2681 hcintmsk.s.chhltdmsk = 1; 2682 cvmx_usb_write_csr32(usb, 2683 CVMX_USBCX_HCINTMSKX(channel, usb->index), 2684 hcintmsk.u32); 2685 usbc_hcchar.s.chdis = 1; 2686 cvmx_usb_write_csr32(usb, 2687 CVMX_USBCX_HCCHARX(channel, usb->index), 2688 usbc_hcchar.u32); 2689 return 0; 2690 } else if (usbc_hcint.s.xfercompl) { 2691 /* 2692 * Successful IN/OUT with transfer complete. 2693 * Channel halt isn't needed. 2694 */ 2695 } else { 2696 dev_err(dev, "USB%d: Channel %d interrupt without halt\n", 2697 usb->index, channel); 2698 return 0; 2699 } 2700 } 2701 } else { 2702 /* 2703 * There is are no interrupts that we need to process when the 2704 * channel is still running 2705 */ 2706 if (!usbc_hcint.s.chhltd) 2707 return 0; 2708 } 2709 2710 /* Disable the channel interrupts now that it is done */ 2711 cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0); 2712 usb->idle_hardware_channels |= (1 << channel); 2713 2714 /* Make sure this channel is tied to a valid pipe */ 2715 pipe = usb->pipe_for_channel[channel]; 2716 prefetch(pipe); 2717 if (!pipe) 2718 return 0; 2719 transaction = list_first_entry(&pipe->transactions, 2720 typeof(*transaction), 2721 node); 2722 prefetch(transaction); 2723 2724 /* 2725 * Disconnect this pipe from the HW channel. Later the schedule 2726 * function will figure out which pipe needs to go 2727 */ 2728 usb->pipe_for_channel[channel] = NULL; 2729 pipe->flags &= ~CVMX_USB_PIPE_FLAGS_SCHEDULED; 2730 2731 /* 2732 * Read the channel config info so we can figure out how much data 2733 * transferred 2734 */ 2735 usbc_hcchar.u32 = cvmx_usb_read_csr32(usb, 2736 CVMX_USBCX_HCCHARX(channel, usb->index)); 2737 usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb, 2738 CVMX_USBCX_HCTSIZX(channel, usb->index)); 2739 2740 /* 2741 * Calculating the number of bytes successfully transferred is dependent 2742 * on the transfer direction 2743 */ 2744 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt; 2745 if (usbc_hcchar.s.epdir) { 2746 /* 2747 * IN transactions are easy. For every byte received the 2748 * hardware decrements xfersize. All we need to do is subtract 2749 * the current value of xfersize from its starting value and we 2750 * know how many bytes were written to the buffer 2751 */ 2752 bytes_this_transfer = transaction->xfersize - 2753 usbc_hctsiz.s.xfersize; 2754 } else { 2755 /* 2756 * OUT transaction don't decrement xfersize. Instead pktcnt is 2757 * decremented on every successful packet send. The hardware 2758 * does this when it receives an ACK, or NYET. If it doesn't 2759 * receive one of these responses pktcnt doesn't change 2760 */ 2761 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps; 2762 /* 2763 * The last packet may not be a full transfer if we didn't have 2764 * enough data 2765 */ 2766 if (bytes_this_transfer > transaction->xfersize) 2767 bytes_this_transfer = transaction->xfersize; 2768 } 2769 /* Figure out how many bytes were in the last packet of the transfer */ 2770 if (packets_processed) 2771 bytes_in_last_packet = bytes_this_transfer - 2772 (packets_processed - 1) * usbc_hcchar.s.mps; 2773 else 2774 bytes_in_last_packet = bytes_this_transfer; 2775 2776 /* 2777 * As a special case, setup transactions output the setup header, not 2778 * the user's data. For this reason we don't count setup data as bytes 2779 * transferred 2780 */ 2781 if ((transaction->stage == CVMX_USB_STAGE_SETUP) || 2782 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE)) 2783 bytes_this_transfer = 0; 2784 2785 /* 2786 * Add the bytes transferred to the running total. It is important that 2787 * bytes_this_transfer doesn't count any data that needs to be 2788 * retransmitted 2789 */ 2790 transaction->actual_bytes += bytes_this_transfer; 2791 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS) 2792 buffer_space_left = transaction->iso_packets[0].length - 2793 transaction->actual_bytes; 2794 else 2795 buffer_space_left = transaction->buffer_length - 2796 transaction->actual_bytes; 2797 2798 /* 2799 * We need to remember the PID toggle state for the next transaction. 2800 * The hardware already updated it for the next transaction 2801 */ 2802 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0); 2803 2804 /* 2805 * For high speed bulk out, assume the next transaction will need to do 2806 * a ping before proceeding. If this isn't true the ACK processing below 2807 * will clear this flag 2808 */ 2809 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) && 2810 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) && 2811 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)) 2812 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; 2813 2814 if (WARN_ON_ONCE(bytes_this_transfer < 0)) { 2815 /* 2816 * In some rare cases the DMA engine seems to get stuck and 2817 * keeps substracting same byte count over and over again. In 2818 * such case we just need to fail every transaction. 2819 */ 2820 cvmx_usb_complete(usb, pipe, transaction, 2821 CVMX_USB_STATUS_ERROR); 2822 return 0; 2823 } 2824 2825 if (usbc_hcint.s.stall) { 2826 /* 2827 * STALL as a response means this transaction cannot be 2828 * completed because the device can't process transactions. Tell 2829 * the user. Any data that was transferred will be counted on 2830 * the actual bytes transferred 2831 */ 2832 pipe->pid_toggle = 0; 2833 cvmx_usb_complete(usb, pipe, transaction, 2834 CVMX_USB_STATUS_STALL); 2835 } else if (usbc_hcint.s.xacterr) { 2836 /* 2837 * XactErr as a response means the device signaled 2838 * something wrong with the transfer. For example, PID 2839 * toggle errors cause these. 2840 */ 2841 cvmx_usb_complete(usb, pipe, transaction, 2842 CVMX_USB_STATUS_XACTERR); 2843 } else if (usbc_hcint.s.bblerr) { 2844 /* Babble Error (BblErr) */ 2845 cvmx_usb_complete(usb, pipe, transaction, 2846 CVMX_USB_STATUS_BABBLEERR); 2847 } else if (usbc_hcint.s.datatglerr) { 2848 /* Data toggle error */ 2849 cvmx_usb_complete(usb, pipe, transaction, 2850 CVMX_USB_STATUS_DATATGLERR); 2851 } else if (usbc_hcint.s.nyet) { 2852 /* 2853 * NYET as a response is only allowed in three cases: as a 2854 * response to a ping, as a response to a split transaction, and 2855 * as a response to a bulk out. The ping case is handled by 2856 * hardware, so we only have splits and bulk out 2857 */ 2858 if (!cvmx_usb_pipe_needs_split(usb, pipe)) { 2859 transaction->retries = 0; 2860 /* 2861 * If there is more data to go then we need to try 2862 * again. Otherwise this transaction is complete 2863 */ 2864 if ((buffer_space_left == 0) || 2865 (bytes_in_last_packet < pipe->max_packet)) 2866 cvmx_usb_complete(usb, pipe, 2867 transaction, 2868 CVMX_USB_STATUS_OK); 2869 } else { 2870 /* 2871 * Split transactions retry the split complete 4 times 2872 * then rewind to the start split and do the entire 2873 * transactions again 2874 */ 2875 transaction->retries++; 2876 if ((transaction->retries & 0x3) == 0) { 2877 /* 2878 * Rewind to the beginning of the transaction by 2879 * anding off the split complete bit 2880 */ 2881 transaction->stage &= ~1; 2882 pipe->split_sc_frame = -1; 2883 } 2884 } 2885 } else if (usbc_hcint.s.ack) { 2886 transaction->retries = 0; 2887 /* 2888 * The ACK bit can only be checked after the other error bits. 2889 * This is because a multi packet transfer may succeed in a 2890 * number of packets and then get a different response on the 2891 * last packet. In this case both ACK and the last response bit 2892 * will be set. If none of the other response bits is set, then 2893 * the last packet must have been an ACK 2894 * 2895 * Since we got an ACK, we know we don't need to do a ping on 2896 * this pipe 2897 */ 2898 pipe->flags &= ~CVMX_USB_PIPE_FLAGS_NEED_PING; 2899 2900 switch (transaction->type) { 2901 case CVMX_USB_TRANSFER_CONTROL: 2902 cvmx_usb_transfer_control(usb, pipe, transaction, 2903 usbc_hcchar, 2904 buffer_space_left, 2905 bytes_in_last_packet); 2906 break; 2907 case CVMX_USB_TRANSFER_BULK: 2908 cvmx_usb_transfer_bulk(usb, pipe, transaction, 2909 usbc_hcint, buffer_space_left, 2910 bytes_in_last_packet); 2911 break; 2912 case CVMX_USB_TRANSFER_INTERRUPT: 2913 cvmx_usb_transfer_intr(usb, pipe, transaction, 2914 buffer_space_left, 2915 bytes_in_last_packet); 2916 break; 2917 case CVMX_USB_TRANSFER_ISOCHRONOUS: 2918 cvmx_usb_transfer_isoc(usb, pipe, transaction, 2919 buffer_space_left, 2920 bytes_in_last_packet, 2921 bytes_this_transfer); 2922 break; 2923 } 2924 } else if (usbc_hcint.s.nak) { 2925 /* 2926 * If this was a split then clear our split in progress marker. 2927 */ 2928 if (usb->active_split == transaction) 2929 usb->active_split = NULL; 2930 /* 2931 * NAK as a response means the device couldn't accept the 2932 * transaction, but it should be retried in the future. Rewind 2933 * to the beginning of the transaction by anding off the split 2934 * complete bit. Retry in the next interval 2935 */ 2936 transaction->retries = 0; 2937 transaction->stage &= ~1; 2938 pipe->next_tx_frame += pipe->interval; 2939 if (pipe->next_tx_frame < usb->frame_number) 2940 pipe->next_tx_frame = usb->frame_number + 2941 pipe->interval - 2942 (usb->frame_number - pipe->next_tx_frame) % 2943 pipe->interval; 2944 } else { 2945 struct cvmx_usb_port_status port; 2946 2947 port = cvmx_usb_get_status(usb); 2948 if (port.port_enabled) { 2949 /* We'll retry the exact same transaction again */ 2950 transaction->retries++; 2951 } else { 2952 /* 2953 * We get channel halted interrupts with no result bits 2954 * sets when the cable is unplugged 2955 */ 2956 cvmx_usb_complete(usb, pipe, transaction, 2957 CVMX_USB_STATUS_ERROR); 2958 } 2959 } 2960 return 0; 2961 } 2962 2963 static void octeon_usb_port_callback(struct octeon_hcd *usb) 2964 { 2965 spin_unlock(&usb->lock); 2966 usb_hcd_poll_rh_status(octeon_to_hcd(usb)); 2967 spin_lock(&usb->lock); 2968 } 2969 2970 /** 2971 * Poll the USB block for status and call all needed callback 2972 * handlers. This function is meant to be called in the interrupt 2973 * handler for the USB controller. It can also be called 2974 * periodically in a loop for non-interrupt based operation. 2975 * 2976 * @usb: USB device state populated by cvmx_usb_initialize(). 2977 * 2978 * Returns: 0 or a negative error code. 2979 */ 2980 static int cvmx_usb_poll(struct octeon_hcd *usb) 2981 { 2982 union cvmx_usbcx_hfnum usbc_hfnum; 2983 union cvmx_usbcx_gintsts usbc_gintsts; 2984 2985 prefetch_range(usb, sizeof(*usb)); 2986 2987 /* Update the frame counter */ 2988 usbc_hfnum.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index)); 2989 if ((usb->frame_number & 0x3fff) > usbc_hfnum.s.frnum) 2990 usb->frame_number += 0x4000; 2991 usb->frame_number &= ~0x3fffull; 2992 usb->frame_number |= usbc_hfnum.s.frnum; 2993 2994 /* Read the pending interrupts */ 2995 usbc_gintsts.u32 = cvmx_usb_read_csr32(usb, 2996 CVMX_USBCX_GINTSTS(usb->index)); 2997 2998 /* Clear the interrupts now that we know about them */ 2999 cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), 3000 usbc_gintsts.u32); 3001 3002 if (usbc_gintsts.s.rxflvl) { 3003 /* 3004 * RxFIFO Non-Empty (RxFLvl) 3005 * Indicates that there is at least one packet pending to be 3006 * read from the RxFIFO. 3007 * 3008 * In DMA mode this is handled by hardware 3009 */ 3010 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) 3011 cvmx_usb_poll_rx_fifo(usb); 3012 } 3013 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) { 3014 /* Fill the Tx FIFOs when not in DMA mode */ 3015 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) 3016 cvmx_usb_poll_tx_fifo(usb); 3017 } 3018 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) { 3019 union cvmx_usbcx_hprt usbc_hprt; 3020 /* 3021 * Disconnect Detected Interrupt (DisconnInt) 3022 * Asserted when a device disconnect is detected. 3023 * 3024 * Host Port Interrupt (PrtInt) 3025 * The core sets this bit to indicate a change in port status of 3026 * one of the O2P USB core ports in Host mode. The application 3027 * must read the Host Port Control and Status (HPRT) register to 3028 * determine the exact event that caused this interrupt. The 3029 * application must clear the appropriate status bit in the Host 3030 * Port Control and Status register to clear this bit. 3031 * 3032 * Call the user's port callback 3033 */ 3034 octeon_usb_port_callback(usb); 3035 /* Clear the port change bits */ 3036 usbc_hprt.u32 = 3037 cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index)); 3038 usbc_hprt.s.prtena = 0; 3039 cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), 3040 usbc_hprt.u32); 3041 } 3042 if (usbc_gintsts.s.hchint) { 3043 /* 3044 * Host Channels Interrupt (HChInt) 3045 * The core sets this bit to indicate that an interrupt is 3046 * pending on one of the channels of the core (in Host mode). 3047 * The application must read the Host All Channels Interrupt 3048 * (HAINT) register to determine the exact number of the channel 3049 * on which the interrupt occurred, and then read the 3050 * corresponding Host Channel-n Interrupt (HCINTn) register to 3051 * determine the exact cause of the interrupt. The application 3052 * must clear the appropriate status bit in the HCINTn register 3053 * to clear this bit. 3054 */ 3055 union cvmx_usbcx_haint usbc_haint; 3056 3057 usbc_haint.u32 = cvmx_usb_read_csr32(usb, 3058 CVMX_USBCX_HAINT(usb->index)); 3059 while (usbc_haint.u32) { 3060 int channel; 3061 3062 channel = __fls(usbc_haint.u32); 3063 cvmx_usb_poll_channel(usb, channel); 3064 usbc_haint.u32 ^= 1 << channel; 3065 } 3066 } 3067 3068 cvmx_usb_schedule(usb, usbc_gintsts.s.sof); 3069 3070 return 0; 3071 } 3072 3073 /* convert between an HCD pointer and the corresponding struct octeon_hcd */ 3074 static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd) 3075 { 3076 return (struct octeon_hcd *)(hcd->hcd_priv); 3077 } 3078 3079 static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd) 3080 { 3081 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3082 unsigned long flags; 3083 3084 spin_lock_irqsave(&usb->lock, flags); 3085 cvmx_usb_poll(usb); 3086 spin_unlock_irqrestore(&usb->lock, flags); 3087 return IRQ_HANDLED; 3088 } 3089 3090 static int octeon_usb_start(struct usb_hcd *hcd) 3091 { 3092 hcd->state = HC_STATE_RUNNING; 3093 return 0; 3094 } 3095 3096 static void octeon_usb_stop(struct usb_hcd *hcd) 3097 { 3098 hcd->state = HC_STATE_HALT; 3099 } 3100 3101 static int octeon_usb_get_frame_number(struct usb_hcd *hcd) 3102 { 3103 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3104 3105 return cvmx_usb_get_frame_number(usb); 3106 } 3107 3108 static int octeon_usb_urb_enqueue(struct usb_hcd *hcd, 3109 struct urb *urb, 3110 gfp_t mem_flags) 3111 { 3112 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3113 struct device *dev = hcd->self.controller; 3114 struct cvmx_usb_transaction *transaction = NULL; 3115 struct cvmx_usb_pipe *pipe; 3116 unsigned long flags; 3117 struct cvmx_usb_iso_packet *iso_packet; 3118 struct usb_host_endpoint *ep = urb->ep; 3119 int rc; 3120 3121 urb->status = 0; 3122 spin_lock_irqsave(&usb->lock, flags); 3123 3124 rc = usb_hcd_link_urb_to_ep(hcd, urb); 3125 if (rc) { 3126 spin_unlock_irqrestore(&usb->lock, flags); 3127 return rc; 3128 } 3129 3130 if (!ep->hcpriv) { 3131 enum cvmx_usb_transfer transfer_type; 3132 enum cvmx_usb_speed speed; 3133 int split_device = 0; 3134 int split_port = 0; 3135 3136 switch (usb_pipetype(urb->pipe)) { 3137 case PIPE_ISOCHRONOUS: 3138 transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS; 3139 break; 3140 case PIPE_INTERRUPT: 3141 transfer_type = CVMX_USB_TRANSFER_INTERRUPT; 3142 break; 3143 case PIPE_CONTROL: 3144 transfer_type = CVMX_USB_TRANSFER_CONTROL; 3145 break; 3146 default: 3147 transfer_type = CVMX_USB_TRANSFER_BULK; 3148 break; 3149 } 3150 switch (urb->dev->speed) { 3151 case USB_SPEED_LOW: 3152 speed = CVMX_USB_SPEED_LOW; 3153 break; 3154 case USB_SPEED_FULL: 3155 speed = CVMX_USB_SPEED_FULL; 3156 break; 3157 default: 3158 speed = CVMX_USB_SPEED_HIGH; 3159 break; 3160 } 3161 /* 3162 * For slow devices on high speed ports we need to find the hub 3163 * that does the speed translation so we know where to send the 3164 * split transactions. 3165 */ 3166 if (speed != CVMX_USB_SPEED_HIGH) { 3167 /* 3168 * Start at this device and work our way up the usb 3169 * tree. 3170 */ 3171 struct usb_device *dev = urb->dev; 3172 3173 while (dev->parent) { 3174 /* 3175 * If our parent is high speed then he'll 3176 * receive the splits. 3177 */ 3178 if (dev->parent->speed == USB_SPEED_HIGH) { 3179 split_device = dev->parent->devnum; 3180 split_port = dev->portnum; 3181 break; 3182 } 3183 /* 3184 * Move up the tree one level. If we make it all 3185 * the way up the tree, then the port must not 3186 * be in high speed mode and we don't need a 3187 * split. 3188 */ 3189 dev = dev->parent; 3190 } 3191 } 3192 pipe = cvmx_usb_open_pipe(usb, usb_pipedevice(urb->pipe), 3193 usb_pipeendpoint(urb->pipe), speed, 3194 le16_to_cpu(ep->desc.wMaxPacketSize) 3195 & 0x7ff, 3196 transfer_type, 3197 usb_pipein(urb->pipe) ? 3198 CVMX_USB_DIRECTION_IN : 3199 CVMX_USB_DIRECTION_OUT, 3200 urb->interval, 3201 (le16_to_cpu(ep->desc.wMaxPacketSize) 3202 >> 11) & 0x3, 3203 split_device, split_port); 3204 if (!pipe) { 3205 usb_hcd_unlink_urb_from_ep(hcd, urb); 3206 spin_unlock_irqrestore(&usb->lock, flags); 3207 dev_dbg(dev, "Failed to create pipe\n"); 3208 return -ENOMEM; 3209 } 3210 ep->hcpriv = pipe; 3211 } else { 3212 pipe = ep->hcpriv; 3213 } 3214 3215 switch (usb_pipetype(urb->pipe)) { 3216 case PIPE_ISOCHRONOUS: 3217 dev_dbg(dev, "Submit isochronous to %d.%d\n", 3218 usb_pipedevice(urb->pipe), 3219 usb_pipeendpoint(urb->pipe)); 3220 /* 3221 * Allocate a structure to use for our private list of 3222 * isochronous packets. 3223 */ 3224 iso_packet = kmalloc_objs(struct cvmx_usb_iso_packet, 3225 urb->number_of_packets, GFP_ATOMIC); 3226 if (iso_packet) { 3227 int i; 3228 /* Fill the list with the data from the URB */ 3229 for (i = 0; i < urb->number_of_packets; i++) { 3230 iso_packet[i].offset = 3231 urb->iso_frame_desc[i].offset; 3232 iso_packet[i].length = 3233 urb->iso_frame_desc[i].length; 3234 iso_packet[i].status = CVMX_USB_STATUS_ERROR; 3235 } 3236 /* 3237 * Store a pointer to the list in the URB setup_packet 3238 * field. We know this currently isn't being used and 3239 * this saves us a bunch of logic. 3240 */ 3241 urb->setup_packet = (char *)iso_packet; 3242 transaction = cvmx_usb_submit_isochronous(usb, 3243 pipe, urb); 3244 /* 3245 * If submit failed we need to free our private packet 3246 * list. 3247 */ 3248 if (!transaction) { 3249 urb->setup_packet = NULL; 3250 kfree(iso_packet); 3251 } 3252 } 3253 break; 3254 case PIPE_INTERRUPT: 3255 dev_dbg(dev, "Submit interrupt to %d.%d\n", 3256 usb_pipedevice(urb->pipe), 3257 usb_pipeendpoint(urb->pipe)); 3258 transaction = cvmx_usb_submit_interrupt(usb, pipe, urb); 3259 break; 3260 case PIPE_CONTROL: 3261 dev_dbg(dev, "Submit control to %d.%d\n", 3262 usb_pipedevice(urb->pipe), 3263 usb_pipeendpoint(urb->pipe)); 3264 transaction = cvmx_usb_submit_control(usb, pipe, urb); 3265 break; 3266 case PIPE_BULK: 3267 dev_dbg(dev, "Submit bulk to %d.%d\n", 3268 usb_pipedevice(urb->pipe), 3269 usb_pipeendpoint(urb->pipe)); 3270 transaction = cvmx_usb_submit_bulk(usb, pipe, urb); 3271 break; 3272 } 3273 if (!transaction) { 3274 usb_hcd_unlink_urb_from_ep(hcd, urb); 3275 spin_unlock_irqrestore(&usb->lock, flags); 3276 dev_dbg(dev, "Failed to submit\n"); 3277 return -ENOMEM; 3278 } 3279 urb->hcpriv = transaction; 3280 spin_unlock_irqrestore(&usb->lock, flags); 3281 return 0; 3282 } 3283 3284 static int octeon_usb_urb_dequeue(struct usb_hcd *hcd, 3285 struct urb *urb, 3286 int status) 3287 { 3288 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3289 unsigned long flags; 3290 int rc; 3291 3292 if (!urb->dev) 3293 return -EINVAL; 3294 3295 spin_lock_irqsave(&usb->lock, flags); 3296 3297 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 3298 if (rc) 3299 goto out; 3300 3301 urb->status = status; 3302 cvmx_usb_cancel(usb, urb->ep->hcpriv, urb->hcpriv); 3303 3304 out: 3305 spin_unlock_irqrestore(&usb->lock, flags); 3306 3307 return rc; 3308 } 3309 3310 static void octeon_usb_endpoint_disable(struct usb_hcd *hcd, 3311 struct usb_host_endpoint *ep) 3312 { 3313 struct device *dev = hcd->self.controller; 3314 3315 if (ep->hcpriv) { 3316 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3317 struct cvmx_usb_pipe *pipe = ep->hcpriv; 3318 unsigned long flags; 3319 3320 spin_lock_irqsave(&usb->lock, flags); 3321 cvmx_usb_cancel_all(usb, pipe); 3322 if (cvmx_usb_close_pipe(usb, pipe)) 3323 dev_dbg(dev, "Closing pipe %p failed\n", pipe); 3324 spin_unlock_irqrestore(&usb->lock, flags); 3325 ep->hcpriv = NULL; 3326 } 3327 } 3328 3329 static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf) 3330 { 3331 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3332 struct cvmx_usb_port_status port_status; 3333 unsigned long flags; 3334 3335 spin_lock_irqsave(&usb->lock, flags); 3336 port_status = cvmx_usb_get_status(usb); 3337 spin_unlock_irqrestore(&usb->lock, flags); 3338 buf[0] = port_status.connect_change << 1; 3339 3340 return buf[0] != 0; 3341 } 3342 3343 static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 3344 u16 wIndex, char *buf, u16 wLength) 3345 { 3346 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3347 struct device *dev = hcd->self.controller; 3348 struct cvmx_usb_port_status usb_port_status; 3349 int port_status; 3350 struct usb_hub_descriptor *desc; 3351 unsigned long flags; 3352 3353 switch (typeReq) { 3354 case ClearHubFeature: 3355 dev_dbg(dev, "ClearHubFeature\n"); 3356 switch (wValue) { 3357 case C_HUB_LOCAL_POWER: 3358 case C_HUB_OVER_CURRENT: 3359 /* Nothing required here */ 3360 break; 3361 default: 3362 return -EINVAL; 3363 } 3364 break; 3365 case ClearPortFeature: 3366 dev_dbg(dev, "ClearPortFeature\n"); 3367 if (wIndex != 1) { 3368 dev_dbg(dev, " INVALID\n"); 3369 return -EINVAL; 3370 } 3371 3372 switch (wValue) { 3373 case USB_PORT_FEAT_ENABLE: 3374 dev_dbg(dev, " ENABLE\n"); 3375 spin_lock_irqsave(&usb->lock, flags); 3376 cvmx_usb_disable(usb); 3377 spin_unlock_irqrestore(&usb->lock, flags); 3378 break; 3379 case USB_PORT_FEAT_SUSPEND: 3380 dev_dbg(dev, " SUSPEND\n"); 3381 /* Not supported on Octeon */ 3382 break; 3383 case USB_PORT_FEAT_POWER: 3384 dev_dbg(dev, " POWER\n"); 3385 /* Not supported on Octeon */ 3386 break; 3387 case USB_PORT_FEAT_INDICATOR: 3388 dev_dbg(dev, " INDICATOR\n"); 3389 /* Port indicator not supported */ 3390 break; 3391 case USB_PORT_FEAT_C_CONNECTION: 3392 dev_dbg(dev, " C_CONNECTION\n"); 3393 /* Clears drivers internal connect status change flag */ 3394 spin_lock_irqsave(&usb->lock, flags); 3395 usb->port_status = cvmx_usb_get_status(usb); 3396 spin_unlock_irqrestore(&usb->lock, flags); 3397 break; 3398 case USB_PORT_FEAT_C_RESET: 3399 dev_dbg(dev, " C_RESET\n"); 3400 /* 3401 * Clears the driver's internal Port Reset Change flag. 3402 */ 3403 spin_lock_irqsave(&usb->lock, flags); 3404 usb->port_status = cvmx_usb_get_status(usb); 3405 spin_unlock_irqrestore(&usb->lock, flags); 3406 break; 3407 case USB_PORT_FEAT_C_ENABLE: 3408 dev_dbg(dev, " C_ENABLE\n"); 3409 /* 3410 * Clears the driver's internal Port Enable/Disable 3411 * Change flag. 3412 */ 3413 spin_lock_irqsave(&usb->lock, flags); 3414 usb->port_status = cvmx_usb_get_status(usb); 3415 spin_unlock_irqrestore(&usb->lock, flags); 3416 break; 3417 case USB_PORT_FEAT_C_SUSPEND: 3418 dev_dbg(dev, " C_SUSPEND\n"); 3419 /* 3420 * Clears the driver's internal Port Suspend Change 3421 * flag, which is set when resume signaling on the host 3422 * port is complete. 3423 */ 3424 break; 3425 case USB_PORT_FEAT_C_OVER_CURRENT: 3426 dev_dbg(dev, " C_OVER_CURRENT\n"); 3427 /* Clears the driver's overcurrent Change flag */ 3428 spin_lock_irqsave(&usb->lock, flags); 3429 usb->port_status = cvmx_usb_get_status(usb); 3430 spin_unlock_irqrestore(&usb->lock, flags); 3431 break; 3432 default: 3433 dev_dbg(dev, " UNKNOWN\n"); 3434 return -EINVAL; 3435 } 3436 break; 3437 case GetHubDescriptor: 3438 dev_dbg(dev, "GetHubDescriptor\n"); 3439 desc = (struct usb_hub_descriptor *)buf; 3440 desc->bDescLength = 9; 3441 desc->bDescriptorType = 0x29; 3442 desc->bNbrPorts = 1; 3443 desc->wHubCharacteristics = cpu_to_le16(0x08); 3444 desc->bPwrOn2PwrGood = 1; 3445 desc->bHubContrCurrent = 0; 3446 desc->u.hs.DeviceRemovable[0] = 0; 3447 desc->u.hs.DeviceRemovable[1] = 0xff; 3448 break; 3449 case GetHubStatus: 3450 dev_dbg(dev, "GetHubStatus\n"); 3451 *(__le32 *)buf = 0; 3452 break; 3453 case GetPortStatus: 3454 dev_dbg(dev, "GetPortStatus\n"); 3455 if (wIndex != 1) { 3456 dev_dbg(dev, " INVALID\n"); 3457 return -EINVAL; 3458 } 3459 3460 spin_lock_irqsave(&usb->lock, flags); 3461 usb_port_status = cvmx_usb_get_status(usb); 3462 spin_unlock_irqrestore(&usb->lock, flags); 3463 port_status = 0; 3464 3465 if (usb_port_status.connect_change) { 3466 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); 3467 dev_dbg(dev, " C_CONNECTION\n"); 3468 } 3469 3470 if (usb_port_status.port_enabled) { 3471 port_status |= (1 << USB_PORT_FEAT_C_ENABLE); 3472 dev_dbg(dev, " C_ENABLE\n"); 3473 } 3474 3475 if (usb_port_status.connected) { 3476 port_status |= (1 << USB_PORT_FEAT_CONNECTION); 3477 dev_dbg(dev, " CONNECTION\n"); 3478 } 3479 3480 if (usb_port_status.port_enabled) { 3481 port_status |= (1 << USB_PORT_FEAT_ENABLE); 3482 dev_dbg(dev, " ENABLE\n"); 3483 } 3484 3485 if (usb_port_status.port_over_current) { 3486 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); 3487 dev_dbg(dev, " OVER_CURRENT\n"); 3488 } 3489 3490 if (usb_port_status.port_powered) { 3491 port_status |= (1 << USB_PORT_FEAT_POWER); 3492 dev_dbg(dev, " POWER\n"); 3493 } 3494 3495 if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) { 3496 port_status |= USB_PORT_STAT_HIGH_SPEED; 3497 dev_dbg(dev, " HIGHSPEED\n"); 3498 } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) { 3499 port_status |= (1 << USB_PORT_FEAT_LOWSPEED); 3500 dev_dbg(dev, " LOWSPEED\n"); 3501 } 3502 3503 *((__le32 *)buf) = cpu_to_le32(port_status); 3504 break; 3505 case SetHubFeature: 3506 dev_dbg(dev, "SetHubFeature\n"); 3507 /* No HUB features supported */ 3508 break; 3509 case SetPortFeature: 3510 dev_dbg(dev, "SetPortFeature\n"); 3511 if (wIndex != 1) { 3512 dev_dbg(dev, " INVALID\n"); 3513 return -EINVAL; 3514 } 3515 3516 switch (wValue) { 3517 case USB_PORT_FEAT_SUSPEND: 3518 dev_dbg(dev, " SUSPEND\n"); 3519 return -EINVAL; 3520 case USB_PORT_FEAT_POWER: 3521 dev_dbg(dev, " POWER\n"); 3522 /* 3523 * Program the port power bit to drive VBUS on the USB. 3524 */ 3525 spin_lock_irqsave(&usb->lock, flags); 3526 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), 3527 cvmx_usbcx_hprt, prtpwr, 1); 3528 spin_unlock_irqrestore(&usb->lock, flags); 3529 return 0; 3530 case USB_PORT_FEAT_RESET: 3531 dev_dbg(dev, " RESET\n"); 3532 spin_lock_irqsave(&usb->lock, flags); 3533 cvmx_usb_reset_port(usb); 3534 spin_unlock_irqrestore(&usb->lock, flags); 3535 return 0; 3536 case USB_PORT_FEAT_INDICATOR: 3537 dev_dbg(dev, " INDICATOR\n"); 3538 /* Not supported */ 3539 break; 3540 default: 3541 dev_dbg(dev, " UNKNOWN\n"); 3542 return -EINVAL; 3543 } 3544 break; 3545 default: 3546 dev_dbg(dev, "Unknown root hub request\n"); 3547 return -EINVAL; 3548 } 3549 return 0; 3550 } 3551 3552 static const struct hc_driver octeon_hc_driver = { 3553 .description = "Octeon USB", 3554 .product_desc = "Octeon Host Controller", 3555 .hcd_priv_size = sizeof(struct octeon_hcd), 3556 .irq = octeon_usb_irq, 3557 .flags = HCD_MEMORY | HCD_DMA | HCD_USB2, 3558 .start = octeon_usb_start, 3559 .stop = octeon_usb_stop, 3560 .urb_enqueue = octeon_usb_urb_enqueue, 3561 .urb_dequeue = octeon_usb_urb_dequeue, 3562 .endpoint_disable = octeon_usb_endpoint_disable, 3563 .get_frame_number = octeon_usb_get_frame_number, 3564 .hub_status_data = octeon_usb_hub_status_data, 3565 .hub_control = octeon_usb_hub_control, 3566 .map_urb_for_dma = octeon_map_urb_for_dma, 3567 .unmap_urb_for_dma = octeon_unmap_urb_for_dma, 3568 }; 3569 3570 static int octeon_usb_probe(struct platform_device *pdev) 3571 { 3572 int status; 3573 int initialize_flags; 3574 int usb_num; 3575 struct resource *res_mem; 3576 struct device_node *usbn_node; 3577 int irq = platform_get_irq(pdev, 0); 3578 struct device *dev = &pdev->dev; 3579 struct octeon_hcd *usb; 3580 struct usb_hcd *hcd; 3581 u32 clock_rate = 48000000; 3582 bool is_crystal_clock = false; 3583 const char *clock_type; 3584 int i; 3585 3586 if (!dev->of_node) { 3587 dev_err(dev, "Error: empty of_node\n"); 3588 return -ENXIO; 3589 } 3590 usbn_node = dev->of_node->parent; 3591 3592 i = of_property_read_u32(usbn_node, 3593 "clock-frequency", &clock_rate); 3594 if (i) 3595 i = of_property_read_u32(usbn_node, 3596 "refclk-frequency", &clock_rate); 3597 if (i) { 3598 dev_err(dev, "No USBN \"clock-frequency\"\n"); 3599 return -ENXIO; 3600 } 3601 switch (clock_rate) { 3602 case 12000000: 3603 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ; 3604 break; 3605 case 24000000: 3606 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ; 3607 break; 3608 case 48000000: 3609 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ; 3610 break; 3611 default: 3612 dev_err(dev, "Illegal USBN \"clock-frequency\" %u\n", 3613 clock_rate); 3614 return -ENXIO; 3615 } 3616 3617 i = of_property_read_string(usbn_node, 3618 "cavium,refclk-type", &clock_type); 3619 if (i) 3620 i = of_property_read_string(usbn_node, 3621 "refclk-type", &clock_type); 3622 3623 if (!i && strcmp("crystal", clock_type) == 0) 3624 is_crystal_clock = true; 3625 3626 if (is_crystal_clock) 3627 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI; 3628 else 3629 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND; 3630 3631 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3632 if (!res_mem) { 3633 dev_err(dev, "found no memory resource\n"); 3634 return -ENXIO; 3635 } 3636 usb_num = (res_mem->start >> 44) & 1; 3637 3638 if (irq < 0) { 3639 /* Defective device tree, but we know how to fix it. */ 3640 irq_hw_number_t hwirq = usb_num ? (1 << 6) + 17 : 56; 3641 3642 irq = irq_create_mapping(NULL, hwirq); 3643 } 3644 3645 /* 3646 * Set the DMA mask to 64bits so we get buffers already translated for 3647 * DMA. 3648 */ 3649 i = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); 3650 if (i) 3651 return i; 3652 3653 /* 3654 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the 3655 * IOB priority registers. Under heavy network load USB 3656 * hardware can be starved by the IOB causing a crash. Give 3657 * it a priority boost if it has been waiting more than 400 3658 * cycles to avoid this situation. 3659 * 3660 * Testing indicates that a cnt_val of 8192 is not sufficient, 3661 * but no failures are seen with 4096. We choose a value of 3662 * 400 to give a safety factor of 10. 3663 */ 3664 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { 3665 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt; 3666 3667 pri_cnt.u64 = 0; 3668 pri_cnt.s.cnt_enb = 1; 3669 pri_cnt.s.cnt_val = 400; 3670 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64); 3671 } 3672 3673 hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev)); 3674 if (!hcd) { 3675 dev_dbg(dev, "Failed to allocate memory for HCD\n"); 3676 return -1; 3677 } 3678 hcd->uses_new_polling = 1; 3679 usb = (struct octeon_hcd *)hcd->hcd_priv; 3680 3681 spin_lock_init(&usb->lock); 3682 hrtimer_setup(&usb->sof_timer, octeon_usb_sof_timer, CLOCK_MONOTONIC, 3683 HRTIMER_MODE_REL); 3684 3685 usb->init_flags = initialize_flags; 3686 3687 /* Initialize the USB state structure */ 3688 usb->index = usb_num; 3689 INIT_LIST_HEAD(&usb->idle_pipes); 3690 for (i = 0; i < ARRAY_SIZE(usb->active_pipes); i++) 3691 INIT_LIST_HEAD(&usb->active_pipes[i]); 3692 3693 /* Due to an errata, CN31XX doesn't support DMA */ 3694 if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { 3695 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA; 3696 /* Only use one channel with non DMA */ 3697 usb->idle_hardware_channels = 0x1; 3698 } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { 3699 /* CN5XXX have an errata with channel 3 */ 3700 usb->idle_hardware_channels = 0xf7; 3701 } else { 3702 usb->idle_hardware_channels = 0xff; 3703 } 3704 3705 status = cvmx_usb_initialize(dev, usb); 3706 if (status) { 3707 dev_dbg(dev, "USB initialization failed with %d\n", status); 3708 usb_put_hcd(hcd); 3709 return -1; 3710 } 3711 3712 status = usb_add_hcd(hcd, irq, 0); 3713 if (status) { 3714 dev_dbg(dev, "USB add HCD failed with %d\n", status); 3715 usb_put_hcd(hcd); 3716 return -1; 3717 } 3718 device_wakeup_enable(hcd->self.controller); 3719 3720 dev_info(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq); 3721 3722 return 0; 3723 } 3724 3725 static void octeon_usb_remove(struct platform_device *pdev) 3726 { 3727 int status; 3728 struct device *dev = &pdev->dev; 3729 struct usb_hcd *hcd = dev_get_drvdata(dev); 3730 struct octeon_hcd *usb = hcd_to_octeon(hcd); 3731 unsigned long flags; 3732 3733 usb_remove_hcd(hcd); 3734 hrtimer_cancel(&usb->sof_timer); 3735 spin_lock_irqsave(&usb->lock, flags); 3736 status = cvmx_usb_shutdown(usb); 3737 spin_unlock_irqrestore(&usb->lock, flags); 3738 if (status) 3739 dev_dbg(dev, "USB shutdown failed with %d\n", status); 3740 3741 usb_put_hcd(hcd); 3742 } 3743 3744 static const struct of_device_id octeon_usb_match[] = { 3745 { 3746 .compatible = "cavium,octeon-5750-usbc", 3747 }, 3748 {}, 3749 }; 3750 MODULE_DEVICE_TABLE(of, octeon_usb_match); 3751 3752 static struct platform_driver octeon_usb_driver = { 3753 .driver = { 3754 .name = "octeon-hcd", 3755 .of_match_table = octeon_usb_match, 3756 }, 3757 .probe = octeon_usb_probe, 3758 .remove = octeon_usb_remove, 3759 }; 3760 3761 static int __init octeon_usb_driver_init(void) 3762 { 3763 if (usb_disabled()) 3764 return 0; 3765 3766 return platform_driver_register(&octeon_usb_driver); 3767 } 3768 module_init(octeon_usb_driver_init); 3769 3770 static void __exit octeon_usb_driver_exit(void) 3771 { 3772 if (usb_disabled()) 3773 return; 3774 3775 platform_driver_unregister(&octeon_usb_driver); 3776 } 3777 module_exit(octeon_usb_driver_exit); 3778 3779 MODULE_LICENSE("GPL"); 3780 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>"); 3781 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver."); 3782