1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7 *******************************************************************************/
8
9 #ifndef __STMMAC_H__
10 #define __STMMAC_H__
11
12 #define STMMAC_RESOURCE_NAME "stmmaceth"
13
14 #include <linux/clk.h>
15 #include <linux/hrtimer.h>
16 #include <linux/if_vlan.h>
17 #include <linux/stmmac.h>
18 #include <linux/phylink.h>
19 #include <linux/pci.h>
20 #include "common.h"
21 #include <linux/ptp_clock_kernel.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/reset.h>
24 #include <net/page_pool/types.h>
25 #include <net/xdp.h>
26 #include <uapi/linux/bpf.h>
27
28 struct stmmac_pcs;
29
30 struct stmmac_resources {
31 void __iomem *addr;
32 u8 mac[ETH_ALEN];
33 int wol_irq;
34 int irq;
35 int sfty_irq;
36 int sfty_ce_irq;
37 int sfty_ue_irq;
38 int rx_irq[MTL_MAX_RX_QUEUES];
39 int tx_irq[MTL_MAX_TX_QUEUES];
40 };
41
42 enum stmmac_txbuf_type {
43 STMMAC_TXBUF_T_SKB,
44 STMMAC_TXBUF_T_XDP_TX,
45 STMMAC_TXBUF_T_XDP_NDO,
46 STMMAC_TXBUF_T_XSK_TX,
47 };
48
49 struct stmmac_tx_info {
50 dma_addr_t buf;
51 bool map_as_page;
52 unsigned len;
53 bool last_segment;
54 bool is_jumbo;
55 enum stmmac_txbuf_type buf_type;
56 struct xsk_tx_metadata_compl xsk_meta;
57 };
58
59 #define STMMAC_TBS_AVAIL BIT(0)
60 #define STMMAC_TBS_EN BIT(1)
61
62 /* Frequently used values are kept adjacent for cache effect */
63 struct stmmac_tx_queue {
64 u32 tx_count_frames;
65 int tbs;
66 struct hrtimer txtimer;
67 u32 queue_index;
68 struct stmmac_priv *priv_data;
69 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
70 struct dma_edesc *dma_entx;
71 struct dma_desc *dma_tx;
72 union {
73 struct sk_buff **tx_skbuff;
74 struct xdp_frame **xdpf;
75 };
76 struct stmmac_tx_info *tx_skbuff_dma;
77 struct xsk_buff_pool *xsk_pool;
78 u32 xsk_frames_done;
79 unsigned int cur_tx;
80 unsigned int dirty_tx;
81 dma_addr_t dma_tx_phy;
82 dma_addr_t tx_tail_addr;
83 u32 mss;
84 };
85
86 struct stmmac_rx_buffer {
87 union {
88 struct {
89 struct page *page;
90 dma_addr_t addr;
91 __u32 page_offset;
92 };
93 struct xdp_buff *xdp;
94 };
95 struct page *sec_page;
96 dma_addr_t sec_addr;
97 };
98
99 struct stmmac_xdp_buff {
100 struct xdp_buff xdp;
101 struct stmmac_priv *priv;
102 struct dma_desc *desc;
103 struct dma_desc *ndesc;
104 };
105
106 struct stmmac_metadata_request {
107 struct stmmac_priv *priv;
108 struct dma_desc *tx_desc;
109 bool *set_ic;
110 struct dma_edesc *edesc;
111 int tbs;
112 };
113
114 struct stmmac_xsk_tx_complete {
115 struct stmmac_priv *priv;
116 struct dma_desc *desc;
117 };
118
119 struct stmmac_rx_queue {
120 u32 rx_count_frames;
121 u32 queue_index;
122 struct xdp_rxq_info xdp_rxq;
123 struct xsk_buff_pool *xsk_pool;
124 struct page_pool *page_pool;
125 struct stmmac_rx_buffer *buf_pool;
126 struct stmmac_priv *priv_data;
127 struct dma_extended_desc *dma_erx;
128 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
129 unsigned int cur_rx;
130 unsigned int dirty_rx;
131 unsigned int buf_alloc_num;
132 unsigned int napi_skb_frag_size;
133 dma_addr_t dma_rx_phy;
134 u32 rx_tail_addr;
135 unsigned int state_saved;
136 struct {
137 struct sk_buff *skb;
138 unsigned int len;
139 unsigned int error;
140 } state;
141 };
142
143 struct stmmac_channel {
144 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
145 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
146 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
147 struct stmmac_priv *priv_data;
148 spinlock_t lock;
149 u32 index;
150 };
151
152 struct stmmac_fpe_cfg {
153 struct ethtool_mmsv mmsv;
154 const struct stmmac_fpe_reg *reg;
155 u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */
156 };
157
158 struct stmmac_tc_entry {
159 bool in_use;
160 bool in_hw;
161 bool is_last;
162 bool is_frag;
163 void *frag_ptr;
164 unsigned int table_pos;
165 u32 handle;
166 u32 prio;
167 struct {
168 u32 match_data;
169 u32 match_en;
170 u8 af:1;
171 u8 rf:1;
172 u8 im:1;
173 u8 nc:1;
174 u8 res1:4;
175 u8 frame_offset;
176 u8 ok_index;
177 u8 dma_ch_no;
178 u32 res2;
179 } __packed val;
180 };
181
182 #define STMMAC_PPS_MAX 4
183 struct stmmac_pps_cfg {
184 bool available;
185 struct timespec64 start;
186 struct timespec64 period;
187 };
188
189 struct stmmac_rss {
190 int enable;
191 u8 key[STMMAC_RSS_HASH_KEY_SIZE];
192 u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
193 };
194
195 #define STMMAC_FLOW_ACTION_DROP BIT(0)
196 struct stmmac_flow_entry {
197 unsigned long cookie;
198 unsigned long action;
199 u8 ip_proto;
200 int in_use;
201 int idx;
202 int is_l4;
203 };
204
205 /* Rx Frame Steering */
206 enum stmmac_rfs_type {
207 STMMAC_RFS_T_VLAN,
208 STMMAC_RFS_T_LLDP,
209 STMMAC_RFS_T_1588,
210 STMMAC_RFS_T_MAX,
211 };
212
213 struct stmmac_rfs_entry {
214 unsigned long cookie;
215 u16 etype;
216 int in_use;
217 int type;
218 int tc;
219 };
220
221 struct stmmac_dma_conf {
222 unsigned int dma_buf_sz;
223
224 /* RX Queue */
225 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
226 unsigned int dma_rx_size;
227
228 /* TX Queue */
229 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
230 unsigned int dma_tx_size;
231 };
232
233 #define EST_GCL 1024
234 struct stmmac_est {
235 int enable;
236 u32 btr_reserve[2];
237 u32 btr_offset[2];
238 u32 btr[2];
239 u32 ctr[2];
240 u32 ter;
241 u32 gcl_unaligned[EST_GCL];
242 u32 gcl[EST_GCL];
243 u32 gcl_size;
244 u32 max_sdu[MTL_MAX_TX_QUEUES];
245 };
246
247 struct stmmac_priv {
248 /* Frequently used values are kept adjacent for cache effect */
249 u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
250 u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
251 u32 rx_coal_frames[MTL_MAX_RX_QUEUES];
252
253 int hwts_tx_en;
254 bool tx_path_in_lpi_mode;
255 bool tso;
256 bool sph_active;
257 bool sph_capable;
258 u32 sarc_type;
259 u32 rx_riwt[MTL_MAX_RX_QUEUES];
260 int hwts_rx_en;
261 bool tsfupdt_coarse;
262
263 void __iomem *ioaddr;
264 struct net_device *dev;
265 struct device *device;
266 struct mac_device_info *hw;
267 int (*hwif_quirks)(struct stmmac_priv *priv);
268 struct mutex lock;
269
270 struct stmmac_dma_conf dma_conf;
271
272 /* Generic channel for NAPI */
273 struct stmmac_channel channel[STMMAC_CH_MAX];
274
275 unsigned int pause_time;
276 struct mii_bus *mii;
277
278 struct stmmac_pcs *integrated_pcs;
279
280 struct phylink_config phylink_config;
281 struct phylink *phylink;
282
283 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
284 struct stmmac_safety_stats sstats;
285 struct plat_stmmacenet_data *plat;
286 /* Protect est parameters */
287 struct mutex est_lock;
288 struct stmmac_est *est;
289 struct dma_features dma_cap;
290 struct stmmac_counters mmc;
291 int hw_cap_support;
292 int synopsys_id;
293 u32 msg_enable;
294 /* Our MAC Wake-on-Lan options */
295 int wolopts;
296 int wol_irq;
297 u32 gmii_address_bus_config;
298 struct timer_list eee_ctrl_timer;
299 u32 tx_lpi_timer;
300 bool tx_lpi_clk_stop;
301 bool eee_enabled;
302 bool eee_active;
303 bool eee_sw_timer_en;
304 bool legacy_serdes_is_powered;
305 unsigned int mode;
306 unsigned int chain_mode;
307 int extend_desc;
308 struct kernel_hwtstamp_config tstamp_config;
309 struct ptp_clock *ptp_clock;
310 struct ptp_clock_info ptp_clock_ops;
311 unsigned int default_addend;
312 u32 sub_second_inc;
313 u32 systime_flags;
314 u32 adv_ts;
315 int use_riwt;
316 int irq_wake;
317 rwlock_t ptp_lock;
318 /* Protects auxiliary snapshot registers from concurrent access. */
319 struct mutex aux_ts_lock;
320 wait_queue_head_t tstamp_busy_wait;
321
322 void __iomem *mmcaddr;
323 void __iomem *ptpaddr;
324 void __iomem *estaddr;
325 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
326 unsigned int num_double_vlans;
327 int sfty_irq;
328 int sfty_ce_irq;
329 int sfty_ue_irq;
330 int rx_irq[MTL_MAX_RX_QUEUES];
331 int tx_irq[MTL_MAX_TX_QUEUES];
332 /*irq name */
333 char int_name_mac[IFNAMSIZ + 9];
334 char int_name_wol[IFNAMSIZ + 9];
335 char int_name_lpi[IFNAMSIZ + 9];
336 char int_name_sfty[IFNAMSIZ + 10];
337 char int_name_sfty_ce[IFNAMSIZ + 10];
338 char int_name_sfty_ue[IFNAMSIZ + 10];
339 char int_name_rx_irq[MTL_MAX_RX_QUEUES][IFNAMSIZ + 14];
340 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
341
342 #ifdef CONFIG_DEBUG_FS
343 struct dentry *dbgfs_dir;
344 #endif
345
346 unsigned long state;
347 struct workqueue_struct *wq;
348 struct work_struct service_task;
349
350 /* Frame Preemption feature (FPE) */
351 struct stmmac_fpe_cfg fpe_cfg;
352
353 /* TC Handling */
354 unsigned int tc_entries_max;
355 unsigned int tc_off_max;
356 struct stmmac_tc_entry *tc_entries;
357 unsigned int flow_entries_max;
358 struct stmmac_flow_entry *flow_entries;
359 unsigned int rfs_entries_max[STMMAC_RFS_T_MAX];
360 unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX];
361 unsigned int rfs_entries_total;
362 struct stmmac_rfs_entry *rfs_entries;
363
364 /* Pulse Per Second output */
365 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
366
367 /* Receive Side Scaling */
368 struct stmmac_rss rss;
369
370 /* XDP BPF Program */
371 unsigned long *af_xdp_zc_qps;
372 struct bpf_prog *xdp_prog;
373
374 struct devlink *devlink;
375 };
376
377 enum stmmac_state {
378 STMMAC_DOWN,
379 STMMAC_RESET_REQUESTED,
380 STMMAC_RESETING,
381 STMMAC_SERVICE_SCHED,
382 };
383
384 extern const struct dev_pm_ops stmmac_simple_pm_ops;
385
386 int stmmac_mdio_unregister(struct net_device *ndev);
387 int stmmac_mdio_register(struct net_device *ndev);
388 int stmmac_mdio_reset(struct mii_bus *mii);
389 void stmmac_mdio_lock(struct stmmac_priv *priv);
390 void stmmac_mdio_unlock(struct stmmac_priv *priv);
391 int stmmac_pcs_setup(struct net_device *ndev);
392 void stmmac_pcs_clean(struct net_device *ndev);
393 void stmmac_set_ethtool_ops(struct net_device *netdev);
394
395 void stmmac_ptp_register(struct stmmac_priv *priv);
396 void stmmac_ptp_unregister(struct stmmac_priv *priv);
397 int stmmac_xdp_open(struct net_device *dev);
398 void stmmac_xdp_release(struct net_device *dev);
399 int stmmac_get_phy_intf_sel(phy_interface_t interface);
400 int stmmac_resume(struct device *dev);
401 int stmmac_suspend(struct device *dev);
402 void stmmac_dvr_remove(struct device *dev);
403 int stmmac_dvr_probe(struct device *device,
404 struct plat_stmmacenet_data *plat_dat,
405 struct stmmac_resources *res);
406 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
407 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
408 int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
409 phy_interface_t interface, int speed);
410
411 struct plat_stmmacenet_data *stmmac_plat_dat_alloc(struct device *dev);
412
stmmac_xdp_is_enabled(struct stmmac_priv * priv)413 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
414 {
415 return !!priv->xdp_prog;
416 }
417
418 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
419 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
420 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
421 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
422 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
423 struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
424 ktime_t current_time,
425 u64 cycle_time);
426
427 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
428 void stmmac_selftest_run(struct net_device *dev,
429 struct ethtool_test *etest, u64 *buf);
430 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
431 int stmmac_selftest_get_count(struct stmmac_priv *priv);
432 #else
stmmac_selftest_run(struct net_device * dev,struct ethtool_test * etest,u64 * buf)433 static inline void stmmac_selftest_run(struct net_device *dev,
434 struct ethtool_test *etest, u64 *buf)
435 {
436 /* Not enabled */
437 }
stmmac_selftest_get_strings(struct stmmac_priv * priv,u8 * data)438 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
439 u8 *data)
440 {
441 /* Not enabled */
442 }
stmmac_selftest_get_count(struct stmmac_priv * priv)443 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
444 {
445 return -EOPNOTSUPP;
446 }
447 #endif /* CONFIG_STMMAC_SELFTESTS */
448
449 #endif /* __STMMAC_H__ */
450