1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) "bcmasp_intf: " fmt
3
4 #include <asm/byteorder.h>
5 #include <linux/brcmphy.h>
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/etherdevice.h>
9 #include <linux/netdevice.h>
10 #include <linux/of_net.h>
11 #include <linux/of_mdio.h>
12 #include <linux/phy.h>
13 #include <linux/phy_fixed.h>
14 #include <linux/ptp_classify.h>
15 #include <linux/platform_device.h>
16 #include <net/ip.h>
17 #include <net/ipv6.h>
18 #include <net/page_pool/helpers.h>
19
20 #include "bcmasp.h"
21 #include "bcmasp_intf_defs.h"
22
incr_ring(int index,int ring_count)23 static int incr_ring(int index, int ring_count)
24 {
25 index++;
26 if (index == ring_count)
27 return 0;
28
29 return index;
30 }
31
32 /* Points to last byte of descriptor */
incr_last_byte(dma_addr_t addr,dma_addr_t beg,int ring_count)33 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg,
34 int ring_count)
35 {
36 dma_addr_t end = beg + (ring_count * DESC_SIZE);
37
38 addr += DESC_SIZE;
39 if (addr > end)
40 return beg + DESC_SIZE - 1;
41
42 return addr;
43 }
44
45 /* Points to first byte of descriptor */
incr_first_byte(dma_addr_t addr,dma_addr_t beg,int ring_count)46 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg,
47 int ring_count)
48 {
49 dma_addr_t end = beg + (ring_count * DESC_SIZE);
50
51 addr += DESC_SIZE;
52 if (addr >= end)
53 return beg;
54
55 return addr;
56 }
57
bcmasp_enable_tx(struct bcmasp_intf * intf,int en)58 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en)
59 {
60 if (en) {
61 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE);
62 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN |
63 TX_EPKT_C_CFG_MISC_PT |
64 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)),
65 TX_EPKT_C_CFG_MISC);
66 } else {
67 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE);
68 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC);
69 }
70 }
71
bcmasp_enable_rx(struct bcmasp_intf * intf,int en)72 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en)
73 {
74 if (en)
75 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN,
76 RX_EDPKT_CFG_ENABLE);
77 else
78 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE);
79 }
80
bcmasp_set_rx_mode(struct net_device * dev)81 static void bcmasp_set_rx_mode(struct net_device *dev)
82 {
83 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
84 struct bcmasp_intf *intf = netdev_priv(dev);
85 struct netdev_hw_addr *ha;
86 int ret;
87
88 spin_lock_bh(&intf->parent->mda_lock);
89
90 bcmasp_disable_all_filters(intf);
91
92 if (dev->flags & IFF_PROMISC)
93 goto set_promisc;
94
95 bcmasp_set_promisc(intf, 0);
96
97 bcmasp_set_broad(intf, 1);
98
99 bcmasp_set_oaddr(intf, dev->dev_addr, 1);
100
101 if (dev->flags & IFF_ALLMULTI) {
102 bcmasp_set_allmulti(intf, 1);
103 } else {
104 bcmasp_set_allmulti(intf, 0);
105
106 netdev_for_each_mc_addr(ha, dev) {
107 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask);
108 if (ret) {
109 intf->mib.mc_filters_full_cnt++;
110 goto set_promisc;
111 }
112 }
113 }
114
115 netdev_for_each_uc_addr(ha, dev) {
116 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask);
117 if (ret) {
118 intf->mib.uc_filters_full_cnt++;
119 goto set_promisc;
120 }
121 }
122
123 spin_unlock_bh(&intf->parent->mda_lock);
124 return;
125
126 set_promisc:
127 bcmasp_set_promisc(intf, 1);
128 intf->mib.promisc_filters_cnt++;
129
130 /* disable all filters used by this port */
131 bcmasp_disable_all_filters(intf);
132
133 spin_unlock_bh(&intf->parent->mda_lock);
134 }
135
bcmasp_clean_txcb(struct bcmasp_intf * intf,int index)136 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index)
137 {
138 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index];
139
140 txcb->skb = NULL;
141 dma_unmap_addr_set(txcb, dma_addr, 0);
142 dma_unmap_len_set(txcb, dma_len, 0);
143 txcb->last = false;
144 }
145
tx_spb_ring_full(struct bcmasp_intf * intf,int cnt)146 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt)
147 {
148 int next_index, i;
149
150 /* Check if we have enough room for cnt descriptors */
151 next_index = intf->tx_spb_index;
152 for (i = 0; i < cnt; i++) {
153 next_index = incr_ring(next_index, DESC_RING_COUNT);
154 if (next_index == intf->tx_spb_clean_index)
155 return 1;
156 }
157
158 return 0;
159 }
160
bcmasp_csum_offload(struct net_device * dev,struct sk_buff * skb,bool * csum_hw)161 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev,
162 struct sk_buff *skb,
163 bool *csum_hw)
164 {
165 struct bcmasp_intf *intf = netdev_priv(dev);
166 u32 header = 0, header2 = 0, epkt = 0;
167 struct bcmasp_pkt_offload *offload;
168 unsigned int header_cnt = 0;
169 u8 ip_proto;
170 int ret;
171
172 if (skb->ip_summed != CHECKSUM_PARTIAL)
173 return skb;
174
175 ret = skb_cow_head(skb, sizeof(*offload));
176 if (ret < 0) {
177 intf->mib.tx_realloc_offload_failed++;
178 goto help;
179 }
180
181 switch (skb->protocol) {
182 case htons(ETH_P_IP):
183 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf);
184 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff);
185 epkt |= PKT_OFFLOAD_EPKT_IP(0);
186 ip_proto = ip_hdr(skb)->protocol;
187 header_cnt += 2;
188 break;
189 case htons(ETH_P_IPV6):
190 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf);
191 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff);
192 epkt |= PKT_OFFLOAD_EPKT_IP(1);
193 ip_proto = ipv6_hdr(skb)->nexthdr;
194 header_cnt += 2;
195 break;
196 default:
197 goto help;
198 }
199
200 switch (ip_proto) {
201 case IPPROTO_TCP:
202 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb));
203 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L4;
204 header_cnt++;
205 break;
206 case IPPROTO_UDP:
207 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN);
208 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L4;
209 header_cnt++;
210 break;
211 default:
212 goto help;
213 }
214
215 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload));
216
217 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) |
218 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN);
219 epkt |= PKT_OFFLOAD_EPKT_OP;
220
221 offload->nop = htonl(PKT_OFFLOAD_NOP);
222 offload->header = htonl(header);
223 offload->header2 = htonl(header2);
224 offload->epkt = htonl(epkt);
225 offload->end = htonl(PKT_OFFLOAD_END_OP);
226 *csum_hw = true;
227
228 return skb;
229
230 help:
231 skb_checksum_help(skb);
232
233 return skb;
234 }
235
bcmasp_xmit(struct sk_buff * skb,struct net_device * dev)236 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev)
237 {
238 struct bcmasp_intf *intf = netdev_priv(dev);
239 unsigned int total_bytes, size;
240 int spb_index, nr_frags, i, j;
241 struct bcmasp_tx_cb *txcb;
242 dma_addr_t mapping, valid;
243 struct bcmasp_desc *desc;
244 bool csum_hw = false;
245 struct device *kdev;
246 skb_frag_t *frag;
247
248 kdev = &intf->parent->pdev->dev;
249
250 nr_frags = skb_shinfo(skb)->nr_frags;
251
252 if (tx_spb_ring_full(intf, nr_frags + 1)) {
253 netif_stop_queue(dev);
254 if (net_ratelimit())
255 netdev_err(dev, "Tx Ring Full!\n");
256 return NETDEV_TX_BUSY;
257 }
258
259 /* Save skb len before adding csum offload header */
260 total_bytes = skb->len;
261 skb = bcmasp_csum_offload(dev, skb, &csum_hw);
262 if (!skb)
263 return NETDEV_TX_OK;
264
265 spb_index = intf->tx_spb_index;
266 valid = intf->tx_spb_dma_valid;
267 for (i = 0; i <= nr_frags; i++) {
268 if (!i) {
269 size = skb_headlen(skb);
270 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) {
271 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN))
272 return NETDEV_TX_OK;
273 size = skb->len;
274 }
275 mapping = dma_map_single(kdev, skb->data, size,
276 DMA_TO_DEVICE);
277 } else {
278 frag = &skb_shinfo(skb)->frags[i - 1];
279 size = skb_frag_size(frag);
280 mapping = skb_frag_dma_map(kdev, frag, 0, size,
281 DMA_TO_DEVICE);
282 }
283
284 if (dma_mapping_error(kdev, mapping)) {
285 intf->mib.tx_dma_failed++;
286 spb_index = intf->tx_spb_index;
287 for (j = 0; j < i; j++) {
288 bcmasp_clean_txcb(intf, spb_index);
289 spb_index = incr_ring(spb_index,
290 DESC_RING_COUNT);
291 }
292 /* Rewind so we do not have a hole */
293 spb_index = intf->tx_spb_index;
294 dev_kfree_skb(skb);
295 return NETDEV_TX_OK;
296 }
297
298 txcb = &intf->tx_cbs[spb_index];
299 desc = &intf->tx_spb_cpu[spb_index];
300 memset(desc, 0, sizeof(*desc));
301 txcb->skb = skb;
302 txcb->bytes_sent = total_bytes;
303 dma_unmap_addr_set(txcb, dma_addr, mapping);
304 dma_unmap_len_set(txcb, dma_len, size);
305 txcb->last = false;
306 if (!i) {
307 desc->flags |= DESC_SOF;
308 if (csum_hw)
309 desc->flags |= DESC_EPKT_CMD;
310 }
311
312 if (i == nr_frags) {
313 desc->flags |= DESC_EOF;
314 txcb->last = true;
315 }
316
317 desc->buf = mapping;
318 desc->size = size;
319 desc->flags |= DESC_INT_EN;
320
321 netif_dbg(intf, tx_queued, dev,
322 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n",
323 __func__, &mapping, desc->size, desc->flags,
324 spb_index);
325
326 spb_index = incr_ring(spb_index, DESC_RING_COUNT);
327 valid = incr_last_byte(valid, intf->tx_spb_dma_addr,
328 DESC_RING_COUNT);
329 }
330
331 /* Ensure all descriptors have been written to DRAM for the
332 * hardware to see up-to-date contents.
333 */
334 wmb();
335
336 intf->tx_spb_index = spb_index;
337 intf->tx_spb_dma_valid = valid;
338
339 skb_tx_timestamp(skb);
340
341 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID);
342
343 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1))
344 netif_stop_queue(dev);
345
346 return NETDEV_TX_OK;
347 }
348
umac_reset_and_init(struct bcmasp_intf * intf,const unsigned char * addr)349 static void umac_reset_and_init(struct bcmasp_intf *intf,
350 const unsigned char *addr)
351 {
352 struct phy_device *phydev = intf->ndev->phydev;
353 u32 mac0, mac1;
354
355 umac_wl(intf, 0x0, UMC_CMD);
356 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD);
357 usleep_range(10, 100);
358 /* We hold the umac in reset and bring it out of
359 * reset when phy link is up.
360 */
361
362 umac_wl(intf, 0x800, UMC_FRM_LEN);
363 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL);
364 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ);
365
366 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
367 addr[3];
368 mac1 = (addr[4] << 8) | addr[5];
369
370 umac_wl(intf, mac0, UMC_MAC0);
371 umac_wl(intf, mac1, UMC_MAC1);
372
373 /* Reset shadow values since we reset the umac */
374 intf->old_duplex = -1;
375 intf->old_link = -1;
376 intf->old_pause = -1;
377 phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER);
378 }
379
umac_enable_set(struct bcmasp_intf * intf,u32 mask,unsigned int enable)380 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask,
381 unsigned int enable)
382 {
383 u32 reg;
384
385 reg = umac_rl(intf, UMC_CMD);
386 if (reg & UMC_CMD_SW_RESET)
387 return;
388 if (enable)
389 reg |= mask;
390 else
391 reg &= ~mask;
392 umac_wl(intf, reg, UMC_CMD);
393
394 /* UniMAC stops on a packet boundary, wait for a full-sized packet
395 * to be processed (1 msec).
396 */
397 if (enable == 0)
398 usleep_range(1000, 2000);
399 }
400
bcmasp_tx_reclaim(struct bcmasp_intf * intf)401 static int bcmasp_tx_reclaim(struct bcmasp_intf *intf)
402 {
403 struct bcmasp_intf_stats64 *stats = &intf->stats64;
404 struct device *kdev = &intf->parent->pdev->dev;
405 unsigned long read, released = 0;
406 struct bcmasp_tx_cb *txcb;
407 struct bcmasp_desc *desc;
408 dma_addr_t mapping;
409
410 read = tx_spb_dma_rq(intf, TX_SPB_DMA_READ);
411 while (intf->tx_spb_dma_read != read) {
412 txcb = &intf->tx_cbs[intf->tx_spb_clean_index];
413 mapping = dma_unmap_addr(txcb, dma_addr);
414
415 dma_unmap_single(kdev, mapping,
416 dma_unmap_len(txcb, dma_len),
417 DMA_TO_DEVICE);
418
419 if (txcb->last) {
420 dev_consume_skb_any(txcb->skb);
421
422 u64_stats_update_begin(&stats->syncp);
423 u64_stats_inc(&stats->tx_packets);
424 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent);
425 u64_stats_update_end(&stats->syncp);
426 }
427
428 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index];
429
430 netif_dbg(intf, tx_done, intf->ndev,
431 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n",
432 __func__, &mapping, desc->size, desc->flags,
433 intf->tx_spb_clean_index);
434
435 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index);
436 released++;
437
438 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index,
439 DESC_RING_COUNT);
440 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read,
441 intf->tx_spb_dma_addr,
442 DESC_RING_COUNT);
443 }
444
445 return released;
446 }
447
bcmasp_tx_poll(struct napi_struct * napi,int budget)448 static int bcmasp_tx_poll(struct napi_struct *napi, int budget)
449 {
450 struct bcmasp_intf *intf =
451 container_of(napi, struct bcmasp_intf, tx_napi);
452 int released = 0;
453
454 released = bcmasp_tx_reclaim(intf);
455
456 napi_complete(&intf->tx_napi);
457
458 bcmasp_enable_tx_irq(intf, 1);
459
460 if (released)
461 netif_wake_queue(intf->ndev);
462
463 return 0;
464 }
465
bcmasp_rx_poll(struct napi_struct * napi,int budget)466 static int bcmasp_rx_poll(struct napi_struct *napi, int budget)
467 {
468 struct bcmasp_intf *intf =
469 container_of(napi, struct bcmasp_intf, rx_napi);
470 struct bcmasp_intf_stats64 *stats = &intf->stats64;
471 struct device *kdev = &intf->parent->pdev->dev;
472 unsigned long processed = 0;
473 struct bcmasp_desc *desc;
474 struct sk_buff *skb;
475 dma_addr_t valid;
476 struct page *page;
477 void *data;
478 u64 flags;
479 u32 len;
480
481 /* Hardware advances DMA_VALID as it writes each descriptor
482 * (RBUF_4K streaming mode); software chases with rx_edpkt_dma_read.
483 */
484 valid = rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID) + 1;
485 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE)
486 valid = intf->rx_edpkt_dma_addr;
487
488 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) {
489 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index];
490
491 /* Ensure the descriptor has been fully written to DRAM by
492 * the hardware before the CPU reads it.
493 */
494 rmb();
495
496 /* Locate the packet data inside the streaming ring buffer. */
497 data = intf->rx_ring_cpu +
498 (DESC_ADDR(desc->buf) - intf->rx_ring_dma);
499
500 flags = DESC_FLAGS(desc->buf);
501 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) {
502 if (net_ratelimit()) {
503 netif_err(intf, rx_status, intf->ndev,
504 "flags=0x%llx\n", flags);
505 }
506
507 u64_stats_update_begin(&stats->syncp);
508 if (flags & DESC_CRC_ERR)
509 u64_stats_inc(&stats->rx_crc_errs);
510 if (flags & DESC_RX_SYM_ERR)
511 u64_stats_inc(&stats->rx_sym_errs);
512 u64_stats_update_end(&stats->syncp);
513
514 goto next;
515 }
516
517 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size,
518 DMA_FROM_DEVICE);
519
520 len = desc->size;
521
522 /* Allocate a page pool page as the SKB data area so the
523 * kernel can recycle it efficiently after the packet is
524 * consumed, avoiding repeated slab allocations.
525 */
526 page = page_pool_dev_alloc_pages(intf->rx_page_pool);
527 if (!page) {
528 u64_stats_update_begin(&stats->syncp);
529 u64_stats_inc(&stats->rx_dropped);
530 u64_stats_update_end(&stats->syncp);
531 intf->mib.alloc_rx_skb_failed++;
532 goto next;
533 }
534
535 skb = napi_build_skb(page_address(page), PAGE_SIZE);
536 if (!skb) {
537 u64_stats_update_begin(&stats->syncp);
538 u64_stats_inc(&stats->rx_dropped);
539 u64_stats_update_end(&stats->syncp);
540 intf->mib.alloc_rx_skb_failed++;
541 page_pool_recycle_direct(intf->rx_page_pool, page);
542 goto next;
543 }
544
545 /* Reserve headroom then copy the full descriptor payload
546 * (hardware prepends a 2-byte alignment pad at the start).
547 */
548 skb_reserve(skb, NET_SKB_PAD);
549 skb_put(skb, len);
550 memcpy(skb->data, data, len);
551 skb_mark_for_recycle(skb);
552
553 /* Skip the 2-byte hardware alignment pad. */
554 skb_pull(skb, 2);
555 len -= 2;
556 if (likely(intf->crc_fwd)) {
557 skb_trim(skb, len - ETH_FCS_LEN);
558 len -= ETH_FCS_LEN;
559 }
560
561 if ((intf->ndev->features & NETIF_F_RXCSUM) &&
562 (desc->buf & DESC_CHKSUM))
563 skb->ip_summed = CHECKSUM_UNNECESSARY;
564
565 skb->protocol = eth_type_trans(skb, intf->ndev);
566
567 napi_gro_receive(napi, skb);
568
569 u64_stats_update_begin(&stats->syncp);
570 u64_stats_inc(&stats->rx_packets);
571 u64_stats_add(&stats->rx_bytes, len);
572 u64_stats_update_end(&stats->syncp);
573
574 next:
575 /* Return this portion of the streaming ring buffer to HW. */
576 rx_edpkt_cfg_wq(intf, (DESC_ADDR(desc->buf) + desc->size),
577 RX_EDPKT_RING_BUFFER_READ);
578
579 processed++;
580 intf->rx_edpkt_dma_read =
581 incr_first_byte(intf->rx_edpkt_dma_read,
582 intf->rx_edpkt_dma_addr,
583 DESC_RING_COUNT);
584 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index,
585 DESC_RING_COUNT);
586 }
587
588 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_read, RX_EDPKT_DMA_READ);
589
590 if (processed < budget && napi_complete_done(&intf->rx_napi, processed))
591 bcmasp_enable_rx_irq(intf, 1);
592
593 return processed;
594 }
595
bcmasp_adj_link(struct net_device * dev)596 static void bcmasp_adj_link(struct net_device *dev)
597 {
598 struct bcmasp_intf *intf = netdev_priv(dev);
599 struct phy_device *phydev = dev->phydev;
600 u32 cmd_bits = 0, reg;
601 int changed = 0;
602
603 if (intf->old_link != phydev->link) {
604 changed = 1;
605 intf->old_link = phydev->link;
606 }
607
608 if (intf->old_duplex != phydev->duplex) {
609 changed = 1;
610 intf->old_duplex = phydev->duplex;
611 }
612
613 switch (phydev->speed) {
614 case SPEED_2500:
615 cmd_bits = UMC_CMD_SPEED_2500;
616 break;
617 case SPEED_1000:
618 cmd_bits = UMC_CMD_SPEED_1000;
619 break;
620 case SPEED_100:
621 cmd_bits = UMC_CMD_SPEED_100;
622 break;
623 case SPEED_10:
624 cmd_bits = UMC_CMD_SPEED_10;
625 break;
626 default:
627 break;
628 }
629 cmd_bits <<= UMC_CMD_SPEED_SHIFT;
630
631 if (phydev->duplex == DUPLEX_HALF)
632 cmd_bits |= UMC_CMD_HD_EN;
633
634 if (intf->old_pause != phydev->pause) {
635 changed = 1;
636 intf->old_pause = phydev->pause;
637 }
638
639 if (!phydev->pause)
640 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE;
641
642 if (!changed)
643 return;
644
645 if (phydev->link) {
646 reg = umac_rl(intf, UMC_CMD);
647 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) |
648 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE |
649 UMC_CMD_TX_PAUSE_IGNORE);
650 reg |= cmd_bits;
651 if (reg & UMC_CMD_SW_RESET) {
652 reg &= ~UMC_CMD_SW_RESET;
653 umac_wl(intf, reg, UMC_CMD);
654 udelay(2);
655 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC;
656 }
657 umac_wl(intf, reg, UMC_CMD);
658
659 umac_wl(intf, phydev->eee_cfg.tx_lpi_timer, UMC_EEE_LPI_TIMER);
660 reg = umac_rl(intf, UMC_EEE_CTRL);
661 if (phydev->enable_tx_lpi)
662 reg |= EEE_EN;
663 else
664 reg &= ~EEE_EN;
665 umac_wl(intf, reg, UMC_EEE_CTRL);
666 }
667
668 reg = rgmii_rl(intf, RGMII_OOB_CNTRL);
669 if (phydev->link)
670 reg |= RGMII_LINK;
671 else
672 reg &= ~RGMII_LINK;
673 rgmii_wl(intf, reg, RGMII_OOB_CNTRL);
674
675 if (changed)
676 phy_print_status(phydev);
677 }
678
679 static struct page_pool *
bcmasp_rx_page_pool_create(struct bcmasp_intf * intf)680 bcmasp_rx_page_pool_create(struct bcmasp_intf *intf)
681 {
682 struct page_pool_params pp_params = {
683 .order = 0,
684 .flags = 0,
685 .pool_size = NUM_4K_BUFFERS,
686 .nid = NUMA_NO_NODE,
687 .dev = &intf->parent->pdev->dev,
688 .napi = &intf->rx_napi,
689 .netdev = intf->ndev,
690 .offset = 0,
691 .max_len = PAGE_SIZE,
692 };
693
694 return page_pool_create(&pp_params);
695 }
696
bcmasp_alloc_rx_buffers(struct bcmasp_intf * intf)697 static int bcmasp_alloc_rx_buffers(struct bcmasp_intf *intf)
698 {
699 struct device *kdev = &intf->parent->pdev->dev;
700 struct page *buffer_pg;
701 int ret;
702
703 /* Contiguous streaming ring that hardware writes packet data into. */
704 intf->rx_buf_order = get_order(RING_BUFFER_SIZE);
705 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order);
706 if (!buffer_pg)
707 return -ENOMEM;
708
709 intf->rx_ring_cpu = page_to_virt(buffer_pg);
710 intf->rx_ring_dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE,
711 DMA_FROM_DEVICE);
712 if (dma_mapping_error(kdev, intf->rx_ring_dma)) {
713 ret = -ENOMEM;
714 goto free_ring_pages;
715 }
716
717 /* Page pool for SKB data areas (copy targets, not DMA buffers). */
718 intf->rx_page_pool = bcmasp_rx_page_pool_create(intf);
719 if (IS_ERR(intf->rx_page_pool)) {
720 ret = PTR_ERR(intf->rx_page_pool);
721 intf->rx_page_pool = NULL;
722 goto free_ring_dma;
723 }
724
725 return 0;
726
727 free_ring_dma:
728 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE,
729 DMA_FROM_DEVICE);
730 free_ring_pages:
731 __free_pages(buffer_pg, intf->rx_buf_order);
732 return ret;
733 }
734
bcmasp_reclaim_rx_buffers(struct bcmasp_intf * intf)735 static void bcmasp_reclaim_rx_buffers(struct bcmasp_intf *intf)
736 {
737 struct device *kdev = &intf->parent->pdev->dev;
738
739 page_pool_destroy(intf->rx_page_pool);
740 intf->rx_page_pool = NULL;
741 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE,
742 DMA_FROM_DEVICE);
743 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order);
744 }
745
bcmasp_alloc_buffers(struct bcmasp_intf * intf)746 static int bcmasp_alloc_buffers(struct bcmasp_intf *intf)
747 {
748 struct device *kdev = &intf->parent->pdev->dev;
749 int ret;
750
751 /* Alloc RX */
752 ret = bcmasp_alloc_rx_buffers(intf);
753 if (ret)
754 return ret;
755
756 intf->rx_edpkt_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE,
757 &intf->rx_edpkt_dma_addr,
758 GFP_KERNEL);
759 if (!intf->rx_edpkt_cpu)
760 goto free_rx_buffers;
761
762 /* Alloc TX */
763 intf->tx_spb_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE,
764 &intf->tx_spb_dma_addr, GFP_KERNEL);
765 if (!intf->tx_spb_cpu)
766 goto free_rx_edpkt_dma;
767
768 intf->tx_cbs = kzalloc_objs(struct bcmasp_tx_cb, DESC_RING_COUNT);
769 if (!intf->tx_cbs)
770 goto free_tx_spb_dma;
771
772 return 0;
773
774 free_tx_spb_dma:
775 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu,
776 intf->tx_spb_dma_addr);
777 free_rx_edpkt_dma:
778 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu,
779 intf->rx_edpkt_dma_addr);
780 free_rx_buffers:
781 bcmasp_reclaim_rx_buffers(intf);
782
783 return -ENOMEM;
784 }
785
bcmasp_reclaim_free_buffers(struct bcmasp_intf * intf)786 static void bcmasp_reclaim_free_buffers(struct bcmasp_intf *intf)
787 {
788 struct device *kdev = &intf->parent->pdev->dev;
789
790 /* RX buffers */
791 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu,
792 intf->rx_edpkt_dma_addr);
793 bcmasp_reclaim_rx_buffers(intf);
794
795 /* TX buffers */
796 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu,
797 intf->tx_spb_dma_addr);
798 kfree(intf->tx_cbs);
799 }
800
bcmasp_init_rx(struct bcmasp_intf * intf)801 static void bcmasp_init_rx(struct bcmasp_intf *intf)
802 {
803 /* Restart from index 0 */
804 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1;
805 intf->rx_edpkt_dma_valid = intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1);
806 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr;
807 intf->rx_edpkt_index = 0;
808
809 /* Make sure channels are disabled */
810 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE);
811
812 /* Streaming data ring: hardware writes raw packet bytes here. */
813 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ);
814 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE);
815 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE);
816 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid,
817 RX_EDPKT_RING_BUFFER_END);
818 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid,
819 RX_EDPKT_RING_BUFFER_VALID);
820
821 /* EDPKT descriptor ring: hardware fills descriptors pointing into
822 * the streaming ring buffer above (RBUF_4K mode).
823 */
824 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K <<
825 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) |
826 (RX_EDPKT_CFG_CFG0_64_ALN <<
827 RX_EDPKT_CFG_CFG0_BALN_SHIFT) |
828 (RX_EDPKT_CFG_CFG0_EFRM_STUF),
829 RX_EDPKT_CFG_CFG0);
830 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE);
831 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ);
832 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE);
833 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_END);
834 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_VALID);
835
836 umac2fb_wl(intf, UMAC2FB_CFG_DEFAULT_EN | ((intf->channel + 11) <<
837 UMAC2FB_CFG_CHID_SHIFT) | (0xd << UMAC2FB_CFG_OK_SEND_SHIFT),
838 UMAC2FB_CFG);
839 }
840
841
bcmasp_init_tx(struct bcmasp_intf * intf)842 static void bcmasp_init_tx(struct bcmasp_intf *intf)
843 {
844 /* Restart from index 0 */
845 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1;
846 intf->tx_spb_dma_read = intf->tx_spb_dma_addr;
847 intf->tx_spb_index = 0;
848 intf->tx_spb_clean_index = 0;
849 memset(intf->tx_cbs, 0, sizeof(struct bcmasp_tx_cb) * DESC_RING_COUNT);
850
851 /* Make sure channels are disabled */
852 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE);
853 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC);
854
855 /* Tx SPB */
856 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT),
857 TX_SPB_CTRL_XF_CTRL2);
858
859 if (intf->parent->tx_chan_offset)
860 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR);
861 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT);
862
863 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ);
864 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE);
865 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END);
866 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID);
867 }
868
bcmasp_ephy_enable_set(struct bcmasp_intf * intf,bool enable)869 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable)
870 {
871 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN |
872 RGMII_EPHY_CFG_IDDQ_GLOBAL;
873 u32 reg;
874
875 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL);
876 if (enable) {
877 reg &= ~RGMII_EPHY_CK25_DIS;
878 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL);
879 mdelay(1);
880
881 reg &= ~mask;
882 reg |= RGMII_EPHY_RESET;
883 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL);
884 mdelay(1);
885
886 reg &= ~RGMII_EPHY_RESET;
887 } else {
888 reg |= mask | RGMII_EPHY_RESET;
889 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL);
890 mdelay(1);
891 reg |= RGMII_EPHY_CK25_DIS;
892 }
893 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL);
894 mdelay(1);
895
896 /* Set or clear the LED control override to avoid lighting up LEDs
897 * while the EPHY is powered off and drawing unnecessary current.
898 */
899 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL);
900 if (enable)
901 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD;
902 else
903 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD;
904 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL);
905 }
906
bcmasp_rgmii_mode_en_set(struct bcmasp_intf * intf,bool enable)907 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable)
908 {
909 u32 reg;
910
911 reg = rgmii_rl(intf, RGMII_OOB_CNTRL);
912 reg &= ~RGMII_OOB_DIS;
913 if (enable)
914 reg |= RGMII_MODE_EN;
915 else
916 reg &= ~RGMII_MODE_EN;
917 rgmii_wl(intf, reg, RGMII_OOB_CNTRL);
918 }
919
bcmasp_phy_hw_unprepare(struct bcmasp_intf * intf)920 static void bcmasp_phy_hw_unprepare(struct bcmasp_intf *intf)
921 {
922 if (intf->internal_phy)
923 bcmasp_ephy_enable_set(intf, false);
924 else
925 bcmasp_rgmii_mode_en_set(intf, false);
926 }
927
bcmasp_netif_deinit(struct net_device * dev,bool stop_phy)928 static void bcmasp_netif_deinit(struct net_device *dev, bool stop_phy)
929 {
930 struct bcmasp_intf *intf = netdev_priv(dev);
931 u32 reg, timeout = 1000;
932
933 napi_disable(&intf->tx_napi);
934
935 bcmasp_enable_tx(intf, 0);
936
937 /* Flush any TX packets in the pipe */
938 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL);
939 do {
940 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS);
941 if (!(reg & TX_SPB_DMA_FIFO_FLUSH))
942 break;
943 usleep_range(1000, 2000);
944 } while (timeout-- > 0);
945 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL);
946
947 bcmasp_tx_reclaim(intf);
948
949 umac_enable_set(intf, UMC_CMD_TX_EN, 0);
950
951 if (stop_phy)
952 phy_stop(dev->phydev);
953
954 umac_enable_set(intf, UMC_CMD_RX_EN, 0);
955
956 bcmasp_flush_rx_port(intf);
957 usleep_range(1000, 2000);
958 bcmasp_enable_rx(intf, 0);
959
960 napi_disable(&intf->rx_napi);
961
962 /* Disable interrupts */
963 bcmasp_enable_tx_irq(intf, 0);
964 bcmasp_enable_rx_irq(intf, 0);
965 bcmasp_enable_phy_irq(intf, 0);
966
967 netif_napi_del(&intf->tx_napi);
968 netif_napi_del(&intf->rx_napi);
969 }
970
bcmasp_stop(struct net_device * dev)971 static int bcmasp_stop(struct net_device *dev)
972 {
973 struct bcmasp_intf *intf = netdev_priv(dev);
974
975 netif_dbg(intf, ifdown, dev, "bcmasp stop\n");
976
977 /* Stop tx from updating HW */
978 netif_tx_disable(dev);
979
980 bcmasp_netif_deinit(dev, true);
981
982 bcmasp_reclaim_free_buffers(intf);
983
984 phy_disconnect(dev->phydev);
985
986 bcmasp_phy_hw_unprepare(intf);
987
988 /* Disable the interface clocks */
989 bcmasp_core_clock_set_intf(intf, false);
990
991 clk_disable_unprepare(intf->parent->clk);
992
993 return 0;
994 }
995
bcmasp_phy_hw_prepare(struct bcmasp_intf * intf)996 static void bcmasp_phy_hw_prepare(struct bcmasp_intf *intf)
997 {
998 u32 reg, id_mode_dis = 0;
999
1000 if (intf->internal_phy)
1001 bcmasp_ephy_enable_set(intf, true);
1002 else
1003 bcmasp_rgmii_mode_en_set(intf, true);
1004
1005 reg = rgmii_rl(intf, RGMII_PORT_CNTRL);
1006 reg &= ~RGMII_PORT_MODE_MASK;
1007
1008 switch (intf->phy_interface) {
1009 case PHY_INTERFACE_MODE_RGMII:
1010 /* RGMII_NO_ID: TXC transitions at the same time as TXD
1011 * (requires PCB or receiver-side delay)
1012 * RGMII: Add 2ns delay on TXC (90 degree shift)
1013 *
1014 * ID is implicitly disabled for 100Mbps (RG)MII operation.
1015 */
1016 id_mode_dis = RGMII_ID_MODE_DIS;
1017 fallthrough;
1018 case PHY_INTERFACE_MODE_RGMII_TXID:
1019 reg |= RGMII_PORT_MODE_EXT_GPHY;
1020 break;
1021 case PHY_INTERFACE_MODE_MII:
1022 reg |= RGMII_PORT_MODE_EXT_EPHY;
1023 break;
1024 default:
1025 break;
1026 }
1027
1028 if (intf->internal_phy)
1029 reg |= RGMII_PORT_MODE_EPHY;
1030
1031 rgmii_wl(intf, reg, RGMII_PORT_CNTRL);
1032
1033 reg = rgmii_rl(intf, RGMII_OOB_CNTRL);
1034 reg &= ~RGMII_ID_MODE_DIS;
1035 reg |= id_mode_dis;
1036 rgmii_wl(intf, reg, RGMII_OOB_CNTRL);
1037 }
1038
bcmasp_phy_iface_for_connect(phy_interface_t mode)1039 static phy_interface_t bcmasp_phy_iface_for_connect(phy_interface_t mode)
1040 {
1041 /* This is an ugly quirk but we have not been correctly
1042 * interpreting the phy_interface values and we have done that
1043 * across different drivers, so at least we are consistent in
1044 * our mistakes.
1045 *
1046 * When the Generic PHY driver is in use either the PHY has
1047 * been strapped or programmed correctly by the boot loader so
1048 * we should stick to our incorrect interpretation since we
1049 * have validated it.
1050 *
1051 * Now when a dedicated PHY driver is in use, we need to
1052 * reverse the meaning of the phy_interface_mode values to
1053 * something that the PHY driver will interpret and act on such
1054 * that we have two mistakes canceling themselves so to speak.
1055 * We only do this for the two modes that GENET driver
1056 * officially supports on Broadcom STB chips:
1057 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID.
1058 * Other modes are not *officially* supported with the boot
1059 * loader and the scripted environment generating Device Tree
1060 * blobs for those platforms.
1061 *
1062 * Note that internal PHY and fixed-link configurations are not
1063 * affected because they use different phy_interface_t values
1064 * or the Generic PHY driver.
1065 */
1066 switch (mode) {
1067 case PHY_INTERFACE_MODE_RGMII:
1068 return PHY_INTERFACE_MODE_RGMII_ID;
1069 case PHY_INTERFACE_MODE_RGMII_TXID:
1070 return PHY_INTERFACE_MODE_RGMII_RXID;
1071 default:
1072 return mode;
1073 }
1074 }
1075
bcmasp_phy_attach(struct bcmasp_intf * intf)1076 static int bcmasp_phy_attach(struct bcmasp_intf *intf)
1077 {
1078 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE |
1079 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1080 PHY_BRCM_IDDQ_SUSPEND;
1081 struct phy_device *phydev;
1082 phy_interface_t phy_iface;
1083
1084 phy_iface = bcmasp_phy_iface_for_connect(intf->phy_interface);
1085 phydev = of_phy_connect(intf->ndev, intf->phy_dn,
1086 bcmasp_adj_link, phy_flags,
1087 phy_iface);
1088 if (!phydev) {
1089 netdev_err(intf->ndev, "could not attach to PHY\n");
1090 return -ENODEV;
1091 }
1092 if (intf->internal_phy)
1093 intf->ndev->phydev->irq = PHY_MAC_INTERRUPT;
1094
1095 phydev->mac_managed_pm = true;
1096
1097 return 0;
1098 }
1099
bcmasp_netif_init(struct net_device * dev)1100 static void bcmasp_netif_init(struct net_device *dev)
1101 {
1102 struct bcmasp_intf *intf = netdev_priv(dev);
1103
1104 bcmasp_init_tx(intf);
1105 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll);
1106 bcmasp_enable_tx(intf, 1);
1107
1108 bcmasp_init_rx(intf);
1109 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll);
1110 bcmasp_enable_rx(intf, 1);
1111
1112 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD);
1113
1114 bcmasp_set_rx_mode(dev);
1115 napi_enable(&intf->tx_napi);
1116 napi_enable(&intf->rx_napi);
1117
1118 bcmasp_enable_rx_irq(intf, 1);
1119 bcmasp_enable_tx_irq(intf, 1);
1120 bcmasp_enable_phy_irq(intf, 1);
1121 }
1122
bcmasp_open(struct net_device * dev)1123 static int bcmasp_open(struct net_device *dev)
1124 {
1125 struct bcmasp_intf *intf = netdev_priv(dev);
1126 int ret;
1127
1128 netif_dbg(intf, ifup, dev, "bcmasp open\n");
1129
1130 ret = bcmasp_alloc_buffers(intf);
1131 if (ret)
1132 return ret;
1133
1134 ret = clk_prepare_enable(intf->parent->clk);
1135 if (ret)
1136 goto err_free_mem;
1137
1138 bcmasp_core_clock_set_intf(intf, true);
1139
1140 bcmasp_phy_hw_prepare(intf);
1141
1142 ret = bcmasp_phy_attach(intf);
1143 if (ret)
1144 goto err_phy_attach;
1145
1146 umac_reset_and_init(intf, dev->dev_addr);
1147
1148 dev->phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER);
1149
1150 bcmasp_netif_init(dev);
1151
1152 phy_start(dev->phydev);
1153
1154 netif_start_queue(dev);
1155
1156 return ret;
1157
1158 err_phy_attach:
1159 bcmasp_phy_hw_unprepare(intf);
1160 bcmasp_core_clock_set_intf(intf, false);
1161 clk_disable_unprepare(intf->parent->clk);
1162 err_free_mem:
1163 bcmasp_reclaim_free_buffers(intf);
1164
1165 return ret;
1166 }
1167
bcmasp_tx_timeout(struct net_device * dev,unsigned int txqueue)1168 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue)
1169 {
1170 struct bcmasp_intf *intf = netdev_priv(dev);
1171
1172 netif_dbg(intf, tx_err, dev, "transmit timeout!\n");
1173 intf->mib.tx_timeout_cnt++;
1174 }
1175
bcmasp_get_phys_port_name(struct net_device * dev,char * name,size_t len)1176 static int bcmasp_get_phys_port_name(struct net_device *dev,
1177 char *name, size_t len)
1178 {
1179 struct bcmasp_intf *intf = netdev_priv(dev);
1180
1181 if (snprintf(name, len, "p%d", intf->port) >= len)
1182 return -EINVAL;
1183
1184 return 0;
1185 }
1186
bcmasp_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)1187 static void bcmasp_get_stats64(struct net_device *dev,
1188 struct rtnl_link_stats64 *stats)
1189 {
1190 struct bcmasp_intf *intf = netdev_priv(dev);
1191 struct bcmasp_intf_stats64 *lstats;
1192 unsigned int start;
1193
1194 lstats = &intf->stats64;
1195
1196 do {
1197 start = u64_stats_fetch_begin(&lstats->syncp);
1198 stats->rx_packets = u64_stats_read(&lstats->rx_packets);
1199 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes);
1200 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped);
1201 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs);
1202 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs);
1203 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1204
1205 stats->tx_packets = u64_stats_read(&lstats->tx_packets);
1206 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes);
1207 } while (u64_stats_fetch_retry(&lstats->syncp, start));
1208 }
1209
1210 static const struct net_device_ops bcmasp_netdev_ops = {
1211 .ndo_open = bcmasp_open,
1212 .ndo_stop = bcmasp_stop,
1213 .ndo_start_xmit = bcmasp_xmit,
1214 .ndo_tx_timeout = bcmasp_tx_timeout,
1215 .ndo_set_rx_mode = bcmasp_set_rx_mode,
1216 .ndo_get_phys_port_name = bcmasp_get_phys_port_name,
1217 .ndo_eth_ioctl = phy_do_ioctl_running,
1218 .ndo_set_mac_address = eth_mac_addr,
1219 .ndo_get_stats64 = bcmasp_get_stats64,
1220 };
1221
bcmasp_map_res(struct bcmasp_priv * priv,struct bcmasp_intf * intf)1222 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf)
1223 {
1224 /* Per port */
1225 intf->res.umac = priv->base + UMC_OFFSET(intf);
1226 intf->res.umac2fb = priv->base + (UMAC2FB_OFFSET + priv->rx_ctrl_offset +
1227 (intf->port * 0x4));
1228 intf->res.rgmii = priv->base + RGMII_OFFSET(intf);
1229
1230 /* Per ch */
1231 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf);
1232 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf);
1233 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf);
1234 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf);
1235 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf);
1236
1237 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf);
1238 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf);
1239 }
1240
bcmasp_interface_create(struct bcmasp_priv * priv,struct device_node * ndev_dn,int i)1241 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv,
1242 struct device_node *ndev_dn, int i)
1243 {
1244 struct device *dev = &priv->pdev->dev;
1245 struct bcmasp_intf *intf;
1246 struct net_device *ndev;
1247 int ch, port, ret;
1248
1249 if (of_property_read_u32(ndev_dn, "reg", &port)) {
1250 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name);
1251 goto err;
1252 }
1253
1254 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) {
1255 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name);
1256 goto err;
1257 }
1258
1259 ndev = alloc_etherdev(sizeof(struct bcmasp_intf));
1260 if (!ndev) {
1261 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name);
1262 goto err;
1263 }
1264 intf = netdev_priv(ndev);
1265
1266 intf->parent = priv;
1267 intf->ndev = ndev;
1268 intf->channel = ch;
1269 intf->port = port;
1270 intf->ndev_dn = ndev_dn;
1271 intf->index = i;
1272
1273 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface);
1274 if (ret < 0) {
1275 dev_err(dev, "invalid PHY mode property\n");
1276 goto err_free_netdev;
1277 }
1278
1279 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
1280 intf->internal_phy = true;
1281
1282 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0);
1283 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) {
1284 ret = of_phy_register_fixed_link(ndev_dn);
1285 if (ret) {
1286 dev_warn(dev, "%s: failed to register fixed PHY\n",
1287 ndev_dn->name);
1288 goto err_free_netdev;
1289 }
1290 intf->phy_dn = ndev_dn;
1291 }
1292
1293 /* Map resource */
1294 bcmasp_map_res(priv, intf);
1295
1296 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) &&
1297 intf->phy_interface != PHY_INTERFACE_MODE_MII &&
1298 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) ||
1299 (intf->port != 1 && intf->internal_phy)) {
1300 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n",
1301 phy_modes(intf->phy_interface), intf->port);
1302 ret = -EINVAL;
1303 goto err_deregister_fixed_link;
1304 }
1305
1306 ret = of_get_ethdev_address(ndev_dn, ndev);
1307 if (ret) {
1308 netdev_warn(ndev, "using random Ethernet MAC\n");
1309 eth_hw_addr_random(ndev);
1310 }
1311
1312 SET_NETDEV_DEV(ndev, dev);
1313 ndev->netdev_ops = &bcmasp_netdev_ops;
1314 ndev->ethtool_ops = &bcmasp_ethtool_ops;
1315 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV |
1316 NETIF_MSG_PROBE |
1317 NETIF_MSG_LINK);
1318 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
1319 NETIF_F_RXCSUM;
1320 ndev->hw_features |= ndev->features;
1321 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload);
1322
1323 netdev_sw_irq_coalesce_default_on(ndev);
1324
1325 return intf;
1326
1327 err_deregister_fixed_link:
1328 if (of_phy_is_fixed_link(ndev_dn))
1329 of_phy_deregister_fixed_link(ndev_dn);
1330 err_free_netdev:
1331 free_netdev(ndev);
1332 err:
1333 return NULL;
1334 }
1335
bcmasp_interface_destroy(struct bcmasp_intf * intf)1336 void bcmasp_interface_destroy(struct bcmasp_intf *intf)
1337 {
1338 if (intf->ndev->reg_state == NETREG_REGISTERED)
1339 unregister_netdev(intf->ndev);
1340 if (of_phy_is_fixed_link(intf->ndev_dn))
1341 of_phy_deregister_fixed_link(intf->ndev_dn);
1342 free_netdev(intf->ndev);
1343 }
1344
bcmasp_suspend_to_wol(struct bcmasp_intf * intf)1345 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf)
1346 {
1347 struct net_device *ndev = intf->ndev;
1348 u32 reg;
1349
1350 reg = umac_rl(intf, UMC_MPD_CTRL);
1351 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE))
1352 reg |= UMC_MPD_CTRL_MPD_EN;
1353 reg &= ~UMC_MPD_CTRL_PSW_EN;
1354 if (intf->wolopts & WAKE_MAGICSECURE) {
1355 /* Program the SecureOn password */
1356 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]),
1357 UMC_PSW_MS);
1358 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]),
1359 UMC_PSW_LS);
1360 reg |= UMC_MPD_CTRL_PSW_EN;
1361 }
1362 umac_wl(intf, reg, UMC_MPD_CTRL);
1363
1364 if (intf->wolopts & WAKE_FILTER)
1365 bcmasp_netfilt_suspend(intf);
1366
1367 /* Bring UniMAC out of reset if needed and enable RX */
1368 reg = umac_rl(intf, UMC_CMD);
1369 if (reg & UMC_CMD_SW_RESET)
1370 reg &= ~UMC_CMD_SW_RESET;
1371
1372 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC;
1373 umac_wl(intf, reg, UMC_CMD);
1374
1375 umac_enable_set(intf, UMC_CMD_RX_EN, 1);
1376
1377 wakeup_intr2_core_wl(intf->parent, 0xffffffff,
1378 ASP_WAKEUP_INTR2_MASK_CLEAR);
1379
1380 if (ndev->phydev && ndev->phydev->eee_cfg.eee_enabled &&
1381 intf->parent->eee_fixup)
1382 intf->parent->eee_fixup(intf, true);
1383
1384 netif_dbg(intf, wol, ndev, "entered WOL mode\n");
1385 }
1386
bcmasp_interface_suspend(struct bcmasp_intf * intf)1387 int bcmasp_interface_suspend(struct bcmasp_intf *intf)
1388 {
1389 struct device *kdev = &intf->parent->pdev->dev;
1390 struct net_device *dev = intf->ndev;
1391 bool wake;
1392
1393 if (!netif_running(dev))
1394 return 0;
1395
1396 netif_device_detach(dev);
1397
1398 wake = device_may_wakeup(kdev) && intf->wolopts;
1399
1400 bcmasp_netif_deinit(dev, !wake);
1401
1402 if (wake) {
1403 /* Disable phy status updates while suspending */
1404 mutex_lock(&dev->phydev->lock);
1405 dev->phydev->state = PHY_READY;
1406 mutex_unlock(&dev->phydev->lock);
1407 cancel_delayed_work_sync(&dev->phydev->state_queue);
1408
1409 bcmasp_suspend_to_wol(intf);
1410 } else {
1411 bcmasp_phy_hw_unprepare(intf);
1412
1413 /* If Wake-on-LAN is disabled, we can safely
1414 * disable the network interface clocks.
1415 */
1416 bcmasp_core_clock_set_intf(intf, false);
1417 }
1418
1419 clk_disable_unprepare(intf->parent->clk);
1420
1421 return 0;
1422 }
1423
bcmasp_resume_from_wol(struct bcmasp_intf * intf)1424 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf)
1425 {
1426 u32 reg;
1427
1428 if (intf->ndev->phydev && intf->ndev->phydev->eee_cfg.eee_enabled &&
1429 intf->parent->eee_fixup)
1430 intf->parent->eee_fixup(intf, false);
1431
1432 reg = umac_rl(intf, UMC_MPD_CTRL);
1433 reg &= ~UMC_MPD_CTRL_MPD_EN;
1434 umac_wl(intf, reg, UMC_MPD_CTRL);
1435
1436 wakeup_intr2_core_wl(intf->parent, 0xffffffff,
1437 ASP_WAKEUP_INTR2_MASK_SET);
1438 }
1439
bcmasp_interface_resume(struct bcmasp_intf * intf)1440 int bcmasp_interface_resume(struct bcmasp_intf *intf)
1441 {
1442 struct device *kdev = &intf->parent->pdev->dev;
1443 struct net_device *dev = intf->ndev;
1444 bool wake;
1445 int ret;
1446 u32 reg;
1447
1448 if (!netif_running(dev))
1449 return 0;
1450
1451 ret = clk_prepare_enable(intf->parent->clk);
1452 if (ret)
1453 return ret;
1454
1455 wake = device_may_wakeup(kdev) && intf->wolopts;
1456
1457 bcmasp_core_clock_set_intf(intf, true);
1458
1459 /* The interface might be HW reset in some suspend modes, so we may
1460 * need to restore the UNIMAC/PHY if that is the case.
1461 */
1462 reg = umac_rl(intf, UMC_CMD);
1463 if (wake && (reg & UMC_CMD_RX_EN)) {
1464 umac_enable_set(intf, UMC_CMD_TX_EN, 1);
1465 bcmasp_resume_from_wol(intf);
1466 } else {
1467 bcmasp_phy_hw_prepare(intf);
1468 umac_reset_and_init(intf, dev->dev_addr);
1469 }
1470
1471 bcmasp_netif_init(dev);
1472
1473 if (wake) {
1474 /* If HW was reset, reprogram the unimac/PHY before resuming
1475 * link status tracking to avoid racing the state machine.
1476 */
1477 if (!(reg & UMC_CMD_RX_EN))
1478 bcmasp_adj_link(dev);
1479
1480 /* Resume link status tracking */
1481 mutex_lock(&dev->phydev->lock);
1482 dev->phydev->state = dev->phydev->link ? PHY_RUNNING : PHY_NOLINK;
1483 mutex_unlock(&dev->phydev->lock);
1484 phy_trigger_machine(dev->phydev);
1485 } else {
1486 phy_start(dev->phydev);
1487 }
1488
1489 netif_device_attach(dev);
1490
1491 return 0;
1492 }
1493