1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_smu.h"
36 #include "atom.h"
37 #include "amd_pcie.h"
38
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41 #include "mp/mp_13_0_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15_common.h"
45 #include "soc21.h"
46 #include "mxgpu_nv.h"
47
48 static const struct amd_ip_funcs soc21_common_ip_funcs;
49
50 /* SOC21 */
51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
55 };
56
57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
60 };
61
62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
65 };
66
67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
70 };
71
72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
78 };
79
80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
85 };
86
87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
90 };
91
92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
95 };
96
97 /* SRIOV SOC21, not const since data is controlled by host */
98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102 };
103
104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
107 };
108
109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
112 };
113
114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
117 };
118
119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
125 };
126
127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
132 };
133
134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
137 };
138
139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
142 };
143
144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = {
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
148 };
149
150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = {
151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0),
152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0,
153 };
154
155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = {
156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
161 };
162
163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = {
164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0),
165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0,
166 };
167
168
soc21_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
170 const struct amdgpu_video_codecs **codecs)
171 {
172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
173 return -EINVAL;
174
175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
176 case IP_VERSION(4, 0, 0):
177 case IP_VERSION(4, 0, 2):
178 case IP_VERSION(4, 0, 4):
179 case IP_VERSION(4, 0, 5):
180 if (amdgpu_sriov_vf(adev)) {
181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
182 !amdgpu_sriov_is_av1_support(adev)) {
183 if (encode)
184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
185 else
186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
187 } else {
188 if (encode)
189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
190 else
191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
192 }
193 } else {
194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
195 if (encode)
196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
197 else
198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
199 } else {
200 if (encode)
201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
202 else
203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
204 }
205 }
206 return 0;
207 case IP_VERSION(4, 0, 6):
208 if (encode)
209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
210 else
211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
212 return 0;
213 case IP_VERSION(5, 3, 0):
214 if (encode)
215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0;
216 else
217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0;
218 return 0;
219 default:
220 return -EINVAL;
221 }
222 }
223
soc21_didt_rreg(struct amdgpu_device * adev,u32 reg)224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
225 {
226 unsigned long flags, address, data;
227 u32 r;
228
229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
231
232 spin_lock_irqsave(&adev->didt_idx_lock, flags);
233 WREG32(address, (reg));
234 r = RREG32(data);
235 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
236 return r;
237 }
238
soc21_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
240 {
241 unsigned long flags, address, data;
242
243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
245
246 spin_lock_irqsave(&adev->didt_idx_lock, flags);
247 WREG32(address, (reg));
248 WREG32(data, (v));
249 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
250 }
251
soc21_get_config_memsize(struct amdgpu_device * adev)252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
253 {
254 return adev->nbio.funcs->get_memsize(adev);
255 }
256
soc21_get_xclk(struct amdgpu_device * adev)257 static u32 soc21_get_xclk(struct amdgpu_device *adev)
258 {
259 u32 reference_clock = adev->clock.spll.reference_freq;
260
261 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */
262 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000)
263 return 9981;
264
265 return reference_clock;
266 }
267
268
soc21_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)269 void soc21_grbm_select(struct amdgpu_device *adev,
270 u32 me, u32 pipe, u32 queue, u32 vmid)
271 {
272 u32 grbm_gfx_cntl = 0;
273 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
277
278 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
279 }
280
soc21_read_disabled_bios(struct amdgpu_device * adev)281 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
282 {
283 /* todo */
284 return false;
285 }
286
287 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
288 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
295 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
296 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
297 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
300 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
303 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
306 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
307 };
308
soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)309 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
310 u32 sh_num, u32 reg_offset)
311 {
312 uint32_t val;
313
314 mutex_lock(&adev->grbm_idx_mutex);
315 if (se_num != 0xffffffff || sh_num != 0xffffffff)
316 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
317
318 val = RREG32(reg_offset);
319
320 if (se_num != 0xffffffff || sh_num != 0xffffffff)
321 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
322 mutex_unlock(&adev->grbm_idx_mutex);
323 return val;
324 }
325
soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)326 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
327 bool indexed, u32 se_num,
328 u32 sh_num, u32 reg_offset)
329 {
330 if (indexed) {
331 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
332 } else {
333 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
334 return adev->gfx.config.gb_addr_config;
335 return RREG32(reg_offset);
336 }
337 }
338
soc21_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)339 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
340 u32 sh_num, u32 reg_offset, u32 *value)
341 {
342 uint32_t i;
343 struct soc15_allowed_register_entry *en;
344
345 *value = 0;
346 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
347 en = &soc21_allowed_read_registers[i];
348 if (!adev->reg_offset[en->hwip][en->inst])
349 continue;
350 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
351 + en->reg_offset))
352 continue;
353
354 *value = soc21_get_register_value(adev,
355 soc21_allowed_read_registers[i].grbm_indexed,
356 se_num, sh_num, reg_offset);
357 return 0;
358 }
359 return -EINVAL;
360 }
361
362 #if 0
363 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
364 {
365 u32 i;
366 int ret = 0;
367
368 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
369
370 /* disable BM */
371 pci_clear_master(adev->pdev);
372
373 amdgpu_device_cache_pci_state(adev->pdev);
374
375 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
376 dev_info(adev->dev, "GPU smu mode1 reset\n");
377 ret = amdgpu_dpm_mode1_reset(adev);
378 } else {
379 dev_info(adev->dev, "GPU psp mode1 reset\n");
380 ret = psp_gpu_reset(adev);
381 }
382
383 if (ret)
384 dev_err(adev->dev, "GPU mode1 reset failed\n");
385 amdgpu_device_load_pci_state(adev->pdev);
386
387 /* wait for asic to come out of reset */
388 for (i = 0; i < adev->usec_timeout; i++) {
389 u32 memsize = adev->nbio.funcs->get_memsize(adev);
390
391 if (memsize != 0xffffffff)
392 break;
393 udelay(1);
394 }
395
396 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
397
398 return ret;
399 }
400 #endif
401
402 static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device * adev)403 soc21_asic_reset_method(struct amdgpu_device *adev)
404 {
405 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
406 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
407 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
408 return amdgpu_reset_method;
409
410 if (amdgpu_reset_method != -1)
411 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
412 amdgpu_reset_method);
413
414 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
415 case IP_VERSION(13, 0, 0):
416 case IP_VERSION(13, 0, 7):
417 case IP_VERSION(13, 0, 10):
418 return AMD_RESET_METHOD_MODE1;
419 case IP_VERSION(13, 0, 4):
420 case IP_VERSION(13, 0, 11):
421 case IP_VERSION(14, 0, 0):
422 case IP_VERSION(14, 0, 1):
423 case IP_VERSION(14, 0, 4):
424 case IP_VERSION(14, 0, 5):
425 case IP_VERSION(15, 0, 0):
426 return AMD_RESET_METHOD_MODE2;
427 default:
428 if (amdgpu_dpm_is_baco_supported(adev))
429 return AMD_RESET_METHOD_BACO;
430 else
431 return AMD_RESET_METHOD_MODE1;
432 }
433 }
434
soc21_asic_reset(struct amdgpu_device * adev)435 static int soc21_asic_reset(struct amdgpu_device *adev)
436 {
437 int ret = 0;
438
439 switch (soc21_asic_reset_method(adev)) {
440 case AMD_RESET_METHOD_PCI:
441 dev_info(adev->dev, "PCI reset\n");
442 ret = amdgpu_device_pci_reset(adev);
443 break;
444 case AMD_RESET_METHOD_BACO:
445 dev_info(adev->dev, "BACO reset\n");
446 ret = amdgpu_dpm_baco_reset(adev);
447 break;
448 case AMD_RESET_METHOD_MODE2:
449 dev_info(adev->dev, "MODE2 reset\n");
450 ret = amdgpu_dpm_mode2_reset(adev);
451 break;
452 default:
453 dev_info(adev->dev, "MODE1 reset\n");
454 ret = amdgpu_device_mode1_reset(adev);
455 break;
456 }
457
458 return ret;
459 }
460
soc21_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)461 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
462 {
463 /* todo */
464 return 0;
465 }
466
soc21_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)467 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
468 {
469 /* todo */
470 return 0;
471 }
472
soc21_program_aspm(struct amdgpu_device * adev)473 static void soc21_program_aspm(struct amdgpu_device *adev)
474 {
475 if (!amdgpu_device_should_use_aspm(adev))
476 return;
477
478 if (adev->nbio.funcs->program_aspm)
479 adev->nbio.funcs->program_aspm(adev);
480 }
481
482 const struct amdgpu_ip_block_version soc21_common_ip_block = {
483 .type = AMD_IP_BLOCK_TYPE_COMMON,
484 .major = 1,
485 .minor = 0,
486 .rev = 0,
487 .funcs = &soc21_common_ip_funcs,
488 };
489
soc21_need_full_reset(struct amdgpu_device * adev)490 static bool soc21_need_full_reset(struct amdgpu_device *adev)
491 {
492 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
493 case IP_VERSION(11, 0, 0):
494 case IP_VERSION(11, 0, 2):
495 case IP_VERSION(11, 0, 3):
496 default:
497 return true;
498 }
499 }
500
soc21_need_reset_on_init(struct amdgpu_device * adev)501 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
502 {
503 u32 sol_reg;
504
505 if (adev->flags & AMD_IS_APU)
506 return false;
507
508 /* Check sOS sign of life register to confirm sys driver and sOS
509 * are already been loaded.
510 */
511 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
512 if (sol_reg)
513 return true;
514
515 return false;
516 }
517
soc21_init_doorbell_index(struct amdgpu_device * adev)518 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
519 {
520 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
521 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
522 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
523 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
524 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
525 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
526 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
527 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
528 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
529 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
530 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
531 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
532 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
533 adev->doorbell_index.gfx_userqueue_start =
534 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
535 adev->doorbell_index.gfx_userqueue_end =
536 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
537 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
538 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
539 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
540 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
541 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
542 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
543 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
544 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
545 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
546 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE;
547 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
548 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
549
550 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
551 adev->doorbell_index.sdma_doorbell_range = 20;
552 }
553
soc21_update_umd_stable_pstate(struct amdgpu_device * adev,bool enter)554 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
555 bool enter)
556 {
557 if (enter)
558 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
559 else
560 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
561
562 if (adev->gfx.funcs->update_perfmon_mgcg)
563 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
564
565 return 0;
566 }
567
568 static const struct amdgpu_asic_funcs soc21_asic_funcs = {
569 .read_disabled_bios = &soc21_read_disabled_bios,
570 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
571 .read_register = &soc21_read_register,
572 .reset = &soc21_asic_reset,
573 .reset_method = &soc21_asic_reset_method,
574 .get_xclk = &soc21_get_xclk,
575 .set_uvd_clocks = &soc21_set_uvd_clocks,
576 .set_vce_clocks = &soc21_set_vce_clocks,
577 .get_config_memsize = &soc21_get_config_memsize,
578 .init_doorbell_index = &soc21_init_doorbell_index,
579 .need_full_reset = &soc21_need_full_reset,
580 .need_reset_on_init = &soc21_need_reset_on_init,
581 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
582 .supports_baco = &amdgpu_dpm_is_baco_supported,
583 .query_video_codecs = &soc21_query_video_codecs,
584 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
585 };
586
soc21_common_early_init(struct amdgpu_ip_block * ip_block)587 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
588 {
589 struct amdgpu_device *adev = ip_block->adev;
590
591 adev->nbio.funcs->set_reg_remap(adev);
592 adev->smc_rreg = NULL;
593 adev->smc_wreg = NULL;
594 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
595 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
596 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
597 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
598 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
599 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
600
601 /* TODO: will add them during VCN v2 implementation */
602 adev->uvd_ctx_rreg = NULL;
603 adev->uvd_ctx_wreg = NULL;
604
605 adev->didt_rreg = &soc21_didt_rreg;
606 adev->didt_wreg = &soc21_didt_wreg;
607
608 adev->asic_funcs = &soc21_asic_funcs;
609
610 adev->rev_id = amdgpu_device_get_rev_id(adev);
611 adev->external_rev_id = 0xff;
612 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
613 case IP_VERSION(11, 0, 0):
614 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
615 AMD_CG_SUPPORT_GFX_CGLS |
616 #if 0
617 AMD_CG_SUPPORT_GFX_3D_CGCG |
618 AMD_CG_SUPPORT_GFX_3D_CGLS |
619 #endif
620 AMD_CG_SUPPORT_GFX_MGCG |
621 AMD_CG_SUPPORT_REPEATER_FGCG |
622 AMD_CG_SUPPORT_GFX_FGCG |
623 AMD_CG_SUPPORT_GFX_PERF_CLK |
624 AMD_CG_SUPPORT_VCN_MGCG |
625 AMD_CG_SUPPORT_JPEG_MGCG |
626 AMD_CG_SUPPORT_ATHUB_MGCG |
627 AMD_CG_SUPPORT_ATHUB_LS |
628 AMD_CG_SUPPORT_MC_MGCG |
629 AMD_CG_SUPPORT_MC_LS |
630 AMD_CG_SUPPORT_IH_CG |
631 AMD_CG_SUPPORT_HDP_SD;
632 adev->pg_flags = AMD_PG_SUPPORT_VCN |
633 AMD_PG_SUPPORT_VCN_DPG |
634 AMD_PG_SUPPORT_JPEG |
635 AMD_PG_SUPPORT_ATHUB |
636 AMD_PG_SUPPORT_MMHUB;
637 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
638 break;
639 case IP_VERSION(11, 0, 2):
640 adev->cg_flags =
641 AMD_CG_SUPPORT_GFX_CGCG |
642 AMD_CG_SUPPORT_GFX_CGLS |
643 AMD_CG_SUPPORT_REPEATER_FGCG |
644 AMD_CG_SUPPORT_VCN_MGCG |
645 AMD_CG_SUPPORT_JPEG_MGCG |
646 AMD_CG_SUPPORT_ATHUB_MGCG |
647 AMD_CG_SUPPORT_ATHUB_LS |
648 AMD_CG_SUPPORT_IH_CG |
649 AMD_CG_SUPPORT_HDP_SD;
650 adev->pg_flags =
651 AMD_PG_SUPPORT_VCN |
652 AMD_PG_SUPPORT_VCN_DPG |
653 AMD_PG_SUPPORT_JPEG |
654 AMD_PG_SUPPORT_ATHUB |
655 AMD_PG_SUPPORT_MMHUB;
656 adev->external_rev_id = adev->rev_id + 0x10;
657 break;
658 case IP_VERSION(11, 0, 1):
659 adev->cg_flags =
660 AMD_CG_SUPPORT_GFX_CGCG |
661 AMD_CG_SUPPORT_GFX_CGLS |
662 AMD_CG_SUPPORT_GFX_MGCG |
663 AMD_CG_SUPPORT_GFX_FGCG |
664 AMD_CG_SUPPORT_REPEATER_FGCG |
665 AMD_CG_SUPPORT_GFX_PERF_CLK |
666 AMD_CG_SUPPORT_MC_MGCG |
667 AMD_CG_SUPPORT_MC_LS |
668 AMD_CG_SUPPORT_HDP_MGCG |
669 AMD_CG_SUPPORT_HDP_LS |
670 AMD_CG_SUPPORT_ATHUB_MGCG |
671 AMD_CG_SUPPORT_ATHUB_LS |
672 AMD_CG_SUPPORT_IH_CG |
673 AMD_CG_SUPPORT_BIF_MGCG |
674 AMD_CG_SUPPORT_BIF_LS |
675 AMD_CG_SUPPORT_VCN_MGCG |
676 AMD_CG_SUPPORT_JPEG_MGCG;
677 adev->pg_flags =
678 AMD_PG_SUPPORT_GFX_PG |
679 AMD_PG_SUPPORT_VCN |
680 AMD_PG_SUPPORT_VCN_DPG |
681 AMD_PG_SUPPORT_JPEG;
682 adev->external_rev_id = adev->rev_id + 0x1;
683 break;
684 case IP_VERSION(11, 0, 3):
685 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
686 AMD_CG_SUPPORT_JPEG_MGCG |
687 AMD_CG_SUPPORT_GFX_CGCG |
688 AMD_CG_SUPPORT_GFX_CGLS |
689 AMD_CG_SUPPORT_REPEATER_FGCG |
690 AMD_CG_SUPPORT_GFX_MGCG |
691 AMD_CG_SUPPORT_HDP_SD |
692 AMD_CG_SUPPORT_ATHUB_MGCG |
693 AMD_CG_SUPPORT_ATHUB_LS;
694 adev->pg_flags = AMD_PG_SUPPORT_VCN |
695 AMD_PG_SUPPORT_VCN_DPG |
696 AMD_PG_SUPPORT_JPEG;
697 adev->external_rev_id = adev->rev_id + 0x20;
698 break;
699 case IP_VERSION(11, 0, 4):
700 adev->cg_flags =
701 AMD_CG_SUPPORT_GFX_CGCG |
702 AMD_CG_SUPPORT_GFX_CGLS |
703 AMD_CG_SUPPORT_GFX_MGCG |
704 AMD_CG_SUPPORT_GFX_FGCG |
705 AMD_CG_SUPPORT_REPEATER_FGCG |
706 AMD_CG_SUPPORT_GFX_PERF_CLK |
707 AMD_CG_SUPPORT_MC_MGCG |
708 AMD_CG_SUPPORT_MC_LS |
709 AMD_CG_SUPPORT_HDP_MGCG |
710 AMD_CG_SUPPORT_HDP_LS |
711 AMD_CG_SUPPORT_ATHUB_MGCG |
712 AMD_CG_SUPPORT_ATHUB_LS |
713 AMD_CG_SUPPORT_IH_CG |
714 AMD_CG_SUPPORT_BIF_MGCG |
715 AMD_CG_SUPPORT_BIF_LS |
716 AMD_CG_SUPPORT_VCN_MGCG |
717 AMD_CG_SUPPORT_JPEG_MGCG;
718 adev->pg_flags = AMD_PG_SUPPORT_VCN |
719 AMD_PG_SUPPORT_VCN_DPG |
720 AMD_PG_SUPPORT_GFX_PG |
721 AMD_PG_SUPPORT_JPEG;
722 adev->external_rev_id = adev->rev_id + 0x80;
723 break;
724 case IP_VERSION(11, 5, 0):
725 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
726 AMD_CG_SUPPORT_JPEG_MGCG |
727 AMD_CG_SUPPORT_GFX_CGCG |
728 AMD_CG_SUPPORT_GFX_CGLS |
729 AMD_CG_SUPPORT_GFX_MGCG |
730 AMD_CG_SUPPORT_GFX_FGCG |
731 AMD_CG_SUPPORT_REPEATER_FGCG |
732 AMD_CG_SUPPORT_GFX_PERF_CLK |
733 AMD_CG_SUPPORT_GFX_3D_CGCG |
734 AMD_CG_SUPPORT_GFX_3D_CGLS |
735 AMD_CG_SUPPORT_MC_MGCG |
736 AMD_CG_SUPPORT_MC_LS |
737 AMD_CG_SUPPORT_HDP_LS |
738 AMD_CG_SUPPORT_HDP_DS |
739 AMD_CG_SUPPORT_HDP_SD |
740 AMD_CG_SUPPORT_ATHUB_MGCG |
741 AMD_CG_SUPPORT_ATHUB_LS |
742 AMD_CG_SUPPORT_IH_CG |
743 AMD_CG_SUPPORT_BIF_MGCG |
744 AMD_CG_SUPPORT_BIF_LS;
745 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
746 AMD_PG_SUPPORT_JPEG_DPG |
747 AMD_PG_SUPPORT_VCN |
748 AMD_PG_SUPPORT_JPEG |
749 AMD_PG_SUPPORT_GFX_PG;
750 if (adev->rev_id == 0)
751 adev->external_rev_id = 0x1;
752 else
753 adev->external_rev_id = adev->rev_id + 0x10;
754 break;
755 case IP_VERSION(11, 5, 1):
756 adev->cg_flags =
757 AMD_CG_SUPPORT_GFX_CGCG |
758 AMD_CG_SUPPORT_GFX_CGLS |
759 AMD_CG_SUPPORT_GFX_MGCG |
760 AMD_CG_SUPPORT_GFX_FGCG |
761 AMD_CG_SUPPORT_REPEATER_FGCG |
762 AMD_CG_SUPPORT_GFX_PERF_CLK |
763 AMD_CG_SUPPORT_GFX_3D_CGCG |
764 AMD_CG_SUPPORT_GFX_3D_CGLS |
765 AMD_CG_SUPPORT_MC_MGCG |
766 AMD_CG_SUPPORT_MC_LS |
767 AMD_CG_SUPPORT_HDP_LS |
768 AMD_CG_SUPPORT_HDP_DS |
769 AMD_CG_SUPPORT_HDP_SD |
770 AMD_CG_SUPPORT_ATHUB_MGCG |
771 AMD_CG_SUPPORT_ATHUB_LS |
772 AMD_CG_SUPPORT_IH_CG |
773 AMD_CG_SUPPORT_BIF_MGCG |
774 AMD_CG_SUPPORT_BIF_LS |
775 AMD_CG_SUPPORT_VCN_MGCG |
776 AMD_CG_SUPPORT_JPEG_MGCG;
777 adev->pg_flags =
778 AMD_PG_SUPPORT_GFX_PG |
779 AMD_PG_SUPPORT_VCN |
780 AMD_PG_SUPPORT_VCN_DPG |
781 AMD_PG_SUPPORT_JPEG;
782 adev->external_rev_id = adev->rev_id + 0xc1;
783 break;
784 case IP_VERSION(11, 5, 2):
785 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
786 AMD_CG_SUPPORT_JPEG_MGCG |
787 AMD_CG_SUPPORT_GFX_CGCG |
788 AMD_CG_SUPPORT_GFX_CGLS |
789 AMD_CG_SUPPORT_GFX_MGCG |
790 AMD_CG_SUPPORT_GFX_FGCG |
791 AMD_CG_SUPPORT_REPEATER_FGCG |
792 AMD_CG_SUPPORT_GFX_PERF_CLK |
793 AMD_CG_SUPPORT_GFX_3D_CGCG |
794 AMD_CG_SUPPORT_GFX_3D_CGLS |
795 AMD_CG_SUPPORT_MC_MGCG |
796 AMD_CG_SUPPORT_MC_LS |
797 AMD_CG_SUPPORT_HDP_LS |
798 AMD_CG_SUPPORT_HDP_DS |
799 AMD_CG_SUPPORT_HDP_SD |
800 AMD_CG_SUPPORT_ATHUB_MGCG |
801 AMD_CG_SUPPORT_ATHUB_LS |
802 AMD_CG_SUPPORT_IH_CG |
803 AMD_CG_SUPPORT_BIF_MGCG |
804 AMD_CG_SUPPORT_BIF_LS;
805 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
806 AMD_PG_SUPPORT_VCN |
807 AMD_PG_SUPPORT_JPEG_DPG |
808 AMD_PG_SUPPORT_JPEG |
809 AMD_PG_SUPPORT_GFX_PG;
810 adev->external_rev_id = adev->rev_id + 0x40;
811 break;
812 case IP_VERSION(11, 5, 3):
813 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
814 AMD_CG_SUPPORT_JPEG_MGCG |
815 AMD_CG_SUPPORT_GFX_CGCG |
816 AMD_CG_SUPPORT_GFX_CGLS |
817 AMD_CG_SUPPORT_GFX_MGCG |
818 AMD_CG_SUPPORT_GFX_FGCG |
819 AMD_CG_SUPPORT_REPEATER_FGCG |
820 AMD_CG_SUPPORT_GFX_PERF_CLK |
821 AMD_CG_SUPPORT_GFX_3D_CGCG |
822 AMD_CG_SUPPORT_GFX_3D_CGLS |
823 AMD_CG_SUPPORT_MC_MGCG |
824 AMD_CG_SUPPORT_MC_LS |
825 AMD_CG_SUPPORT_HDP_LS |
826 AMD_CG_SUPPORT_HDP_DS |
827 AMD_CG_SUPPORT_HDP_SD |
828 AMD_CG_SUPPORT_ATHUB_MGCG |
829 AMD_CG_SUPPORT_ATHUB_LS |
830 AMD_CG_SUPPORT_IH_CG |
831 AMD_CG_SUPPORT_BIF_MGCG |
832 AMD_CG_SUPPORT_BIF_LS;
833 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
834 AMD_PG_SUPPORT_VCN |
835 AMD_PG_SUPPORT_JPEG_DPG |
836 AMD_PG_SUPPORT_JPEG |
837 AMD_PG_SUPPORT_GFX_PG;
838 adev->external_rev_id = adev->rev_id + 0x50;
839 break;
840 case IP_VERSION(11, 5, 4):
841 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
842 AMD_CG_SUPPORT_JPEG_MGCG |
843 AMD_CG_SUPPORT_GFX_CGCG |
844 AMD_CG_SUPPORT_GFX_CGLS |
845 AMD_CG_SUPPORT_GFX_MGCG |
846 AMD_CG_SUPPORT_GFX_FGCG |
847 AMD_CG_SUPPORT_REPEATER_FGCG |
848 AMD_CG_SUPPORT_GFX_PERF_CLK |
849 AMD_CG_SUPPORT_GFX_3D_CGCG |
850 AMD_CG_SUPPORT_GFX_3D_CGLS |
851 AMD_CG_SUPPORT_MC_MGCG |
852 AMD_CG_SUPPORT_MC_LS |
853 AMD_CG_SUPPORT_HDP_LS |
854 AMD_CG_SUPPORT_HDP_DS |
855 AMD_CG_SUPPORT_HDP_SD |
856 AMD_CG_SUPPORT_ATHUB_MGCG |
857 AMD_CG_SUPPORT_ATHUB_LS |
858 AMD_CG_SUPPORT_IH_CG |
859 AMD_CG_SUPPORT_BIF_MGCG |
860 AMD_CG_SUPPORT_BIF_LS;
861 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
862 AMD_PG_SUPPORT_VCN |
863 AMD_PG_SUPPORT_JPEG_DPG |
864 AMD_PG_SUPPORT_JPEG |
865 AMD_PG_SUPPORT_GFX_PG;
866 adev->external_rev_id = adev->rev_id + 0x1;
867 break;
868 default:
869 /* FIXME: not supported yet */
870 return -EINVAL;
871 }
872
873 if (amdgpu_sriov_vf(adev)) {
874 amdgpu_virt_init_setting(adev);
875 xgpu_nv_mailbox_set_irq_funcs(adev);
876 }
877
878 return 0;
879 }
880
soc21_common_late_init(struct amdgpu_ip_block * ip_block)881 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block)
882 {
883 struct amdgpu_device *adev = ip_block->adev;
884
885 if (amdgpu_sriov_vf(adev)) {
886 xgpu_nv_mailbox_get_irq(adev);
887 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
888 !amdgpu_sriov_is_av1_support(adev)) {
889 amdgpu_virt_update_sriov_video_codec(adev,
890 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
891 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
892 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
893 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
894 } else {
895 amdgpu_virt_update_sriov_video_codec(adev,
896 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
897 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
898 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
899 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
900 }
901 } else {
902 if (adev->nbio.ras &&
903 adev->nbio.ras_err_event_athub_irq.funcs)
904 /* don't need to fail gpu late init
905 * if enabling athub_err_event interrupt failed
906 * nbio v4_3 only support fatal error hanlding
907 * just enable the interrupt directly */
908 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
909 }
910
911 /* Enable selfring doorbell aperture late because doorbell BAR
912 * aperture will change if resize BAR successfully in gmc sw_init.
913 */
914 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
915
916 return 0;
917 }
918
soc21_common_sw_init(struct amdgpu_ip_block * ip_block)919 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block)
920 {
921 struct amdgpu_device *adev = ip_block->adev;
922
923 if (amdgpu_sriov_vf(adev))
924 xgpu_nv_mailbox_add_irq_id(adev);
925
926 return 0;
927 }
928
soc21_common_hw_init(struct amdgpu_ip_block * ip_block)929 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block)
930 {
931 struct amdgpu_device *adev = ip_block->adev;
932
933 /* enable aspm */
934 soc21_program_aspm(adev);
935 /* setup nbio registers */
936 adev->nbio.funcs->init_registers(adev);
937 /* remap HDP registers to a hole in mmio space,
938 * for the purpose of expose those registers
939 * to process space
940 */
941 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
942 adev->nbio.funcs->remap_hdp_registers(adev);
943 /* enable the doorbell aperture */
944 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
945
946 return 0;
947 }
948
soc21_common_hw_fini(struct amdgpu_ip_block * ip_block)949 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block)
950 {
951 struct amdgpu_device *adev = ip_block->adev;
952
953 /* Disable the doorbell aperture and selfring doorbell aperture
954 * separately in hw_fini because soc21_enable_doorbell_aperture
955 * has been removed and there is no need to delay disabling
956 * selfring doorbell.
957 */
958 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
959 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
960
961 if (amdgpu_sriov_vf(adev)) {
962 xgpu_nv_mailbox_put_irq(adev);
963 } else {
964 if (adev->nbio.ras &&
965 adev->nbio.ras_err_event_athub_irq.funcs)
966 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
967 }
968
969 return 0;
970 }
971
soc21_common_suspend(struct amdgpu_ip_block * ip_block)972 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block)
973 {
974 return soc21_common_hw_fini(ip_block);
975 }
976
soc21_need_reset_on_resume(struct amdgpu_device * adev)977 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
978 {
979 u32 sol_reg1, sol_reg2;
980
981 /* Will reset for the following suspend abort cases.
982 * 1) Only reset dGPU side.
983 * 2) S3 suspend got aborted and TOS is active.
984 * As for dGPU suspend abort cases the SOL value
985 * will be kept as zero at this resume point.
986 */
987 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) {
988 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
989 msleep(100);
990 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
991
992 return (sol_reg1 != sol_reg2);
993 }
994
995 return false;
996 }
997
soc21_common_resume(struct amdgpu_ip_block * ip_block)998 static int soc21_common_resume(struct amdgpu_ip_block *ip_block)
999 {
1000 struct amdgpu_device *adev = ip_block->adev;
1001
1002 if (soc21_need_reset_on_resume(adev)) {
1003 dev_info(adev->dev, "S3 suspend aborted, resetting...");
1004 soc21_asic_reset(adev);
1005 }
1006
1007 return soc21_common_hw_init(ip_block);
1008 }
1009
soc21_common_is_idle(struct amdgpu_ip_block * ip_block)1010 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
1011 {
1012 return true;
1013 }
1014
soc21_common_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1015 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1016 enum amd_clockgating_state state)
1017 {
1018 struct amdgpu_device *adev = ip_block->adev;
1019
1020 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1021 case IP_VERSION(4, 3, 0):
1022 case IP_VERSION(4, 3, 1):
1023 case IP_VERSION(7, 7, 0):
1024 case IP_VERSION(7, 7, 1):
1025 case IP_VERSION(7, 11, 0):
1026 case IP_VERSION(7, 11, 1):
1027 case IP_VERSION(7, 11, 2):
1028 case IP_VERSION(7, 11, 3):
1029 case IP_VERSION(7, 11, 4):
1030 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1031 state == AMD_CG_STATE_GATE);
1032 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1033 state == AMD_CG_STATE_GATE);
1034 adev->hdp.funcs->update_clock_gating(adev,
1035 state == AMD_CG_STATE_GATE);
1036 break;
1037 default:
1038 break;
1039 }
1040 return 0;
1041 }
1042
soc21_common_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)1043 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1044 enum amd_powergating_state state)
1045 {
1046 struct amdgpu_device *adev = ip_block->adev;
1047
1048 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
1049 case IP_VERSION(6, 0, 0):
1050 case IP_VERSION(6, 0, 2):
1051 adev->lsdma.funcs->update_memory_power_gating(adev,
1052 state == AMD_PG_STATE_GATE);
1053 break;
1054 default:
1055 break;
1056 }
1057
1058 return 0;
1059 }
1060
soc21_common_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)1061 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1062 {
1063 struct amdgpu_device *adev = ip_block->adev;
1064
1065 adev->nbio.funcs->get_clockgating_state(adev, flags);
1066
1067 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1068 }
1069
1070 static const struct amd_ip_funcs soc21_common_ip_funcs = {
1071 .name = "soc21_common",
1072 .early_init = soc21_common_early_init,
1073 .late_init = soc21_common_late_init,
1074 .sw_init = soc21_common_sw_init,
1075 .hw_init = soc21_common_hw_init,
1076 .hw_fini = soc21_common_hw_fini,
1077 .suspend = soc21_common_suspend,
1078 .resume = soc21_common_resume,
1079 .is_idle = soc21_common_is_idle,
1080 .set_clockgating_state = soc21_common_set_clockgating_state,
1081 .set_powergating_state = soc21_common_set_powergating_state,
1082 .get_clockgating_state = soc21_common_get_clockgating_state,
1083 };
1084