1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/module.h>
8 #include <linux/msi.h>
9 #include <linux/pci.h>
10 #include <linux/of.h>
11 #include <linux/time.h>
12 #include <linux/vmalloc.h>
13
14 #include "pci.h"
15 #include "core.h"
16 #include "hif.h"
17 #include "mhi.h"
18 #include "debug.h"
19 #include "pcic.h"
20 #include "qmi.h"
21
22 #define ATH11K_PCI_BAR_NUM 0
23 #define ATH11K_PCI_DMA_MASK 36
24 #define ATH11K_PCI_COHERENT_DMA_MASK 32
25
26 #define TCSR_SOC_HW_VERSION 0x0224
27 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
28 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
29
30 #define QCA6390_DEVICE_ID 0x1101
31 #define QCN9074_DEVICE_ID 0x1104
32 #define WCN6855_DEVICE_ID 0x1103
33
34 #define TCSR_SOC_HW_SUB_VER 0x1910010
35
36 static const struct pci_device_id ath11k_pci_id_table[] = {
37 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
38 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
39 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
40 {}
41 };
42
43 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
44
ath11k_pci_bus_wake_up(struct ath11k_base * ab)45 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
46 {
47 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
48
49 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
50 }
51
ath11k_pci_bus_release(struct ath11k_base * ab)52 static void ath11k_pci_bus_release(struct ath11k_base *ab)
53 {
54 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
55
56 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
57 }
58
ath11k_pci_get_window_start(struct ath11k_base * ab,u32 offset)59 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
60 {
61 if (!ab->hw_params.static_window_map)
62 return ATH11K_PCI_WINDOW_START;
63
64 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
65 /* if offset lies within DP register range, use 3rd window */
66 return 3 * ATH11K_PCI_WINDOW_START;
67 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
68 ATH11K_PCI_WINDOW_RANGE_MASK)
69 /* if offset lies within CE register range, use 2nd window */
70 return 2 * ATH11K_PCI_WINDOW_START;
71 else
72 return ATH11K_PCI_WINDOW_START;
73 }
74
ath11k_pci_select_window(struct ath11k_pci * ab_pci,u32 offset)75 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
76 {
77 struct ath11k_base *ab = ab_pci->ab;
78
79 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
80
81 lockdep_assert_held(&ab_pci->window_lock);
82
83 if (window != ab_pci->register_window) {
84 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
85 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
86 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
87 ab_pci->register_window = window;
88 }
89 }
90
91 static void
ath11k_pci_window_write32(struct ath11k_base * ab,u32 offset,u32 value)92 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
93 {
94 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
95 u32 window_start;
96
97 window_start = ath11k_pci_get_window_start(ab, offset);
98
99 if (window_start == ATH11K_PCI_WINDOW_START) {
100 spin_lock_bh(&ab_pci->window_lock);
101 ath11k_pci_select_window(ab_pci, offset);
102 iowrite32(value, ab->mem + window_start +
103 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
104 spin_unlock_bh(&ab_pci->window_lock);
105 } else {
106 iowrite32(value, ab->mem + window_start +
107 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
108 }
109 }
110
ath11k_pci_window_read32(struct ath11k_base * ab,u32 offset)111 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
112 {
113 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
114 u32 window_start, val;
115
116 window_start = ath11k_pci_get_window_start(ab, offset);
117
118 if (window_start == ATH11K_PCI_WINDOW_START) {
119 spin_lock_bh(&ab_pci->window_lock);
120 ath11k_pci_select_window(ab_pci, offset);
121 val = ioread32(ab->mem + window_start +
122 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
123 spin_unlock_bh(&ab_pci->window_lock);
124 } else {
125 val = ioread32(ab->mem + window_start +
126 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
127 }
128
129 return val;
130 }
131
ath11k_pci_get_msi_irq(struct ath11k_base * ab,unsigned int vector)132 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
133 {
134 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
135
136 return pci_irq_vector(pci_dev, vector);
137 }
138
139 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
140 .wakeup = ath11k_pci_bus_wake_up,
141 .release = ath11k_pci_bus_release,
142 .get_msi_irq = ath11k_pci_get_msi_irq,
143 .window_write32 = ath11k_pci_window_write32,
144 .window_read32 = ath11k_pci_window_read32,
145 };
146
147 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
148 .wakeup = NULL,
149 .release = NULL,
150 .get_msi_irq = ath11k_pci_get_msi_irq,
151 .window_write32 = ath11k_pci_window_write32,
152 .window_read32 = ath11k_pci_window_read32,
153 };
154
155 static const struct ath11k_msi_config msi_config_one_msi = {
156 .total_vectors = 1,
157 .total_users = 4,
158 .users = (struct ath11k_msi_user[]) {
159 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
160 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
161 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
162 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
163 },
164 };
165
ath11k_pci_select_static_window(struct ath11k_pci * ab_pci)166 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
167 {
168 u32 umac_window;
169 u32 ce_window;
170 u32 window;
171
172 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
173 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
174 window = (umac_window << 12) | (ce_window << 6);
175
176 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
177 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
178 }
179
ath11k_pci_restore_window(struct ath11k_base * ab)180 static void ath11k_pci_restore_window(struct ath11k_base *ab)
181 {
182 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
183
184 spin_lock_bh(&ab_pci->window_lock);
185
186 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | ab_pci->register_window,
187 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
188 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
189
190 spin_unlock_bh(&ab_pci->window_lock);
191 }
192
ath11k_pci_soc_global_reset(struct ath11k_base * ab)193 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
194 {
195 u32 val, delay;
196
197 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
198
199 val |= PCIE_SOC_GLOBAL_RESET_V;
200
201 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
202 /* Flush the posted write to the device */
203 ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
204
205 /* TODO: exact time to sleep is uncertain */
206 delay = 10;
207 mdelay(delay);
208
209 /* Need to toggle V bit back otherwise stuck in reset status */
210 val &= ~PCIE_SOC_GLOBAL_RESET_V;
211
212 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
213 /* Flush the posted write to the device */
214 ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
215
216 mdelay(delay);
217
218 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
219 if (val == 0xffffffff)
220 ath11k_warn(ab, "link down error during global reset\n");
221
222 /* Restore window register as its content is cleared during
223 * hardware global reset, such that it aligns with host cache.
224 */
225 ath11k_pci_restore_window(ab);
226 }
227
ath11k_pci_clear_dbg_registers(struct ath11k_base * ab)228 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
229 {
230 u32 val;
231
232 /* read cookie */
233 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
234 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);
235
236 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
237 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
238
239 /* TODO: exact time to sleep is uncertain */
240 mdelay(10);
241
242 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
243 * continuing warm path and entering dead loop.
244 */
245 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
246 mdelay(10);
247
248 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
249 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
250
251 /* A read clear register. clear the register to prevent
252 * Q6 from entering wrong code path.
253 */
254 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
255 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
256 }
257
ath11k_pci_set_link_reg(struct ath11k_base * ab,u32 offset,u32 value,u32 mask)258 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
259 u32 offset, u32 value, u32 mask)
260 {
261 u32 v;
262 int i;
263
264 v = ath11k_pcic_read32(ab, offset);
265 if ((v & mask) == value)
266 return 0;
267
268 for (i = 0; i < 10; i++) {
269 ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
270
271 v = ath11k_pcic_read32(ab, offset);
272 if ((v & mask) == value)
273 return 0;
274
275 mdelay(2);
276 }
277
278 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
279 offset, v & mask, value);
280
281 return -ETIMEDOUT;
282 }
283
ath11k_pci_fix_l1ss(struct ath11k_base * ab)284 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
285 {
286 int ret;
287
288 ret = ath11k_pci_set_link_reg(ab,
289 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
290 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
291 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
292 if (ret) {
293 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
294 return ret;
295 }
296
297 ret = ath11k_pci_set_link_reg(ab,
298 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
299 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
300 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
301 if (ret) {
302 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
303 return ret;
304 }
305
306 ret = ath11k_pci_set_link_reg(ab,
307 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
308 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
309 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
310 if (ret) {
311 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
312 return ret;
313 }
314
315 ret = ath11k_pci_set_link_reg(ab,
316 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
317 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
318 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
319 if (ret) {
320 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
321 return ret;
322 }
323
324 return 0;
325 }
326
ath11k_pci_enable_ltssm(struct ath11k_base * ab)327 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
328 {
329 u32 val;
330 int i;
331
332 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
333
334 /* PCIE link seems very unstable after the Hot Reset*/
335 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
336 if (val == 0xffffffff)
337 mdelay(5);
338
339 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
340 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
341 }
342
343 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val);
344
345 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
346 val |= GCC_GCC_PCIE_HOT_RST_VAL;
347 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
348 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
349
350 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val);
351
352 mdelay(5);
353 }
354
ath11k_pci_clear_all_intrs(struct ath11k_base * ab)355 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
356 {
357 /* This is a WAR for PCIE Hotreset.
358 * When target receive Hotreset, but will set the interrupt.
359 * So when download SBL again, SBL will open Interrupt and
360 * receive it, and crash immediately.
361 */
362 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
363 }
364
ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base * ab)365 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
366 {
367 u32 val;
368
369 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
370 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
371 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
372 }
373
ath11k_pci_force_wake(struct ath11k_base * ab)374 static void ath11k_pci_force_wake(struct ath11k_base *ab)
375 {
376 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
377 mdelay(5);
378 }
379
ath11k_pci_sw_reset(struct ath11k_base * ab,bool power_on)380 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
381 {
382 mdelay(100);
383
384 if (power_on) {
385 ath11k_pci_enable_ltssm(ab);
386 ath11k_pci_clear_all_intrs(ab);
387 ath11k_pci_set_wlaon_pwr_ctrl(ab);
388 if (ab->hw_params.fix_l1ss)
389 ath11k_pci_fix_l1ss(ab);
390 }
391
392 ath11k_mhi_clear_vector(ab);
393 ath11k_pci_clear_dbg_registers(ab);
394 ath11k_pci_soc_global_reset(ab);
395 ath11k_mhi_set_mhictrl_reset(ab);
396 }
397
ath11k_pci_init_qmi_ce_config(struct ath11k_base * ab)398 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
399 {
400 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
401
402 cfg->tgt_ce = ab->hw_params.target_ce_config;
403 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
404
405 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
406 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
407 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
408
409 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
410 &cfg->shadow_reg_v2_len);
411 }
412
ath11k_pci_msi_config(struct ath11k_pci * ab_pci,bool enable)413 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
414 {
415 struct pci_dev *dev = ab_pci->pdev;
416 u16 control;
417
418 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
419
420 if (enable)
421 control |= PCI_MSI_FLAGS_ENABLE;
422 else
423 control &= ~PCI_MSI_FLAGS_ENABLE;
424
425 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
426 }
427
ath11k_pci_msi_enable(struct ath11k_pci * ab_pci)428 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
429 {
430 ath11k_pci_msi_config(ab_pci, true);
431 }
432
ath11k_pci_msi_disable(struct ath11k_pci * ab_pci)433 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
434 {
435 ath11k_pci_msi_config(ab_pci, false);
436 }
437
ath11k_pci_alloc_msi(struct ath11k_pci * ab_pci)438 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
439 {
440 struct ath11k_base *ab = ab_pci->ab;
441 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
442 struct pci_dev *pci_dev = ab_pci->pdev;
443 struct msi_desc *msi_desc;
444 int num_vectors;
445 int ret;
446
447 num_vectors = pci_alloc_irq_vectors(pci_dev,
448 msi_config->total_vectors,
449 msi_config->total_vectors,
450 PCI_IRQ_MSI);
451 if (num_vectors == msi_config->total_vectors) {
452 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
453 } else {
454 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
455 1,
456 1,
457 PCI_IRQ_MSI);
458 if (num_vectors < 0) {
459 ret = -EINVAL;
460 goto reset_msi_config;
461 }
462 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
463 ab->pci.msi.config = &msi_config_one_msi;
464 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n");
465 }
466 ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
467
468 ath11k_pci_msi_disable(ab_pci);
469
470 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
471 if (!msi_desc) {
472 ath11k_err(ab, "msi_desc is NULL!\n");
473 ret = -EINVAL;
474 goto free_msi_vector;
475 }
476
477 ab->pci.msi.ep_base_data = msi_desc->msg.data;
478
479 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
480 &ab->pci.msi.addr_lo);
481
482 if (msi_desc->pci.msi_attrib.is_64) {
483 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
484 &ab->pci.msi.addr_hi);
485 } else {
486 ab->pci.msi.addr_hi = 0;
487 }
488
489 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
490
491 return 0;
492
493 free_msi_vector:
494 pci_free_irq_vectors(ab_pci->pdev);
495
496 reset_msi_config:
497 return ret;
498 }
499
ath11k_pci_free_msi(struct ath11k_pci * ab_pci)500 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
501 {
502 pci_free_irq_vectors(ab_pci->pdev);
503 }
504
ath11k_pci_config_msi_data(struct ath11k_pci * ab_pci)505 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
506 {
507 struct msi_desc *msi_desc;
508
509 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
510 if (!msi_desc) {
511 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
512 pci_free_irq_vectors(ab_pci->pdev);
513 return -EINVAL;
514 }
515
516 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
517
518 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n",
519 ab_pci->ab->pci.msi.ep_base_data);
520
521 return 0;
522 }
523
ath11k_pci_claim(struct ath11k_pci * ab_pci,struct pci_dev * pdev)524 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
525 {
526 struct ath11k_base *ab = ab_pci->ab;
527 u16 device_id;
528 int ret = 0;
529
530 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
531 if (device_id != ab_pci->dev_id) {
532 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
533 device_id, ab_pci->dev_id);
534 ret = -EIO;
535 goto out;
536 }
537
538 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
539 if (ret) {
540 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
541 goto out;
542 }
543
544 ret = pci_enable_device(pdev);
545 if (ret) {
546 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
547 goto out;
548 }
549
550 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
551 if (ret) {
552 ath11k_err(ab, "failed to request pci region: %d\n", ret);
553 goto disable_device;
554 }
555
556 ret = dma_set_mask(&pdev->dev,
557 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
558 if (ret) {
559 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
560 ATH11K_PCI_DMA_MASK, ret);
561 goto release_region;
562 }
563
564 ab_pci->dma_mask = DMA_BIT_MASK(ATH11K_PCI_DMA_MASK);
565
566 ret = dma_set_coherent_mask(&pdev->dev,
567 DMA_BIT_MASK(ATH11K_PCI_COHERENT_DMA_MASK));
568 if (ret) {
569 ath11k_err(ab, "failed to set pci coherent dma mask to %d: %d\n",
570 ATH11K_PCI_COHERENT_DMA_MASK, ret);
571 goto release_region;
572 }
573
574 pci_set_master(pdev);
575
576 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
577 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
578 if (!ab->mem) {
579 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
580 ret = -EIO;
581 goto release_region;
582 }
583
584 ab->mem_ce = ab->mem;
585
586 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem);
587 return 0;
588
589 release_region:
590 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
591 disable_device:
592 pci_disable_device(pdev);
593 out:
594 return ret;
595 }
596
ath11k_pci_free_region(struct ath11k_pci * ab_pci)597 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
598 {
599 struct ath11k_base *ab = ab_pci->ab;
600 struct pci_dev *pci_dev = ab_pci->pdev;
601
602 pci_iounmap(pci_dev, ab->mem);
603 ab->mem = NULL;
604 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
605 if (pci_is_enabled(pci_dev))
606 pci_disable_device(pci_dev);
607 }
608
ath11k_pci_aspm_disable(struct ath11k_pci * ab_pci)609 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
610 {
611 struct ath11k_base *ab = ab_pci->ab;
612
613 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
614 &ab_pci->link_ctl);
615
616 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n",
617 ab_pci->link_ctl,
618 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
619 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
620
621 /* disable L0s and L1 */
622 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
623 PCI_EXP_LNKCTL_ASPMC);
624
625 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
626 }
627
ath11k_pci_aspm_restore(struct ath11k_pci * ab_pci)628 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
629 {
630 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
631 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
632 PCI_EXP_LNKCTL_ASPMC,
633 ab_pci->link_ctl &
634 PCI_EXP_LNKCTL_ASPMC);
635 }
636
637 #ifdef CONFIG_DEV_COREDUMP
ath11k_pci_coredump_calculate_size(struct ath11k_base * ab,u32 * dump_seg_sz)638 static int ath11k_pci_coredump_calculate_size(struct ath11k_base *ab, u32 *dump_seg_sz)
639 {
640 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
641 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
642 struct image_info *rddm_img, *fw_img;
643 struct ath11k_tlv_dump_data *dump_tlv;
644 enum ath11k_fw_crash_dump_type mem_type;
645 u32 len = 0, rddm_tlv_sz = 0, paging_tlv_sz = 0;
646 struct ath11k_dump_file_data *file_data;
647 int i;
648
649 rddm_img = mhi_ctrl->rddm_image;
650 if (!rddm_img) {
651 ath11k_err(ab, "No RDDM dump found\n");
652 return 0;
653 }
654
655 fw_img = mhi_ctrl->fbc_image;
656
657 for (i = 0; i < fw_img->entries ; i++) {
658 if (!fw_img->mhi_buf[i].buf)
659 continue;
660
661 paging_tlv_sz += fw_img->mhi_buf[i].len;
662 }
663 dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA] = paging_tlv_sz;
664
665 for (i = 0; i < rddm_img->entries; i++) {
666 if (!rddm_img->mhi_buf[i].buf)
667 continue;
668
669 rddm_tlv_sz += rddm_img->mhi_buf[i].len;
670 }
671 dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA] = rddm_tlv_sz;
672
673 for (i = 0; i < ab->qmi.mem_seg_count; i++) {
674 mem_type = ath11k_coredump_get_dump_type(ab->qmi.target_mem[i].type);
675
676 if (mem_type == FW_CRASH_DUMP_NONE)
677 continue;
678
679 if (mem_type == FW_CRASH_DUMP_TYPE_MAX) {
680 ath11k_dbg(ab, ATH11K_DBG_PCI,
681 "target mem region type %d not supported",
682 ab->qmi.target_mem[i].type);
683 continue;
684 }
685
686 if (!ab->qmi.target_mem[i].anyaddr)
687 continue;
688
689 dump_seg_sz[mem_type] += ab->qmi.target_mem[i].size;
690 }
691
692 for (i = 0; i < FW_CRASH_DUMP_TYPE_MAX; i++) {
693 if (!dump_seg_sz[i])
694 continue;
695
696 len += sizeof(*dump_tlv) + dump_seg_sz[i];
697 }
698
699 if (len)
700 len += sizeof(*file_data);
701
702 return len;
703 }
704
ath11k_pci_coredump_download(struct ath11k_base * ab)705 static void ath11k_pci_coredump_download(struct ath11k_base *ab)
706 {
707 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
708 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
709 struct image_info *rddm_img, *fw_img;
710 struct timespec64 timestamp;
711 int i, len, mem_idx;
712 enum ath11k_fw_crash_dump_type mem_type;
713 struct ath11k_dump_file_data *file_data;
714 struct ath11k_tlv_dump_data *dump_tlv;
715 size_t hdr_len = sizeof(*file_data);
716 void *buf;
717 u32 dump_seg_sz[FW_CRASH_DUMP_TYPE_MAX] = {};
718
719 ath11k_mhi_coredump(mhi_ctrl, false);
720
721 len = ath11k_pci_coredump_calculate_size(ab, dump_seg_sz);
722 if (!len) {
723 ath11k_warn(ab, "No crash dump data found for devcoredump");
724 return;
725 }
726
727 rddm_img = mhi_ctrl->rddm_image;
728 fw_img = mhi_ctrl->fbc_image;
729
730 /* dev_coredumpv() requires vmalloc data */
731 buf = vzalloc(len);
732 if (!buf)
733 return;
734
735 ab->dump_data = buf;
736 ab->ath11k_coredump_len = len;
737 file_data = ab->dump_data;
738 strscpy(file_data->df_magic, "ATH11K-FW-DUMP", sizeof(file_data->df_magic));
739 file_data->len = cpu_to_le32(len);
740 file_data->version = cpu_to_le32(ATH11K_FW_CRASH_DUMP_V2);
741 file_data->chip_id = cpu_to_le32(ab_pci->dev_id);
742 file_data->qrtr_id = cpu_to_le32(ab_pci->ab->qmi.service_ins_id);
743 file_data->bus_id = cpu_to_le32(pci_domain_nr(ab_pci->pdev->bus));
744 guid_gen(&file_data->guid);
745 ktime_get_real_ts64(×tamp);
746 file_data->tv_sec = cpu_to_le64(timestamp.tv_sec);
747 file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec);
748 buf += hdr_len;
749 dump_tlv = buf;
750 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_PAGING_DATA);
751 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA]);
752 buf += COREDUMP_TLV_HDR_SIZE;
753
754 /* append all segments together as they are all part of a single contiguous
755 * block of memory
756 */
757 for (i = 0; i < fw_img->entries ; i++) {
758 if (!fw_img->mhi_buf[i].buf)
759 continue;
760
761 memcpy_fromio(buf, (void const __iomem *)fw_img->mhi_buf[i].buf,
762 fw_img->mhi_buf[i].len);
763 buf += fw_img->mhi_buf[i].len;
764 }
765
766 dump_tlv = buf;
767 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_RDDM_DATA);
768 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA]);
769 buf += COREDUMP_TLV_HDR_SIZE;
770
771 /* append all segments together as they are all part of a single contiguous
772 * block of memory
773 */
774 for (i = 0; i < rddm_img->entries; i++) {
775 if (!rddm_img->mhi_buf[i].buf)
776 continue;
777
778 memcpy_fromio(buf, (void const __iomem *)rddm_img->mhi_buf[i].buf,
779 rddm_img->mhi_buf[i].len);
780 buf += rddm_img->mhi_buf[i].len;
781 }
782
783 mem_idx = FW_CRASH_DUMP_REMOTE_MEM_DATA;
784 for (; mem_idx < FW_CRASH_DUMP_TYPE_MAX; mem_idx++) {
785 if (mem_idx == FW_CRASH_DUMP_NONE)
786 continue;
787
788 for (i = 0; i < ab->qmi.mem_seg_count; i++) {
789 mem_type = ath11k_coredump_get_dump_type
790 (ab->qmi.target_mem[i].type);
791
792 if (mem_type != mem_idx)
793 continue;
794
795 if (!ab->qmi.target_mem[i].anyaddr) {
796 ath11k_dbg(ab, ATH11K_DBG_PCI,
797 "Skipping mem region type %d",
798 ab->qmi.target_mem[i].type);
799 continue;
800 }
801
802 dump_tlv = buf;
803 dump_tlv->type = cpu_to_le32(mem_idx);
804 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[mem_idx]);
805 buf += COREDUMP_TLV_HDR_SIZE;
806
807 memcpy_fromio(buf, ab->qmi.target_mem[i].iaddr,
808 ab->qmi.target_mem[i].size);
809
810 buf += ab->qmi.target_mem[i].size;
811 }
812 }
813
814 queue_work(ab->workqueue, &ab->dump_work);
815 }
816 #endif
817
ath11k_pci_power_up(struct ath11k_base * ab)818 static int ath11k_pci_power_up(struct ath11k_base *ab)
819 {
820 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
821 int ret;
822
823 ab_pci->register_window = 0;
824 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
825 ath11k_pci_sw_reset(ab_pci->ab, true);
826
827 /* Disable ASPM during firmware download due to problems switching
828 * to AMSS state.
829 */
830 ath11k_pci_aspm_disable(ab_pci);
831
832 ath11k_pci_msi_enable(ab_pci);
833
834 ret = ath11k_mhi_start(ab_pci);
835 if (ret) {
836 ath11k_err(ab, "failed to start mhi: %d\n", ret);
837 return ret;
838 }
839
840 if (ab->hw_params.static_window_map)
841 ath11k_pci_select_static_window(ab_pci);
842
843 return 0;
844 }
845
ath11k_pci_power_down(struct ath11k_base * ab,bool is_suspend)846 static void ath11k_pci_power_down(struct ath11k_base *ab, bool is_suspend)
847 {
848 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
849
850 /* restore aspm in case firmware bootup fails */
851 ath11k_pci_aspm_restore(ab_pci);
852
853 ath11k_pci_force_wake(ab_pci->ab);
854
855 ath11k_pci_msi_disable(ab_pci);
856
857 ath11k_mhi_stop(ab_pci, is_suspend);
858 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
859 ath11k_pci_sw_reset(ab_pci->ab, false);
860 }
861
ath11k_pci_hif_suspend(struct ath11k_base * ab)862 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
863 {
864 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
865
866 return ath11k_mhi_suspend(ar_pci);
867 }
868
ath11k_pci_hif_resume(struct ath11k_base * ab)869 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
870 {
871 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
872
873 return ath11k_mhi_resume(ar_pci);
874 }
875
ath11k_pci_hif_ce_irq_enable(struct ath11k_base * ab)876 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
877 {
878 ath11k_pcic_ce_irqs_enable(ab);
879 }
880
ath11k_pci_hif_ce_irq_disable(struct ath11k_base * ab)881 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
882 {
883 ath11k_pcic_ce_irq_disable_sync(ab);
884 }
885
ath11k_pci_start(struct ath11k_base * ab)886 static int ath11k_pci_start(struct ath11k_base *ab)
887 {
888 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
889
890 /* TODO: for now don't restore ASPM in case of single MSI
891 * vector as MHI register reading in M2 causes system hang.
892 */
893 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
894 ath11k_pci_aspm_restore(ab_pci);
895 else
896 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
897
898 ath11k_pcic_start(ab);
899
900 return 0;
901 }
902
903 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
904 .start = ath11k_pci_start,
905 .stop = ath11k_pcic_stop,
906 .read32 = ath11k_pcic_read32,
907 .write32 = ath11k_pcic_write32,
908 .read = ath11k_pcic_read,
909 .power_down = ath11k_pci_power_down,
910 .power_up = ath11k_pci_power_up,
911 .suspend = ath11k_pci_hif_suspend,
912 .resume = ath11k_pci_hif_resume,
913 .irq_enable = ath11k_pcic_ext_irq_enable,
914 .irq_disable = ath11k_pcic_ext_irq_disable,
915 .get_msi_address = ath11k_pcic_get_msi_address,
916 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
917 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
918 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
919 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
920 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
921 #ifdef CONFIG_DEV_COREDUMP
922 .coredump_download = ath11k_pci_coredump_download,
923 #endif
924 };
925
ath11k_pci_read_hw_version(struct ath11k_base * ab,u32 * major,u32 * minor)926 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
927 {
928 u32 soc_hw_version;
929
930 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
931 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
932 soc_hw_version);
933 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
934 soc_hw_version);
935
936 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n",
937 *major, *minor);
938 }
939
ath11k_pci_set_irq_affinity_hint(struct ath11k_pci * ab_pci,const struct cpumask * m)940 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
941 const struct cpumask *m)
942 {
943 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
944 return 0;
945
946 return irq_set_affinity_and_hint(ab_pci->pdev->irq, m);
947 }
948
ath11k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)949 static int ath11k_pci_probe(struct pci_dev *pdev,
950 const struct pci_device_id *pci_dev)
951 {
952 struct ath11k_base *ab;
953 struct ath11k_pci *ab_pci;
954 u32 soc_hw_version_major, soc_hw_version_minor;
955 int ret;
956 u32 sub_version;
957
958 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
959
960 if (!ab) {
961 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
962 return -ENOMEM;
963 }
964
965 ab->dev = &pdev->dev;
966 pci_set_drvdata(pdev, ab);
967 ab_pci = ath11k_pci_priv(ab);
968 ab_pci->dev_id = pci_dev->device;
969 ab_pci->ab = ab;
970 ab_pci->pdev = pdev;
971 ab->hif.ops = &ath11k_pci_hif_ops;
972 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
973 pci_set_drvdata(pdev, ab);
974 spin_lock_init(&ab_pci->window_lock);
975
976 /* Set fixed_mem_region to true for platforms support reserved memory
977 * from DT. If memory is reserved from DT for FW, ath11k driver need not
978 * allocate memory.
979 */
980 if (of_property_present(ab->dev->of_node, "memory-region"))
981 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
982
983 ret = ath11k_pci_claim(ab_pci, pdev);
984 if (ret) {
985 ath11k_err(ab, "failed to claim device: %d\n", ret);
986 goto err_free_core;
987 }
988
989 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
990 pdev->vendor, pdev->device,
991 pdev->subsystem_vendor, pdev->subsystem_device);
992
993 ab->id.vendor = pdev->vendor;
994 ab->id.device = pdev->device;
995 ab->id.subsystem_vendor = pdev->subsystem_vendor;
996 ab->id.subsystem_device = pdev->subsystem_device;
997
998 switch (pci_dev->device) {
999 case QCA6390_DEVICE_ID:
1000 ret = ath11k_pcic_register_pci_ops(ab, &ath11k_pci_ops_qca6390);
1001 if (ret) {
1002 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
1003 goto err_pci_free_region;
1004 }
1005
1006 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
1007 &soc_hw_version_minor);
1008 switch (soc_hw_version_major) {
1009 case 2:
1010 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
1011 break;
1012 default:
1013 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
1014 soc_hw_version_major, soc_hw_version_minor);
1015 ret = -EOPNOTSUPP;
1016 goto err_pci_free_region;
1017 }
1018
1019 break;
1020 case QCN9074_DEVICE_ID:
1021 ret = ath11k_pcic_register_pci_ops(ab, &ath11k_pci_ops_qcn9074);
1022 if (ret) {
1023 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
1024 goto err_pci_free_region;
1025 }
1026 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
1027 break;
1028 case WCN6855_DEVICE_ID:
1029 ret = ath11k_pcic_register_pci_ops(ab, &ath11k_pci_ops_qca6390);
1030 if (ret) {
1031 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
1032 goto err_pci_free_region;
1033 }
1034 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
1035 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
1036 &soc_hw_version_minor);
1037 switch (soc_hw_version_major) {
1038 case 2:
1039 switch (soc_hw_version_minor) {
1040 case 0x00:
1041 case 0x01:
1042 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
1043 break;
1044 case 0x10:
1045 case 0x11:
1046 sub_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_SUB_VER);
1047 ath11k_dbg(ab, ATH11K_DBG_PCI, "sub_version 0x%x\n",
1048 sub_version);
1049 switch (sub_version) {
1050 case 0x1019A0E1:
1051 case 0x1019B0E1:
1052 case 0x1019C0E1:
1053 case 0x1019D0E1:
1054 ab->hw_rev = ATH11K_HW_QCA2066_HW21;
1055 break;
1056 case 0x001e60e1:
1057 ab->hw_rev = ATH11K_HW_QCA6698AQ_HW21;
1058 break;
1059 default:
1060 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
1061 }
1062 break;
1063 default:
1064 goto unsupported_wcn6855_soc;
1065 }
1066 break;
1067 default:
1068 unsupported_wcn6855_soc:
1069 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
1070 soc_hw_version_major, soc_hw_version_minor);
1071 ret = -EOPNOTSUPP;
1072 goto err_pci_free_region;
1073 }
1074
1075 break;
1076 default:
1077 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1078 pci_dev->device);
1079 ret = -EOPNOTSUPP;
1080 goto err_pci_free_region;
1081 }
1082
1083 ret = ath11k_pcic_init_msi_config(ab);
1084 if (ret) {
1085 ath11k_err(ab, "failed to init msi config: %d\n", ret);
1086 goto err_pci_free_region;
1087 }
1088
1089 ret = ath11k_pci_alloc_msi(ab_pci);
1090 if (ret) {
1091 ath11k_err(ab, "failed to enable msi: %d\n", ret);
1092 goto err_pci_free_region;
1093 }
1094
1095 ret = ath11k_core_pre_init(ab);
1096 if (ret)
1097 goto err_pci_disable_msi;
1098
1099 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
1100 if (ret) {
1101 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
1102 goto err_pci_disable_msi;
1103 }
1104
1105 ret = ath11k_mhi_register(ab_pci);
1106 if (ret) {
1107 ath11k_err(ab, "failed to register mhi: %d\n", ret);
1108 goto err_irq_affinity_cleanup;
1109 }
1110
1111 ret = ath11k_hal_srng_init(ab);
1112 if (ret)
1113 goto err_mhi_unregister;
1114
1115 ret = ath11k_ce_alloc_pipes(ab);
1116 if (ret) {
1117 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1118 goto err_hal_srng_deinit;
1119 }
1120
1121 ath11k_pci_init_qmi_ce_config(ab);
1122
1123 ret = ath11k_pcic_config_irq(ab);
1124 if (ret) {
1125 ath11k_err(ab, "failed to config irq: %d\n", ret);
1126 goto err_ce_free;
1127 }
1128
1129 /* kernel may allocate a dummy vector before request_irq and
1130 * then allocate a real vector when request_irq is called.
1131 * So get msi_data here again to avoid spurious interrupt
1132 * as msi_data will configured to srngs.
1133 */
1134 ret = ath11k_pci_config_msi_data(ab_pci);
1135 if (ret) {
1136 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
1137 goto err_free_irq;
1138 }
1139
1140 ret = ath11k_core_init(ab);
1141 if (ret) {
1142 ath11k_err(ab, "failed to init core: %d\n", ret);
1143 goto err_free_irq;
1144 }
1145 ath11k_qmi_fwreset_from_cold_boot(ab);
1146 return 0;
1147
1148 err_free_irq:
1149 /* __free_irq() expects the caller to have cleared the affinity hint */
1150 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
1151 ath11k_pcic_free_irq(ab);
1152
1153 err_ce_free:
1154 ath11k_ce_free_pipes(ab);
1155
1156 err_hal_srng_deinit:
1157 ath11k_hal_srng_deinit(ab);
1158
1159 err_mhi_unregister:
1160 ath11k_mhi_unregister(ab_pci);
1161
1162 err_irq_affinity_cleanup:
1163 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
1164
1165 err_pci_disable_msi:
1166 ath11k_pci_free_msi(ab_pci);
1167
1168 err_pci_free_region:
1169 ath11k_pci_free_region(ab_pci);
1170
1171 err_free_core:
1172 ath11k_core_free(ab);
1173
1174 return ret;
1175 }
1176
ath11k_pci_remove(struct pci_dev * pdev)1177 static void ath11k_pci_remove(struct pci_dev *pdev)
1178 {
1179 struct ath11k_base *ab = pci_get_drvdata(pdev);
1180 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1181
1182 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
1183
1184 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1185 ath11k_pci_power_down(ab, false);
1186 ath11k_debugfs_soc_destroy(ab);
1187 ath11k_qmi_deinit_service(ab);
1188 ath11k_core_pm_notifier_unregister(ab);
1189 goto qmi_fail;
1190 }
1191
1192 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
1193
1194 cancel_work_sync(&ab->reset_work);
1195 cancel_work_sync(&ab->dump_work);
1196 ath11k_core_deinit(ab);
1197
1198 qmi_fail:
1199 ath11k_fw_destroy(ab);
1200 ath11k_mhi_unregister(ab_pci);
1201
1202 ath11k_pcic_free_irq(ab);
1203 ath11k_pci_free_msi(ab_pci);
1204 ath11k_pci_free_region(ab_pci);
1205
1206 ath11k_hal_srng_deinit(ab);
1207 ath11k_ce_free_pipes(ab);
1208 ath11k_core_free(ab);
1209 }
1210
ath11k_pci_shutdown(struct pci_dev * pdev)1211 static void ath11k_pci_shutdown(struct pci_dev *pdev)
1212 {
1213 struct ath11k_base *ab = pci_get_drvdata(pdev);
1214 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1215
1216 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
1217
1218 spin_lock_bh(&ab->base_lock);
1219 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
1220 spin_unlock_bh(&ab->base_lock);
1221
1222 cancel_work_sync(&ab->reset_work);
1223 cancel_work_sync(&ab->dump_work);
1224
1225 ath11k_pci_power_down(ab, false);
1226 }
1227
ath11k_pci_pm_suspend(struct device * dev)1228 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
1229 {
1230 struct ath11k_base *ab = dev_get_drvdata(dev);
1231 int ret;
1232
1233 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1234 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
1235 return 0;
1236 }
1237
1238 ret = ath11k_core_suspend(ab);
1239 if (ret)
1240 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
1241
1242 return 0;
1243 }
1244
ath11k_pci_pm_resume(struct device * dev)1245 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
1246 {
1247 struct ath11k_base *ab = dev_get_drvdata(dev);
1248 int ret;
1249
1250 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1251 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
1252 return 0;
1253 }
1254
1255 ret = ath11k_core_resume(ab);
1256 if (ret)
1257 ath11k_warn(ab, "failed to resume core: %d\n", ret);
1258
1259 return ret;
1260 }
1261
ath11k_pci_pm_suspend_late(struct device * dev)1262 static __maybe_unused int ath11k_pci_pm_suspend_late(struct device *dev)
1263 {
1264 struct ath11k_base *ab = dev_get_drvdata(dev);
1265 int ret;
1266
1267 ret = ath11k_core_suspend_late(ab);
1268 if (ret)
1269 ath11k_warn(ab, "failed to late suspend core: %d\n", ret);
1270
1271 /* Similar to ath11k_pci_pm_suspend(), we return success here
1272 * even error happens, to allow system suspend/hibernation survive.
1273 */
1274 return 0;
1275 }
1276
ath11k_pci_pm_resume_early(struct device * dev)1277 static __maybe_unused int ath11k_pci_pm_resume_early(struct device *dev)
1278 {
1279 struct ath11k_base *ab = dev_get_drvdata(dev);
1280 int ret;
1281
1282 ret = ath11k_core_resume_early(ab);
1283 if (ret)
1284 ath11k_warn(ab, "failed to early resume core: %d\n", ret);
1285
1286 return ret;
1287 }
1288
1289 static const struct dev_pm_ops __maybe_unused ath11k_pci_pm_ops = {
1290 SET_SYSTEM_SLEEP_PM_OPS(ath11k_pci_pm_suspend,
1291 ath11k_pci_pm_resume)
1292 SET_LATE_SYSTEM_SLEEP_PM_OPS(ath11k_pci_pm_suspend_late,
1293 ath11k_pci_pm_resume_early)
1294 };
1295
1296 static struct pci_driver ath11k_pci_driver = {
1297 .name = "ath11k_pci",
1298 .id_table = ath11k_pci_id_table,
1299 .probe = ath11k_pci_probe,
1300 .remove = ath11k_pci_remove,
1301 .shutdown = ath11k_pci_shutdown,
1302 #ifdef CONFIG_PM
1303 .driver.pm = &ath11k_pci_pm_ops,
1304 #endif
1305 };
1306
ath11k_pci_init(void)1307 static int ath11k_pci_init(void)
1308 {
1309 int ret;
1310
1311 ret = pci_register_driver(&ath11k_pci_driver);
1312 if (ret)
1313 pr_err("failed to register ath11k pci driver: %d\n",
1314 ret);
1315
1316 return ret;
1317 }
1318 module_init(ath11k_pci_init);
1319
ath11k_pci_exit(void)1320 static void ath11k_pci_exit(void)
1321 {
1322 pci_unregister_driver(&ath11k_pci_driver);
1323 }
1324
1325 module_exit(ath11k_pci_exit);
1326
1327 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11ax WLAN devices");
1328 MODULE_LICENSE("Dual BSD/GPL");
1329
1330 /* firmware files */
1331 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*");
1332 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*");
1333 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*");
1334 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*");
1335