1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI SN65DSI83,84,85 driver
4 *
5 * Currently supported:
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
15 * (should be easy to add by someone who has the HW)
16 * - SN65DSI85
17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
18 * - Unsupported
19 * (should be easy to add by someone who has the HW)
20 *
21 * Copyright (C) 2021 Marek Vasut <marex@denx.de>
22 *
23 * Based on previous work of:
24 * Valentin Raevsky <valentin@compulab.co.il>
25 * Philippe Schenker <philippe.schenker@toradex.com>
26 */
27
28 #include <linux/bits.h>
29 #include <linux/clk.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/i2c.h>
32 #include <linux/media-bus-format.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_graph.h>
36 #include <linux/regmap.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/timer.h>
39 #include <linux/workqueue.h>
40
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_bridge.h>
43 #include <drm/drm_bridge_helper.h>
44 #include <drm/drm_mipi_dsi.h>
45 #include <drm/drm_of.h>
46 #include <drm/drm_print.h>
47 #include <drm/drm_probe_helper.h>
48
49 /* ID registers */
50 #define REG_ID(n) (0x00 + (n))
51 /* Reset and clock registers */
52 #define REG_RC_RESET 0x09
53 #define REG_RC_RESET_SOFT_RESET BIT(0)
54 #define REG_RC_LVDS_PLL 0x0a
55 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7)
56 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1)
57 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0)
58 #define REG_RC_DSI_CLK 0x0b
59 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3)
60 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3)
61 #define REG_RC_PLL_EN 0x0d
62 #define REG_RC_PLL_EN_PLL_EN BIT(0)
63 /* DSI registers */
64 #define REG_DSI_LANE 0x10
65 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */
66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */
67 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */
68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5)
69 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3)
70 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1)
71 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0)
72 #define REG_DSI_EQ 0x11
73 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6)
74 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2)
75 #define REG_DSI_CLK 0x12
76 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff)
77 /* LVDS registers */
78 #define REG_LVDS_FMT 0x18
79 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7)
80 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6)
81 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5)
82 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */
83 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3)
84 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2)
85 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1)
86 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0)
87 #define REG_LVDS_VCOM 0x19
88 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6)
89 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4)
90 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2)
91 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3)
92 #define REG_LVDS_LANE 0x1a
93 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6)
94 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5)
95 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4)
96 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1)
97 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0)
98 #define REG_LVDS_CM 0x1b
99 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4)
100 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3)
101 /* Video registers */
102 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20
103 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21
104 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24
105 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25
106 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28
107 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29
108 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c
109 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d
110 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
111 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
112 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34
113 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36
114 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38
115 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a
116 #define REG_VID_CHA_TEST_PATTERN 0x3c
117 #define REG_VID_CHA_TEST_PATTERN_EN BIT(4)
118 /* IRQ registers */
119 #define REG_IRQ_GLOBAL 0xe0
120 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0)
121 #define REG_IRQ_EN 0xe1
122 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7)
123 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6)
124 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5)
125 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4)
126 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3)
127 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2)
128 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0)
129 #define REG_IRQ_STAT 0xe5
130 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7)
131 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6)
132 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5)
133 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4)
134 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3)
135 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2)
136 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0)
137
138 static bool sn65dsi83_test_pattern;
139 module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644);
140
141 enum sn65dsi83_channel {
142 CHANNEL_A,
143 CHANNEL_B
144 };
145
146 enum sn65dsi83_lvds_term {
147 OHM_100,
148 OHM_200
149 };
150
151 enum sn65dsi83_model {
152 MODEL_SN65DSI83,
153 MODEL_SN65DSI84,
154 };
155
156 struct sn65dsi83 {
157 struct drm_bridge bridge;
158 struct device *dev;
159 struct regmap *regmap;
160 struct mipi_dsi_device *dsi;
161 struct drm_bridge *panel_bridge;
162 struct gpio_desc *enable_gpio;
163 struct regulator *vcc;
164 bool lvds_dual_link;
165 bool lvds_dual_link_even_odd_swap;
166 int lvds_vod_swing_conf[2];
167 int lvds_term_conf[2];
168 int irq;
169 struct delayed_work monitor_work;
170 struct work_struct reset_work;
171 };
172
173 static const struct regmap_range sn65dsi83_readable_ranges[] = {
174 regmap_reg_range(REG_ID(0), REG_ID(8)),
175 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
176 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
177 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
178 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
179 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
180 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
181 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
182 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
183 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
184 REG_VID_CHA_SYNC_DELAY_HIGH),
185 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
186 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
187 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
188 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
190 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
191 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
192 REG_VID_CHA_VERTICAL_BACK_PORCH),
193 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
194 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
195 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
196 REG_VID_CHA_VERTICAL_FRONT_PORCH),
197 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
198 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
199 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
200 };
201
202 static const struct regmap_access_table sn65dsi83_readable_table = {
203 .yes_ranges = sn65dsi83_readable_ranges,
204 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
205 };
206
207 static const struct regmap_range sn65dsi83_writeable_ranges[] = {
208 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
209 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
210 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
211 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
212 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
213 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
214 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
215 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
216 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
217 REG_VID_CHA_SYNC_DELAY_HIGH),
218 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
219 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
220 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
221 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
223 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
224 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
225 REG_VID_CHA_VERTICAL_BACK_PORCH),
226 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
227 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
228 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
229 REG_VID_CHA_VERTICAL_FRONT_PORCH),
230 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
231 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
232 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
233 };
234
235 static const struct regmap_access_table sn65dsi83_writeable_table = {
236 .yes_ranges = sn65dsi83_writeable_ranges,
237 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
238 };
239
240 static const struct regmap_range sn65dsi83_volatile_ranges[] = {
241 regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
242 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
243 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
244 };
245
246 static const struct regmap_access_table sn65dsi83_volatile_table = {
247 .yes_ranges = sn65dsi83_volatile_ranges,
248 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
249 };
250
251 static const struct regmap_config sn65dsi83_regmap_config = {
252 .reg_bits = 8,
253 .val_bits = 8,
254 .rd_table = &sn65dsi83_readable_table,
255 .wr_table = &sn65dsi83_writeable_table,
256 .volatile_table = &sn65dsi83_volatile_table,
257 .cache_type = REGCACHE_MAPLE,
258 .max_register = REG_IRQ_STAT,
259 };
260
261 static const int lvds_vod_swing_data_table[2][4][2] = {
262 { /* 100 Ohm */
263 { 180000, 313000 },
264 { 215000, 372000 },
265 { 250000, 430000 },
266 { 290000, 488000 },
267 },
268 { /* 200 Ohm */
269 { 150000, 261000 },
270 { 200000, 346000 },
271 { 250000, 428000 },
272 { 300000, 511000 },
273 },
274 };
275
276 static const int lvds_vod_swing_clock_table[2][4][2] = {
277 { /* 100 Ohm */
278 { 140000, 244000 },
279 { 168000, 290000 },
280 { 195000, 335000 },
281 { 226000, 381000 },
282 },
283 { /* 200 Ohm */
284 { 117000, 204000 },
285 { 156000, 270000 },
286 { 195000, 334000 },
287 { 234000, 399000 },
288 },
289 };
290
bridge_to_sn65dsi83(struct drm_bridge * bridge)291 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
292 {
293 return container_of(bridge, struct sn65dsi83, bridge);
294 }
295
sn65dsi83_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)296 static int sn65dsi83_attach(struct drm_bridge *bridge,
297 struct drm_encoder *encoder,
298 enum drm_bridge_attach_flags flags)
299 {
300 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
301
302 return drm_bridge_attach(encoder, ctx->panel_bridge,
303 &ctx->bridge, flags);
304 }
305
sn65dsi83_detach(struct drm_bridge * bridge)306 static void sn65dsi83_detach(struct drm_bridge *bridge)
307 {
308 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
309
310 if (!ctx->dsi)
311 return;
312
313 ctx->dsi = NULL;
314 }
315
sn65dsi83_get_lvds_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)316 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
317 const struct drm_display_mode *mode)
318 {
319 /*
320 * The encoding of the LVDS_CLK_RANGE is as follows:
321 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
322 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
323 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
324 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
325 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
326 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
327 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
328 * the ends of the ranges are clamped to the supported range. Since
329 * sn65dsi83_mode_valid() already filters the valid modes and limits
330 * the clock to 25..154 MHz, the range calculation can be simplified
331 * as follows:
332 */
333 int mode_clock = mode->clock;
334
335 if (ctx->lvds_dual_link)
336 mode_clock /= 2;
337
338 return (mode_clock - 12500) / 25000;
339 }
340
sn65dsi83_get_dsi_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)341 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
342 const struct drm_display_mode *mode)
343 {
344 /*
345 * The encoding of the CHA_DSI_CLK_RANGE is as follows:
346 * 0x00 through 0x07 - Reserved
347 * 0x08 - 40 <= DSI_CLK < 45 MHz
348 * 0x09 - 45 <= DSI_CLK < 50 MHz
349 * ...
350 * 0x63 - 495 <= DSI_CLK < 500 MHz
351 * 0x64 - 500 MHz
352 * 0x65 through 0xFF - Reserved
353 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
354 * The DSI clock are calculated as:
355 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
356 * the 2 is there because the bus is DDR.
357 */
358 return clamp((unsigned int)mode->clock *
359 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
360 ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U;
361 }
362
sn65dsi83_get_dsi_div(struct sn65dsi83 * ctx)363 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
364 {
365 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
366 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
367
368 dsi_div /= ctx->dsi->lanes;
369
370 if (!ctx->lvds_dual_link)
371 dsi_div /= 2;
372
373 return dsi_div - 1;
374 }
375
sn65dsi83_reset_pipe(struct sn65dsi83 * sn65dsi83)376 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83)
377 {
378 struct drm_modeset_acquire_ctx ctx;
379 int err;
380
381 /*
382 * Reset active outputs of the related CRTC.
383 *
384 * This way, drm core will reconfigure each components in the CRTC
385 * outputs path. In our case, this will force the previous component to
386 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83
387 * bridge.
388 *
389 * Keep the lock during the whole operation to be atomic.
390 */
391
392 drm_modeset_acquire_init(&ctx, 0);
393
394 dev_warn(sn65dsi83->dev, "reset the pipe\n");
395
396 retry:
397 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx);
398 if (err == -EDEADLK) {
399 drm_modeset_backoff(&ctx);
400 goto retry;
401 }
402
403 drm_modeset_drop_locks(&ctx);
404 drm_modeset_acquire_fini(&ctx);
405
406 return err;
407 }
408
sn65dsi83_reset_work(struct work_struct * ws)409 static void sn65dsi83_reset_work(struct work_struct *ws)
410 {
411 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work);
412 int ret;
413 int idx;
414
415 if (!drm_bridge_enter(&ctx->bridge, &idx))
416 return;
417
418 /* Reset the pipe */
419 ret = sn65dsi83_reset_pipe(ctx);
420 if (ret) {
421 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret));
422 goto bridge_exit;
423 }
424
425 if (ctx->irq)
426 enable_irq(ctx->irq);
427
428 bridge_exit:
429 drm_bridge_exit(idx);
430 }
431
sn65dsi83_handle_errors(struct sn65dsi83 * ctx)432 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx)
433 {
434 unsigned int irq_stat;
435 int ret;
436 int idx;
437
438 if (!drm_bridge_enter(&ctx->bridge, &idx))
439 return;
440
441 /*
442 * Schedule a reset in case of:
443 * - the bridge doesn't answer
444 * - the bridge signals an error
445 */
446
447 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat);
448
449 /*
450 * Some hardware (Toradex Verdin AM62) is known to report the
451 * PLL_UNLOCK error interrupt while working without visible
452 * problems. In lack of a reliable way to discriminate such cases
453 * from user-visible PLL_UNLOCK cases, ignore that bit entirely.
454 */
455 if (ret || irq_stat & ~REG_IRQ_STAT_CHA_PLL_UNLOCK) {
456 /*
457 * IRQ acknowledged is not always possible (the bridge can be in
458 * a state where it doesn't answer anymore). To prevent an
459 * interrupt storm, disable interrupt. The interrupt will be
460 * after the reset.
461 */
462 if (ctx->irq)
463 disable_irq_nosync(ctx->irq);
464
465 schedule_work(&ctx->reset_work);
466 }
467
468 drm_bridge_exit(idx);
469 }
470
sn65dsi83_monitor_work(struct work_struct * work)471 static void sn65dsi83_monitor_work(struct work_struct *work)
472 {
473 struct sn65dsi83 *ctx = container_of(to_delayed_work(work),
474 struct sn65dsi83, monitor_work);
475
476 sn65dsi83_handle_errors(ctx);
477
478 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
479 }
480
sn65dsi83_monitor_start(struct sn65dsi83 * ctx)481 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx)
482 {
483 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
484 }
485
sn65dsi83_monitor_stop(struct sn65dsi83 * ctx)486 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx)
487 {
488 cancel_delayed_work_sync(&ctx->monitor_work);
489 }
490
491 /*
492 * Release resources taken by sn65dsi83_atomic_pre_enable().
493 *
494 * Invoked by sn65dsi83_atomic_disable() normally, or by devres after
495 * sn65dsi83_remove() in case this happens befora atomic_disable.
496 */
sn65dsi83_release_resources(void * data)497 static void sn65dsi83_release_resources(void *data)
498 {
499 struct sn65dsi83 *ctx = (struct sn65dsi83 *)data;
500 int ret;
501
502 if (ctx->irq) {
503 /* Disable irq */
504 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0);
505 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0);
506 } else {
507 /* Stop the polling task */
508 sn65dsi83_monitor_stop(ctx);
509 }
510
511 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
512 gpiod_set_value_cansleep(ctx->enable_gpio, 0);
513 usleep_range(10000, 11000);
514
515 ret = regulator_disable(ctx->vcc);
516 if (ret)
517 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
518
519 regcache_mark_dirty(ctx->regmap);
520 }
521
sn65dsi83_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_commit * state)522 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
523 struct drm_atomic_commit *state)
524 {
525 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
526 const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1;
527 const struct drm_bridge_state *bridge_state;
528 const struct drm_crtc_state *crtc_state;
529 const struct drm_display_mode *mode;
530 struct drm_connector *connector;
531 struct drm_crtc *crtc;
532 bool test_pattern = sn65dsi83_test_pattern;
533 bool lvds_format_24bpp;
534 bool lvds_format_jeida;
535 unsigned int pval;
536 __le16 le16val;
537 u16 val;
538 int ret;
539 int idx;
540
541 if (!drm_bridge_enter(bridge, &idx))
542 return;
543
544 ret = regulator_enable(ctx->vcc);
545 if (ret) {
546 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret);
547 goto err_exit;
548 }
549
550 /* Deassert reset */
551 gpiod_set_value_cansleep(ctx->enable_gpio, 1);
552 usleep_range(10000, 11000);
553
554 /* Get the LVDS format from the bridge state. */
555 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
556
557 switch (bridge_state->output_bus_cfg.format) {
558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
559 lvds_format_24bpp = false;
560 lvds_format_jeida = true;
561 break;
562 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
563 lvds_format_24bpp = true;
564 lvds_format_jeida = true;
565 break;
566 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
567 lvds_format_24bpp = true;
568 lvds_format_jeida = false;
569 break;
570 default:
571 /*
572 * Some bridges still don't set the correct
573 * LVDS bus pixel format, use SPWG24 default
574 * format until those are fixed.
575 */
576 lvds_format_24bpp = true;
577 lvds_format_jeida = false;
578 dev_warn(ctx->dev,
579 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
580 bridge_state->output_bus_cfg.format);
581 break;
582 }
583
584 /*
585 * Retrieve the CRTC adjusted mode. This requires a little dance to go
586 * from the bridge to the encoder, to the connector and to the CRTC.
587 */
588 connector = drm_atomic_get_new_connector_for_encoder(state,
589 bridge->encoder);
590 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
591 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
592 mode = &crtc_state->adjusted_mode;
593
594 /* Clear reset, disable PLL */
595 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
596 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
597
598 /* Reference clock derived from DSI link clock. */
599 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
600 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
601 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
602 regmap_write(ctx->regmap, REG_DSI_CLK,
603 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
604 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
605 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
606
607 /* Set number of DSI lanes and LVDS link config. */
608 regmap_write(ctx->regmap, REG_DSI_LANE,
609 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
610 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) |
611 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
612 REG_DSI_LANE_CHB_DSI_LANES(3));
613 /* No equalization. */
614 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
615
616 /* Set up sync signal polarity. */
617 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
618 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
619 (mode->flags & DRM_MODE_FLAG_NVSYNC ?
620 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
621 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ?
622 REG_LVDS_FMT_DE_NEG_POLARITY : 0;
623
624 /* Set up bits-per-pixel, 18bpp or 24bpp. */
625 if (lvds_format_24bpp) {
626 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
627 if (ctx->lvds_dual_link)
628 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
629 }
630
631 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
632 if (lvds_format_jeida) {
633 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
634 if (ctx->lvds_dual_link)
635 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
636 }
637
638 /* Set up LVDS output config (DSI84,DSI85) */
639 if (!ctx->lvds_dual_link)
640 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
641
642 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
643 regmap_write(ctx->regmap, REG_LVDS_VCOM,
644 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) |
645 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B]));
646 regmap_write(ctx->regmap, REG_LVDS_LANE,
647 (ctx->lvds_dual_link_even_odd_swap ?
648 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
649 (ctx->lvds_term_conf[CHANNEL_A] ?
650 REG_LVDS_LANE_CHA_LVDS_TERM : 0) |
651 (ctx->lvds_term_conf[CHANNEL_B] ?
652 REG_LVDS_LANE_CHB_LVDS_TERM : 0));
653 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
654
655 /*
656 * Active line length needs to be halved for test pattern
657 * generation in dual LVDS output.
658 */
659 le16val = cpu_to_le16(mode->hdisplay / (test_pattern ? dual_factor : 1));
660 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
661 &le16val, 2);
662 le16val = cpu_to_le16(mode->vdisplay);
663 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
664 &le16val, 2);
665 /* 32 + 1 pixel clock to ensure proper operation */
666 le16val = cpu_to_le16(32 + 1);
667 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
668 le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_factor);
669 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
670 &le16val, 2);
671 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
672 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
673 &le16val, 2);
674 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
675 (mode->htotal - mode->hsync_end) / dual_factor);
676 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
677 mode->vtotal - mode->vsync_end);
678 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
679 (mode->hsync_start - mode->hdisplay) / dual_factor);
680 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
681 mode->vsync_start - mode->vdisplay);
682 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN,
683 test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0);
684
685 /* Enable PLL */
686 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
687 usleep_range(3000, 4000);
688 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
689 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
690 1000, 100000);
691 if (ret) {
692 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
693 /* On failure, disable PLL again and exit. */
694 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
695 goto err_add_action;
696 }
697
698 /* Trigger reset after CSR register update. */
699 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
700
701 /* Wait for 10ms after soft reset as specified in datasheet */
702 usleep_range(10000, 12000);
703
704 err_add_action:
705 devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx);
706 err_exit:
707 drm_bridge_exit(idx);
708 }
709
sn65dsi83_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_commit * state)710 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
711 struct drm_atomic_commit *state)
712 {
713 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
714 unsigned int pval;
715 int idx;
716
717 if (!drm_bridge_enter(bridge, &idx))
718 return;
719
720 /* Clear all errors that got asserted during initialization. */
721 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
722 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
723
724 /* Wait for 1ms and check for errors in status register */
725 usleep_range(1000, 1100);
726 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
727 if (pval)
728 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval);
729
730 if (ctx->irq) {
731 /* Enable irq to detect errors */
732 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN);
733 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff & ~REG_IRQ_EN_CHA_PLL_UNLOCK_EN);
734 } else {
735 /* Use the polling task */
736 sn65dsi83_monitor_start(ctx);
737 }
738
739 drm_bridge_exit(idx);
740 }
741
sn65dsi83_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_commit * state)742 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
743 struct drm_atomic_commit *state)
744 {
745 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
746 int idx;
747
748 if (!drm_bridge_enter(bridge, &idx))
749 return;
750
751 devm_release_action(ctx->dev, sn65dsi83_release_resources, ctx);
752
753 drm_bridge_exit(idx);
754 }
755
756 static enum drm_mode_status
sn65dsi83_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)757 sn65dsi83_mode_valid(struct drm_bridge *bridge,
758 const struct drm_display_info *info,
759 const struct drm_display_mode *mode)
760 {
761 /* LVDS output clock range 25..154 MHz */
762 if (mode->clock < 25000)
763 return MODE_CLOCK_LOW;
764 if (mode->clock > 154000)
765 return MODE_CLOCK_HIGH;
766
767 return MODE_OK;
768 }
769
770 #define MAX_INPUT_SEL_FORMATS 1
771
772 static u32 *
sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)773 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
774 struct drm_bridge_state *bridge_state,
775 struct drm_crtc_state *crtc_state,
776 struct drm_connector_state *conn_state,
777 u32 output_fmt,
778 unsigned int *num_input_fmts)
779 {
780 u32 *input_fmts;
781
782 *num_input_fmts = 0;
783
784 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
785 GFP_KERNEL);
786 if (!input_fmts)
787 return NULL;
788
789 /* This is the DSI-end bus format */
790 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
791 *num_input_fmts = 1;
792
793 return input_fmts;
794 }
795
796 static const struct drm_bridge_funcs sn65dsi83_funcs = {
797 .attach = sn65dsi83_attach,
798 .detach = sn65dsi83_detach,
799 .atomic_enable = sn65dsi83_atomic_enable,
800 .atomic_pre_enable = sn65dsi83_atomic_pre_enable,
801 .atomic_disable = sn65dsi83_atomic_disable,
802 .mode_valid = sn65dsi83_mode_valid,
803
804 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
805 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
806 .atomic_create_state = drm_atomic_helper_bridge_create_state,
807 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
808 };
809
sn65dsi83_select_lvds_vod_swing(struct device * dev,u32 lvds_vod_swing_data[2],u32 lvds_vod_swing_clk[2],u8 lvds_term)810 static int sn65dsi83_select_lvds_vod_swing(struct device *dev,
811 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term)
812 {
813 int i;
814
815 for (i = 0; i <= 3; i++) {
816 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] &&
817 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] &&
818 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] &&
819 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1])
820 return i;
821 }
822
823 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n");
824 return -EINVAL;
825 }
826
sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 * ctx,int channel)827 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
828 {
829 struct device *dev = ctx->dev;
830 struct device_node *endpoint;
831 int endpoint_reg;
832 /* Set so the property can be freely selected if not defined */
833 u32 lvds_vod_swing_data[2] = { 0, 1000000 };
834 u32 lvds_vod_swing_clk[2] = { 0, 1000000 };
835 /* Set default near end terminataion to 200 Ohm */
836 u32 lvds_term = 200;
837 int lvds_vod_swing_conf;
838 int ret = 0;
839 int ret_data;
840 int ret_clock;
841
842 if (channel == CHANNEL_A)
843 endpoint_reg = 2;
844 else
845 endpoint_reg = 3;
846
847 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1);
848
849 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term);
850 if (lvds_term == 100)
851 ctx->lvds_term_conf[channel] = OHM_100;
852 else if (lvds_term == 200)
853 ctx->lvds_term_conf[channel] = OHM_200;
854 else {
855 ret = -EINVAL;
856 goto exit;
857 }
858
859 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt",
860 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data));
861 if (ret_data != 0 && ret_data != -EINVAL) {
862 ret = ret_data;
863 goto exit;
864 }
865
866 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt",
867 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk));
868 if (ret_clock != 0 && ret_clock != -EINVAL) {
869 ret = ret_clock;
870 goto exit;
871 }
872
873 /* Use default value if both properties are NOT defined. */
874 if (ret_data == -EINVAL && ret_clock == -EINVAL)
875 lvds_vod_swing_conf = 0x1;
876
877 /* Use lookup table if any of the two properties is defined. */
878 if (!ret_data || !ret_clock) {
879 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data,
880 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]);
881 if (lvds_vod_swing_conf < 0) {
882 ret = lvds_vod_swing_conf;
883 goto exit;
884 }
885 }
886
887 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf;
888 ret = 0;
889 exit:
890 of_node_put(endpoint);
891 return ret;
892 }
893
sn65dsi83_parse_dt(struct sn65dsi83 * ctx,enum sn65dsi83_model model)894 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
895 {
896 struct drm_bridge *panel_bridge;
897 struct device *dev = ctx->dev;
898 int ret;
899
900 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A);
901 if (ret < 0)
902 return ret;
903
904 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B);
905 if (ret < 0)
906 return ret;
907
908 ctx->lvds_dual_link = false;
909 ctx->lvds_dual_link_even_odd_swap = false;
910 if (model != MODEL_SN65DSI83) {
911 struct device_node *port2, *port3;
912 int dual_link;
913
914 port2 = of_graph_get_port_by_id(dev->of_node, 2);
915 port3 = of_graph_get_port_by_id(dev->of_node, 3);
916 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
917 of_node_put(port2);
918 of_node_put(port3);
919
920 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
921 ctx->lvds_dual_link = true;
922 /* Odd pixels to LVDS Channel A, even pixels to B */
923 ctx->lvds_dual_link_even_odd_swap = false;
924 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
925 ctx->lvds_dual_link = true;
926 /* Even pixels to LVDS Channel A, odd pixels to B */
927 ctx->lvds_dual_link_even_odd_swap = true;
928 }
929 }
930
931 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
932 if (IS_ERR(panel_bridge))
933 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n");
934
935 ctx->panel_bridge = panel_bridge;
936
937 ctx->vcc = devm_regulator_get(dev, "vcc");
938 if (IS_ERR(ctx->vcc))
939 return dev_err_probe(dev, PTR_ERR(ctx->vcc),
940 "Failed to get supply 'vcc'\n");
941
942 return 0;
943 }
944
sn65dsi83_host_attach(struct sn65dsi83 * ctx)945 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
946 {
947 struct device *dev = ctx->dev;
948 struct device_node *host_node;
949 struct device_node *endpoint;
950 struct mipi_dsi_device *dsi;
951 struct mipi_dsi_host *host;
952 const struct mipi_dsi_device_info info = {
953 .type = "sn65dsi83",
954 .channel = 0,
955 .node = NULL,
956 };
957 int dsi_lanes, ret;
958
959 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
960 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
961 host_node = of_graph_get_remote_port_parent(endpoint);
962 host = of_find_mipi_dsi_host_by_node(host_node);
963 of_node_put(host_node);
964 of_node_put(endpoint);
965
966 if (!host)
967 return -EPROBE_DEFER;
968
969 if (dsi_lanes < 0)
970 return dsi_lanes;
971
972 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
973 if (IS_ERR(dsi))
974 return dev_err_probe(dev, PTR_ERR(dsi),
975 "failed to create dsi device\n");
976
977 ctx->dsi = dsi;
978
979 dsi->lanes = dsi_lanes;
980 dsi->format = MIPI_DSI_FMT_RGB888;
981 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
982 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET;
983
984 ret = devm_mipi_dsi_attach(dev, dsi);
985 if (ret < 0) {
986 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
987 return ret;
988 }
989
990 return 0;
991 }
992
sn65dsi83_irq(int irq,void * data)993 static irqreturn_t sn65dsi83_irq(int irq, void *data)
994 {
995 struct sn65dsi83 *ctx = data;
996
997 sn65dsi83_handle_errors(ctx);
998 return IRQ_HANDLED;
999 }
1000
sn65dsi83_probe(struct i2c_client * client)1001 static int sn65dsi83_probe(struct i2c_client *client)
1002 {
1003 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1004 struct device *dev = &client->dev;
1005 enum sn65dsi83_model model;
1006 struct sn65dsi83 *ctx;
1007 int ret;
1008
1009 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs);
1010 if (IS_ERR(ctx))
1011 return PTR_ERR(ctx);
1012
1013 ctx->dev = dev;
1014 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work);
1015 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work);
1016
1017 if (dev->of_node) {
1018 model = (enum sn65dsi83_model)(uintptr_t)
1019 of_device_get_match_data(dev);
1020 } else {
1021 model = id->driver_data;
1022 }
1023
1024 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
1025 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable",
1026 GPIOD_OUT_LOW);
1027 if (IS_ERR(ctx->enable_gpio))
1028 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n");
1029
1030 usleep_range(10000, 11000);
1031
1032 ret = sn65dsi83_parse_dt(ctx, model);
1033 if (ret)
1034 return ret;
1035
1036 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
1037 if (IS_ERR(ctx->regmap))
1038 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n");
1039
1040 if (client->irq) {
1041 ctx->irq = client->irq;
1042 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq,
1043 IRQF_ONESHOT, dev_name(ctx->dev), ctx);
1044 if (ret)
1045 return dev_err_probe(dev, ret, "failed to request irq\n");
1046 }
1047
1048 dev_set_drvdata(dev, ctx);
1049 i2c_set_clientdata(client, ctx);
1050
1051 ctx->bridge.of_node = dev->of_node;
1052 ctx->bridge.pre_enable_prev_first = true;
1053 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS;
1054 drm_bridge_add(&ctx->bridge);
1055
1056 ret = sn65dsi83_host_attach(ctx);
1057 if (ret) {
1058 dev_err_probe(dev, ret, "failed to attach DSI host\n");
1059 goto err_remove_bridge;
1060 }
1061
1062 return 0;
1063
1064 err_remove_bridge:
1065 drm_bridge_remove(&ctx->bridge);
1066 return ret;
1067 }
1068
sn65dsi83_remove(struct i2c_client * client)1069 static void sn65dsi83_remove(struct i2c_client *client)
1070 {
1071 struct sn65dsi83 *ctx = i2c_get_clientdata(client);
1072
1073 drm_bridge_unplug(&ctx->bridge);
1074 }
1075
1076 static const struct i2c_device_id sn65dsi83_id[] = {
1077 { .name = "ti,sn65dsi83", .driver_data = MODEL_SN65DSI83 },
1078 { .name = "ti,sn65dsi84", .driver_data = MODEL_SN65DSI84 },
1079 { }
1080 };
1081 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
1082
1083 static const struct of_device_id sn65dsi83_match_table[] = {
1084 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
1085 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
1086 {},
1087 };
1088 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
1089
1090 static struct i2c_driver sn65dsi83_driver = {
1091 .probe = sn65dsi83_probe,
1092 .remove = sn65dsi83_remove,
1093 .id_table = sn65dsi83_id,
1094 .driver = {
1095 .name = "sn65dsi83",
1096 .of_match_table = sn65dsi83_match_table,
1097 },
1098 };
1099 module_i2c_driver(sn65dsi83_driver);
1100
1101 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1102 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
1103 MODULE_LICENSE("GPL v2");
1104