1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_0_kicker.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
63 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
64
65 #define mmMP1_SMN_C2PMSG_66 0x0282
66 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
67
68 #define mmMP1_SMN_C2PMSG_82 0x0292
69 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
70
71 #define mmMP1_SMN_C2PMSG_90 0x029a
72 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
73
74 #define SMU13_VOLTAGE_SCALE 4
75
76 #define LINK_WIDTH_MAX 6
77 #define LINK_SPEED_MAX 3
78
79 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
81 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
82 #define smnPCIE_LC_SPEED_CNTL 0x11140290
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
84 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
85
86 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
87
88 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
89
90 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
91 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
92
smu_v13_0_init_microcode(struct smu_context * smu)93 int smu_v13_0_init_microcode(struct smu_context *smu)
94 {
95 struct amdgpu_device *adev = smu->adev;
96 char ucode_prefix[30];
97 int err = 0;
98 const struct smc_firmware_header_v1_0 *hdr;
99 const struct common_firmware_header *header;
100 struct amdgpu_firmware_info *ucode = NULL;
101
102 /* doesn't need to load smu firmware in IOV mode */
103 if (amdgpu_sriov_vf(adev))
104 return 0;
105
106 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
107
108 if (amdgpu_is_kicker_fw(adev))
109 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
110 "amdgpu/%s_kicker.bin", ucode_prefix);
111 else
112 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
113 "amdgpu/%s.bin", ucode_prefix);
114 if (err)
115 goto out;
116
117 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
118 amdgpu_ucode_print_smc_hdr(&hdr->header);
119 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
120
121 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
122 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
123 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
124 ucode->fw = adev->pm.fw;
125 header = (const struct common_firmware_header *)ucode->fw->data;
126 adev->firmware.fw_size +=
127 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
128 }
129
130 out:
131 if (err)
132 amdgpu_ucode_release(&adev->pm.fw);
133 return err;
134 }
135
smu_v13_0_fini_microcode(struct smu_context * smu)136 void smu_v13_0_fini_microcode(struct smu_context *smu)
137 {
138 struct amdgpu_device *adev = smu->adev;
139
140 amdgpu_ucode_release(&adev->pm.fw);
141 adev->pm.fw_version = 0;
142 }
143
smu_v13_0_load_microcode(struct smu_context * smu)144 int smu_v13_0_load_microcode(struct smu_context *smu)
145 {
146 #if 0
147 struct amdgpu_device *adev = smu->adev;
148 const uint32_t *src;
149 const struct smc_firmware_header_v1_0 *hdr;
150 uint32_t addr_start = MP1_SRAM;
151 uint32_t i;
152 uint32_t smc_fw_size;
153 uint32_t mp1_fw_flags;
154
155 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
156 src = (const uint32_t *)(adev->pm.fw->data +
157 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
158 smc_fw_size = hdr->header.ucode_size_bytes;
159
160 for (i = 1; i < smc_fw_size/4 - 1; i++) {
161 WREG32_PCIE(addr_start, src[i]);
162 addr_start += 4;
163 }
164
165 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
166 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
167 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
168 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
169
170 for (i = 0; i < adev->usec_timeout; i++) {
171 mp1_fw_flags = RREG32_PCIE(MP1_Public |
172 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
173 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
174 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
175 break;
176 udelay(1);
177 }
178
179 if (i == adev->usec_timeout)
180 return -ETIME;
181 #endif
182
183 return 0;
184 }
185
smu_v13_0_init_pptable_microcode(struct smu_context * smu)186 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
187 {
188 struct amdgpu_device *adev = smu->adev;
189 struct amdgpu_firmware_info *ucode = NULL;
190 uint32_t size = 0, pptable_id = 0;
191 int ret = 0;
192 void *table;
193
194 /* doesn't need to load smu firmware in IOV mode */
195 if (amdgpu_sriov_vf(adev))
196 return 0;
197
198 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
199 return 0;
200
201 if (!adev->scpm_enabled)
202 return 0;
203
204 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 7)) ||
205 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) ||
206 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)))
207 return 0;
208
209 /* override pptable_id from driver parameter */
210 if (amdgpu_smu_pptable_id >= 0) {
211 pptable_id = amdgpu_smu_pptable_id;
212 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
213 } else {
214 pptable_id = smu->smu_table.boot_values.pp_table_id;
215 }
216
217 /* "pptable_id == 0" means vbios carries the pptable. */
218 if (!pptable_id)
219 return 0;
220
221 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
222 if (ret)
223 return ret;
224
225 smu->pptable_firmware.data = table;
226 smu->pptable_firmware.size = size;
227
228 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
229 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
230 ucode->fw = &smu->pptable_firmware;
231 adev->firmware.fw_size +=
232 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
233
234 return 0;
235 }
236
smu_v13_0_check_fw_status(struct smu_context * smu)237 int smu_v13_0_check_fw_status(struct smu_context *smu)
238 {
239 struct amdgpu_device *adev = smu->adev;
240 uint32_t mp1_fw_flags;
241
242 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
243 case IP_VERSION(13, 0, 4):
244 case IP_VERSION(13, 0, 11):
245 mp1_fw_flags = RREG32_PCIE(MP1_Public |
246 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
247 break;
248 default:
249 mp1_fw_flags = RREG32_PCIE(MP1_Public |
250 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
251 break;
252 }
253
254 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
255 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
256 return 0;
257
258 return -EIO;
259 }
260
smu_v13_0_check_fw_version(struct smu_context * smu)261 int smu_v13_0_check_fw_version(struct smu_context *smu)
262 {
263 struct amdgpu_device *adev = smu->adev;
264 uint32_t if_version = 0xff, smu_version = 0xff;
265 uint8_t smu_program, smu_major, smu_minor, smu_debug;
266 int ret = 0;
267
268 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
269 if (ret)
270 return ret;
271
272 smu_program = (smu_version >> 24) & 0xff;
273 smu_major = (smu_version >> 16) & 0xff;
274 smu_minor = (smu_version >> 8) & 0xff;
275 smu_debug = (smu_version >> 0) & 0xff;
276 adev->pm.fw_version = smu_version;
277
278 /* only for dGPU w/ SMU13*/
279 if (adev->pm.fw)
280 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
281 smu_program, smu_version, smu_major, smu_minor, smu_debug);
282
283 /*
284 * 1. if_version mismatch is not critical as our fw is designed
285 * to be backward compatible.
286 * 2. New fw usually brings some optimizations. But that's visible
287 * only on the paired driver.
288 * Considering above, we just leave user a verbal message instead
289 * of halt driver loading.
290 */
291 if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION &&
292 if_version != smu->smc_driver_if_version) {
293 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
294 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
295 smu->smc_driver_if_version, if_version,
296 smu_program, smu_version, smu_major, smu_minor, smu_debug);
297 dev_info(adev->dev, "SMU driver if version not matched\n");
298 }
299
300 return ret;
301 }
302
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)303 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
304 {
305 struct amdgpu_device *adev = smu->adev;
306 uint32_t ppt_offset_bytes;
307 const struct smc_firmware_header_v2_0 *v2;
308
309 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
310
311 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
312 *size = le32_to_cpu(v2->ppt_size_bytes);
313 *table = (uint8_t *)v2 + ppt_offset_bytes;
314
315 return 0;
316 }
317
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)318 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
319 uint32_t *size, uint32_t pptable_id)
320 {
321 struct amdgpu_device *adev = smu->adev;
322 const struct smc_firmware_header_v2_1 *v2_1;
323 struct smc_soft_pptable_entry *entries;
324 uint32_t pptable_count = 0;
325 int i = 0;
326
327 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
328 entries = (struct smc_soft_pptable_entry *)
329 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
330 pptable_count = le32_to_cpu(v2_1->pptable_count);
331 for (i = 0; i < pptable_count; i++) {
332 if (le32_to_cpu(entries[i].id) == pptable_id) {
333 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
334 *size = le32_to_cpu(entries[i].ppt_size_bytes);
335 break;
336 }
337 }
338
339 if (i == pptable_count)
340 return -EINVAL;
341
342 return 0;
343 }
344
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)345 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
346 {
347 struct amdgpu_device *adev = smu->adev;
348 uint16_t atom_table_size;
349 uint8_t frev, crev;
350 int ret, index;
351
352 dev_info(adev->dev, "use vbios provided pptable\n");
353 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
354 powerplayinfo);
355
356 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
357 (uint8_t **)table);
358 if (ret)
359 return ret;
360
361 if (size)
362 *size = atom_table_size;
363
364 return 0;
365 }
366
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)367 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
368 void **table,
369 uint32_t *size,
370 uint32_t pptable_id)
371 {
372 const struct smc_firmware_header_v1_0 *hdr;
373 struct amdgpu_device *adev = smu->adev;
374 uint16_t version_major, version_minor;
375 int ret;
376
377 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
378 if (!hdr)
379 return -EINVAL;
380
381 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
382
383 version_major = le16_to_cpu(hdr->header.header_version_major);
384 version_minor = le16_to_cpu(hdr->header.header_version_minor);
385 if (version_major != 2) {
386 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
387 version_major, version_minor);
388 return -EINVAL;
389 }
390
391 switch (version_minor) {
392 case 0:
393 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
394 break;
395 case 1:
396 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
397 break;
398 default:
399 ret = -EINVAL;
400 break;
401 }
402
403 return ret;
404 }
405
smu_v13_0_setup_pptable(struct smu_context * smu)406 int smu_v13_0_setup_pptable(struct smu_context *smu)
407 {
408 struct amdgpu_device *adev = smu->adev;
409 uint32_t size = 0, pptable_id = 0;
410 void *table;
411 int ret = 0;
412
413 /* override pptable_id from driver parameter */
414 if (amdgpu_smu_pptable_id >= 0) {
415 pptable_id = amdgpu_smu_pptable_id;
416 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
417 } else {
418 pptable_id = smu->smu_table.boot_values.pp_table_id;
419 }
420
421 /* force using vbios pptable in sriov mode */
422 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
423 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
424 else
425 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
426
427 if (ret)
428 return ret;
429
430 if (!smu->smu_table.power_play_table)
431 smu->smu_table.power_play_table = table;
432 if (!smu->smu_table.power_play_table_size)
433 smu->smu_table.power_play_table_size = size;
434
435 return 0;
436 }
437
smu_v13_0_init_smc_tables(struct smu_context * smu)438 int smu_v13_0_init_smc_tables(struct smu_context *smu)
439 {
440 struct smu_table_context *smu_table = &smu->smu_table;
441 struct smu_table *tables = smu_table->tables;
442 int ret = 0;
443
444 smu_table->driver_pptable =
445 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
446 if (!smu_table->driver_pptable) {
447 ret = -ENOMEM;
448 goto err0_out;
449 }
450
451 smu_table->max_sustainable_clocks =
452 kzalloc_obj(struct smu_13_0_max_sustainable_clocks);
453 if (!smu_table->max_sustainable_clocks) {
454 ret = -ENOMEM;
455 goto err1_out;
456 }
457
458 /* Aldebaran does not support OVERDRIVE */
459 if (tables[SMU_TABLE_OVERDRIVE].size) {
460 smu_table->overdrive_table =
461 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
462 if (!smu_table->overdrive_table) {
463 ret = -ENOMEM;
464 goto err2_out;
465 }
466
467 smu_table->boot_overdrive_table =
468 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
469 if (!smu_table->boot_overdrive_table) {
470 ret = -ENOMEM;
471 goto err3_out;
472 }
473
474 smu_table->user_overdrive_table =
475 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
476 if (!smu_table->user_overdrive_table) {
477 ret = -ENOMEM;
478 goto err4_out;
479 }
480 }
481
482 smu_table->combo_pptable =
483 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
484 if (!smu_table->combo_pptable) {
485 ret = -ENOMEM;
486 goto err5_out;
487 }
488
489 return 0;
490
491 err5_out:
492 kfree(smu_table->user_overdrive_table);
493 err4_out:
494 kfree(smu_table->boot_overdrive_table);
495 err3_out:
496 kfree(smu_table->overdrive_table);
497 err2_out:
498 kfree(smu_table->max_sustainable_clocks);
499 err1_out:
500 kfree(smu_table->driver_pptable);
501 err0_out:
502 return ret;
503 }
504
smu_v13_0_fini_smc_tables(struct smu_context * smu)505 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
506 {
507 struct smu_table_context *smu_table = &smu->smu_table;
508 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
509
510 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
511 kfree(smu_table->combo_pptable);
512 kfree(smu_table->user_overdrive_table);
513 kfree(smu_table->boot_overdrive_table);
514 kfree(smu_table->overdrive_table);
515 kfree(smu_table->max_sustainable_clocks);
516 kfree(smu_table->driver_pptable);
517 smu_table->combo_pptable = NULL;
518 smu_table->user_overdrive_table = NULL;
519 smu_table->boot_overdrive_table = NULL;
520 smu_table->overdrive_table = NULL;
521 smu_table->max_sustainable_clocks = NULL;
522 smu_table->driver_pptable = NULL;
523 kfree(smu_table->hardcode_pptable);
524 smu_table->hardcode_pptable = NULL;
525
526 kfree(smu_table->ecc_table);
527 kfree(smu_table->metrics_table);
528 kfree(smu_table->watermarks_table);
529 smu_table->ecc_table = NULL;
530 smu_table->metrics_table = NULL;
531 smu_table->watermarks_table = NULL;
532 smu_table->metrics_time = 0;
533
534 kfree(smu_dpm->dpm_policies);
535 kfree(smu_dpm->dpm_context);
536 kfree(smu_dpm->golden_dpm_context);
537 kfree(smu_dpm->dpm_current_power_state);
538 kfree(smu_dpm->dpm_request_power_state);
539 smu_dpm->dpm_policies = NULL;
540 smu_dpm->dpm_context = NULL;
541 smu_dpm->golden_dpm_context = NULL;
542 smu_dpm->dpm_context_size = 0;
543 smu_dpm->dpm_current_power_state = NULL;
544 smu_dpm->dpm_request_power_state = NULL;
545
546 return 0;
547 }
548
smu_v13_0_init_power(struct smu_context * smu)549 int smu_v13_0_init_power(struct smu_context *smu)
550 {
551 struct smu_power_context *smu_power = &smu->smu_power;
552
553 if (smu_power->power_context || smu_power->power_context_size != 0)
554 return -EINVAL;
555
556 smu_power->power_context = kzalloc_obj(struct smu_13_0_power_context);
557 if (!smu_power->power_context)
558 return -ENOMEM;
559 smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
560
561 return 0;
562 }
563
smu_v13_0_fini_power(struct smu_context * smu)564 int smu_v13_0_fini_power(struct smu_context *smu)
565 {
566 struct smu_power_context *smu_power = &smu->smu_power;
567
568 if (!smu_power->power_context || smu_power->power_context_size == 0)
569 return -EINVAL;
570
571 kfree(smu_power->power_context);
572 smu_power->power_context = NULL;
573 smu_power->power_context_size = 0;
574
575 return 0;
576 }
577
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)578 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
579 {
580 int ret, index;
581 uint16_t size;
582 uint8_t frev, crev;
583 struct atom_common_table_header *header;
584 struct atom_firmware_info_v3_4 *v_3_4;
585 struct atom_firmware_info_v3_3 *v_3_3;
586 struct atom_firmware_info_v3_1 *v_3_1;
587 struct atom_smu_info_v3_6 *smu_info_v3_6;
588 struct atom_smu_info_v4_0 *smu_info_v4_0;
589
590 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
591 firmwareinfo);
592
593 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
594 (uint8_t **)&header);
595 if (ret)
596 return ret;
597
598 if (header->format_revision != 3) {
599 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
600 return -EINVAL;
601 }
602
603 switch (header->content_revision) {
604 case 0:
605 case 1:
606 case 2:
607 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
608 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
609 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
610 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
611 smu->smu_table.boot_values.socclk = 0;
612 smu->smu_table.boot_values.dcefclk = 0;
613 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
614 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
615 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
616 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
617 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
618 smu->smu_table.boot_values.pp_table_id = 0;
619 break;
620 case 3:
621 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
622 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
623 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
624 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
625 smu->smu_table.boot_values.socclk = 0;
626 smu->smu_table.boot_values.dcefclk = 0;
627 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
628 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
629 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
630 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
631 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
632 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
633 break;
634 case 4:
635 default:
636 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
637 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
638 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
639 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
640 smu->smu_table.boot_values.socclk = 0;
641 smu->smu_table.boot_values.dcefclk = 0;
642 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
643 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
644 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
645 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
646 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
647 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
648 break;
649 }
650
651 smu->smu_table.boot_values.format_revision = header->format_revision;
652 smu->smu_table.boot_values.content_revision = header->content_revision;
653
654 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
655 smu_info);
656 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
657 (uint8_t **)&header)) {
658
659 if ((frev == 3) && (crev == 6)) {
660 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
661
662 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
663 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
664 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
665 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
666 } else if ((frev == 3) && (crev == 1)) {
667 return 0;
668 } else if ((frev == 4) && (crev == 0)) {
669 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
670
671 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
672 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
673 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
674 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
675 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
676 } else {
677 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
678 (uint32_t)frev, (uint32_t)crev);
679 }
680 }
681
682 return 0;
683 }
684
685
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)686 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
687 {
688 struct smu_table_context *smu_table = &smu->smu_table;
689 struct smu_table *memory_pool = &smu_table->memory_pool;
690 int ret = 0;
691 uint64_t address;
692 uint32_t address_low, address_high;
693
694 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
695 return ret;
696
697 address = memory_pool->mc_address;
698 address_high = (uint32_t)upper_32_bits(address);
699 address_low = (uint32_t)lower_32_bits(address);
700
701 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
702 address_high, NULL);
703 if (ret)
704 return ret;
705 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
706 address_low, NULL);
707 if (ret)
708 return ret;
709 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
710 (uint32_t)memory_pool->size, NULL);
711 if (ret)
712 return ret;
713
714 return ret;
715 }
716
smu_v13_0_set_driver_table_location(struct smu_context * smu)717 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
718 {
719 struct smu_table *driver_table = &smu->smu_table.driver_table;
720 int ret = 0;
721
722 if (driver_table->mc_address) {
723 ret = smu_cmn_send_smc_msg_with_param(smu,
724 SMU_MSG_SetDriverDramAddrHigh,
725 upper_32_bits(driver_table->mc_address),
726 NULL);
727 if (!ret)
728 ret = smu_cmn_send_smc_msg_with_param(smu,
729 SMU_MSG_SetDriverDramAddrLow,
730 lower_32_bits(driver_table->mc_address),
731 NULL);
732 }
733
734 return ret;
735 }
736
smu_v13_0_set_tool_table_location(struct smu_context * smu)737 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
738 {
739 int ret = 0;
740 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
741
742 if (tool_table->mc_address) {
743 ret = smu_cmn_send_smc_msg_with_param(smu,
744 SMU_MSG_SetToolsDramAddrHigh,
745 upper_32_bits(tool_table->mc_address),
746 NULL);
747 if (!ret)
748 ret = smu_cmn_send_smc_msg_with_param(smu,
749 SMU_MSG_SetToolsDramAddrLow,
750 lower_32_bits(tool_table->mc_address),
751 NULL);
752 }
753
754 return ret;
755 }
756
smu_v13_0_set_allowed_mask(struct smu_context * smu)757 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
758 {
759 struct smu_feature *feature = &smu->smu_feature;
760 int ret = 0;
761 uint32_t feature_mask[2];
762
763 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
764 feature->feature_num < SMU_FEATURE_NUM_DEFAULT)
765 return -EINVAL;
766
767 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
768
769 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
770 feature_mask[1], NULL);
771 if (ret)
772 return ret;
773
774 return smu_cmn_send_smc_msg_with_param(smu,
775 SMU_MSG_SetAllowedFeaturesMaskLow,
776 feature_mask[0],
777 NULL);
778 }
779
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)780 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
781 {
782 int ret = 0;
783 struct amdgpu_device *adev = smu->adev;
784
785 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
786 case IP_VERSION(13, 0, 0):
787 case IP_VERSION(13, 0, 1):
788 case IP_VERSION(13, 0, 3):
789 case IP_VERSION(13, 0, 4):
790 case IP_VERSION(13, 0, 5):
791 case IP_VERSION(13, 0, 7):
792 case IP_VERSION(13, 0, 8):
793 case IP_VERSION(13, 0, 10):
794 case IP_VERSION(13, 0, 11):
795 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
796 return 0;
797 if (enable)
798 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
799 else
800 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
801 break;
802 default:
803 break;
804 }
805
806 return ret;
807 }
808
smu_v13_0_system_features_control(struct smu_context * smu,bool en)809 int smu_v13_0_system_features_control(struct smu_context *smu,
810 bool en)
811 {
812 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
813 SMU_MSG_DisableAllSmuFeatures), NULL);
814 }
815
smu_v13_0_notify_display_change(struct smu_context * smu)816 int smu_v13_0_notify_display_change(struct smu_context *smu)
817 {
818 int ret = 0;
819
820 if (!amdgpu_device_has_dc_support(smu->adev))
821 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL);
822
823 return ret;
824 }
825
826 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)827 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
828 enum smu_clk_type clock_select)
829 {
830 int ret = 0;
831 int clk_id;
832
833 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
834 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
835 return 0;
836
837 clk_id = smu_cmn_to_asic_specific_index(smu,
838 CMN2ASIC_MAPPING_CLK,
839 clock_select);
840 if (clk_id < 0)
841 return -EINVAL;
842
843 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
844 clk_id << 16, clock);
845 if (ret) {
846 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
847 return ret;
848 }
849
850 if (*clock != 0)
851 return 0;
852
853 /* if DC limit is zero, return AC limit */
854 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
855 clk_id << 16, clock);
856 if (ret) {
857 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
858 return ret;
859 }
860
861 return 0;
862 }
863
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)864 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
865 {
866 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
867 smu->smu_table.max_sustainable_clocks;
868 int ret = 0;
869
870 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
871 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
872 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
873 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
874 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
875 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
876
877 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
878 ret = smu_v13_0_get_max_sustainable_clock(smu,
879 &(max_sustainable_clocks->uclock),
880 SMU_UCLK);
881 if (ret) {
882 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
883 __func__);
884 return ret;
885 }
886 }
887
888 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
889 ret = smu_v13_0_get_max_sustainable_clock(smu,
890 &(max_sustainable_clocks->soc_clock),
891 SMU_SOCCLK);
892 if (ret) {
893 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
894 __func__);
895 return ret;
896 }
897 }
898
899 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
900 ret = smu_v13_0_get_max_sustainable_clock(smu,
901 &(max_sustainable_clocks->dcef_clock),
902 SMU_DCEFCLK);
903 if (ret) {
904 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
905 __func__);
906 return ret;
907 }
908
909 ret = smu_v13_0_get_max_sustainable_clock(smu,
910 &(max_sustainable_clocks->display_clock),
911 SMU_DISPCLK);
912 if (ret) {
913 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
914 __func__);
915 return ret;
916 }
917 ret = smu_v13_0_get_max_sustainable_clock(smu,
918 &(max_sustainable_clocks->phy_clock),
919 SMU_PHYCLK);
920 if (ret) {
921 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
922 __func__);
923 return ret;
924 }
925 ret = smu_v13_0_get_max_sustainable_clock(smu,
926 &(max_sustainable_clocks->pixel_clock),
927 SMU_PIXCLK);
928 if (ret) {
929 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
930 __func__);
931 return ret;
932 }
933 }
934
935 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
936 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
937
938 return 0;
939 }
940
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)941 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
942 uint32_t *power_limit)
943 {
944 int power_src;
945 int ret = 0;
946
947 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
948 return -EINVAL;
949
950 power_src = smu_cmn_to_asic_specific_index(smu,
951 CMN2ASIC_MAPPING_PWR,
952 smu->adev->pm.ac_power ?
953 SMU_POWER_SOURCE_AC :
954 SMU_POWER_SOURCE_DC);
955 if (power_src < 0)
956 return -EINVAL;
957
958 ret = smu_cmn_send_smc_msg_with_param(smu,
959 SMU_MSG_GetPptLimit,
960 power_src << 16,
961 power_limit);
962 if (ret)
963 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
964
965 return ret;
966 }
967
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)968 int smu_v13_0_set_power_limit(struct smu_context *smu,
969 enum smu_ppt_limit_type limit_type,
970 uint32_t limit)
971 {
972 int ret = 0;
973
974 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
975 return -EINVAL;
976
977 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
978 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
979 return -EOPNOTSUPP;
980 }
981
982 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
983 if (ret) {
984 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
985 return ret;
986 }
987
988 smu->current_power_limit = limit;
989
990 return 0;
991 }
992
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)993 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
994 {
995 return smu_cmn_send_smc_msg(smu,
996 SMU_MSG_AllowIHHostInterrupt,
997 NULL);
998 }
999
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1000 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1001 {
1002 int ret = 0;
1003
1004 if (smu->dc_controlled_by_gpio &&
1005 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1006 ret = smu_v13_0_allow_ih_interrupt(smu);
1007
1008 return ret;
1009 }
1010
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1011 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1012 {
1013 int ret = 0;
1014
1015 if (!smu->irq_source.num_types)
1016 return 0;
1017
1018 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1019 if (ret)
1020 return ret;
1021
1022 return smu_v13_0_process_pending_interrupt(smu);
1023 }
1024
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1025 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1026 {
1027 if (!smu->irq_source.num_types)
1028 return 0;
1029
1030 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1031 }
1032
convert_to_vddc(uint8_t vid)1033 static uint16_t convert_to_vddc(uint8_t vid)
1034 {
1035 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1036 }
1037
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1038 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1039 {
1040 struct amdgpu_device *adev = smu->adev;
1041 uint32_t vdd = 0, val_vid = 0;
1042
1043 if (!value)
1044 return -EINVAL;
1045 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1046 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1047 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1048
1049 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1050
1051 *value = vdd;
1052
1053 return 0;
1054
1055 }
1056
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1057 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1058 {
1059 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1060 return AMD_FAN_CTRL_MANUAL;
1061 else
1062 return AMD_FAN_CTRL_AUTO;
1063 }
1064
1065 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1066 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1067 {
1068 int ret = 0;
1069
1070 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1071 return 0;
1072
1073 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1074 if (ret)
1075 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1076 __func__, (auto_fan_control ? "Start" : "Stop"));
1077
1078 return ret;
1079 }
1080
1081 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1082 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1083 {
1084 struct amdgpu_device *adev = smu->adev;
1085
1086 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1087 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1088 CG_FDO_CTRL2, TMIN, 0));
1089 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1090 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1091 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1092
1093 return 0;
1094 }
1095
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1096 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1097 uint32_t speed)
1098 {
1099 struct amdgpu_device *adev = smu->adev;
1100 uint32_t duty100, duty;
1101 uint64_t tmp64;
1102
1103 speed = min_t(uint32_t, speed, 255);
1104
1105 if (smu_v13_0_auto_fan_control(smu, 0))
1106 return -EINVAL;
1107
1108 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1109 CG_FDO_CTRL1, FMAX_DUTY100);
1110 if (!duty100)
1111 return -EINVAL;
1112
1113 tmp64 = (uint64_t)speed * duty100;
1114 do_div(tmp64, 255);
1115 duty = (uint32_t)tmp64;
1116
1117 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1118 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1119 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1120
1121 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1122 }
1123
1124 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1125 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1126 uint32_t mode)
1127 {
1128 int ret = 0;
1129
1130 switch (mode) {
1131 case AMD_FAN_CTRL_NONE:
1132 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1133 break;
1134 case AMD_FAN_CTRL_MANUAL:
1135 ret = smu_v13_0_auto_fan_control(smu, 0);
1136 break;
1137 case AMD_FAN_CTRL_AUTO:
1138 ret = smu_v13_0_auto_fan_control(smu, 1);
1139 break;
1140 default:
1141 break;
1142 }
1143
1144 if (ret) {
1145 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1146 return -EINVAL;
1147 }
1148
1149 return ret;
1150 }
1151
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1152 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1153 uint32_t speed)
1154 {
1155 struct amdgpu_device *adev = smu->adev;
1156 uint32_t crystal_clock_freq = 2500;
1157 uint32_t tach_period;
1158 int ret;
1159
1160 if (!speed || speed > UINT_MAX/8)
1161 return -EINVAL;
1162
1163 ret = smu_v13_0_auto_fan_control(smu, 0);
1164 if (ret)
1165 return ret;
1166
1167 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1168 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1169 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1170 CG_TACH_CTRL, TARGET_PERIOD,
1171 tach_period));
1172
1173 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1174 }
1175
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1176 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1177 uint32_t pstate)
1178 {
1179 int ret = 0;
1180 ret = smu_cmn_send_smc_msg_with_param(smu,
1181 SMU_MSG_SetXgmiMode,
1182 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1183 NULL);
1184 return ret;
1185 }
1186
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1187 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1188 struct amdgpu_irq_src *source,
1189 unsigned tyep,
1190 enum amdgpu_interrupt_state state)
1191 {
1192 struct smu_context *smu = adev->powerplay.pp_handle;
1193 uint32_t low, high;
1194 uint32_t val = 0;
1195
1196 switch (state) {
1197 case AMDGPU_IRQ_STATE_DISABLE:
1198 /* For THM irqs */
1199 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1200 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1201 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1202 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1203
1204 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1205
1206 /* For MP1 SW irqs */
1207 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1208 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1209 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1210
1211 break;
1212 case AMDGPU_IRQ_STATE_ENABLE:
1213 /* For THM irqs */
1214 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1215 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1216 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1217 smu->thermal_range.software_shutdown_temp);
1218
1219 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1220 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1221 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1222 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1223 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1224 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1225 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1226 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1227 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1228
1229 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1230 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1231 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1232 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1233
1234 /* For MP1 SW irqs */
1235 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1236 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1237 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1238 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1239
1240 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1241 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1242 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1243
1244 break;
1245 default:
1246 break;
1247 }
1248
1249 return 0;
1250 }
1251
smu_v13_0_interrupt_work(struct smu_context * smu)1252 void smu_v13_0_interrupt_work(struct smu_context *smu)
1253 {
1254 smu_cmn_send_smc_msg(smu,
1255 SMU_MSG_ReenableAcDcInterrupt,
1256 NULL);
1257 }
1258
1259 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1260 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1261 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1262
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1263 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1264 struct amdgpu_irq_src *source,
1265 struct amdgpu_iv_entry *entry)
1266 {
1267 struct smu_context *smu = adev->powerplay.pp_handle;
1268 uint32_t client_id = entry->client_id;
1269 uint32_t src_id = entry->src_id;
1270 /*
1271 * ctxid is used to distinguish different
1272 * events for SMCToHost interrupt.
1273 */
1274 uint32_t ctxid = entry->src_data[0];
1275 uint32_t data;
1276 uint32_t high;
1277
1278 if (client_id == SOC15_IH_CLIENTID_THM) {
1279 switch (src_id) {
1280 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1281 schedule_delayed_work(&smu->swctf_delayed_work,
1282 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1283 break;
1284 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1285 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1286 break;
1287 default:
1288 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1289 src_id);
1290 break;
1291 }
1292 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1293 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1294 /*
1295 * HW CTF just occurred. Shutdown to prevent further damage.
1296 */
1297 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1298 orderly_poweroff(true);
1299 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1300 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1301 /* ACK SMUToHost interrupt */
1302 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1303 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1304 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1305
1306 switch (ctxid) {
1307 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1308 dev_dbg(adev->dev, "Switched to AC mode!\n");
1309 schedule_work(&smu->interrupt_work);
1310 adev->pm.ac_power = true;
1311 break;
1312 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1313 dev_dbg(adev->dev, "Switched to DC mode!\n");
1314 schedule_work(&smu->interrupt_work);
1315 adev->pm.ac_power = false;
1316 break;
1317 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1318 /*
1319 * Increment the throttle interrupt counter
1320 */
1321 atomic64_inc(&smu->throttle_int_counter);
1322
1323 if (!atomic_read(&adev->throttling_logging_enabled))
1324 return 0;
1325
1326 if (__ratelimit(&adev->throttling_logging_rs))
1327 schedule_work(&smu->throttling_logging_work);
1328
1329 break;
1330 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL:
1331 high = smu->thermal_range.software_shutdown_temp +
1332 smu->thermal_range.software_shutdown_temp_offset;
1333 high = min_t(typeof(high),
1334 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1335 high);
1336 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1337 high,
1338 smu->thermal_range.software_shutdown_temp_offset);
1339
1340 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1341 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1342 DIG_THERM_INTH,
1343 (high & 0xff));
1344 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1345 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1346 break;
1347 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY:
1348 high = min_t(typeof(high),
1349 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1350 smu->thermal_range.software_shutdown_temp);
1351 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1352
1353 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1354 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1355 DIG_THERM_INTH,
1356 (high & 0xff));
1357 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1358 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1359 break;
1360 default:
1361 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1362 ctxid, client_id);
1363 break;
1364 }
1365 }
1366 }
1367
1368 return 0;
1369 }
1370
1371 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1372 .set = smu_v13_0_set_irq_state,
1373 .process = smu_v13_0_irq_process,
1374 };
1375
smu_v13_0_register_irq_handler(struct smu_context * smu)1376 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1377 {
1378 struct amdgpu_device *adev = smu->adev;
1379 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1380 int ret = 0;
1381
1382 if (amdgpu_sriov_vf(adev))
1383 return 0;
1384
1385 irq_src->num_types = 1;
1386 irq_src->funcs = &smu_v13_0_irq_funcs;
1387
1388 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1389 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1390 irq_src);
1391 if (ret)
1392 return ret;
1393
1394 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1395 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1396 irq_src);
1397 if (ret)
1398 return ret;
1399
1400 /* Register CTF(GPIO_19) interrupt */
1401 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1402 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1403 irq_src);
1404 if (ret)
1405 return ret;
1406
1407 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1408 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1409 irq_src);
1410 if (ret)
1411 return ret;
1412
1413 return ret;
1414 }
1415
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1416 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1417 struct pp_smu_nv_clock_table *max_clocks)
1418 {
1419 struct smu_table_context *table_context = &smu->smu_table;
1420 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1421
1422 if (!max_clocks || !table_context->max_sustainable_clocks)
1423 return -EINVAL;
1424
1425 sustainable_clocks = table_context->max_sustainable_clocks;
1426
1427 max_clocks->dcfClockInKhz =
1428 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1429 max_clocks->displayClockInKhz =
1430 (unsigned int) sustainable_clocks->display_clock * 1000;
1431 max_clocks->phyClockInKhz =
1432 (unsigned int) sustainable_clocks->phy_clock * 1000;
1433 max_clocks->pixelClockInKhz =
1434 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1435 max_clocks->uClockInKhz =
1436 (unsigned int) sustainable_clocks->uclock * 1000;
1437 max_clocks->socClockInKhz =
1438 (unsigned int) sustainable_clocks->soc_clock * 1000;
1439 max_clocks->dscClockInKhz = 0;
1440 max_clocks->dppClockInKhz = 0;
1441 max_clocks->fabricClockInKhz = 0;
1442
1443 return 0;
1444 }
1445
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1446 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1447 {
1448 int ret = 0;
1449
1450 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1451
1452 return ret;
1453 }
1454
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1455 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1456 uint64_t event_arg)
1457 {
1458 int ret = 0;
1459
1460 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1461 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1462
1463 return ret;
1464 }
1465
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1466 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1467 uint64_t event_arg)
1468 {
1469 int ret = -EINVAL;
1470
1471 switch (event) {
1472 case SMU_EVENT_RESET_COMPLETE:
1473 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1474 break;
1475 default:
1476 break;
1477 }
1478
1479 return ret;
1480 }
1481
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1482 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1483 uint32_t *min, uint32_t *max)
1484 {
1485 int ret = 0, clk_id = 0;
1486 uint32_t param = 0;
1487 uint32_t clock_limit;
1488
1489 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1490 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
1491 if (ret)
1492 return ret;
1493
1494 /* clock in Mhz unit */
1495 if (min)
1496 *min = clock_limit / 100;
1497 if (max)
1498 *max = clock_limit / 100;
1499
1500 return 0;
1501 }
1502
1503 clk_id = smu_cmn_to_asic_specific_index(smu,
1504 CMN2ASIC_MAPPING_CLK,
1505 clk_type);
1506 if (clk_id < 0) {
1507 ret = -EINVAL;
1508 goto failed;
1509 }
1510 param = (clk_id & 0xffff) << 16;
1511
1512 if (max) {
1513 if (smu->adev->pm.ac_power)
1514 ret = smu_cmn_send_smc_msg_with_param(smu,
1515 SMU_MSG_GetMaxDpmFreq,
1516 param,
1517 max);
1518 else
1519 ret = smu_cmn_send_smc_msg_with_param(smu,
1520 SMU_MSG_GetDcModeMaxDpmFreq,
1521 param,
1522 max);
1523 if (ret)
1524 goto failed;
1525 }
1526
1527 if (min) {
1528 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1529 if (ret)
1530 goto failed;
1531 }
1532
1533 failed:
1534 return ret;
1535 }
1536
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1537 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1538 enum smu_clk_type clk_type,
1539 uint32_t min,
1540 uint32_t max,
1541 bool automatic)
1542 {
1543 int ret = 0, clk_id = 0;
1544 uint32_t param;
1545
1546 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1547 return 0;
1548
1549 clk_id = smu_cmn_to_asic_specific_index(smu,
1550 CMN2ASIC_MAPPING_CLK,
1551 clk_type);
1552 if (clk_id < 0)
1553 return clk_id;
1554
1555 if (max > 0) {
1556 max = SMU_V13_SOFT_FREQ_ROUND(max);
1557 if (automatic)
1558 param = (uint32_t)((clk_id << 16) | 0xffff);
1559 else
1560 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1561 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1562 param, NULL);
1563 if (ret)
1564 goto out;
1565 }
1566
1567 if (min > 0) {
1568 if (automatic)
1569 param = (uint32_t)((clk_id << 16) | 0);
1570 else
1571 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1572 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1573 param, NULL);
1574 if (ret)
1575 goto out;
1576 }
1577
1578 out:
1579 return ret;
1580 }
1581
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1582 int smu_v13_0_set_performance_level(struct smu_context *smu,
1583 enum amd_dpm_forced_level level)
1584 {
1585 struct smu_13_0_dpm_context *dpm_context =
1586 smu->smu_dpm.dpm_context;
1587 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1588 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
1589 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
1590 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
1591 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
1592 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
1593 struct smu_umd_pstate_table *pstate_table =
1594 &smu->pstate_table;
1595 struct amdgpu_device *adev = smu->adev;
1596 uint32_t sclk_min = 0, sclk_max = 0;
1597 uint32_t mclk_min = 0, mclk_max = 0;
1598 uint32_t socclk_min = 0, socclk_max = 0;
1599 uint32_t vclk_min = 0, vclk_max = 0;
1600 uint32_t dclk_min = 0, dclk_max = 0;
1601 uint32_t fclk_min = 0, fclk_max = 0;
1602 int ret = 0, i;
1603 bool auto_level = false;
1604
1605 switch (level) {
1606 case AMD_DPM_FORCED_LEVEL_HIGH:
1607 sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1608 mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1609 socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1610 vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
1611 dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
1612 fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
1613 break;
1614 case AMD_DPM_FORCED_LEVEL_LOW:
1615 sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);
1616 mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);
1617 socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);
1618 vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table);
1619 dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table);
1620 fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table);
1621 break;
1622 case AMD_DPM_FORCED_LEVEL_AUTO:
1623 sclk_min = SMU_DPM_TABLE_MIN(gfx_table);
1624 sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1625 mclk_min = SMU_DPM_TABLE_MIN(mem_table);
1626 mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1627 socclk_min = SMU_DPM_TABLE_MIN(soc_table);
1628 socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1629 vclk_min = SMU_DPM_TABLE_MIN(vclk_table);
1630 vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
1631 dclk_min = SMU_DPM_TABLE_MIN(dclk_table);
1632 dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
1633 fclk_min = SMU_DPM_TABLE_MIN(fclk_table);
1634 fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
1635 auto_level = true;
1636 break;
1637 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1638 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1639 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1640 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1641 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1642 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1643 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1644 break;
1645 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1646 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1647 break;
1648 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1649 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1650 break;
1651 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1652 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1653 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1654 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1655 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1656 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1657 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1658 break;
1659 case AMD_DPM_FORCED_LEVEL_MANUAL:
1660 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1661 return 0;
1662 default:
1663 dev_err(adev->dev, "Invalid performance level %d\n", level);
1664 return -EINVAL;
1665 }
1666
1667 /*
1668 * Unset those settings for SMU 13.0.2. As soft limits settings
1669 * for those clock domains are not supported.
1670 */
1671 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) {
1672 mclk_min = mclk_max = 0;
1673 socclk_min = socclk_max = 0;
1674 vclk_min = vclk_max = 0;
1675 dclk_min = dclk_max = 0;
1676 fclk_min = fclk_max = 0;
1677 auto_level = false;
1678 }
1679
1680 if (sclk_min && sclk_max) {
1681 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1682 SMU_GFXCLK,
1683 sclk_min,
1684 sclk_max,
1685 auto_level);
1686 if (ret)
1687 return ret;
1688
1689 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1690 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1691 }
1692
1693 if (mclk_min && mclk_max) {
1694 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1695 SMU_MCLK,
1696 mclk_min,
1697 mclk_max,
1698 auto_level);
1699 if (ret)
1700 return ret;
1701
1702 pstate_table->uclk_pstate.curr.min = mclk_min;
1703 pstate_table->uclk_pstate.curr.max = mclk_max;
1704 }
1705
1706 if (socclk_min && socclk_max) {
1707 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1708 SMU_SOCCLK,
1709 socclk_min,
1710 socclk_max,
1711 auto_level);
1712 if (ret)
1713 return ret;
1714
1715 pstate_table->socclk_pstate.curr.min = socclk_min;
1716 pstate_table->socclk_pstate.curr.max = socclk_max;
1717 }
1718
1719 if (vclk_min && vclk_max) {
1720 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1721 if (adev->vcn.harvest_config & (1 << i))
1722 continue;
1723 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1724 i ? SMU_VCLK1 : SMU_VCLK,
1725 vclk_min,
1726 vclk_max,
1727 auto_level);
1728 if (ret)
1729 return ret;
1730 }
1731 pstate_table->vclk_pstate.curr.min = vclk_min;
1732 pstate_table->vclk_pstate.curr.max = vclk_max;
1733 }
1734
1735 if (dclk_min && dclk_max) {
1736 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1737 if (adev->vcn.harvest_config & (1 << i))
1738 continue;
1739 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1740 i ? SMU_DCLK1 : SMU_DCLK,
1741 dclk_min,
1742 dclk_max,
1743 auto_level);
1744 if (ret)
1745 return ret;
1746 }
1747 pstate_table->dclk_pstate.curr.min = dclk_min;
1748 pstate_table->dclk_pstate.curr.max = dclk_max;
1749 }
1750
1751 if (fclk_min && fclk_max) {
1752 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1753 SMU_FCLK,
1754 fclk_min,
1755 fclk_max,
1756 auto_level);
1757 if (ret)
1758 return ret;
1759
1760 pstate_table->fclk_pstate.curr.min = fclk_min;
1761 pstate_table->fclk_pstate.curr.max = fclk_max;
1762 }
1763
1764 return ret;
1765 }
1766
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1767 int smu_v13_0_set_power_source(struct smu_context *smu,
1768 enum smu_power_src_type power_src)
1769 {
1770 int pwr_source;
1771
1772 pwr_source = smu_cmn_to_asic_specific_index(smu,
1773 CMN2ASIC_MAPPING_PWR,
1774 (uint32_t)power_src);
1775 if (pwr_source < 0)
1776 return -EINVAL;
1777
1778 return smu_cmn_send_smc_msg_with_param(smu,
1779 SMU_MSG_NotifyPowerSource,
1780 pwr_source,
1781 NULL);
1782 }
1783
smu_v13_0_get_boot_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1784 int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
1785 enum smu_clk_type clk_type,
1786 uint32_t *value)
1787 {
1788 int ret = 0;
1789
1790 switch (clk_type) {
1791 case SMU_MCLK:
1792 case SMU_UCLK:
1793 *value = smu->smu_table.boot_values.uclk;
1794 break;
1795 case SMU_FCLK:
1796 *value = smu->smu_table.boot_values.fclk;
1797 break;
1798 case SMU_GFXCLK:
1799 case SMU_SCLK:
1800 *value = smu->smu_table.boot_values.gfxclk;
1801 break;
1802 case SMU_SOCCLK:
1803 *value = smu->smu_table.boot_values.socclk;
1804 break;
1805 case SMU_VCLK:
1806 *value = smu->smu_table.boot_values.vclk;
1807 break;
1808 case SMU_DCLK:
1809 *value = smu->smu_table.boot_values.dclk;
1810 break;
1811 default:
1812 ret = -EINVAL;
1813 break;
1814 }
1815 return ret;
1816 }
1817
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1818 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1819 enum smu_clk_type clk_type, uint16_t level,
1820 uint32_t *value)
1821 {
1822 int ret = 0, clk_id = 0;
1823 uint32_t param;
1824
1825 if (!value)
1826 return -EINVAL;
1827
1828 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1829 return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);
1830
1831 clk_id = smu_cmn_to_asic_specific_index(smu,
1832 CMN2ASIC_MAPPING_CLK,
1833 clk_type);
1834 if (clk_id < 0)
1835 return clk_id;
1836
1837 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1838
1839 ret = smu_cmn_send_smc_msg_with_param(smu,
1840 SMU_MSG_GetDpmFreqByIndex,
1841 param,
1842 value);
1843 if (ret)
1844 return ret;
1845
1846 *value = *value & 0x7fffffff;
1847
1848 return ret;
1849 }
1850
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1851 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1852 enum smu_clk_type clk_type,
1853 uint32_t *value)
1854 {
1855 int ret;
1856
1857 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1858 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1859 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) && (!ret && value))
1860 ++(*value);
1861
1862 return ret;
1863 }
1864
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1865 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1866 enum smu_clk_type clk_type,
1867 bool *is_fine_grained_dpm)
1868 {
1869 int ret = 0, clk_id = 0;
1870 uint32_t param;
1871 uint32_t value;
1872
1873 if (!is_fine_grained_dpm)
1874 return -EINVAL;
1875
1876 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1877 return 0;
1878
1879 clk_id = smu_cmn_to_asic_specific_index(smu,
1880 CMN2ASIC_MAPPING_CLK,
1881 clk_type);
1882 if (clk_id < 0)
1883 return clk_id;
1884
1885 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1886
1887 ret = smu_cmn_send_smc_msg_with_param(smu,
1888 SMU_MSG_GetDpmFreqByIndex,
1889 param,
1890 &value);
1891 if (ret)
1892 return ret;
1893
1894 /*
1895 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1896 * now, we un-support it
1897 */
1898 *is_fine_grained_dpm = value & 0x80000000;
1899
1900 return 0;
1901 }
1902
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_dpm_table * single_dpm_table)1903 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1904 enum smu_clk_type clk_type,
1905 struct smu_dpm_table *single_dpm_table)
1906 {
1907 int ret = 0;
1908 uint32_t clk;
1909 int i;
1910 bool is_fine_grained;
1911
1912 ret = smu_v13_0_get_dpm_level_count(smu,
1913 clk_type,
1914 &single_dpm_table->count);
1915 if (ret) {
1916 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1917 return ret;
1918 }
1919
1920 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) {
1921 ret = smu_v13_0_get_fine_grained_status(smu, clk_type,
1922 &is_fine_grained);
1923 if (ret) {
1924 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1925 return ret;
1926 }
1927 if (is_fine_grained)
1928 single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
1929 }
1930
1931 for (i = 0; i < single_dpm_table->count; i++) {
1932 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1933 clk_type,
1934 i,
1935 &clk);
1936 if (ret) {
1937 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1938 return ret;
1939 }
1940
1941 single_dpm_table->dpm_levels[i].value = clk;
1942 single_dpm_table->dpm_levels[i].enabled = true;
1943 }
1944
1945 return 0;
1946 }
1947
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)1948 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1949 {
1950 struct amdgpu_device *adev = smu->adev;
1951
1952 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1953 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1954 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1955 }
1956
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)1957 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1958 {
1959 uint32_t width_level;
1960
1961 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1962 if (width_level > LINK_WIDTH_MAX)
1963 width_level = 0;
1964
1965 return link_width[width_level];
1966 }
1967
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)1968 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1969 {
1970 struct amdgpu_device *adev = smu->adev;
1971
1972 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1973 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1974 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1975 }
1976
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)1977 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1978 {
1979 uint32_t speed_level;
1980
1981 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1982 if (speed_level > LINK_SPEED_MAX)
1983 speed_level = 0;
1984
1985 return link_speed[speed_level];
1986 }
1987
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable,int inst)1988 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
1989 bool enable,
1990 int inst)
1991 {
1992 struct amdgpu_device *adev = smu->adev;
1993 int ret = 0;
1994
1995 if (adev->vcn.harvest_config & (1 << inst))
1996 return ret;
1997
1998 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1999 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2000 inst << 16U, NULL);
2001
2002 return ret;
2003 }
2004
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2005 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2006 bool enable)
2007 {
2008 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2009 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2010 0, NULL);
2011 }
2012
smu_v13_0_run_btc(struct smu_context * smu)2013 int smu_v13_0_run_btc(struct smu_context *smu)
2014 {
2015 int res;
2016
2017 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2018 if (res)
2019 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2020
2021 return res;
2022 }
2023
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2024 int smu_v13_0_gpo_control(struct smu_context *smu,
2025 bool enablement)
2026 {
2027 int res;
2028
2029 res = smu_cmn_send_smc_msg_with_param(smu,
2030 SMU_MSG_AllowGpo,
2031 enablement ? 1 : 0,
2032 NULL);
2033 if (res)
2034 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2035
2036 return res;
2037 }
2038
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2039 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2040 bool enablement)
2041 {
2042 struct amdgpu_device *adev = smu->adev;
2043 int ret = 0;
2044
2045 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2046 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2047 if (ret) {
2048 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2049 return ret;
2050 }
2051 }
2052
2053 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2054 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2055 if (ret) {
2056 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2057 return ret;
2058 }
2059 }
2060
2061 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2062 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2063 if (ret) {
2064 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2065 return ret;
2066 }
2067 }
2068
2069 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2070 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2071 if (ret) {
2072 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2073 return ret;
2074 }
2075 }
2076
2077 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2078 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2079 if (ret) {
2080 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2081 return ret;
2082 }
2083 }
2084
2085 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2086 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2087 if (ret) {
2088 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2089 return ret;
2090 }
2091 }
2092
2093 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2094 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2095 if (ret) {
2096 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2097 return ret;
2098 }
2099 }
2100
2101 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2102 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2103 if (ret) {
2104 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2105 return ret;
2106 }
2107 }
2108
2109 return ret;
2110 }
2111
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2112 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2113 bool enablement)
2114 {
2115 int ret = 0;
2116
2117 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2118 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2119
2120 return ret;
2121 }
2122
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2123 static int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2124 enum smu_baco_seq baco_seq)
2125 {
2126 struct smu_baco_context *smu_baco = &smu->smu_baco;
2127 int ret;
2128
2129 ret = smu_cmn_send_smc_msg_with_param(smu,
2130 SMU_MSG_ArmD3,
2131 baco_seq,
2132 NULL);
2133 if (ret)
2134 return ret;
2135
2136 if (baco_seq == BACO_SEQ_BAMACO ||
2137 baco_seq == BACO_SEQ_BACO)
2138 smu_baco->state = SMU_BACO_STATE_ENTER;
2139 else
2140 smu_baco->state = SMU_BACO_STATE_EXIT;
2141
2142 return 0;
2143 }
2144
smu_v13_0_baco_get_state(struct smu_context * smu)2145 static enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2146 {
2147 struct smu_baco_context *smu_baco = &smu->smu_baco;
2148
2149 return smu_baco->state;
2150 }
2151
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2152 static int smu_v13_0_baco_set_state(struct smu_context *smu,
2153 enum smu_baco_state state)
2154 {
2155 struct smu_baco_context *smu_baco = &smu->smu_baco;
2156 struct amdgpu_device *adev = smu->adev;
2157 int ret = 0;
2158
2159 if (smu_v13_0_baco_get_state(smu) == state)
2160 return 0;
2161
2162 if (state == SMU_BACO_STATE_ENTER) {
2163 ret = smu_cmn_send_smc_msg_with_param(smu,
2164 SMU_MSG_EnterBaco,
2165 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2166 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2167 NULL);
2168 } else {
2169 ret = smu_cmn_send_smc_msg(smu,
2170 SMU_MSG_ExitBaco,
2171 NULL);
2172 if (ret)
2173 return ret;
2174
2175 /* clear vbios scratch 6 and 7 for coming asic reinit */
2176 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2177 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2178 }
2179
2180 if (!ret)
2181 smu_baco->state = state;
2182
2183 return ret;
2184 }
2185
smu_v13_0_get_bamaco_support(struct smu_context * smu)2186 int smu_v13_0_get_bamaco_support(struct smu_context *smu)
2187 {
2188 struct smu_baco_context *smu_baco = &smu->smu_baco;
2189 int bamaco_support = 0;
2190
2191 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
2192 return 0;
2193
2194 if (smu_baco->maco_support)
2195 bamaco_support |= MACO_SUPPORT;
2196
2197 /* return true if ASIC is in BACO state already */
2198 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2199 return bamaco_support |= BACO_SUPPORT;
2200
2201 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2202 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2203 return 0;
2204
2205 return (bamaco_support |= BACO_SUPPORT);
2206 }
2207
smu_v13_0_baco_enter(struct smu_context * smu)2208 int smu_v13_0_baco_enter(struct smu_context *smu)
2209 {
2210 struct amdgpu_device *adev = smu->adev;
2211 int ret;
2212
2213 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2214 return smu_v13_0_baco_set_armd3_sequence(smu,
2215 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2216 BACO_SEQ_BAMACO : BACO_SEQ_BACO);
2217 } else {
2218 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
2219 if (!ret)
2220 usleep_range(10000, 11000);
2221
2222 return ret;
2223 }
2224 }
2225
smu_v13_0_baco_exit(struct smu_context * smu)2226 int smu_v13_0_baco_exit(struct smu_context *smu)
2227 {
2228 struct amdgpu_device *adev = smu->adev;
2229 int ret;
2230
2231 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2232 /* Wait for PMFW handling for the Dstate change */
2233 usleep_range(10000, 11000);
2234 ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2235 } else {
2236 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
2237 }
2238
2239 if (!ret)
2240 adev->gfx.is_poweron = false;
2241
2242 return ret;
2243 }
2244
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2245 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2246 {
2247 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2248 struct amdgpu_device *adev = smu->adev;
2249 int ret;
2250
2251 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2252 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
2253 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
2254 }
2255
2256 mutex_lock(&ctl->lock);
2257 ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu,
2258 ENABLE_IMU_ARG_GFXOFF_ENABLE);
2259 mutex_unlock(&ctl->lock);
2260
2261 return ret;
2262 }
2263
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2264 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2265 enum PP_OD_DPM_TABLE_COMMAND type,
2266 long input[], uint32_t size)
2267 {
2268 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2269 int ret = 0;
2270
2271 /* Only allowed in manual mode */
2272 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2273 return -EINVAL;
2274
2275 switch (type) {
2276 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2277 if (size != 2) {
2278 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2279 return -EINVAL;
2280 }
2281
2282 if (input[0] == 0) {
2283 if (input[1] < smu->gfx_default_hard_min_freq) {
2284 dev_warn(smu->adev->dev,
2285 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2286 input[1], smu->gfx_default_hard_min_freq);
2287 return -EINVAL;
2288 }
2289 smu->gfx_actual_hard_min_freq = input[1];
2290 } else if (input[0] == 1) {
2291 if (input[1] > smu->gfx_default_soft_max_freq) {
2292 dev_warn(smu->adev->dev,
2293 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2294 input[1], smu->gfx_default_soft_max_freq);
2295 return -EINVAL;
2296 }
2297 smu->gfx_actual_soft_max_freq = input[1];
2298 } else {
2299 return -EINVAL;
2300 }
2301 break;
2302 case PP_OD_RESTORE_DEFAULT_TABLE:
2303 if (size != 0) {
2304 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2305 return -EINVAL;
2306 }
2307 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2308 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2309 break;
2310 case PP_OD_COMMIT_DPM_TABLE:
2311 if (size != 0) {
2312 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2313 return -EINVAL;
2314 }
2315 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2316 dev_err(smu->adev->dev,
2317 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2318 smu->gfx_actual_hard_min_freq,
2319 smu->gfx_actual_soft_max_freq);
2320 return -EINVAL;
2321 }
2322
2323 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2324 smu->gfx_actual_hard_min_freq,
2325 NULL);
2326 if (ret) {
2327 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2328 return ret;
2329 }
2330
2331 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2332 smu->gfx_actual_soft_max_freq,
2333 NULL);
2334 if (ret) {
2335 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2336 return ret;
2337 }
2338 break;
2339 default:
2340 return -ENOSYS;
2341 }
2342
2343 return ret;
2344 }
2345
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2346 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2347 {
2348 struct smu_table_context *smu_table = &smu->smu_table;
2349
2350 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2351 smu_table->clocks_table, false);
2352 }
2353
smu_v13_0_init_msg_ctl(struct smu_context * smu,const struct cmn2asic_msg_mapping * message_map)2354 void smu_v13_0_init_msg_ctl(struct smu_context *smu,
2355 const struct cmn2asic_msg_mapping *message_map)
2356 {
2357 struct amdgpu_device *adev = smu->adev;
2358 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2359
2360 ctl->smu = smu;
2361 mutex_init(&ctl->lock);
2362 ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2363 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2364 ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2365 ctl->config.num_arg_regs = 1;
2366 ctl->ops = &smu_msg_v1_ops;
2367 ctl->default_timeout = adev->usec_timeout * 20;
2368 ctl->message_map = message_map;
2369 ctl->flags = 0;
2370 }
2371
smu_v13_0_mode1_reset(struct smu_context * smu)2372 int smu_v13_0_mode1_reset(struct smu_context *smu)
2373 {
2374 int ret = 0;
2375
2376 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2377 if (!ret)
2378 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2379
2380 return ret;
2381 }
2382
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2383 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2384 uint8_t pcie_gen_cap,
2385 uint8_t pcie_width_cap)
2386 {
2387 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2388 struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2389 int num_of_levels = pcie_table->lclk_levels;
2390 uint32_t smu_pcie_arg;
2391 int ret = 0;
2392 int i;
2393
2394 if (!num_of_levels)
2395 return 0;
2396
2397 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2398 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2399 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2400
2401 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2402 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2403
2404 /* Force all levels to use the same settings */
2405 for (i = 0; i < num_of_levels; i++) {
2406 pcie_table->pcie_gen[i] = pcie_gen_cap;
2407 pcie_table->pcie_lane[i] = pcie_width_cap;
2408 smu_pcie_arg = i << 16;
2409 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2410 smu_pcie_arg |= pcie_table->pcie_lane[i];
2411
2412 ret = smu_cmn_send_smc_msg_with_param(smu,
2413 SMU_MSG_OverridePcieParameters,
2414 smu_pcie_arg,
2415 NULL);
2416 if (ret)
2417 break;
2418 }
2419 } else {
2420 for (i = 0; i < num_of_levels; i++) {
2421 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
2422 pcie_table->pcie_lane[i] > pcie_width_cap) {
2423 pcie_table->pcie_gen[i] = pcie_gen_cap;
2424 pcie_table->pcie_lane[i] = pcie_width_cap;
2425 smu_pcie_arg = i << 16;
2426 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2427 smu_pcie_arg |= pcie_table->pcie_lane[i];
2428
2429 ret = smu_cmn_send_smc_msg_with_param(smu,
2430 SMU_MSG_OverridePcieParameters,
2431 smu_pcie_arg,
2432 NULL);
2433 if (ret)
2434 break;
2435 }
2436 }
2437 }
2438
2439 return ret;
2440 }
2441
smu_v13_0_disable_pmfw_state(struct smu_context * smu)2442 int smu_v13_0_disable_pmfw_state(struct smu_context *smu)
2443 {
2444 int ret;
2445 struct amdgpu_device *adev = smu->adev;
2446
2447 WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0);
2448
2449 ret = RREG32_PCIE(MP1_Public |
2450 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
2451
2452 return ret == 0 ? 0 : -EINVAL;
2453 }
2454
smu_v13_0_enable_uclk_shadow(struct smu_context * smu,bool enable)2455 int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)
2456 {
2457 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);
2458 }
2459
smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context * smu,struct freq_band_range * exclusion_ranges)2460 int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
2461 struct freq_band_range *exclusion_ranges)
2462 {
2463 WifiBandEntryTable_t wifi_bands;
2464 int valid_entries = 0;
2465 int ret, i;
2466
2467 memset(&wifi_bands, 0, sizeof(wifi_bands));
2468 for (i = 0; i < ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {
2469 if (!exclusion_ranges[i].start && !exclusion_ranges[i].end)
2470 break;
2471
2472 /* PMFW expects the inputs to be in Mhz unit */
2473 wifi_bands.WifiBandEntry[valid_entries].LowFreq =
2474 DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);
2475 wifi_bands.WifiBandEntry[valid_entries++].HighFreq =
2476 DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);
2477 }
2478 wifi_bands.WifiBandEntryNum = valid_entries;
2479
2480 /*
2481 * Per confirm with PMFW team, WifiBandEntryNum = 0
2482 * is a valid setting.
2483 *
2484 * Considering the scenarios below:
2485 * - At first the wifi device adds an exclusion range e.g. (2400,2500) to
2486 * BIOS and our driver gets notified. We will set WifiBandEntryNum = 1
2487 * and pass the WifiBandEntry (2400, 2500) to PMFW.
2488 *
2489 * - Later the wifi device removes the wifiband list added above and
2490 * our driver gets notified again. At this time, driver will set
2491 * WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.
2492 *
2493 * - PMFW may still need to do some uclk shadow update(e.g. switching
2494 * from shadow clock back to primary clock) on receiving this.
2495 */
2496 ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &wifi_bands, true);
2497 if (ret)
2498 dev_warn(smu->adev->dev, "Failed to set wifiband!");
2499
2500 return ret;
2501 }
2502
smu_v13_0_reset_custom_level(struct smu_context * smu)2503 void smu_v13_0_reset_custom_level(struct smu_context *smu)
2504 {
2505 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2506
2507 pstate_table->uclk_pstate.custom.min = 0;
2508 pstate_table->uclk_pstate.custom.max = 0;
2509 pstate_table->gfxclk_pstate.custom.min = 0;
2510 pstate_table->gfxclk_pstate.custom.max = 0;
2511 }
2512