1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99 #define SMU_13_0_6_DSCLK_THRESHOLD 140
100
101 #define MCA_BANK_IPID(_ip, _hwid, _type) \
102 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
103
104 #define SMU_CAP(x) SMU_13_0_6_CAPS_##x
105
106 enum smu_v13_0_6_caps {
107 SMU_CAP(DPM),
108 SMU_CAP(UNI_METRICS),
109 SMU_CAP(DPM_POLICY),
110 SMU_CAP(OTHER_END_METRICS),
111 SMU_CAP(SET_UCLK_MAX),
112 SMU_CAP(PCIE_METRICS),
113 SMU_CAP(HST_LIMIT_METRICS),
114 SMU_CAP(MCA_DEBUG_MODE),
115 SMU_CAP(PER_INST_METRICS),
116 SMU_CAP(CTF_LIMIT),
117 SMU_CAP(RMA_MSG),
118 SMU_CAP(ACA_SYND),
119 SMU_CAP(SDMA_RESET),
120 SMU_CAP(ALL),
121 };
122
123 struct mca_bank_ipid {
124 enum amdgpu_mca_ip ip;
125 uint16_t hwid;
126 uint16_t mcatype;
127 };
128
129 struct mca_ras_info {
130 enum amdgpu_ras_block blkid;
131 enum amdgpu_mca_ip ip;
132 int *err_code_array;
133 int err_code_count;
134 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
135 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
136 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
137 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
138 };
139
140 #define P2S_TABLE_ID_A 0x50325341
141 #define P2S_TABLE_ID_X 0x50325358
142 #define P2S_TABLE_ID_3 0x50325303
143
144 // clang-format off
145 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
146 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
147 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
148 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
149 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
150 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
151 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
152 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
153 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
154 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
155 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
156 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
157 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
158 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
159 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
160 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
161 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
162 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
163 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
164 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
165 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
166 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
167 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
168 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
169 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
170 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
171 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
172 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
173 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
174 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
175 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
176 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
177 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
178 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
179 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
180 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
181 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
182 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
183 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
184 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
185 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
186 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
187 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
188 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
189 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
190 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
191 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
192 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
193 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
194 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
195 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
196 MSG_MAP(SelectPstatePolicy, PPSMC_MSG_SelectPstatePolicy, 0),
197 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
198 };
199
200 // clang-format on
201 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
202 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
203 CLK_MAP(FCLK, PPCLK_FCLK),
204 CLK_MAP(UCLK, PPCLK_UCLK),
205 CLK_MAP(MCLK, PPCLK_UCLK),
206 CLK_MAP(DCLK, PPCLK_DCLK),
207 CLK_MAP(VCLK, PPCLK_VCLK),
208 CLK_MAP(LCLK, PPCLK_LCLK),
209 };
210
211 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
216 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
217 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
218 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
219 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
220 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
221 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
222 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
223 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
224 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
225 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
226 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
227 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
228 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
229 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
230 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
231 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
232 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
233 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
234 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
235 };
236
237 #define TABLE_PMSTATUSLOG 0
238 #define TABLE_SMU_METRICS 1
239 #define TABLE_I2C_COMMANDS 2
240 #define TABLE_COUNT 3
241
242 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
243 TAB_MAP(PMSTATUSLOG),
244 TAB_MAP(SMU_METRICS),
245 TAB_MAP(I2C_COMMANDS),
246 };
247
248 static const uint8_t smu_v13_0_6_throttler_map[] = {
249 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
250 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
251 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
252 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
253 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
254 };
255
256 struct PPTable_t {
257 uint32_t MaxSocketPowerLimit;
258 uint32_t MaxGfxclkFrequency;
259 uint32_t MinGfxclkFrequency;
260 uint32_t FclkFrequencyTable[4];
261 uint32_t UclkFrequencyTable[4];
262 uint32_t SocclkFrequencyTable[4];
263 uint32_t VclkFrequencyTable[4];
264 uint32_t DclkFrequencyTable[4];
265 uint32_t LclkFrequencyTable[4];
266 uint32_t MaxLclkDpmRange;
267 uint32_t MinLclkDpmRange;
268 uint64_t PublicSerialNumber_AID;
269 bool Init;
270 };
271
272 #define SMUQ10_TO_UINT(x) ((x) >> 10)
273 #define SMUQ10_FRAC(x) ((x) & 0x3ff)
274 #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
275 #define GET_METRIC_FIELD(field, flag) ((flag) ?\
276 (metrics_a->field) : (metrics_x->field))
277
278 struct smu_v13_0_6_dpm_map {
279 enum smu_clk_type clk_type;
280 uint32_t feature_num;
281 struct smu_13_0_dpm_table *dpm_table;
282 uint32_t *freq_table;
283 };
284
smu_v13_0_6_cap_set(struct smu_context * smu,enum smu_v13_0_6_caps cap)285 static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
286 enum smu_v13_0_6_caps cap)
287 {
288 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
289
290 dpm_context->caps |= BIT_ULL(cap);
291 }
292
smu_v13_0_6_cap_clear(struct smu_context * smu,enum smu_v13_0_6_caps cap)293 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
294 enum smu_v13_0_6_caps cap)
295 {
296 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
297
298 dpm_context->caps &= ~BIT_ULL(cap);
299 }
300
smu_v13_0_6_cap_supported(struct smu_context * smu,enum smu_v13_0_6_caps cap)301 static inline bool smu_v13_0_6_cap_supported(struct smu_context *smu,
302 enum smu_v13_0_6_caps cap)
303 {
304 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
305
306 return !!(dpm_context->caps & BIT_ULL(cap));
307 }
308
smu_v13_0_14_init_caps(struct smu_context * smu)309 static void smu_v13_0_14_init_caps(struct smu_context *smu)
310 {
311 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
312 SMU_CAP(UNI_METRICS),
313 SMU_CAP(SET_UCLK_MAX),
314 SMU_CAP(DPM_POLICY),
315 SMU_CAP(PCIE_METRICS),
316 SMU_CAP(CTF_LIMIT),
317 SMU_CAP(MCA_DEBUG_MODE),
318 SMU_CAP(RMA_MSG),
319 SMU_CAP(ACA_SYND) };
320 uint32_t fw_ver = smu->smc_fw_version;
321
322 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
323 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
324
325 if (fw_ver >= 0x05550E00)
326 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
327 if (fw_ver >= 0x05551000)
328 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
329 if (fw_ver >= 0x05550B00)
330 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
331 if (fw_ver >= 0x5551200)
332 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
333 }
334
smu_v13_0_12_init_caps(struct smu_context * smu)335 static void smu_v13_0_12_init_caps(struct smu_context *smu)
336 {
337 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
338 SMU_CAP(UNI_METRICS),
339 SMU_CAP(PCIE_METRICS),
340 SMU_CAP(CTF_LIMIT),
341 SMU_CAP(MCA_DEBUG_MODE),
342 SMU_CAP(RMA_MSG),
343 SMU_CAP(ACA_SYND) };
344 uint32_t fw_ver = smu->smc_fw_version;
345
346 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
347 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
348
349 if (fw_ver < 0x00561900)
350 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
351
352 if (fw_ver >= 0x00561700)
353 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
354 }
355
smu_v13_0_6_init_caps(struct smu_context * smu)356 static void smu_v13_0_6_init_caps(struct smu_context *smu)
357 {
358 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
359 SMU_CAP(UNI_METRICS),
360 SMU_CAP(SET_UCLK_MAX),
361 SMU_CAP(DPM_POLICY),
362 SMU_CAP(PCIE_METRICS),
363 SMU_CAP(CTF_LIMIT),
364 SMU_CAP(MCA_DEBUG_MODE),
365 SMU_CAP(RMA_MSG),
366 SMU_CAP(ACA_SYND) };
367 struct amdgpu_device *adev = smu->adev;
368 uint32_t fw_ver = smu->smc_fw_version;
369 uint32_t pgm = (fw_ver >> 24) & 0xFF;
370
371 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
372 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
373
374 if (fw_ver < 0x552F00)
375 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
376 if (fw_ver < 0x554500)
377 smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
378
379 if (adev->flags & AMD_IS_APU) {
380 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
381 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
382 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
383 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
384
385 if (fw_ver <= 0x4556900)
386 smu_v13_0_6_cap_clear(smu, SMU_CAP(UNI_METRICS));
387 if (fw_ver >= 0x04556F00)
388 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
389 if (fw_ver >= 0x04556A00)
390 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
391 } else {
392 if (fw_ver >= 0x557600)
393 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
394 if (fw_ver < 0x00556000)
395 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
396 if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
397 smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
398 if (fw_ver < 0x556300)
399 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
400 if (fw_ver < 0x554800)
401 smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
402 if (fw_ver >= 0x556F00)
403 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
404 if (fw_ver < 0x00555a00)
405 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
406 if (fw_ver < 0x00555600)
407 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
408 if (pgm == 0 && fw_ver >= 0x557900)
409 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
410 }
411 if (((pgm == 7) && (fw_ver >= 0x7550700)) ||
412 ((pgm == 0) && (fw_ver >= 0x00557900)) ||
413 ((pgm == 4) && (fw_ver >= 0x4557000)))
414 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
415 }
416
smu_v13_0_x_init_caps(struct smu_context * smu)417 static void smu_v13_0_x_init_caps(struct smu_context *smu)
418 {
419 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
420 case IP_VERSION(13, 0, 12):
421 return smu_v13_0_12_init_caps(smu);
422 case IP_VERSION(13, 0, 14):
423 return smu_v13_0_14_init_caps(smu);
424 default:
425 return smu_v13_0_6_init_caps(smu);
426 }
427 }
428
smu_v13_0_6_check_fw_version(struct smu_context * smu)429 static int smu_v13_0_6_check_fw_version(struct smu_context *smu)
430 {
431 int r;
432
433 r = smu_v13_0_check_fw_version(smu);
434 /* Initialize caps flags once fw version is fetched */
435 if (!r)
436 smu_v13_0_x_init_caps(smu);
437
438 return r;
439 }
440
smu_v13_0_6_init_microcode(struct smu_context * smu)441 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
442 {
443 const struct smc_firmware_header_v2_1 *v2_1;
444 const struct common_firmware_header *hdr;
445 struct amdgpu_firmware_info *ucode = NULL;
446 struct smc_soft_pptable_entry *entries;
447 struct amdgpu_device *adev = smu->adev;
448 uint32_t p2s_table_id = P2S_TABLE_ID_A;
449 int ret = 0, i, p2stable_count;
450 int var = (adev->pdev->device & 0xF);
451 char ucode_prefix[15];
452
453 /* No need to load P2S tables in IOV mode */
454 if (amdgpu_sriov_vf(adev))
455 return 0;
456
457 if (!(adev->flags & AMD_IS_APU)) {
458 p2s_table_id = P2S_TABLE_ID_X;
459 if (var == 0x5)
460 p2s_table_id = P2S_TABLE_ID_3;
461 }
462
463 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
464 sizeof(ucode_prefix));
465 ret = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
466 "amdgpu/%s.bin", ucode_prefix);
467 if (ret)
468 goto out;
469
470 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
471 amdgpu_ucode_print_smc_hdr(hdr);
472
473 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
474 * are used to carry p2s tables.
475 */
476 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
477 entries = (struct smc_soft_pptable_entry
478 *)((uint8_t *)v2_1 +
479 le32_to_cpu(v2_1->pptable_entry_offset));
480 p2stable_count = le32_to_cpu(v2_1->pptable_count);
481 for (i = 0; i < p2stable_count; i++) {
482 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
483 smu->pptable_firmware.data =
484 ((uint8_t *)v2_1 +
485 le32_to_cpu(entries[i].ppt_offset_bytes));
486 smu->pptable_firmware.size =
487 le32_to_cpu(entries[i].ppt_size_bytes);
488 break;
489 }
490 }
491
492 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
493 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
494 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
495 ucode->fw = &smu->pptable_firmware;
496 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
497 }
498
499 return 0;
500 out:
501 amdgpu_ucode_release(&adev->pm.fw);
502
503 return ret;
504 }
505
smu_v13_0_6_tables_init(struct smu_context * smu)506 static int smu_v13_0_6_tables_init(struct smu_context *smu)
507 {
508 struct smu_table_context *smu_table = &smu->smu_table;
509 struct smu_table *tables = smu_table->tables;
510 struct amdgpu_device *adev = smu->adev;
511
512 if (!(adev->flags & AMD_IS_APU))
513 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
514 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
515
516 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
517 max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)),
518 PAGE_SIZE,
519 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
520
521 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
522 PAGE_SIZE,
523 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
524
525 smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableX_t),
526 sizeof(MetricsTableA_t)), GFP_KERNEL);
527 if (!smu_table->metrics_table)
528 return -ENOMEM;
529 smu_table->metrics_time = 0;
530
531 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_7);
532 smu_table->gpu_metrics_table =
533 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
534 if (!smu_table->gpu_metrics_table) {
535 kfree(smu_table->metrics_table);
536 return -ENOMEM;
537 }
538
539 smu_table->driver_pptable =
540 kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
541 if (!smu_table->driver_pptable) {
542 kfree(smu_table->metrics_table);
543 kfree(smu_table->gpu_metrics_table);
544 return -ENOMEM;
545 }
546
547 return 0;
548 }
549
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)550 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
551 int policy)
552 {
553 struct amdgpu_device *adev = smu->adev;
554 int ret, param;
555
556 switch (policy) {
557 case SOC_PSTATE_DEFAULT:
558 param = 0;
559 break;
560 case SOC_PSTATE_0:
561 param = 1;
562 break;
563 case SOC_PSTATE_1:
564 param = 2;
565 break;
566 case SOC_PSTATE_2:
567 param = 3;
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SelectPstatePolicy,
574 param, NULL);
575
576 if (ret)
577 dev_err(adev->dev, "select soc pstate policy %d failed",
578 policy);
579
580 return ret;
581 }
582
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)583 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
584 {
585 struct amdgpu_device *adev = smu->adev;
586 int ret, param;
587
588 switch (level) {
589 case XGMI_PLPD_DEFAULT:
590 param = PPSMC_PLPD_MODE_DEFAULT;
591 break;
592 case XGMI_PLPD_OPTIMIZED:
593 param = PPSMC_PLPD_MODE_OPTIMIZED;
594 break;
595 case XGMI_PLPD_DISALLOW:
596 param = 0;
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 if (level == XGMI_PLPD_DISALLOW)
603 ret = smu_cmn_send_smc_msg_with_param(
604 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
605 else
606 /* change xgmi per-link power down policy */
607 ret = smu_cmn_send_smc_msg_with_param(
608 smu, SMU_MSG_SelectPLPDMode, param, NULL);
609
610 if (ret)
611 dev_err(adev->dev,
612 "select xgmi per-link power down policy %d failed\n",
613 level);
614
615 return ret;
616 }
617
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)618 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
619 {
620 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
621 struct smu_dpm_policy *policy;
622
623 smu_dpm->dpm_context =
624 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
625 if (!smu_dpm->dpm_context)
626 return -ENOMEM;
627 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
628
629 smu_dpm->dpm_policies =
630 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
631 if (!smu_dpm->dpm_policies) {
632 kfree(smu_dpm->dpm_context);
633 return -ENOMEM;
634 }
635
636 if (!(smu->adev->flags & AMD_IS_APU)) {
637 policy = &(smu_dpm->dpm_policies->policies[0]);
638
639 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
640 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
641 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
642 BIT(SOC_PSTATE_2);
643 policy->current_level = SOC_PSTATE_DEFAULT;
644 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
645 smu_cmn_generic_soc_policy_desc(policy);
646 smu_dpm->dpm_policies->policy_mask |=
647 BIT(PP_PM_POLICY_SOC_PSTATE);
648 }
649 policy = &(smu_dpm->dpm_policies->policies[1]);
650
651 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
652 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
653 BIT(XGMI_PLPD_OPTIMIZED);
654 policy->current_level = XGMI_PLPD_DEFAULT;
655 policy->set_policy = smu_v13_0_6_select_plpd_policy;
656 smu_cmn_generic_plpd_policy_desc(policy);
657 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
658
659 return 0;
660 }
661
smu_v13_0_6_init_smc_tables(struct smu_context * smu)662 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
663 {
664 int ret = 0;
665
666 ret = smu_v13_0_6_tables_init(smu);
667 if (ret)
668 return ret;
669
670 ret = smu_v13_0_6_allocate_dpm_context(smu);
671
672 return ret;
673 }
674
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)675 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
676 uint32_t *feature_mask,
677 uint32_t num)
678 {
679 if (num > 2)
680 return -EINVAL;
681
682 /* pptable will handle the features to enable */
683 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
684
685 return 0;
686 }
687
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)688 static int smu_v13_0_6_get_metrics_table(struct smu_context *smu,
689 void *metrics_table, bool bypass_cache)
690 {
691 struct smu_table_context *smu_table = &smu->smu_table;
692 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
693 struct smu_table *table = &smu_table->driver_table;
694 int ret;
695
696 if (bypass_cache || !smu_table->metrics_time ||
697 time_after(jiffies,
698 smu_table->metrics_time + msecs_to_jiffies(1))) {
699 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
700 if (ret) {
701 dev_info(smu->adev->dev,
702 "Failed to export SMU metrics table!\n");
703 return ret;
704 }
705
706 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
707 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
708
709 smu_table->metrics_time = jiffies;
710 }
711
712 if (metrics_table)
713 memcpy(metrics_table, smu_table->metrics_table, table_size);
714
715 return 0;
716 }
717
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)718 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
719 void *metrics, size_t max_size)
720 {
721 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
722 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
723 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
724 struct amdgpu_pm_metrics *pm_metrics = metrics;
725 uint32_t pmfw_version;
726 int ret;
727
728 if (!pm_metrics || !max_size)
729 return -EINVAL;
730
731 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
732 return -EOVERFLOW;
733
734 /* Don't use cached metrics data */
735 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
736 if (ret)
737 return ret;
738
739 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
740
741 memset(&pm_metrics->common_header, 0,
742 sizeof(pm_metrics->common_header));
743 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6))
744 pm_metrics->common_header.mp1_ip_discovery_version = IP_VERSION(13, 0, 6);
745 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
746 pm_metrics->common_header.mp1_ip_discovery_version = IP_VERSION(13, 0, 14);
747 pm_metrics->common_header.pmfw_version = pmfw_version;
748 pm_metrics->common_header.pmmetrics_version = table_version;
749 pm_metrics->common_header.structure_size =
750 sizeof(pm_metrics->common_header) + table_size;
751
752 return pm_metrics->common_header.structure_size;
753 }
754
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)755 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
756 {
757 struct smu_table_context *smu_table = &smu->smu_table;
758 MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
759 MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
760 struct PPTable_t *pptable =
761 (struct PPTable_t *)smu_table->driver_pptable;
762 bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
763 int ret, i, retry = 100;
764 uint32_t table_version;
765
766 /* Store one-time values in driver PPTable */
767 if (!pptable->Init) {
768 while (--retry) {
769 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
770 if (ret)
771 return ret;
772
773 /* Ensure that metrics have been updated */
774 if (GET_METRIC_FIELD(AccumulationCounter, flag))
775 break;
776
777 usleep_range(1000, 1100);
778 }
779
780 if (!retry)
781 return -ETIME;
782
783 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
784 &table_version);
785 if (ret)
786 return ret;
787 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
788 table_version;
789
790 pptable->MaxSocketPowerLimit =
791 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, flag));
792 pptable->MaxGfxclkFrequency =
793 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, flag));
794 pptable->MinGfxclkFrequency =
795 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, flag));
796
797 for (i = 0; i < 4; ++i) {
798 pptable->FclkFrequencyTable[i] =
799 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, flag)[i]);
800 pptable->UclkFrequencyTable[i] =
801 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, flag)[i]);
802 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
803 GET_METRIC_FIELD(SocclkFrequencyTable, flag)[i]);
804 pptable->VclkFrequencyTable[i] =
805 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, flag)[i]);
806 pptable->DclkFrequencyTable[i] =
807 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, flag)[i]);
808 pptable->LclkFrequencyTable[i] =
809 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, flag)[i]);
810 }
811
812 /* use AID0 serial number by default */
813 pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, flag)[0];
814
815 pptable->Init = true;
816 }
817
818 return 0;
819 }
820
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)821 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
822 enum smu_clk_type clk_type,
823 uint32_t *min, uint32_t *max)
824 {
825 struct smu_table_context *smu_table = &smu->smu_table;
826 struct PPTable_t *pptable =
827 (struct PPTable_t *)smu_table->driver_pptable;
828 uint32_t clock_limit = 0, param;
829 int ret = 0, clk_id = 0;
830
831 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
832 switch (clk_type) {
833 case SMU_MCLK:
834 case SMU_UCLK:
835 if (pptable->Init)
836 clock_limit = pptable->UclkFrequencyTable[0];
837 break;
838 case SMU_GFXCLK:
839 case SMU_SCLK:
840 if (pptable->Init)
841 clock_limit = pptable->MinGfxclkFrequency;
842 break;
843 case SMU_SOCCLK:
844 if (pptable->Init)
845 clock_limit = pptable->SocclkFrequencyTable[0];
846 break;
847 case SMU_FCLK:
848 if (pptable->Init)
849 clock_limit = pptable->FclkFrequencyTable[0];
850 break;
851 case SMU_VCLK:
852 if (pptable->Init)
853 clock_limit = pptable->VclkFrequencyTable[0];
854 break;
855 case SMU_DCLK:
856 if (pptable->Init)
857 clock_limit = pptable->DclkFrequencyTable[0];
858 break;
859 default:
860 break;
861 }
862
863 if (min)
864 *min = clock_limit;
865
866 if (max)
867 *max = clock_limit;
868
869 return 0;
870 }
871
872 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
873 clk_id = smu_cmn_to_asic_specific_index(
874 smu, CMN2ASIC_MAPPING_CLK, clk_type);
875 if (clk_id < 0) {
876 ret = -EINVAL;
877 goto failed;
878 }
879 param = (clk_id & 0xffff) << 16;
880 }
881
882 if (max) {
883 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
884 ret = smu_cmn_send_smc_msg(
885 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
886 else
887 ret = smu_cmn_send_smc_msg_with_param(
888 smu, SMU_MSG_GetMaxDpmFreq, param, max);
889 if (ret)
890 goto failed;
891 }
892
893 if (min) {
894 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
895 ret = smu_cmn_send_smc_msg(
896 smu, SMU_MSG_GetMinGfxclkFrequency, min);
897 else
898 ret = smu_cmn_send_smc_msg_with_param(
899 smu, SMU_MSG_GetMinDpmFreq, param, min);
900 }
901
902 failed:
903 return ret;
904 }
905
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)906 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
907 enum smu_clk_type clk_type,
908 uint32_t *levels)
909 {
910 int ret;
911
912 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
913 if (!ret)
914 ++(*levels);
915
916 return ret;
917 }
918
smu_v13_0_6_pm_policy_init(struct smu_context * smu)919 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
920 {
921 struct smu_dpm_policy *policy;
922
923 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
924 if (policy)
925 policy->current_level = SOC_PSTATE_DEFAULT;
926 }
927
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)928 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
929 {
930 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
931 struct smu_table_context *smu_table = &smu->smu_table;
932 struct smu_13_0_dpm_table *dpm_table = NULL;
933 struct PPTable_t *pptable =
934 (struct PPTable_t *)smu_table->driver_pptable;
935 uint32_t gfxclkmin, gfxclkmax, levels;
936 int ret = 0, i, j;
937 struct smu_v13_0_6_dpm_map dpm_map[] = {
938 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
939 &dpm_context->dpm_tables.soc_table,
940 pptable->SocclkFrequencyTable },
941 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
942 &dpm_context->dpm_tables.uclk_table,
943 pptable->UclkFrequencyTable },
944 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
945 &dpm_context->dpm_tables.fclk_table,
946 pptable->FclkFrequencyTable },
947 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
948 &dpm_context->dpm_tables.vclk_table,
949 pptable->VclkFrequencyTable },
950 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
951 &dpm_context->dpm_tables.dclk_table,
952 pptable->DclkFrequencyTable },
953 };
954
955 smu_v13_0_6_setup_driver_pptable(smu);
956
957 /* DPM policy not supported in older firmwares */
958 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
959 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
960
961 smu_dpm->dpm_policies->policy_mask &=
962 ~BIT(PP_PM_POLICY_SOC_PSTATE);
963 }
964
965 smu_v13_0_6_pm_policy_init(smu);
966 /* gfxclk dpm table setup */
967 dpm_table = &dpm_context->dpm_tables.gfx_table;
968 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
969 /* In the case of gfxclk, only fine-grained dpm is honored.
970 * Get min/max values from FW.
971 */
972 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
973 &gfxclkmin, &gfxclkmax);
974 if (ret)
975 return ret;
976
977 dpm_table->count = 2;
978 dpm_table->dpm_levels[0].value = gfxclkmin;
979 dpm_table->dpm_levels[0].enabled = true;
980 dpm_table->dpm_levels[1].value = gfxclkmax;
981 dpm_table->dpm_levels[1].enabled = true;
982 dpm_table->min = dpm_table->dpm_levels[0].value;
983 dpm_table->max = dpm_table->dpm_levels[1].value;
984 } else {
985 dpm_table->count = 1;
986 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
987 dpm_table->dpm_levels[0].enabled = true;
988 dpm_table->min = dpm_table->dpm_levels[0].value;
989 dpm_table->max = dpm_table->dpm_levels[0].value;
990 }
991
992 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
993 dpm_table = dpm_map[j].dpm_table;
994 levels = 1;
995 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
996 ret = smu_v13_0_6_get_dpm_level_count(
997 smu, dpm_map[j].clk_type, &levels);
998 if (ret)
999 return ret;
1000 }
1001 dpm_table->count = levels;
1002 for (i = 0; i < dpm_table->count; ++i) {
1003 dpm_table->dpm_levels[i].value =
1004 dpm_map[j].freq_table[i];
1005 dpm_table->dpm_levels[i].enabled = true;
1006
1007 }
1008 dpm_table->min = dpm_table->dpm_levels[0].value;
1009 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
1010
1011 }
1012
1013 return 0;
1014 }
1015
smu_v13_0_6_setup_pptable(struct smu_context * smu)1016 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
1017 {
1018 struct smu_table_context *table_context = &smu->smu_table;
1019
1020 /* TODO: PPTable is not available.
1021 * 1) Find an alternate way to get 'PPTable values' here.
1022 * 2) Check if there is SW CTF
1023 */
1024 table_context->thermal_controller_type = 0;
1025
1026 return 0;
1027 }
1028
smu_v13_0_6_check_fw_status(struct smu_context * smu)1029 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
1030 {
1031 struct amdgpu_device *adev = smu->adev;
1032 uint32_t mp1_fw_flags;
1033
1034 mp1_fw_flags =
1035 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
1036
1037 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
1038 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
1039 return 0;
1040
1041 return -EIO;
1042 }
1043
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)1044 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
1045 {
1046 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1047 struct smu_13_0_dpm_table *gfx_table =
1048 &dpm_context->dpm_tables.gfx_table;
1049 struct smu_13_0_dpm_table *mem_table =
1050 &dpm_context->dpm_tables.uclk_table;
1051 struct smu_13_0_dpm_table *soc_table =
1052 &dpm_context->dpm_tables.soc_table;
1053 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1054
1055 pstate_table->gfxclk_pstate.min = gfx_table->min;
1056 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1057 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1058 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1059
1060 pstate_table->uclk_pstate.min = mem_table->min;
1061 pstate_table->uclk_pstate.peak = mem_table->max;
1062 pstate_table->uclk_pstate.curr.min = mem_table->min;
1063 pstate_table->uclk_pstate.curr.max = mem_table->max;
1064
1065 pstate_table->socclk_pstate.min = soc_table->min;
1066 pstate_table->socclk_pstate.peak = soc_table->max;
1067 pstate_table->socclk_pstate.curr.min = soc_table->min;
1068 pstate_table->socclk_pstate.curr.max = soc_table->max;
1069
1070 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
1071 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
1072 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
1073 pstate_table->gfxclk_pstate.standard =
1074 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
1075 pstate_table->uclk_pstate.standard =
1076 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
1077 pstate_table->socclk_pstate.standard =
1078 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
1079 } else {
1080 pstate_table->gfxclk_pstate.standard =
1081 pstate_table->gfxclk_pstate.min;
1082 pstate_table->uclk_pstate.standard =
1083 pstate_table->uclk_pstate.min;
1084 pstate_table->socclk_pstate.standard =
1085 pstate_table->socclk_pstate.min;
1086 }
1087
1088 return 0;
1089 }
1090
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)1091 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
1092 struct pp_clock_levels_with_latency *clocks,
1093 struct smu_13_0_dpm_table *dpm_table)
1094 {
1095 int i, count;
1096
1097 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
1098 dpm_table->count;
1099 clocks->num_levels = count;
1100
1101 for (i = 0; i < count; i++) {
1102 clocks->data[i].clocks_in_khz =
1103 dpm_table->dpm_levels[i].value * 1000;
1104 clocks->data[i].latency_in_us = 0;
1105 }
1106
1107 return 0;
1108 }
1109
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)1110 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
1111 int32_t frequency2)
1112 {
1113 return (abs(frequency1 - frequency2) <= EPSILON);
1114 }
1115
smu_v13_0_6_get_throttler_status(struct smu_context * smu)1116 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
1117 {
1118 struct smu_power_context *smu_power = &smu->smu_power;
1119 struct smu_13_0_power_context *power_context = smu_power->power_context;
1120 uint32_t throttler_status = 0;
1121
1122 throttler_status = atomic_read(&power_context->throttle_status);
1123 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
1124
1125 return throttler_status;
1126 }
1127
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1128 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
1129 MetricsMember_t member,
1130 uint32_t *value)
1131 {
1132 struct smu_table_context *smu_table = &smu->smu_table;
1133 MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
1134 MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
1135 bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
1136 struct amdgpu_device *adev = smu->adev;
1137 int ret = 0;
1138 int xcc_id;
1139
1140 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
1141 if (ret)
1142 return ret;
1143
1144 /* For clocks with multiple instances, only report the first one */
1145 switch (member) {
1146 case METRICS_CURR_GFXCLK:
1147 case METRICS_AVERAGE_GFXCLK:
1148 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
1149 xcc_id = GET_INST(GC, 0);
1150 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]);
1151 } else {
1152 *value = 0;
1153 }
1154 break;
1155 case METRICS_CURR_SOCCLK:
1156 case METRICS_AVERAGE_SOCCLK:
1157 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[0]);
1158 break;
1159 case METRICS_CURR_UCLK:
1160 case METRICS_AVERAGE_UCLK:
1161 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag));
1162 break;
1163 case METRICS_CURR_VCLK:
1164 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[0]);
1165 break;
1166 case METRICS_CURR_DCLK:
1167 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[0]);
1168 break;
1169 case METRICS_CURR_FCLK:
1170 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, flag));
1171 break;
1172 case METRICS_AVERAGE_GFXACTIVITY:
1173 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag));
1174 break;
1175 case METRICS_AVERAGE_MEMACTIVITY:
1176 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag));
1177 break;
1178 case METRICS_CURR_SOCKETPOWER:
1179 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)) << 8;
1180 break;
1181 case METRICS_TEMPERATURE_HOTSPOT:
1182 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)) *
1183 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1184 break;
1185 case METRICS_TEMPERATURE_MEM:
1186 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)) *
1187 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1188 break;
1189 /* This is the max of all VRs and not just SOC VR.
1190 * No need to define another data type for the same.
1191 */
1192 case METRICS_TEMPERATURE_VRSOC:
1193 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)) *
1194 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1195 break;
1196 default:
1197 *value = UINT_MAX;
1198 break;
1199 }
1200
1201 return ret;
1202 }
1203
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1204 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1205 enum smu_clk_type clk_type,
1206 uint32_t *value)
1207 {
1208 MetricsMember_t member_type;
1209
1210 if (!value)
1211 return -EINVAL;
1212
1213 switch (clk_type) {
1214 case SMU_GFXCLK:
1215 member_type = METRICS_CURR_GFXCLK;
1216 break;
1217 case SMU_UCLK:
1218 member_type = METRICS_CURR_UCLK;
1219 break;
1220 case SMU_SOCCLK:
1221 member_type = METRICS_CURR_SOCCLK;
1222 break;
1223 case SMU_VCLK:
1224 member_type = METRICS_CURR_VCLK;
1225 break;
1226 case SMU_DCLK:
1227 member_type = METRICS_CURR_DCLK;
1228 break;
1229 case SMU_FCLK:
1230 member_type = METRICS_CURR_FCLK;
1231 break;
1232 default:
1233 return -EINVAL;
1234 }
1235
1236 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1237 }
1238
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1239 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1240 struct smu_13_0_dpm_table *single_dpm_table,
1241 uint32_t curr_clk, const char *clk_name)
1242 {
1243 struct pp_clock_levels_with_latency clocks;
1244 int i, ret, level = -1;
1245 uint32_t clk1, clk2;
1246
1247 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1248 if (ret) {
1249 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1250 clk_name);
1251 return ret;
1252 }
1253
1254 if (!clocks.num_levels)
1255 return -EINVAL;
1256
1257 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1258 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1259 for (i = 0; i < clocks.num_levels; i++)
1260 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1261 clocks.data[i].clocks_in_khz /
1262 1000);
1263
1264 } else {
1265 if ((clocks.num_levels == 1) ||
1266 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1267 level = 0;
1268 for (i = 0; i < clocks.num_levels; i++) {
1269 clk1 = clocks.data[i].clocks_in_khz / 1000;
1270
1271 if (i < (clocks.num_levels - 1))
1272 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1273
1274 if (curr_clk == clk1) {
1275 level = i;
1276 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1277 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1278 i :
1279 i + 1;
1280 }
1281
1282 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1283 clk1, (level == i) ? "*" : "");
1284 }
1285 }
1286
1287 return size;
1288 }
1289
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1290 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1291 enum smu_clk_type type, char *buf)
1292 {
1293 int now, size = 0;
1294 int ret = 0;
1295 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1296 struct smu_13_0_dpm_table *single_dpm_table;
1297 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1298 struct smu_13_0_dpm_context *dpm_context = NULL;
1299 uint32_t min_clk, max_clk;
1300
1301 smu_cmn_get_sysfs_buf(&buf, &size);
1302
1303 if (amdgpu_ras_intr_triggered()) {
1304 size += sysfs_emit_at(buf, size, "unavailable\n");
1305 return size;
1306 }
1307
1308 dpm_context = smu_dpm->dpm_context;
1309
1310 switch (type) {
1311 case SMU_OD_SCLK:
1312 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1313 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1314 pstate_table->gfxclk_pstate.curr.min,
1315 pstate_table->gfxclk_pstate.curr.max);
1316 break;
1317 case SMU_SCLK:
1318 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1319 &now);
1320 if (ret) {
1321 dev_err(smu->adev->dev,
1322 "Attempt to get current gfx clk Failed!");
1323 return ret;
1324 }
1325
1326 min_clk = pstate_table->gfxclk_pstate.curr.min;
1327 max_clk = pstate_table->gfxclk_pstate.curr.max;
1328
1329 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1330 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1331 now);
1332 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1333 min_clk);
1334 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1335 max_clk);
1336
1337 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1338 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1339 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1340 min_clk);
1341 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1342 now);
1343 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1344 max_clk);
1345 } else {
1346 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1347 min_clk,
1348 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1349 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1350 max_clk,
1351 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1352 }
1353
1354 break;
1355
1356 case SMU_OD_MCLK:
1357 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1358 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1359 pstate_table->uclk_pstate.curr.min,
1360 pstate_table->uclk_pstate.curr.max);
1361 break;
1362 case SMU_MCLK:
1363 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1364 &now);
1365 if (ret) {
1366 dev_err(smu->adev->dev,
1367 "Attempt to get current mclk Failed!");
1368 return ret;
1369 }
1370
1371 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1372
1373 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1374 now, "mclk");
1375
1376 case SMU_SOCCLK:
1377 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1378 &now);
1379 if (ret) {
1380 dev_err(smu->adev->dev,
1381 "Attempt to get current socclk Failed!");
1382 return ret;
1383 }
1384
1385 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1386
1387 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1388 now, "socclk");
1389
1390 case SMU_FCLK:
1391 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1392 &now);
1393 if (ret) {
1394 dev_err(smu->adev->dev,
1395 "Attempt to get current fclk Failed!");
1396 return ret;
1397 }
1398
1399 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1400
1401 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1402 now, "fclk");
1403
1404 case SMU_VCLK:
1405 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1406 &now);
1407 if (ret) {
1408 dev_err(smu->adev->dev,
1409 "Attempt to get current vclk Failed!");
1410 return ret;
1411 }
1412
1413 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1414
1415 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1416 now, "vclk");
1417
1418 case SMU_DCLK:
1419 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1420 &now);
1421 if (ret) {
1422 dev_err(smu->adev->dev,
1423 "Attempt to get current dclk Failed!");
1424 return ret;
1425 }
1426
1427 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1428
1429 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1430 now, "dclk");
1431
1432 default:
1433 break;
1434 }
1435
1436 return size;
1437 }
1438
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1439 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1440 uint32_t feature_mask, uint32_t level)
1441 {
1442 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1443 uint32_t freq;
1444 int ret = 0;
1445
1446 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1447 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1448 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1449 ret = smu_cmn_send_smc_msg_with_param(
1450 smu,
1451 (max ? SMU_MSG_SetSoftMaxGfxClk :
1452 SMU_MSG_SetSoftMinGfxclk),
1453 freq & 0xffff, NULL);
1454 if (ret) {
1455 dev_err(smu->adev->dev,
1456 "Failed to set soft %s gfxclk !\n",
1457 max ? "max" : "min");
1458 return ret;
1459 }
1460 }
1461
1462 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1463 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1464 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1465 .value;
1466 ret = smu_cmn_send_smc_msg_with_param(
1467 smu,
1468 (max ? SMU_MSG_SetSoftMaxByFreq :
1469 SMU_MSG_SetSoftMinByFreq),
1470 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1471 if (ret) {
1472 dev_err(smu->adev->dev,
1473 "Failed to set soft %s memclk !\n",
1474 max ? "max" : "min");
1475 return ret;
1476 }
1477 }
1478
1479 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1480 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1481 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1482 ret = smu_cmn_send_smc_msg_with_param(
1483 smu,
1484 (max ? SMU_MSG_SetSoftMaxByFreq :
1485 SMU_MSG_SetSoftMinByFreq),
1486 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1487 if (ret) {
1488 dev_err(smu->adev->dev,
1489 "Failed to set soft %s socclk !\n",
1490 max ? "max" : "min");
1491 return ret;
1492 }
1493 }
1494
1495 return ret;
1496 }
1497
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1498 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1499 enum smu_clk_type type, uint32_t mask)
1500 {
1501 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1502 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1503 uint32_t soft_min_level, soft_max_level;
1504 int ret = 0;
1505
1506 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1507 soft_max_level = mask ? (fls(mask) - 1) : 0;
1508
1509 switch (type) {
1510 case SMU_SCLK:
1511 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1512 if (soft_max_level >= single_dpm_table->count) {
1513 dev_err(smu->adev->dev,
1514 "Clock level specified %d is over max allowed %d\n",
1515 soft_max_level, single_dpm_table->count - 1);
1516 ret = -EINVAL;
1517 break;
1518 }
1519
1520 ret = smu_v13_0_6_upload_dpm_level(
1521 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1522 soft_min_level);
1523 if (ret) {
1524 dev_err(smu->adev->dev,
1525 "Failed to upload boot level to lowest!\n");
1526 break;
1527 }
1528
1529 ret = smu_v13_0_6_upload_dpm_level(
1530 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1531 soft_max_level);
1532 if (ret)
1533 dev_err(smu->adev->dev,
1534 "Failed to upload dpm max level to highest!\n");
1535
1536 break;
1537
1538 case SMU_MCLK:
1539 case SMU_SOCCLK:
1540 case SMU_FCLK:
1541 /*
1542 * Should not arrive here since smu_13_0_6 does not
1543 * support mclk/socclk/fclk softmin/softmax settings
1544 */
1545 ret = -EINVAL;
1546 break;
1547
1548 default:
1549 break;
1550 }
1551
1552 return ret;
1553 }
1554
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1555 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1556 enum amd_pp_sensors sensor,
1557 uint32_t *value)
1558 {
1559 int ret = 0;
1560
1561 if (!value)
1562 return -EINVAL;
1563
1564 switch (sensor) {
1565 case AMDGPU_PP_SENSOR_GPU_LOAD:
1566 ret = smu_v13_0_6_get_smu_metrics_data(
1567 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1568 break;
1569 case AMDGPU_PP_SENSOR_MEM_LOAD:
1570 ret = smu_v13_0_6_get_smu_metrics_data(
1571 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1572 break;
1573 default:
1574 dev_err(smu->adev->dev,
1575 "Invalid sensor for retrieving clock activity\n");
1576 return -EINVAL;
1577 }
1578
1579 return ret;
1580 }
1581
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1582 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1583 enum amd_pp_sensors sensor,
1584 uint32_t *value)
1585 {
1586 int ret = 0;
1587
1588 if (!value)
1589 return -EINVAL;
1590
1591 switch (sensor) {
1592 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1593 ret = smu_v13_0_6_get_smu_metrics_data(
1594 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1595 break;
1596 case AMDGPU_PP_SENSOR_MEM_TEMP:
1597 ret = smu_v13_0_6_get_smu_metrics_data(
1598 smu, METRICS_TEMPERATURE_MEM, value);
1599 break;
1600 default:
1601 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1602 return -EINVAL;
1603 }
1604
1605 return ret;
1606 }
1607
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1608 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1609 enum amd_pp_sensors sensor, void *data,
1610 uint32_t *size)
1611 {
1612 int ret = 0;
1613
1614 if (amdgpu_ras_intr_triggered())
1615 return 0;
1616
1617 if (!data || !size)
1618 return -EINVAL;
1619
1620 switch (sensor) {
1621 case AMDGPU_PP_SENSOR_MEM_LOAD:
1622 case AMDGPU_PP_SENSOR_GPU_LOAD:
1623 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1624 (uint32_t *)data);
1625 *size = 4;
1626 break;
1627 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1628 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1629 METRICS_CURR_SOCKETPOWER,
1630 (uint32_t *)data);
1631 *size = 4;
1632 break;
1633 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1634 case AMDGPU_PP_SENSOR_MEM_TEMP:
1635 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1636 (uint32_t *)data);
1637 *size = 4;
1638 break;
1639 case AMDGPU_PP_SENSOR_GFX_MCLK:
1640 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1641 smu, SMU_UCLK, (uint32_t *)data);
1642 /* the output clock frequency in 10K unit */
1643 *(uint32_t *)data *= 100;
1644 *size = 4;
1645 break;
1646 case AMDGPU_PP_SENSOR_GFX_SCLK:
1647 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1648 smu, SMU_GFXCLK, (uint32_t *)data);
1649 *(uint32_t *)data *= 100;
1650 *size = 4;
1651 break;
1652 case AMDGPU_PP_SENSOR_VDDGFX:
1653 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1654 *size = 4;
1655 break;
1656 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1657 default:
1658 ret = -EOPNOTSUPP;
1659 break;
1660 }
1661
1662 return ret;
1663 }
1664
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1665 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1666 uint32_t *current_power_limit,
1667 uint32_t *default_power_limit,
1668 uint32_t *max_power_limit,
1669 uint32_t *min_power_limit)
1670 {
1671 struct smu_table_context *smu_table = &smu->smu_table;
1672 struct PPTable_t *pptable =
1673 (struct PPTable_t *)smu_table->driver_pptable;
1674 uint32_t power_limit = 0;
1675 int ret;
1676
1677 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1678
1679 if (ret) {
1680 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1681 return -EINVAL;
1682 }
1683
1684 if (current_power_limit)
1685 *current_power_limit = power_limit;
1686 if (default_power_limit)
1687 *default_power_limit = power_limit;
1688
1689 if (max_power_limit) {
1690 *max_power_limit = pptable->MaxSocketPowerLimit;
1691 }
1692
1693 if (min_power_limit)
1694 *min_power_limit = 0;
1695 return 0;
1696 }
1697
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1698 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1699 enum smu_ppt_limit_type limit_type,
1700 uint32_t limit)
1701 {
1702 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1703 }
1704
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1705 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1706 struct amdgpu_irq_src *source,
1707 struct amdgpu_iv_entry *entry)
1708 {
1709 struct smu_context *smu = adev->powerplay.pp_handle;
1710 struct smu_power_context *smu_power = &smu->smu_power;
1711 struct smu_13_0_power_context *power_context = smu_power->power_context;
1712 uint32_t client_id = entry->client_id;
1713 uint32_t ctxid = entry->src_data[0];
1714 uint32_t src_id = entry->src_id;
1715 uint32_t data;
1716
1717 if (client_id == SOC15_IH_CLIENTID_MP1) {
1718 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1719 /* ACK SMUToHost interrupt */
1720 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1721 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1722 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1723 /*
1724 * ctxid is used to distinguish different events for SMCToHost
1725 * interrupt.
1726 */
1727 switch (ctxid) {
1728 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1729 /*
1730 * Increment the throttle interrupt counter
1731 */
1732 atomic64_inc(&smu->throttle_int_counter);
1733
1734 if (!atomic_read(&adev->throttling_logging_enabled))
1735 return 0;
1736
1737 /* This uses the new method which fixes the
1738 * incorrect throttling status reporting
1739 * through metrics table. For older FWs,
1740 * it will be ignored.
1741 */
1742 if (__ratelimit(&adev->throttling_logging_rs)) {
1743 atomic_set(
1744 &power_context->throttle_status,
1745 entry->src_data[1]);
1746 schedule_work(&smu->throttling_logging_work);
1747 }
1748 break;
1749 default:
1750 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1751 ctxid, client_id);
1752 break;
1753 }
1754 }
1755 }
1756
1757 return 0;
1758 }
1759
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1760 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1761 struct amdgpu_irq_src *source,
1762 unsigned tyep,
1763 enum amdgpu_interrupt_state state)
1764 {
1765 uint32_t val = 0;
1766
1767 switch (state) {
1768 case AMDGPU_IRQ_STATE_DISABLE:
1769 /* For MP1 SW irqs */
1770 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1771 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1772 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1773
1774 break;
1775 case AMDGPU_IRQ_STATE_ENABLE:
1776 /* For MP1 SW irqs */
1777 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1778 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1779 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1780 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1781
1782 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1783 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1784 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1785
1786 break;
1787 default:
1788 break;
1789 }
1790
1791 return 0;
1792 }
1793
1794 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1795 .set = smu_v13_0_6_set_irq_state,
1796 .process = smu_v13_0_6_irq_process,
1797 };
1798
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1799 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1800 {
1801 struct amdgpu_device *adev = smu->adev;
1802 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1803 int ret = 0;
1804
1805 if (amdgpu_sriov_vf(adev))
1806 return 0;
1807
1808 irq_src->num_types = 1;
1809 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1810
1811 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1812 IH_INTERRUPT_ID_TO_DRIVER,
1813 irq_src);
1814 if (ret)
1815 return ret;
1816
1817 return ret;
1818 }
1819
smu_v13_0_6_notify_unload(struct smu_context * smu)1820 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1821 {
1822 if (amdgpu_in_reset(smu->adev))
1823 return 0;
1824
1825 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1826 /* Ignore return, just intimate FW that driver is not going to be there */
1827 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1828
1829 return 0;
1830 }
1831
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1832 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1833 {
1834 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1835 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
1836 return 0;
1837
1838 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1839 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1840 NULL);
1841 }
1842
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1843 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1844 bool enable)
1845 {
1846 struct amdgpu_device *adev = smu->adev;
1847 int ret = 0;
1848
1849 if (amdgpu_sriov_vf(adev))
1850 return 0;
1851
1852 if (enable) {
1853 if (!(adev->flags & AMD_IS_APU))
1854 ret = smu_v13_0_system_features_control(smu, enable);
1855 } else {
1856 /* Notify FW that the device is no longer driver managed */
1857 smu_v13_0_6_notify_unload(smu);
1858 }
1859
1860 return ret;
1861 }
1862
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1863 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1864 uint32_t min,
1865 uint32_t max)
1866 {
1867 int ret;
1868
1869 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1870 max & 0xffff, NULL);
1871 if (ret)
1872 return ret;
1873
1874 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1875 min & 0xffff, NULL);
1876
1877 return ret;
1878 }
1879
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1880 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1881 enum amd_dpm_forced_level level)
1882 {
1883 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1884 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1885 struct smu_13_0_dpm_table *gfx_table =
1886 &dpm_context->dpm_tables.gfx_table;
1887 struct smu_13_0_dpm_table *uclk_table =
1888 &dpm_context->dpm_tables.uclk_table;
1889 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1890 int ret;
1891
1892 /* Disable determinism if switching to another mode */
1893 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1894 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1895 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1896 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1897 }
1898
1899 switch (level) {
1900 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1901 return 0;
1902
1903 case AMD_DPM_FORCED_LEVEL_AUTO:
1904 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
1905 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
1906 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1907 smu, gfx_table->min, gfx_table->max);
1908 if (ret)
1909 return ret;
1910
1911 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1912 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1913 }
1914
1915 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
1916 /* Min UCLK is not expected to be changed */
1917 ret = smu_v13_0_set_soft_freq_limited_range(
1918 smu, SMU_UCLK, 0, uclk_table->max, false);
1919 if (ret)
1920 return ret;
1921 pstate_table->uclk_pstate.curr.max = uclk_table->max;
1922 }
1923 pstate_table->uclk_pstate.custom.max = 0;
1924
1925 return 0;
1926 case AMD_DPM_FORCED_LEVEL_MANUAL:
1927 return 0;
1928 default:
1929 break;
1930 }
1931
1932 return -EINVAL;
1933 }
1934
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1935 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
1936 enum smu_clk_type clk_type,
1937 uint32_t min, uint32_t max,
1938 bool automatic)
1939 {
1940 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1941 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1942 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1943 struct amdgpu_device *adev = smu->adev;
1944 uint32_t min_clk;
1945 uint32_t max_clk;
1946 int ret = 0;
1947
1948 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
1949 clk_type != SMU_UCLK)
1950 return -EINVAL;
1951
1952 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
1953 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1954 return -EINVAL;
1955
1956 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1957 if (min >= max) {
1958 dev_err(smu->adev->dev,
1959 "Minimum clk should be less than the maximum allowed clock\n");
1960 return -EINVAL;
1961 }
1962
1963 if (clk_type == SMU_GFXCLK) {
1964 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1965 (max == pstate_table->gfxclk_pstate.curr.max))
1966 return 0;
1967
1968 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1969 smu, min, max);
1970 if (!ret) {
1971 pstate_table->gfxclk_pstate.curr.min = min;
1972 pstate_table->gfxclk_pstate.curr.max = max;
1973 }
1974 }
1975
1976 if (clk_type == SMU_UCLK) {
1977 if (max == pstate_table->uclk_pstate.curr.max)
1978 return 0;
1979 /* For VF, only allowed in FW versions 85.102 or greater */
1980 if (!smu_v13_0_6_cap_supported(smu,
1981 SMU_CAP(SET_UCLK_MAX)))
1982 return -EOPNOTSUPP;
1983 /* Only max clock limiting is allowed for UCLK */
1984 ret = smu_v13_0_set_soft_freq_limited_range(
1985 smu, SMU_UCLK, 0, max, false);
1986 if (!ret)
1987 pstate_table->uclk_pstate.curr.max = max;
1988 }
1989
1990 return ret;
1991 }
1992
1993 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1994 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1995 (max > dpm_context->dpm_tables.gfx_table.max)) {
1996 dev_warn(
1997 adev->dev,
1998 "Invalid max frequency %d MHz specified for determinism\n",
1999 max);
2000 return -EINVAL;
2001 }
2002
2003 /* Restore default min/max clocks and enable determinism */
2004 min_clk = dpm_context->dpm_tables.gfx_table.min;
2005 max_clk = dpm_context->dpm_tables.gfx_table.max;
2006 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
2007 max_clk);
2008 if (!ret) {
2009 usleep_range(500, 1000);
2010 ret = smu_cmn_send_smc_msg_with_param(
2011 smu, SMU_MSG_EnableDeterminism, max, NULL);
2012 if (ret) {
2013 dev_err(adev->dev,
2014 "Failed to enable determinism at GFX clock %d MHz\n",
2015 max);
2016 } else {
2017 pstate_table->gfxclk_pstate.curr.min = min_clk;
2018 pstate_table->gfxclk_pstate.curr.max = max;
2019 }
2020 }
2021 }
2022
2023 return ret;
2024 }
2025
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2026 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
2027 enum PP_OD_DPM_TABLE_COMMAND type,
2028 long input[], uint32_t size)
2029 {
2030 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2031 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2032 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2033 uint32_t min_clk;
2034 uint32_t max_clk;
2035 int ret = 0;
2036
2037 /* Only allowed in manual or determinism mode */
2038 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2039 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2040 return -EINVAL;
2041
2042 switch (type) {
2043 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2044 if (size != 2) {
2045 dev_err(smu->adev->dev,
2046 "Input parameter number not correct\n");
2047 return -EINVAL;
2048 }
2049
2050 if (input[0] == 0) {
2051 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
2052 dev_warn(
2053 smu->adev->dev,
2054 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
2055 input[1],
2056 dpm_context->dpm_tables.gfx_table.min);
2057 pstate_table->gfxclk_pstate.custom.min =
2058 pstate_table->gfxclk_pstate.curr.min;
2059 return -EINVAL;
2060 }
2061
2062 pstate_table->gfxclk_pstate.custom.min = input[1];
2063 } else if (input[0] == 1) {
2064 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
2065 dev_warn(
2066 smu->adev->dev,
2067 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2068 input[1],
2069 dpm_context->dpm_tables.gfx_table.max);
2070 pstate_table->gfxclk_pstate.custom.max =
2071 pstate_table->gfxclk_pstate.curr.max;
2072 return -EINVAL;
2073 }
2074
2075 pstate_table->gfxclk_pstate.custom.max = input[1];
2076 } else {
2077 return -EINVAL;
2078 }
2079 break;
2080 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2081 if (size != 2) {
2082 dev_err(smu->adev->dev,
2083 "Input parameter number not correct\n");
2084 return -EINVAL;
2085 }
2086
2087 if (!smu_cmn_feature_is_enabled(smu,
2088 SMU_FEATURE_DPM_UCLK_BIT)) {
2089 dev_warn(smu->adev->dev,
2090 "UCLK_LIMITS setting not supported!\n");
2091 return -EOPNOTSUPP;
2092 }
2093
2094 if (input[0] == 0) {
2095 dev_info(smu->adev->dev,
2096 "Setting min UCLK level is not supported");
2097 return -EINVAL;
2098 } else if (input[0] == 1) {
2099 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
2100 dev_warn(
2101 smu->adev->dev,
2102 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2103 input[1],
2104 dpm_context->dpm_tables.uclk_table.max);
2105 pstate_table->uclk_pstate.custom.max =
2106 pstate_table->uclk_pstate.curr.max;
2107 return -EINVAL;
2108 }
2109
2110 pstate_table->uclk_pstate.custom.max = input[1];
2111 }
2112 break;
2113
2114 case PP_OD_RESTORE_DEFAULT_TABLE:
2115 if (size != 0) {
2116 dev_err(smu->adev->dev,
2117 "Input parameter number not correct\n");
2118 return -EINVAL;
2119 } else {
2120 /* Use the default frequencies for manual and determinism mode */
2121 min_clk = dpm_context->dpm_tables.gfx_table.min;
2122 max_clk = dpm_context->dpm_tables.gfx_table.max;
2123
2124 ret = smu_v13_0_6_set_soft_freq_limited_range(
2125 smu, SMU_GFXCLK, min_clk, max_clk, false);
2126
2127 if (ret)
2128 return ret;
2129
2130 min_clk = dpm_context->dpm_tables.uclk_table.min;
2131 max_clk = dpm_context->dpm_tables.uclk_table.max;
2132 ret = smu_v13_0_6_set_soft_freq_limited_range(
2133 smu, SMU_UCLK, min_clk, max_clk, false);
2134 if (ret)
2135 return ret;
2136 pstate_table->uclk_pstate.custom.max = 0;
2137 }
2138 break;
2139 case PP_OD_COMMIT_DPM_TABLE:
2140 if (size != 0) {
2141 dev_err(smu->adev->dev,
2142 "Input parameter number not correct\n");
2143 return -EINVAL;
2144 } else {
2145 if (!pstate_table->gfxclk_pstate.custom.min)
2146 pstate_table->gfxclk_pstate.custom.min =
2147 pstate_table->gfxclk_pstate.curr.min;
2148
2149 if (!pstate_table->gfxclk_pstate.custom.max)
2150 pstate_table->gfxclk_pstate.custom.max =
2151 pstate_table->gfxclk_pstate.curr.max;
2152
2153 min_clk = pstate_table->gfxclk_pstate.custom.min;
2154 max_clk = pstate_table->gfxclk_pstate.custom.max;
2155
2156 ret = smu_v13_0_6_set_soft_freq_limited_range(
2157 smu, SMU_GFXCLK, min_clk, max_clk, false);
2158
2159 if (ret)
2160 return ret;
2161
2162 if (!pstate_table->uclk_pstate.custom.max)
2163 return 0;
2164
2165 min_clk = pstate_table->uclk_pstate.curr.min;
2166 max_clk = pstate_table->uclk_pstate.custom.max;
2167 return smu_v13_0_6_set_soft_freq_limited_range(
2168 smu, SMU_UCLK, min_clk, max_clk, false);
2169 }
2170 break;
2171 default:
2172 return -ENOSYS;
2173 }
2174
2175 return ret;
2176 }
2177
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2178 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2179 uint64_t *feature_mask)
2180 {
2181 int ret;
2182
2183 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2184
2185 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
2186 *feature_mask = 0;
2187 ret = 0;
2188 }
2189
2190 return ret;
2191 }
2192
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2193 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2194 {
2195 int ret;
2196 uint64_t feature_enabled;
2197
2198 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2199
2200 if (ret)
2201 return false;
2202
2203 return !!(feature_enabled & SMC_DPM_FEATURE);
2204 }
2205
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2206 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2207 void *table_data)
2208 {
2209 struct smu_table_context *smu_table = &smu->smu_table;
2210 struct smu_table *table = &smu_table->driver_table;
2211 struct amdgpu_device *adev = smu->adev;
2212 uint32_t table_size;
2213 int ret = 0;
2214
2215 if (!table_data)
2216 return -EINVAL;
2217
2218 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2219
2220 memcpy(table->cpu_addr, table_data, table_size);
2221 /* Flush hdp cache */
2222 amdgpu_asic_flush_hdp(adev, NULL);
2223 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2224 NULL);
2225
2226 return ret;
2227 }
2228
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2229 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2230 struct i2c_msg *msg, int num_msgs)
2231 {
2232 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2233 struct amdgpu_device *adev = smu_i2c->adev;
2234 struct smu_context *smu = adev->powerplay.pp_handle;
2235 struct smu_table_context *smu_table = &smu->smu_table;
2236 struct smu_table *table = &smu_table->driver_table;
2237 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2238 int i, j, r, c;
2239 u16 dir;
2240
2241 if (!adev->pm.dpm_enabled)
2242 return -EBUSY;
2243
2244 req = kzalloc(sizeof(*req), GFP_KERNEL);
2245 if (!req)
2246 return -ENOMEM;
2247
2248 req->I2CcontrollerPort = smu_i2c->port;
2249 req->I2CSpeed = I2C_SPEED_FAST_400K;
2250 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2251 dir = msg[0].flags & I2C_M_RD;
2252
2253 for (c = i = 0; i < num_msgs; i++) {
2254 for (j = 0; j < msg[i].len; j++, c++) {
2255 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2256
2257 if (!(msg[i].flags & I2C_M_RD)) {
2258 /* write */
2259 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2260 cmd->ReadWriteData = msg[i].buf[j];
2261 }
2262
2263 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2264 /* The direction changes.
2265 */
2266 dir = msg[i].flags & I2C_M_RD;
2267 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2268 }
2269
2270 req->NumCmds++;
2271
2272 /*
2273 * Insert STOP if we are at the last byte of either last
2274 * message for the transaction or the client explicitly
2275 * requires a STOP at this particular message.
2276 */
2277 if ((j == msg[i].len - 1) &&
2278 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2279 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2280 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2281 }
2282 }
2283 }
2284 mutex_lock(&adev->pm.mutex);
2285 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2286 if (r) {
2287 /* Retry once, in case of an i2c collision */
2288 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2289 if (r)
2290 goto fail;
2291 }
2292
2293 for (c = i = 0; i < num_msgs; i++) {
2294 if (!(msg[i].flags & I2C_M_RD)) {
2295 c += msg[i].len;
2296 continue;
2297 }
2298 for (j = 0; j < msg[i].len; j++, c++) {
2299 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2300
2301 msg[i].buf[j] = cmd->ReadWriteData;
2302 }
2303 }
2304 r = num_msgs;
2305 fail:
2306 mutex_unlock(&adev->pm.mutex);
2307 kfree(req);
2308 return r;
2309 }
2310
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2311 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2312 {
2313 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2314 }
2315
2316 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2317 .master_xfer = smu_v13_0_6_i2c_xfer,
2318 .functionality = smu_v13_0_6_i2c_func,
2319 };
2320
2321 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2322 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2323 .max_read_len = MAX_SW_I2C_COMMANDS,
2324 .max_write_len = MAX_SW_I2C_COMMANDS,
2325 .max_comb_1st_msg_len = 2,
2326 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2327 };
2328
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2329 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2330 {
2331 struct amdgpu_device *adev = smu->adev;
2332 int res, i;
2333
2334 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2335 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2336 struct i2c_adapter *control = &smu_i2c->adapter;
2337
2338 smu_i2c->adev = adev;
2339 smu_i2c->port = i;
2340 mutex_init(&smu_i2c->mutex);
2341 control->owner = THIS_MODULE;
2342 control->dev.parent = &adev->pdev->dev;
2343 control->algo = &smu_v13_0_6_i2c_algo;
2344 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2345 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2346 i2c_set_adapdata(control, smu_i2c);
2347
2348 res = i2c_add_adapter(control);
2349 if (res) {
2350 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2351 goto Out_err;
2352 }
2353 }
2354
2355 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2356 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2357
2358 return 0;
2359 Out_err:
2360 for ( ; i >= 0; i--) {
2361 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2362 struct i2c_adapter *control = &smu_i2c->adapter;
2363
2364 i2c_del_adapter(control);
2365 }
2366 return res;
2367 }
2368
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2369 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2370 {
2371 struct amdgpu_device *adev = smu->adev;
2372 int i;
2373
2374 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2375 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2376 struct i2c_adapter *control = &smu_i2c->adapter;
2377
2378 i2c_del_adapter(control);
2379 }
2380 adev->pm.ras_eeprom_i2c_bus = NULL;
2381 adev->pm.fru_eeprom_i2c_bus = NULL;
2382 }
2383
smu_v13_0_6_get_unique_id(struct smu_context * smu)2384 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2385 {
2386 struct amdgpu_device *adev = smu->adev;
2387 struct smu_table_context *smu_table = &smu->smu_table;
2388 struct PPTable_t *pptable =
2389 (struct PPTable_t *)smu_table->driver_pptable;
2390
2391 adev->unique_id = pptable->PublicSerialNumber_AID;
2392 }
2393
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2394 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2395 {
2396 /* smu_13_0_6 does not support baco */
2397
2398 return 0;
2399 }
2400
2401 static const char *const throttling_logging_label[] = {
2402 [THROTTLER_PROCHOT_BIT] = "Prochot",
2403 [THROTTLER_PPT_BIT] = "PPT",
2404 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2405 [THROTTLER_THERMAL_VR_BIT] = "VR",
2406 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2407 };
2408
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2409 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2410 {
2411 int throttler_idx, throttling_events = 0, buf_idx = 0;
2412 struct amdgpu_device *adev = smu->adev;
2413 uint32_t throttler_status;
2414 char log_buf[256];
2415
2416 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2417 if (!throttler_status)
2418 return;
2419
2420 memset(log_buf, 0, sizeof(log_buf));
2421 for (throttler_idx = 0;
2422 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2423 throttler_idx++) {
2424 if (throttler_status & (1U << throttler_idx)) {
2425 throttling_events++;
2426 buf_idx += snprintf(
2427 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2428 "%s%s", throttling_events > 1 ? " and " : "",
2429 throttling_logging_label[throttler_idx]);
2430 if (buf_idx >= sizeof(log_buf)) {
2431 dev_err(adev->dev, "buffer overflow!\n");
2432 log_buf[sizeof(log_buf) - 1] = '\0';
2433 break;
2434 }
2435 }
2436 }
2437
2438 dev_warn(adev->dev,
2439 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2440 log_buf);
2441 kgd2kfd_smi_event_throttle(
2442 smu->adev->kfd.dev,
2443 smu_cmn_get_indep_throttler_status(throttler_status,
2444 smu_v13_0_6_throttler_map));
2445 }
2446
2447 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2448 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2449 {
2450 struct amdgpu_device *adev = smu->adev;
2451
2452 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2453 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2454 }
2455
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2456 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2457 {
2458 struct amdgpu_device *adev = smu->adev;
2459 uint32_t speed_level;
2460 uint32_t esm_ctrl;
2461
2462 /* TODO: confirm this on real target */
2463 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2464 if ((esm_ctrl >> 15) & 0x1)
2465 return (((esm_ctrl >> 8) & 0x7F) + 128);
2466
2467 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2468 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2469 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2470 if (speed_level > LINK_SPEED_MAX)
2471 speed_level = 0;
2472
2473 return pcie_gen_to_speed(speed_level + 1);
2474 }
2475
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2476 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2477 {
2478 struct smu_table_context *smu_table = &smu->smu_table;
2479 struct gpu_metrics_v1_7 *gpu_metrics =
2480 (struct gpu_metrics_v1_7 *)smu_table->gpu_metrics_table;
2481 bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
2482 int ret = 0, xcc_id, inst, i, j, k, idx;
2483 struct amdgpu_device *adev = smu->adev;
2484 MetricsTableX_t *metrics_x;
2485 MetricsTableA_t *metrics_a;
2486 struct amdgpu_xcp *xcp;
2487 u16 link_width_level;
2488 u32 inst_mask;
2489 bool per_inst;
2490
2491 metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL);
2492 ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true);
2493 if (ret) {
2494 kfree(metrics_x);
2495 return ret;
2496 }
2497
2498 metrics_a = (MetricsTableA_t *)metrics_x;
2499
2500 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 7);
2501
2502 gpu_metrics->temperature_hotspot =
2503 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag));
2504 /* Individual HBM stack temperature is not reported */
2505 gpu_metrics->temperature_mem =
2506 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag));
2507 /* Reports max temperature of all voltage rails */
2508 gpu_metrics->temperature_vrsoc =
2509 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag));
2510
2511 gpu_metrics->average_gfx_activity =
2512 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag));
2513 gpu_metrics->average_umc_activity =
2514 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag));
2515
2516 gpu_metrics->mem_max_bandwidth =
2517 SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, flag));
2518
2519 gpu_metrics->curr_socket_power =
2520 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag));
2521 /* Energy counter reported in 15.259uJ (2^-16) units */
2522 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, flag);
2523
2524 for (i = 0; i < MAX_GFX_CLKS; i++) {
2525 xcc_id = GET_INST(GC, i);
2526 if (xcc_id >= 0)
2527 gpu_metrics->current_gfxclk[i] =
2528 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]);
2529
2530 if (i < MAX_CLKS) {
2531 gpu_metrics->current_socclk[i] =
2532 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[i]);
2533 inst = GET_INST(VCN, i);
2534 if (inst >= 0) {
2535 gpu_metrics->current_vclk0[i] =
2536 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[inst]);
2537 gpu_metrics->current_dclk0[i] =
2538 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[inst]);
2539 }
2540 }
2541 }
2542
2543 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag));
2544
2545 /* Total accumulated cycle counter */
2546 gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, flag);
2547
2548 /* Accumulated throttler residencies */
2549 gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, flag);
2550 gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, flag);
2551 gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, flag);
2552 gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, flag);
2553 gpu_metrics->hbm_thm_residency_acc = GET_METRIC_FIELD(HbmThmResidencyAcc, flag);
2554
2555 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2556 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0);
2557
2558 if (!(adev->flags & AMD_IS_APU)) {
2559 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2560 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2561 * for pf from registers
2562 */
2563 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
2564 gpu_metrics->pcie_link_width = metrics_x->PCIeLinkWidth;
2565 gpu_metrics->pcie_link_speed =
2566 pcie_gen_to_speed(metrics_x->PCIeLinkSpeed);
2567 } else if (!amdgpu_sriov_vf(adev)) {
2568 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2569 if (link_width_level > MAX_LINK_WIDTH)
2570 link_width_level = 0;
2571
2572 gpu_metrics->pcie_link_width =
2573 DECODE_LANE_WIDTH(link_width_level);
2574 gpu_metrics->pcie_link_speed =
2575 smu_v13_0_6_get_current_pcie_link_speed(smu);
2576 }
2577
2578 gpu_metrics->pcie_bandwidth_acc =
2579 SMUQ10_ROUND(metrics_x->PcieBandwidthAcc[0]);
2580 gpu_metrics->pcie_bandwidth_inst =
2581 SMUQ10_ROUND(metrics_x->PcieBandwidth[0]);
2582 gpu_metrics->pcie_l0_to_recov_count_acc =
2583 metrics_x->PCIeL0ToRecoveryCountAcc;
2584 gpu_metrics->pcie_replay_count_acc =
2585 metrics_x->PCIenReplayAAcc;
2586 gpu_metrics->pcie_replay_rover_count_acc =
2587 metrics_x->PCIenReplayARolloverCountAcc;
2588 gpu_metrics->pcie_nak_sent_count_acc =
2589 metrics_x->PCIeNAKSentCountAcc;
2590 gpu_metrics->pcie_nak_rcvd_count_acc =
2591 metrics_x->PCIeNAKReceivedCountAcc;
2592 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
2593 gpu_metrics->pcie_lc_perf_other_end_recovery =
2594 metrics_x->PCIeOtherEndRecoveryAcc;
2595
2596 }
2597
2598 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2599
2600 gpu_metrics->gfx_activity_acc =
2601 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, flag));
2602 gpu_metrics->mem_activity_acc =
2603 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, flag));
2604
2605 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2606 gpu_metrics->xgmi_read_data_acc[i] =
2607 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, flag)[i]);
2608 gpu_metrics->xgmi_write_data_acc[i] =
2609 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]);
2610 ret = amdgpu_get_xgmi_link_status(adev, i);
2611 if (ret >= 0)
2612 gpu_metrics->xgmi_link_status[i] = ret;
2613 }
2614
2615 gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
2616
2617 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2618
2619 for_each_xcp(adev->xcp_mgr, xcp, i) {
2620 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2621 idx = 0;
2622 for_each_inst(k, inst_mask) {
2623 /* Both JPEG and VCN has same instances */
2624 inst = GET_INST(VCN, k);
2625
2626 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
2627 gpu_metrics->xcp_stats[i].jpeg_busy
2628 [(idx * adev->jpeg.num_jpeg_rings) + j] =
2629 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag)
2630 [(inst * adev->jpeg.num_jpeg_rings) + j]);
2631 }
2632 gpu_metrics->xcp_stats[i].vcn_busy[idx] =
2633 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]);
2634 idx++;
2635
2636 }
2637
2638 if (per_inst) {
2639 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2640 idx = 0;
2641 for_each_inst(k, inst_mask) {
2642 inst = GET_INST(GC, k);
2643 gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
2644 SMUQ10_ROUND(metrics_x->GfxBusy[inst]);
2645 gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
2646 SMUQ10_ROUND(metrics_x->GfxBusyAcc[inst]);
2647
2648 if (smu_v13_0_6_cap_supported(
2649 smu, SMU_CAP(HST_LIMIT_METRICS)))
2650 gpu_metrics->xcp_stats[i].gfx_below_host_limit_acc[idx] =
2651 SMUQ10_ROUND(metrics_x->GfxclkBelowHostLimitAcc
2652 [inst]);
2653 idx++;
2654 }
2655 }
2656 }
2657
2658 gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag));
2659 gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, flag));
2660
2661 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag);
2662
2663 *table = (void *)gpu_metrics;
2664 kfree(metrics_x);
2665
2666 return sizeof(*gpu_metrics);
2667 }
2668
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2669 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2670 {
2671 struct amdgpu_device *adev = smu->adev;
2672 int i;
2673
2674 for (i = 0; i < 16; i++)
2675 pci_write_config_dword(adev->pdev, i * 4,
2676 adev->pdev->saved_config_space[i]);
2677 pci_restore_msi_state(adev->pdev);
2678 }
2679
smu_v13_0_6_mode2_reset(struct smu_context * smu)2680 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2681 {
2682 int ret = 0, index;
2683 struct amdgpu_device *adev = smu->adev;
2684 int timeout = 10;
2685
2686 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2687 SMU_MSG_GfxDeviceDriverReset);
2688 if (index < 0)
2689 return index;
2690
2691 mutex_lock(&smu->message_lock);
2692
2693 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2694 SMU_RESET_MODE_2);
2695
2696 /* Reset takes a bit longer, wait for 200ms. */
2697 msleep(200);
2698
2699 dev_dbg(smu->adev->dev, "restore config space...\n");
2700 /* Restore the config space saved during init */
2701 amdgpu_device_load_pci_state(adev->pdev);
2702
2703 /* Certain platforms have switches which assign virtual BAR values to
2704 * devices. OS uses the virtual BAR values and device behind the switch
2705 * is assgined another BAR value. When device's config space registers
2706 * are queried, switch returns the virtual BAR values. When mode-2 reset
2707 * is performed, switch is unaware of it, and will continue to return
2708 * the same virtual values to the OS.This affects
2709 * pci_restore_config_space() API as it doesn't write the value saved if
2710 * the current value read from config space is the same as what is
2711 * saved. As a workaround, make sure the config space is restored
2712 * always.
2713 */
2714 if (!(adev->flags & AMD_IS_APU))
2715 smu_v13_0_6_restore_pci_config(smu);
2716
2717 dev_dbg(smu->adev->dev, "wait for reset ack\n");
2718 do {
2719 ret = smu_cmn_wait_for_response(smu);
2720 /* Wait a bit more time for getting ACK */
2721 if (ret == -ETIME) {
2722 --timeout;
2723 usleep_range(500, 1000);
2724 continue;
2725 }
2726
2727 if (ret)
2728 goto out;
2729
2730 } while (ret == -ETIME && timeout);
2731
2732 out:
2733 mutex_unlock(&smu->message_lock);
2734
2735 if (ret)
2736 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
2737 ret);
2738
2739 return ret;
2740 }
2741
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2742 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
2743 struct smu_temperature_range *range)
2744 {
2745 struct amdgpu_device *adev = smu->adev;
2746 u32 aid_temp, xcd_temp, max_temp;
2747 u32 ccd_temp = 0;
2748 int ret;
2749
2750 if (amdgpu_sriov_vf(smu->adev))
2751 return 0;
2752
2753 if (!range)
2754 return -EINVAL;
2755
2756 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
2757 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
2758 return 0;
2759
2760 /* Get SOC Max operating temperature */
2761 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2762 PPSMC_AID_THM_TYPE, &aid_temp);
2763 if (ret)
2764 goto failed;
2765 if (adev->flags & AMD_IS_APU) {
2766 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2767 PPSMC_CCD_THM_TYPE, &ccd_temp);
2768 if (ret)
2769 goto failed;
2770 }
2771 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2772 PPSMC_XCD_THM_TYPE, &xcd_temp);
2773 if (ret)
2774 goto failed;
2775 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
2776 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2777
2778 /* Get HBM Max operating temperature */
2779 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2780 PPSMC_HBM_THM_TYPE, &max_temp);
2781 if (ret)
2782 goto failed;
2783 range->mem_emergency_max =
2784 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2785
2786 /* Get SOC thermal throttle limit */
2787 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2788 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
2789 &max_temp);
2790 if (ret)
2791 goto failed;
2792 range->hotspot_crit_max =
2793 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2794
2795 /* Get HBM thermal throttle limit */
2796 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2797 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
2798 &max_temp);
2799 if (ret)
2800 goto failed;
2801
2802 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2803
2804 failed:
2805 return ret;
2806 }
2807
smu_v13_0_6_mode1_reset(struct smu_context * smu)2808 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
2809 {
2810 struct amdgpu_device *adev = smu->adev;
2811 u32 fatal_err, param;
2812 int ret = 0;
2813
2814 fatal_err = 0;
2815 param = SMU_RESET_MODE_1;
2816
2817 /* fatal error triggered by ras, PMFW supports the flag */
2818 if (amdgpu_ras_get_fed_status(adev))
2819 fatal_err = 1;
2820
2821 param |= (fatal_err << 16);
2822 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
2823 param, NULL);
2824
2825 if (!ret)
2826 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2827
2828 return ret;
2829 }
2830
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)2831 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
2832 {
2833 return true;
2834 }
2835
smu_v13_0_6_is_mode2_reset_supported(struct smu_context * smu)2836 static bool smu_v13_0_6_is_mode2_reset_supported(struct smu_context *smu)
2837 {
2838 return true;
2839 }
2840
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)2841 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
2842 uint32_t size)
2843 {
2844 int ret = 0;
2845
2846 /* message SMU to update the bad page number on SMUBUS */
2847 ret = smu_cmn_send_smc_msg_with_param(
2848 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2849 if (ret)
2850 dev_err(smu->adev->dev,
2851 "[%s] failed to message SMU to update HBM bad pages number\n",
2852 __func__);
2853
2854 return ret;
2855 }
2856
smu_v13_0_6_send_rma_reason(struct smu_context * smu)2857 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
2858 {
2859 int ret;
2860
2861 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
2862 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
2863 return 0;
2864
2865 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
2866 if (ret)
2867 dev_err(smu->adev->dev,
2868 "[%s] failed to send BadPageThreshold event to SMU\n",
2869 __func__);
2870
2871 return ret;
2872 }
2873
smu_v13_0_6_reset_sdma(struct smu_context * smu,uint32_t inst_mask)2874 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
2875 {
2876 int ret = 0;
2877
2878 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET)))
2879 return -EOPNOTSUPP;
2880
2881 ret = smu_cmn_send_smc_msg_with_param(smu,
2882 SMU_MSG_ResetSDMA, inst_mask, NULL);
2883 if (ret)
2884 dev_err(smu->adev->dev,
2885 "failed to send ResetSDMA event with mask 0x%x\n",
2886 inst_mask);
2887
2888 return ret;
2889 }
2890
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)2891 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
2892 {
2893 struct smu_context *smu = adev->powerplay.pp_handle;
2894
2895 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
2896 }
2897
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)2898 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
2899 {
2900 uint32_t msg;
2901 int ret;
2902
2903 if (!count)
2904 return -EINVAL;
2905
2906 switch (type) {
2907 case AMDGPU_MCA_ERROR_TYPE_UE:
2908 msg = SMU_MSG_QueryValidMcaCount;
2909 break;
2910 case AMDGPU_MCA_ERROR_TYPE_CE:
2911 msg = SMU_MSG_QueryValidMcaCeCount;
2912 break;
2913 default:
2914 return -EINVAL;
2915 }
2916
2917 ret = smu_cmn_send_smc_msg(smu, msg, count);
2918 if (ret) {
2919 *count = 0;
2920 return ret;
2921 }
2922
2923 return 0;
2924 }
2925
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)2926 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2927 int idx, int offset, uint32_t *val)
2928 {
2929 uint32_t msg, param;
2930
2931 switch (type) {
2932 case AMDGPU_MCA_ERROR_TYPE_UE:
2933 msg = SMU_MSG_McaBankDumpDW;
2934 break;
2935 case AMDGPU_MCA_ERROR_TYPE_CE:
2936 msg = SMU_MSG_McaBankCeDumpDW;
2937 break;
2938 default:
2939 return -EINVAL;
2940 }
2941
2942 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
2943
2944 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
2945 }
2946
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)2947 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2948 int idx, int offset, uint32_t *val, int count)
2949 {
2950 int ret, i;
2951
2952 if (!val)
2953 return -EINVAL;
2954
2955 for (i = 0; i < count; i++) {
2956 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
2957 if (ret)
2958 return ret;
2959 }
2960
2961 return 0;
2962 }
2963
2964 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
2965 MCA_BANK_IPID(UMC, 0x96, 0x0),
2966 MCA_BANK_IPID(SMU, 0x01, 0x1),
2967 MCA_BANK_IPID(MP5, 0x01, 0x2),
2968 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
2969 };
2970
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)2971 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
2972 {
2973 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
2974 u32 instidhi, instid;
2975
2976 /* NOTE: All MCA IPID register share the same format,
2977 * so the driver can share the MCMP1 register header file.
2978 * */
2979
2980 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
2981 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
2982
2983 /*
2984 * Unfied DieID Format: SAASS. A:AID, S:Socket.
2985 * Unfied DieID[4] = InstanceId[0]
2986 * Unfied DieID[0:3] = InstanceIdHi[0:3]
2987 */
2988 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
2989 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
2990 info->aid = ((instidhi >> 2) & 0x03);
2991 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
2992 }
2993
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)2994 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
2995 int idx, int reg_idx, uint64_t *val)
2996 {
2997 struct smu_context *smu = adev->powerplay.pp_handle;
2998 uint32_t data[2] = {0, 0};
2999 int ret;
3000
3001 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
3002 return -EINVAL;
3003
3004 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3005 if (ret)
3006 return ret;
3007
3008 *val = (uint64_t)data[1] << 32 | data[0];
3009
3010 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3011 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3012
3013 return 0;
3014 }
3015
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3016 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3017 int idx, struct mca_bank_entry *entry)
3018 {
3019 int i, ret;
3020
3021 /* NOTE: populated all mca register by default */
3022 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
3023 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
3024 if (ret)
3025 return ret;
3026 }
3027
3028 entry->idx = idx;
3029 entry->type = type;
3030
3031 mca_bank_entry_info_decode(entry, &entry->info);
3032
3033 return 0;
3034 }
3035
mca_decode_ipid_to_hwip(uint64_t val)3036 static int mca_decode_ipid_to_hwip(uint64_t val)
3037 {
3038 const struct mca_bank_ipid *ipid;
3039 uint16_t hwid, mcatype;
3040 int i;
3041
3042 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
3043 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3044
3045 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
3046 ipid = &smu_v13_0_6_mca_ipid_table[i];
3047
3048 if (!ipid->hwid)
3049 continue;
3050
3051 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
3052 return i;
3053 }
3054
3055 return AMDGPU_MCA_IP_UNKNOW;
3056 }
3057
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3058 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3059 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3060 {
3061 uint64_t status0;
3062 uint32_t ext_error_code;
3063 uint32_t odecc_err_cnt;
3064
3065 status0 = entry->regs[MCA_REG_IDX_STATUS];
3066 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
3067 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3068
3069 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3070 *count = 0;
3071 return 0;
3072 }
3073
3074 if (umc_v12_0_is_deferred_error(adev, status0) ||
3075 umc_v12_0_is_uncorrectable_error(adev, status0) ||
3076 umc_v12_0_is_correctable_error(adev, status0))
3077 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
3078
3079 amdgpu_umc_update_ecc_status(adev,
3080 entry->regs[MCA_REG_IDX_STATUS],
3081 entry->regs[MCA_REG_IDX_IPID],
3082 entry->regs[MCA_REG_IDX_ADDR]);
3083
3084 return 0;
3085 }
3086
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3087 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3088 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
3089 uint32_t *count)
3090 {
3091 u32 ext_error_code;
3092 u32 err_cnt;
3093
3094 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
3095 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3096
3097 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3098 (ext_error_code == 0 || ext_error_code == 9))
3099 *count = err_cnt;
3100 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
3101 *count = err_cnt;
3102
3103 return 0;
3104 }
3105
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)3106 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3107 uint32_t errcode)
3108 {
3109 int i;
3110
3111 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
3112 return true;
3113
3114 for (i = 0; i < mca_ras->err_code_count; i++) {
3115 if (errcode == mca_ras->err_code_array[i])
3116 return true;
3117 }
3118
3119 return false;
3120 }
3121
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3122 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3123 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3124 {
3125 uint64_t status0, misc0;
3126
3127 status0 = entry->regs[MCA_REG_IDX_STATUS];
3128 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3129 *count = 0;
3130 return 0;
3131 }
3132
3133 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3134 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3135 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3136 *count = 1;
3137 return 0;
3138 } else {
3139 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3140 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3141 }
3142
3143 return 0;
3144 }
3145
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3146 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3147 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3148 {
3149 uint64_t status0, misc0;
3150
3151 status0 = entry->regs[MCA_REG_IDX_STATUS];
3152 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3153 *count = 0;
3154 return 0;
3155 }
3156
3157 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3158 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3159 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3160 if (count)
3161 *count = 1;
3162 return 0;
3163 }
3164
3165 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3166 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3167
3168 return 0;
3169 }
3170
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3171 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3172 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3173 {
3174 uint32_t instlo;
3175
3176 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3177 instlo &= GENMASK(31, 1);
3178 switch (instlo) {
3179 case 0x36430400: /* SMNAID XCD 0 */
3180 case 0x38430400: /* SMNAID XCD 1 */
3181 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
3182 return true;
3183 default:
3184 return false;
3185 }
3186
3187 return false;
3188 };
3189
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3190 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3191 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3192 {
3193 struct smu_context *smu = adev->powerplay.pp_handle;
3194 uint32_t errcode, instlo;
3195
3196 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3197 instlo &= GENMASK(31, 1);
3198 if (instlo != 0x03b30400)
3199 return false;
3200
3201 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
3202 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
3203 errcode &= 0xff;
3204 } else {
3205 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
3206 }
3207
3208 return mca_smu_check_error_code(adev, mca_ras, errcode);
3209 }
3210
3211 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
3212 static int mmhub_err_codes[] = {
3213 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
3214 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
3215 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
3216 };
3217
3218 static int vcn_err_codes[] = {
3219 CODE_VIDD, CODE_VIDV,
3220 };
3221 static int jpeg_err_codes[] = {
3222 CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
3223 CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
3224 CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
3225 CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
3226 };
3227
3228 static const struct mca_ras_info mca_ras_table[] = {
3229 {
3230 .blkid = AMDGPU_RAS_BLOCK__UMC,
3231 .ip = AMDGPU_MCA_IP_UMC,
3232 .get_err_count = mca_umc_mca_get_err_count,
3233 }, {
3234 .blkid = AMDGPU_RAS_BLOCK__GFX,
3235 .ip = AMDGPU_MCA_IP_SMU,
3236 .get_err_count = mca_gfx_mca_get_err_count,
3237 .bank_is_valid = mca_gfx_smu_bank_is_valid,
3238 }, {
3239 .blkid = AMDGPU_RAS_BLOCK__SDMA,
3240 .ip = AMDGPU_MCA_IP_SMU,
3241 .err_code_array = sdma_err_codes,
3242 .err_code_count = ARRAY_SIZE(sdma_err_codes),
3243 .get_err_count = mca_smu_mca_get_err_count,
3244 .bank_is_valid = mca_smu_bank_is_valid,
3245 }, {
3246 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
3247 .ip = AMDGPU_MCA_IP_SMU,
3248 .err_code_array = mmhub_err_codes,
3249 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3250 .get_err_count = mca_smu_mca_get_err_count,
3251 .bank_is_valid = mca_smu_bank_is_valid,
3252 }, {
3253 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3254 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3255 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3256 }, {
3257 .blkid = AMDGPU_RAS_BLOCK__VCN,
3258 .ip = AMDGPU_MCA_IP_SMU,
3259 .err_code_array = vcn_err_codes,
3260 .err_code_count = ARRAY_SIZE(vcn_err_codes),
3261 .get_err_count = mca_smu_mca_get_err_count,
3262 .bank_is_valid = mca_smu_bank_is_valid,
3263 }, {
3264 .blkid = AMDGPU_RAS_BLOCK__JPEG,
3265 .ip = AMDGPU_MCA_IP_SMU,
3266 .err_code_array = jpeg_err_codes,
3267 .err_code_count = ARRAY_SIZE(jpeg_err_codes),
3268 .get_err_count = mca_smu_mca_get_err_count,
3269 .bank_is_valid = mca_smu_bank_is_valid,
3270 },
3271 };
3272
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3273 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3274 {
3275 int i;
3276
3277 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3278 if (mca_ras_table[i].blkid == blkid)
3279 return &mca_ras_table[i];
3280 }
3281
3282 return NULL;
3283 }
3284
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3285 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3286 {
3287 struct smu_context *smu = adev->powerplay.pp_handle;
3288 int ret;
3289
3290 switch (type) {
3291 case AMDGPU_MCA_ERROR_TYPE_UE:
3292 case AMDGPU_MCA_ERROR_TYPE_CE:
3293 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3294 break;
3295 default:
3296 ret = -EINVAL;
3297 break;
3298 }
3299
3300 return ret;
3301 }
3302
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3303 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3304 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3305 {
3306 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3307 return false;
3308
3309 if (mca_ras->bank_is_valid)
3310 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3311
3312 return true;
3313 }
3314
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3315 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3316 struct mca_bank_entry *entry, uint32_t *count)
3317 {
3318 const struct mca_ras_info *mca_ras;
3319
3320 if (!entry || !count)
3321 return -EINVAL;
3322
3323 mca_ras = mca_get_mca_ras_info(adev, blk);
3324 if (!mca_ras)
3325 return -EOPNOTSUPP;
3326
3327 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3328 *count = 0;
3329 return 0;
3330 }
3331
3332 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3333 }
3334
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3335 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3336 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3337 {
3338 return mca_get_mca_entry(adev, type, idx, entry);
3339 }
3340
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3341 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3342 enum amdgpu_mca_error_type type, uint32_t *count)
3343 {
3344 return mca_get_valid_mca_count(adev, type, count);
3345 }
3346
3347 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3348 .max_ue_count = 12,
3349 .max_ce_count = 12,
3350 .mca_set_debug_mode = mca_smu_set_debug_mode,
3351 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3352 .mca_get_mca_entry = mca_smu_get_mca_entry,
3353 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3354 };
3355
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3356 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3357 {
3358 struct smu_context *smu = adev->powerplay.pp_handle;
3359
3360 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3361 }
3362
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3363 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3364 {
3365 uint32_t msg;
3366 int ret;
3367
3368 if (!count)
3369 return -EINVAL;
3370
3371 switch (type) {
3372 case ACA_SMU_TYPE_UE:
3373 msg = SMU_MSG_QueryValidMcaCount;
3374 break;
3375 case ACA_SMU_TYPE_CE:
3376 msg = SMU_MSG_QueryValidMcaCeCount;
3377 break;
3378 default:
3379 return -EINVAL;
3380 }
3381
3382 ret = smu_cmn_send_smc_msg(smu, msg, count);
3383 if (ret) {
3384 *count = 0;
3385 return ret;
3386 }
3387
3388 return 0;
3389 }
3390
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3391 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3392 enum aca_smu_type type, u32 *count)
3393 {
3394 struct smu_context *smu = adev->powerplay.pp_handle;
3395 int ret;
3396
3397 switch (type) {
3398 case ACA_SMU_TYPE_UE:
3399 case ACA_SMU_TYPE_CE:
3400 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3401 break;
3402 default:
3403 ret = -EINVAL;
3404 break;
3405 }
3406
3407 return ret;
3408 }
3409
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3410 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3411 int idx, int offset, u32 *val)
3412 {
3413 uint32_t msg, param;
3414
3415 switch (type) {
3416 case ACA_SMU_TYPE_UE:
3417 msg = SMU_MSG_McaBankDumpDW;
3418 break;
3419 case ACA_SMU_TYPE_CE:
3420 msg = SMU_MSG_McaBankCeDumpDW;
3421 break;
3422 default:
3423 return -EINVAL;
3424 }
3425
3426 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3427
3428 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3429 }
3430
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3431 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3432 int idx, int offset, u32 *val, int count)
3433 {
3434 int ret, i;
3435
3436 if (!val)
3437 return -EINVAL;
3438
3439 for (i = 0; i < count; i++) {
3440 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3441 if (ret)
3442 return ret;
3443 }
3444
3445 return 0;
3446 }
3447
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3448 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3449 int idx, int reg_idx, u64 *val)
3450 {
3451 struct smu_context *smu = adev->powerplay.pp_handle;
3452 u32 data[2] = {0, 0};
3453 int ret;
3454
3455 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3456 return -EINVAL;
3457
3458 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3459 if (ret)
3460 return ret;
3461
3462 *val = (u64)data[1] << 32 | data[0];
3463
3464 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3465 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3466
3467 return 0;
3468 }
3469
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3470 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3471 enum aca_smu_type type, int idx, struct aca_bank *bank)
3472 {
3473 int i, ret, count;
3474
3475 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3476 for (i = 0; i < count; i++) {
3477 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3478 if (ret)
3479 return ret;
3480 }
3481
3482 return 0;
3483 }
3484
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3485 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3486 {
3487 struct smu_context *smu = adev->powerplay.pp_handle;
3488 int error_code;
3489
3490 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
3491 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3492 else
3493 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3494
3495 return error_code & 0xff;
3496 }
3497
3498 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3499 .max_ue_bank_count = 12,
3500 .max_ce_bank_count = 12,
3501 .set_debug_mode = aca_smu_set_debug_mode,
3502 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3503 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3504 .parse_error_code = aca_smu_parse_error_code,
3505 };
3506
3507 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3508 /* init dpm */
3509 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3510 /* dpm/clk tables */
3511 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3512 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3513 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3514 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3515 .read_sensor = smu_v13_0_6_read_sensor,
3516 .set_performance_level = smu_v13_0_6_set_performance_level,
3517 .get_power_limit = smu_v13_0_6_get_power_limit,
3518 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3519 .get_unique_id = smu_v13_0_6_get_unique_id,
3520 .init_microcode = smu_v13_0_6_init_microcode,
3521 .fini_microcode = smu_v13_0_fini_microcode,
3522 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3523 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3524 .init_power = smu_v13_0_init_power,
3525 .fini_power = smu_v13_0_fini_power,
3526 .check_fw_status = smu_v13_0_6_check_fw_status,
3527 /* pptable related */
3528 .check_fw_version = smu_v13_0_6_check_fw_version,
3529 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3530 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3531 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3532 .system_features_control = smu_v13_0_6_system_features_control,
3533 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3534 .send_smc_msg = smu_cmn_send_smc_msg,
3535 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3536 .feature_is_enabled = smu_cmn_feature_is_enabled,
3537 .set_power_limit = smu_v13_0_6_set_power_limit,
3538 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3539 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3540 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3541 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3542 .setup_pptable = smu_v13_0_6_setup_pptable,
3543 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3544 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3545 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3546 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3547 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3548 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3549 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3550 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3551 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3552 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3553 .mode2_reset_is_support = smu_v13_0_6_is_mode2_reset_supported,
3554 .mode1_reset = smu_v13_0_6_mode1_reset,
3555 .mode2_reset = smu_v13_0_6_mode2_reset,
3556 .wait_for_event = smu_v13_0_wait_for_event,
3557 .i2c_init = smu_v13_0_6_i2c_control_init,
3558 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3559 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3560 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3561 .reset_sdma = smu_v13_0_6_reset_sdma,
3562 };
3563
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3564 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3565 {
3566 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3567 smu->message_map = smu_v13_0_6_message_map;
3568 smu->clock_map = smu_v13_0_6_clk_map;
3569 smu->feature_map = smu_v13_0_6_feature_mask_map;
3570 smu->table_map = smu_v13_0_6_table_map;
3571 smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
3572 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3573 smu_v13_0_set_smu_mailbox_registers(smu);
3574 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3575 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3576 }
3577