1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99
100 #define SMU_13_0_6_DSCLK_THRESHOLD 140
101
102 #define MCA_BANK_IPID(_ip, _hwid, _type) \
103 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
104
105 struct mca_bank_ipid {
106 enum amdgpu_mca_ip ip;
107 uint16_t hwid;
108 uint16_t mcatype;
109 };
110
111 struct mca_ras_info {
112 enum amdgpu_ras_block blkid;
113 enum amdgpu_mca_ip ip;
114 int *err_code_array;
115 int err_code_count;
116 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
117 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
118 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
119 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
120 };
121
122 #define P2S_TABLE_ID_A 0x50325341
123 #define P2S_TABLE_ID_X 0x50325358
124 #define P2S_TABLE_ID_3 0x50325303
125
126 // clang-format off
127 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
128 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
129 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
130 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
131 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
132 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
133 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
134 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
135 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
136 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
137 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
138 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
139 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
140 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
141 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
142 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
143 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
144 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
145 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
146 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
147 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
148 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
149 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
150 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
151 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
152 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
153 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
154 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
155 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
156 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
157 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
158 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
159 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
160 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
161 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
162 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
163 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
164 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
165 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
166 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
167 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
168 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
169 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
170 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
171 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
172 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
173 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
174 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
175 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
176 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
177 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
178 MSG_MAP(SelectPstatePolicy, PPSMC_MSG_SelectPstatePolicy, 0),
179 };
180
181 // clang-format on
182 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
183 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
184 CLK_MAP(FCLK, PPCLK_FCLK),
185 CLK_MAP(UCLK, PPCLK_UCLK),
186 CLK_MAP(MCLK, PPCLK_UCLK),
187 CLK_MAP(DCLK, PPCLK_DCLK),
188 CLK_MAP(VCLK, PPCLK_VCLK),
189 CLK_MAP(LCLK, PPCLK_LCLK),
190 };
191
192 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
193 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
194 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
195 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
196 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
197 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
198 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
199 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
200 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
201 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
202 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
203 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
204 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
205 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
206 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
207 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
208 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
209 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
210 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
216 };
217
218 #define TABLE_PMSTATUSLOG 0
219 #define TABLE_SMU_METRICS 1
220 #define TABLE_I2C_COMMANDS 2
221 #define TABLE_COUNT 3
222
223 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
224 TAB_MAP(PMSTATUSLOG),
225 TAB_MAP(SMU_METRICS),
226 TAB_MAP(I2C_COMMANDS),
227 };
228
229 static const uint8_t smu_v13_0_6_throttler_map[] = {
230 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
231 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
232 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
233 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
234 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
235 };
236
237 struct PPTable_t {
238 uint32_t MaxSocketPowerLimit;
239 uint32_t MaxGfxclkFrequency;
240 uint32_t MinGfxclkFrequency;
241 uint32_t FclkFrequencyTable[4];
242 uint32_t UclkFrequencyTable[4];
243 uint32_t SocclkFrequencyTable[4];
244 uint32_t VclkFrequencyTable[4];
245 uint32_t DclkFrequencyTable[4];
246 uint32_t LclkFrequencyTable[4];
247 uint32_t MaxLclkDpmRange;
248 uint32_t MinLclkDpmRange;
249 uint64_t PublicSerialNumber_AID;
250 bool Init;
251 };
252
253 #define SMUQ10_TO_UINT(x) ((x) >> 10)
254 #define SMUQ10_FRAC(x) ((x) & 0x3ff)
255 #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
256 #define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\
257 (metrics_a->field) : (metrics_x->field))
258
259 struct smu_v13_0_6_dpm_map {
260 enum smu_clk_type clk_type;
261 uint32_t feature_num;
262 struct smu_13_0_dpm_table *dpm_table;
263 uint32_t *freq_table;
264 };
265
smu_v13_0_6_init_microcode(struct smu_context * smu)266 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
267 {
268 const struct smc_firmware_header_v2_1 *v2_1;
269 const struct common_firmware_header *hdr;
270 struct amdgpu_firmware_info *ucode = NULL;
271 struct smc_soft_pptable_entry *entries;
272 struct amdgpu_device *adev = smu->adev;
273 uint32_t p2s_table_id = P2S_TABLE_ID_A;
274 int ret = 0, i, p2stable_count;
275 int var = (adev->pdev->device & 0xF);
276 char ucode_prefix[15];
277
278 /* No need to load P2S tables in IOV mode */
279 if (amdgpu_sriov_vf(adev))
280 return 0;
281
282 if (!(adev->flags & AMD_IS_APU)) {
283 p2s_table_id = P2S_TABLE_ID_X;
284 if (var == 0x5)
285 p2s_table_id = P2S_TABLE_ID_3;
286 }
287
288 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
289 sizeof(ucode_prefix));
290 ret = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
291 if (ret)
292 goto out;
293
294 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
295 amdgpu_ucode_print_smc_hdr(hdr);
296
297 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
298 * are used to carry p2s tables.
299 */
300 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
301 entries = (struct smc_soft_pptable_entry
302 *)((uint8_t *)v2_1 +
303 le32_to_cpu(v2_1->pptable_entry_offset));
304 p2stable_count = le32_to_cpu(v2_1->pptable_count);
305 for (i = 0; i < p2stable_count; i++) {
306 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
307 smu->pptable_firmware.data =
308 ((uint8_t *)v2_1 +
309 le32_to_cpu(entries[i].ppt_offset_bytes));
310 smu->pptable_firmware.size =
311 le32_to_cpu(entries[i].ppt_size_bytes);
312 break;
313 }
314 }
315
316 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
317 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
318 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
319 ucode->fw = &smu->pptable_firmware;
320 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
321 }
322
323 return 0;
324 out:
325 amdgpu_ucode_release(&adev->pm.fw);
326
327 return ret;
328 }
329
smu_v13_0_6_tables_init(struct smu_context * smu)330 static int smu_v13_0_6_tables_init(struct smu_context *smu)
331 {
332 struct smu_table_context *smu_table = &smu->smu_table;
333 struct smu_table *tables = smu_table->tables;
334 struct amdgpu_device *adev = smu->adev;
335
336 if (!(adev->flags & AMD_IS_APU))
337 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
338 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
339
340 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
341 max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)),
342 PAGE_SIZE,
343 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
344
345 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
346 PAGE_SIZE,
347 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
348
349 smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableX_t),
350 sizeof(MetricsTableA_t)), GFP_KERNEL);
351 if (!smu_table->metrics_table)
352 return -ENOMEM;
353 smu_table->metrics_time = 0;
354
355 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5);
356 smu_table->gpu_metrics_table =
357 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
358 if (!smu_table->gpu_metrics_table) {
359 kfree(smu_table->metrics_table);
360 return -ENOMEM;
361 }
362
363 smu_table->driver_pptable =
364 kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
365 if (!smu_table->driver_pptable) {
366 kfree(smu_table->metrics_table);
367 kfree(smu_table->gpu_metrics_table);
368 return -ENOMEM;
369 }
370
371 return 0;
372 }
373
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)374 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
375 int policy)
376 {
377 struct amdgpu_device *adev = smu->adev;
378 int ret, param;
379
380 switch (policy) {
381 case SOC_PSTATE_DEFAULT:
382 param = 0;
383 break;
384 case SOC_PSTATE_0:
385 param = 1;
386 break;
387 case SOC_PSTATE_1:
388 param = 2;
389 break;
390 case SOC_PSTATE_2:
391 param = 3;
392 break;
393 default:
394 return -EINVAL;
395 }
396
397 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SelectPstatePolicy,
398 param, NULL);
399
400 if (ret)
401 dev_err(adev->dev, "select soc pstate policy %d failed",
402 policy);
403
404 return ret;
405 }
406
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)407 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
408 {
409 struct amdgpu_device *adev = smu->adev;
410 int ret, param;
411
412 switch (level) {
413 case XGMI_PLPD_DEFAULT:
414 param = PPSMC_PLPD_MODE_DEFAULT;
415 break;
416 case XGMI_PLPD_OPTIMIZED:
417 param = PPSMC_PLPD_MODE_OPTIMIZED;
418 break;
419 case XGMI_PLPD_DISALLOW:
420 param = 0;
421 break;
422 default:
423 return -EINVAL;
424 }
425
426 if (level == XGMI_PLPD_DISALLOW)
427 ret = smu_cmn_send_smc_msg_with_param(
428 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
429 else
430 /* change xgmi per-link power down policy */
431 ret = smu_cmn_send_smc_msg_with_param(
432 smu, SMU_MSG_SelectPLPDMode, param, NULL);
433
434 if (ret)
435 dev_err(adev->dev,
436 "select xgmi per-link power down policy %d failed\n",
437 level);
438
439 return ret;
440 }
441
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)442 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
443 {
444 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
445 struct smu_dpm_policy *policy;
446
447 smu_dpm->dpm_context =
448 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
449 if (!smu_dpm->dpm_context)
450 return -ENOMEM;
451 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
452
453 smu_dpm->dpm_policies =
454 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
455 if (!smu_dpm->dpm_policies) {
456 kfree(smu_dpm->dpm_context);
457 return -ENOMEM;
458 }
459
460 if (!(smu->adev->flags & AMD_IS_APU)) {
461 policy = &(smu_dpm->dpm_policies->policies[0]);
462
463 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
464 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
465 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
466 BIT(SOC_PSTATE_2);
467 policy->current_level = SOC_PSTATE_DEFAULT;
468 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
469 smu_cmn_generic_soc_policy_desc(policy);
470 smu_dpm->dpm_policies->policy_mask |=
471 BIT(PP_PM_POLICY_SOC_PSTATE);
472 }
473 policy = &(smu_dpm->dpm_policies->policies[1]);
474
475 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
476 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
477 BIT(XGMI_PLPD_OPTIMIZED);
478 policy->current_level = XGMI_PLPD_DEFAULT;
479 policy->set_policy = smu_v13_0_6_select_plpd_policy;
480 smu_cmn_generic_plpd_policy_desc(policy);
481 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
482
483 return 0;
484 }
485
smu_v13_0_6_init_smc_tables(struct smu_context * smu)486 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
487 {
488 int ret = 0;
489
490 ret = smu_v13_0_6_tables_init(smu);
491 if (ret)
492 return ret;
493
494 ret = smu_v13_0_6_allocate_dpm_context(smu);
495
496 return ret;
497 }
498
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)499 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
500 uint32_t *feature_mask,
501 uint32_t num)
502 {
503 if (num > 2)
504 return -EINVAL;
505
506 /* pptable will handle the features to enable */
507 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
508
509 return 0;
510 }
511
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)512 static int smu_v13_0_6_get_metrics_table(struct smu_context *smu,
513 void *metrics_table, bool bypass_cache)
514 {
515 struct smu_table_context *smu_table = &smu->smu_table;
516 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
517 struct smu_table *table = &smu_table->driver_table;
518 int ret;
519
520 if (bypass_cache || !smu_table->metrics_time ||
521 time_after(jiffies,
522 smu_table->metrics_time + msecs_to_jiffies(1))) {
523 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
524 if (ret) {
525 dev_info(smu->adev->dev,
526 "Failed to export SMU metrics table!\n");
527 return ret;
528 }
529
530 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
531 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
532
533 smu_table->metrics_time = jiffies;
534 }
535
536 if (metrics_table)
537 memcpy(metrics_table, smu_table->metrics_table, table_size);
538
539 return 0;
540 }
541
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)542 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
543 void *metrics, size_t max_size)
544 {
545 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
546 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
547 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
548 struct amdgpu_pm_metrics *pm_metrics = metrics;
549 uint32_t pmfw_version;
550 int ret;
551
552 if (!pm_metrics || !max_size)
553 return -EINVAL;
554
555 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
556 return -EOVERFLOW;
557
558 /* Don't use cached metrics data */
559 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
560 if (ret)
561 return ret;
562
563 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
564
565 memset(&pm_metrics->common_header, 0,
566 sizeof(pm_metrics->common_header));
567 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6))
568 pm_metrics->common_header.mp1_ip_discovery_version = IP_VERSION(13, 0, 6);
569 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
570 pm_metrics->common_header.mp1_ip_discovery_version = IP_VERSION(13, 0, 14);
571 pm_metrics->common_header.pmfw_version = pmfw_version;
572 pm_metrics->common_header.pmmetrics_version = table_version;
573 pm_metrics->common_header.structure_size =
574 sizeof(pm_metrics->common_header) + table_size;
575
576 return pm_metrics->common_header.structure_size;
577 }
578
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)579 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
580 {
581 struct smu_table_context *smu_table = &smu->smu_table;
582 MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
583 MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
584 struct PPTable_t *pptable =
585 (struct PPTable_t *)smu_table->driver_pptable;
586 struct amdgpu_device *adev = smu->adev;
587 int ret, i, retry = 100;
588 uint32_t table_version;
589
590 /* Store one-time values in driver PPTable */
591 if (!pptable->Init) {
592 while (--retry) {
593 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
594 if (ret)
595 return ret;
596
597 /* Ensure that metrics have been updated */
598 if (GET_METRIC_FIELD(AccumulationCounter))
599 break;
600
601 usleep_range(1000, 1100);
602 }
603
604 if (!retry)
605 return -ETIME;
606
607 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
608 &table_version);
609 if (ret)
610 return ret;
611 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
612 table_version;
613
614 pptable->MaxSocketPowerLimit =
615 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit));
616 pptable->MaxGfxclkFrequency =
617 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency));
618 pptable->MinGfxclkFrequency =
619 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency));
620
621 for (i = 0; i < 4; ++i) {
622 pptable->FclkFrequencyTable[i] =
623 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]);
624 pptable->UclkFrequencyTable[i] =
625 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]);
626 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
627 GET_METRIC_FIELD(SocclkFrequencyTable)[i]);
628 pptable->VclkFrequencyTable[i] =
629 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]);
630 pptable->DclkFrequencyTable[i] =
631 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]);
632 pptable->LclkFrequencyTable[i] =
633 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]);
634 }
635
636 /* use AID0 serial number by default */
637 pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0];
638
639 pptable->Init = true;
640 }
641
642 return 0;
643 }
644
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)645 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
646 enum smu_clk_type clk_type,
647 uint32_t *min, uint32_t *max)
648 {
649 struct smu_table_context *smu_table = &smu->smu_table;
650 struct PPTable_t *pptable =
651 (struct PPTable_t *)smu_table->driver_pptable;
652 uint32_t clock_limit = 0, param;
653 int ret = 0, clk_id = 0;
654
655 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
656 switch (clk_type) {
657 case SMU_MCLK:
658 case SMU_UCLK:
659 if (pptable->Init)
660 clock_limit = pptable->UclkFrequencyTable[0];
661 break;
662 case SMU_GFXCLK:
663 case SMU_SCLK:
664 if (pptable->Init)
665 clock_limit = pptable->MinGfxclkFrequency;
666 break;
667 case SMU_SOCCLK:
668 if (pptable->Init)
669 clock_limit = pptable->SocclkFrequencyTable[0];
670 break;
671 case SMU_FCLK:
672 if (pptable->Init)
673 clock_limit = pptable->FclkFrequencyTable[0];
674 break;
675 case SMU_VCLK:
676 if (pptable->Init)
677 clock_limit = pptable->VclkFrequencyTable[0];
678 break;
679 case SMU_DCLK:
680 if (pptable->Init)
681 clock_limit = pptable->DclkFrequencyTable[0];
682 break;
683 default:
684 break;
685 }
686
687 if (min)
688 *min = clock_limit;
689
690 if (max)
691 *max = clock_limit;
692
693 return 0;
694 }
695
696 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
697 clk_id = smu_cmn_to_asic_specific_index(
698 smu, CMN2ASIC_MAPPING_CLK, clk_type);
699 if (clk_id < 0) {
700 ret = -EINVAL;
701 goto failed;
702 }
703 param = (clk_id & 0xffff) << 16;
704 }
705
706 if (max) {
707 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
708 ret = smu_cmn_send_smc_msg(
709 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
710 else
711 ret = smu_cmn_send_smc_msg_with_param(
712 smu, SMU_MSG_GetMaxDpmFreq, param, max);
713 if (ret)
714 goto failed;
715 }
716
717 if (min) {
718 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
719 ret = smu_cmn_send_smc_msg(
720 smu, SMU_MSG_GetMinGfxclkFrequency, min);
721 else
722 ret = smu_cmn_send_smc_msg_with_param(
723 smu, SMU_MSG_GetMinDpmFreq, param, min);
724 }
725
726 failed:
727 return ret;
728 }
729
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)730 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
731 enum smu_clk_type clk_type,
732 uint32_t *levels)
733 {
734 int ret;
735
736 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
737 if (!ret)
738 ++(*levels);
739
740 return ret;
741 }
742
smu_v13_0_6_pm_policy_init(struct smu_context * smu)743 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
744 {
745 struct smu_dpm_policy *policy;
746
747 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
748 if (policy)
749 policy->current_level = SOC_PSTATE_DEFAULT;
750 }
751
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)752 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
753 {
754 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
755 struct smu_table_context *smu_table = &smu->smu_table;
756 struct smu_13_0_dpm_table *dpm_table = NULL;
757 struct PPTable_t *pptable =
758 (struct PPTable_t *)smu_table->driver_pptable;
759 uint32_t gfxclkmin, gfxclkmax, levels;
760 int ret = 0, i, j;
761 struct smu_v13_0_6_dpm_map dpm_map[] = {
762 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
763 &dpm_context->dpm_tables.soc_table,
764 pptable->SocclkFrequencyTable },
765 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
766 &dpm_context->dpm_tables.uclk_table,
767 pptable->UclkFrequencyTable },
768 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
769 &dpm_context->dpm_tables.fclk_table,
770 pptable->FclkFrequencyTable },
771 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
772 &dpm_context->dpm_tables.vclk_table,
773 pptable->VclkFrequencyTable },
774 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
775 &dpm_context->dpm_tables.dclk_table,
776 pptable->DclkFrequencyTable },
777 };
778
779 smu_v13_0_6_setup_driver_pptable(smu);
780
781 /* DPM policy not supported in older firmwares */
782 if (!(smu->adev->flags & AMD_IS_APU) &&
783 (smu->smc_fw_version < 0x00556000)) {
784 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
785
786 smu_dpm->dpm_policies->policy_mask &=
787 ~BIT(PP_PM_POLICY_SOC_PSTATE);
788 }
789
790 smu_v13_0_6_pm_policy_init(smu);
791 /* gfxclk dpm table setup */
792 dpm_table = &dpm_context->dpm_tables.gfx_table;
793 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
794 /* In the case of gfxclk, only fine-grained dpm is honored.
795 * Get min/max values from FW.
796 */
797 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
798 &gfxclkmin, &gfxclkmax);
799 if (ret)
800 return ret;
801
802 dpm_table->count = 2;
803 dpm_table->dpm_levels[0].value = gfxclkmin;
804 dpm_table->dpm_levels[0].enabled = true;
805 dpm_table->dpm_levels[1].value = gfxclkmax;
806 dpm_table->dpm_levels[1].enabled = true;
807 dpm_table->min = dpm_table->dpm_levels[0].value;
808 dpm_table->max = dpm_table->dpm_levels[1].value;
809 } else {
810 dpm_table->count = 1;
811 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
812 dpm_table->dpm_levels[0].enabled = true;
813 dpm_table->min = dpm_table->dpm_levels[0].value;
814 dpm_table->max = dpm_table->dpm_levels[0].value;
815 }
816
817 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
818 dpm_table = dpm_map[j].dpm_table;
819 levels = 1;
820 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
821 ret = smu_v13_0_6_get_dpm_level_count(
822 smu, dpm_map[j].clk_type, &levels);
823 if (ret)
824 return ret;
825 }
826 dpm_table->count = levels;
827 for (i = 0; i < dpm_table->count; ++i) {
828 dpm_table->dpm_levels[i].value =
829 dpm_map[j].freq_table[i];
830 dpm_table->dpm_levels[i].enabled = true;
831
832 }
833 dpm_table->min = dpm_table->dpm_levels[0].value;
834 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
835
836 }
837
838 return 0;
839 }
840
smu_v13_0_6_setup_pptable(struct smu_context * smu)841 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
842 {
843 struct smu_table_context *table_context = &smu->smu_table;
844
845 /* TODO: PPTable is not available.
846 * 1) Find an alternate way to get 'PPTable values' here.
847 * 2) Check if there is SW CTF
848 */
849 table_context->thermal_controller_type = 0;
850
851 return 0;
852 }
853
smu_v13_0_6_check_fw_status(struct smu_context * smu)854 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
855 {
856 struct amdgpu_device *adev = smu->adev;
857 uint32_t mp1_fw_flags;
858
859 mp1_fw_flags =
860 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
861
862 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
863 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
864 return 0;
865
866 return -EIO;
867 }
868
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)869 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
870 {
871 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
872 struct smu_13_0_dpm_table *gfx_table =
873 &dpm_context->dpm_tables.gfx_table;
874 struct smu_13_0_dpm_table *mem_table =
875 &dpm_context->dpm_tables.uclk_table;
876 struct smu_13_0_dpm_table *soc_table =
877 &dpm_context->dpm_tables.soc_table;
878 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
879
880 pstate_table->gfxclk_pstate.min = gfx_table->min;
881 pstate_table->gfxclk_pstate.peak = gfx_table->max;
882 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
883 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
884
885 pstate_table->uclk_pstate.min = mem_table->min;
886 pstate_table->uclk_pstate.peak = mem_table->max;
887 pstate_table->uclk_pstate.curr.min = mem_table->min;
888 pstate_table->uclk_pstate.curr.max = mem_table->max;
889
890 pstate_table->socclk_pstate.min = soc_table->min;
891 pstate_table->socclk_pstate.peak = soc_table->max;
892 pstate_table->socclk_pstate.curr.min = soc_table->min;
893 pstate_table->socclk_pstate.curr.max = soc_table->max;
894
895 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
896 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
897 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
898 pstate_table->gfxclk_pstate.standard =
899 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
900 pstate_table->uclk_pstate.standard =
901 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
902 pstate_table->socclk_pstate.standard =
903 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
904 } else {
905 pstate_table->gfxclk_pstate.standard =
906 pstate_table->gfxclk_pstate.min;
907 pstate_table->uclk_pstate.standard =
908 pstate_table->uclk_pstate.min;
909 pstate_table->socclk_pstate.standard =
910 pstate_table->socclk_pstate.min;
911 }
912
913 return 0;
914 }
915
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)916 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
917 struct pp_clock_levels_with_latency *clocks,
918 struct smu_13_0_dpm_table *dpm_table)
919 {
920 int i, count;
921
922 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
923 dpm_table->count;
924 clocks->num_levels = count;
925
926 for (i = 0; i < count; i++) {
927 clocks->data[i].clocks_in_khz =
928 dpm_table->dpm_levels[i].value * 1000;
929 clocks->data[i].latency_in_us = 0;
930 }
931
932 return 0;
933 }
934
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)935 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
936 int32_t frequency2)
937 {
938 return (abs(frequency1 - frequency2) <= EPSILON);
939 }
940
smu_v13_0_6_get_throttler_status(struct smu_context * smu)941 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
942 {
943 struct smu_power_context *smu_power = &smu->smu_power;
944 struct smu_13_0_power_context *power_context = smu_power->power_context;
945 uint32_t throttler_status = 0;
946
947 throttler_status = atomic_read(&power_context->throttle_status);
948 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
949
950 return throttler_status;
951 }
952
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)953 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
954 MetricsMember_t member,
955 uint32_t *value)
956 {
957 struct smu_table_context *smu_table = &smu->smu_table;
958 MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
959 MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
960 struct amdgpu_device *adev = smu->adev;
961 int ret = 0;
962 int xcc_id;
963
964 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
965 if (ret)
966 return ret;
967
968 /* For clocks with multiple instances, only report the first one */
969 switch (member) {
970 case METRICS_CURR_GFXCLK:
971 case METRICS_AVERAGE_GFXCLK:
972 if (smu->smc_fw_version >= 0x552F00) {
973 xcc_id = GET_INST(GC, 0);
974 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);
975 } else {
976 *value = 0;
977 }
978 break;
979 case METRICS_CURR_SOCCLK:
980 case METRICS_AVERAGE_SOCCLK:
981 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]);
982 break;
983 case METRICS_CURR_UCLK:
984 case METRICS_AVERAGE_UCLK:
985 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));
986 break;
987 case METRICS_CURR_VCLK:
988 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]);
989 break;
990 case METRICS_CURR_DCLK:
991 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]);
992 break;
993 case METRICS_CURR_FCLK:
994 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency));
995 break;
996 case METRICS_AVERAGE_GFXACTIVITY:
997 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));
998 break;
999 case METRICS_AVERAGE_MEMACTIVITY:
1000 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));
1001 break;
1002 case METRICS_CURR_SOCKETPOWER:
1003 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) << 8;
1004 break;
1005 case METRICS_TEMPERATURE_HOTSPOT:
1006 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) *
1007 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1008 break;
1009 case METRICS_TEMPERATURE_MEM:
1010 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) *
1011 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1012 break;
1013 /* This is the max of all VRs and not just SOC VR.
1014 * No need to define another data type for the same.
1015 */
1016 case METRICS_TEMPERATURE_VRSOC:
1017 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) *
1018 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1019 break;
1020 default:
1021 *value = UINT_MAX;
1022 break;
1023 }
1024
1025 return ret;
1026 }
1027
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1028 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1029 enum smu_clk_type clk_type,
1030 uint32_t *value)
1031 {
1032 MetricsMember_t member_type;
1033
1034 if (!value)
1035 return -EINVAL;
1036
1037 switch (clk_type) {
1038 case SMU_GFXCLK:
1039 member_type = METRICS_CURR_GFXCLK;
1040 break;
1041 case SMU_UCLK:
1042 member_type = METRICS_CURR_UCLK;
1043 break;
1044 case SMU_SOCCLK:
1045 member_type = METRICS_CURR_SOCCLK;
1046 break;
1047 case SMU_VCLK:
1048 member_type = METRICS_CURR_VCLK;
1049 break;
1050 case SMU_DCLK:
1051 member_type = METRICS_CURR_DCLK;
1052 break;
1053 case SMU_FCLK:
1054 member_type = METRICS_CURR_FCLK;
1055 break;
1056 default:
1057 return -EINVAL;
1058 }
1059
1060 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1061 }
1062
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1063 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1064 struct smu_13_0_dpm_table *single_dpm_table,
1065 uint32_t curr_clk, const char *clk_name)
1066 {
1067 struct pp_clock_levels_with_latency clocks;
1068 int i, ret, level = -1;
1069 uint32_t clk1, clk2;
1070
1071 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1072 if (ret) {
1073 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1074 clk_name);
1075 return ret;
1076 }
1077
1078 if (!clocks.num_levels)
1079 return -EINVAL;
1080
1081 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1082 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1083 for (i = 0; i < clocks.num_levels; i++)
1084 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1085 clocks.data[i].clocks_in_khz /
1086 1000);
1087
1088 } else {
1089 if ((clocks.num_levels == 1) ||
1090 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1091 level = 0;
1092 for (i = 0; i < clocks.num_levels; i++) {
1093 clk1 = clocks.data[i].clocks_in_khz / 1000;
1094
1095 if (i < (clocks.num_levels - 1))
1096 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1097
1098 if (curr_clk == clk1) {
1099 level = i;
1100 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1101 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1102 i :
1103 i + 1;
1104 }
1105
1106 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1107 clk1, (level == i) ? "*" : "");
1108 }
1109 }
1110
1111 return size;
1112 }
1113
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1114 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1115 enum smu_clk_type type, char *buf)
1116 {
1117 int now, size = 0;
1118 int ret = 0;
1119 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1120 struct smu_13_0_dpm_table *single_dpm_table;
1121 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1122 struct smu_13_0_dpm_context *dpm_context = NULL;
1123 uint32_t min_clk, max_clk;
1124
1125 smu_cmn_get_sysfs_buf(&buf, &size);
1126
1127 if (amdgpu_ras_intr_triggered()) {
1128 size += sysfs_emit_at(buf, size, "unavailable\n");
1129 return size;
1130 }
1131
1132 dpm_context = smu_dpm->dpm_context;
1133
1134 switch (type) {
1135 case SMU_OD_SCLK:
1136 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1137 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1138 pstate_table->gfxclk_pstate.curr.min,
1139 pstate_table->gfxclk_pstate.curr.max);
1140 break;
1141 case SMU_SCLK:
1142 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1143 &now);
1144 if (ret) {
1145 dev_err(smu->adev->dev,
1146 "Attempt to get current gfx clk Failed!");
1147 return ret;
1148 }
1149
1150 min_clk = pstate_table->gfxclk_pstate.curr.min;
1151 max_clk = pstate_table->gfxclk_pstate.curr.max;
1152
1153 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1154 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1155 now);
1156 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1157 min_clk);
1158 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1159 max_clk);
1160
1161 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1162 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1163 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1164 min_clk);
1165 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1166 now);
1167 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1168 max_clk);
1169 } else {
1170 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1171 min_clk,
1172 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1173 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1174 max_clk,
1175 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1176 }
1177
1178 break;
1179
1180 case SMU_OD_MCLK:
1181 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1182 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1183 pstate_table->uclk_pstate.curr.min,
1184 pstate_table->uclk_pstate.curr.max);
1185 break;
1186 case SMU_MCLK:
1187 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1188 &now);
1189 if (ret) {
1190 dev_err(smu->adev->dev,
1191 "Attempt to get current mclk Failed!");
1192 return ret;
1193 }
1194
1195 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1196
1197 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1198 now, "mclk");
1199
1200 case SMU_SOCCLK:
1201 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1202 &now);
1203 if (ret) {
1204 dev_err(smu->adev->dev,
1205 "Attempt to get current socclk Failed!");
1206 return ret;
1207 }
1208
1209 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1210
1211 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1212 now, "socclk");
1213
1214 case SMU_FCLK:
1215 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1216 &now);
1217 if (ret) {
1218 dev_err(smu->adev->dev,
1219 "Attempt to get current fclk Failed!");
1220 return ret;
1221 }
1222
1223 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1224
1225 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1226 now, "fclk");
1227
1228 case SMU_VCLK:
1229 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1230 &now);
1231 if (ret) {
1232 dev_err(smu->adev->dev,
1233 "Attempt to get current vclk Failed!");
1234 return ret;
1235 }
1236
1237 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1238
1239 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1240 now, "vclk");
1241
1242 case SMU_DCLK:
1243 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1244 &now);
1245 if (ret) {
1246 dev_err(smu->adev->dev,
1247 "Attempt to get current dclk Failed!");
1248 return ret;
1249 }
1250
1251 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1252
1253 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1254 now, "dclk");
1255
1256 default:
1257 break;
1258 }
1259
1260 return size;
1261 }
1262
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1263 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1264 uint32_t feature_mask, uint32_t level)
1265 {
1266 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1267 uint32_t freq;
1268 int ret = 0;
1269
1270 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1271 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1272 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1273 ret = smu_cmn_send_smc_msg_with_param(
1274 smu,
1275 (max ? SMU_MSG_SetSoftMaxGfxClk :
1276 SMU_MSG_SetSoftMinGfxclk),
1277 freq & 0xffff, NULL);
1278 if (ret) {
1279 dev_err(smu->adev->dev,
1280 "Failed to set soft %s gfxclk !\n",
1281 max ? "max" : "min");
1282 return ret;
1283 }
1284 }
1285
1286 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1287 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1288 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1289 .value;
1290 ret = smu_cmn_send_smc_msg_with_param(
1291 smu,
1292 (max ? SMU_MSG_SetSoftMaxByFreq :
1293 SMU_MSG_SetSoftMinByFreq),
1294 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1295 if (ret) {
1296 dev_err(smu->adev->dev,
1297 "Failed to set soft %s memclk !\n",
1298 max ? "max" : "min");
1299 return ret;
1300 }
1301 }
1302
1303 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1304 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1305 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1306 ret = smu_cmn_send_smc_msg_with_param(
1307 smu,
1308 (max ? SMU_MSG_SetSoftMaxByFreq :
1309 SMU_MSG_SetSoftMinByFreq),
1310 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1311 if (ret) {
1312 dev_err(smu->adev->dev,
1313 "Failed to set soft %s socclk !\n",
1314 max ? "max" : "min");
1315 return ret;
1316 }
1317 }
1318
1319 return ret;
1320 }
1321
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1322 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1323 enum smu_clk_type type, uint32_t mask)
1324 {
1325 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1326 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1327 uint32_t soft_min_level, soft_max_level;
1328 int ret = 0;
1329
1330 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1331 soft_max_level = mask ? (fls(mask) - 1) : 0;
1332
1333 switch (type) {
1334 case SMU_SCLK:
1335 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1336 if (soft_max_level >= single_dpm_table->count) {
1337 dev_err(smu->adev->dev,
1338 "Clock level specified %d is over max allowed %d\n",
1339 soft_max_level, single_dpm_table->count - 1);
1340 ret = -EINVAL;
1341 break;
1342 }
1343
1344 ret = smu_v13_0_6_upload_dpm_level(
1345 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1346 soft_min_level);
1347 if (ret) {
1348 dev_err(smu->adev->dev,
1349 "Failed to upload boot level to lowest!\n");
1350 break;
1351 }
1352
1353 ret = smu_v13_0_6_upload_dpm_level(
1354 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1355 soft_max_level);
1356 if (ret)
1357 dev_err(smu->adev->dev,
1358 "Failed to upload dpm max level to highest!\n");
1359
1360 break;
1361
1362 case SMU_MCLK:
1363 case SMU_SOCCLK:
1364 case SMU_FCLK:
1365 /*
1366 * Should not arrive here since smu_13_0_6 does not
1367 * support mclk/socclk/fclk softmin/softmax settings
1368 */
1369 ret = -EINVAL;
1370 break;
1371
1372 default:
1373 break;
1374 }
1375
1376 return ret;
1377 }
1378
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1379 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1380 enum amd_pp_sensors sensor,
1381 uint32_t *value)
1382 {
1383 int ret = 0;
1384
1385 if (!value)
1386 return -EINVAL;
1387
1388 switch (sensor) {
1389 case AMDGPU_PP_SENSOR_GPU_LOAD:
1390 ret = smu_v13_0_6_get_smu_metrics_data(
1391 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1392 break;
1393 case AMDGPU_PP_SENSOR_MEM_LOAD:
1394 ret = smu_v13_0_6_get_smu_metrics_data(
1395 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1396 break;
1397 default:
1398 dev_err(smu->adev->dev,
1399 "Invalid sensor for retrieving clock activity\n");
1400 return -EINVAL;
1401 }
1402
1403 return ret;
1404 }
1405
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1406 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1407 enum amd_pp_sensors sensor,
1408 uint32_t *value)
1409 {
1410 int ret = 0;
1411
1412 if (!value)
1413 return -EINVAL;
1414
1415 switch (sensor) {
1416 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1417 ret = smu_v13_0_6_get_smu_metrics_data(
1418 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1419 break;
1420 case AMDGPU_PP_SENSOR_MEM_TEMP:
1421 ret = smu_v13_0_6_get_smu_metrics_data(
1422 smu, METRICS_TEMPERATURE_MEM, value);
1423 break;
1424 default:
1425 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1426 return -EINVAL;
1427 }
1428
1429 return ret;
1430 }
1431
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1432 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1433 enum amd_pp_sensors sensor, void *data,
1434 uint32_t *size)
1435 {
1436 int ret = 0;
1437
1438 if (amdgpu_ras_intr_triggered())
1439 return 0;
1440
1441 if (!data || !size)
1442 return -EINVAL;
1443
1444 switch (sensor) {
1445 case AMDGPU_PP_SENSOR_MEM_LOAD:
1446 case AMDGPU_PP_SENSOR_GPU_LOAD:
1447 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1448 (uint32_t *)data);
1449 *size = 4;
1450 break;
1451 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1452 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1453 METRICS_CURR_SOCKETPOWER,
1454 (uint32_t *)data);
1455 *size = 4;
1456 break;
1457 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1458 case AMDGPU_PP_SENSOR_MEM_TEMP:
1459 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1460 (uint32_t *)data);
1461 *size = 4;
1462 break;
1463 case AMDGPU_PP_SENSOR_GFX_MCLK:
1464 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1465 smu, SMU_UCLK, (uint32_t *)data);
1466 /* the output clock frequency in 10K unit */
1467 *(uint32_t *)data *= 100;
1468 *size = 4;
1469 break;
1470 case AMDGPU_PP_SENSOR_GFX_SCLK:
1471 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1472 smu, SMU_GFXCLK, (uint32_t *)data);
1473 *(uint32_t *)data *= 100;
1474 *size = 4;
1475 break;
1476 case AMDGPU_PP_SENSOR_VDDGFX:
1477 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1478 *size = 4;
1479 break;
1480 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1481 default:
1482 ret = -EOPNOTSUPP;
1483 break;
1484 }
1485
1486 return ret;
1487 }
1488
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1489 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1490 uint32_t *current_power_limit,
1491 uint32_t *default_power_limit,
1492 uint32_t *max_power_limit,
1493 uint32_t *min_power_limit)
1494 {
1495 struct smu_table_context *smu_table = &smu->smu_table;
1496 struct PPTable_t *pptable =
1497 (struct PPTable_t *)smu_table->driver_pptable;
1498 uint32_t power_limit = 0;
1499 int ret;
1500
1501 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1502
1503 if (ret) {
1504 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1505 return -EINVAL;
1506 }
1507
1508 if (current_power_limit)
1509 *current_power_limit = power_limit;
1510 if (default_power_limit)
1511 *default_power_limit = power_limit;
1512
1513 if (max_power_limit) {
1514 *max_power_limit = pptable->MaxSocketPowerLimit;
1515 }
1516
1517 if (min_power_limit)
1518 *min_power_limit = 0;
1519 return 0;
1520 }
1521
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1522 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1523 enum smu_ppt_limit_type limit_type,
1524 uint32_t limit)
1525 {
1526 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1527 }
1528
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1529 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1530 struct amdgpu_irq_src *source,
1531 struct amdgpu_iv_entry *entry)
1532 {
1533 struct smu_context *smu = adev->powerplay.pp_handle;
1534 struct smu_power_context *smu_power = &smu->smu_power;
1535 struct smu_13_0_power_context *power_context = smu_power->power_context;
1536 uint32_t client_id = entry->client_id;
1537 uint32_t ctxid = entry->src_data[0];
1538 uint32_t src_id = entry->src_id;
1539 uint32_t data;
1540
1541 if (client_id == SOC15_IH_CLIENTID_MP1) {
1542 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1543 /* ACK SMUToHost interrupt */
1544 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1545 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1546 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1547 /*
1548 * ctxid is used to distinguish different events for SMCToHost
1549 * interrupt.
1550 */
1551 switch (ctxid) {
1552 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1553 /*
1554 * Increment the throttle interrupt counter
1555 */
1556 atomic64_inc(&smu->throttle_int_counter);
1557
1558 if (!atomic_read(&adev->throttling_logging_enabled))
1559 return 0;
1560
1561 /* This uses the new method which fixes the
1562 * incorrect throttling status reporting
1563 * through metrics table. For older FWs,
1564 * it will be ignored.
1565 */
1566 if (__ratelimit(&adev->throttling_logging_rs)) {
1567 atomic_set(
1568 &power_context->throttle_status,
1569 entry->src_data[1]);
1570 schedule_work(&smu->throttling_logging_work);
1571 }
1572 break;
1573 default:
1574 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1575 ctxid, client_id);
1576 break;
1577 }
1578 }
1579 }
1580
1581 return 0;
1582 }
1583
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1584 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1585 struct amdgpu_irq_src *source,
1586 unsigned tyep,
1587 enum amdgpu_interrupt_state state)
1588 {
1589 uint32_t val = 0;
1590
1591 switch (state) {
1592 case AMDGPU_IRQ_STATE_DISABLE:
1593 /* For MP1 SW irqs */
1594 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1595 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1596 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1597
1598 break;
1599 case AMDGPU_IRQ_STATE_ENABLE:
1600 /* For MP1 SW irqs */
1601 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1602 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1603 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1604 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1605
1606 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1607 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1608 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1609
1610 break;
1611 default:
1612 break;
1613 }
1614
1615 return 0;
1616 }
1617
1618 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1619 .set = smu_v13_0_6_set_irq_state,
1620 .process = smu_v13_0_6_irq_process,
1621 };
1622
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1623 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1624 {
1625 struct amdgpu_device *adev = smu->adev;
1626 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1627 int ret = 0;
1628
1629 if (amdgpu_sriov_vf(adev))
1630 return 0;
1631
1632 irq_src->num_types = 1;
1633 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1634
1635 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1636 IH_INTERRUPT_ID_TO_DRIVER,
1637 irq_src);
1638 if (ret)
1639 return ret;
1640
1641 return ret;
1642 }
1643
smu_v13_0_6_notify_unload(struct smu_context * smu)1644 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1645 {
1646 if (amdgpu_in_reset(smu->adev))
1647 return 0;
1648
1649 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1650 /* Ignore return, just intimate FW that driver is not going to be there */
1651 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1652
1653 return 0;
1654 }
1655
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1656 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1657 {
1658 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1659 if (smu->smc_fw_version < 0x554800)
1660 return 0;
1661
1662 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1663 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1664 NULL);
1665 }
1666
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1667 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1668 bool enable)
1669 {
1670 struct amdgpu_device *adev = smu->adev;
1671 int ret = 0;
1672
1673 if (amdgpu_sriov_vf(adev))
1674 return 0;
1675
1676 if (enable) {
1677 if (!(adev->flags & AMD_IS_APU))
1678 ret = smu_v13_0_system_features_control(smu, enable);
1679 } else {
1680 /* Notify FW that the device is no longer driver managed */
1681 smu_v13_0_6_notify_unload(smu);
1682 }
1683
1684 return ret;
1685 }
1686
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1687 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1688 uint32_t min,
1689 uint32_t max)
1690 {
1691 int ret;
1692
1693 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1694 max & 0xffff, NULL);
1695 if (ret)
1696 return ret;
1697
1698 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1699 min & 0xffff, NULL);
1700
1701 return ret;
1702 }
1703
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1704 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1705 enum amd_dpm_forced_level level)
1706 {
1707 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1708 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1709 struct smu_13_0_dpm_table *gfx_table =
1710 &dpm_context->dpm_tables.gfx_table;
1711 struct smu_13_0_dpm_table *uclk_table =
1712 &dpm_context->dpm_tables.uclk_table;
1713 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1714 int ret;
1715
1716 /* Disable determinism if switching to another mode */
1717 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1718 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1719 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1720 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1721 }
1722
1723 switch (level) {
1724 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1725 return 0;
1726
1727 case AMD_DPM_FORCED_LEVEL_AUTO:
1728 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
1729 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
1730 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1731 smu, gfx_table->min, gfx_table->max);
1732 if (ret)
1733 return ret;
1734
1735 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1736 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1737 }
1738
1739 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
1740 /* Min UCLK is not expected to be changed */
1741 ret = smu_v13_0_set_soft_freq_limited_range(
1742 smu, SMU_UCLK, 0, uclk_table->max);
1743 if (ret)
1744 return ret;
1745 pstate_table->uclk_pstate.curr.max = uclk_table->max;
1746 }
1747 pstate_table->uclk_pstate.custom.max = 0;
1748
1749 return 0;
1750 case AMD_DPM_FORCED_LEVEL_MANUAL:
1751 return 0;
1752 default:
1753 break;
1754 }
1755
1756 return -EINVAL;
1757 }
1758
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1759 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
1760 enum smu_clk_type clk_type,
1761 uint32_t min, uint32_t max)
1762 {
1763 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1764 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1765 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1766 struct amdgpu_device *adev = smu->adev;
1767 uint32_t min_clk;
1768 uint32_t max_clk;
1769 int ret = 0;
1770
1771 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
1772 clk_type != SMU_UCLK)
1773 return -EINVAL;
1774
1775 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
1776 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1777 return -EINVAL;
1778
1779 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1780 if (min >= max) {
1781 dev_err(smu->adev->dev,
1782 "Minimum clk should be less than the maximum allowed clock\n");
1783 return -EINVAL;
1784 }
1785
1786 if (clk_type == SMU_GFXCLK) {
1787 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1788 (max == pstate_table->gfxclk_pstate.curr.max))
1789 return 0;
1790
1791 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1792 smu, min, max);
1793 if (!ret) {
1794 pstate_table->gfxclk_pstate.curr.min = min;
1795 pstate_table->gfxclk_pstate.curr.max = max;
1796 }
1797 }
1798
1799 if (clk_type == SMU_UCLK) {
1800 if (max == pstate_table->uclk_pstate.curr.max)
1801 return 0;
1802 /* For VF, only allowed in FW versions 85.102 or greater */
1803 if (amdgpu_sriov_vf(adev) &&
1804 ((smu->smc_fw_version < 0x556600) ||
1805 (adev->flags & AMD_IS_APU)))
1806 return -EOPNOTSUPP;
1807 /* Only max clock limiting is allowed for UCLK */
1808 ret = smu_v13_0_set_soft_freq_limited_range(
1809 smu, SMU_UCLK, 0, max);
1810 if (!ret)
1811 pstate_table->uclk_pstate.curr.max = max;
1812 }
1813
1814 return ret;
1815 }
1816
1817 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1818 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1819 (max > dpm_context->dpm_tables.gfx_table.max)) {
1820 dev_warn(
1821 adev->dev,
1822 "Invalid max frequency %d MHz specified for determinism\n",
1823 max);
1824 return -EINVAL;
1825 }
1826
1827 /* Restore default min/max clocks and enable determinism */
1828 min_clk = dpm_context->dpm_tables.gfx_table.min;
1829 max_clk = dpm_context->dpm_tables.gfx_table.max;
1830 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
1831 max_clk);
1832 if (!ret) {
1833 usleep_range(500, 1000);
1834 ret = smu_cmn_send_smc_msg_with_param(
1835 smu, SMU_MSG_EnableDeterminism, max, NULL);
1836 if (ret) {
1837 dev_err(adev->dev,
1838 "Failed to enable determinism at GFX clock %d MHz\n",
1839 max);
1840 } else {
1841 pstate_table->gfxclk_pstate.curr.min = min_clk;
1842 pstate_table->gfxclk_pstate.curr.max = max;
1843 }
1844 }
1845 }
1846
1847 return ret;
1848 }
1849
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1850 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
1851 enum PP_OD_DPM_TABLE_COMMAND type,
1852 long input[], uint32_t size)
1853 {
1854 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1855 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1856 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1857 uint32_t min_clk;
1858 uint32_t max_clk;
1859 int ret = 0;
1860
1861 /* Only allowed in manual or determinism mode */
1862 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
1863 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1864 return -EINVAL;
1865
1866 switch (type) {
1867 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1868 if (size != 2) {
1869 dev_err(smu->adev->dev,
1870 "Input parameter number not correct\n");
1871 return -EINVAL;
1872 }
1873
1874 if (input[0] == 0) {
1875 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1876 dev_warn(
1877 smu->adev->dev,
1878 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1879 input[1],
1880 dpm_context->dpm_tables.gfx_table.min);
1881 pstate_table->gfxclk_pstate.custom.min =
1882 pstate_table->gfxclk_pstate.curr.min;
1883 return -EINVAL;
1884 }
1885
1886 pstate_table->gfxclk_pstate.custom.min = input[1];
1887 } else if (input[0] == 1) {
1888 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1889 dev_warn(
1890 smu->adev->dev,
1891 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1892 input[1],
1893 dpm_context->dpm_tables.gfx_table.max);
1894 pstate_table->gfxclk_pstate.custom.max =
1895 pstate_table->gfxclk_pstate.curr.max;
1896 return -EINVAL;
1897 }
1898
1899 pstate_table->gfxclk_pstate.custom.max = input[1];
1900 } else {
1901 return -EINVAL;
1902 }
1903 break;
1904 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1905 if (size != 2) {
1906 dev_err(smu->adev->dev,
1907 "Input parameter number not correct\n");
1908 return -EINVAL;
1909 }
1910
1911 if (!smu_cmn_feature_is_enabled(smu,
1912 SMU_FEATURE_DPM_UCLK_BIT)) {
1913 dev_warn(smu->adev->dev,
1914 "UCLK_LIMITS setting not supported!\n");
1915 return -EOPNOTSUPP;
1916 }
1917
1918 if (input[0] == 0) {
1919 dev_info(smu->adev->dev,
1920 "Setting min UCLK level is not supported");
1921 return -EINVAL;
1922 } else if (input[0] == 1) {
1923 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
1924 dev_warn(
1925 smu->adev->dev,
1926 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1927 input[1],
1928 dpm_context->dpm_tables.uclk_table.max);
1929 pstate_table->uclk_pstate.custom.max =
1930 pstate_table->uclk_pstate.curr.max;
1931 return -EINVAL;
1932 }
1933
1934 pstate_table->uclk_pstate.custom.max = input[1];
1935 }
1936 break;
1937
1938 case PP_OD_RESTORE_DEFAULT_TABLE:
1939 if (size != 0) {
1940 dev_err(smu->adev->dev,
1941 "Input parameter number not correct\n");
1942 return -EINVAL;
1943 } else {
1944 /* Use the default frequencies for manual and determinism mode */
1945 min_clk = dpm_context->dpm_tables.gfx_table.min;
1946 max_clk = dpm_context->dpm_tables.gfx_table.max;
1947
1948 ret = smu_v13_0_6_set_soft_freq_limited_range(
1949 smu, SMU_GFXCLK, min_clk, max_clk);
1950
1951 if (ret)
1952 return ret;
1953
1954 min_clk = dpm_context->dpm_tables.uclk_table.min;
1955 max_clk = dpm_context->dpm_tables.uclk_table.max;
1956 ret = smu_v13_0_6_set_soft_freq_limited_range(
1957 smu, SMU_UCLK, min_clk, max_clk);
1958 if (ret)
1959 return ret;
1960 pstate_table->uclk_pstate.custom.max = 0;
1961 }
1962 break;
1963 case PP_OD_COMMIT_DPM_TABLE:
1964 if (size != 0) {
1965 dev_err(smu->adev->dev,
1966 "Input parameter number not correct\n");
1967 return -EINVAL;
1968 } else {
1969 if (!pstate_table->gfxclk_pstate.custom.min)
1970 pstate_table->gfxclk_pstate.custom.min =
1971 pstate_table->gfxclk_pstate.curr.min;
1972
1973 if (!pstate_table->gfxclk_pstate.custom.max)
1974 pstate_table->gfxclk_pstate.custom.max =
1975 pstate_table->gfxclk_pstate.curr.max;
1976
1977 min_clk = pstate_table->gfxclk_pstate.custom.min;
1978 max_clk = pstate_table->gfxclk_pstate.custom.max;
1979
1980 ret = smu_v13_0_6_set_soft_freq_limited_range(
1981 smu, SMU_GFXCLK, min_clk, max_clk);
1982
1983 if (ret)
1984 return ret;
1985
1986 if (!pstate_table->uclk_pstate.custom.max)
1987 return 0;
1988
1989 min_clk = pstate_table->uclk_pstate.curr.min;
1990 max_clk = pstate_table->uclk_pstate.custom.max;
1991 return smu_v13_0_6_set_soft_freq_limited_range(
1992 smu, SMU_UCLK, min_clk, max_clk);
1993 }
1994 break;
1995 default:
1996 return -ENOSYS;
1997 }
1998
1999 return ret;
2000 }
2001
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2002 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2003 uint64_t *feature_mask)
2004 {
2005 int ret;
2006
2007 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2008
2009 if (ret == -EIO && smu->smc_fw_version < 0x552F00) {
2010 *feature_mask = 0;
2011 ret = 0;
2012 }
2013
2014 return ret;
2015 }
2016
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2017 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2018 {
2019 int ret;
2020 uint64_t feature_enabled;
2021
2022 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2023
2024 if (ret)
2025 return false;
2026
2027 return !!(feature_enabled & SMC_DPM_FEATURE);
2028 }
2029
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2030 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2031 void *table_data)
2032 {
2033 struct smu_table_context *smu_table = &smu->smu_table;
2034 struct smu_table *table = &smu_table->driver_table;
2035 struct amdgpu_device *adev = smu->adev;
2036 uint32_t table_size;
2037 int ret = 0;
2038
2039 if (!table_data)
2040 return -EINVAL;
2041
2042 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2043
2044 memcpy(table->cpu_addr, table_data, table_size);
2045 /* Flush hdp cache */
2046 amdgpu_asic_flush_hdp(adev, NULL);
2047 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2048 NULL);
2049
2050 return ret;
2051 }
2052
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2053 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2054 struct i2c_msg *msg, int num_msgs)
2055 {
2056 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2057 struct amdgpu_device *adev = smu_i2c->adev;
2058 struct smu_context *smu = adev->powerplay.pp_handle;
2059 struct smu_table_context *smu_table = &smu->smu_table;
2060 struct smu_table *table = &smu_table->driver_table;
2061 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2062 int i, j, r, c;
2063 u16 dir;
2064
2065 if (!adev->pm.dpm_enabled)
2066 return -EBUSY;
2067
2068 req = kzalloc(sizeof(*req), GFP_KERNEL);
2069 if (!req)
2070 return -ENOMEM;
2071
2072 req->I2CcontrollerPort = smu_i2c->port;
2073 req->I2CSpeed = I2C_SPEED_FAST_400K;
2074 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2075 dir = msg[0].flags & I2C_M_RD;
2076
2077 for (c = i = 0; i < num_msgs; i++) {
2078 for (j = 0; j < msg[i].len; j++, c++) {
2079 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2080
2081 if (!(msg[i].flags & I2C_M_RD)) {
2082 /* write */
2083 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2084 cmd->ReadWriteData = msg[i].buf[j];
2085 }
2086
2087 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2088 /* The direction changes.
2089 */
2090 dir = msg[i].flags & I2C_M_RD;
2091 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2092 }
2093
2094 req->NumCmds++;
2095
2096 /*
2097 * Insert STOP if we are at the last byte of either last
2098 * message for the transaction or the client explicitly
2099 * requires a STOP at this particular message.
2100 */
2101 if ((j == msg[i].len - 1) &&
2102 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2103 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2104 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2105 }
2106 }
2107 }
2108 mutex_lock(&adev->pm.mutex);
2109 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2110 if (r) {
2111 /* Retry once, in case of an i2c collision */
2112 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2113 if (r)
2114 goto fail;
2115 }
2116
2117 for (c = i = 0; i < num_msgs; i++) {
2118 if (!(msg[i].flags & I2C_M_RD)) {
2119 c += msg[i].len;
2120 continue;
2121 }
2122 for (j = 0; j < msg[i].len; j++, c++) {
2123 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2124
2125 msg[i].buf[j] = cmd->ReadWriteData;
2126 }
2127 }
2128 r = num_msgs;
2129 fail:
2130 mutex_unlock(&adev->pm.mutex);
2131 kfree(req);
2132 return r;
2133 }
2134
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2135 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2136 {
2137 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2138 }
2139
2140 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2141 .master_xfer = smu_v13_0_6_i2c_xfer,
2142 .functionality = smu_v13_0_6_i2c_func,
2143 };
2144
2145 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2146 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2147 .max_read_len = MAX_SW_I2C_COMMANDS,
2148 .max_write_len = MAX_SW_I2C_COMMANDS,
2149 .max_comb_1st_msg_len = 2,
2150 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2151 };
2152
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2153 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2154 {
2155 struct amdgpu_device *adev = smu->adev;
2156 int res, i;
2157
2158 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2159 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2160 struct i2c_adapter *control = &smu_i2c->adapter;
2161
2162 smu_i2c->adev = adev;
2163 smu_i2c->port = i;
2164 mutex_init(&smu_i2c->mutex);
2165 control->owner = THIS_MODULE;
2166 control->dev.parent = &adev->pdev->dev;
2167 control->algo = &smu_v13_0_6_i2c_algo;
2168 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2169 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2170 i2c_set_adapdata(control, smu_i2c);
2171
2172 res = i2c_add_adapter(control);
2173 if (res) {
2174 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2175 goto Out_err;
2176 }
2177 }
2178
2179 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2180 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2181
2182 return 0;
2183 Out_err:
2184 for ( ; i >= 0; i--) {
2185 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2186 struct i2c_adapter *control = &smu_i2c->adapter;
2187
2188 i2c_del_adapter(control);
2189 }
2190 return res;
2191 }
2192
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2193 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2194 {
2195 struct amdgpu_device *adev = smu->adev;
2196 int i;
2197
2198 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2199 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2200 struct i2c_adapter *control = &smu_i2c->adapter;
2201
2202 i2c_del_adapter(control);
2203 }
2204 adev->pm.ras_eeprom_i2c_bus = NULL;
2205 adev->pm.fru_eeprom_i2c_bus = NULL;
2206 }
2207
smu_v13_0_6_get_unique_id(struct smu_context * smu)2208 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2209 {
2210 struct amdgpu_device *adev = smu->adev;
2211 struct smu_table_context *smu_table = &smu->smu_table;
2212 struct PPTable_t *pptable =
2213 (struct PPTable_t *)smu_table->driver_pptable;
2214
2215 adev->unique_id = pptable->PublicSerialNumber_AID;
2216 }
2217
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2218 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2219 {
2220 /* smu_13_0_6 does not support baco */
2221
2222 return 0;
2223 }
2224
2225 static const char *const throttling_logging_label[] = {
2226 [THROTTLER_PROCHOT_BIT] = "Prochot",
2227 [THROTTLER_PPT_BIT] = "PPT",
2228 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2229 [THROTTLER_THERMAL_VR_BIT] = "VR",
2230 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2231 };
2232
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2233 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2234 {
2235 int throttler_idx, throttling_events = 0, buf_idx = 0;
2236 struct amdgpu_device *adev = smu->adev;
2237 uint32_t throttler_status;
2238 char log_buf[256];
2239
2240 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2241 if (!throttler_status)
2242 return;
2243
2244 memset(log_buf, 0, sizeof(log_buf));
2245 for (throttler_idx = 0;
2246 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2247 throttler_idx++) {
2248 if (throttler_status & (1U << throttler_idx)) {
2249 throttling_events++;
2250 buf_idx += snprintf(
2251 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2252 "%s%s", throttling_events > 1 ? " and " : "",
2253 throttling_logging_label[throttler_idx]);
2254 if (buf_idx >= sizeof(log_buf)) {
2255 dev_err(adev->dev, "buffer overflow!\n");
2256 log_buf[sizeof(log_buf) - 1] = '\0';
2257 break;
2258 }
2259 }
2260 }
2261
2262 dev_warn(adev->dev,
2263 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2264 log_buf);
2265 kgd2kfd_smi_event_throttle(
2266 smu->adev->kfd.dev,
2267 smu_cmn_get_indep_throttler_status(throttler_status,
2268 smu_v13_0_6_throttler_map));
2269 }
2270
2271 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2272 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2273 {
2274 struct amdgpu_device *adev = smu->adev;
2275
2276 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2277 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2278 }
2279
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2280 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2281 {
2282 struct amdgpu_device *adev = smu->adev;
2283 uint32_t speed_level;
2284 uint32_t esm_ctrl;
2285
2286 /* TODO: confirm this on real target */
2287 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2288 if ((esm_ctrl >> 15) & 0x1)
2289 return (((esm_ctrl >> 8) & 0x7F) + 128);
2290
2291 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2292 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2293 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2294 if (speed_level > LINK_SPEED_MAX)
2295 speed_level = 0;
2296
2297 return pcie_gen_to_speed(speed_level + 1);
2298 }
2299
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2300 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2301 {
2302 struct smu_table_context *smu_table = &smu->smu_table;
2303 struct gpu_metrics_v1_5 *gpu_metrics =
2304 (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table;
2305 struct amdgpu_device *adev = smu->adev;
2306 int ret = 0, xcc_id, inst, i, j;
2307 MetricsTableX_t *metrics_x;
2308 MetricsTableA_t *metrics_a;
2309 u16 link_width_level;
2310
2311 metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL);
2312 ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true);
2313 if (ret) {
2314 kfree(metrics_x);
2315 return ret;
2316 }
2317
2318 metrics_a = (MetricsTableA_t *)metrics_x;
2319
2320 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5);
2321
2322 gpu_metrics->temperature_hotspot =
2323 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature));
2324 /* Individual HBM stack temperature is not reported */
2325 gpu_metrics->temperature_mem =
2326 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature));
2327 /* Reports max temperature of all voltage rails */
2328 gpu_metrics->temperature_vrsoc =
2329 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature));
2330
2331 gpu_metrics->average_gfx_activity =
2332 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));
2333 gpu_metrics->average_umc_activity =
2334 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));
2335
2336 gpu_metrics->curr_socket_power =
2337 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower));
2338 /* Energy counter reported in 15.259uJ (2^-16) units */
2339 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc);
2340
2341 for (i = 0; i < MAX_GFX_CLKS; i++) {
2342 xcc_id = GET_INST(GC, i);
2343 if (xcc_id >= 0)
2344 gpu_metrics->current_gfxclk[i] =
2345 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);
2346
2347 if (i < MAX_CLKS) {
2348 gpu_metrics->current_socclk[i] =
2349 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]);
2350 inst = GET_INST(VCN, i);
2351 if (inst >= 0) {
2352 gpu_metrics->current_vclk0[i] =
2353 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]);
2354 gpu_metrics->current_dclk0[i] =
2355 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]);
2356 }
2357 }
2358 }
2359
2360 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));
2361
2362 /* Throttle status is not reported through metrics now */
2363 gpu_metrics->throttle_status = 0;
2364
2365 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2366 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0);
2367
2368 if (!(adev->flags & AMD_IS_APU)) {
2369 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2370 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2371 * for pf from registers
2372 */
2373 if (smu->smc_fw_version >= 0x556300) {
2374 gpu_metrics->pcie_link_width = metrics_x->PCIeLinkWidth;
2375 gpu_metrics->pcie_link_speed =
2376 pcie_gen_to_speed(metrics_x->PCIeLinkSpeed);
2377 } else if (!amdgpu_sriov_vf(adev)) {
2378 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2379 if (link_width_level > MAX_LINK_WIDTH)
2380 link_width_level = 0;
2381
2382 gpu_metrics->pcie_link_width =
2383 DECODE_LANE_WIDTH(link_width_level);
2384 gpu_metrics->pcie_link_speed =
2385 smu_v13_0_6_get_current_pcie_link_speed(smu);
2386 }
2387
2388 gpu_metrics->pcie_bandwidth_acc =
2389 SMUQ10_ROUND(metrics_x->PcieBandwidthAcc[0]);
2390 gpu_metrics->pcie_bandwidth_inst =
2391 SMUQ10_ROUND(metrics_x->PcieBandwidth[0]);
2392 gpu_metrics->pcie_l0_to_recov_count_acc =
2393 metrics_x->PCIeL0ToRecoveryCountAcc;
2394 gpu_metrics->pcie_replay_count_acc =
2395 metrics_x->PCIenReplayAAcc;
2396 gpu_metrics->pcie_replay_rover_count_acc =
2397 metrics_x->PCIenReplayARolloverCountAcc;
2398 gpu_metrics->pcie_nak_sent_count_acc =
2399 metrics_x->PCIeNAKSentCountAcc;
2400 gpu_metrics->pcie_nak_rcvd_count_acc =
2401 metrics_x->PCIeNAKReceivedCountAcc;
2402 }
2403
2404 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2405
2406 gpu_metrics->gfx_activity_acc =
2407 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc));
2408 gpu_metrics->mem_activity_acc =
2409 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc));
2410
2411 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2412 gpu_metrics->xgmi_read_data_acc[i] =
2413 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]);
2414 gpu_metrics->xgmi_write_data_acc[i] =
2415 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]);
2416 }
2417
2418 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
2419 inst = GET_INST(JPEG, i);
2420 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
2421 gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] =
2422 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy)
2423 [(inst * adev->jpeg.num_jpeg_rings) + j]);
2424 }
2425 }
2426
2427 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2428 inst = GET_INST(VCN, i);
2429 gpu_metrics->vcn_activity[i] =
2430 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]);
2431 }
2432
2433 gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth));
2434 gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate));
2435
2436 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp);
2437
2438 *table = (void *)gpu_metrics;
2439 kfree(metrics_x);
2440
2441 return sizeof(*gpu_metrics);
2442 }
2443
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2444 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2445 {
2446 struct amdgpu_device *adev = smu->adev;
2447 int i;
2448
2449 for (i = 0; i < 16; i++)
2450 pci_write_config_dword(adev->pdev, i * 4,
2451 adev->pdev->saved_config_space[i]);
2452 pci_restore_msi_state(adev->pdev);
2453 }
2454
smu_v13_0_6_mode2_reset(struct smu_context * smu)2455 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2456 {
2457 int ret = 0, index;
2458 struct amdgpu_device *adev = smu->adev;
2459 int timeout = 10;
2460
2461 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2462 SMU_MSG_GfxDeviceDriverReset);
2463 if (index < 0)
2464 return index;
2465
2466 mutex_lock(&smu->message_lock);
2467
2468 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2469 SMU_RESET_MODE_2);
2470
2471 /* Reset takes a bit longer, wait for 200ms. */
2472 msleep(200);
2473
2474 dev_dbg(smu->adev->dev, "restore config space...\n");
2475 /* Restore the config space saved during init */
2476 amdgpu_device_load_pci_state(adev->pdev);
2477
2478 /* Certain platforms have switches which assign virtual BAR values to
2479 * devices. OS uses the virtual BAR values and device behind the switch
2480 * is assgined another BAR value. When device's config space registers
2481 * are queried, switch returns the virtual BAR values. When mode-2 reset
2482 * is performed, switch is unaware of it, and will continue to return
2483 * the same virtual values to the OS.This affects
2484 * pci_restore_config_space() API as it doesn't write the value saved if
2485 * the current value read from config space is the same as what is
2486 * saved. As a workaround, make sure the config space is restored
2487 * always.
2488 */
2489 if (!(adev->flags & AMD_IS_APU))
2490 smu_v13_0_6_restore_pci_config(smu);
2491
2492 dev_dbg(smu->adev->dev, "wait for reset ack\n");
2493 do {
2494 ret = smu_cmn_wait_for_response(smu);
2495 /* Wait a bit more time for getting ACK */
2496 if (ret == -ETIME) {
2497 --timeout;
2498 usleep_range(500, 1000);
2499 continue;
2500 }
2501
2502 if (ret)
2503 goto out;
2504
2505 } while (ret == -ETIME && timeout);
2506
2507 out:
2508 mutex_unlock(&smu->message_lock);
2509
2510 if (ret)
2511 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
2512 ret);
2513
2514 return ret;
2515 }
2516
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2517 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
2518 struct smu_temperature_range *range)
2519 {
2520 struct amdgpu_device *adev = smu->adev;
2521 u32 aid_temp, xcd_temp, max_temp;
2522 u32 ccd_temp = 0;
2523 int ret;
2524
2525 if (amdgpu_sriov_vf(smu->adev))
2526 return 0;
2527
2528 if (!range)
2529 return -EINVAL;
2530
2531 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
2532 if (smu->smc_fw_version < 0x554500)
2533 return 0;
2534
2535 /* Get SOC Max operating temperature */
2536 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2537 PPSMC_AID_THM_TYPE, &aid_temp);
2538 if (ret)
2539 goto failed;
2540 if (adev->flags & AMD_IS_APU) {
2541 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2542 PPSMC_CCD_THM_TYPE, &ccd_temp);
2543 if (ret)
2544 goto failed;
2545 }
2546 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2547 PPSMC_XCD_THM_TYPE, &xcd_temp);
2548 if (ret)
2549 goto failed;
2550 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
2551 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2552
2553 /* Get HBM Max operating temperature */
2554 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2555 PPSMC_HBM_THM_TYPE, &max_temp);
2556 if (ret)
2557 goto failed;
2558 range->mem_emergency_max =
2559 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2560
2561 /* Get SOC thermal throttle limit */
2562 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2563 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
2564 &max_temp);
2565 if (ret)
2566 goto failed;
2567 range->hotspot_crit_max =
2568 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2569
2570 /* Get HBM thermal throttle limit */
2571 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2572 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
2573 &max_temp);
2574 if (ret)
2575 goto failed;
2576
2577 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2578
2579 failed:
2580 return ret;
2581 }
2582
smu_v13_0_6_mode1_reset(struct smu_context * smu)2583 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
2584 {
2585 struct amdgpu_device *adev = smu->adev;
2586 u32 fatal_err, param;
2587 int ret = 0;
2588
2589 fatal_err = 0;
2590 param = SMU_RESET_MODE_1;
2591
2592 /* fatal error triggered by ras, PMFW supports the flag */
2593 if (amdgpu_ras_get_fed_status(adev))
2594 fatal_err = 1;
2595
2596 param |= (fatal_err << 16);
2597 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
2598 param, NULL);
2599
2600 if (!ret)
2601 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2602
2603 return ret;
2604 }
2605
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)2606 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
2607 {
2608 return true;
2609 }
2610
smu_v13_0_6_is_mode2_reset_supported(struct smu_context * smu)2611 static bool smu_v13_0_6_is_mode2_reset_supported(struct smu_context *smu)
2612 {
2613 return true;
2614 }
2615
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)2616 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
2617 uint32_t size)
2618 {
2619 int ret = 0;
2620
2621 /* message SMU to update the bad page number on SMUBUS */
2622 ret = smu_cmn_send_smc_msg_with_param(
2623 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2624 if (ret)
2625 dev_err(smu->adev->dev,
2626 "[%s] failed to message SMU to update HBM bad pages number\n",
2627 __func__);
2628
2629 return ret;
2630 }
2631
smu_v13_0_6_send_rma_reason(struct smu_context * smu)2632 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
2633 {
2634 struct amdgpu_device *adev = smu->adev;
2635 int ret;
2636
2637 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
2638 if ((adev->flags & AMD_IS_APU) || smu->smc_fw_version < 0x00555a00)
2639 return 0;
2640
2641 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
2642 if (ret)
2643 dev_err(smu->adev->dev,
2644 "[%s] failed to send BadPageThreshold event to SMU\n",
2645 __func__);
2646
2647 return ret;
2648 }
2649
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)2650 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
2651 {
2652 struct smu_context *smu = adev->powerplay.pp_handle;
2653
2654 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
2655 }
2656
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)2657 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
2658 {
2659 uint32_t msg;
2660 int ret;
2661
2662 if (!count)
2663 return -EINVAL;
2664
2665 switch (type) {
2666 case AMDGPU_MCA_ERROR_TYPE_UE:
2667 msg = SMU_MSG_QueryValidMcaCount;
2668 break;
2669 case AMDGPU_MCA_ERROR_TYPE_CE:
2670 msg = SMU_MSG_QueryValidMcaCeCount;
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675
2676 ret = smu_cmn_send_smc_msg(smu, msg, count);
2677 if (ret) {
2678 *count = 0;
2679 return ret;
2680 }
2681
2682 return 0;
2683 }
2684
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)2685 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2686 int idx, int offset, uint32_t *val)
2687 {
2688 uint32_t msg, param;
2689
2690 switch (type) {
2691 case AMDGPU_MCA_ERROR_TYPE_UE:
2692 msg = SMU_MSG_McaBankDumpDW;
2693 break;
2694 case AMDGPU_MCA_ERROR_TYPE_CE:
2695 msg = SMU_MSG_McaBankCeDumpDW;
2696 break;
2697 default:
2698 return -EINVAL;
2699 }
2700
2701 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
2702
2703 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
2704 }
2705
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)2706 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2707 int idx, int offset, uint32_t *val, int count)
2708 {
2709 int ret, i;
2710
2711 if (!val)
2712 return -EINVAL;
2713
2714 for (i = 0; i < count; i++) {
2715 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
2716 if (ret)
2717 return ret;
2718 }
2719
2720 return 0;
2721 }
2722
2723 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
2724 MCA_BANK_IPID(UMC, 0x96, 0x0),
2725 MCA_BANK_IPID(SMU, 0x01, 0x1),
2726 MCA_BANK_IPID(MP5, 0x01, 0x2),
2727 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
2728 };
2729
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)2730 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
2731 {
2732 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
2733 u32 instidhi, instid;
2734
2735 /* NOTE: All MCA IPID register share the same format,
2736 * so the driver can share the MCMP1 register header file.
2737 * */
2738
2739 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
2740 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
2741
2742 /*
2743 * Unfied DieID Format: SAASS. A:AID, S:Socket.
2744 * Unfied DieID[4] = InstanceId[0]
2745 * Unfied DieID[0:3] = InstanceIdHi[0:3]
2746 */
2747 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
2748 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
2749 info->aid = ((instidhi >> 2) & 0x03);
2750 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
2751 }
2752
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)2753 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
2754 int idx, int reg_idx, uint64_t *val)
2755 {
2756 struct smu_context *smu = adev->powerplay.pp_handle;
2757 uint32_t data[2] = {0, 0};
2758 int ret;
2759
2760 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
2761 return -EINVAL;
2762
2763 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
2764 if (ret)
2765 return ret;
2766
2767 *val = (uint64_t)data[1] << 32 | data[0];
2768
2769 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
2770 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
2771
2772 return 0;
2773 }
2774
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)2775 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
2776 int idx, struct mca_bank_entry *entry)
2777 {
2778 int i, ret;
2779
2780 /* NOTE: populated all mca register by default */
2781 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
2782 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
2783 if (ret)
2784 return ret;
2785 }
2786
2787 entry->idx = idx;
2788 entry->type = type;
2789
2790 mca_bank_entry_info_decode(entry, &entry->info);
2791
2792 return 0;
2793 }
2794
mca_decode_ipid_to_hwip(uint64_t val)2795 static int mca_decode_ipid_to_hwip(uint64_t val)
2796 {
2797 const struct mca_bank_ipid *ipid;
2798 uint16_t hwid, mcatype;
2799 int i;
2800
2801 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
2802 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
2803
2804 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
2805 ipid = &smu_v13_0_6_mca_ipid_table[i];
2806
2807 if (!ipid->hwid)
2808 continue;
2809
2810 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
2811 return i;
2812 }
2813
2814 return AMDGPU_MCA_IP_UNKNOW;
2815 }
2816
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2817 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2818 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2819 {
2820 uint64_t status0;
2821 uint32_t ext_error_code;
2822 uint32_t odecc_err_cnt;
2823
2824 status0 = entry->regs[MCA_REG_IDX_STATUS];
2825 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
2826 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
2827
2828 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
2829 *count = 0;
2830 return 0;
2831 }
2832
2833 if (umc_v12_0_is_deferred_error(adev, status0) ||
2834 umc_v12_0_is_uncorrectable_error(adev, status0) ||
2835 umc_v12_0_is_correctable_error(adev, status0))
2836 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
2837
2838 amdgpu_umc_update_ecc_status(adev,
2839 entry->regs[MCA_REG_IDX_STATUS],
2840 entry->regs[MCA_REG_IDX_IPID],
2841 entry->regs[MCA_REG_IDX_ADDR]);
2842
2843 return 0;
2844 }
2845
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2846 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2847 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
2848 uint32_t *count)
2849 {
2850 u32 ext_error_code;
2851 u32 err_cnt;
2852
2853 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
2854 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
2855
2856 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
2857 (ext_error_code == 0 || ext_error_code == 9))
2858 *count = err_cnt;
2859 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
2860 *count = err_cnt;
2861
2862 return 0;
2863 }
2864
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)2865 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
2866 uint32_t errcode)
2867 {
2868 int i;
2869
2870 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
2871 return true;
2872
2873 for (i = 0; i < mca_ras->err_code_count; i++) {
2874 if (errcode == mca_ras->err_code_array[i])
2875 return true;
2876 }
2877
2878 return false;
2879 }
2880
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2881 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2882 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2883 {
2884 uint64_t status0, misc0;
2885
2886 status0 = entry->regs[MCA_REG_IDX_STATUS];
2887 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
2888 *count = 0;
2889 return 0;
2890 }
2891
2892 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
2893 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
2894 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
2895 *count = 1;
2896 return 0;
2897 } else {
2898 misc0 = entry->regs[MCA_REG_IDX_MISC0];
2899 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
2900 }
2901
2902 return 0;
2903 }
2904
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)2905 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2906 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2907 {
2908 uint64_t status0, misc0;
2909
2910 status0 = entry->regs[MCA_REG_IDX_STATUS];
2911 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
2912 *count = 0;
2913 return 0;
2914 }
2915
2916 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
2917 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
2918 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
2919 if (count)
2920 *count = 1;
2921 return 0;
2922 }
2923
2924 misc0 = entry->regs[MCA_REG_IDX_MISC0];
2925 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
2926
2927 return 0;
2928 }
2929
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)2930 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2931 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2932 {
2933 uint32_t instlo;
2934
2935 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
2936 instlo &= GENMASK(31, 1);
2937 switch (instlo) {
2938 case 0x36430400: /* SMNAID XCD 0 */
2939 case 0x38430400: /* SMNAID XCD 1 */
2940 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
2941 return true;
2942 default:
2943 return false;
2944 }
2945
2946 return false;
2947 };
2948
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)2949 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
2950 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2951 {
2952 struct smu_context *smu = adev->powerplay.pp_handle;
2953 uint32_t errcode, instlo;
2954
2955 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
2956 instlo &= GENMASK(31, 1);
2957 if (instlo != 0x03b30400)
2958 return false;
2959
2960 if (!(adev->flags & AMD_IS_APU) && smu->smc_fw_version >= 0x00555600) {
2961 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
2962 errcode &= 0xff;
2963 } else {
2964 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
2965 }
2966
2967 return mca_smu_check_error_code(adev, mca_ras, errcode);
2968 }
2969
2970 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
2971 static int mmhub_err_codes[] = {
2972 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
2973 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
2974 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
2975 };
2976
2977 static const struct mca_ras_info mca_ras_table[] = {
2978 {
2979 .blkid = AMDGPU_RAS_BLOCK__UMC,
2980 .ip = AMDGPU_MCA_IP_UMC,
2981 .get_err_count = mca_umc_mca_get_err_count,
2982 }, {
2983 .blkid = AMDGPU_RAS_BLOCK__GFX,
2984 .ip = AMDGPU_MCA_IP_SMU,
2985 .get_err_count = mca_gfx_mca_get_err_count,
2986 .bank_is_valid = mca_gfx_smu_bank_is_valid,
2987 }, {
2988 .blkid = AMDGPU_RAS_BLOCK__SDMA,
2989 .ip = AMDGPU_MCA_IP_SMU,
2990 .err_code_array = sdma_err_codes,
2991 .err_code_count = ARRAY_SIZE(sdma_err_codes),
2992 .get_err_count = mca_smu_mca_get_err_count,
2993 .bank_is_valid = mca_smu_bank_is_valid,
2994 }, {
2995 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
2996 .ip = AMDGPU_MCA_IP_SMU,
2997 .err_code_array = mmhub_err_codes,
2998 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
2999 .get_err_count = mca_smu_mca_get_err_count,
3000 .bank_is_valid = mca_smu_bank_is_valid,
3001 }, {
3002 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3003 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3004 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3005 },
3006 };
3007
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3008 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3009 {
3010 int i;
3011
3012 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3013 if (mca_ras_table[i].blkid == blkid)
3014 return &mca_ras_table[i];
3015 }
3016
3017 return NULL;
3018 }
3019
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3020 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3021 {
3022 struct smu_context *smu = adev->powerplay.pp_handle;
3023 int ret;
3024
3025 switch (type) {
3026 case AMDGPU_MCA_ERROR_TYPE_UE:
3027 case AMDGPU_MCA_ERROR_TYPE_CE:
3028 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3029 break;
3030 default:
3031 ret = -EINVAL;
3032 break;
3033 }
3034
3035 return ret;
3036 }
3037
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3038 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3039 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3040 {
3041 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3042 return false;
3043
3044 if (mca_ras->bank_is_valid)
3045 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3046
3047 return true;
3048 }
3049
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3050 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3051 struct mca_bank_entry *entry, uint32_t *count)
3052 {
3053 const struct mca_ras_info *mca_ras;
3054
3055 if (!entry || !count)
3056 return -EINVAL;
3057
3058 mca_ras = mca_get_mca_ras_info(adev, blk);
3059 if (!mca_ras)
3060 return -EOPNOTSUPP;
3061
3062 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3063 *count = 0;
3064 return 0;
3065 }
3066
3067 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3068 }
3069
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3070 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3071 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3072 {
3073 return mca_get_mca_entry(adev, type, idx, entry);
3074 }
3075
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3076 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3077 enum amdgpu_mca_error_type type, uint32_t *count)
3078 {
3079 return mca_get_valid_mca_count(adev, type, count);
3080 }
3081
3082 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3083 .max_ue_count = 12,
3084 .max_ce_count = 12,
3085 .mca_set_debug_mode = mca_smu_set_debug_mode,
3086 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3087 .mca_get_mca_entry = mca_smu_get_mca_entry,
3088 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3089 };
3090
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3091 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3092 {
3093 struct smu_context *smu = adev->powerplay.pp_handle;
3094
3095 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3096 }
3097
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3098 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3099 {
3100 uint32_t msg;
3101 int ret;
3102
3103 if (!count)
3104 return -EINVAL;
3105
3106 switch (type) {
3107 case ACA_SMU_TYPE_UE:
3108 msg = SMU_MSG_QueryValidMcaCount;
3109 break;
3110 case ACA_SMU_TYPE_CE:
3111 msg = SMU_MSG_QueryValidMcaCeCount;
3112 break;
3113 default:
3114 return -EINVAL;
3115 }
3116
3117 ret = smu_cmn_send_smc_msg(smu, msg, count);
3118 if (ret) {
3119 *count = 0;
3120 return ret;
3121 }
3122
3123 return 0;
3124 }
3125
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3126 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3127 enum aca_smu_type type, u32 *count)
3128 {
3129 struct smu_context *smu = adev->powerplay.pp_handle;
3130 int ret;
3131
3132 switch (type) {
3133 case ACA_SMU_TYPE_UE:
3134 case ACA_SMU_TYPE_CE:
3135 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3136 break;
3137 default:
3138 ret = -EINVAL;
3139 break;
3140 }
3141
3142 return ret;
3143 }
3144
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3145 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3146 int idx, int offset, u32 *val)
3147 {
3148 uint32_t msg, param;
3149
3150 switch (type) {
3151 case ACA_SMU_TYPE_UE:
3152 msg = SMU_MSG_McaBankDumpDW;
3153 break;
3154 case ACA_SMU_TYPE_CE:
3155 msg = SMU_MSG_McaBankCeDumpDW;
3156 break;
3157 default:
3158 return -EINVAL;
3159 }
3160
3161 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3162
3163 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3164 }
3165
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3166 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3167 int idx, int offset, u32 *val, int count)
3168 {
3169 int ret, i;
3170
3171 if (!val)
3172 return -EINVAL;
3173
3174 for (i = 0; i < count; i++) {
3175 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3176 if (ret)
3177 return ret;
3178 }
3179
3180 return 0;
3181 }
3182
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3183 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3184 int idx, int reg_idx, u64 *val)
3185 {
3186 struct smu_context *smu = adev->powerplay.pp_handle;
3187 u32 data[2] = {0, 0};
3188 int ret;
3189
3190 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3191 return -EINVAL;
3192
3193 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3194 if (ret)
3195 return ret;
3196
3197 *val = (u64)data[1] << 32 | data[0];
3198
3199 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3200 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3201
3202 return 0;
3203 }
3204
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3205 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3206 enum aca_smu_type type, int idx, struct aca_bank *bank)
3207 {
3208 int i, ret, count;
3209
3210 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3211 for (i = 0; i < count; i++) {
3212 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3213 if (ret)
3214 return ret;
3215 }
3216
3217 return 0;
3218 }
3219
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3220 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3221 {
3222 int error_code;
3223
3224 if (!(adev->flags & AMD_IS_APU) && adev->pm.fw_version >= 0x00555600)
3225 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3226 else
3227 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3228
3229 return error_code & 0xff;
3230 }
3231
3232 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3233 .max_ue_bank_count = 12,
3234 .max_ce_bank_count = 12,
3235 .set_debug_mode = aca_smu_set_debug_mode,
3236 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3237 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3238 .parse_error_code = aca_smu_parse_error_code,
3239 };
3240
3241 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3242 /* init dpm */
3243 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3244 /* dpm/clk tables */
3245 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3246 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3247 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3248 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3249 .read_sensor = smu_v13_0_6_read_sensor,
3250 .set_performance_level = smu_v13_0_6_set_performance_level,
3251 .get_power_limit = smu_v13_0_6_get_power_limit,
3252 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3253 .get_unique_id = smu_v13_0_6_get_unique_id,
3254 .init_microcode = smu_v13_0_6_init_microcode,
3255 .fini_microcode = smu_v13_0_fini_microcode,
3256 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3257 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3258 .init_power = smu_v13_0_init_power,
3259 .fini_power = smu_v13_0_fini_power,
3260 .check_fw_status = smu_v13_0_6_check_fw_status,
3261 /* pptable related */
3262 .check_fw_version = smu_v13_0_check_fw_version,
3263 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3264 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3265 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3266 .system_features_control = smu_v13_0_6_system_features_control,
3267 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3268 .send_smc_msg = smu_cmn_send_smc_msg,
3269 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3270 .feature_is_enabled = smu_cmn_feature_is_enabled,
3271 .set_power_limit = smu_v13_0_6_set_power_limit,
3272 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3273 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3274 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3275 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3276 .setup_pptable = smu_v13_0_6_setup_pptable,
3277 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3278 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3279 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3280 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3281 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3282 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3283 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3284 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3285 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3286 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3287 .mode2_reset_is_support = smu_v13_0_6_is_mode2_reset_supported,
3288 .mode1_reset = smu_v13_0_6_mode1_reset,
3289 .mode2_reset = smu_v13_0_6_mode2_reset,
3290 .wait_for_event = smu_v13_0_wait_for_event,
3291 .i2c_init = smu_v13_0_6_i2c_control_init,
3292 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3293 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3294 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3295 };
3296
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3297 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3298 {
3299 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3300 smu->message_map = smu_v13_0_6_message_map;
3301 smu->clock_map = smu_v13_0_6_clk_map;
3302 smu->feature_map = smu_v13_0_6_feature_mask_map;
3303 smu->table_map = smu_v13_0_6_table_map;
3304 smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
3305 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3306 smu_v13_0_set_smu_mailbox_registers(smu);
3307 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3308 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3309 }
3310