1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_0_ppt.h"
39 #include "smu_v13_0_0_pptable.h"
40 #include "smu_v13_0_0_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
63 int od_feature_bit,
64 int32_t *min, int32_t *max);
65
66 static const struct smu_feature_bits smu_v13_0_0_dpm_features = {
67 .bits = {
68 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
69 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
70 SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
71 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
72 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
73 SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)
74 }
75 };
76
77 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
78
79 #define mmMP1_SMN_C2PMSG_75 0x028b
80 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
81
82 #define mmMP1_SMN_C2PMSG_53 0x0275
83 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
84
85 #define mmMP1_SMN_C2PMSG_54 0x0276
86 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
87
88 #define DEBUGSMC_MSG_Mode1Reset 2
89
90 /*
91 * SMU_v13_0_10 supports ECCTABLE since version 80.34.0,
92 * use this to check ECCTABLE feature whether support
93 */
94 #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200
95
96 #define PP_OD_FEATURE_GFXCLK_FMIN 0
97 #define PP_OD_FEATURE_GFXCLK_FMAX 1
98 #define PP_OD_FEATURE_UCLK_FMIN 2
99 #define PP_OD_FEATURE_UCLK_FMAX 3
100 #define PP_OD_FEATURE_GFX_VF_CURVE 4
101 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
102 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
103 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
104 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
105 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
106 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
107 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
108 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
109
110 #define LINK_SPEED_MAX 3
111
112 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
113 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
114 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
115 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
116 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
117 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
118 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
119 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
120 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
121 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
122 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
123 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
124 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
125 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
126 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0),
127 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
128 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
129 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
130 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
131 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
132 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
133 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
134 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
135 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
136 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
137 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
138 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
139 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
140 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
141 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
142 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
143 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
144 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
145 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
146 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
147 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
148 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
149 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 0),
150 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
151 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
152 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
153 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
154 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
155 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
156 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
157 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
158 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
159 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
160 MSG_MAP(Mode2Reset, PPSMC_MSG_Mode2Reset, 0),
161 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
162 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
163 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
164 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
165 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
166 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
167 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
168 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
169 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
170 MSG_MAP(DALNotPresent, PPSMC_MSG_DALNotPresent, 0),
171 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
172 };
173
174 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
175 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
176 CLK_MAP(SCLK, PPCLK_GFXCLK),
177 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
178 CLK_MAP(FCLK, PPCLK_FCLK),
179 CLK_MAP(UCLK, PPCLK_UCLK),
180 CLK_MAP(MCLK, PPCLK_UCLK),
181 CLK_MAP(VCLK, PPCLK_VCLK_0),
182 CLK_MAP(VCLK1, PPCLK_VCLK_1),
183 CLK_MAP(DCLK, PPCLK_DCLK_0),
184 CLK_MAP(DCLK1, PPCLK_DCLK_1),
185 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
186 };
187
188 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
189 FEA_MAP(FW_DATA_READ),
190 FEA_MAP(DPM_GFXCLK),
191 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
192 FEA_MAP(DPM_UCLK),
193 FEA_MAP(DPM_FCLK),
194 FEA_MAP(DPM_SOCCLK),
195 FEA_MAP(DPM_MP0CLK),
196 FEA_MAP(DPM_LINK),
197 FEA_MAP(DPM_DCN),
198 FEA_MAP(VMEMP_SCALING),
199 FEA_MAP(VDDIO_MEM_SCALING),
200 FEA_MAP(DS_GFXCLK),
201 FEA_MAP(DS_SOCCLK),
202 FEA_MAP(DS_FCLK),
203 FEA_MAP(DS_LCLK),
204 FEA_MAP(DS_DCFCLK),
205 FEA_MAP(DS_UCLK),
206 FEA_MAP(GFX_ULV),
207 FEA_MAP(FW_DSTATE),
208 FEA_MAP(GFXOFF),
209 FEA_MAP(BACO),
210 FEA_MAP(MM_DPM),
211 FEA_MAP(SOC_MPCLK_DS),
212 FEA_MAP(BACO_MPCLK_DS),
213 FEA_MAP(THROTTLERS),
214 FEA_MAP(SMARTSHIFT),
215 FEA_MAP(GTHR),
216 FEA_MAP(ACDC),
217 FEA_MAP(VR0HOT),
218 FEA_MAP(FW_CTF),
219 FEA_MAP(FAN_CONTROL),
220 FEA_MAP(GFX_DCS),
221 FEA_MAP(GFX_READ_MARGIN),
222 FEA_MAP(LED_DISPLAY),
223 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
224 FEA_MAP(OUT_OF_BAND_MONITOR),
225 FEA_MAP(OPTIMIZED_VMIN),
226 FEA_MAP(GFX_IMU),
227 FEA_MAP(BOOT_TIME_CAL),
228 FEA_MAP(GFX_PCC_DFLL),
229 FEA_MAP(SOC_CG),
230 FEA_MAP(DF_CSTATE),
231 FEA_MAP(GFX_EDC),
232 FEA_MAP(BOOT_POWER_OPT),
233 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
234 FEA_MAP(DS_VCN),
235 FEA_MAP(BACO_CG),
236 FEA_MAP(MEM_TEMP_READ),
237 FEA_MAP(ATHUB_MMHUB_PG),
238 FEA_MAP(SOC_PCC),
239 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
240 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
241 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
242 };
243
244 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
245 TAB_MAP(PPTABLE),
246 TAB_MAP(WATERMARKS),
247 TAB_MAP(AVFS_PSM_DEBUG),
248 TAB_MAP(PMSTATUSLOG),
249 TAB_MAP(SMU_METRICS),
250 TAB_MAP(DRIVER_SMU_CONFIG),
251 TAB_MAP(ACTIVITY_MONITOR_COEFF),
252 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
253 TAB_MAP(I2C_COMMANDS),
254 TAB_MAP(ECCINFO),
255 TAB_MAP(OVERDRIVE),
256 TAB_MAP(WIFIBAND),
257 };
258
259 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
260 PWR_MAP(AC),
261 PWR_MAP(DC),
262 };
263
264 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
265 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
266 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
267 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
268 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
269 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
270 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
271 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
272 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
273 };
274
275 static const uint8_t smu_v13_0_0_throttler_map[] = {
276 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
277 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
278 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
279 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
280 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
281 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
282 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
283 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
284 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
285 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
286 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
287 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
288 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
289 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
290 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
291 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
292 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
293 };
294
295 static int
smu_v13_0_0_init_allowed_features(struct smu_context * smu)296 smu_v13_0_0_init_allowed_features(struct smu_context *smu)
297 {
298 struct amdgpu_device *adev = smu->adev;
299
300 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
301
302 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
303 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
304 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
305 }
306
307 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
308 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
309 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
310
311 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
312 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
313
314 if ((smu->smc_fw_version < 0x004e3a00) ||
315 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
316 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
317
318 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
319 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
320 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
321 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
322 }
323
324 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
325 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
326
327 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
328 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
329 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
330 }
331
332 if (!(adev->pm.pp_feature & PP_ULV_MASK))
333 smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
334
335 return 0;
336 }
337
smu_v13_0_0_check_powerplay_table(struct smu_context * smu)338 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
339 {
340 struct smu_table_context *table_context = &smu->smu_table;
341 struct smu_13_0_0_powerplay_table *powerplay_table =
342 table_context->power_play_table;
343 struct smu_baco_context *smu_baco = &smu->smu_baco;
344 PPTable_t *pptable = smu->smu_table.driver_pptable;
345 const OverDriveLimits_t * const overdrive_upperlimits =
346 &pptable->SkuTable.OverDriveLimitsBasicMax;
347 const OverDriveLimits_t * const overdrive_lowerlimits =
348 &pptable->SkuTable.OverDriveLimitsMin;
349
350 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
351 smu->dc_controlled_by_gpio = true;
352
353 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) {
354 smu_baco->platform_support = true;
355
356 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
357 smu_baco->maco_support = true;
358 }
359
360 if (!overdrive_lowerlimits->FeatureCtrlMask ||
361 !overdrive_upperlimits->FeatureCtrlMask)
362 smu->od_enabled = false;
363
364 table_context->thermal_controller_type =
365 powerplay_table->thermal_controller_type;
366
367 /*
368 * Instead of having its own buffer space and get overdrive_table copied,
369 * smu->od_settings just points to the actual overdrive_table
370 */
371 smu->od_settings = &powerplay_table->overdrive_table;
372
373 smu->adev->pm.no_fan =
374 !(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
375
376 return 0;
377 }
378
smu_v13_0_0_store_powerplay_table(struct smu_context * smu)379 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
380 {
381 struct smu_table_context *table_context = &smu->smu_table;
382 struct smu_13_0_0_powerplay_table *powerplay_table =
383 table_context->power_play_table;
384
385 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
386 sizeof(PPTable_t));
387
388 return 0;
389 }
390
391 #ifndef atom_smc_dpm_info_table_13_0_0
392 struct atom_smc_dpm_info_table_13_0_0 {
393 struct atom_common_table_header table_header;
394 BoardTable_t BoardTable;
395 };
396 #endif
397
smu_v13_0_0_append_powerplay_table(struct smu_context * smu)398 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
399 {
400 struct smu_table_context *table_context = &smu->smu_table;
401 PPTable_t *smc_pptable = table_context->driver_pptable;
402 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
403 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
404 int index, ret;
405
406 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
407 smc_dpm_info);
408
409 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
410 (uint8_t **)&smc_dpm_table);
411 if (ret)
412 return ret;
413
414 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
415
416 return 0;
417 }
418
smu_v13_0_0_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)419 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
420 void **table,
421 uint32_t *size)
422 {
423 struct smu_table_context *smu_table = &smu->smu_table;
424 void *combo_pptable = smu_table->combo_pptable;
425 int ret = 0;
426
427 ret = smu_cmn_get_combo_pptable(smu);
428 if (ret)
429 return ret;
430
431 *table = combo_pptable;
432 *size = sizeof(struct smu_13_0_0_powerplay_table);
433
434 return 0;
435 }
436
smu_v13_0_0_setup_pptable(struct smu_context * smu)437 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
438 {
439 struct smu_table_context *smu_table = &smu->smu_table;
440 struct amdgpu_device *adev = smu->adev;
441 int ret = 0;
442
443 if (amdgpu_sriov_vf(smu->adev))
444 return 0;
445
446 ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
447 &smu_table->power_play_table,
448 &smu_table->power_play_table_size);
449 if (ret)
450 return ret;
451
452 ret = smu_v13_0_0_store_powerplay_table(smu);
453 if (ret)
454 return ret;
455
456 /*
457 * With SCPM enabled, the operation below will be handled
458 * by PSP. Driver involvment is unnecessary and useless.
459 */
460 if (!adev->scpm_enabled) {
461 ret = smu_v13_0_0_append_powerplay_table(smu);
462 if (ret)
463 return ret;
464 }
465
466 ret = smu_v13_0_0_check_powerplay_table(smu);
467 if (ret)
468 return ret;
469
470 return ret;
471 }
472
smu_v13_0_0_tables_init(struct smu_context * smu)473 static int smu_v13_0_0_tables_init(struct smu_context *smu)
474 {
475 struct smu_table_context *smu_table = &smu->smu_table;
476 struct smu_table *tables = smu_table->tables;
477 int ret;
478
479 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
480 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
481 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
482 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
483 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
484 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
485 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
486 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
487 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
488 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
489 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
490 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
491 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
492 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
493 AMDGPU_GEM_DOMAIN_VRAM);
494 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
496 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
497 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
498 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
499 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
500 AMDGPU_GEM_DOMAIN_VRAM);
501
502 smu_table->metrics_table = kzalloc_obj(SmuMetricsExternal_t);
503 if (!smu_table->metrics_table)
504 goto err0_out;
505 smu_table->metrics_time = 0;
506
507 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
508 sizeof(struct gpu_metrics_v1_3),
509 SMU_GPU_METRICS_CACHE_INTERVAL);
510 if (ret)
511 goto err1_out;
512
513 smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
514 if (!smu_table->watermarks_table)
515 goto err2_out;
516
517 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
518 if (!smu_table->ecc_table)
519 goto err3_out;
520
521 return 0;
522
523 err3_out:
524 kfree(smu_table->watermarks_table);
525 err2_out:
526 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
527 err1_out:
528 kfree(smu_table->metrics_table);
529 err0_out:
530 return -ENOMEM;
531 }
532
smu_v13_0_0_allocate_dpm_context(struct smu_context * smu)533 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
534 {
535 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
536
537 smu_dpm->dpm_context = kzalloc_obj(struct smu_13_0_dpm_context);
538 if (!smu_dpm->dpm_context)
539 return -ENOMEM;
540
541 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
542
543 return 0;
544 }
545
smu_v13_0_0_init_smc_tables(struct smu_context * smu)546 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
547 {
548 int ret = 0;
549
550 ret = smu_v13_0_0_tables_init(smu);
551 if (ret)
552 return ret;
553
554 ret = smu_v13_0_0_allocate_dpm_context(smu);
555 if (ret)
556 return ret;
557
558 return smu_v13_0_init_smc_tables(smu);
559 }
560
smu_v13_0_0_set_default_dpm_table(struct smu_context * smu)561 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
562 {
563 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
564 struct smu_table_context *table_context = &smu->smu_table;
565 PPTable_t *pptable = table_context->driver_pptable;
566 SkuTable_t *skutable = &pptable->SkuTable;
567 struct smu_dpm_table *dpm_table;
568 int ret = 0;
569
570 /* socclk dpm table setup */
571 dpm_table = &dpm_context->dpm_tables.soc_table;
572 dpm_table->clk_type = SMU_SOCCLK;
573 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
574 ret = smu_v13_0_set_single_dpm_table(smu,
575 SMU_SOCCLK,
576 dpm_table);
577 if (ret)
578 return ret;
579 } else {
580 dpm_table->count = 1;
581 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
582 dpm_table->dpm_levels[0].enabled = true;
583 }
584
585 /* gfxclk dpm table setup */
586 dpm_table = &dpm_context->dpm_tables.gfx_table;
587 dpm_table->clk_type = SMU_GFXCLK;
588 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
589 ret = smu_v13_0_set_single_dpm_table(smu,
590 SMU_GFXCLK,
591 dpm_table);
592 if (ret)
593 return ret;
594
595 /*
596 * Update the reported maximum shader clock to the value
597 * which can be guarded to be achieved on all cards. This
598 * is aligned with Window setting. And considering that value
599 * might be not the peak frequency the card can achieve, it
600 * is normal some real-time clock frequency can overtake this
601 * labelled maximum clock frequency(for example in pp_dpm_sclk
602 * sysfs output).
603 */
604 if (skutable->DriverReportedClocks.GameClockAc &&
605 (dpm_table->dpm_levels[dpm_table->count - 1].value >
606 skutable->DriverReportedClocks.GameClockAc)) {
607 dpm_table->dpm_levels[dpm_table->count - 1].value =
608 skutable->DriverReportedClocks.GameClockAc;
609 }
610 } else {
611 dpm_table->count = 1;
612 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
613 dpm_table->dpm_levels[0].enabled = true;
614 }
615
616 /* uclk dpm table setup */
617 dpm_table = &dpm_context->dpm_tables.uclk_table;
618 dpm_table->clk_type = SMU_UCLK;
619 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
620 ret = smu_v13_0_set_single_dpm_table(smu,
621 SMU_UCLK,
622 dpm_table);
623 if (ret)
624 return ret;
625 } else {
626 dpm_table->count = 1;
627 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
628 dpm_table->dpm_levels[0].enabled = true;
629 }
630
631 /* fclk dpm table setup */
632 dpm_table = &dpm_context->dpm_tables.fclk_table;
633 dpm_table->clk_type = SMU_FCLK;
634 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
635 ret = smu_v13_0_set_single_dpm_table(smu,
636 SMU_FCLK,
637 dpm_table);
638 if (ret)
639 return ret;
640 } else {
641 dpm_table->count = 1;
642 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
643 dpm_table->dpm_levels[0].enabled = true;
644 }
645
646 /* vclk dpm table setup */
647 dpm_table = &dpm_context->dpm_tables.vclk_table;
648 dpm_table->clk_type = SMU_VCLK;
649 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
650 ret = smu_v13_0_set_single_dpm_table(smu,
651 SMU_VCLK,
652 dpm_table);
653 if (ret)
654 return ret;
655 } else {
656 dpm_table->count = 1;
657 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
658 dpm_table->dpm_levels[0].enabled = true;
659 }
660
661 /* dclk dpm table setup */
662 dpm_table = &dpm_context->dpm_tables.dclk_table;
663 dpm_table->clk_type = SMU_DCLK;
664 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
665 ret = smu_v13_0_set_single_dpm_table(smu,
666 SMU_DCLK,
667 dpm_table);
668 if (ret)
669 return ret;
670 } else {
671 dpm_table->count = 1;
672 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
673 dpm_table->dpm_levels[0].enabled = true;
674 }
675
676 /* dcefclk dpm table setup */
677 dpm_table = &dpm_context->dpm_tables.dcef_table;
678 dpm_table->clk_type = SMU_DCEFCLK;
679 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
680 ret = smu_v13_0_set_single_dpm_table(smu,
681 SMU_DCEFCLK,
682 dpm_table);
683 if (ret)
684 return ret;
685 } else {
686 dpm_table->count = 1;
687 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
688 dpm_table->dpm_levels[0].enabled = true;
689 }
690
691 return 0;
692 }
693
smu_v13_0_0_is_dpm_running(struct smu_context * smu)694 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
695 {
696 int ret = 0;
697 struct smu_feature_bits feature_enabled;
698
699 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
700 if (ret)
701 return false;
702
703 return smu_feature_bits_test_mask(&feature_enabled,
704 smu_v13_0_0_dpm_features.bits);
705 }
706
smu_v13_0_0_system_features_control(struct smu_context * smu,bool en)707 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
708 bool en)
709 {
710 return smu_v13_0_system_features_control(smu, en);
711 }
712
smu_v13_0_get_throttler_status(SmuMetrics_t * metrics)713 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
714 {
715 uint32_t throttler_status = 0;
716 int i;
717
718 for (i = 0; i < THROTTLER_COUNT; i++)
719 throttler_status |=
720 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
721
722 return throttler_status;
723 }
724
725 #define SMU_13_0_0_BUSY_THRESHOLD 15
smu_v13_0_0_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)726 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
727 MetricsMember_t member,
728 uint32_t *value)
729 {
730 struct smu_table_context *smu_table = &smu->smu_table;
731 SmuMetrics_t *metrics =
732 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
733 int ret = 0;
734
735 ret = smu_cmn_get_metrics_table(smu,
736 NULL,
737 false);
738 if (ret)
739 return ret;
740
741 switch (member) {
742 case METRICS_CURR_GFXCLK:
743 *value = metrics->CurrClock[PPCLK_GFXCLK];
744 break;
745 case METRICS_CURR_SOCCLK:
746 *value = metrics->CurrClock[PPCLK_SOCCLK];
747 break;
748 case METRICS_CURR_UCLK:
749 *value = metrics->CurrClock[PPCLK_UCLK];
750 break;
751 case METRICS_CURR_VCLK:
752 *value = metrics->CurrClock[PPCLK_VCLK_0];
753 break;
754 case METRICS_CURR_VCLK1:
755 *value = metrics->CurrClock[PPCLK_VCLK_1];
756 break;
757 case METRICS_CURR_DCLK:
758 *value = metrics->CurrClock[PPCLK_DCLK_0];
759 break;
760 case METRICS_CURR_DCLK1:
761 *value = metrics->CurrClock[PPCLK_DCLK_1];
762 break;
763 case METRICS_CURR_FCLK:
764 *value = metrics->CurrClock[PPCLK_FCLK];
765 break;
766 case METRICS_CURR_DCEFCLK:
767 *value = metrics->CurrClock[PPCLK_DCFCLK];
768 break;
769 case METRICS_AVERAGE_GFXCLK:
770 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
771 *value = metrics->AverageGfxclkFrequencyPostDs;
772 else
773 *value = metrics->AverageGfxclkFrequencyPreDs;
774 break;
775 case METRICS_AVERAGE_FCLK:
776 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_0_BUSY_THRESHOLD)
777 *value = metrics->AverageFclkFrequencyPostDs;
778 else
779 *value = metrics->AverageFclkFrequencyPreDs;
780 break;
781 case METRICS_AVERAGE_UCLK:
782 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_0_BUSY_THRESHOLD)
783 *value = metrics->AverageMemclkFrequencyPostDs;
784 else
785 *value = metrics->AverageMemclkFrequencyPreDs;
786 break;
787 case METRICS_AVERAGE_VCLK:
788 *value = metrics->AverageVclk0Frequency;
789 break;
790 case METRICS_AVERAGE_DCLK:
791 *value = metrics->AverageDclk0Frequency;
792 break;
793 case METRICS_AVERAGE_VCLK1:
794 *value = metrics->AverageVclk1Frequency;
795 break;
796 case METRICS_AVERAGE_DCLK1:
797 *value = metrics->AverageDclk1Frequency;
798 break;
799 case METRICS_AVERAGE_GFXACTIVITY:
800 *value = metrics->AverageGfxActivity;
801 break;
802 case METRICS_AVERAGE_MEMACTIVITY:
803 *value = smu_safe_u16_nn(metrics->AverageUclkActivity);
804 break;
805 case METRICS_AVERAGE_VCNACTIVITY:
806 *value = max(metrics->Vcn0ActivityPercentage,
807 metrics->Vcn1ActivityPercentage);
808 break;
809 case METRICS_AVERAGE_SOCKETPOWER:
810 *value = metrics->AverageSocketPower << 8;
811 break;
812 case METRICS_TEMPERATURE_EDGE:
813 *value = metrics->AvgTemperature[TEMP_EDGE] *
814 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
815 break;
816 case METRICS_TEMPERATURE_HOTSPOT:
817 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
818 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
819 break;
820 case METRICS_TEMPERATURE_MEM:
821 *value = metrics->AvgTemperature[TEMP_MEM] *
822 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
823 break;
824 case METRICS_TEMPERATURE_VRGFX:
825 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
826 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
827 break;
828 case METRICS_TEMPERATURE_VRSOC:
829 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
830 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
831 break;
832 case METRICS_THROTTLER_STATUS:
833 *value = smu_v13_0_get_throttler_status(metrics);
834 break;
835 case METRICS_CURR_FANSPEED:
836 *value = metrics->AvgFanRpm;
837 break;
838 case METRICS_CURR_FANPWM:
839 *value = metrics->AvgFanPwm;
840 break;
841 case METRICS_VOLTAGE_VDDGFX:
842 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
843 break;
844 case METRICS_PCIE_RATE:
845 *value = metrics->PcieRate;
846 break;
847 case METRICS_PCIE_WIDTH:
848 *value = metrics->PcieWidth;
849 break;
850 default:
851 *value = UINT_MAX;
852 break;
853 }
854
855 return ret;
856 }
857
smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)858 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
859 enum smu_clk_type clk_type,
860 uint32_t *min,
861 uint32_t *max)
862 {
863 struct smu_13_0_dpm_context *dpm_context =
864 smu->smu_dpm.dpm_context;
865 struct smu_dpm_table *dpm_table;
866
867 switch (clk_type) {
868 case SMU_MCLK:
869 case SMU_UCLK:
870 /* uclk dpm table */
871 dpm_table = &dpm_context->dpm_tables.uclk_table;
872 break;
873 case SMU_GFXCLK:
874 case SMU_SCLK:
875 /* gfxclk dpm table */
876 dpm_table = &dpm_context->dpm_tables.gfx_table;
877 break;
878 case SMU_SOCCLK:
879 /* socclk dpm table */
880 dpm_table = &dpm_context->dpm_tables.soc_table;
881 break;
882 case SMU_FCLK:
883 /* fclk dpm table */
884 dpm_table = &dpm_context->dpm_tables.fclk_table;
885 break;
886 case SMU_VCLK:
887 case SMU_VCLK1:
888 /* vclk dpm table */
889 dpm_table = &dpm_context->dpm_tables.vclk_table;
890 break;
891 case SMU_DCLK:
892 case SMU_DCLK1:
893 /* dclk dpm table */
894 dpm_table = &dpm_context->dpm_tables.dclk_table;
895 break;
896 default:
897 dev_err(smu->adev->dev, "Unsupported clock type!\n");
898 return -EINVAL;
899 }
900
901 if (min)
902 *min = SMU_DPM_TABLE_MIN(dpm_table);
903 if (max)
904 *max = SMU_DPM_TABLE_MAX(dpm_table);
905
906 return 0;
907 }
908
smu_v13_0_0_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)909 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
910 enum amd_pp_sensors sensor,
911 void *data,
912 uint32_t *size)
913 {
914 struct smu_table_context *table_context = &smu->smu_table;
915 PPTable_t *smc_pptable = table_context->driver_pptable;
916 int ret = 0;
917
918 switch (sensor) {
919 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
920 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
921 *size = 4;
922 break;
923 case AMDGPU_PP_SENSOR_MEM_LOAD:
924 ret = smu_v13_0_0_get_smu_metrics_data(smu,
925 METRICS_AVERAGE_MEMACTIVITY,
926 (uint32_t *)data);
927 *size = 4;
928 break;
929 case AMDGPU_PP_SENSOR_GPU_LOAD:
930 ret = smu_v13_0_0_get_smu_metrics_data(smu,
931 METRICS_AVERAGE_GFXACTIVITY,
932 (uint32_t *)data);
933 *size = 4;
934 break;
935 case AMDGPU_PP_SENSOR_VCN_LOAD:
936 ret = smu_v13_0_0_get_smu_metrics_data(smu,
937 METRICS_AVERAGE_VCNACTIVITY,
938 (uint32_t *)data);
939 *size = 4;
940 break;
941 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
942 ret = smu_v13_0_0_get_smu_metrics_data(smu,
943 METRICS_AVERAGE_SOCKETPOWER,
944 (uint32_t *)data);
945 *size = 4;
946 break;
947 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
948 ret = smu_v13_0_0_get_smu_metrics_data(smu,
949 METRICS_TEMPERATURE_HOTSPOT,
950 (uint32_t *)data);
951 *size = 4;
952 break;
953 case AMDGPU_PP_SENSOR_EDGE_TEMP:
954 ret = smu_v13_0_0_get_smu_metrics_data(smu,
955 METRICS_TEMPERATURE_EDGE,
956 (uint32_t *)data);
957 *size = 4;
958 break;
959 case AMDGPU_PP_SENSOR_MEM_TEMP:
960 ret = smu_v13_0_0_get_smu_metrics_data(smu,
961 METRICS_TEMPERATURE_MEM,
962 (uint32_t *)data);
963 *size = 4;
964 break;
965 case AMDGPU_PP_SENSOR_GFX_MCLK:
966 ret = smu_v13_0_0_get_smu_metrics_data(smu,
967 METRICS_CURR_UCLK,
968 (uint32_t *)data);
969 *(uint32_t *)data *= 100;
970 *size = 4;
971 break;
972 case AMDGPU_PP_SENSOR_GFX_SCLK:
973 ret = smu_v13_0_0_get_smu_metrics_data(smu,
974 METRICS_AVERAGE_GFXCLK,
975 (uint32_t *)data);
976 *(uint32_t *)data *= 100;
977 *size = 4;
978 break;
979 case AMDGPU_PP_SENSOR_VDDGFX:
980 ret = smu_v13_0_0_get_smu_metrics_data(smu,
981 METRICS_VOLTAGE_VDDGFX,
982 (uint32_t *)data);
983 *size = 4;
984 break;
985 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
986 default:
987 ret = -EOPNOTSUPP;
988 break;
989 }
990
991 return ret;
992 }
993
smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)994 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
995 enum smu_clk_type clk_type,
996 uint32_t *value)
997 {
998 MetricsMember_t member_type;
999 int clk_id = 0;
1000
1001 clk_id = smu_cmn_to_asic_specific_index(smu,
1002 CMN2ASIC_MAPPING_CLK,
1003 clk_type);
1004 if (clk_id < 0)
1005 return -EINVAL;
1006
1007 switch (clk_id) {
1008 case PPCLK_GFXCLK:
1009 member_type = METRICS_AVERAGE_GFXCLK;
1010 break;
1011 case PPCLK_UCLK:
1012 member_type = METRICS_CURR_UCLK;
1013 break;
1014 case PPCLK_FCLK:
1015 member_type = METRICS_CURR_FCLK;
1016 break;
1017 case PPCLK_SOCCLK:
1018 member_type = METRICS_CURR_SOCCLK;
1019 break;
1020 case PPCLK_VCLK_0:
1021 member_type = METRICS_AVERAGE_VCLK;
1022 break;
1023 case PPCLK_DCLK_0:
1024 member_type = METRICS_AVERAGE_DCLK;
1025 break;
1026 case PPCLK_VCLK_1:
1027 member_type = METRICS_AVERAGE_VCLK1;
1028 break;
1029 case PPCLK_DCLK_1:
1030 member_type = METRICS_AVERAGE_DCLK1;
1031 break;
1032 case PPCLK_DCFCLK:
1033 member_type = METRICS_CURR_DCEFCLK;
1034 break;
1035 default:
1036 return -EINVAL;
1037 }
1038
1039 return smu_v13_0_0_get_smu_metrics_data(smu,
1040 member_type,
1041 value);
1042 }
1043
smu_v13_0_0_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1044 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
1045 int od_feature_bit)
1046 {
1047 PPTable_t *pptable = smu->smu_table.driver_pptable;
1048 const OverDriveLimits_t * const overdrive_upperlimits =
1049 &pptable->SkuTable.OverDriveLimitsBasicMax;
1050 int32_t min_value, max_value;
1051 bool feature_enabled;
1052
1053 switch (od_feature_bit) {
1054 case PP_OD_FEATURE_FAN_CURVE_BIT:
1055 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
1056 if (feature_enabled) {
1057 smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP,
1058 &min_value, &max_value);
1059 if (!min_value && !max_value) {
1060 feature_enabled = false;
1061 goto out;
1062 }
1063
1064 smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM,
1065 &min_value, &max_value);
1066 if (!min_value && !max_value) {
1067 feature_enabled = false;
1068 goto out;
1069 }
1070 }
1071 break;
1072 default:
1073 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
1074 break;
1075 }
1076
1077 out:
1078 return feature_enabled;
1079 }
1080
smu_v13_0_0_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1081 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
1082 int od_feature_bit,
1083 int32_t *min,
1084 int32_t *max)
1085 {
1086 PPTable_t *pptable = smu->smu_table.driver_pptable;
1087 const OverDriveLimits_t * const overdrive_upperlimits =
1088 &pptable->SkuTable.OverDriveLimitsBasicMax;
1089 const OverDriveLimits_t * const overdrive_lowerlimits =
1090 &pptable->SkuTable.OverDriveLimitsMin;
1091 int32_t od_min_setting, od_max_setting;
1092
1093 switch (od_feature_bit) {
1094 case PP_OD_FEATURE_GFXCLK_FMIN:
1095 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1096 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1097 break;
1098 case PP_OD_FEATURE_GFXCLK_FMAX:
1099 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1100 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1101 break;
1102 case PP_OD_FEATURE_UCLK_FMIN:
1103 od_min_setting = overdrive_lowerlimits->UclkFmin;
1104 od_max_setting = overdrive_upperlimits->UclkFmin;
1105 break;
1106 case PP_OD_FEATURE_UCLK_FMAX:
1107 od_min_setting = overdrive_lowerlimits->UclkFmax;
1108 od_max_setting = overdrive_upperlimits->UclkFmax;
1109 break;
1110 case PP_OD_FEATURE_GFX_VF_CURVE:
1111 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1112 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1113 break;
1114 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1115 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1116 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1117 break;
1118 case PP_OD_FEATURE_FAN_CURVE_PWM:
1119 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1120 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1121 break;
1122 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1123 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1124 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1125 break;
1126 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1127 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1128 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1129 break;
1130 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1131 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1132 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1133 break;
1134 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1135 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1136 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1137 break;
1138 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1139 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1140 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1141 break;
1142 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1143 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1144 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1145 break;
1146 default:
1147 od_min_setting = od_max_setting = INT_MAX;
1148 break;
1149 }
1150
1151 if (min)
1152 *min = od_min_setting;
1153 if (max)
1154 *max = od_max_setting;
1155 }
1156
smu_v13_0_0_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1157 static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
1158 OverDriveTableExternal_t *od_table)
1159 {
1160 struct amdgpu_device *adev = smu->adev;
1161
1162 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1163 od_table->OverDriveTable.GfxclkFmax);
1164 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1165 od_table->OverDriveTable.UclkFmax);
1166 }
1167
smu_v13_0_0_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1168 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
1169 OverDriveTableExternal_t *od_table)
1170 {
1171 int ret = 0;
1172
1173 ret = smu_cmn_update_table(smu,
1174 SMU_TABLE_OVERDRIVE,
1175 0,
1176 (void *)od_table,
1177 false);
1178 if (ret)
1179 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1180
1181 return ret;
1182 }
1183
smu_v13_0_0_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1184 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
1185 OverDriveTableExternal_t *od_table)
1186 {
1187 int ret = 0;
1188
1189 ret = smu_cmn_update_table(smu,
1190 SMU_TABLE_OVERDRIVE,
1191 0,
1192 (void *)od_table,
1193 true);
1194 if (ret)
1195 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1196
1197 return ret;
1198 }
1199
smu_v13_0_0_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)1200 static int smu_v13_0_0_emit_clk_levels(struct smu_context *smu,
1201 enum smu_clk_type clk_type, char *buf,
1202 int *offset)
1203 {
1204 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1205 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1206 OverDriveTableExternal_t *od_table =
1207 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1208 int i, curr_freq, size = *offset, start_offset = *offset;
1209 struct smu_dpm_table *single_dpm_table = NULL;
1210 struct smu_pcie_table *pcie_table;
1211 uint32_t gen_speed, lane_width;
1212 int32_t min_value, max_value;
1213 int ret = 0;
1214
1215 if (amdgpu_ras_intr_triggered()) {
1216 sysfs_emit_at(buf, size, "unavailable\n");
1217 return -EBUSY;
1218 }
1219
1220 switch (clk_type) {
1221 case SMU_SCLK:
1222 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1223 break;
1224 case SMU_MCLK:
1225 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1226 break;
1227 case SMU_SOCCLK:
1228 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1229 break;
1230 case SMU_FCLK:
1231 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1232 break;
1233 case SMU_VCLK:
1234 case SMU_VCLK1:
1235 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1236 break;
1237 case SMU_DCLK:
1238 case SMU_DCLK1:
1239 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1240 break;
1241 case SMU_DCEFCLK:
1242 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1243 break;
1244 case SMU_PCIE:
1245 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1246 METRICS_PCIE_RATE,
1247 &gen_speed);
1248 if (ret)
1249 return ret;
1250
1251 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1252 METRICS_PCIE_WIDTH,
1253 &lane_width);
1254 if (ret)
1255 return ret;
1256
1257 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1258 return smu_cmn_print_pcie_levels(smu, pcie_table,
1259 SMU_DPM_PCIE_GEN_IDX(gen_speed),
1260 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
1261 buf, offset);
1262 case SMU_OD_SCLK:
1263 if (!smu_v13_0_0_is_od_feature_supported(smu,
1264 PP_OD_FEATURE_GFXCLK_BIT))
1265 break;
1266
1267 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1268 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1269 od_table->OverDriveTable.GfxclkFmin,
1270 od_table->OverDriveTable.GfxclkFmax);
1271 break;
1272
1273 case SMU_OD_MCLK:
1274 if (!smu_v13_0_0_is_od_feature_supported(smu,
1275 PP_OD_FEATURE_UCLK_BIT))
1276 break;
1277
1278 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1279 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1280 od_table->OverDriveTable.UclkFmin,
1281 od_table->OverDriveTable.UclkFmax);
1282 break;
1283
1284 case SMU_OD_VDDGFX_OFFSET:
1285 if (!smu_v13_0_0_is_od_feature_supported(smu,
1286 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1287 break;
1288
1289 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1290 size += sysfs_emit_at(buf, size, "%dmV\n",
1291 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1292 break;
1293
1294 case SMU_OD_FAN_CURVE:
1295 if (!smu_v13_0_0_is_od_feature_supported(smu,
1296 PP_OD_FEATURE_FAN_CURVE_BIT))
1297 break;
1298
1299 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1300 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1301 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1302 i,
1303 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1304 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1305
1306 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1307 smu_v13_0_0_get_od_setting_limits(smu,
1308 PP_OD_FEATURE_FAN_CURVE_TEMP,
1309 &min_value,
1310 &max_value);
1311 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1312 min_value, max_value);
1313
1314 smu_v13_0_0_get_od_setting_limits(smu,
1315 PP_OD_FEATURE_FAN_CURVE_PWM,
1316 &min_value,
1317 &max_value);
1318 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1319 min_value, max_value);
1320
1321 break;
1322
1323 case SMU_OD_ACOUSTIC_LIMIT:
1324 if (!smu_v13_0_0_is_od_feature_supported(smu,
1325 PP_OD_FEATURE_FAN_CURVE_BIT))
1326 break;
1327
1328 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1329 size += sysfs_emit_at(buf, size, "%d\n",
1330 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1331
1332 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1333 smu_v13_0_0_get_od_setting_limits(smu,
1334 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1335 &min_value,
1336 &max_value);
1337 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1338 min_value, max_value);
1339 break;
1340
1341 case SMU_OD_ACOUSTIC_TARGET:
1342 if (!smu_v13_0_0_is_od_feature_supported(smu,
1343 PP_OD_FEATURE_FAN_CURVE_BIT))
1344 break;
1345
1346 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1347 size += sysfs_emit_at(buf, size, "%d\n",
1348 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1349
1350 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1351 smu_v13_0_0_get_od_setting_limits(smu,
1352 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1353 &min_value,
1354 &max_value);
1355 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1356 min_value, max_value);
1357 break;
1358
1359 case SMU_OD_FAN_TARGET_TEMPERATURE:
1360 if (!smu_v13_0_0_is_od_feature_supported(smu,
1361 PP_OD_FEATURE_FAN_CURVE_BIT))
1362 break;
1363
1364 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1365 size += sysfs_emit_at(buf, size, "%d\n",
1366 (int)od_table->OverDriveTable.FanTargetTemperature);
1367
1368 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1369 smu_v13_0_0_get_od_setting_limits(smu,
1370 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1371 &min_value,
1372 &max_value);
1373 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1374 min_value, max_value);
1375 break;
1376
1377 case SMU_OD_FAN_MINIMUM_PWM:
1378 if (!smu_v13_0_0_is_od_feature_supported(smu,
1379 PP_OD_FEATURE_FAN_CURVE_BIT))
1380 break;
1381
1382 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1383 size += sysfs_emit_at(buf, size, "%d\n",
1384 (int)od_table->OverDriveTable.FanMinimumPwm);
1385
1386 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1387 smu_v13_0_0_get_od_setting_limits(smu,
1388 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1389 &min_value,
1390 &max_value);
1391 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1392 min_value, max_value);
1393 break;
1394
1395 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1396 if (!smu_v13_0_0_is_od_feature_supported(smu,
1397 PP_OD_FEATURE_ZERO_FAN_BIT))
1398 break;
1399
1400 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1401 size += sysfs_emit_at(buf, size, "%d\n",
1402 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1403
1404 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1405 smu_v13_0_0_get_od_setting_limits(smu,
1406 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1407 &min_value,
1408 &max_value);
1409 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1410 min_value, max_value);
1411 break;
1412
1413 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1414 if (!smu_v13_0_0_is_od_feature_supported(smu,
1415 PP_OD_FEATURE_ZERO_FAN_BIT))
1416 break;
1417
1418 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1419 size += sysfs_emit_at(buf, size, "%d\n",
1420 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1421
1422 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1423 smu_v13_0_0_get_od_setting_limits(smu,
1424 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1425 &min_value,
1426 &max_value);
1427 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1428 min_value, max_value);
1429 break;
1430
1431 case SMU_OD_RANGE:
1432 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1433 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1434 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1435 break;
1436
1437 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1438
1439 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1440 smu_v13_0_0_get_od_setting_limits(smu,
1441 PP_OD_FEATURE_GFXCLK_FMIN,
1442 &min_value,
1443 NULL);
1444 smu_v13_0_0_get_od_setting_limits(smu,
1445 PP_OD_FEATURE_GFXCLK_FMAX,
1446 NULL,
1447 &max_value);
1448 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1449 min_value, max_value);
1450 }
1451
1452 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1453 smu_v13_0_0_get_od_setting_limits(smu,
1454 PP_OD_FEATURE_UCLK_FMIN,
1455 &min_value,
1456 NULL);
1457 smu_v13_0_0_get_od_setting_limits(smu,
1458 PP_OD_FEATURE_UCLK_FMAX,
1459 NULL,
1460 &max_value);
1461 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1462 min_value, max_value);
1463 }
1464
1465 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1466 smu_v13_0_0_get_od_setting_limits(smu,
1467 PP_OD_FEATURE_GFX_VF_CURVE,
1468 &min_value,
1469 &max_value);
1470 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1471 min_value, max_value);
1472 }
1473 break;
1474
1475 default:
1476 break;
1477 }
1478
1479 if (single_dpm_table) {
1480 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type,
1481 &curr_freq);
1482 if (ret) {
1483 dev_err(smu->adev->dev,
1484 "Failed to get current clock freq!");
1485 return ret;
1486 }
1487 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
1488 curr_freq, buf, offset);
1489 }
1490
1491 *offset += size - start_offset;
1492
1493 return 0;
1494 }
1495
1496
smu_v13_0_0_od_restore_table_single(struct smu_context * smu,long input)1497 static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input)
1498 {
1499 struct smu_table_context *table_context = &smu->smu_table;
1500 OverDriveTableExternal_t *boot_overdrive_table =
1501 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1502 OverDriveTableExternal_t *od_table =
1503 (OverDriveTableExternal_t *)table_context->overdrive_table;
1504 struct amdgpu_device *adev = smu->adev;
1505 int i;
1506
1507 switch (input) {
1508 case PP_OD_EDIT_FAN_CURVE:
1509 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1510 od_table->OverDriveTable.FanLinearTempPoints[i] =
1511 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1512 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1513 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1514 }
1515 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1516 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1517 break;
1518 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1519 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1520 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1521 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1522 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1523 break;
1524 case PP_OD_EDIT_ACOUSTIC_TARGET:
1525 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1526 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1527 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1528 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1529 break;
1530 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1531 od_table->OverDriveTable.FanTargetTemperature =
1532 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1533 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1534 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1535 break;
1536 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1537 od_table->OverDriveTable.FanMinimumPwm =
1538 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1539 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1540 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1541 break;
1542 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1543 od_table->OverDriveTable.FanZeroRpmEnable =
1544 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1545 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1546 break;
1547 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1548 od_table->OverDriveTable.FanZeroRpmStopTemp =
1549 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1550 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1551 break;
1552 default:
1553 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1554 return -EINVAL;
1555 }
1556
1557 return 0;
1558 }
1559
smu_v13_0_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1560 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
1561 enum PP_OD_DPM_TABLE_COMMAND type,
1562 long input[],
1563 uint32_t size)
1564 {
1565 struct smu_table_context *table_context = &smu->smu_table;
1566 OverDriveTableExternal_t *od_table =
1567 (OverDriveTableExternal_t *)table_context->overdrive_table;
1568 struct amdgpu_device *adev = smu->adev;
1569 uint32_t offset_of_voltageoffset;
1570 int32_t minimum, maximum;
1571 uint32_t feature_ctrlmask;
1572 int i, ret = 0;
1573
1574 switch (type) {
1575 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1576 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1577 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1578 return -ENOTSUPP;
1579 }
1580
1581 for (i = 0; i < size; i += 2) {
1582 if (i + 2 > size) {
1583 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1584 return -EINVAL;
1585 }
1586
1587 switch (input[i]) {
1588 case 0:
1589 smu_v13_0_0_get_od_setting_limits(smu,
1590 PP_OD_FEATURE_GFXCLK_FMIN,
1591 &minimum,
1592 &maximum);
1593 if (input[i + 1] < minimum ||
1594 input[i + 1] > maximum) {
1595 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1596 input[i + 1], minimum, maximum);
1597 return -EINVAL;
1598 }
1599
1600 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1601 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1602 break;
1603
1604 case 1:
1605 smu_v13_0_0_get_od_setting_limits(smu,
1606 PP_OD_FEATURE_GFXCLK_FMAX,
1607 &minimum,
1608 &maximum);
1609 if (input[i + 1] < minimum ||
1610 input[i + 1] > maximum) {
1611 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1612 input[i + 1], minimum, maximum);
1613 return -EINVAL;
1614 }
1615
1616 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1617 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1618 break;
1619
1620 default:
1621 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1622 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1623 return -EINVAL;
1624 }
1625 }
1626
1627 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1628 dev_err(adev->dev,
1629 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1630 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1631 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1632 return -EINVAL;
1633 }
1634 break;
1635
1636 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1637 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1638 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1639 return -ENOTSUPP;
1640 }
1641
1642 for (i = 0; i < size; i += 2) {
1643 if (i + 2 > size) {
1644 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1645 return -EINVAL;
1646 }
1647
1648 switch (input[i]) {
1649 case 0:
1650 smu_v13_0_0_get_od_setting_limits(smu,
1651 PP_OD_FEATURE_UCLK_FMIN,
1652 &minimum,
1653 &maximum);
1654 if (input[i + 1] < minimum ||
1655 input[i + 1] > maximum) {
1656 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1657 input[i + 1], minimum, maximum);
1658 return -EINVAL;
1659 }
1660
1661 od_table->OverDriveTable.UclkFmin = input[i + 1];
1662 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1663 break;
1664
1665 case 1:
1666 smu_v13_0_0_get_od_setting_limits(smu,
1667 PP_OD_FEATURE_UCLK_FMAX,
1668 &minimum,
1669 &maximum);
1670 if (input[i + 1] < minimum ||
1671 input[i + 1] > maximum) {
1672 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1673 input[i + 1], minimum, maximum);
1674 return -EINVAL;
1675 }
1676
1677 od_table->OverDriveTable.UclkFmax = input[i + 1];
1678 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1679 break;
1680
1681 default:
1682 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1683 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1684 return -EINVAL;
1685 }
1686 }
1687
1688 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1689 dev_err(adev->dev,
1690 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1691 (uint32_t)od_table->OverDriveTable.UclkFmin,
1692 (uint32_t)od_table->OverDriveTable.UclkFmax);
1693 return -EINVAL;
1694 }
1695 break;
1696
1697 case PP_OD_EDIT_VDDGFX_OFFSET:
1698 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1699 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1700 return -ENOTSUPP;
1701 }
1702
1703 smu_v13_0_0_get_od_setting_limits(smu,
1704 PP_OD_FEATURE_GFX_VF_CURVE,
1705 &minimum,
1706 &maximum);
1707 if (input[0] < minimum ||
1708 input[0] > maximum) {
1709 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1710 input[0], minimum, maximum);
1711 return -EINVAL;
1712 }
1713
1714 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1715 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1716 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1717 break;
1718
1719 case PP_OD_EDIT_FAN_CURVE:
1720 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1721 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1722 return -ENOTSUPP;
1723 }
1724
1725 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1726 input[0] < 0)
1727 return -EINVAL;
1728
1729 smu_v13_0_0_get_od_setting_limits(smu,
1730 PP_OD_FEATURE_FAN_CURVE_TEMP,
1731 &minimum,
1732 &maximum);
1733 if (input[1] < minimum ||
1734 input[1] > maximum) {
1735 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1736 input[1], minimum, maximum);
1737 return -EINVAL;
1738 }
1739
1740 smu_v13_0_0_get_od_setting_limits(smu,
1741 PP_OD_FEATURE_FAN_CURVE_PWM,
1742 &minimum,
1743 &maximum);
1744 if (input[2] < minimum ||
1745 input[2] > maximum) {
1746 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1747 input[2], minimum, maximum);
1748 return -EINVAL;
1749 }
1750
1751 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1752 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1753 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1754 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1755 break;
1756
1757 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1758 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1759 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1760 return -ENOTSUPP;
1761 }
1762
1763 smu_v13_0_0_get_od_setting_limits(smu,
1764 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1765 &minimum,
1766 &maximum);
1767 if (input[0] < minimum ||
1768 input[0] > maximum) {
1769 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1770 input[0], minimum, maximum);
1771 return -EINVAL;
1772 }
1773
1774 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1775 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1776 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1777 break;
1778
1779 case PP_OD_EDIT_ACOUSTIC_TARGET:
1780 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1781 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1782 return -ENOTSUPP;
1783 }
1784
1785 smu_v13_0_0_get_od_setting_limits(smu,
1786 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1787 &minimum,
1788 &maximum);
1789 if (input[0] < minimum ||
1790 input[0] > maximum) {
1791 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1792 input[0], minimum, maximum);
1793 return -EINVAL;
1794 }
1795
1796 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1797 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1798 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1799 break;
1800
1801 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1802 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1803 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1804 return -ENOTSUPP;
1805 }
1806
1807 smu_v13_0_0_get_od_setting_limits(smu,
1808 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1809 &minimum,
1810 &maximum);
1811 if (input[0] < minimum ||
1812 input[0] > maximum) {
1813 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1814 input[0], minimum, maximum);
1815 return -EINVAL;
1816 }
1817
1818 od_table->OverDriveTable.FanTargetTemperature = input[0];
1819 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1820 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1821 break;
1822
1823 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1824 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1825 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1826 return -ENOTSUPP;
1827 }
1828
1829 smu_v13_0_0_get_od_setting_limits(smu,
1830 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1831 &minimum,
1832 &maximum);
1833 if (input[0] < minimum ||
1834 input[0] > maximum) {
1835 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1836 input[0], minimum, maximum);
1837 return -EINVAL;
1838 }
1839
1840 od_table->OverDriveTable.FanMinimumPwm = input[0];
1841 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1842 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1843 break;
1844
1845 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1846 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1847 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1848 return -ENOTSUPP;
1849 }
1850
1851 smu_v13_0_0_get_od_setting_limits(smu,
1852 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1853 &minimum,
1854 &maximum);
1855 if (input[0] < minimum ||
1856 input[0] > maximum) {
1857 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1858 input[0], minimum, maximum);
1859 return -EINVAL;
1860 }
1861
1862 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1863 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1864 break;
1865
1866 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1867 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1868 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1869 return -ENOTSUPP;
1870 }
1871
1872 smu_v13_0_0_get_od_setting_limits(smu,
1873 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1874 &minimum,
1875 &maximum);
1876 if (input[0] < minimum ||
1877 input[0] > maximum) {
1878 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1879 input[0], minimum, maximum);
1880 return -EINVAL;
1881 }
1882
1883 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1884 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1885 break;
1886
1887 case PP_OD_RESTORE_DEFAULT_TABLE:
1888 if (size == 1) {
1889 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]);
1890 if (ret)
1891 return ret;
1892 } else {
1893 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1894 memcpy(od_table,
1895 table_context->boot_overdrive_table,
1896 sizeof(OverDriveTableExternal_t));
1897 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1898 }
1899 fallthrough;
1900 case PP_OD_COMMIT_DPM_TABLE:
1901 /*
1902 * The member below instructs PMFW the settings focused in
1903 * this single operation.
1904 * `uint32_t FeatureCtrlMask;`
1905 * It does not contain actual informations about user's custom
1906 * settings. Thus we do not cache it.
1907 */
1908 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1909 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1910 table_context->user_overdrive_table + offset_of_voltageoffset,
1911 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1912 smu_v13_0_0_dump_od_table(smu, od_table);
1913
1914 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
1915 if (ret) {
1916 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1917 return ret;
1918 }
1919
1920 od_table->OverDriveTable.FeatureCtrlMask = 0;
1921 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1922 (u8 *)od_table + offset_of_voltageoffset,
1923 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1924
1925 if (!memcmp(table_context->user_overdrive_table,
1926 table_context->boot_overdrive_table,
1927 sizeof(OverDriveTableExternal_t)))
1928 smu->user_dpm_profile.user_od = false;
1929 else
1930 smu->user_dpm_profile.user_od = true;
1931 }
1932 break;
1933
1934 default:
1935 return -ENOSYS;
1936 }
1937
1938 return ret;
1939 }
1940
smu_v13_0_0_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1941 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1942 enum smu_clk_type clk_type,
1943 uint32_t mask)
1944 {
1945 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1946 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1947 struct smu_dpm_table *single_dpm_table;
1948 uint32_t soft_min_level, soft_max_level;
1949 uint32_t min_freq, max_freq;
1950 int ret = 0;
1951
1952 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1953 soft_max_level = mask ? (fls(mask) - 1) : 0;
1954
1955 switch (clk_type) {
1956 case SMU_GFXCLK:
1957 case SMU_SCLK:
1958 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1959 break;
1960 case SMU_MCLK:
1961 case SMU_UCLK:
1962 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1963 break;
1964 case SMU_SOCCLK:
1965 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1966 break;
1967 case SMU_FCLK:
1968 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1969 break;
1970 case SMU_VCLK:
1971 case SMU_VCLK1:
1972 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1973 break;
1974 case SMU_DCLK:
1975 case SMU_DCLK1:
1976 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1977 break;
1978 default:
1979 break;
1980 }
1981
1982 switch (clk_type) {
1983 case SMU_GFXCLK:
1984 case SMU_SCLK:
1985 case SMU_MCLK:
1986 case SMU_UCLK:
1987 case SMU_SOCCLK:
1988 case SMU_FCLK:
1989 case SMU_VCLK:
1990 case SMU_VCLK1:
1991 case SMU_DCLK:
1992 case SMU_DCLK1:
1993 if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) {
1994 /* There is only 2 levels for fine grained DPM */
1995 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1996 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1997 } else {
1998 if ((soft_max_level >= single_dpm_table->count) ||
1999 (soft_min_level >= single_dpm_table->count))
2000 return -EINVAL;
2001 }
2002
2003 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2004 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2005
2006 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2007 clk_type,
2008 min_freq,
2009 max_freq,
2010 false);
2011 break;
2012 case SMU_DCEFCLK:
2013 case SMU_PCIE:
2014 default:
2015 break;
2016 }
2017
2018 return ret;
2019 }
2020
2021 static const struct smu_temperature_range smu13_thermal_policy[] = {
2022 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2023 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2024 };
2025
smu_v13_0_0_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2026 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
2027 struct smu_temperature_range *range)
2028 {
2029 struct smu_table_context *table_context = &smu->smu_table;
2030 struct smu_13_0_0_powerplay_table *powerplay_table =
2031 table_context->power_play_table;
2032 PPTable_t *pptable = smu->smu_table.driver_pptable;
2033
2034 if (amdgpu_sriov_vf(smu->adev))
2035 return 0;
2036
2037 if (!range)
2038 return -EINVAL;
2039
2040 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2041
2042 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2043 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2044 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2045 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2046 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2047 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2048 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2049 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2050 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2051 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2052 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2053 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2054 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2055 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2056
2057 return 0;
2058 }
2059
smu_v13_0_0_get_gpu_metrics(struct smu_context * smu,void ** table)2060 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
2061 void **table)
2062 {
2063 struct gpu_metrics_v1_3 *gpu_metrics =
2064 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr(
2065 smu, SMU_DRIVER_TABLE_GPU_METRICS);
2066 SmuMetricsExternal_t metrics_ext;
2067 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2068 uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
2069 int ret = 0;
2070
2071 ret = smu_cmn_get_metrics_table(smu,
2072 &metrics_ext,
2073 true);
2074 if (ret)
2075 return ret;
2076
2077 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2078
2079 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2080 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2081 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2082 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2083 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2084 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2085 metrics->AvgTemperature[TEMP_VR_MEM1]);
2086
2087 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2088 gpu_metrics->average_umc_activity = smu_safe_u16_nn(metrics->AverageUclkActivity);
2089 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2090 metrics->Vcn1ActivityPercentage);
2091
2092 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2093
2094 if ((mp1_ver == IP_VERSION(13, 0, 0) && smu->smc_fw_version <= 0x004e1e00) ||
2095 (mp1_ver == IP_VERSION(13, 0, 10) && smu->smc_fw_version <= 0x00500800))
2096 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2097 else
2098 gpu_metrics->energy_accumulator = UINT_MAX;
2099
2100 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2101 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2102 else
2103 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2104
2105 if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_0_BUSY_THRESHOLD)
2106 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2107 else
2108 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2109
2110 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2111 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2112 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2113 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2114
2115 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2116 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2117 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2118 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2119 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2120 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2121 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2122
2123 gpu_metrics->throttle_status =
2124 smu_v13_0_get_throttler_status(metrics);
2125 gpu_metrics->indep_throttle_status =
2126 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2127 smu_v13_0_0_throttler_map);
2128
2129 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2130
2131 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2132 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2133 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2134 else
2135 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2136
2137 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2138
2139 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2140 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2141 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2142
2143 *table = (void *)gpu_metrics;
2144
2145 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
2146
2147 return sizeof(struct gpu_metrics_v1_3);
2148 }
2149
smu_v13_0_0_set_supported_od_feature_mask(struct smu_context * smu)2150 static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu)
2151 {
2152 struct amdgpu_device *adev = smu->adev;
2153
2154 if (smu_v13_0_0_is_od_feature_supported(smu,
2155 PP_OD_FEATURE_FAN_CURVE_BIT))
2156 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2157 OD_OPS_SUPPORT_FAN_CURVE_SET |
2158 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2159 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2160 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2161 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2162 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2163 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2164 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2165 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2166 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2167 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2168 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2169 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2170 }
2171
smu_v13_0_0_set_default_od_settings(struct smu_context * smu)2172 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu)
2173 {
2174 OverDriveTableExternal_t *od_table =
2175 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2176 OverDriveTableExternal_t *boot_od_table =
2177 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2178 OverDriveTableExternal_t *user_od_table =
2179 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2180 OverDriveTableExternal_t user_od_table_bak;
2181 int ret = 0;
2182 int i;
2183
2184 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table);
2185 if (ret)
2186 return ret;
2187
2188 smu_v13_0_0_dump_od_table(smu, boot_od_table);
2189
2190 memcpy(od_table,
2191 boot_od_table,
2192 sizeof(OverDriveTableExternal_t));
2193
2194 /*
2195 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2196 * but we have to preserve user defined values in "user_od_table".
2197 */
2198 if (!smu->adev->in_suspend) {
2199 memcpy(user_od_table,
2200 boot_od_table,
2201 sizeof(OverDriveTableExternal_t));
2202 smu->user_dpm_profile.user_od = false;
2203 } else if (smu->user_dpm_profile.user_od) {
2204 memcpy(&user_od_table_bak,
2205 user_od_table,
2206 sizeof(OverDriveTableExternal_t));
2207 memcpy(user_od_table,
2208 boot_od_table,
2209 sizeof(OverDriveTableExternal_t));
2210 user_od_table->OverDriveTable.GfxclkFmin =
2211 user_od_table_bak.OverDriveTable.GfxclkFmin;
2212 user_od_table->OverDriveTable.GfxclkFmax =
2213 user_od_table_bak.OverDriveTable.GfxclkFmax;
2214 user_od_table->OverDriveTable.UclkFmin =
2215 user_od_table_bak.OverDriveTable.UclkFmin;
2216 user_od_table->OverDriveTable.UclkFmax =
2217 user_od_table_bak.OverDriveTable.UclkFmax;
2218 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2219 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2220 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2221 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2222 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2223 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2224 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2225 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2226 }
2227 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2228 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2229 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2230 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2231 user_od_table->OverDriveTable.FanTargetTemperature =
2232 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2233 user_od_table->OverDriveTable.FanMinimumPwm =
2234 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2235 user_od_table->OverDriveTable.FanZeroRpmEnable =
2236 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2237 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2238 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2239 }
2240
2241 smu_v13_0_0_set_supported_od_feature_mask(smu);
2242
2243 return 0;
2244 }
2245
smu_v13_0_0_restore_user_od_settings(struct smu_context * smu)2246 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu)
2247 {
2248 struct smu_table_context *table_context = &smu->smu_table;
2249 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2250 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2251 int res;
2252
2253 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2254 BIT(PP_OD_FEATURE_UCLK_BIT) |
2255 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2256 BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
2257 BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
2258 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table);
2259 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2260 if (res == 0)
2261 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2262
2263 return res;
2264 }
2265
smu_v13_0_0_populate_umd_state_clk(struct smu_context * smu)2266 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
2267 {
2268 struct smu_13_0_dpm_context *dpm_context =
2269 smu->smu_dpm.dpm_context;
2270 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
2271 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
2272 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
2273 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
2274 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
2275 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
2276 struct smu_umd_pstate_table *pstate_table =
2277 &smu->pstate_table;
2278 struct smu_table_context *table_context = &smu->smu_table;
2279 PPTable_t *pptable = table_context->driver_pptable;
2280 DriverReportedClocks_t driver_clocks =
2281 pptable->SkuTable.DriverReportedClocks;
2282
2283 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
2284 if (driver_clocks.GameClockAc &&
2285 (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table)))
2286 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2287 else
2288 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
2289
2290 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
2291 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
2292
2293 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
2294 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
2295
2296 pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table);
2297 pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table);
2298
2299 pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table);
2300 pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table);
2301
2302 pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table);
2303 pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table);
2304
2305 if (driver_clocks.BaseClockAc &&
2306 driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table))
2307 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2308 else
2309 pstate_table->gfxclk_pstate.standard =
2310 SMU_DPM_TABLE_MAX(gfx_table);
2311 pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table);
2312 pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table);
2313 pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table);
2314 pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table);
2315 pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table);
2316
2317 return 0;
2318 }
2319
smu_v13_0_0_get_unique_id(struct smu_context * smu)2320 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
2321 {
2322 struct smu_table_context *smu_table = &smu->smu_table;
2323 SmuMetrics_t *metrics =
2324 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
2325 struct amdgpu_device *adev = smu->adev;
2326 uint32_t upper32 = 0, lower32 = 0;
2327 int ret;
2328
2329 ret = smu_cmn_get_metrics_table(smu, NULL, false);
2330 if (ret)
2331 goto out;
2332
2333 upper32 = metrics->PublicSerialNumberUpper;
2334 lower32 = metrics->PublicSerialNumberLower;
2335
2336 out:
2337 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2338 }
2339
smu_v13_0_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2340 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
2341 uint32_t *speed)
2342 {
2343 int ret;
2344
2345 if (!speed)
2346 return -EINVAL;
2347
2348 ret = smu_v13_0_0_get_smu_metrics_data(smu,
2349 METRICS_CURR_FANPWM,
2350 speed);
2351 if (ret) {
2352 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2353 return ret;
2354 }
2355
2356 /* Convert the PMFW output which is in percent to pwm(255) based */
2357 *speed = min(*speed * 255 / 100, (uint32_t)255);
2358
2359 return 0;
2360 }
2361
smu_v13_0_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2362 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
2363 uint32_t *speed)
2364 {
2365 if (!speed)
2366 return -EINVAL;
2367
2368 return smu_v13_0_0_get_smu_metrics_data(smu,
2369 METRICS_CURR_FANSPEED,
2370 speed);
2371 }
2372
smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context * smu)2373 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
2374 {
2375 struct smu_table_context *table_context = &smu->smu_table;
2376 PPTable_t *pptable = table_context->driver_pptable;
2377 SkuTable_t *skutable = &pptable->SkuTable;
2378
2379 /*
2380 * Skip the MGpuFanBoost setting for those ASICs
2381 * which do not support it
2382 */
2383 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2384 return 0;
2385
2386 return smu_cmn_send_smc_msg_with_param(smu,
2387 SMU_MSG_SetMGpuFanBoostLimitRpm,
2388 0,
2389 NULL);
2390 }
2391
smu_v13_0_0_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2392 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
2393 uint32_t *current_power_limit,
2394 uint32_t *default_power_limit,
2395 uint32_t *max_power_limit,
2396 uint32_t *min_power_limit)
2397 {
2398 struct smu_table_context *table_context = &smu->smu_table;
2399 struct smu_13_0_0_powerplay_table *powerplay_table =
2400 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
2401 PPTable_t *pptable = table_context->driver_pptable;
2402 SkuTable_t *skutable = &pptable->SkuTable;
2403 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2404 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2405
2406 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2407 power_limit = smu->adev->pm.ac_power ?
2408 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2409 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2410
2411 if (current_power_limit)
2412 *current_power_limit = power_limit;
2413 if (default_power_limit)
2414 *default_power_limit = power_limit;
2415
2416 if (powerplay_table) {
2417 if (smu->od_enabled &&
2418 smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2419 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2420 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2421 } else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2422 od_percent_upper = 0;
2423 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2424 }
2425 }
2426
2427 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2428 od_percent_upper, od_percent_lower, power_limit);
2429
2430 if (max_power_limit) {
2431 *max_power_limit = msg_limit * (100 + od_percent_upper);
2432 *max_power_limit /= 100;
2433 }
2434
2435 if (min_power_limit) {
2436 *min_power_limit = power_limit * (100 - od_percent_lower);
2437 *min_power_limit /= 100;
2438 }
2439
2440 return 0;
2441 }
2442
smu_v13_0_0_get_power_profile_mode(struct smu_context * smu,char * buf)2443 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
2444 char *buf)
2445 {
2446 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2447 DpmActivityMonitorCoeffInt_t *activity_monitor =
2448 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2449 static const char *title[] = {
2450 "PROFILE_INDEX(NAME)",
2451 "CLOCK_TYPE(NAME)",
2452 "FPS",
2453 "MinActiveFreqType",
2454 "MinActiveFreq",
2455 "BoosterFreqType",
2456 "BoosterFreq",
2457 "PD_Data_limit_c",
2458 "PD_Data_error_coeff",
2459 "PD_Data_error_rate_coeff"};
2460 int16_t workload_type = 0;
2461 uint32_t i, size = 0;
2462 int result = 0;
2463
2464 if (!buf)
2465 return -EINVAL;
2466
2467 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
2468 title[0], title[1], title[2], title[3], title[4], title[5],
2469 title[6], title[7], title[8], title[9]);
2470
2471 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2472 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2473 workload_type = smu_cmn_to_asic_specific_index(smu,
2474 CMN2ASIC_MAPPING_WORKLOAD,
2475 i);
2476 if (workload_type == -ENOTSUPP)
2477 continue;
2478 else if (workload_type < 0)
2479 return -EINVAL;
2480
2481 result = smu_cmn_update_table(smu,
2482 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2483 workload_type,
2484 (void *)(&activity_monitor_external),
2485 false);
2486 if (result) {
2487 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2488 return result;
2489 }
2490
2491 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
2492 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
2493
2494 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2495 " ",
2496 0,
2497 "GFXCLK",
2498 activity_monitor->Gfx_FPS,
2499 activity_monitor->Gfx_MinActiveFreqType,
2500 activity_monitor->Gfx_MinActiveFreq,
2501 activity_monitor->Gfx_BoosterFreqType,
2502 activity_monitor->Gfx_BoosterFreq,
2503 activity_monitor->Gfx_PD_Data_limit_c,
2504 activity_monitor->Gfx_PD_Data_error_coeff,
2505 activity_monitor->Gfx_PD_Data_error_rate_coeff);
2506
2507 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2508 " ",
2509 1,
2510 "FCLK",
2511 activity_monitor->Fclk_FPS,
2512 activity_monitor->Fclk_MinActiveFreqType,
2513 activity_monitor->Fclk_MinActiveFreq,
2514 activity_monitor->Fclk_BoosterFreqType,
2515 activity_monitor->Fclk_BoosterFreq,
2516 activity_monitor->Fclk_PD_Data_limit_c,
2517 activity_monitor->Fclk_PD_Data_error_coeff,
2518 activity_monitor->Fclk_PD_Data_error_rate_coeff);
2519 }
2520
2521 return size;
2522 }
2523
2524 #define SMU_13_0_0_CUSTOM_PARAMS_COUNT 9
2525 #define SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT 2
2526 #define SMU_13_0_0_CUSTOM_PARAMS_SIZE (SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_0_CUSTOM_PARAMS_COUNT * sizeof(long))
2527
smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2528 static int smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context *smu,
2529 long *input)
2530 {
2531 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2532 DpmActivityMonitorCoeffInt_t *activity_monitor =
2533 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2534 int ret, idx;
2535
2536 ret = smu_cmn_update_table(smu,
2537 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2538 WORKLOAD_PPLIB_CUSTOM_BIT,
2539 (void *)(&activity_monitor_external),
2540 false);
2541 if (ret) {
2542 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2543 return ret;
2544 }
2545
2546 idx = 0 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2547 if (input[idx]) {
2548 /* Gfxclk */
2549 activity_monitor->Gfx_FPS = input[idx + 1];
2550 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2];
2551 activity_monitor->Gfx_MinActiveFreq = input[idx + 3];
2552 activity_monitor->Gfx_BoosterFreqType = input[idx + 4];
2553 activity_monitor->Gfx_BoosterFreq = input[idx + 5];
2554 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6];
2555 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7];
2556 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8];
2557 }
2558 idx = 1 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2559 if (input[idx]) {
2560 /* Fclk */
2561 activity_monitor->Fclk_FPS = input[idx + 1];
2562 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2];
2563 activity_monitor->Fclk_MinActiveFreq = input[idx + 3];
2564 activity_monitor->Fclk_BoosterFreqType = input[idx + 4];
2565 activity_monitor->Fclk_BoosterFreq = input[idx + 5];
2566 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6];
2567 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7];
2568 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8];
2569 }
2570
2571 ret = smu_cmn_update_table(smu,
2572 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2573 WORKLOAD_PPLIB_CUSTOM_BIT,
2574 (void *)(&activity_monitor_external),
2575 true);
2576 if (ret) {
2577 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2578 return ret;
2579 }
2580
2581 return ret;
2582 }
2583
smu_v13_0_0_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2584 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
2585 u32 workload_mask,
2586 long *custom_params,
2587 u32 custom_params_max_idx)
2588 {
2589 u32 backend_workload_mask = 0;
2590 int workload_type, ret, idx = -1, i;
2591
2592 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2593 &backend_workload_mask);
2594
2595 /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
2596 if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) &&
2597 ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2598 ((smu->adev->pm.fw_version == 0x004e6601) ||
2599 (smu->adev->pm.fw_version >= 0x004e7300))) ||
2600 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2601 smu->adev->pm.fw_version >= 0x00504500))) {
2602 workload_type = smu_cmn_to_asic_specific_index(smu,
2603 CMN2ASIC_MAPPING_WORKLOAD,
2604 PP_SMC_POWER_PROFILE_POWERSAVING);
2605 if (workload_type >= 0)
2606 backend_workload_mask |= 1 << workload_type;
2607 }
2608
2609 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2610 if (!smu->custom_profile_params) {
2611 smu->custom_profile_params =
2612 kzalloc(SMU_13_0_0_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2613 if (!smu->custom_profile_params)
2614 return -ENOMEM;
2615 }
2616 if (custom_params && custom_params_max_idx) {
2617 if (custom_params_max_idx != SMU_13_0_0_CUSTOM_PARAMS_COUNT)
2618 return -EINVAL;
2619 if (custom_params[0] >= SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT)
2620 return -EINVAL;
2621 idx = custom_params[0] * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2622 smu->custom_profile_params[idx] = 1;
2623 for (i = 1; i < custom_params_max_idx; i++)
2624 smu->custom_profile_params[idx + i] = custom_params[i];
2625 }
2626 ret = smu_v13_0_0_set_power_profile_mode_coeff(smu,
2627 smu->custom_profile_params);
2628 if (ret) {
2629 if (idx != -1)
2630 smu->custom_profile_params[idx] = 0;
2631 return ret;
2632 }
2633 } else if (smu->custom_profile_params) {
2634 memset(smu->custom_profile_params, 0, SMU_13_0_0_CUSTOM_PARAMS_SIZE);
2635 }
2636
2637 ret = smu_cmn_send_smc_msg_with_param(smu,
2638 SMU_MSG_SetWorkloadMask,
2639 backend_workload_mask,
2640 NULL);
2641 if (ret) {
2642 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2643 workload_mask);
2644 if (idx != -1)
2645 smu->custom_profile_params[idx] = 0;
2646 return ret;
2647 }
2648
2649 return ret;
2650 }
2651
smu_v13_0_0_is_mode1_reset_supported(struct smu_context * smu)2652 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
2653 {
2654 struct amdgpu_device *adev = smu->adev;
2655
2656 /* SRIOV does not support SMU mode1 reset */
2657 if (amdgpu_sriov_vf(adev))
2658 return false;
2659
2660 return true;
2661 }
2662
smu_v13_0_0_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2663 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
2664 struct i2c_msg *msg, int num_msgs)
2665 {
2666 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2667 struct amdgpu_device *adev = smu_i2c->adev;
2668 struct smu_context *smu = adev->powerplay.pp_handle;
2669 struct smu_table_context *smu_table = &smu->smu_table;
2670 struct smu_table *table = &smu_table->driver_table;
2671 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2672 int i, j, r, c;
2673 u16 dir;
2674
2675 if (!adev->pm.dpm_enabled)
2676 return -EBUSY;
2677
2678 req = kzalloc_obj(*req);
2679 if (!req)
2680 return -ENOMEM;
2681
2682 req->I2CcontrollerPort = smu_i2c->port;
2683 req->I2CSpeed = I2C_SPEED_FAST_400K;
2684 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2685 dir = msg[0].flags & I2C_M_RD;
2686
2687 for (c = i = 0; i < num_msgs; i++) {
2688 for (j = 0; j < msg[i].len; j++, c++) {
2689 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2690
2691 if (!(msg[i].flags & I2C_M_RD)) {
2692 /* write */
2693 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2694 cmd->ReadWriteData = msg[i].buf[j];
2695 }
2696
2697 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2698 /* The direction changes.
2699 */
2700 dir = msg[i].flags & I2C_M_RD;
2701 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2702 }
2703
2704 req->NumCmds++;
2705
2706 /*
2707 * Insert STOP if we are at the last byte of either last
2708 * message for the transaction or the client explicitly
2709 * requires a STOP at this particular message.
2710 */
2711 if ((j == msg[i].len - 1) &&
2712 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2713 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2714 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2715 }
2716 }
2717 }
2718 mutex_lock(&adev->pm.mutex);
2719 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2720 if (r)
2721 goto fail;
2722
2723 for (c = i = 0; i < num_msgs; i++) {
2724 if (!(msg[i].flags & I2C_M_RD)) {
2725 c += msg[i].len;
2726 continue;
2727 }
2728 for (j = 0; j < msg[i].len; j++, c++) {
2729 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2730
2731 msg[i].buf[j] = cmd->ReadWriteData;
2732 }
2733 }
2734 r = num_msgs;
2735 fail:
2736 mutex_unlock(&adev->pm.mutex);
2737 kfree(req);
2738 return r;
2739 }
2740
smu_v13_0_0_i2c_func(struct i2c_adapter * adap)2741 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
2742 {
2743 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2744 }
2745
2746 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
2747 .master_xfer = smu_v13_0_0_i2c_xfer,
2748 .functionality = smu_v13_0_0_i2c_func,
2749 };
2750
2751 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
2752 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2753 .max_read_len = MAX_SW_I2C_COMMANDS,
2754 .max_write_len = MAX_SW_I2C_COMMANDS,
2755 .max_comb_1st_msg_len = 2,
2756 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2757 };
2758
smu_v13_0_0_i2c_control_init(struct smu_context * smu)2759 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
2760 {
2761 struct amdgpu_device *adev = smu->adev;
2762 int res, i;
2763
2764 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2765 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2766 struct i2c_adapter *control = &smu_i2c->adapter;
2767
2768 smu_i2c->adev = adev;
2769 smu_i2c->port = i;
2770 mutex_init(&smu_i2c->mutex);
2771 control->owner = THIS_MODULE;
2772 control->dev.parent = &adev->pdev->dev;
2773 control->algo = &smu_v13_0_0_i2c_algo;
2774 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2775 control->quirks = &smu_v13_0_0_i2c_control_quirks;
2776 i2c_set_adapdata(control, smu_i2c);
2777
2778 res = devm_i2c_add_adapter(adev->dev, control);
2779 if (res) {
2780 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2781 return res;
2782 }
2783 }
2784
2785 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2786 /* XXX ideally this would be something in a vbios data table */
2787 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2788 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2789
2790 return 0;
2791 }
2792
smu_v13_0_0_i2c_control_fini(struct smu_context * smu)2793 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
2794 {
2795 struct amdgpu_device *adev = smu->adev;
2796
2797 adev->pm.ras_eeprom_i2c_bus = NULL;
2798 adev->pm.fru_eeprom_i2c_bus = NULL;
2799 }
2800
smu_v13_0_0_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2801 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
2802 enum pp_mp1_state mp1_state)
2803 {
2804 int ret;
2805
2806 switch (mp1_state) {
2807 case PP_MP1_STATE_UNLOAD:
2808 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2809 break;
2810 default:
2811 /* Ignore others */
2812 ret = 0;
2813 }
2814
2815 return ret;
2816 }
2817
smu_v13_0_0_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2818 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
2819 enum pp_df_cstate state)
2820 {
2821 return smu_cmn_send_smc_msg_with_param(smu,
2822 SMU_MSG_DFCstateControl,
2823 state,
2824 NULL);
2825 }
2826
smu_v13_0_0_set_mode1_reset_param(struct smu_context * smu,uint32_t supported_version,uint32_t * param)2827 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu,
2828 uint32_t supported_version,
2829 uint32_t *param)
2830 {
2831 struct amdgpu_device *adev = smu->adev;
2832
2833 if ((smu->smc_fw_version >= supported_version) &&
2834 amdgpu_ras_get_fed_status(adev))
2835 /* Set RAS fatal error reset flag */
2836 *param = 1 << 16;
2837 else
2838 *param = 0;
2839 }
2840
smu_v13_0_0_mode1_reset(struct smu_context * smu)2841 static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
2842 {
2843 int ret;
2844 uint32_t param;
2845 struct amdgpu_device *adev = smu->adev;
2846
2847 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2848 case IP_VERSION(13, 0, 0):
2849 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */
2850 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m);
2851
2852 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2853 DEBUGSMC_MSG_Mode1Reset, param);
2854
2855 break;
2856
2857 case IP_VERSION(13, 0, 10):
2858 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */
2859 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m);
2860
2861 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2862 DEBUGSMC_MSG_Mode1Reset, param);
2863 break;
2864
2865 default:
2866 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2867 break;
2868 }
2869
2870 if (!ret) {
2871 /* disable mmio access while doing mode 1 reset*/
2872 smu->adev->no_hw_access = true;
2873 /* ensure no_hw_access is globally visible before any MMIO */
2874 smp_mb();
2875 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2876 }
2877
2878 return ret;
2879 }
2880
smu_v13_0_0_mode2_reset(struct smu_context * smu)2881 static int smu_v13_0_0_mode2_reset(struct smu_context *smu)
2882 {
2883 int ret;
2884 struct amdgpu_device *adev = smu->adev;
2885
2886 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2887 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL);
2888 else
2889 return -EOPNOTSUPP;
2890
2891 return ret;
2892 }
2893
smu_v13_0_0_enable_gfx_features(struct smu_context * smu)2894 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu)
2895 {
2896 struct amdgpu_device *adev = smu->adev;
2897
2898 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2899 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2900 FEATURE_PWR_GFX, NULL);
2901 else
2902 return -EOPNOTSUPP;
2903 }
2904
smu_v13_0_0_init_msg_ctl(struct smu_context * smu)2905 static void smu_v13_0_0_init_msg_ctl(struct smu_context *smu)
2906 {
2907 struct amdgpu_device *adev = smu->adev;
2908 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2909
2910 smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map);
2911
2912 /* Set up debug mailbox registers */
2913 ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2914 ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2915 ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2916 ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;
2917 }
2918
smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context * smu,uint32_t size)2919 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
2920 uint32_t size)
2921 {
2922 int ret = 0;
2923
2924 /* message SMU to update the bad page number on SMUBUS */
2925 ret = smu_cmn_send_smc_msg_with_param(smu,
2926 SMU_MSG_SetNumBadMemoryPagesRetired,
2927 size, NULL);
2928 if (ret)
2929 dev_err(smu->adev->dev,
2930 "[%s] failed to message SMU to update bad memory pages number\n",
2931 __func__);
2932
2933 return ret;
2934 }
2935
smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context * smu,uint32_t size)2936 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
2937 uint32_t size)
2938 {
2939 int ret = 0;
2940
2941 /* message SMU to update the bad channel info on SMUBUS */
2942 ret = smu_cmn_send_smc_msg_with_param(smu,
2943 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
2944 size, NULL);
2945 if (ret)
2946 dev_err(smu->adev->dev,
2947 "[%s] failed to message SMU to update bad memory pages channel info\n",
2948 __func__);
2949
2950 return ret;
2951 }
2952
smu_v13_0_0_check_ecc_table_support(struct smu_context * smu)2953 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu)
2954 {
2955 struct amdgpu_device *adev = smu->adev;
2956 int ret = 0;
2957
2958 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) &&
2959 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION))
2960 return ret;
2961 else
2962 return -EOPNOTSUPP;
2963 }
2964
smu_v13_0_0_get_ecc_info(struct smu_context * smu,void * table)2965 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,
2966 void *table)
2967 {
2968 struct smu_table_context *smu_table = &smu->smu_table;
2969 struct amdgpu_device *adev = smu->adev;
2970 EccInfoTable_t *ecc_table = NULL;
2971 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
2972 int i, ret = 0;
2973 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
2974
2975 ret = smu_v13_0_0_check_ecc_table_support(smu);
2976 if (ret)
2977 return ret;
2978
2979 ret = smu_cmn_update_table(smu,
2980 SMU_TABLE_ECCINFO,
2981 0,
2982 smu_table->ecc_table,
2983 false);
2984 if (ret) {
2985 dev_info(adev->dev, "Failed to export SMU ecc table!\n");
2986 return ret;
2987 }
2988
2989 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
2990
2991 for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
2992 ecc_info_per_channel = &(eccinfo->ecc[i]);
2993 ecc_info_per_channel->ce_count_lo_chip =
2994 ecc_table->EccInfo[i].ce_count_lo_chip;
2995 ecc_info_per_channel->ce_count_hi_chip =
2996 ecc_table->EccInfo[i].ce_count_hi_chip;
2997 ecc_info_per_channel->mca_umc_status =
2998 ecc_table->EccInfo[i].mca_umc_status;
2999 ecc_info_per_channel->mca_umc_addr =
3000 ecc_table->EccInfo[i].mca_umc_addr;
3001 }
3002
3003 return ret;
3004 }
3005
smu_v13_0_0_wbrf_support_check(struct smu_context * smu)3006 static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)
3007 {
3008 struct amdgpu_device *adev = smu->adev;
3009
3010 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3011 case IP_VERSION(13, 0, 0):
3012 return smu->smc_fw_version >= 0x004e6300;
3013 case IP_VERSION(13, 0, 10):
3014 return smu->smc_fw_version >= 0x00503300;
3015 default:
3016 return false;
3017 }
3018 }
3019
smu_v13_0_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)3020 static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
3021 enum smu_ppt_limit_type limit_type,
3022 uint32_t limit)
3023 {
3024 PPTable_t *pptable = smu->smu_table.driver_pptable;
3025 SkuTable_t *skutable = &pptable->SkuTable;
3026 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
3027 struct smu_table_context *table_context = &smu->smu_table;
3028 OverDriveTableExternal_t *od_table =
3029 (OverDriveTableExternal_t *)table_context->overdrive_table;
3030 int ret = 0;
3031
3032 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
3033 return -EINVAL;
3034
3035 if (limit <= msg_limit) {
3036 if (smu->current_power_limit > msg_limit) {
3037 od_table->OverDriveTable.Ppt = 0;
3038 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3039
3040 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3041 if (ret) {
3042 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3043 return ret;
3044 }
3045 }
3046 return smu_v13_0_set_power_limit(smu, limit_type, limit);
3047 } else if (smu->od_enabled) {
3048 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
3049 if (ret)
3050 return ret;
3051
3052 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
3053 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3054
3055 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3056 if (ret) {
3057 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3058 return ret;
3059 }
3060
3061 smu->current_power_limit = limit;
3062 } else {
3063 return -EINVAL;
3064 }
3065
3066 return 0;
3067 }
3068
smu_v13_0_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)3069 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
3070 uint8_t pcie_gen_cap,
3071 uint8_t pcie_width_cap)
3072 {
3073 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
3074 struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
3075 int num_of_levels;
3076 uint32_t smu_pcie_arg;
3077 uint32_t link_level;
3078 struct smu_table_context *table_context = &smu->smu_table;
3079 PPTable_t *pptable = table_context->driver_pptable;
3080 SkuTable_t *skutable = &pptable->SkuTable;
3081 int ret = 0;
3082 int i;
3083
3084 pcie_table->lclk_levels = 0;
3085
3086 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
3087 if (!skutable->PcieGenSpeed[link_level] &&
3088 !skutable->PcieLaneCount[link_level] &&
3089 !skutable->LclkFreq[link_level])
3090 continue;
3091
3092 pcie_table->pcie_gen[pcie_table->lclk_levels] =
3093 skutable->PcieGenSpeed[link_level];
3094 pcie_table->pcie_lane[pcie_table->lclk_levels] =
3095 skutable->PcieLaneCount[link_level];
3096 pcie_table->lclk_freq[pcie_table->lclk_levels] =
3097 skutable->LclkFreq[link_level];
3098 pcie_table->lclk_levels++;
3099 }
3100
3101 num_of_levels = pcie_table->lclk_levels;
3102 if (!num_of_levels)
3103 return 0;
3104
3105 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
3106 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
3107 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
3108
3109 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
3110 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
3111
3112 /* Force all levels to use the same settings */
3113 for (i = 0; i < num_of_levels; i++) {
3114 pcie_table->pcie_gen[i] = pcie_gen_cap;
3115 pcie_table->pcie_lane[i] = pcie_width_cap;
3116 smu_pcie_arg = i << 16;
3117 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
3118 smu_pcie_arg |= pcie_table->pcie_lane[i];
3119
3120 ret = smu_cmn_send_smc_msg_with_param(smu,
3121 SMU_MSG_OverridePcieParameters,
3122 smu_pcie_arg,
3123 NULL);
3124 if (ret)
3125 break;
3126 }
3127 } else {
3128 for (i = 0; i < num_of_levels; i++) {
3129 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
3130 pcie_table->pcie_lane[i] > pcie_width_cap) {
3131 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ?
3132 pcie_gen_cap : pcie_table->pcie_gen[i];
3133 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ?
3134 pcie_width_cap : pcie_table->pcie_lane[i];
3135 smu_pcie_arg = i << 16;
3136 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
3137 smu_pcie_arg |= pcie_table->pcie_lane[i];
3138
3139 ret = smu_cmn_send_smc_msg_with_param(smu,
3140 SMU_MSG_OverridePcieParameters,
3141 smu_pcie_arg,
3142 NULL);
3143 if (ret)
3144 break;
3145 }
3146 }
3147 }
3148
3149 return ret;
3150 }
3151
3152 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
3153 .init_allowed_features = smu_v13_0_0_init_allowed_features,
3154 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
3155 .i2c_init = smu_v13_0_0_i2c_control_init,
3156 .i2c_fini = smu_v13_0_0_i2c_control_fini,
3157 .is_dpm_running = smu_v13_0_0_is_dpm_running,
3158 .init_microcode = smu_v13_0_init_microcode,
3159 .load_microcode = smu_v13_0_load_microcode,
3160 .fini_microcode = smu_v13_0_fini_microcode,
3161 .init_smc_tables = smu_v13_0_0_init_smc_tables,
3162 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3163 .init_power = smu_v13_0_init_power,
3164 .fini_power = smu_v13_0_fini_power,
3165 .check_fw_status = smu_v13_0_check_fw_status,
3166 .setup_pptable = smu_v13_0_0_setup_pptable,
3167 .check_fw_version = smu_cmn_check_fw_version,
3168 .write_pptable = smu_cmn_write_pptable,
3169 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3170 .system_features_control = smu_v13_0_0_system_features_control,
3171 .set_allowed_mask = smu_v13_0_set_allowed_mask,
3172 .get_enabled_mask = smu_cmn_get_enabled_mask,
3173 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
3174 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
3175 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
3176 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
3177 .read_sensor = smu_v13_0_0_read_sensor,
3178 .feature_is_enabled = smu_cmn_feature_is_enabled,
3179 .emit_clk_levels = smu_v13_0_0_emit_clk_levels,
3180 .force_clk_levels = smu_v13_0_0_force_clk_levels,
3181 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
3182 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
3183 .register_irq_handler = smu_v13_0_register_irq_handler,
3184 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3185 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3186 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3187 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
3188 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
3189 .set_default_od_settings = smu_v13_0_0_set_default_od_settings,
3190 .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings,
3191 .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table,
3192 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
3193 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
3194 .set_performance_level = smu_v13_0_set_performance_level,
3195 .gfx_off_control = smu_v13_0_gfx_off_control,
3196 .get_unique_id = smu_v13_0_0_get_unique_id,
3197 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
3198 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
3199 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
3200 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
3201 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
3202 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
3203 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
3204 .get_power_limit = smu_v13_0_0_get_power_limit,
3205 .set_power_limit = smu_v13_0_0_set_power_limit,
3206 .set_power_source = smu_v13_0_set_power_source,
3207 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
3208 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
3209 .run_btc = smu_v13_0_run_btc,
3210 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3211 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3212 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3213 .deep_sleep_control = smu_v13_0_deep_sleep_control,
3214 .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
3215 .get_bamaco_support = smu_v13_0_get_bamaco_support,
3216 .baco_enter = smu_v13_0_baco_enter,
3217 .baco_exit = smu_v13_0_baco_exit,
3218 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
3219 .mode1_reset = smu_v13_0_0_mode1_reset,
3220 .mode2_reset = smu_v13_0_0_mode2_reset,
3221 .enable_gfx_features = smu_v13_0_0_enable_gfx_features,
3222 .set_mp1_state = smu_v13_0_0_set_mp1_state,
3223 .set_df_cstate = smu_v13_0_0_set_df_cstate,
3224 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num,
3225 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag,
3226 .gpo_control = smu_v13_0_gpo_control,
3227 .get_ecc_info = smu_v13_0_0_get_ecc_info,
3228 .notify_display_change = smu_v13_0_notify_display_change,
3229 .is_asic_wbrf_supported = smu_v13_0_0_wbrf_support_check,
3230 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
3231 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
3232 .interrupt_work = smu_v13_0_interrupt_work,
3233 };
3234
smu_v13_0_0_set_ppt_funcs(struct smu_context * smu)3235 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
3236 {
3237 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
3238 smu->clock_map = smu_v13_0_0_clk_map;
3239 smu->feature_map = smu_v13_0_0_feature_mask_map;
3240 smu->table_map = smu_v13_0_0_table_map;
3241 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
3242 smu->workload_map = smu_v13_0_0_workload_map;
3243 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;
3244 smu_v13_0_0_init_msg_ctl(smu);
3245
3246 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3247 IP_VERSION(13, 0, 10) &&
3248 !amdgpu_device_has_display_hardware(smu->adev))
3249 smu->adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3250 }
3251