1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27 #include <linux/power_supply.h>
28 #include <linux/reboot.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
33 #include "atom.h"
34 #include "arcturus_ppt.h"
35 #include "navi10_ppt.h"
36 #include "sienna_cichlid_ppt.h"
37 #include "renoir_ppt.h"
38 #include "vangogh_ppt.h"
39 #include "aldebaran_ppt.h"
40 #include "yellow_carp_ppt.h"
41 #include "cyan_skillfish_ppt.h"
42 #include "smu_v13_0_0_ppt.h"
43 #include "smu_v13_0_4_ppt.h"
44 #include "smu_v13_0_5_ppt.h"
45 #include "smu_v13_0_6_ppt.h"
46 #include "smu_v13_0_7_ppt.h"
47 #include "smu_v14_0_0_ppt.h"
48 #include "smu_v14_0_2_ppt.h"
49 #include "amd_pcie.h"
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 static const struct amd_pm_funcs swsmu_pm_funcs;
62 static int smu_force_smuclk_levels(struct smu_context *smu,
63 enum smu_clk_type clk_type,
64 uint32_t mask);
65 static int smu_handle_task(struct smu_context *smu,
66 enum amd_dpm_forced_level level,
67 enum amd_pp_task task_id);
68 static int smu_reset(struct smu_context *smu);
69 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
70 static int smu_set_fan_control_mode(void *handle, u32 value);
71 static int smu_set_power_limit(void *handle, uint32_t limit);
72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
75 static void smu_power_profile_mode_get(struct smu_context *smu,
76 enum PP_SMC_POWER_PROFILE profile_mode);
77 static void smu_power_profile_mode_put(struct smu_context *smu,
78 enum PP_SMC_POWER_PROFILE profile_mode);
79 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type);
80 static int smu_od_edit_dpm_table(void *handle,
81 enum PP_OD_DPM_TABLE_COMMAND type,
82 long *input, uint32_t size);
83
smu_sys_get_pp_feature_mask(void * handle,char * buf)84 static int smu_sys_get_pp_feature_mask(void *handle,
85 char *buf)
86 {
87 struct smu_context *smu = handle;
88
89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
90 return -EOPNOTSUPP;
91
92 return smu_get_pp_feature_mask(smu, buf);
93 }
94
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)95 static int smu_sys_set_pp_feature_mask(void *handle,
96 uint64_t new_mask)
97 {
98 struct smu_context *smu = handle;
99
100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
101 return -EOPNOTSUPP;
102
103 return smu_set_pp_feature_mask(smu, new_mask);
104 }
105
smu_set_residency_gfxoff(struct smu_context * smu,bool value)106 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
107 {
108 if (!smu->ppt_funcs->set_gfx_off_residency)
109 return -EINVAL;
110
111 return smu_set_gfx_off_residency(smu, value);
112 }
113
smu_get_residency_gfxoff(struct smu_context * smu,u32 * value)114 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
115 {
116 if (!smu->ppt_funcs->get_gfx_off_residency)
117 return -EINVAL;
118
119 return smu_get_gfx_off_residency(smu, value);
120 }
121
smu_get_entrycount_gfxoff(struct smu_context * smu,u64 * value)122 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
123 {
124 if (!smu->ppt_funcs->get_gfx_off_entrycount)
125 return -EINVAL;
126
127 return smu_get_gfx_off_entrycount(smu, value);
128 }
129
smu_get_status_gfxoff(struct smu_context * smu,uint32_t * value)130 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
131 {
132 if (!smu->ppt_funcs->get_gfx_off_status)
133 return -EINVAL;
134
135 *value = smu_get_gfx_off_status(smu);
136
137 return 0;
138 }
139
smu_set_soft_freq_range(struct smu_context * smu,enum pp_clock_type type,uint32_t min,uint32_t max)140 int smu_set_soft_freq_range(struct smu_context *smu,
141 enum pp_clock_type type,
142 uint32_t min,
143 uint32_t max)
144 {
145 enum smu_clk_type clk_type;
146 int ret = 0;
147
148 clk_type = smu_convert_to_smuclk(type);
149 if (clk_type == SMU_CLK_COUNT)
150 return -EINVAL;
151
152 if (smu->ppt_funcs->set_soft_freq_limited_range)
153 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
154 clk_type,
155 min,
156 max,
157 false);
158
159 return ret;
160 }
161
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)162 int smu_get_dpm_freq_range(struct smu_context *smu,
163 enum smu_clk_type clk_type,
164 uint32_t *min,
165 uint32_t *max)
166 {
167 int ret = -ENOTSUPP;
168
169 if (!min && !max)
170 return -EINVAL;
171
172 if (smu->ppt_funcs->get_dpm_ultimate_freq)
173 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
174 clk_type,
175 min,
176 max);
177
178 return ret;
179 }
180
smu_set_gfx_power_up_by_imu(struct smu_context * smu)181 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
182 {
183 int ret = 0;
184 struct amdgpu_device *adev = smu->adev;
185
186 if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
187 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
188 if (ret)
189 dev_err(adev->dev, "Failed to enable gfx imu!\n");
190 }
191 return ret;
192 }
193
smu_get_mclk(void * handle,bool low)194 static u32 smu_get_mclk(void *handle, bool low)
195 {
196 struct smu_context *smu = handle;
197 uint32_t clk_freq;
198 int ret = 0;
199
200 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
201 low ? &clk_freq : NULL,
202 !low ? &clk_freq : NULL);
203 if (ret)
204 return 0;
205 return clk_freq * 100;
206 }
207
smu_get_sclk(void * handle,bool low)208 static u32 smu_get_sclk(void *handle, bool low)
209 {
210 struct smu_context *smu = handle;
211 uint32_t clk_freq;
212 int ret = 0;
213
214 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
215 low ? &clk_freq : NULL,
216 !low ? &clk_freq : NULL);
217 if (ret)
218 return 0;
219 return clk_freq * 100;
220 }
221
smu_set_gfx_imu_enable(struct smu_context * smu)222 static int smu_set_gfx_imu_enable(struct smu_context *smu)
223 {
224 struct amdgpu_device *adev = smu->adev;
225
226 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
227 return 0;
228
229 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
230 return 0;
231
232 return smu_set_gfx_power_up_by_imu(smu);
233 }
234
is_vcn_enabled(struct amdgpu_device * adev)235 static bool is_vcn_enabled(struct amdgpu_device *adev)
236 {
237 int i;
238
239 for (i = 0; i < adev->num_ip_blocks; i++) {
240 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
241 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) &&
242 !adev->ip_blocks[i].status.valid)
243 return false;
244 }
245
246 return true;
247 }
248
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)249 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
250 bool enable,
251 int inst)
252 {
253 struct smu_power_context *smu_power = &smu->smu_power;
254 struct smu_power_gate *power_gate = &smu_power->power_gate;
255 int ret = 0;
256
257 /*
258 * don't poweron vcn/jpeg when they are skipped.
259 */
260 if (!is_vcn_enabled(smu->adev))
261 return 0;
262
263 if (!smu->ppt_funcs->dpm_set_vcn_enable)
264 return 0;
265
266 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
267 return 0;
268
269 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
270 if (!ret)
271 atomic_set(&power_gate->vcn_gated[inst], !enable);
272
273 return ret;
274 }
275
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)276 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
277 bool enable)
278 {
279 struct smu_power_context *smu_power = &smu->smu_power;
280 struct smu_power_gate *power_gate = &smu_power->power_gate;
281 int ret = 0;
282
283 if (!is_vcn_enabled(smu->adev))
284 return 0;
285
286 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
287 return 0;
288
289 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
290 return 0;
291
292 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
293 if (!ret)
294 atomic_set(&power_gate->jpeg_gated, !enable);
295
296 return ret;
297 }
298
smu_dpm_set_vpe_enable(struct smu_context * smu,bool enable)299 static int smu_dpm_set_vpe_enable(struct smu_context *smu,
300 bool enable)
301 {
302 struct smu_power_context *smu_power = &smu->smu_power;
303 struct smu_power_gate *power_gate = &smu_power->power_gate;
304 int ret = 0;
305
306 if (!smu->ppt_funcs->dpm_set_vpe_enable)
307 return 0;
308
309 if (atomic_read(&power_gate->vpe_gated) ^ enable)
310 return 0;
311
312 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable);
313 if (!ret)
314 atomic_set(&power_gate->vpe_gated, !enable);
315
316 return ret;
317 }
318
smu_dpm_set_isp_enable(struct smu_context * smu,bool enable)319 static int smu_dpm_set_isp_enable(struct smu_context *smu,
320 bool enable)
321 {
322 struct smu_power_context *smu_power = &smu->smu_power;
323 struct smu_power_gate *power_gate = &smu_power->power_gate;
324 int ret;
325
326 if (!smu->ppt_funcs->dpm_set_isp_enable)
327 return 0;
328
329 if (atomic_read(&power_gate->isp_gated) ^ enable)
330 return 0;
331
332 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable);
333 if (!ret)
334 atomic_set(&power_gate->isp_gated, !enable);
335
336 return ret;
337 }
338
smu_dpm_set_umsch_mm_enable(struct smu_context * smu,bool enable)339 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu,
340 bool enable)
341 {
342 struct smu_power_context *smu_power = &smu->smu_power;
343 struct smu_power_gate *power_gate = &smu_power->power_gate;
344 int ret = 0;
345
346 if (!smu->adev->enable_umsch_mm)
347 return 0;
348
349 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable)
350 return 0;
351
352 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable)
353 return 0;
354
355 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable);
356 if (!ret)
357 atomic_set(&power_gate->umsch_mm_gated, !enable);
358
359 return ret;
360 }
361
smu_set_mall_enable(struct smu_context * smu)362 static int smu_set_mall_enable(struct smu_context *smu)
363 {
364 int ret = 0;
365
366 if (!smu->ppt_funcs->set_mall_enable)
367 return 0;
368
369 ret = smu->ppt_funcs->set_mall_enable(smu);
370
371 return ret;
372 }
373
374 /**
375 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
376 *
377 * @handle: smu_context pointer
378 * @block_type: the IP block to power gate/ungate
379 * @gate: to power gate if true, ungate otherwise
380 * @inst: the instance of the IP block to power gate/ungate
381 *
382 * This API uses no smu->mutex lock protection due to:
383 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
384 * This is guarded to be race condition free by the caller.
385 * 2. Or get called on user setting request of power_dpm_force_performance_level.
386 * Under this case, the smu->mutex lock protection is already enforced on
387 * the parent API smu_force_performance_level of the call path.
388 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate,int inst)389 static int smu_dpm_set_power_gate(void *handle,
390 uint32_t block_type,
391 bool gate,
392 int inst)
393 {
394 struct smu_context *smu = handle;
395 int ret = 0;
396
397 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
398 dev_WARN(smu->adev->dev,
399 "SMU uninitialized but power %s requested for %u!\n",
400 gate ? "gate" : "ungate", block_type);
401 return -EOPNOTSUPP;
402 }
403
404 switch (block_type) {
405 /*
406 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
407 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
408 */
409 case AMD_IP_BLOCK_TYPE_UVD:
410 case AMD_IP_BLOCK_TYPE_VCN:
411 ret = smu_dpm_set_vcn_enable(smu, !gate, inst);
412 if (ret)
413 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
414 gate ? "gate" : "ungate", inst);
415 break;
416 case AMD_IP_BLOCK_TYPE_GFX:
417 ret = smu_gfx_off_control(smu, gate);
418 if (ret)
419 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
420 gate ? "enable" : "disable");
421 break;
422 case AMD_IP_BLOCK_TYPE_SDMA:
423 ret = smu_powergate_sdma(smu, gate);
424 if (ret)
425 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
426 gate ? "gate" : "ungate");
427 break;
428 case AMD_IP_BLOCK_TYPE_JPEG:
429 ret = smu_dpm_set_jpeg_enable(smu, !gate);
430 if (ret)
431 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
432 gate ? "gate" : "ungate");
433 break;
434 case AMD_IP_BLOCK_TYPE_VPE:
435 ret = smu_dpm_set_vpe_enable(smu, !gate);
436 if (ret)
437 dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
438 gate ? "gate" : "ungate");
439 break;
440 case AMD_IP_BLOCK_TYPE_ISP:
441 ret = smu_dpm_set_isp_enable(smu, !gate);
442 if (ret)
443 dev_err(smu->adev->dev, "Failed to power %s ISP!\n",
444 gate ? "gate" : "ungate");
445 break;
446 default:
447 dev_err(smu->adev->dev, "Unsupported block type!\n");
448 return -EINVAL;
449 }
450
451 return ret;
452 }
453
454 /**
455 * smu_set_user_clk_dependencies - set user profile clock dependencies
456 *
457 * @smu: smu_context pointer
458 * @clk: enum smu_clk_type type
459 *
460 * Enable/Disable the clock dependency for the @clk type.
461 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)462 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
463 {
464 if (smu->adev->in_suspend)
465 return;
466
467 if (clk == SMU_MCLK) {
468 smu->user_dpm_profile.clk_dependency = 0;
469 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
470 } else if (clk == SMU_FCLK) {
471 /* MCLK takes precedence over FCLK */
472 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
473 return;
474
475 smu->user_dpm_profile.clk_dependency = 0;
476 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
477 } else if (clk == SMU_SOCCLK) {
478 /* MCLK takes precedence over SOCCLK */
479 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
480 return;
481
482 smu->user_dpm_profile.clk_dependency = 0;
483 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
484 } else
485 /* Add clk dependencies here, if any */
486 return;
487 }
488
489 /**
490 * smu_restore_dpm_user_profile - reinstate user dpm profile
491 *
492 * @smu: smu_context pointer
493 *
494 * Restore the saved user power configurations include power limit,
495 * clock frequencies, fan control mode and fan speed.
496 */
smu_restore_dpm_user_profile(struct smu_context * smu)497 static void smu_restore_dpm_user_profile(struct smu_context *smu)
498 {
499 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
500 int ret = 0;
501
502 if (!smu->adev->in_suspend)
503 return;
504
505 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
506 return;
507
508 /* Enable restore flag */
509 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
510
511 /* set the user dpm power limit */
512 if (smu->user_dpm_profile.power_limit) {
513 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
514 if (ret)
515 dev_err(smu->adev->dev, "Failed to set power limit value\n");
516 }
517
518 /* set the user dpm clock configurations */
519 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
520 enum smu_clk_type clk_type;
521
522 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
523 /*
524 * Iterate over smu clk type and force the saved user clk
525 * configs, skip if clock dependency is enabled
526 */
527 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
528 smu->user_dpm_profile.clk_mask[clk_type]) {
529 ret = smu_force_smuclk_levels(smu, clk_type,
530 smu->user_dpm_profile.clk_mask[clk_type]);
531 if (ret)
532 dev_err(smu->adev->dev,
533 "Failed to set clock type = %d\n", clk_type);
534 }
535 }
536 }
537
538 /* set the user dpm fan configurations */
539 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
540 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
541 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
542 if (ret != -EOPNOTSUPP) {
543 smu->user_dpm_profile.fan_speed_pwm = 0;
544 smu->user_dpm_profile.fan_speed_rpm = 0;
545 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
546 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
547 }
548
549 if (smu->user_dpm_profile.fan_speed_pwm) {
550 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
551 if (ret != -EOPNOTSUPP)
552 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
553 }
554
555 if (smu->user_dpm_profile.fan_speed_rpm) {
556 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
557 if (ret != -EOPNOTSUPP)
558 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
559 }
560 }
561
562 /* Restore user customized OD settings */
563 if (smu->user_dpm_profile.user_od) {
564 if (smu->ppt_funcs->restore_user_od_settings) {
565 ret = smu->ppt_funcs->restore_user_od_settings(smu);
566 if (ret)
567 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
568 }
569 }
570
571 /* Disable restore flag */
572 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
573 }
574
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)575 static int smu_get_power_num_states(void *handle,
576 struct pp_states_info *state_info)
577 {
578 if (!state_info)
579 return -EINVAL;
580
581 /* not support power state */
582 memset(state_info, 0, sizeof(struct pp_states_info));
583 state_info->nums = 1;
584 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
585
586 return 0;
587 }
588
is_support_sw_smu(struct amdgpu_device * adev)589 bool is_support_sw_smu(struct amdgpu_device *adev)
590 {
591 /* vega20 is 11.0.2, but it's supported via the powerplay code */
592 if (adev->asic_type == CHIP_VEGA20)
593 return false;
594
595 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) &&
596 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC))
597 return true;
598
599 return false;
600 }
601
is_support_cclk_dpm(struct amdgpu_device * adev)602 bool is_support_cclk_dpm(struct amdgpu_device *adev)
603 {
604 struct smu_context *smu = adev->powerplay.pp_handle;
605
606 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
607 return false;
608
609 return true;
610 }
611
612
smu_sys_get_pp_table(void * handle,char ** table)613 static int smu_sys_get_pp_table(void *handle,
614 char **table)
615 {
616 struct smu_context *smu = handle;
617 struct smu_table_context *smu_table = &smu->smu_table;
618
619 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
620 return -EOPNOTSUPP;
621
622 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
623 return -EINVAL;
624
625 if (smu_table->hardcode_pptable)
626 *table = smu_table->hardcode_pptable;
627 else
628 *table = smu_table->power_play_table;
629
630 return smu_table->power_play_table_size;
631 }
632
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)633 static int smu_sys_set_pp_table(void *handle,
634 const char *buf,
635 size_t size)
636 {
637 struct smu_context *smu = handle;
638 struct smu_table_context *smu_table = &smu->smu_table;
639 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
640 int ret = 0;
641
642 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
643 return -EOPNOTSUPP;
644
645 if (header->usStructureSize != size) {
646 dev_err(smu->adev->dev, "pp table size not matched !\n");
647 return -EIO;
648 }
649
650 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) {
651 kfree(smu_table->hardcode_pptable);
652 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
653 if (!smu_table->hardcode_pptable)
654 return -ENOMEM;
655 }
656
657 memcpy(smu_table->hardcode_pptable, buf, size);
658 smu_table->power_play_table = smu_table->hardcode_pptable;
659 smu_table->power_play_table_size = size;
660
661 /*
662 * Special hw_fini action(for Navi1x, the DPMs disablement will be
663 * skipped) may be needed for custom pptable uploading.
664 */
665 smu->uploading_custom_pp_table = true;
666
667 ret = smu_reset(smu);
668 if (ret)
669 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
670
671 smu->uploading_custom_pp_table = false;
672
673 return ret;
674 }
675
smu_get_driver_allowed_feature_mask(struct smu_context * smu)676 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
677 {
678 struct smu_feature *feature = &smu->smu_feature;
679 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
680 int ret = 0;
681
682 /*
683 * With SCPM enabled, the allowed featuremasks setting(via
684 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
685 * That means there is no way to let PMFW knows the settings below.
686 * Thus, we just assume all the features are allowed under
687 * such scenario.
688 */
689 if (smu->adev->scpm_enabled) {
690 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
691 return 0;
692 }
693
694 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
695
696 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
697 SMU_FEATURE_MAX/32);
698 if (ret)
699 return ret;
700
701 bitmap_or(feature->allowed, feature->allowed,
702 (unsigned long *)allowed_feature_mask,
703 feature->feature_num);
704
705 return ret;
706 }
707
smu_set_funcs(struct amdgpu_device * adev)708 static int smu_set_funcs(struct amdgpu_device *adev)
709 {
710 struct smu_context *smu = adev->powerplay.pp_handle;
711
712 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
713 smu->od_enabled = true;
714
715 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
716 case IP_VERSION(11, 0, 0):
717 case IP_VERSION(11, 0, 5):
718 case IP_VERSION(11, 0, 9):
719 navi10_set_ppt_funcs(smu);
720 break;
721 case IP_VERSION(11, 0, 7):
722 case IP_VERSION(11, 0, 11):
723 case IP_VERSION(11, 0, 12):
724 case IP_VERSION(11, 0, 13):
725 sienna_cichlid_set_ppt_funcs(smu);
726 break;
727 case IP_VERSION(12, 0, 0):
728 case IP_VERSION(12, 0, 1):
729 renoir_set_ppt_funcs(smu);
730 break;
731 case IP_VERSION(11, 5, 0):
732 case IP_VERSION(11, 5, 2):
733 vangogh_set_ppt_funcs(smu);
734 break;
735 case IP_VERSION(13, 0, 1):
736 case IP_VERSION(13, 0, 3):
737 case IP_VERSION(13, 0, 8):
738 yellow_carp_set_ppt_funcs(smu);
739 break;
740 case IP_VERSION(13, 0, 4):
741 case IP_VERSION(13, 0, 11):
742 smu_v13_0_4_set_ppt_funcs(smu);
743 break;
744 case IP_VERSION(13, 0, 5):
745 smu_v13_0_5_set_ppt_funcs(smu);
746 break;
747 case IP_VERSION(11, 0, 8):
748 cyan_skillfish_set_ppt_funcs(smu);
749 break;
750 case IP_VERSION(11, 0, 2):
751 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
752 arcturus_set_ppt_funcs(smu);
753 /* OD is not supported on Arcturus */
754 smu->od_enabled = false;
755 break;
756 case IP_VERSION(13, 0, 2):
757 aldebaran_set_ppt_funcs(smu);
758 /* Enable pp_od_clk_voltage node */
759 smu->od_enabled = true;
760 break;
761 case IP_VERSION(13, 0, 0):
762 case IP_VERSION(13, 0, 10):
763 smu_v13_0_0_set_ppt_funcs(smu);
764 break;
765 case IP_VERSION(13, 0, 6):
766 case IP_VERSION(13, 0, 14):
767 case IP_VERSION(13, 0, 12):
768 smu_v13_0_6_set_ppt_funcs(smu);
769 /* Enable pp_od_clk_voltage node */
770 smu->od_enabled = true;
771 break;
772 case IP_VERSION(13, 0, 7):
773 smu_v13_0_7_set_ppt_funcs(smu);
774 break;
775 case IP_VERSION(14, 0, 0):
776 case IP_VERSION(14, 0, 1):
777 case IP_VERSION(14, 0, 4):
778 case IP_VERSION(14, 0, 5):
779 smu_v14_0_0_set_ppt_funcs(smu);
780 break;
781 case IP_VERSION(14, 0, 2):
782 case IP_VERSION(14, 0, 3):
783 smu_v14_0_2_set_ppt_funcs(smu);
784 break;
785 default:
786 return -EINVAL;
787 }
788
789 return 0;
790 }
791
smu_early_init(struct amdgpu_ip_block * ip_block)792 static int smu_early_init(struct amdgpu_ip_block *ip_block)
793 {
794 struct amdgpu_device *adev = ip_block->adev;
795 struct smu_context *smu;
796 int r;
797
798 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
799 if (!smu)
800 return -ENOMEM;
801
802 smu->adev = adev;
803 smu->pm_enabled = !!amdgpu_dpm;
804 smu->is_apu = false;
805 smu->smu_baco.state = SMU_BACO_STATE_NONE;
806 smu->smu_baco.platform_support = false;
807 smu->smu_baco.maco_support = false;
808 smu->user_dpm_profile.fan_mode = -1;
809 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN;
810
811 mutex_init(&smu->message_lock);
812
813 adev->powerplay.pp_handle = smu;
814 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
815
816 r = smu_set_funcs(adev);
817 if (r)
818 return r;
819 return smu_init_microcode(smu);
820 }
821
smu_set_default_dpm_table(struct smu_context * smu)822 static int smu_set_default_dpm_table(struct smu_context *smu)
823 {
824 struct amdgpu_device *adev = smu->adev;
825 struct smu_power_context *smu_power = &smu->smu_power;
826 struct smu_power_gate *power_gate = &smu_power->power_gate;
827 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i;
828 int ret = 0;
829
830 if (!smu->ppt_funcs->set_default_dpm_table)
831 return 0;
832
833 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
834 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
835 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]);
836 }
837 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
838 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
839
840 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
841 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
842 ret = smu_dpm_set_vcn_enable(smu, true, i);
843 if (ret)
844 return ret;
845 }
846 }
847
848 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
849 ret = smu_dpm_set_jpeg_enable(smu, true);
850 if (ret)
851 goto err_out;
852 }
853
854 ret = smu->ppt_funcs->set_default_dpm_table(smu);
855 if (ret)
856 dev_err(smu->adev->dev,
857 "Failed to setup default dpm clock tables!\n");
858
859 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
860 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
861 err_out:
862 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
863 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
864 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i);
865 }
866
867 return ret;
868 }
869
smu_apply_default_config_table_settings(struct smu_context * smu)870 static int smu_apply_default_config_table_settings(struct smu_context *smu)
871 {
872 struct amdgpu_device *adev = smu->adev;
873 int ret = 0;
874
875 ret = smu_get_default_config_table_settings(smu,
876 &adev->pm.config_table);
877 if (ret)
878 return ret;
879
880 return smu_set_config_table(smu, &adev->pm.config_table);
881 }
882
smu_late_init(struct amdgpu_ip_block * ip_block)883 static int smu_late_init(struct amdgpu_ip_block *ip_block)
884 {
885 struct amdgpu_device *adev = ip_block->adev;
886 struct smu_context *smu = adev->powerplay.pp_handle;
887 int ret = 0;
888
889 smu_set_fine_grain_gfx_freq_parameters(smu);
890
891 if (!smu->pm_enabled)
892 return 0;
893
894 ret = smu_post_init(smu);
895 if (ret) {
896 dev_err(adev->dev, "Failed to post smu init!\n");
897 return ret;
898 }
899
900 /*
901 * Explicitly notify PMFW the power mode the system in. Since
902 * the PMFW may boot the ASIC with a different mode.
903 * For those supporting ACDC switch via gpio, PMFW will
904 * handle the switch automatically. Driver involvement
905 * is unnecessary.
906 */
907 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
908 smu_set_ac_dc(smu);
909
910 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) ||
911 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3)))
912 return 0;
913
914 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
915 ret = smu_set_default_od_settings(smu);
916 if (ret) {
917 dev_err(adev->dev, "Failed to setup default OD settings!\n");
918 return ret;
919 }
920 }
921
922 ret = smu_populate_umd_state_clk(smu);
923 if (ret) {
924 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
925 return ret;
926 }
927
928 ret = smu_get_asic_power_limits(smu,
929 &smu->current_power_limit,
930 &smu->default_power_limit,
931 &smu->max_power_limit,
932 &smu->min_power_limit);
933 if (ret) {
934 dev_err(adev->dev, "Failed to get asic power limits!\n");
935 return ret;
936 }
937
938 if (!amdgpu_sriov_vf(adev))
939 smu_get_unique_id(smu);
940
941 smu_get_fan_parameters(smu);
942
943 smu_handle_task(smu,
944 smu->smu_dpm.dpm_level,
945 AMD_PP_TASK_COMPLETE_INIT);
946
947 ret = smu_apply_default_config_table_settings(smu);
948 if (ret && (ret != -EOPNOTSUPP)) {
949 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
950 return ret;
951 }
952
953 smu_restore_dpm_user_profile(smu);
954
955 return 0;
956 }
957
smu_init_fb_allocations(struct smu_context * smu)958 static int smu_init_fb_allocations(struct smu_context *smu)
959 {
960 struct amdgpu_device *adev = smu->adev;
961 struct smu_table_context *smu_table = &smu->smu_table;
962 struct smu_table *tables = smu_table->tables;
963 struct smu_table *driver_table = &(smu_table->driver_table);
964 uint32_t max_table_size = 0;
965 int ret, i;
966
967 /* VRAM allocation for tool table */
968 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
969 ret = amdgpu_bo_create_kernel(adev,
970 tables[SMU_TABLE_PMSTATUSLOG].size,
971 tables[SMU_TABLE_PMSTATUSLOG].align,
972 tables[SMU_TABLE_PMSTATUSLOG].domain,
973 &tables[SMU_TABLE_PMSTATUSLOG].bo,
974 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
975 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
976 if (ret) {
977 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
978 return ret;
979 }
980 }
981
982 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT;
983 /* VRAM allocation for driver table */
984 for (i = 0; i < SMU_TABLE_COUNT; i++) {
985 if (tables[i].size == 0)
986 continue;
987
988 /* If one of the tables has VRAM domain restriction, keep it in
989 * VRAM
990 */
991 if ((tables[i].domain &
992 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) ==
993 AMDGPU_GEM_DOMAIN_VRAM)
994 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
995
996 if (i == SMU_TABLE_PMSTATUSLOG)
997 continue;
998
999 if (max_table_size < tables[i].size)
1000 max_table_size = tables[i].size;
1001 }
1002
1003 driver_table->size = max_table_size;
1004 driver_table->align = PAGE_SIZE;
1005
1006 ret = amdgpu_bo_create_kernel(adev,
1007 driver_table->size,
1008 driver_table->align,
1009 driver_table->domain,
1010 &driver_table->bo,
1011 &driver_table->mc_address,
1012 &driver_table->cpu_addr);
1013 if (ret) {
1014 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
1015 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1016 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1017 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1018 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1019 }
1020
1021 return ret;
1022 }
1023
smu_fini_fb_allocations(struct smu_context * smu)1024 static int smu_fini_fb_allocations(struct smu_context *smu)
1025 {
1026 struct smu_table_context *smu_table = &smu->smu_table;
1027 struct smu_table *tables = smu_table->tables;
1028 struct smu_table *driver_table = &(smu_table->driver_table);
1029
1030 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1031 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1032 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1033 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1034
1035 amdgpu_bo_free_kernel(&driver_table->bo,
1036 &driver_table->mc_address,
1037 &driver_table->cpu_addr);
1038
1039 return 0;
1040 }
1041
smu_update_gpu_addresses(struct smu_context * smu)1042 static void smu_update_gpu_addresses(struct smu_context *smu)
1043 {
1044 struct smu_table_context *smu_table = &smu->smu_table;
1045 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG;
1046 struct smu_table *driver_table = &(smu_table->driver_table);
1047 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table;
1048
1049 if (pm_status_table->bo)
1050 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo);
1051 if (driver_table->bo)
1052 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo);
1053 if (dummy_read_1_table->bo)
1054 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo);
1055 }
1056
1057 /**
1058 * smu_alloc_memory_pool - allocate memory pool in the system memory
1059 *
1060 * @smu: amdgpu_device pointer
1061 *
1062 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1063 * and DramLogSetDramAddr can notify it changed.
1064 *
1065 * Returns 0 on success, error on failure.
1066 */
smu_alloc_memory_pool(struct smu_context * smu)1067 static int smu_alloc_memory_pool(struct smu_context *smu)
1068 {
1069 struct amdgpu_device *adev = smu->adev;
1070 struct smu_table_context *smu_table = &smu->smu_table;
1071 struct smu_table *memory_pool = &smu_table->memory_pool;
1072 uint64_t pool_size = smu->pool_size;
1073 int ret = 0;
1074
1075 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1076 return ret;
1077
1078 memory_pool->size = pool_size;
1079 memory_pool->align = PAGE_SIZE;
1080 memory_pool->domain =
1081 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ?
1082 AMDGPU_GEM_DOMAIN_VRAM :
1083 AMDGPU_GEM_DOMAIN_GTT;
1084
1085 switch (pool_size) {
1086 case SMU_MEMORY_POOL_SIZE_256_MB:
1087 case SMU_MEMORY_POOL_SIZE_512_MB:
1088 case SMU_MEMORY_POOL_SIZE_1_GB:
1089 case SMU_MEMORY_POOL_SIZE_2_GB:
1090 ret = amdgpu_bo_create_kernel(adev,
1091 memory_pool->size,
1092 memory_pool->align,
1093 memory_pool->domain,
1094 &memory_pool->bo,
1095 &memory_pool->mc_address,
1096 &memory_pool->cpu_addr);
1097 if (ret)
1098 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 return ret;
1105 }
1106
smu_free_memory_pool(struct smu_context * smu)1107 static int smu_free_memory_pool(struct smu_context *smu)
1108 {
1109 struct smu_table_context *smu_table = &smu->smu_table;
1110 struct smu_table *memory_pool = &smu_table->memory_pool;
1111
1112 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1113 return 0;
1114
1115 amdgpu_bo_free_kernel(&memory_pool->bo,
1116 &memory_pool->mc_address,
1117 &memory_pool->cpu_addr);
1118
1119 memset(memory_pool, 0, sizeof(struct smu_table));
1120
1121 return 0;
1122 }
1123
smu_alloc_dummy_read_table(struct smu_context * smu)1124 static int smu_alloc_dummy_read_table(struct smu_context *smu)
1125 {
1126 struct smu_table_context *smu_table = &smu->smu_table;
1127 struct smu_table *dummy_read_1_table =
1128 &smu_table->dummy_read_1_table;
1129 struct amdgpu_device *adev = smu->adev;
1130 int ret = 0;
1131
1132 if (!dummy_read_1_table->size)
1133 return 0;
1134
1135 ret = amdgpu_bo_create_kernel(adev,
1136 dummy_read_1_table->size,
1137 dummy_read_1_table->align,
1138 dummy_read_1_table->domain,
1139 &dummy_read_1_table->bo,
1140 &dummy_read_1_table->mc_address,
1141 &dummy_read_1_table->cpu_addr);
1142 if (ret)
1143 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
1144
1145 return ret;
1146 }
1147
smu_free_dummy_read_table(struct smu_context * smu)1148 static void smu_free_dummy_read_table(struct smu_context *smu)
1149 {
1150 struct smu_table_context *smu_table = &smu->smu_table;
1151 struct smu_table *dummy_read_1_table =
1152 &smu_table->dummy_read_1_table;
1153
1154
1155 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
1156 &dummy_read_1_table->mc_address,
1157 &dummy_read_1_table->cpu_addr);
1158
1159 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
1160 }
1161
smu_smc_table_sw_init(struct smu_context * smu)1162 static int smu_smc_table_sw_init(struct smu_context *smu)
1163 {
1164 int ret;
1165
1166 /**
1167 * Create smu_table structure, and init smc tables such as
1168 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
1169 */
1170 ret = smu_init_smc_tables(smu);
1171 if (ret) {
1172 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
1173 return ret;
1174 }
1175
1176 /**
1177 * Create smu_power_context structure, and allocate smu_dpm_context and
1178 * context size to fill the smu_power_context data.
1179 */
1180 ret = smu_init_power(smu);
1181 if (ret) {
1182 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1183 return ret;
1184 }
1185
1186 /*
1187 * allocate vram bos to store smc table contents.
1188 */
1189 ret = smu_init_fb_allocations(smu);
1190 if (ret)
1191 return ret;
1192
1193 ret = smu_alloc_memory_pool(smu);
1194 if (ret)
1195 return ret;
1196
1197 ret = smu_alloc_dummy_read_table(smu);
1198 if (ret)
1199 return ret;
1200
1201 ret = smu_i2c_init(smu);
1202 if (ret)
1203 return ret;
1204
1205 return 0;
1206 }
1207
smu_smc_table_sw_fini(struct smu_context * smu)1208 static int smu_smc_table_sw_fini(struct smu_context *smu)
1209 {
1210 int ret;
1211
1212 smu_i2c_fini(smu);
1213
1214 smu_free_dummy_read_table(smu);
1215
1216 ret = smu_free_memory_pool(smu);
1217 if (ret)
1218 return ret;
1219
1220 ret = smu_fini_fb_allocations(smu);
1221 if (ret)
1222 return ret;
1223
1224 ret = smu_fini_power(smu);
1225 if (ret) {
1226 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1227 return ret;
1228 }
1229
1230 ret = smu_fini_smc_tables(smu);
1231 if (ret) {
1232 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1233 return ret;
1234 }
1235
1236 return 0;
1237 }
1238
smu_throttling_logging_work_fn(struct work_struct * work)1239 static void smu_throttling_logging_work_fn(struct work_struct *work)
1240 {
1241 struct smu_context *smu = container_of(work, struct smu_context,
1242 throttling_logging_work);
1243
1244 smu_log_thermal_throttling(smu);
1245 }
1246
smu_interrupt_work_fn(struct work_struct * work)1247 static void smu_interrupt_work_fn(struct work_struct *work)
1248 {
1249 struct smu_context *smu = container_of(work, struct smu_context,
1250 interrupt_work);
1251
1252 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1253 smu->ppt_funcs->interrupt_work(smu);
1254 }
1255
smu_swctf_delayed_work_handler(struct work_struct * work)1256 static void smu_swctf_delayed_work_handler(struct work_struct *work)
1257 {
1258 struct smu_context *smu =
1259 container_of(work, struct smu_context, swctf_delayed_work.work);
1260 struct smu_temperature_range *range =
1261 &smu->thermal_range;
1262 struct amdgpu_device *adev = smu->adev;
1263 uint32_t hotspot_tmp, size;
1264
1265 /*
1266 * If the hotspot temperature is confirmed as below SW CTF setting point
1267 * after the delay enforced, nothing will be done.
1268 * Otherwise, a graceful shutdown will be performed to prevent further damage.
1269 */
1270 if (range->software_shutdown_temp &&
1271 smu->ppt_funcs->read_sensor &&
1272 !smu->ppt_funcs->read_sensor(smu,
1273 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1274 &hotspot_tmp,
1275 &size) &&
1276 hotspot_tmp / 1000 < range->software_shutdown_temp)
1277 return;
1278
1279 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1280 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1281 orderly_poweroff(true);
1282 }
1283
smu_init_xgmi_plpd_mode(struct smu_context * smu)1284 static void smu_init_xgmi_plpd_mode(struct smu_context *smu)
1285 {
1286 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm);
1287 struct smu_dpm_policy_ctxt *policy_ctxt;
1288 struct smu_dpm_policy *policy;
1289
1290 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD);
1291 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1292 if (policy)
1293 policy->current_level = XGMI_PLPD_DEFAULT;
1294 return;
1295 }
1296
1297 /* PMFW put PLPD into default policy after enabling the feature */
1298 if (smu_feature_is_enabled(smu,
1299 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) {
1300 if (policy)
1301 policy->current_level = XGMI_PLPD_DEFAULT;
1302 } else {
1303 policy_ctxt = dpm_ctxt->dpm_policies;
1304 if (policy_ctxt)
1305 policy_ctxt->policy_mask &=
1306 ~BIT(PP_PM_POLICY_XGMI_PLPD);
1307 }
1308 }
1309
smu_init_power_profile(struct smu_context * smu)1310 static void smu_init_power_profile(struct smu_context *smu)
1311 {
1312 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN)
1313 smu->power_profile_mode =
1314 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1315 smu_power_profile_mode_get(smu, smu->power_profile_mode);
1316 }
1317
smu_feature_cap_set(struct smu_context * smu,enum smu_feature_cap_id fea_id)1318 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id)
1319 {
1320 struct smu_feature_cap *fea_cap = &smu->fea_cap;
1321
1322 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT)
1323 return;
1324
1325 set_bit(fea_id, fea_cap->cap_map);
1326 }
1327
smu_feature_cap_test(struct smu_context * smu,enum smu_feature_cap_id fea_id)1328 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id)
1329 {
1330 struct smu_feature_cap *fea_cap = &smu->fea_cap;
1331
1332 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT)
1333 return false;
1334
1335 return test_bit(fea_id, fea_cap->cap_map);
1336 }
1337
smu_feature_cap_init(struct smu_context * smu)1338 static void smu_feature_cap_init(struct smu_context *smu)
1339 {
1340 struct smu_feature_cap *fea_cap = &smu->fea_cap;
1341
1342 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT);
1343 }
1344
smu_sw_init(struct amdgpu_ip_block * ip_block)1345 static int smu_sw_init(struct amdgpu_ip_block *ip_block)
1346 {
1347 struct amdgpu_device *adev = ip_block->adev;
1348 struct smu_context *smu = adev->powerplay.pp_handle;
1349 int i, ret;
1350
1351 smu->pool_size = adev->pm.smu_prv_buffer_size;
1352 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1353 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1354 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1355
1356 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1357 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1358 atomic64_set(&smu->throttle_int_counter, 0);
1359 smu->watermarks_bitmap = 0;
1360
1361 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1362 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
1363 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1364 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
1365 atomic_set(&smu->smu_power.power_gate.isp_gated, 1);
1366 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
1367
1368 smu_init_power_profile(smu);
1369 smu->display_config = &adev->pm.pm_display_cfg;
1370
1371 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1372 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1373
1374 INIT_DELAYED_WORK(&smu->swctf_delayed_work,
1375 smu_swctf_delayed_work_handler);
1376
1377 smu_feature_cap_init(smu);
1378
1379 ret = smu_smc_table_sw_init(smu);
1380 if (ret) {
1381 dev_err(adev->dev, "Failed to sw init smc table!\n");
1382 return ret;
1383 }
1384
1385 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1386 ret = smu_get_vbios_bootup_values(smu);
1387 if (ret) {
1388 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1389 return ret;
1390 }
1391
1392 ret = smu_init_pptable_microcode(smu);
1393 if (ret) {
1394 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1395 return ret;
1396 }
1397
1398 ret = smu_register_irq_handler(smu);
1399 if (ret) {
1400 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1401 return ret;
1402 }
1403
1404 /* If there is no way to query fan control mode, fan control is not supported */
1405 if (!smu->ppt_funcs->get_fan_control_mode)
1406 smu->adev->pm.no_fan = true;
1407
1408 return 0;
1409 }
1410
smu_sw_fini(struct amdgpu_ip_block * ip_block)1411 static int smu_sw_fini(struct amdgpu_ip_block *ip_block)
1412 {
1413 struct amdgpu_device *adev = ip_block->adev;
1414 struct smu_context *smu = adev->powerplay.pp_handle;
1415 int ret;
1416
1417 ret = smu_smc_table_sw_fini(smu);
1418 if (ret) {
1419 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1420 return ret;
1421 }
1422
1423 if (smu->custom_profile_params) {
1424 kfree(smu->custom_profile_params);
1425 smu->custom_profile_params = NULL;
1426 }
1427
1428 smu_fini_microcode(smu);
1429
1430 return 0;
1431 }
1432
smu_get_thermal_temperature_range(struct smu_context * smu)1433 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1434 {
1435 struct amdgpu_device *adev = smu->adev;
1436 struct smu_temperature_range *range =
1437 &smu->thermal_range;
1438 int ret = 0;
1439
1440 if (!smu->ppt_funcs->get_thermal_temperature_range)
1441 return 0;
1442
1443 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1444 if (ret)
1445 return ret;
1446
1447 adev->pm.dpm.thermal.min_temp = range->min;
1448 adev->pm.dpm.thermal.max_temp = range->max;
1449 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1450 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1451 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1452 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1453 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1454 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1455 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1456
1457 return ret;
1458 }
1459
1460 /**
1461 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges
1462 *
1463 * @smu: smu_context pointer
1464 *
1465 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling.
1466 * Returns 0 on success, error on failure.
1467 */
smu_wbrf_handle_exclusion_ranges(struct smu_context * smu)1468 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
1469 {
1470 struct wbrf_ranges_in_out wbrf_exclusion = {0};
1471 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list;
1472 struct amdgpu_device *adev = smu->adev;
1473 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;
1474 uint64_t start, end;
1475 int ret, i, j;
1476
1477 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion);
1478 if (ret) {
1479 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n");
1480 return ret;
1481 }
1482
1483 /*
1484 * The exclusion ranges array we got might be filled with holes and duplicate
1485 * entries. For example:
1486 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...}
1487 * We need to do some sortups to eliminate those holes and duplicate entries.
1488 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...}
1489 */
1490 for (i = 0; i < num_of_wbrf_ranges; i++) {
1491 start = wifi_bands[i].start;
1492 end = wifi_bands[i].end;
1493
1494 /* get the last valid entry to fill the intermediate hole */
1495 if (!start && !end) {
1496 for (j = num_of_wbrf_ranges - 1; j > i; j--)
1497 if (wifi_bands[j].start && wifi_bands[j].end)
1498 break;
1499
1500 /* no valid entry left */
1501 if (j <= i)
1502 break;
1503
1504 start = wifi_bands[i].start = wifi_bands[j].start;
1505 end = wifi_bands[i].end = wifi_bands[j].end;
1506 wifi_bands[j].start = 0;
1507 wifi_bands[j].end = 0;
1508 num_of_wbrf_ranges = j;
1509 }
1510
1511 /* eliminate duplicate entries */
1512 for (j = i + 1; j < num_of_wbrf_ranges; j++) {
1513 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) {
1514 wifi_bands[j].start = 0;
1515 wifi_bands[j].end = 0;
1516 }
1517 }
1518 }
1519
1520 /* Send the sorted wifi_bands to PMFW */
1521 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1522 /* Try to set the wifi_bands again */
1523 if (unlikely(ret == -EBUSY)) {
1524 mdelay(5);
1525 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1526 }
1527
1528 return ret;
1529 }
1530
1531 /**
1532 * smu_wbrf_event_handler - handle notify events
1533 *
1534 * @nb: notifier block
1535 * @action: event type
1536 * @_arg: event data
1537 *
1538 * Calls relevant amdgpu function in response to wbrf event
1539 * notification from kernel.
1540 */
smu_wbrf_event_handler(struct notifier_block * nb,unsigned long action,void * _arg)1541 static int smu_wbrf_event_handler(struct notifier_block *nb,
1542 unsigned long action, void *_arg)
1543 {
1544 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier);
1545
1546 switch (action) {
1547 case WBRF_CHANGED:
1548 schedule_delayed_work(&smu->wbrf_delayed_work,
1549 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1550 break;
1551 default:
1552 return NOTIFY_DONE;
1553 }
1554
1555 return NOTIFY_OK;
1556 }
1557
1558 /**
1559 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired
1560 *
1561 * @work: struct work_struct pointer
1562 *
1563 * Flood is over and driver will consume the latest exclusion ranges.
1564 */
smu_wbrf_delayed_work_handler(struct work_struct * work)1565 static void smu_wbrf_delayed_work_handler(struct work_struct *work)
1566 {
1567 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work);
1568
1569 smu_wbrf_handle_exclusion_ranges(smu);
1570 }
1571
1572 /**
1573 * smu_wbrf_support_check - check wbrf support
1574 *
1575 * @smu: smu_context pointer
1576 *
1577 * Verifies the ACPI interface whether wbrf is supported.
1578 */
smu_wbrf_support_check(struct smu_context * smu)1579 static void smu_wbrf_support_check(struct smu_context *smu)
1580 {
1581 struct amdgpu_device *adev = smu->adev;
1582
1583 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf &&
1584 acpi_amd_wbrf_supported_consumer(adev->dev);
1585
1586 if (smu->wbrf_supported)
1587 dev_info(adev->dev, "RF interference mitigation is supported\n");
1588 }
1589
1590 /**
1591 * smu_wbrf_init - init driver wbrf support
1592 *
1593 * @smu: smu_context pointer
1594 *
1595 * Verifies the AMD ACPI interfaces and registers with the wbrf
1596 * notifier chain if wbrf feature is supported.
1597 * Returns 0 on success, error on failure.
1598 */
smu_wbrf_init(struct smu_context * smu)1599 static int smu_wbrf_init(struct smu_context *smu)
1600 {
1601 int ret;
1602
1603 if (!smu->wbrf_supported)
1604 return 0;
1605
1606 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler);
1607
1608 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler;
1609 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier);
1610 if (ret)
1611 return ret;
1612
1613 /*
1614 * Some wifiband exclusion ranges may be already there
1615 * before our driver loaded. To make sure our driver
1616 * is awared of those exclusion ranges.
1617 */
1618 schedule_delayed_work(&smu->wbrf_delayed_work,
1619 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1620
1621 return 0;
1622 }
1623
1624 /**
1625 * smu_wbrf_fini - tear down driver wbrf support
1626 *
1627 * @smu: smu_context pointer
1628 *
1629 * Unregisters with the wbrf notifier chain.
1630 */
smu_wbrf_fini(struct smu_context * smu)1631 static void smu_wbrf_fini(struct smu_context *smu)
1632 {
1633 if (!smu->wbrf_supported)
1634 return;
1635
1636 amd_wbrf_unregister_notifier(&smu->wbrf_notifier);
1637
1638 cancel_delayed_work_sync(&smu->wbrf_delayed_work);
1639 }
1640
smu_smc_hw_setup(struct smu_context * smu)1641 static int smu_smc_hw_setup(struct smu_context *smu)
1642 {
1643 struct smu_feature *feature = &smu->smu_feature;
1644 struct amdgpu_device *adev = smu->adev;
1645 uint8_t pcie_gen = 0, pcie_width = 0;
1646 uint64_t features_supported;
1647 int ret = 0;
1648
1649 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1650 case IP_VERSION(11, 0, 7):
1651 case IP_VERSION(11, 0, 11):
1652 case IP_VERSION(11, 5, 0):
1653 case IP_VERSION(11, 5, 2):
1654 case IP_VERSION(11, 0, 12):
1655 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1656 dev_info(adev->dev, "dpm has been enabled\n");
1657 ret = smu_system_features_control(smu, true);
1658 if (ret)
1659 dev_err(adev->dev, "Failed system features control!\n");
1660 return ret;
1661 }
1662 break;
1663 default:
1664 break;
1665 }
1666
1667 ret = smu_init_display_count(smu, 0);
1668 if (ret) {
1669 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1670 return ret;
1671 }
1672
1673 ret = smu_set_driver_table_location(smu);
1674 if (ret) {
1675 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1676 return ret;
1677 }
1678
1679 /*
1680 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1681 */
1682 ret = smu_set_tool_table_location(smu);
1683 if (ret) {
1684 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1685 return ret;
1686 }
1687
1688 /*
1689 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1690 * pool location.
1691 */
1692 ret = smu_notify_memory_pool_location(smu);
1693 if (ret) {
1694 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1695 return ret;
1696 }
1697
1698 /*
1699 * It is assumed the pptable used before runpm is same as
1700 * the one used afterwards. Thus, we can reuse the stored
1701 * copy and do not need to resetup the pptable again.
1702 */
1703 if (!adev->in_runpm) {
1704 ret = smu_setup_pptable(smu);
1705 if (ret) {
1706 dev_err(adev->dev, "Failed to setup pptable!\n");
1707 return ret;
1708 }
1709 }
1710
1711 /* smu_dump_pptable(smu); */
1712
1713 /*
1714 * With SCPM enabled, PSP is responsible for the PPTable transferring
1715 * (to SMU). Driver involvement is not needed and permitted.
1716 */
1717 if (!adev->scpm_enabled) {
1718 /*
1719 * Copy pptable bo in the vram to smc with SMU MSGs such as
1720 * SetDriverDramAddr and TransferTableDram2Smu.
1721 */
1722 ret = smu_write_pptable(smu);
1723 if (ret) {
1724 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1725 return ret;
1726 }
1727 }
1728
1729 /* issue Run*Btc msg */
1730 ret = smu_run_btc(smu);
1731 if (ret)
1732 return ret;
1733
1734 /* Enable UclkShadow on wbrf supported */
1735 if (smu->wbrf_supported) {
1736 ret = smu_enable_uclk_shadow(smu, true);
1737 if (ret) {
1738 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n");
1739 return ret;
1740 }
1741 }
1742
1743 /*
1744 * With SCPM enabled, these actions(and relevant messages) are
1745 * not needed and permitted.
1746 */
1747 if (!adev->scpm_enabled) {
1748 ret = smu_feature_set_allowed_mask(smu);
1749 if (ret) {
1750 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1751 return ret;
1752 }
1753 }
1754
1755 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5)
1756 pcie_gen = 4;
1757 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1758 pcie_gen = 3;
1759 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1760 pcie_gen = 2;
1761 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1762 pcie_gen = 1;
1763 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1764 pcie_gen = 0;
1765
1766 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1767 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1768 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1769 */
1770 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
1771 pcie_width = 7;
1772 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1773 pcie_width = 6;
1774 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1775 pcie_width = 5;
1776 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1777 pcie_width = 4;
1778 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1779 pcie_width = 3;
1780 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1781 pcie_width = 2;
1782 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1783 pcie_width = 1;
1784 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1785 if (ret) {
1786 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1787 return ret;
1788 }
1789
1790 ret = smu_system_features_control(smu, true);
1791 if (ret) {
1792 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1793 return ret;
1794 }
1795
1796 smu_init_xgmi_plpd_mode(smu);
1797
1798 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1799 if (ret) {
1800 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1801 return ret;
1802 }
1803 bitmap_copy(feature->supported,
1804 (unsigned long *)&features_supported,
1805 feature->feature_num);
1806
1807 if (!smu_is_dpm_running(smu))
1808 dev_info(adev->dev, "dpm has been disabled\n");
1809
1810 /*
1811 * Set initialized values (get from vbios) to dpm tables context such as
1812 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1813 * type of clks.
1814 */
1815 ret = smu_set_default_dpm_table(smu);
1816 if (ret) {
1817 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1818 return ret;
1819 }
1820
1821 ret = smu_get_thermal_temperature_range(smu);
1822 if (ret) {
1823 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1824 return ret;
1825 }
1826
1827 ret = smu_enable_thermal_alert(smu);
1828 if (ret) {
1829 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1830 return ret;
1831 }
1832
1833 ret = smu_notify_display_change(smu);
1834 if (ret) {
1835 dev_err(adev->dev, "Failed to notify display change!\n");
1836 return ret;
1837 }
1838
1839 /*
1840 * Set min deep sleep dce fclk with bootup value from vbios via
1841 * SetMinDeepSleepDcefclk MSG.
1842 */
1843 ret = smu_set_min_dcef_deep_sleep(smu,
1844 smu->smu_table.boot_values.dcefclk / 100);
1845 if (ret) {
1846 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n");
1847 return ret;
1848 }
1849
1850 /* Init wbrf support. Properly setup the notifier */
1851 ret = smu_wbrf_init(smu);
1852 if (ret)
1853 dev_err(adev->dev, "Error during wbrf init call\n");
1854
1855 return ret;
1856 }
1857
smu_start_smc_engine(struct smu_context * smu)1858 static int smu_start_smc_engine(struct smu_context *smu)
1859 {
1860 struct amdgpu_device *adev = smu->adev;
1861 int ret = 0;
1862
1863 if (amdgpu_virt_xgmi_migrate_enabled(adev))
1864 smu_update_gpu_addresses(smu);
1865
1866 smu->smc_fw_state = SMU_FW_INIT;
1867
1868 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1869 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) {
1870 if (smu->ppt_funcs->load_microcode) {
1871 ret = smu->ppt_funcs->load_microcode(smu);
1872 if (ret)
1873 return ret;
1874 }
1875 }
1876 }
1877
1878 if (smu->ppt_funcs->check_fw_status) {
1879 ret = smu->ppt_funcs->check_fw_status(smu);
1880 if (ret) {
1881 dev_err(adev->dev, "SMC is not ready\n");
1882 return ret;
1883 }
1884 }
1885
1886 /*
1887 * Send msg GetDriverIfVersion to check if the return value is equal
1888 * with DRIVER_IF_VERSION of smc header.
1889 */
1890 ret = smu_check_fw_version(smu);
1891 if (ret)
1892 return ret;
1893
1894 return ret;
1895 }
1896
smu_hw_init(struct amdgpu_ip_block * ip_block)1897 static int smu_hw_init(struct amdgpu_ip_block *ip_block)
1898 {
1899 int i, ret;
1900 struct amdgpu_device *adev = ip_block->adev;
1901 struct smu_context *smu = adev->powerplay.pp_handle;
1902
1903 if (amdgpu_sriov_multi_vf_mode(adev)) {
1904 smu->pm_enabled = false;
1905 return 0;
1906 }
1907
1908 ret = smu_start_smc_engine(smu);
1909 if (ret) {
1910 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1911 return ret;
1912 }
1913
1914 /*
1915 * Check whether wbrf is supported. This needs to be done
1916 * before SMU setup starts since part of SMU configuration
1917 * relies on this.
1918 */
1919 smu_wbrf_support_check(smu);
1920
1921 if (smu->is_apu) {
1922 ret = smu_set_gfx_imu_enable(smu);
1923 if (ret)
1924 return ret;
1925 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1926 smu_dpm_set_vcn_enable(smu, true, i);
1927 smu_dpm_set_jpeg_enable(smu, true);
1928 smu_dpm_set_umsch_mm_enable(smu, true);
1929 smu_set_mall_enable(smu);
1930 smu_set_gfx_cgpg(smu, true);
1931 }
1932
1933 if (!smu->pm_enabled)
1934 return 0;
1935
1936 ret = smu_get_driver_allowed_feature_mask(smu);
1937 if (ret)
1938 return ret;
1939
1940 ret = smu_smc_hw_setup(smu);
1941 if (ret) {
1942 dev_err(adev->dev, "Failed to setup smc hw!\n");
1943 return ret;
1944 }
1945
1946 /*
1947 * Move maximum sustainable clock retrieving here considering
1948 * 1. It is not needed on resume(from S3).
1949 * 2. DAL settings come between .hw_init and .late_init of SMU.
1950 * And DAL needs to know the maximum sustainable clocks. Thus
1951 * it cannot be put in .late_init().
1952 */
1953 ret = smu_init_max_sustainable_clocks(smu);
1954 if (ret) {
1955 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1956 return ret;
1957 }
1958
1959 adev->pm.dpm_enabled = true;
1960
1961 dev_info(adev->dev, "SMU is initialized successfully!\n");
1962
1963 return 0;
1964 }
1965
smu_disable_dpms(struct smu_context * smu)1966 static int smu_disable_dpms(struct smu_context *smu)
1967 {
1968 struct amdgpu_device *adev = smu->adev;
1969 int ret = 0;
1970 bool use_baco = !smu->is_apu &&
1971 ((amdgpu_in_reset(adev) &&
1972 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1973 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1974
1975 /*
1976 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1977 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1978 */
1979 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1980 case IP_VERSION(13, 0, 0):
1981 case IP_VERSION(13, 0, 7):
1982 case IP_VERSION(13, 0, 10):
1983 case IP_VERSION(14, 0, 2):
1984 case IP_VERSION(14, 0, 3):
1985 return 0;
1986 default:
1987 break;
1988 }
1989
1990 /*
1991 * For custom pptable uploading, skip the DPM features
1992 * disable process on Navi1x ASICs.
1993 * - As the gfx related features are under control of
1994 * RLC on those ASICs. RLC reinitialization will be
1995 * needed to reenable them. That will cost much more
1996 * efforts.
1997 *
1998 * - SMU firmware can handle the DPM reenablement
1999 * properly.
2000 */
2001 if (smu->uploading_custom_pp_table) {
2002 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2003 case IP_VERSION(11, 0, 0):
2004 case IP_VERSION(11, 0, 5):
2005 case IP_VERSION(11, 0, 9):
2006 case IP_VERSION(11, 0, 7):
2007 case IP_VERSION(11, 0, 11):
2008 case IP_VERSION(11, 5, 0):
2009 case IP_VERSION(11, 5, 2):
2010 case IP_VERSION(11, 0, 12):
2011 case IP_VERSION(11, 0, 13):
2012 return 0;
2013 default:
2014 break;
2015 }
2016 }
2017
2018 /*
2019 * For Sienna_Cichlid, PMFW will handle the features disablement properly
2020 * on BACO in. Driver involvement is unnecessary.
2021 */
2022 if (use_baco) {
2023 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2024 case IP_VERSION(11, 0, 7):
2025 case IP_VERSION(11, 0, 0):
2026 case IP_VERSION(11, 0, 5):
2027 case IP_VERSION(11, 0, 9):
2028 case IP_VERSION(13, 0, 7):
2029 return 0;
2030 default:
2031 break;
2032 }
2033 }
2034
2035 /*
2036 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly
2037 * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
2038 */
2039 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 &&
2040 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
2041 return 0;
2042
2043 /*
2044 * For gpu reset, runpm and hibernation through BACO,
2045 * BACO feature has to be kept enabled.
2046 */
2047 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
2048 ret = smu_disable_all_features_with_exception(smu,
2049 SMU_FEATURE_BACO_BIT);
2050 if (ret)
2051 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
2052 } else {
2053 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
2054 if (!adev->scpm_enabled) {
2055 ret = smu_system_features_control(smu, false);
2056 if (ret)
2057 dev_err(adev->dev, "Failed to disable smu features.\n");
2058 }
2059 }
2060
2061 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction.
2062 * otherwise SMU will hang while interacting with RLC if RLC is halted
2063 * this is a WA for Vangogh asic which fix the SMU hang issue.
2064 */
2065 ret = smu_notify_rlc_state(smu, false);
2066 if (ret) {
2067 dev_err(adev->dev, "Fail to notify rlc status!\n");
2068 return ret;
2069 }
2070
2071 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&
2072 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&
2073 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
2074 adev->gfx.rlc.funcs->stop(adev);
2075
2076 return ret;
2077 }
2078
smu_smc_hw_cleanup(struct smu_context * smu)2079 static int smu_smc_hw_cleanup(struct smu_context *smu)
2080 {
2081 struct amdgpu_device *adev = smu->adev;
2082 int ret = 0;
2083
2084 smu_wbrf_fini(smu);
2085
2086 cancel_work_sync(&smu->throttling_logging_work);
2087 cancel_work_sync(&smu->interrupt_work);
2088
2089 ret = smu_disable_thermal_alert(smu);
2090 if (ret) {
2091 dev_err(adev->dev, "Fail to disable thermal alert!\n");
2092 return ret;
2093 }
2094
2095 cancel_delayed_work_sync(&smu->swctf_delayed_work);
2096
2097 ret = smu_disable_dpms(smu);
2098 if (ret) {
2099 dev_err(adev->dev, "Fail to disable dpm features!\n");
2100 return ret;
2101 }
2102
2103 return 0;
2104 }
2105
smu_reset_mp1_state(struct smu_context * smu)2106 static int smu_reset_mp1_state(struct smu_context *smu)
2107 {
2108 struct amdgpu_device *adev = smu->adev;
2109 int ret = 0;
2110
2111 if ((!adev->in_runpm) && (!adev->in_suspend) &&
2112 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2113 IP_VERSION(13, 0, 10) &&
2114 !amdgpu_device_has_display_hardware(adev))
2115 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
2116
2117 return ret;
2118 }
2119
smu_hw_fini(struct amdgpu_ip_block * ip_block)2120 static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
2121 {
2122 struct amdgpu_device *adev = ip_block->adev;
2123 struct smu_context *smu = adev->powerplay.pp_handle;
2124 int i, ret;
2125
2126 if (amdgpu_sriov_multi_vf_mode(adev))
2127 return 0;
2128
2129 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2130 smu_dpm_set_vcn_enable(smu, false, i);
2131 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE;
2132 }
2133 smu_dpm_set_jpeg_enable(smu, false);
2134 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
2135 smu_dpm_set_umsch_mm_enable(smu, false);
2136
2137 if (!smu->pm_enabled)
2138 return 0;
2139
2140 adev->pm.dpm_enabled = false;
2141
2142 ret = smu_smc_hw_cleanup(smu);
2143 if (ret)
2144 return ret;
2145
2146 ret = smu_reset_mp1_state(smu);
2147 if (ret)
2148 return ret;
2149
2150 return 0;
2151 }
2152
smu_late_fini(struct amdgpu_ip_block * ip_block)2153 static void smu_late_fini(struct amdgpu_ip_block *ip_block)
2154 {
2155 struct amdgpu_device *adev = ip_block->adev;
2156 struct smu_context *smu = adev->powerplay.pp_handle;
2157
2158 kfree(smu);
2159 }
2160
smu_reset(struct smu_context * smu)2161 static int smu_reset(struct smu_context *smu)
2162 {
2163 struct amdgpu_device *adev = smu->adev;
2164 struct amdgpu_ip_block *ip_block;
2165 int ret;
2166
2167 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC);
2168 if (!ip_block)
2169 return -EINVAL;
2170
2171 ret = smu_hw_fini(ip_block);
2172 if (ret)
2173 return ret;
2174
2175 ret = smu_hw_init(ip_block);
2176 if (ret)
2177 return ret;
2178
2179 ret = smu_late_init(ip_block);
2180 if (ret)
2181 return ret;
2182
2183 return 0;
2184 }
2185
smu_suspend(struct amdgpu_ip_block * ip_block)2186 static int smu_suspend(struct amdgpu_ip_block *ip_block)
2187 {
2188 struct amdgpu_device *adev = ip_block->adev;
2189 struct smu_context *smu = adev->powerplay.pp_handle;
2190 int ret;
2191 uint64_t count;
2192
2193 if (amdgpu_sriov_multi_vf_mode(adev))
2194 return 0;
2195
2196 if (!smu->pm_enabled)
2197 return 0;
2198
2199 adev->pm.dpm_enabled = false;
2200
2201 ret = smu_smc_hw_cleanup(smu);
2202 if (ret)
2203 return ret;
2204
2205 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
2206
2207 smu_set_gfx_cgpg(smu, false);
2208
2209 /*
2210 * pwfw resets entrycount when device is suspended, so we save the
2211 * last value to be used when we resume to keep it consistent
2212 */
2213 ret = smu_get_entrycount_gfxoff(smu, &count);
2214 if (!ret)
2215 adev->gfx.gfx_off_entrycount = count;
2216
2217 /* clear this on suspend so it will get reprogrammed on resume */
2218 smu->workload_mask = 0;
2219
2220 return 0;
2221 }
2222
smu_resume(struct amdgpu_ip_block * ip_block)2223 static int smu_resume(struct amdgpu_ip_block *ip_block)
2224 {
2225 int ret;
2226 struct amdgpu_device *adev = ip_block->adev;
2227 struct smu_context *smu = adev->powerplay.pp_handle;
2228 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2229
2230 if (amdgpu_sriov_multi_vf_mode(adev))
2231 return 0;
2232
2233 if (!smu->pm_enabled)
2234 return 0;
2235
2236 dev_info(adev->dev, "SMU is resuming...\n");
2237
2238 ret = smu_start_smc_engine(smu);
2239 if (ret) {
2240 dev_err(adev->dev, "SMC engine is not correctly up!\n");
2241 return ret;
2242 }
2243
2244 ret = smu_smc_hw_setup(smu);
2245 if (ret) {
2246 dev_err(adev->dev, "Failed to setup smc hw!\n");
2247 return ret;
2248 }
2249
2250 ret = smu_set_gfx_imu_enable(smu);
2251 if (ret)
2252 return ret;
2253
2254 smu_set_gfx_cgpg(smu, true);
2255
2256 smu->disable_uclk_switch = 0;
2257
2258 adev->pm.dpm_enabled = true;
2259
2260 if (smu->current_power_limit) {
2261 ret = smu_set_power_limit(smu, smu->current_power_limit);
2262 if (ret && ret != -EOPNOTSUPP)
2263 return ret;
2264 }
2265
2266 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL && smu->od_enabled) {
2267 ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0);
2268 if (ret)
2269 return ret;
2270 }
2271
2272 dev_info(adev->dev, "SMU is resumed successfully!\n");
2273
2274 return 0;
2275 }
2276
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)2277 static int smu_display_configuration_change(void *handle,
2278 const struct amd_pp_display_configuration *display_config)
2279 {
2280 struct smu_context *smu = handle;
2281
2282 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2283 return -EOPNOTSUPP;
2284
2285 if (!display_config)
2286 return -EINVAL;
2287
2288 smu_set_min_dcef_deep_sleep(smu,
2289 display_config->min_dcef_deep_sleep_set_clk / 100);
2290
2291 return 0;
2292 }
2293
smu_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2294 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2295 enum amd_clockgating_state state)
2296 {
2297 return 0;
2298 }
2299
smu_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2300 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
2301 enum amd_powergating_state state)
2302 {
2303 return 0;
2304 }
2305
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)2306 static int smu_enable_umd_pstate(void *handle,
2307 enum amd_dpm_forced_level *level)
2308 {
2309 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
2310 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
2311 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
2312 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
2313
2314 struct smu_context *smu = (struct smu_context*)(handle);
2315 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2316
2317 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2318 return -EINVAL;
2319
2320 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
2321 /* enter umd pstate, save current level, disable gfx cg*/
2322 if (*level & profile_mode_mask) {
2323 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
2324 smu_gpo_control(smu, false);
2325 smu_gfx_ulv_control(smu, false);
2326 smu_deep_sleep_control(smu, false);
2327 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
2328 }
2329 } else {
2330 /* exit umd pstate, restore level, enable gfx cg*/
2331 if (!(*level & profile_mode_mask)) {
2332 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
2333 *level = smu_dpm_ctx->saved_dpm_level;
2334 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
2335 smu_deep_sleep_control(smu, true);
2336 smu_gfx_ulv_control(smu, true);
2337 smu_gpo_control(smu, true);
2338 }
2339 }
2340
2341 return 0;
2342 }
2343
smu_bump_power_profile_mode(struct smu_context * smu,long * custom_params,u32 custom_params_max_idx)2344 static int smu_bump_power_profile_mode(struct smu_context *smu,
2345 long *custom_params,
2346 u32 custom_params_max_idx)
2347 {
2348 u32 workload_mask = 0;
2349 int i, ret = 0;
2350
2351 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2352 if (smu->workload_refcount[i])
2353 workload_mask |= 1 << i;
2354 }
2355
2356 if (smu->workload_mask == workload_mask)
2357 return 0;
2358
2359 if (smu->ppt_funcs->set_power_profile_mode)
2360 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask,
2361 custom_params,
2362 custom_params_max_idx);
2363
2364 if (!ret)
2365 smu->workload_mask = workload_mask;
2366
2367 return ret;
2368 }
2369
smu_power_profile_mode_get(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile_mode)2370 static void smu_power_profile_mode_get(struct smu_context *smu,
2371 enum PP_SMC_POWER_PROFILE profile_mode)
2372 {
2373 smu->workload_refcount[profile_mode]++;
2374 }
2375
smu_power_profile_mode_put(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile_mode)2376 static void smu_power_profile_mode_put(struct smu_context *smu,
2377 enum PP_SMC_POWER_PROFILE profile_mode)
2378 {
2379 if (smu->workload_refcount[profile_mode])
2380 smu->workload_refcount[profile_mode]--;
2381 }
2382
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings)2383 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
2384 enum amd_dpm_forced_level level,
2385 bool skip_display_settings)
2386 {
2387 int ret = 0;
2388 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2389
2390 if (!skip_display_settings) {
2391 ret = smu_display_config_changed(smu);
2392 if (ret) {
2393 dev_err(smu->adev->dev, "Failed to change display config!");
2394 return ret;
2395 }
2396 }
2397
2398 ret = smu_apply_clocks_adjust_rules(smu);
2399 if (ret) {
2400 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
2401 return ret;
2402 }
2403
2404 if (!skip_display_settings) {
2405 ret = smu_notify_smc_display_config(smu);
2406 if (ret) {
2407 dev_err(smu->adev->dev, "Failed to notify smc display config!");
2408 return ret;
2409 }
2410 }
2411
2412 if (smu_dpm_ctx->dpm_level != level) {
2413 ret = smu_asic_set_performance_level(smu, level);
2414 if (ret) {
2415 if (ret == -EOPNOTSUPP)
2416 dev_info(smu->adev->dev, "set performance level %d not supported",
2417 level);
2418 else
2419 dev_err(smu->adev->dev, "Failed to set performance level %d",
2420 level);
2421 return ret;
2422 }
2423
2424 /* update the saved copy */
2425 smu_dpm_ctx->dpm_level = level;
2426 }
2427
2428 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2429 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2430 smu_bump_power_profile_mode(smu, NULL, 0);
2431
2432 return ret;
2433 }
2434
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id)2435 static int smu_handle_task(struct smu_context *smu,
2436 enum amd_dpm_forced_level level,
2437 enum amd_pp_task task_id)
2438 {
2439 int ret = 0;
2440
2441 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2442 return -EOPNOTSUPP;
2443
2444 switch (task_id) {
2445 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
2446 ret = smu_pre_display_config_changed(smu);
2447 if (ret)
2448 return ret;
2449 ret = smu_adjust_power_state_dynamic(smu, level, false);
2450 break;
2451 case AMD_PP_TASK_COMPLETE_INIT:
2452 ret = smu_adjust_power_state_dynamic(smu, level, true);
2453 break;
2454 case AMD_PP_TASK_READJUST_POWER_STATE:
2455 ret = smu_adjust_power_state_dynamic(smu, level, true);
2456 break;
2457 default:
2458 break;
2459 }
2460
2461 return ret;
2462 }
2463
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)2464 static int smu_handle_dpm_task(void *handle,
2465 enum amd_pp_task task_id,
2466 enum amd_pm_state_type *user_state)
2467 {
2468 struct smu_context *smu = handle;
2469 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2470
2471 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
2472
2473 }
2474
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool enable)2475 static int smu_switch_power_profile(void *handle,
2476 enum PP_SMC_POWER_PROFILE type,
2477 bool enable)
2478 {
2479 struct smu_context *smu = handle;
2480 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2481 int ret;
2482
2483 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2484 return -EOPNOTSUPP;
2485
2486 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
2487 return -EINVAL;
2488
2489 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2490 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2491 if (enable)
2492 smu_power_profile_mode_get(smu, type);
2493 else
2494 smu_power_profile_mode_put(smu, type);
2495 /* don't switch the active workload when paused */
2496 if (smu->pause_workload)
2497 ret = 0;
2498 else
2499 ret = smu_bump_power_profile_mode(smu, NULL, 0);
2500 if (ret) {
2501 if (enable)
2502 smu_power_profile_mode_put(smu, type);
2503 else
2504 smu_power_profile_mode_get(smu, type);
2505 return ret;
2506 }
2507 }
2508
2509 return 0;
2510 }
2511
smu_pause_power_profile(void * handle,bool pause)2512 static int smu_pause_power_profile(void *handle,
2513 bool pause)
2514 {
2515 struct smu_context *smu = handle;
2516 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2517 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
2518 int ret;
2519
2520 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2521 return -EOPNOTSUPP;
2522
2523 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2524 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2525 smu->pause_workload = pause;
2526
2527 /* force to bootup default profile */
2528 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode)
2529 ret = smu->ppt_funcs->set_power_profile_mode(smu,
2530 workload_mask,
2531 NULL,
2532 0);
2533 else
2534 ret = smu_bump_power_profile_mode(smu, NULL, 0);
2535 return ret;
2536 }
2537
2538 return 0;
2539 }
2540
smu_get_performance_level(void * handle)2541 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
2542 {
2543 struct smu_context *smu = handle;
2544 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2545
2546 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2547 return -EOPNOTSUPP;
2548
2549 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2550 return -EINVAL;
2551
2552 return smu_dpm_ctx->dpm_level;
2553 }
2554
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)2555 static int smu_force_performance_level(void *handle,
2556 enum amd_dpm_forced_level level)
2557 {
2558 struct smu_context *smu = handle;
2559 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2560 int ret = 0;
2561
2562 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2563 return -EOPNOTSUPP;
2564
2565 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2566 return -EINVAL;
2567
2568 ret = smu_enable_umd_pstate(smu, &level);
2569 if (ret)
2570 return ret;
2571
2572 ret = smu_handle_task(smu, level,
2573 AMD_PP_TASK_READJUST_POWER_STATE);
2574
2575 /* reset user dpm clock state */
2576 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2577 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
2578 smu->user_dpm_profile.clk_dependency = 0;
2579 }
2580
2581 return ret;
2582 }
2583
smu_set_display_count(void * handle,uint32_t count)2584 static int smu_set_display_count(void *handle, uint32_t count)
2585 {
2586 struct smu_context *smu = handle;
2587
2588 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2589 return -EOPNOTSUPP;
2590
2591 return smu_init_display_count(smu, count);
2592 }
2593
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)2594 static int smu_force_smuclk_levels(struct smu_context *smu,
2595 enum smu_clk_type clk_type,
2596 uint32_t mask)
2597 {
2598 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2599 int ret = 0;
2600
2601 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2602 return -EOPNOTSUPP;
2603
2604 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2605 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
2606 return -EINVAL;
2607 }
2608
2609 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
2610 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
2611 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2612 smu->user_dpm_profile.clk_mask[clk_type] = mask;
2613 smu_set_user_clk_dependencies(smu, clk_type);
2614 }
2615 }
2616
2617 return ret;
2618 }
2619
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)2620 static int smu_force_ppclk_levels(void *handle,
2621 enum pp_clock_type type,
2622 uint32_t mask)
2623 {
2624 struct smu_context *smu = handle;
2625 enum smu_clk_type clk_type;
2626
2627 switch (type) {
2628 case PP_SCLK:
2629 clk_type = SMU_SCLK; break;
2630 case PP_MCLK:
2631 clk_type = SMU_MCLK; break;
2632 case PP_PCIE:
2633 clk_type = SMU_PCIE; break;
2634 case PP_SOCCLK:
2635 clk_type = SMU_SOCCLK; break;
2636 case PP_FCLK:
2637 clk_type = SMU_FCLK; break;
2638 case PP_DCEFCLK:
2639 clk_type = SMU_DCEFCLK; break;
2640 case PP_VCLK:
2641 clk_type = SMU_VCLK; break;
2642 case PP_VCLK1:
2643 clk_type = SMU_VCLK1; break;
2644 case PP_DCLK:
2645 clk_type = SMU_DCLK; break;
2646 case PP_DCLK1:
2647 clk_type = SMU_DCLK1; break;
2648 case OD_SCLK:
2649 clk_type = SMU_OD_SCLK; break;
2650 case OD_MCLK:
2651 clk_type = SMU_OD_MCLK; break;
2652 case OD_VDDC_CURVE:
2653 clk_type = SMU_OD_VDDC_CURVE; break;
2654 case OD_RANGE:
2655 clk_type = SMU_OD_RANGE; break;
2656 default:
2657 return -EINVAL;
2658 }
2659
2660 return smu_force_smuclk_levels(smu, clk_type, mask);
2661 }
2662
2663 /*
2664 * On system suspending or resetting, the dpm_enabled
2665 * flag will be cleared. So that those SMU services which
2666 * are not supported will be gated.
2667 * However, the mp1 state setting should still be granted
2668 * even if the dpm_enabled cleared.
2669 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2670 static int smu_set_mp1_state(void *handle,
2671 enum pp_mp1_state mp1_state)
2672 {
2673 struct smu_context *smu = handle;
2674 int ret = 0;
2675
2676 if (!smu->pm_enabled)
2677 return -EOPNOTSUPP;
2678
2679 if (smu->ppt_funcs &&
2680 smu->ppt_funcs->set_mp1_state)
2681 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2682
2683 return ret;
2684 }
2685
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2686 static int smu_set_df_cstate(void *handle,
2687 enum pp_df_cstate state)
2688 {
2689 struct smu_context *smu = handle;
2690 int ret = 0;
2691
2692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2693 return -EOPNOTSUPP;
2694
2695 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2696 return 0;
2697
2698 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2699 if (ret)
2700 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2701
2702 return ret;
2703 }
2704
smu_write_watermarks_table(struct smu_context * smu)2705 int smu_write_watermarks_table(struct smu_context *smu)
2706 {
2707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2708 return -EOPNOTSUPP;
2709
2710 return smu_set_watermarks_table(smu, NULL);
2711 }
2712
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2713 static int smu_set_watermarks_for_clock_ranges(void *handle,
2714 struct pp_smu_wm_range_sets *clock_ranges)
2715 {
2716 struct smu_context *smu = handle;
2717
2718 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2719 return -EOPNOTSUPP;
2720
2721 if (smu->disable_watermark)
2722 return 0;
2723
2724 return smu_set_watermarks_table(smu, clock_ranges);
2725 }
2726
smu_set_ac_dc(struct smu_context * smu)2727 int smu_set_ac_dc(struct smu_context *smu)
2728 {
2729 int ret = 0;
2730
2731 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2732 return -EOPNOTSUPP;
2733
2734 /* controlled by firmware */
2735 if (smu->dc_controlled_by_gpio)
2736 return 0;
2737
2738 ret = smu_set_power_source(smu,
2739 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2740 SMU_POWER_SOURCE_DC);
2741 if (ret)
2742 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2743 smu->adev->pm.ac_power ? "AC" : "DC");
2744
2745 return ret;
2746 }
2747
2748 const struct amd_ip_funcs smu_ip_funcs = {
2749 .name = "smu",
2750 .early_init = smu_early_init,
2751 .late_init = smu_late_init,
2752 .sw_init = smu_sw_init,
2753 .sw_fini = smu_sw_fini,
2754 .hw_init = smu_hw_init,
2755 .hw_fini = smu_hw_fini,
2756 .late_fini = smu_late_fini,
2757 .suspend = smu_suspend,
2758 .resume = smu_resume,
2759 .is_idle = NULL,
2760 .check_soft_reset = NULL,
2761 .wait_for_idle = NULL,
2762 .soft_reset = NULL,
2763 .set_clockgating_state = smu_set_clockgating_state,
2764 .set_powergating_state = smu_set_powergating_state,
2765 };
2766
2767 const struct amdgpu_ip_block_version smu_v11_0_ip_block = {
2768 .type = AMD_IP_BLOCK_TYPE_SMC,
2769 .major = 11,
2770 .minor = 0,
2771 .rev = 0,
2772 .funcs = &smu_ip_funcs,
2773 };
2774
2775 const struct amdgpu_ip_block_version smu_v12_0_ip_block = {
2776 .type = AMD_IP_BLOCK_TYPE_SMC,
2777 .major = 12,
2778 .minor = 0,
2779 .rev = 0,
2780 .funcs = &smu_ip_funcs,
2781 };
2782
2783 const struct amdgpu_ip_block_version smu_v13_0_ip_block = {
2784 .type = AMD_IP_BLOCK_TYPE_SMC,
2785 .major = 13,
2786 .minor = 0,
2787 .rev = 0,
2788 .funcs = &smu_ip_funcs,
2789 };
2790
2791 const struct amdgpu_ip_block_version smu_v14_0_ip_block = {
2792 .type = AMD_IP_BLOCK_TYPE_SMC,
2793 .major = 14,
2794 .minor = 0,
2795 .rev = 0,
2796 .funcs = &smu_ip_funcs,
2797 };
2798
smu_load_microcode(void * handle)2799 static int smu_load_microcode(void *handle)
2800 {
2801 struct smu_context *smu = handle;
2802 struct amdgpu_device *adev = smu->adev;
2803 int ret = 0;
2804
2805 if (!smu->pm_enabled)
2806 return -EOPNOTSUPP;
2807
2808 /* This should be used for non PSP loading */
2809 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2810 return 0;
2811
2812 if (smu->ppt_funcs->load_microcode) {
2813 ret = smu->ppt_funcs->load_microcode(smu);
2814 if (ret) {
2815 dev_err(adev->dev, "Load microcode failed\n");
2816 return ret;
2817 }
2818 }
2819
2820 if (smu->ppt_funcs->check_fw_status) {
2821 ret = smu->ppt_funcs->check_fw_status(smu);
2822 if (ret) {
2823 dev_err(adev->dev, "SMC is not ready\n");
2824 return ret;
2825 }
2826 }
2827
2828 return ret;
2829 }
2830
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2831 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2832 {
2833 int ret = 0;
2834
2835 if (smu->ppt_funcs->set_gfx_cgpg)
2836 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2837
2838 return ret;
2839 }
2840
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2841 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2842 {
2843 struct smu_context *smu = handle;
2844 int ret = 0;
2845
2846 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2847 return -EOPNOTSUPP;
2848
2849 if (!smu->ppt_funcs->set_fan_speed_rpm)
2850 return -EOPNOTSUPP;
2851
2852 if (speed == U32_MAX)
2853 return -EINVAL;
2854
2855 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2856 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2857 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2858 smu->user_dpm_profile.fan_speed_rpm = speed;
2859
2860 /* Override custom PWM setting as they cannot co-exist */
2861 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2862 smu->user_dpm_profile.fan_speed_pwm = 0;
2863 }
2864
2865 return ret;
2866 }
2867
2868 /**
2869 * smu_get_power_limit - Request one of the SMU Power Limits
2870 *
2871 * @handle: pointer to smu context
2872 * @limit: requested limit is written back to this variable
2873 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2874 * @pp_power_type: &pp_power_type type of power
2875 * Return: 0 on success, <0 on error
2876 *
2877 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2878 int smu_get_power_limit(void *handle,
2879 uint32_t *limit,
2880 enum pp_power_limit_level pp_limit_level,
2881 enum pp_power_type pp_power_type)
2882 {
2883 struct smu_context *smu = handle;
2884 struct amdgpu_device *adev = smu->adev;
2885 enum smu_ppt_limit_level limit_level;
2886 uint32_t limit_type;
2887 int ret = 0;
2888
2889 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2890 return -EOPNOTSUPP;
2891
2892 switch (pp_power_type) {
2893 case PP_PWR_TYPE_SUSTAINED:
2894 limit_type = SMU_DEFAULT_PPT_LIMIT;
2895 break;
2896 case PP_PWR_TYPE_FAST:
2897 limit_type = SMU_FAST_PPT_LIMIT;
2898 break;
2899 default:
2900 return -EOPNOTSUPP;
2901 }
2902
2903 switch (pp_limit_level) {
2904 case PP_PWR_LIMIT_CURRENT:
2905 limit_level = SMU_PPT_LIMIT_CURRENT;
2906 break;
2907 case PP_PWR_LIMIT_DEFAULT:
2908 limit_level = SMU_PPT_LIMIT_DEFAULT;
2909 break;
2910 case PP_PWR_LIMIT_MAX:
2911 limit_level = SMU_PPT_LIMIT_MAX;
2912 break;
2913 case PP_PWR_LIMIT_MIN:
2914 limit_level = SMU_PPT_LIMIT_MIN;
2915 break;
2916 default:
2917 return -EOPNOTSUPP;
2918 }
2919
2920 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2921 if (smu->ppt_funcs->get_ppt_limit)
2922 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2923 } else {
2924 switch (limit_level) {
2925 case SMU_PPT_LIMIT_CURRENT:
2926 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2927 case IP_VERSION(13, 0, 2):
2928 case IP_VERSION(13, 0, 6):
2929 case IP_VERSION(13, 0, 12):
2930 case IP_VERSION(13, 0, 14):
2931 case IP_VERSION(11, 0, 7):
2932 case IP_VERSION(11, 0, 11):
2933 case IP_VERSION(11, 0, 12):
2934 case IP_VERSION(11, 0, 13):
2935 ret = smu_get_asic_power_limits(smu,
2936 &smu->current_power_limit,
2937 NULL, NULL, NULL);
2938 break;
2939 default:
2940 break;
2941 }
2942 *limit = smu->current_power_limit;
2943 break;
2944 case SMU_PPT_LIMIT_DEFAULT:
2945 *limit = smu->default_power_limit;
2946 break;
2947 case SMU_PPT_LIMIT_MAX:
2948 *limit = smu->max_power_limit;
2949 break;
2950 case SMU_PPT_LIMIT_MIN:
2951 *limit = smu->min_power_limit;
2952 break;
2953 default:
2954 return -EINVAL;
2955 }
2956 }
2957
2958 return ret;
2959 }
2960
smu_set_power_limit(void * handle,uint32_t limit)2961 static int smu_set_power_limit(void *handle, uint32_t limit)
2962 {
2963 struct smu_context *smu = handle;
2964 uint32_t limit_type = limit >> 24;
2965 int ret = 0;
2966
2967 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2968 return -EOPNOTSUPP;
2969
2970 limit &= (1<<24)-1;
2971 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2972 if (smu->ppt_funcs->set_power_limit)
2973 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2974
2975 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) {
2976 dev_err(smu->adev->dev,
2977 "New power limit (%d) is out of range [%d,%d]\n",
2978 limit, smu->min_power_limit, smu->max_power_limit);
2979 return -EINVAL;
2980 }
2981
2982 if (!limit)
2983 limit = smu->current_power_limit;
2984
2985 if (smu->ppt_funcs->set_power_limit) {
2986 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2987 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2988 smu->user_dpm_profile.power_limit = limit;
2989 }
2990
2991 return ret;
2992 }
2993
smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)2994 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2995 {
2996 int ret = 0;
2997
2998 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2999 return -EOPNOTSUPP;
3000
3001 if (smu->ppt_funcs->print_clk_levels)
3002 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
3003
3004 return ret;
3005 }
3006
smu_convert_to_smuclk(enum pp_clock_type type)3007 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
3008 {
3009 enum smu_clk_type clk_type;
3010
3011 switch (type) {
3012 case PP_SCLK:
3013 clk_type = SMU_SCLK; break;
3014 case PP_MCLK:
3015 clk_type = SMU_MCLK; break;
3016 case PP_PCIE:
3017 clk_type = SMU_PCIE; break;
3018 case PP_SOCCLK:
3019 clk_type = SMU_SOCCLK; break;
3020 case PP_FCLK:
3021 clk_type = SMU_FCLK; break;
3022 case PP_DCEFCLK:
3023 clk_type = SMU_DCEFCLK; break;
3024 case PP_VCLK:
3025 clk_type = SMU_VCLK; break;
3026 case PP_VCLK1:
3027 clk_type = SMU_VCLK1; break;
3028 case PP_DCLK:
3029 clk_type = SMU_DCLK; break;
3030 case PP_DCLK1:
3031 clk_type = SMU_DCLK1; break;
3032 case PP_ISPICLK:
3033 clk_type = SMU_ISPICLK;
3034 break;
3035 case PP_ISPXCLK:
3036 clk_type = SMU_ISPXCLK;
3037 break;
3038 case OD_SCLK:
3039 clk_type = SMU_OD_SCLK; break;
3040 case OD_MCLK:
3041 clk_type = SMU_OD_MCLK; break;
3042 case OD_VDDC_CURVE:
3043 clk_type = SMU_OD_VDDC_CURVE; break;
3044 case OD_RANGE:
3045 clk_type = SMU_OD_RANGE; break;
3046 case OD_VDDGFX_OFFSET:
3047 clk_type = SMU_OD_VDDGFX_OFFSET; break;
3048 case OD_CCLK:
3049 clk_type = SMU_OD_CCLK; break;
3050 case OD_FAN_CURVE:
3051 clk_type = SMU_OD_FAN_CURVE; break;
3052 case OD_ACOUSTIC_LIMIT:
3053 clk_type = SMU_OD_ACOUSTIC_LIMIT; break;
3054 case OD_ACOUSTIC_TARGET:
3055 clk_type = SMU_OD_ACOUSTIC_TARGET; break;
3056 case OD_FAN_TARGET_TEMPERATURE:
3057 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break;
3058 case OD_FAN_MINIMUM_PWM:
3059 clk_type = SMU_OD_FAN_MINIMUM_PWM; break;
3060 case OD_FAN_ZERO_RPM_ENABLE:
3061 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break;
3062 case OD_FAN_ZERO_RPM_STOP_TEMP:
3063 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break;
3064 default:
3065 clk_type = SMU_CLK_COUNT; break;
3066 }
3067
3068 return clk_type;
3069 }
3070
smu_print_ppclk_levels(void * handle,enum pp_clock_type type,char * buf)3071 static int smu_print_ppclk_levels(void *handle,
3072 enum pp_clock_type type,
3073 char *buf)
3074 {
3075 struct smu_context *smu = handle;
3076 enum smu_clk_type clk_type;
3077
3078 clk_type = smu_convert_to_smuclk(type);
3079 if (clk_type == SMU_CLK_COUNT)
3080 return -EINVAL;
3081
3082 return smu_print_smuclk_levels(smu, clk_type, buf);
3083 }
3084
smu_emit_ppclk_levels(void * handle,enum pp_clock_type type,char * buf,int * offset)3085 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
3086 {
3087 struct smu_context *smu = handle;
3088 enum smu_clk_type clk_type;
3089
3090 clk_type = smu_convert_to_smuclk(type);
3091 if (clk_type == SMU_CLK_COUNT)
3092 return -EINVAL;
3093
3094 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3095 return -EOPNOTSUPP;
3096
3097 if (!smu->ppt_funcs->emit_clk_levels)
3098 return -ENOENT;
3099
3100 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
3101
3102 }
3103
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)3104 static int smu_od_edit_dpm_table(void *handle,
3105 enum PP_OD_DPM_TABLE_COMMAND type,
3106 long *input, uint32_t size)
3107 {
3108 struct smu_context *smu = handle;
3109 int ret = 0;
3110
3111 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3112 return -EOPNOTSUPP;
3113
3114 if (smu->ppt_funcs->od_edit_dpm_table) {
3115 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
3116 }
3117
3118 return ret;
3119 }
3120
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)3121 static int smu_read_sensor(void *handle,
3122 int sensor,
3123 void *data,
3124 int *size_arg)
3125 {
3126 struct smu_context *smu = handle;
3127 struct amdgpu_device *adev = smu->adev;
3128 struct smu_umd_pstate_table *pstate_table =
3129 &smu->pstate_table;
3130 int i, ret = 0;
3131 uint32_t *size, size_val;
3132
3133 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3134 return -EOPNOTSUPP;
3135
3136 if (!data || !size_arg)
3137 return -EINVAL;
3138
3139 size_val = *size_arg;
3140 size = &size_val;
3141
3142 if (smu->ppt_funcs->read_sensor)
3143 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
3144 goto unlock;
3145
3146 switch (sensor) {
3147 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
3148 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
3149 *size = 4;
3150 break;
3151 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
3152 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
3153 *size = 4;
3154 break;
3155 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
3156 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
3157 *size = 4;
3158 break;
3159 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
3160 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
3161 *size = 4;
3162 break;
3163 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3164 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
3165 *size = 8;
3166 break;
3167 case AMDGPU_PP_SENSOR_UVD_POWER:
3168 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
3169 *size = 4;
3170 break;
3171 case AMDGPU_PP_SENSOR_VCE_POWER:
3172 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
3173 *size = 4;
3174 break;
3175 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
3176 *(uint32_t *)data = 0;
3177 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
3178 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
3179 *(uint32_t *)data = 1;
3180 break;
3181 }
3182 }
3183 *size = 4;
3184 break;
3185 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
3186 *(uint32_t *)data = 0;
3187 *size = 4;
3188 break;
3189 default:
3190 *size = 0;
3191 ret = -EOPNOTSUPP;
3192 break;
3193 }
3194
3195 unlock:
3196 // assign uint32_t to int
3197 *size_arg = size_val;
3198
3199 return ret;
3200 }
3201
smu_get_apu_thermal_limit(void * handle,uint32_t * limit)3202 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)
3203 {
3204 int ret = -EOPNOTSUPP;
3205 struct smu_context *smu = handle;
3206
3207 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit)
3208 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit);
3209
3210 return ret;
3211 }
3212
smu_set_apu_thermal_limit(void * handle,uint32_t limit)3213 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)
3214 {
3215 int ret = -EOPNOTSUPP;
3216 struct smu_context *smu = handle;
3217
3218 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)
3219 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit);
3220
3221 return ret;
3222 }
3223
smu_get_power_profile_mode(void * handle,char * buf)3224 static int smu_get_power_profile_mode(void *handle, char *buf)
3225 {
3226 struct smu_context *smu = handle;
3227
3228 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3229 !smu->ppt_funcs->get_power_profile_mode)
3230 return -EOPNOTSUPP;
3231 if (!buf)
3232 return -EINVAL;
3233
3234 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
3235 }
3236
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)3237 static int smu_set_power_profile_mode(void *handle,
3238 long *param,
3239 uint32_t param_size)
3240 {
3241 struct smu_context *smu = handle;
3242 bool custom = false;
3243 int ret = 0;
3244
3245 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3246 !smu->ppt_funcs->set_power_profile_mode)
3247 return -EOPNOTSUPP;
3248
3249 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) {
3250 custom = true;
3251 /* clear frontend mask so custom changes propogate */
3252 smu->workload_mask = 0;
3253 }
3254
3255 if ((param[param_size] != smu->power_profile_mode) || custom) {
3256 /* clear the old user preference */
3257 smu_power_profile_mode_put(smu, smu->power_profile_mode);
3258 /* set the new user preference */
3259 smu_power_profile_mode_get(smu, param[param_size]);
3260 ret = smu_bump_power_profile_mode(smu,
3261 custom ? param : NULL,
3262 custom ? param_size : 0);
3263 if (ret)
3264 smu_power_profile_mode_put(smu, param[param_size]);
3265 else
3266 /* store the user's preference */
3267 smu->power_profile_mode = param[param_size];
3268 }
3269
3270 return ret;
3271 }
3272
smu_get_fan_control_mode(void * handle,u32 * fan_mode)3273 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
3274 {
3275 struct smu_context *smu = handle;
3276
3277 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3278 return -EOPNOTSUPP;
3279
3280 if (!smu->ppt_funcs->get_fan_control_mode)
3281 return -EOPNOTSUPP;
3282
3283 if (!fan_mode)
3284 return -EINVAL;
3285
3286 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
3287
3288 return 0;
3289 }
3290
smu_set_fan_control_mode(void * handle,u32 value)3291 static int smu_set_fan_control_mode(void *handle, u32 value)
3292 {
3293 struct smu_context *smu = handle;
3294 int ret = 0;
3295
3296 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3297 return -EOPNOTSUPP;
3298
3299 if (!smu->ppt_funcs->set_fan_control_mode)
3300 return -EOPNOTSUPP;
3301
3302 if (value == U32_MAX)
3303 return -EINVAL;
3304
3305 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
3306 if (ret)
3307 goto out;
3308
3309 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3310 smu->user_dpm_profile.fan_mode = value;
3311
3312 /* reset user dpm fan speed */
3313 if (value != AMD_FAN_CTRL_MANUAL) {
3314 smu->user_dpm_profile.fan_speed_pwm = 0;
3315 smu->user_dpm_profile.fan_speed_rpm = 0;
3316 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
3317 }
3318 }
3319
3320 out:
3321 return ret;
3322 }
3323
smu_get_fan_speed_pwm(void * handle,u32 * speed)3324 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
3325 {
3326 struct smu_context *smu = handle;
3327 int ret = 0;
3328
3329 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3330 return -EOPNOTSUPP;
3331
3332 if (!smu->ppt_funcs->get_fan_speed_pwm)
3333 return -EOPNOTSUPP;
3334
3335 if (!speed)
3336 return -EINVAL;
3337
3338 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
3339
3340 return ret;
3341 }
3342
smu_set_fan_speed_pwm(void * handle,u32 speed)3343 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
3344 {
3345 struct smu_context *smu = handle;
3346 int ret = 0;
3347
3348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3349 return -EOPNOTSUPP;
3350
3351 if (!smu->ppt_funcs->set_fan_speed_pwm)
3352 return -EOPNOTSUPP;
3353
3354 if (speed == U32_MAX)
3355 return -EINVAL;
3356
3357 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
3358 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3359 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
3360 smu->user_dpm_profile.fan_speed_pwm = speed;
3361
3362 /* Override custom RPM setting as they cannot co-exist */
3363 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
3364 smu->user_dpm_profile.fan_speed_rpm = 0;
3365 }
3366
3367 return ret;
3368 }
3369
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)3370 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
3371 {
3372 struct smu_context *smu = handle;
3373 int ret = 0;
3374
3375 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3376 return -EOPNOTSUPP;
3377
3378 if (!smu->ppt_funcs->get_fan_speed_rpm)
3379 return -EOPNOTSUPP;
3380
3381 if (!speed)
3382 return -EINVAL;
3383
3384 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
3385
3386 return ret;
3387 }
3388
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)3389 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
3390 {
3391 struct smu_context *smu = handle;
3392
3393 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3394 return -EOPNOTSUPP;
3395
3396 return smu_set_min_dcef_deep_sleep(smu, clk);
3397 }
3398
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)3399 static int smu_get_clock_by_type_with_latency(void *handle,
3400 enum amd_pp_clock_type type,
3401 struct pp_clock_levels_with_latency *clocks)
3402 {
3403 struct smu_context *smu = handle;
3404 enum smu_clk_type clk_type;
3405 int ret = 0;
3406
3407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3408 return -EOPNOTSUPP;
3409
3410 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
3411 switch (type) {
3412 case amd_pp_sys_clock:
3413 clk_type = SMU_GFXCLK;
3414 break;
3415 case amd_pp_mem_clock:
3416 clk_type = SMU_MCLK;
3417 break;
3418 case amd_pp_dcef_clock:
3419 clk_type = SMU_DCEFCLK;
3420 break;
3421 case amd_pp_disp_clock:
3422 clk_type = SMU_DISPCLK;
3423 break;
3424 default:
3425 dev_err(smu->adev->dev, "Invalid clock type!\n");
3426 return -EINVAL;
3427 }
3428
3429 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
3430 }
3431
3432 return ret;
3433 }
3434
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)3435 static int smu_display_clock_voltage_request(void *handle,
3436 struct pp_display_clock_request *clock_req)
3437 {
3438 struct smu_context *smu = handle;
3439 int ret = 0;
3440
3441 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3442 return -EOPNOTSUPP;
3443
3444 if (smu->ppt_funcs->display_clock_voltage_request)
3445 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
3446
3447 return ret;
3448 }
3449
3450
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)3451 static int smu_display_disable_memory_clock_switch(void *handle,
3452 bool disable_memory_clock_switch)
3453 {
3454 struct smu_context *smu = handle;
3455 int ret = -EINVAL;
3456
3457 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3458 return -EOPNOTSUPP;
3459
3460 if (smu->ppt_funcs->display_disable_memory_clock_switch)
3461 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
3462
3463 return ret;
3464 }
3465
smu_set_xgmi_pstate(void * handle,uint32_t pstate)3466 static int smu_set_xgmi_pstate(void *handle,
3467 uint32_t pstate)
3468 {
3469 struct smu_context *smu = handle;
3470 int ret = 0;
3471
3472 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3473 return -EOPNOTSUPP;
3474
3475 if (smu->ppt_funcs->set_xgmi_pstate)
3476 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
3477
3478 if (ret)
3479 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
3480
3481 return ret;
3482 }
3483
smu_get_baco_capability(void * handle)3484 static int smu_get_baco_capability(void *handle)
3485 {
3486 struct smu_context *smu = handle;
3487
3488 if (!smu->pm_enabled)
3489 return false;
3490
3491 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support)
3492 return false;
3493
3494 return smu->ppt_funcs->get_bamaco_support(smu);
3495 }
3496
smu_baco_set_state(void * handle,int state)3497 static int smu_baco_set_state(void *handle, int state)
3498 {
3499 struct smu_context *smu = handle;
3500 int ret = 0;
3501
3502 if (!smu->pm_enabled)
3503 return -EOPNOTSUPP;
3504
3505 if (state == 0) {
3506 if (smu->ppt_funcs->baco_exit)
3507 ret = smu->ppt_funcs->baco_exit(smu);
3508 } else if (state == 1) {
3509 if (smu->ppt_funcs->baco_enter)
3510 ret = smu->ppt_funcs->baco_enter(smu);
3511 } else {
3512 return -EINVAL;
3513 }
3514
3515 if (ret)
3516 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
3517 (state)?"enter":"exit");
3518
3519 return ret;
3520 }
3521
smu_mode1_reset_is_support(struct smu_context * smu)3522 bool smu_mode1_reset_is_support(struct smu_context *smu)
3523 {
3524 bool ret = false;
3525
3526 if (!smu->pm_enabled)
3527 return false;
3528
3529 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
3530 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
3531
3532 return ret;
3533 }
3534
smu_link_reset_is_support(struct smu_context * smu)3535 bool smu_link_reset_is_support(struct smu_context *smu)
3536 {
3537 if (!smu->pm_enabled)
3538 return false;
3539
3540 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET);
3541 }
3542
smu_mode1_reset(struct smu_context * smu)3543 int smu_mode1_reset(struct smu_context *smu)
3544 {
3545 int ret = 0;
3546
3547 if (!smu->pm_enabled)
3548 return -EOPNOTSUPP;
3549
3550 if (smu->ppt_funcs->mode1_reset)
3551 ret = smu->ppt_funcs->mode1_reset(smu);
3552
3553 return ret;
3554 }
3555
smu_mode2_reset(void * handle)3556 static int smu_mode2_reset(void *handle)
3557 {
3558 struct smu_context *smu = handle;
3559 int ret = 0;
3560
3561 if (!smu->pm_enabled)
3562 return -EOPNOTSUPP;
3563
3564 if (smu->ppt_funcs->mode2_reset)
3565 ret = smu->ppt_funcs->mode2_reset(smu);
3566
3567 if (ret)
3568 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
3569
3570 return ret;
3571 }
3572
smu_link_reset(struct smu_context * smu)3573 int smu_link_reset(struct smu_context *smu)
3574 {
3575 int ret = 0;
3576
3577 if (!smu->pm_enabled)
3578 return -EOPNOTSUPP;
3579
3580 if (smu->ppt_funcs->link_reset)
3581 ret = smu->ppt_funcs->link_reset(smu);
3582
3583 return ret;
3584 }
3585
smu_enable_gfx_features(void * handle)3586 static int smu_enable_gfx_features(void *handle)
3587 {
3588 struct smu_context *smu = handle;
3589 int ret = 0;
3590
3591 if (!smu->pm_enabled)
3592 return -EOPNOTSUPP;
3593
3594 if (smu->ppt_funcs->enable_gfx_features)
3595 ret = smu->ppt_funcs->enable_gfx_features(smu);
3596
3597 if (ret)
3598 dev_err(smu->adev->dev, "enable gfx features failed!\n");
3599
3600 return ret;
3601 }
3602
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)3603 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
3604 struct pp_smu_nv_clock_table *max_clocks)
3605 {
3606 struct smu_context *smu = handle;
3607 int ret = 0;
3608
3609 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3610 return -EOPNOTSUPP;
3611
3612 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
3613 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
3614
3615 return ret;
3616 }
3617
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)3618 static int smu_get_uclk_dpm_states(void *handle,
3619 unsigned int *clock_values_in_khz,
3620 unsigned int *num_states)
3621 {
3622 struct smu_context *smu = handle;
3623 int ret = 0;
3624
3625 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3626 return -EOPNOTSUPP;
3627
3628 if (smu->ppt_funcs->get_uclk_dpm_states)
3629 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
3630
3631 return ret;
3632 }
3633
smu_get_current_power_state(void * handle)3634 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
3635 {
3636 struct smu_context *smu = handle;
3637 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
3638
3639 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3640 return -EOPNOTSUPP;
3641
3642 if (smu->ppt_funcs->get_current_power_state)
3643 pm_state = smu->ppt_funcs->get_current_power_state(smu);
3644
3645 return pm_state;
3646 }
3647
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)3648 static int smu_get_dpm_clock_table(void *handle,
3649 struct dpm_clocks *clock_table)
3650 {
3651 struct smu_context *smu = handle;
3652 int ret = 0;
3653
3654 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3655 return -EOPNOTSUPP;
3656
3657 if (smu->ppt_funcs->get_dpm_clock_table)
3658 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3659
3660 return ret;
3661 }
3662
smu_sys_get_gpu_metrics(void * handle,void ** table)3663 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3664 {
3665 struct smu_context *smu = handle;
3666
3667 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3668 return -EOPNOTSUPP;
3669
3670 if (!smu->ppt_funcs->get_gpu_metrics)
3671 return -EOPNOTSUPP;
3672
3673 return smu->ppt_funcs->get_gpu_metrics(smu, table);
3674 }
3675
smu_sys_get_pm_metrics(void * handle,void * pm_metrics,size_t size)3676 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics,
3677 size_t size)
3678 {
3679 struct smu_context *smu = handle;
3680
3681 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3682 return -EOPNOTSUPP;
3683
3684 if (!smu->ppt_funcs->get_pm_metrics)
3685 return -EOPNOTSUPP;
3686
3687 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size);
3688 }
3689
smu_enable_mgpu_fan_boost(void * handle)3690 static int smu_enable_mgpu_fan_boost(void *handle)
3691 {
3692 struct smu_context *smu = handle;
3693 int ret = 0;
3694
3695 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3696 return -EOPNOTSUPP;
3697
3698 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3699 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3700
3701 return ret;
3702 }
3703
smu_gfx_state_change_set(void * handle,uint32_t state)3704 static int smu_gfx_state_change_set(void *handle,
3705 uint32_t state)
3706 {
3707 struct smu_context *smu = handle;
3708 int ret = 0;
3709
3710 if (smu->ppt_funcs->gfx_state_change_set)
3711 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3712
3713 return ret;
3714 }
3715
smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)3716 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
3717 {
3718 int ret = 0;
3719
3720 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3721 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
3722
3723 return ret;
3724 }
3725
smu_get_ecc_info(struct smu_context * smu,void * umc_ecc)3726 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
3727 {
3728 int ret = -EOPNOTSUPP;
3729
3730 if (smu->ppt_funcs &&
3731 smu->ppt_funcs->get_ecc_info)
3732 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3733
3734 return ret;
3735
3736 }
3737
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3738 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3739 {
3740 struct smu_context *smu = handle;
3741 struct smu_table_context *smu_table = &smu->smu_table;
3742 struct smu_table *memory_pool = &smu_table->memory_pool;
3743
3744 if (!addr || !size)
3745 return -EINVAL;
3746
3747 *addr = NULL;
3748 *size = 0;
3749 if (memory_pool->bo) {
3750 *addr = memory_pool->cpu_addr;
3751 *size = memory_pool->size;
3752 }
3753
3754 return 0;
3755 }
3756
smu_print_dpm_policy(struct smu_dpm_policy * policy,char * sysbuf,size_t * size)3757 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf,
3758 size_t *size)
3759 {
3760 size_t offset = *size;
3761 int level;
3762
3763 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) {
3764 if (level == policy->current_level)
3765 offset += sysfs_emit_at(sysbuf, offset,
3766 "%d : %s*\n", level,
3767 policy->desc->get_desc(policy, level));
3768 else
3769 offset += sysfs_emit_at(sysbuf, offset,
3770 "%d : %s\n", level,
3771 policy->desc->get_desc(policy, level));
3772 }
3773
3774 *size = offset;
3775 }
3776
smu_get_pm_policy_info(struct smu_context * smu,enum pp_pm_policy p_type,char * sysbuf)3777 ssize_t smu_get_pm_policy_info(struct smu_context *smu,
3778 enum pp_pm_policy p_type, char *sysbuf)
3779 {
3780 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3781 struct smu_dpm_policy_ctxt *policy_ctxt;
3782 struct smu_dpm_policy *dpm_policy;
3783 size_t offset = 0;
3784
3785 policy_ctxt = dpm_ctxt->dpm_policies;
3786 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt ||
3787 !policy_ctxt->policy_mask)
3788 return -EOPNOTSUPP;
3789
3790 if (p_type == PP_PM_POLICY_NONE)
3791 return -EINVAL;
3792
3793 dpm_policy = smu_get_pm_policy(smu, p_type);
3794 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc)
3795 return -ENOENT;
3796
3797 if (!sysbuf)
3798 return -EINVAL;
3799
3800 smu_print_dpm_policy(dpm_policy, sysbuf, &offset);
3801
3802 return offset;
3803 }
3804
smu_get_pm_policy(struct smu_context * smu,enum pp_pm_policy p_type)3805 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu,
3806 enum pp_pm_policy p_type)
3807 {
3808 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3809 struct smu_dpm_policy_ctxt *policy_ctxt;
3810 int i;
3811
3812 policy_ctxt = dpm_ctxt->dpm_policies;
3813 if (!policy_ctxt)
3814 return NULL;
3815
3816 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) {
3817 if (policy_ctxt->policies[i].policy_type == p_type)
3818 return &policy_ctxt->policies[i];
3819 }
3820
3821 return NULL;
3822 }
3823
smu_set_pm_policy(struct smu_context * smu,enum pp_pm_policy p_type,int level)3824 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
3825 int level)
3826 {
3827 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3828 struct smu_dpm_policy *dpm_policy = NULL;
3829 struct smu_dpm_policy_ctxt *policy_ctxt;
3830 int ret = -EOPNOTSUPP;
3831
3832 policy_ctxt = dpm_ctxt->dpm_policies;
3833 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt ||
3834 !policy_ctxt->policy_mask)
3835 return ret;
3836
3837 if (level < 0 || level >= PP_POLICY_MAX_LEVELS)
3838 return -EINVAL;
3839
3840 dpm_policy = smu_get_pm_policy(smu, p_type);
3841
3842 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy)
3843 return ret;
3844
3845 if (dpm_policy->current_level == level)
3846 return 0;
3847
3848 ret = dpm_policy->set_policy(smu, level);
3849
3850 if (!ret)
3851 dpm_policy->current_level = level;
3852
3853 return ret;
3854 }
3855
smu_sys_get_temp_metrics(void * handle,enum smu_temp_metric_type type,void * table)3856 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table)
3857 {
3858 struct smu_context *smu = handle;
3859 struct smu_table_context *smu_table = &smu->smu_table;
3860 struct smu_table *tables = smu_table->tables;
3861 enum smu_table_id table_id;
3862
3863 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3864 return -EOPNOTSUPP;
3865
3866 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics)
3867 return -EOPNOTSUPP;
3868
3869 table_id = smu_metrics_get_temp_table_id(type);
3870
3871 if (table_id == SMU_TABLE_COUNT)
3872 return -EINVAL;
3873
3874 /* If the request is to get size alone, return the cached table size */
3875 if (!table && tables[table_id].cache.size)
3876 return tables[table_id].cache.size;
3877
3878 if (smu_table_cache_is_valid(&tables[table_id])) {
3879 memcpy(table, tables[table_id].cache.buffer,
3880 tables[table_id].cache.size);
3881 return tables[table_id].cache.size;
3882 }
3883
3884 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table);
3885 }
3886
smu_temp_metrics_is_supported(void * handle,enum smu_temp_metric_type type)3887 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type)
3888 {
3889 struct smu_context *smu = handle;
3890 bool ret = false;
3891
3892 if (!smu->pm_enabled)
3893 return false;
3894
3895 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported)
3896 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type);
3897
3898 return ret;
3899 }
3900
smu_sys_get_xcp_metrics(void * handle,int xcp_id,void * table)3901 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table)
3902 {
3903 struct smu_context *smu = handle;
3904
3905 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3906 return -EOPNOTSUPP;
3907
3908 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics)
3909 return -EOPNOTSUPP;
3910
3911 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table);
3912 }
3913
3914 static const struct amd_pm_funcs swsmu_pm_funcs = {
3915 /* export for sysfs */
3916 .set_fan_control_mode = smu_set_fan_control_mode,
3917 .get_fan_control_mode = smu_get_fan_control_mode,
3918 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3919 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3920 .force_clock_level = smu_force_ppclk_levels,
3921 .print_clock_levels = smu_print_ppclk_levels,
3922 .emit_clock_levels = smu_emit_ppclk_levels,
3923 .force_performance_level = smu_force_performance_level,
3924 .read_sensor = smu_read_sensor,
3925 .get_apu_thermal_limit = smu_get_apu_thermal_limit,
3926 .set_apu_thermal_limit = smu_set_apu_thermal_limit,
3927 .get_performance_level = smu_get_performance_level,
3928 .get_current_power_state = smu_get_current_power_state,
3929 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3930 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3931 .get_pp_num_states = smu_get_power_num_states,
3932 .get_pp_table = smu_sys_get_pp_table,
3933 .set_pp_table = smu_sys_set_pp_table,
3934 .switch_power_profile = smu_switch_power_profile,
3935 .pause_power_profile = smu_pause_power_profile,
3936 /* export to amdgpu */
3937 .dispatch_tasks = smu_handle_dpm_task,
3938 .load_firmware = smu_load_microcode,
3939 .set_powergating_by_smu = smu_dpm_set_power_gate,
3940 .set_power_limit = smu_set_power_limit,
3941 .get_power_limit = smu_get_power_limit,
3942 .get_power_profile_mode = smu_get_power_profile_mode,
3943 .set_power_profile_mode = smu_set_power_profile_mode,
3944 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3945 .set_mp1_state = smu_set_mp1_state,
3946 .gfx_state_change_set = smu_gfx_state_change_set,
3947 /* export to DC */
3948 .get_sclk = smu_get_sclk,
3949 .get_mclk = smu_get_mclk,
3950 .display_configuration_change = smu_display_configuration_change,
3951 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3952 .display_clock_voltage_request = smu_display_clock_voltage_request,
3953 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3954 .set_active_display_count = smu_set_display_count,
3955 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3956 .get_asic_baco_capability = smu_get_baco_capability,
3957 .set_asic_baco_state = smu_baco_set_state,
3958 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3959 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3960 .asic_reset_mode_2 = smu_mode2_reset,
3961 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3962 .set_df_cstate = smu_set_df_cstate,
3963 .set_xgmi_pstate = smu_set_xgmi_pstate,
3964 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3965 .get_pm_metrics = smu_sys_get_pm_metrics,
3966 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3967 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3968 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3969 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3970 .get_dpm_clock_table = smu_get_dpm_clock_table,
3971 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3972 .get_xcp_metrics = smu_sys_get_xcp_metrics,
3973 .get_temp_metrics = smu_sys_get_temp_metrics,
3974 .temp_metrics_is_supported = smu_temp_metrics_is_supported,
3975 };
3976
smu_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)3977 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3978 uint64_t event_arg)
3979 {
3980 int ret = -EINVAL;
3981
3982 if (smu->ppt_funcs->wait_for_event)
3983 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3984
3985 return ret;
3986 }
3987
smu_stb_collect_info(struct smu_context * smu,void * buf,uint32_t size)3988 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3989 {
3990
3991 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3992 return -EOPNOTSUPP;
3993
3994 /* Confirm the buffer allocated is of correct size */
3995 if (size != smu->stb_context.stb_buf_size)
3996 return -EINVAL;
3997
3998 /*
3999 * No need to lock smu mutex as we access STB directly through MMIO
4000 * and not going through SMU messaging route (for now at least).
4001 * For registers access rely on implementation internal locking.
4002 */
4003 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
4004 }
4005
4006 #if defined(CONFIG_DEBUG_FS)
4007
smu_stb_debugfs_open(struct inode * inode,struct file * filp)4008 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
4009 {
4010 struct amdgpu_device *adev = filp->f_inode->i_private;
4011 struct smu_context *smu = adev->powerplay.pp_handle;
4012 unsigned char *buf;
4013 int r;
4014
4015 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
4016 if (!buf)
4017 return -ENOMEM;
4018
4019 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
4020 if (r)
4021 goto out;
4022
4023 filp->private_data = buf;
4024
4025 return 0;
4026
4027 out:
4028 kvfree(buf);
4029 return r;
4030 }
4031
smu_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)4032 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
4033 loff_t *pos)
4034 {
4035 struct amdgpu_device *adev = filp->f_inode->i_private;
4036 struct smu_context *smu = adev->powerplay.pp_handle;
4037
4038
4039 if (!filp->private_data)
4040 return -EINVAL;
4041
4042 return simple_read_from_buffer(buf,
4043 size,
4044 pos, filp->private_data,
4045 smu->stb_context.stb_buf_size);
4046 }
4047
smu_stb_debugfs_release(struct inode * inode,struct file * filp)4048 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
4049 {
4050 kvfree(filp->private_data);
4051 filp->private_data = NULL;
4052
4053 return 0;
4054 }
4055
4056 /*
4057 * We have to define not only read method but also
4058 * open and release because .read takes up to PAGE_SIZE
4059 * data each time so and so is invoked multiple times.
4060 * We allocate the STB buffer in .open and release it
4061 * in .release
4062 */
4063 static const struct file_operations smu_stb_debugfs_fops = {
4064 .owner = THIS_MODULE,
4065 .open = smu_stb_debugfs_open,
4066 .read = smu_stb_debugfs_read,
4067 .release = smu_stb_debugfs_release,
4068 .llseek = default_llseek,
4069 };
4070
4071 #endif
4072
amdgpu_smu_stb_debug_fs_init(struct amdgpu_device * adev)4073 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
4074 {
4075 #if defined(CONFIG_DEBUG_FS)
4076
4077 struct smu_context *smu = adev->powerplay.pp_handle;
4078
4079 if (!smu || (!smu->stb_context.stb_buf_size))
4080 return;
4081
4082 debugfs_create_file_size("amdgpu_smu_stb_dump",
4083 S_IRUSR,
4084 adev_to_drm(adev)->primary->debugfs_root,
4085 adev,
4086 &smu_stb_debugfs_fops,
4087 smu->stb_context.stb_buf_size);
4088 #endif
4089 }
4090
smu_send_hbm_bad_pages_num(struct smu_context * smu,uint32_t size)4091 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
4092 {
4093 int ret = 0;
4094
4095 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
4096 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
4097
4098 return ret;
4099 }
4100
smu_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)4101 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
4102 {
4103 int ret = 0;
4104
4105 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
4106 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
4107
4108 return ret;
4109 }
4110
smu_send_rma_reason(struct smu_context * smu)4111 int smu_send_rma_reason(struct smu_context *smu)
4112 {
4113 int ret = 0;
4114
4115 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
4116 ret = smu->ppt_funcs->send_rma_reason(smu);
4117
4118 return ret;
4119 }
4120
4121 /**
4122 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU
4123 * @smu: smu_context pointer
4124 *
4125 * This function checks if the SMU supports resetting the SDMA engine.
4126 * It returns true if supported, false otherwise.
4127 */
smu_reset_sdma_is_supported(struct smu_context * smu)4128 bool smu_reset_sdma_is_supported(struct smu_context *smu)
4129 {
4130 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET);
4131 }
4132
smu_reset_sdma(struct smu_context * smu,uint32_t inst_mask)4133 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
4134 {
4135 int ret = 0;
4136
4137 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma)
4138 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask);
4139
4140 return ret;
4141 }
4142
smu_reset_vcn_is_supported(struct smu_context * smu)4143 bool smu_reset_vcn_is_supported(struct smu_context *smu)
4144 {
4145 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET);
4146 }
4147
smu_reset_vcn(struct smu_context * smu,uint32_t inst_mask)4148 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
4149 {
4150 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn)
4151 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask);
4152
4153 return 0;
4154 }
4155