1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2020, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/acpi.h> 14 #include <linux/array_size.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/dmi.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/limits.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/rtc.h> 27 #include <linux/serio.h> 28 #include <linux/suspend.h> 29 #include <linux/seq_file.h> 30 #include <linux/uaccess.h> 31 32 #include <asm/amd/node.h> 33 34 #include "pmc.h" 35 36 static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = { 37 {"DISPLAY", BIT(0)}, 38 {"CPU", BIT(1)}, 39 {"GFX", BIT(2)}, 40 {"VDD", BIT(3)}, 41 {"VDD_CCX", BIT(4)}, 42 {"ACP", BIT(5)}, 43 {"VCN_0", BIT(6)}, 44 {"VCN_1", BIT(7)}, 45 {"ISP", BIT(8)}, 46 {"NBIO", BIT(9)}, 47 {"DF", BIT(10)}, 48 {"USB3_0", BIT(11)}, 49 {"USB3_1", BIT(12)}, 50 {"LAPIC", BIT(13)}, 51 {"USB3_2", BIT(14)}, 52 {"USB4_RT0", BIT(15)}, 53 {"USB4_RT1", BIT(16)}, 54 {"USB4_0", BIT(17)}, 55 {"USB4_1", BIT(18)}, 56 {"MPM", BIT(19)}, 57 {"JPEG_0", BIT(20)}, 58 {"JPEG_1", BIT(21)}, 59 {"IPU", BIT(22)}, 60 {"UMSCH", BIT(23)}, 61 {"VPE", BIT(24)}, 62 }; 63 64 static const struct amd_pmc_bit_map soc15_ip_blk[] = { 65 {"DISPLAY", BIT(0)}, 66 {"CPU", BIT(1)}, 67 {"GFX", BIT(2)}, 68 {"VDD", BIT(3)}, 69 {"ACP", BIT(4)}, 70 {"VCN", BIT(5)}, 71 {"ISP", BIT(6)}, 72 {"NBIO", BIT(7)}, 73 {"DF", BIT(8)}, 74 {"USB3_0", BIT(9)}, 75 {"USB3_1", BIT(10)}, 76 {"LAPIC", BIT(11)}, 77 {"USB3_2", BIT(12)}, 78 {"USB3_3", BIT(13)}, 79 {"USB3_4", BIT(14)}, 80 {"USB4_0", BIT(15)}, 81 {"USB4_1", BIT(16)}, 82 {"MPM", BIT(17)}, 83 {"JPEG", BIT(18)}, 84 {"IPU", BIT(19)}, 85 {"UMSCH", BIT(20)}, 86 {"VPE", BIT(21)}, 87 }; 88 89 /* CPU info structures for different SoC variants */ 90 static const struct amd_pmc_cpu_info amd_pco_cpu_info = { 91 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 92 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 93 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 94 .num_ips = 12, 95 .ips_ptr = soc15_ip_blk, 96 .os_hint = MSG_OS_HINT_PCO, 97 }; 98 99 static const struct amd_pmc_cpu_info amd_czn_cpu_info = { 100 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 101 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 102 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 103 .num_ips = 12, 104 .scratch_reg = AMD_PMC_SCRATCH_REG_CZN, 105 .ips_ptr = soc15_ip_blk, 106 .os_hint = MSG_OS_HINT_RN, 107 }; 108 109 static const struct amd_pmc_cpu_info amd_vg_cpu_info = { 110 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 111 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 112 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 113 .num_ips = 12, 114 .ips_ptr = soc15_ip_blk, 115 .os_hint = MSG_OS_HINT_RN, 116 }; 117 118 static const struct amd_pmc_cpu_info amd_yc_cpu_info = { 119 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 120 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 121 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 122 .num_ips = 12, 123 .scratch_reg = AMD_PMC_SCRATCH_REG_YC, 124 .ips_ptr = soc15_ip_blk, 125 .os_hint = MSG_OS_HINT_RN, 126 }; 127 128 static const struct amd_pmc_cpu_info amd_ps_cpu_info = { 129 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 130 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 131 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 132 .num_ips = 21, 133 .scratch_reg = AMD_PMC_SCRATCH_REG_YC, 134 .ips_ptr = soc15_ip_blk, 135 .os_hint = MSG_OS_HINT_RN, 136 }; 137 138 static const struct amd_pmc_cpu_info amd_1ah_cpu_info = { 139 .smu_msg = AMD_PMC_REGISTER_MSG_1AH_20H, 140 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 141 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 142 .num_ips = ARRAY_SIZE(soc15_ip_blk), 143 .scratch_reg = AMD_PMC_SCRATCH_REG_1AH, 144 .ips_ptr = soc15_ip_blk, 145 .os_hint = MSG_OS_HINT_RN, 146 }; 147 148 static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = { 149 .smu_msg = AMD_PMC_REGISTER_MSG_1AH_20H, 150 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 151 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 152 .num_ips = ARRAY_SIZE(soc15_ip_blk_v2), 153 .scratch_reg = AMD_PMC_SCRATCH_REG_1AH, 154 .ips_ptr = soc15_ip_blk_v2, 155 .os_hint = MSG_OS_HINT_RN, 156 }; 157 158 static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = { 159 .smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H, 160 .smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H, 161 .smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H, 162 .num_ips = ARRAY_SIZE(soc15_ip_blk), 163 .scratch_reg = AMD_PMC_SCRATCH_REG_1AH, 164 .ips_ptr = soc15_ip_blk, 165 .os_hint = MSG_OS_HINT_RN, 166 }; 167 168 static const struct pci_device_id pmc_pci_ids[] = { 169 { PCI_DEVICE_DATA(AMD, CPU_ID_PCO, &amd_pco_cpu_info) }, 170 { PCI_DEVICE_DATA(AMD, CPU_ID_CZN, &amd_czn_cpu_info) }, 171 { PCI_DEVICE_DATA(AMD, CPU_ID_VG, &amd_vg_cpu_info) }, 172 { PCI_DEVICE_DATA(AMD, CPU_ID_YC, &amd_yc_cpu_info) }, 173 { PCI_DEVICE_DATA(AMD, CPU_ID_CB, &amd_yc_cpu_info) }, 174 { PCI_DEVICE_DATA(AMD, CPU_ID_PS, &amd_ps_cpu_info) }, 175 { PCI_DEVICE_DATA(AMD, CPU_ID_SP, NULL) }, 176 { PCI_DEVICE_DATA(AMD, CPU_ID_SHP, NULL) }, 177 { PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, NULL) }, 178 { PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, NULL) }, 179 { PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_1ah_m80_cpu_info) }, 180 { } 181 }; 182 183 static bool disable_workarounds; 184 module_param(disable_workarounds, bool, 0644); 185 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); 186 187 static int delay_suspend = -1; 188 module_param(delay_suspend, int, 0644); 189 MODULE_PARM_DESC(delay_suspend, 190 "Delays s2idle by 2.5 seconds to work around buggy ECs, often causing keyboard issues after suspend. 0: don't delay, 1: do delay, -1 (default): let amd_pmc decide. If you need this please report this to: platform-driver-x86@vger.kernel.org"); 191 192 static struct amd_pmc_dev pmc; 193 194 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) 195 { 196 return ioread32(dev->regbase + reg_offset); 197 } 198 199 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) 200 { 201 iowrite32(val, dev->regbase + reg_offset); 202 } 203 204 static int amd_pmc_set_cpu_info(struct amd_pmc_dev *dev, struct pci_dev *rdev) 205 { 206 const struct pci_device_id *id; 207 208 id = pci_match_id(pmc_pci_ids, rdev); 209 if (!id) 210 return -ENODEV; 211 212 dev->cpu_id = rdev->device; 213 214 if (id->driver_data) { 215 dev->cpu_info = (const struct amd_pmc_cpu_info *)id->driver_data; 216 return 0; 217 } 218 219 /* Special case: 1Ah M20H/M60H needs x86_model detection */ 220 switch (dev->cpu_id) { 221 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 222 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 223 if (boot_cpu_data.x86_model == 0x70) 224 dev->cpu_info = &amd_1ah_m70_cpu_info; 225 else 226 dev->cpu_info = &amd_1ah_cpu_info; 227 break; 228 case AMD_CPU_ID_SP: 229 case AMD_CPU_ID_SHP: 230 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n"); 231 return -ENODEV; 232 default: 233 dev_err(dev->dev, "Unknown CPU ID: 0x%x\n", dev->cpu_id); 234 return -ENODEV; 235 } 236 237 return 0; 238 } 239 240 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) 241 { 242 if (dev->cpu_id == AMD_CPU_ID_PCO) { 243 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); 244 return -EINVAL; 245 } 246 247 /* Get Active devices list from SMU */ 248 if (!dev->active_ips) 249 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true); 250 251 /* Get dram address */ 252 if (!dev->smu_virt_addr) { 253 u32 phys_addr_low, phys_addr_hi; 254 u64 smu_phys_addr; 255 256 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true); 257 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true); 258 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 259 260 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, 261 sizeof(struct smu_metrics)); 262 if (!dev->smu_virt_addr) 263 return -ENOMEM; 264 } 265 266 memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics)); 267 268 /* Start the logging */ 269 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false); 270 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false); 271 272 return 0; 273 } 274 275 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) 276 { 277 int rc; 278 279 if (!pdev->smu_virt_addr) { 280 rc = amd_pmc_setup_smu_logging(pdev); 281 if (rc) 282 return rc; 283 } 284 285 if (pdev->cpu_id == AMD_CPU_ID_PCO) 286 return -ENODEV; 287 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics)); 288 return 0; 289 } 290 291 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) 292 { 293 struct smu_metrics table; 294 295 if (get_metrics_table(pdev, &table)) 296 return; 297 298 if (!table.s0i3_last_entry_status) 299 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n"); 300 pm_report_hw_sleep_time(table.s0i3_last_entry_status ? 301 table.timein_s0i3_lastcapture : 0); 302 } 303 304 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) 305 { 306 int rc; 307 u32 val; 308 309 if (dev->cpu_id == AMD_CPU_ID_PCO) 310 return -ENODEV; 311 312 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true); 313 if (rc) 314 return rc; 315 316 dev->smu_program = (val >> 24) & GENMASK(7, 0); 317 dev->major = (val >> 16) & GENMASK(7, 0); 318 dev->minor = (val >> 8) & GENMASK(7, 0); 319 dev->rev = (val >> 0) & GENMASK(7, 0); 320 321 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", 322 dev->smu_program, dev->major, dev->minor, dev->rev); 323 324 return 0; 325 } 326 327 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, 328 char *buf) 329 { 330 struct amd_pmc_dev *dev = dev_get_drvdata(d); 331 int rc; 332 333 if (!dev->major) { 334 rc = amd_pmc_get_smu_version(dev); 335 if (rc) 336 return rc; 337 } 338 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev); 339 } 340 341 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, 342 char *buf) 343 { 344 struct amd_pmc_dev *dev = dev_get_drvdata(d); 345 int rc; 346 347 if (!dev->major) { 348 rc = amd_pmc_get_smu_version(dev); 349 if (rc) 350 return rc; 351 } 352 return sysfs_emit(buf, "%u\n", dev->smu_program); 353 } 354 355 static DEVICE_ATTR_RO(smu_fw_version); 356 static DEVICE_ATTR_RO(smu_program); 357 358 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 359 { 360 struct device *dev = kobj_to_dev(kobj); 361 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 362 363 if (pdev->cpu_id == AMD_CPU_ID_PCO) 364 return 0; 365 return 0444; 366 } 367 368 static struct attribute *pmc_attrs[] = { 369 &dev_attr_smu_fw_version.attr, 370 &dev_attr_smu_program.attr, 371 NULL, 372 }; 373 374 static struct attribute_group pmc_attr_group = { 375 .attrs = pmc_attrs, 376 .is_visible = pmc_attr_is_visible, 377 }; 378 379 static const struct attribute_group *pmc_groups[] = { 380 &pmc_attr_group, 381 NULL, 382 }; 383 384 static int smu_fw_info_show(struct seq_file *s, void *unused) 385 { 386 struct amd_pmc_dev *dev = s->private; 387 struct smu_metrics table; 388 int idx; 389 390 if (get_metrics_table(dev, &table)) 391 return -EINVAL; 392 393 seq_puts(s, "\n=== SMU Statistics ===\n"); 394 seq_printf(s, "Table Version: %d\n", table.table_version); 395 seq_printf(s, "Hint Count: %d\n", table.hint_count); 396 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : 397 "Unknown/Fail"); 398 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); 399 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); 400 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", 401 table.timeto_resume_to_os_lastcapture); 402 403 seq_puts(s, "\n=== Active time (in us) ===\n"); 404 for (idx = 0 ; idx < dev->cpu_info->num_ips ; idx++) { 405 if (dev->cpu_info->ips_ptr[idx].bit_mask & dev->active_ips) 406 seq_printf(s, "%-8s : %lld\n", dev->cpu_info->ips_ptr[idx].name, 407 table.timecondition_notmet_lastcapture[idx]); 408 } 409 410 return 0; 411 } 412 DEFINE_SHOW_ATTRIBUTE(smu_fw_info); 413 414 static int s0ix_stats_show(struct seq_file *s, void *unused) 415 { 416 struct amd_pmc_dev *dev = s->private; 417 u64 entry_time, exit_time, residency; 418 419 /* Use FCH registers to get the S0ix stats */ 420 if (!dev->fch_virt_addr) { 421 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW; 422 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; 423 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 424 425 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); 426 if (!dev->fch_virt_addr) 427 return -ENOMEM; 428 } 429 430 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); 431 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); 432 433 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); 434 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); 435 436 /* It's in 48MHz. We need to convert it */ 437 residency = exit_time - entry_time; 438 do_div(residency, 48); 439 440 seq_puts(s, "=== S0ix statistics ===\n"); 441 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); 442 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); 443 seq_printf(s, "Residency Time: %lld\n", residency); 444 445 return 0; 446 } 447 DEFINE_SHOW_ATTRIBUTE(s0ix_stats); 448 449 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, 450 struct seq_file *s) 451 { 452 u32 val; 453 int rc; 454 455 /* we haven't yet read SMU version */ 456 if (pdev->cpu_id == AMD_CPU_ID_CZN) { 457 if (!pdev->major) { 458 rc = amd_pmc_get_smu_version(pdev); 459 if (rc) 460 return rc; 461 } 462 if (!(pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))) 463 return -EINVAL; 464 } 465 466 if (!pdev->cpu_info->scratch_reg) 467 return -EINVAL; 468 469 val = amd_pmc_reg_read(pdev, pdev->cpu_info->scratch_reg); 470 471 if (dev) 472 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); 473 474 if (s) 475 seq_printf(s, "SMU idlemask : 0x%x\n", val); 476 477 return 0; 478 } 479 480 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) 481 { 482 return amd_pmc_idlemask_read(s->private, NULL, s); 483 } 484 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); 485 486 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 487 { 488 debugfs_remove_recursive(dev->dbgfs_dir); 489 } 490 491 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) 492 { 493 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); 494 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, 495 &smu_fw_info_fops); 496 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, 497 &s0ix_stats_fops); 498 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, 499 &amd_pmc_idlemask_fops); 500 } 501 502 static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev) 503 { 504 switch (dev->msg_port) { 505 case MSG_PORT_PMC: 506 return "PMC"; 507 case MSG_PORT_S2D: 508 return "S2D"; 509 default: 510 return "Invalid message port"; 511 } 512 } 513 514 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 515 { 516 u32 value, message, argument, response; 517 518 if (dev->msg_port == MSG_PORT_S2D) { 519 message = dev->stb_arg.msg; 520 argument = dev->stb_arg.arg; 521 response = dev->stb_arg.resp; 522 } else { 523 message = dev->cpu_info->smu_msg; 524 argument = dev->cpu_info->smu_arg; 525 response = dev->cpu_info->smu_rsp; 526 } 527 528 value = amd_pmc_reg_read(dev, response); 529 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value); 530 531 value = amd_pmc_reg_read(dev, argument); 532 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value); 533 534 value = amd_pmc_reg_read(dev, message); 535 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value); 536 } 537 538 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) 539 { 540 int rc; 541 u32 val, message, argument, response; 542 543 guard(mutex)(&dev->lock); 544 545 if (dev->msg_port == MSG_PORT_S2D) { 546 message = dev->stb_arg.msg; 547 argument = dev->stb_arg.arg; 548 response = dev->stb_arg.resp; 549 } else { 550 message = dev->cpu_info->smu_msg; 551 argument = dev->cpu_info->smu_arg; 552 response = dev->cpu_info->smu_rsp; 553 } 554 555 /* Wait until we get a valid response */ 556 rc = readx_poll_timeout(ioread32, dev->regbase + response, 557 val, val != 0, PMC_MSG_DELAY_MIN_US, 558 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 559 if (rc) { 560 dev_err(dev->dev, "failed to talk to SMU\n"); 561 return rc; 562 } 563 564 /* Write zero to response register */ 565 amd_pmc_reg_write(dev, response, 0); 566 567 /* Write argument into response register */ 568 amd_pmc_reg_write(dev, argument, arg); 569 570 /* Write message ID to message ID register */ 571 amd_pmc_reg_write(dev, message, msg); 572 573 /* Wait until we get a valid response */ 574 rc = readx_poll_timeout(ioread32, dev->regbase + response, 575 val, val != 0, PMC_MSG_DELAY_MIN_US, 576 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 577 if (rc) { 578 dev_err(dev->dev, "SMU response timed out\n"); 579 return rc; 580 } 581 582 switch (val) { 583 case AMD_PMC_RESULT_OK: 584 if (ret) { 585 /* PMFW may take longer time to return back the data */ 586 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 587 *data = amd_pmc_reg_read(dev, argument); 588 } 589 break; 590 case AMD_PMC_RESULT_CMD_REJECT_BUSY: 591 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 592 rc = -EBUSY; 593 break; 594 case AMD_PMC_RESULT_CMD_UNKNOWN: 595 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 596 rc = -EINVAL; 597 break; 598 case AMD_PMC_RESULT_CMD_REJECT_PREREQ: 599 case AMD_PMC_RESULT_FAILED: 600 default: 601 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 602 rc = -EIO; 603 break; 604 } 605 606 amd_pmc_dump_registers(dev); 607 return rc; 608 } 609 610 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) 611 { 612 struct device *d; 613 614 d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); 615 if (!d) 616 return 0; 617 if (device_may_wakeup(d)) { 618 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n"); 619 disable_irq_wake(1); 620 device_set_wakeup_enable(d, false); 621 } 622 put_device(d); 623 624 return 0; 625 } 626 627 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 628 { 629 struct rtc_device *rtc_device; 630 time64_t then, now, duration; 631 struct rtc_wkalrm alarm; 632 struct rtc_time tm; 633 int rc; 634 635 /* we haven't yet read SMU version */ 636 if (!pdev->major) { 637 rc = amd_pmc_get_smu_version(pdev); 638 if (rc) 639 return rc; 640 } 641 642 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) 643 return 0; 644 645 rtc_device = rtc_class_open("rtc0"); 646 if (!rtc_device) 647 return 0; 648 rc = rtc_read_alarm(rtc_device, &alarm); 649 if (rc) 650 return rc; 651 if (!alarm.enabled) { 652 dev_dbg(pdev->dev, "alarm not enabled\n"); 653 return 0; 654 } 655 rc = rtc_read_time(rtc_device, &tm); 656 if (rc) 657 return rc; 658 then = rtc_tm_to_time64(&alarm.time); 659 now = rtc_tm_to_time64(&tm); 660 duration = then-now; 661 662 /* in the past */ 663 if (then < now) 664 return 0; 665 666 /* will be stored in upper 16 bits of s0i3 hint argument, 667 * so timer wakeup from s0i3 is limited to ~18 hours or less 668 */ 669 if (duration <= 4 || duration > U16_MAX) 670 return -EINVAL; 671 672 *arg |= (duration << 16); 673 rc = rtc_alarm_irq_enable(rtc_device, 0); 674 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration); 675 676 return rc; 677 } 678 679 static bool amd_pmc_intermediate_wakeup_need_delay(struct amd_pmc_dev *pdev) 680 { 681 /* 682 * Starting a new HW sleep cycle right after waking from one 683 * can cause electrical problems triggering the over voltage protection. 684 * That is avoided by delaying the next suspend a bit, see also 685 * https://lore.kernel.org/all/20250414162446.3853194-1-superm1@kernel.org/ 686 */ 687 struct smu_metrics table; 688 689 return get_metrics_table(pdev, &table) == 0 && table.s0i3_last_entry_status; 690 } 691 692 static bool amd_pmc_want_suspend_delay(struct amd_pmc_dev *pdev) 693 { 694 /* 695 * intermediate_wakeup implies that the machine didn't get to deepest sleep 696 * state before - otherwise this function isn't called in amd_pmc_s2idle_check() 697 * because amd_pmc_intermediate_wakeup_need_delay() returns true first. 698 * On some IdeaPads that happens when charging, because the EC seems 699 * to send lots of messages then that wake the machine. 700 * 701 * But even in that case, the sleep here is necessary (on those IdeaPads), 702 * otherwise they wake up completely (resume) after a few seconds. 703 * So this variable is only used to avoid spamming dmesg on each 704 * intermediate wakeup. 705 */ 706 bool intermediate_wakeup = !pdev->is_first_check_after_suspend; 707 708 /* 709 * Some Lenovo Laptops (like different IdeaPad 3 Slims) need some 710 * me-time before sleeping or they get uncooperative after waking 711 * up and don't send events for keyboard and lid switch anymore. 712 * 713 * Unfortunately this doesn't entirely fix the problem: It can still 714 * happen when resuming with a timer (wakealarm), but at least the 715 * more common usecases (wakeup by opening lid or pressing a key) 716 * work fine with this workaround. 717 * 718 * See https://bugzilla.kernel.org/show_bug.cgi?id=221383 719 */ 720 if (amd_pmc_quirk_need_suspend_delay(pdev)) { 721 /* 722 * delay_suspend=1 force-enables this, otherwise it can be 723 * disabled with disable_workarounds or delay_suspend=0 724 */ 725 if (delay_suspend == 1 || (delay_suspend == -1 && !disable_workarounds)) { 726 if (!intermediate_wakeup) 727 dev_info(pdev->dev, "Delaying suspend by 2.5s to avoid platform bug\n"); 728 return true; 729 } 730 if (!intermediate_wakeup) 731 dev_info(pdev->dev, "Not delaying suspend because of module parameter, even though your device is assumed to need it!\n"); 732 } else if (delay_suspend == 1) { 733 if (!intermediate_wakeup) 734 dev_info(pdev->dev, "Delaying suspend by 2.5s because delay_suspend=1. If this solves problems on your machine, please report this whole line to: platform-driver-x86@vger.kernel.org so it can be automatically detected as affected in the future. System Vendor: \"%s\" Product Name: \"%s\" Product Family: \"%s\" Board Vendor: \"%s\" Board Name: \"%s\"\n", 735 dmi_get_system_info(DMI_SYS_VENDOR), 736 dmi_get_system_info(DMI_PRODUCT_NAME), 737 dmi_get_system_info(DMI_PRODUCT_FAMILY), 738 dmi_get_system_info(DMI_BOARD_VENDOR), 739 dmi_get_system_info(DMI_BOARD_NAME)); 740 return true; 741 } 742 return false; 743 } 744 745 static void amd_pmc_s2idle_prepare(void) 746 { 747 struct amd_pmc_dev *pdev = &pmc; 748 int rc; 749 u32 arg = 1; 750 751 /* Reset this variable because this is a fresh suspend */ 752 pdev->is_first_check_after_suspend = true; 753 754 /* Reset and Start SMU logging - to monitor the s0i3 stats */ 755 amd_pmc_setup_smu_logging(pdev); 756 757 /* Activate CZN specific platform bug workarounds */ 758 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { 759 rc = amd_pmc_verify_czn_rtc(pdev, &arg); 760 if (rc) { 761 dev_err(pdev->dev, "failed to set RTC: %d\n", rc); 762 return; 763 } 764 } 765 766 rc = amd_pmc_send_cmd(pdev, arg, NULL, pdev->cpu_info->os_hint, false); 767 if (rc) { 768 dev_err(pdev->dev, "suspend failed: %d\n", rc); 769 return; 770 } 771 772 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE); 773 if (rc) 774 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 775 } 776 777 static void amd_pmc_s2idle_check(void) 778 { 779 struct amd_pmc_dev *pdev = &pmc; 780 int rc; 781 782 if (amd_pmc_intermediate_wakeup_need_delay(pdev) || 783 amd_pmc_want_suspend_delay(pdev)) 784 msleep(2500); 785 786 /* Dump the IdleMask before we add to the STB */ 787 amd_pmc_idlemask_read(pdev, pdev->dev, NULL); 788 789 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK); 790 if (rc) 791 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 792 793 /* remember that first check after suspend is done (until next prepare) */ 794 pdev->is_first_check_after_suspend = false; 795 } 796 797 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) 798 { 799 if (pdev->cpu_id == AMD_CPU_ID_PCO) 800 return -ENODEV; 801 802 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false); 803 } 804 805 static void amd_pmc_s2idle_restore(void) 806 { 807 struct amd_pmc_dev *pdev = &pmc; 808 int rc; 809 810 rc = amd_pmc_send_cmd(pdev, 0, NULL, pdev->cpu_info->os_hint, false); 811 if (rc) 812 dev_err(pdev->dev, "resume failed: %d\n", rc); 813 814 /* Let SMU know that we are looking for stats */ 815 amd_pmc_dump_data(pdev); 816 817 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE); 818 if (rc) 819 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 820 821 /* Notify on failed entry */ 822 amd_pmc_validate_deepest(pdev); 823 824 amd_pmc_process_restore_quirks(pdev); 825 } 826 827 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = { 828 .prepare = amd_pmc_s2idle_prepare, 829 .check = amd_pmc_s2idle_check, 830 .restore = amd_pmc_s2idle_restore, 831 }; 832 833 static int amd_pmc_suspend_handler(struct device *dev) 834 { 835 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 836 int rc; 837 838 /* 839 * Must be called only from the same set of dev_pm_ops handlers 840 * as i8042_pm_suspend() is called: currently just from .suspend. 841 */ 842 if (pdev->disable_8042_wakeup && !disable_workarounds) { 843 rc = amd_pmc_wa_irq1(pdev); 844 if (rc) { 845 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc); 846 return rc; 847 } 848 } 849 850 return 0; 851 } 852 853 static const struct dev_pm_ops amd_pmc_pm = { 854 .suspend = amd_pmc_suspend_handler, 855 }; 856 857 static int amd_pmc_probe(struct platform_device *pdev) 858 { 859 struct amd_pmc_dev *dev = &pmc; 860 struct pci_dev *rdev; 861 u32 base_addr_lo, base_addr_hi; 862 u64 base_addr; 863 int err; 864 u32 val; 865 866 dev->dev = &pdev->dev; 867 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 868 if (!rdev) { 869 err = -ENODEV; 870 goto err_pci_dev_put; 871 } 872 873 err = amd_pmc_set_cpu_info(dev, rdev); 874 if (err) 875 goto err_pci_dev_put; 876 877 dev->rdev = rdev; 878 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); 879 if (err) { 880 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO); 881 err = pcibios_err_to_errno(err); 882 goto err_pci_dev_put; 883 } 884 885 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; 886 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val); 887 if (err) { 888 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI); 889 err = pcibios_err_to_errno(err); 890 goto err_pci_dev_put; 891 } 892 893 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; 894 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 895 896 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, 897 AMD_PMC_MAPPING_SIZE); 898 if (!dev->regbase) { 899 err = -ENOMEM; 900 goto err_pci_dev_put; 901 } 902 903 err = devm_mutex_init(dev->dev, &dev->lock); 904 if (err) 905 goto err_pci_dev_put; 906 907 platform_set_drvdata(pdev, dev); 908 if (IS_ENABLED(CONFIG_SUSPEND)) { 909 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops); 910 if (err) 911 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n"); 912 if (!disable_workarounds) 913 amd_pmc_quirks_init(dev); 914 } 915 916 amd_pmc_dbgfs_register(dev); 917 err = amd_stb_s2d_init(dev); 918 if (err) 919 goto err_pci_dev_put; 920 921 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 922 amd_mp2_stb_init(dev); 923 pm_report_max_hw_sleep(U64_MAX); 924 return 0; 925 926 err_pci_dev_put: 927 pci_dev_put(rdev); 928 return err; 929 } 930 931 static void amd_pmc_remove(struct platform_device *pdev) 932 { 933 struct amd_pmc_dev *dev = platform_get_drvdata(pdev); 934 935 if (IS_ENABLED(CONFIG_SUSPEND)) 936 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); 937 amd_pmc_dbgfs_unregister(dev); 938 pci_dev_put(dev->rdev); 939 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 940 amd_mp2_stb_deinit(dev); 941 } 942 943 static const struct acpi_device_id amd_pmc_acpi_ids[] = { 944 {"AMDI0005", 0}, 945 {"AMDI0006", 0}, 946 {"AMDI0007", 0}, 947 {"AMDI0008", 0}, 948 {"AMDI0009", 0}, 949 {"AMDI000A", 0}, 950 {"AMDI000B", 0}, 951 {"AMDI000C", 0}, 952 {"AMD0004", 0}, 953 {"AMD0005", 0}, 954 { } 955 }; 956 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); 957 958 static struct platform_driver amd_pmc_driver = { 959 .driver = { 960 .name = "amd_pmc", 961 .acpi_match_table = amd_pmc_acpi_ids, 962 .dev_groups = pmc_groups, 963 .pm = pm_sleep_ptr(&amd_pmc_pm), 964 }, 965 .probe = amd_pmc_probe, 966 .remove = amd_pmc_remove, 967 }; 968 module_platform_driver(amd_pmc_driver); 969 970 MODULE_LICENSE("GPL v2"); 971 MODULE_DESCRIPTION("AMD PMC Driver"); 972