1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "pp_debug.h"
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
28 #include "atombios.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
31 #include "smumgr.h"
32 #include "hwmgr.h"
33 #include "hardwaremanager.h"
34 #include "rv_ppsmc.h"
35 #include "smu10_hwmgr.h"
36 #include "power_state.h"
37 #include "soc15_common.h"
38 #include "smu10.h"
39 #include "asic_reg/pwr/pwr_10_0_offset.h"
40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
41
42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
43 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
44 #define SCLK_MIN_DIV_INTV_SHIFT 12
45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
46 #define SMC_RAM_END 0x40000
47
48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
49
50
smu10_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock_req)51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
52 struct pp_display_clock_request *clock_req)
53 {
54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
55 enum amd_pp_clock_type clk_type = clock_req->clock_type;
56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
57 PPSMC_Msg msg;
58
59 switch (clk_type) {
60 case amd_pp_dcf_clock:
61 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
62 return 0;
63 msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
64 smu10_data->dcf_actual_hard_min_freq = clk_freq;
65 break;
66 case amd_pp_soc_clock:
67 msg = PPSMC_MSG_SetHardMinSocclkByFreq;
68 break;
69 case amd_pp_f_clock:
70 if (clk_freq == smu10_data->f_actual_hard_min_freq)
71 return 0;
72 smu10_data->f_actual_hard_min_freq = clk_freq;
73 msg = PPSMC_MSG_SetHardMinFclkByFreq;
74 break;
75 default:
76 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
77 return -EINVAL;
78 }
79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
80
81 return 0;
82 }
83
cast_smu10_ps(struct pp_hw_power_state * hw_ps)84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
85 {
86 if (SMU10_Magic != hw_ps->magic)
87 return NULL;
88
89 return (struct smu10_power_state *)hw_ps;
90 }
91
cast_const_smu10_ps(const struct pp_hw_power_state * hw_ps)92 static const struct smu10_power_state *cast_const_smu10_ps(
93 const struct pp_hw_power_state *hw_ps)
94 {
95 if (SMU10_Magic != hw_ps->magic)
96 return NULL;
97
98 return (struct smu10_power_state *)hw_ps;
99 }
100
smu10_initialize_dpm_defaults(struct pp_hwmgr * hwmgr)101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
102 {
103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
104
105 smu10_data->dce_slow_sclk_threshold = 30000;
106 smu10_data->thermal_auto_throttling_treshold = 0;
107 smu10_data->is_nb_dpm_enabled = 1;
108 smu10_data->dpm_flags = 1;
109 smu10_data->need_min_deep_sleep_dcefclk = true;
110 smu10_data->num_active_display = 0;
111 smu10_data->deep_sleep_dcefclk = 0;
112
113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
114 PHM_PlatformCaps_SclkDeepSleep);
115
116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
117 PHM_PlatformCaps_SclkThrottleLowNotification);
118
119 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
120 PHM_PlatformCaps_PowerPlaySupport);
121 return 0;
122 }
123
smu10_construct_max_power_limits_table(struct pp_hwmgr * hwmgr,struct phm_clock_and_voltage_limits * table)124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
125 struct phm_clock_and_voltage_limits *table)
126 {
127 return 0;
128 }
129
smu10_init_dynamic_state_adjustment_rule_settings(struct pp_hwmgr * hwmgr)130 static int smu10_init_dynamic_state_adjustment_rule_settings(
131 struct pp_hwmgr *hwmgr)
132 {
133 int count = 8;
134 struct phm_clock_voltage_dependency_table *table_clk_vlt;
135
136 table_clk_vlt = kzalloc_flex(*table_clk_vlt, entries, count);
137
138 if (NULL == table_clk_vlt) {
139 pr_err("Can not allocate memory!\n");
140 return -ENOMEM;
141 }
142
143 table_clk_vlt->count = count;
144 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
145 table_clk_vlt->entries[0].v = 0;
146 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
147 table_clk_vlt->entries[1].v = 1;
148 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
149 table_clk_vlt->entries[2].v = 2;
150 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
151 table_clk_vlt->entries[3].v = 3;
152 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
153 table_clk_vlt->entries[4].v = 4;
154 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
155 table_clk_vlt->entries[5].v = 5;
156 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
157 table_clk_vlt->entries[6].v = 6;
158 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
159 table_clk_vlt->entries[7].v = 7;
160 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
161
162 return 0;
163 }
164
smu10_get_system_info_data(struct pp_hwmgr * hwmgr)165 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
166 {
167 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
168
169 smu10_data->sys_info.htc_hyst_lmt = 5;
170 smu10_data->sys_info.htc_tmp_lmt = 203;
171
172 if (smu10_data->thermal_auto_throttling_treshold == 0)
173 smu10_data->thermal_auto_throttling_treshold = 203;
174
175 smu10_construct_max_power_limits_table (hwmgr,
176 &hwmgr->dyn_state.max_clock_voltage_on_ac);
177
178 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
179
180 return 0;
181 }
182
smu10_construct_boot_state(struct pp_hwmgr * hwmgr)183 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
184 {
185 return 0;
186 }
187
smu10_set_clock_limit(struct pp_hwmgr * hwmgr,const void * input)188 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
189 {
190 struct PP_Clocks clocks = {0};
191 struct pp_display_clock_request clock_req;
192
193 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
194 clock_req.clock_type = amd_pp_dcf_clock;
195 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
196
197 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
198 "Attempt to set DCF Clock Failed!", return -EINVAL);
199
200 return 0;
201 }
202
smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr * hwmgr,uint32_t clock)203 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
204 {
205 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
206
207 if (clock && smu10_data->deep_sleep_dcefclk != clock) {
208 smu10_data->deep_sleep_dcefclk = clock;
209 smum_send_msg_to_smc_with_parameter(hwmgr,
210 PPSMC_MSG_SetMinDeepSleepDcefclk,
211 smu10_data->deep_sleep_dcefclk,
212 NULL);
213 }
214 return 0;
215 }
216
smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr * hwmgr,uint32_t clock)217 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
218 {
219 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
220
221 if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
222 smu10_data->dcf_actual_hard_min_freq = clock;
223 smum_send_msg_to_smc_with_parameter(hwmgr,
224 PPSMC_MSG_SetHardMinDcefclkByFreq,
225 smu10_data->dcf_actual_hard_min_freq,
226 NULL);
227 }
228 return 0;
229 }
230
smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr * hwmgr,uint32_t clock)231 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
232 {
233 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
234
235 if (clock && smu10_data->f_actual_hard_min_freq != clock) {
236 smu10_data->f_actual_hard_min_freq = clock;
237 smum_send_msg_to_smc_with_parameter(hwmgr,
238 PPSMC_MSG_SetHardMinFclkByFreq,
239 smu10_data->f_actual_hard_min_freq,
240 NULL);
241 }
242 return 0;
243 }
244
smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr * hwmgr,uint32_t clock)245 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
246 {
247 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
248
249 if (clock && smu10_data->gfx_actual_soft_min_freq != clock) {
250 smu10_data->gfx_actual_soft_min_freq = clock;
251 smum_send_msg_to_smc_with_parameter(hwmgr,
252 PPSMC_MSG_SetHardMinGfxClk,
253 clock,
254 NULL);
255 }
256 return 0;
257 }
258
smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr * hwmgr,uint32_t clock)259 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
260 {
261 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
262
263 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) {
264 smu10_data->gfx_max_freq_limit = clock * 100;
265 smum_send_msg_to_smc_with_parameter(hwmgr,
266 PPSMC_MSG_SetSoftMaxGfxClk,
267 clock,
268 NULL);
269 }
270 return 0;
271 }
272
smu10_set_active_display_count(struct pp_hwmgr * hwmgr,uint32_t count)273 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
274 {
275 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
276
277 if (smu10_data->num_active_display != count) {
278 smu10_data->num_active_display = count;
279 smum_send_msg_to_smc_with_parameter(hwmgr,
280 PPSMC_MSG_SetDisplayCount,
281 smu10_data->num_active_display,
282 NULL);
283 }
284
285 return 0;
286 }
287
smu10_set_power_state_tasks(struct pp_hwmgr * hwmgr,const void * input)288 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
289 {
290 return smu10_set_clock_limit(hwmgr, input);
291 }
292
smu10_init_power_gate_state(struct pp_hwmgr * hwmgr)293 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
294 {
295 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
296 struct amdgpu_device *adev = hwmgr->adev;
297
298 smu10_data->vcn_power_gated = true;
299 smu10_data->isp_tileA_power_gated = true;
300 smu10_data->isp_tileB_power_gated = true;
301
302 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
303 return smum_send_msg_to_smc_with_parameter(hwmgr,
304 PPSMC_MSG_SetGfxCGPG,
305 true,
306 NULL);
307 else
308 return 0;
309 }
310
311
smu10_setup_asic_task(struct pp_hwmgr * hwmgr)312 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
313 {
314 return smu10_init_power_gate_state(hwmgr);
315 }
316
smu10_reset_cc6_data(struct pp_hwmgr * hwmgr)317 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
318 {
319 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
320
321 smu10_data->separation_time = 0;
322 smu10_data->cc6_disable = false;
323 smu10_data->pstate_disable = false;
324 smu10_data->cc6_setting_changed = false;
325
326 return 0;
327 }
328
smu10_power_off_asic(struct pp_hwmgr * hwmgr)329 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
330 {
331 return smu10_reset_cc6_data(hwmgr);
332 }
333
smu10_is_gfx_on(struct pp_hwmgr * hwmgr)334 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
335 {
336 uint32_t reg;
337 struct amdgpu_device *adev = hwmgr->adev;
338
339 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
340 if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
341 (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
342 return true;
343
344 return false;
345 }
346
smu10_disable_gfx_off(struct pp_hwmgr * hwmgr)347 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
348 {
349 struct amdgpu_device *adev = hwmgr->adev;
350
351 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
352 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
353
354 /* confirm gfx is back to "on" state */
355 while (!smu10_is_gfx_on(hwmgr))
356 msleep(1);
357 }
358
359 return 0;
360 }
361
smu10_disable_dpm_tasks(struct pp_hwmgr * hwmgr)362 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
363 {
364 return 0;
365 }
366
smu10_enable_gfx_off(struct pp_hwmgr * hwmgr)367 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
368 {
369 struct amdgpu_device *adev = hwmgr->adev;
370
371 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
372 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
373
374 return 0;
375 }
376
smu10_populate_umdpstate_clocks(struct pp_hwmgr * hwmgr)377 static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
378 {
379 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;
380 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;
381
382 smum_send_msg_to_smc(hwmgr,
383 PPSMC_MSG_GetMaxGfxclkFrequency,
384 &hwmgr->pstate_sclk_peak);
385 hwmgr->pstate_mclk_peak = SMU10_UMD_PSTATE_PEAK_FCLK;
386 }
387
smu10_enable_dpm_tasks(struct pp_hwmgr * hwmgr)388 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
389 {
390 struct amdgpu_device *adev = hwmgr->adev;
391 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
392 int ret = -EINVAL;
393
394 if (adev->in_suspend) {
395 pr_info("restore the fine grain parameters\n");
396
397 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
398 PPSMC_MSG_SetHardMinGfxClk,
399 smu10_data->gfx_actual_soft_min_freq,
400 NULL);
401 if (ret)
402 return ret;
403 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
404 PPSMC_MSG_SetSoftMaxGfxClk,
405 smu10_data->gfx_actual_soft_max_freq,
406 NULL);
407 if (ret)
408 return ret;
409 }
410
411 smu10_populate_umdpstate_clocks(hwmgr);
412
413 return 0;
414 }
415
smu10_gfx_off_control(struct pp_hwmgr * hwmgr,bool enable)416 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
417 {
418 if (enable)
419 return smu10_enable_gfx_off(hwmgr);
420 else
421 return smu10_disable_gfx_off(hwmgr);
422 }
423
smu10_apply_state_adjust_rules(struct pp_hwmgr * hwmgr,struct pp_power_state * prequest_ps,const struct pp_power_state * pcurrent_ps)424 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
425 struct pp_power_state *prequest_ps,
426 const struct pp_power_state *pcurrent_ps)
427 {
428 return 0;
429 }
430
431 /* temporary hardcoded clock voltage breakdown tables */
432 static const DpmClock_t VddDcfClk[] = {
433 { 300, 2600},
434 { 600, 3200},
435 { 600, 3600},
436 };
437
438 static const DpmClock_t VddSocClk[] = {
439 { 478, 2600},
440 { 722, 3200},
441 { 722, 3600},
442 };
443
444 static const DpmClock_t VddFClk[] = {
445 { 400, 2600},
446 {1200, 3200},
447 {1200, 3600},
448 };
449
450 static const DpmClock_t VddDispClk[] = {
451 { 435, 2600},
452 { 661, 3200},
453 {1086, 3600},
454 };
455
456 static const DpmClock_t VddDppClk[] = {
457 { 435, 2600},
458 { 661, 3200},
459 { 661, 3600},
460 };
461
462 static const DpmClock_t VddPhyClk[] = {
463 { 540, 2600},
464 { 810, 3200},
465 { 810, 3600},
466 };
467
smu10_get_clock_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct smu10_voltage_dependency_table ** pptable,uint32_t num_entry,const DpmClock_t * pclk_dependency_table)468 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
469 struct smu10_voltage_dependency_table **pptable,
470 uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
471 {
472 uint32_t i;
473 struct smu10_voltage_dependency_table *ptable;
474
475 ptable = kzalloc_flex(*ptable, entries, num_entry);
476 if (NULL == ptable)
477 return -ENOMEM;
478
479 ptable->count = num_entry;
480
481 for (i = 0; i < ptable->count; i++) {
482 ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
483 ptable->entries[i].vol = pclk_dependency_table->Vol;
484 pclk_dependency_table++;
485 }
486
487 *pptable = ptable;
488
489 return 0;
490 }
491
492
smu10_populate_clock_table(struct pp_hwmgr * hwmgr)493 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
494 {
495 uint32_t result;
496
497 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
498 DpmClocks_t *table = &(smu10_data->clock_table);
499 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
500
501 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
502
503 PP_ASSERT_WITH_CODE((0 == result),
504 "Attempt to copy clock table from smc failed",
505 return result);
506
507 if (0 == result && table->DcefClocks[0].Freq != 0) {
508 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
509 NUM_DCEFCLK_DPM_LEVELS,
510 &smu10_data->clock_table.DcefClocks[0]);
511 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
512 NUM_SOCCLK_DPM_LEVELS,
513 &smu10_data->clock_table.SocClocks[0]);
514 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
515 NUM_FCLK_DPM_LEVELS,
516 &smu10_data->clock_table.FClocks[0]);
517 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
518 NUM_MEMCLK_DPM_LEVELS,
519 &smu10_data->clock_table.MemClocks[0]);
520 } else {
521 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
522 ARRAY_SIZE(VddDcfClk),
523 &VddDcfClk[0]);
524 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
525 ARRAY_SIZE(VddSocClk),
526 &VddSocClk[0]);
527 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
528 ARRAY_SIZE(VddFClk),
529 &VddFClk[0]);
530 }
531 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
532 ARRAY_SIZE(VddDispClk),
533 &VddDispClk[0]);
534 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
535 ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
536 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
537 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
538
539 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
540 smu10_data->gfx_min_freq_limit = result / 10 * 1000;
541
542 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
543 smu10_data->gfx_max_freq_limit = result / 10 * 1000;
544
545 return 0;
546 }
547
smu10_hwmgr_backend_init(struct pp_hwmgr * hwmgr)548 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
549 {
550 int result = 0;
551 struct smu10_hwmgr *data;
552
553 data = kzalloc_obj(struct smu10_hwmgr);
554 if (data == NULL)
555 return -ENOMEM;
556
557 hwmgr->backend = data;
558
559 result = smu10_initialize_dpm_defaults(hwmgr);
560 if (result != 0) {
561 pr_err("smu10_initialize_dpm_defaults failed\n");
562 return result;
563 }
564
565 smu10_populate_clock_table(hwmgr);
566
567 result = smu10_get_system_info_data(hwmgr);
568 if (result != 0) {
569 pr_err("smu10_get_system_info_data failed\n");
570 return result;
571 }
572
573 smu10_construct_boot_state(hwmgr);
574
575 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
576 SMU10_MAX_HARDWARE_POWERLEVELS;
577
578 hwmgr->platform_descriptor.hardwarePerformanceLevels =
579 SMU10_MAX_HARDWARE_POWERLEVELS;
580
581 hwmgr->platform_descriptor.vbiosInterruptId = 0;
582
583 hwmgr->platform_descriptor.clockStep.engineClock = 500;
584
585 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
586
587 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
588
589 /* enable the pp_od_clk_voltage sysfs file */
590 hwmgr->od_enabled = 1;
591 /* disabled fine grain tuning function by default */
592 data->fine_grain_enabled = 0;
593 return result;
594 }
595
smu10_hwmgr_backend_fini(struct pp_hwmgr * hwmgr)596 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
597 {
598 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
599 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
600
601 kfree(pinfo->vdd_dep_on_dcefclk);
602 pinfo->vdd_dep_on_dcefclk = NULL;
603 kfree(pinfo->vdd_dep_on_socclk);
604 pinfo->vdd_dep_on_socclk = NULL;
605 kfree(pinfo->vdd_dep_on_fclk);
606 pinfo->vdd_dep_on_fclk = NULL;
607 kfree(pinfo->vdd_dep_on_dispclk);
608 pinfo->vdd_dep_on_dispclk = NULL;
609 kfree(pinfo->vdd_dep_on_dppclk);
610 pinfo->vdd_dep_on_dppclk = NULL;
611 kfree(pinfo->vdd_dep_on_phyclk);
612 pinfo->vdd_dep_on_phyclk = NULL;
613
614 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
615 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
616
617 kfree(hwmgr->backend);
618 hwmgr->backend = NULL;
619
620 return 0;
621 }
622
smu10_dpm_force_dpm_level(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)623 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
624 enum amd_dpm_forced_level level)
625 {
626 struct smu10_hwmgr *data = hwmgr->backend;
627 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
628 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
629 uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
630 uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
631 uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;
632
633 if (hwmgr->smu_version < 0x1E3700) {
634 pr_info("smu firmware version too old, can not set dpm level\n");
635 return 0;
636 }
637
638 if (min_sclk < data->gfx_min_freq_limit)
639 min_sclk = data->gfx_min_freq_limit;
640
641 min_sclk /= 100; /* transfer 10KHz to MHz */
642 if (min_mclk < data->clock_table.FClocks[0].Freq)
643 min_mclk = data->clock_table.FClocks[0].Freq;
644
645 switch (level) {
646 case AMD_DPM_FORCED_LEVEL_HIGH:
647 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
648 data->fine_grain_enabled = 0;
649
650 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
651 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
652
653 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
654 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
655
656 smum_send_msg_to_smc_with_parameter(hwmgr,
657 PPSMC_MSG_SetHardMinGfxClk,
658 data->gfx_max_freq_limit/100,
659 NULL);
660 smum_send_msg_to_smc_with_parameter(hwmgr,
661 PPSMC_MSG_SetHardMinFclkByFreq,
662 SMU10_UMD_PSTATE_PEAK_FCLK,
663 NULL);
664 smum_send_msg_to_smc_with_parameter(hwmgr,
665 PPSMC_MSG_SetHardMinSocclkByFreq,
666 SMU10_UMD_PSTATE_PEAK_SOCCLK,
667 NULL);
668 smum_send_msg_to_smc_with_parameter(hwmgr,
669 PPSMC_MSG_SetHardMinVcn,
670 SMU10_UMD_PSTATE_VCE,
671 NULL);
672
673 smum_send_msg_to_smc_with_parameter(hwmgr,
674 PPSMC_MSG_SetSoftMaxGfxClk,
675 data->gfx_max_freq_limit/100,
676 NULL);
677 smum_send_msg_to_smc_with_parameter(hwmgr,
678 PPSMC_MSG_SetSoftMaxFclkByFreq,
679 SMU10_UMD_PSTATE_PEAK_FCLK,
680 NULL);
681 smum_send_msg_to_smc_with_parameter(hwmgr,
682 PPSMC_MSG_SetSoftMaxSocclkByFreq,
683 SMU10_UMD_PSTATE_PEAK_SOCCLK,
684 NULL);
685 smum_send_msg_to_smc_with_parameter(hwmgr,
686 PPSMC_MSG_SetSoftMaxVcn,
687 SMU10_UMD_PSTATE_VCE,
688 NULL);
689 break;
690 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
691 data->fine_grain_enabled = 0;
692
693 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
694 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
695
696 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
697 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
698
699 smum_send_msg_to_smc_with_parameter(hwmgr,
700 PPSMC_MSG_SetHardMinGfxClk,
701 min_sclk,
702 NULL);
703 smum_send_msg_to_smc_with_parameter(hwmgr,
704 PPSMC_MSG_SetSoftMaxGfxClk,
705 min_sclk,
706 NULL);
707 break;
708 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
709 data->fine_grain_enabled = 0;
710
711 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
712 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
713
714 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
715 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
716
717 smum_send_msg_to_smc_with_parameter(hwmgr,
718 PPSMC_MSG_SetHardMinFclkByFreq,
719 min_mclk,
720 NULL);
721 smum_send_msg_to_smc_with_parameter(hwmgr,
722 PPSMC_MSG_SetSoftMaxFclkByFreq,
723 min_mclk,
724 NULL);
725 break;
726 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
727 data->fine_grain_enabled = 0;
728
729 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
730 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
731
732 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
733 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
734
735 smum_send_msg_to_smc_with_parameter(hwmgr,
736 PPSMC_MSG_SetHardMinGfxClk,
737 SMU10_UMD_PSTATE_GFXCLK,
738 NULL);
739 smum_send_msg_to_smc_with_parameter(hwmgr,
740 PPSMC_MSG_SetHardMinFclkByFreq,
741 SMU10_UMD_PSTATE_FCLK,
742 NULL);
743 smum_send_msg_to_smc_with_parameter(hwmgr,
744 PPSMC_MSG_SetHardMinSocclkByFreq,
745 SMU10_UMD_PSTATE_SOCCLK,
746 NULL);
747 smum_send_msg_to_smc_with_parameter(hwmgr,
748 PPSMC_MSG_SetHardMinVcn,
749 SMU10_UMD_PSTATE_PROFILE_VCE,
750 NULL);
751
752 smum_send_msg_to_smc_with_parameter(hwmgr,
753 PPSMC_MSG_SetSoftMaxGfxClk,
754 SMU10_UMD_PSTATE_GFXCLK,
755 NULL);
756 smum_send_msg_to_smc_with_parameter(hwmgr,
757 PPSMC_MSG_SetSoftMaxFclkByFreq,
758 SMU10_UMD_PSTATE_FCLK,
759 NULL);
760 smum_send_msg_to_smc_with_parameter(hwmgr,
761 PPSMC_MSG_SetSoftMaxSocclkByFreq,
762 SMU10_UMD_PSTATE_SOCCLK,
763 NULL);
764 smum_send_msg_to_smc_with_parameter(hwmgr,
765 PPSMC_MSG_SetSoftMaxVcn,
766 SMU10_UMD_PSTATE_PROFILE_VCE,
767 NULL);
768 break;
769 case AMD_DPM_FORCED_LEVEL_AUTO:
770 data->fine_grain_enabled = 0;
771
772 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
773 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
774
775 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
776 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
777
778 smum_send_msg_to_smc_with_parameter(hwmgr,
779 PPSMC_MSG_SetHardMinGfxClk,
780 min_sclk,
781 NULL);
782 smum_send_msg_to_smc_with_parameter(hwmgr,
783 PPSMC_MSG_SetHardMinFclkByFreq,
784 hwmgr->display_config->num_display > 3 ?
785 (data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) :
786 min_mclk,
787 NULL);
788
789 smum_send_msg_to_smc_with_parameter(hwmgr,
790 PPSMC_MSG_SetHardMinSocclkByFreq,
791 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk / 100,
792 NULL);
793 smum_send_msg_to_smc_with_parameter(hwmgr,
794 PPSMC_MSG_SetHardMinVcn,
795 SMU10_UMD_PSTATE_MIN_VCE,
796 NULL);
797
798 smum_send_msg_to_smc_with_parameter(hwmgr,
799 PPSMC_MSG_SetSoftMaxGfxClk,
800 data->gfx_max_freq_limit/100,
801 NULL);
802 smum_send_msg_to_smc_with_parameter(hwmgr,
803 PPSMC_MSG_SetSoftMaxFclkByFreq,
804 data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk / 100,
805 NULL);
806 smum_send_msg_to_smc_with_parameter(hwmgr,
807 PPSMC_MSG_SetSoftMaxSocclkByFreq,
808 data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk / 100,
809 NULL);
810 smum_send_msg_to_smc_with_parameter(hwmgr,
811 PPSMC_MSG_SetSoftMaxVcn,
812 SMU10_UMD_PSTATE_VCE,
813 NULL);
814 break;
815 case AMD_DPM_FORCED_LEVEL_LOW:
816 data->fine_grain_enabled = 0;
817
818 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
819 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
820
821 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
822 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
823
824 smum_send_msg_to_smc_with_parameter(hwmgr,
825 PPSMC_MSG_SetHardMinGfxClk,
826 data->gfx_min_freq_limit/100,
827 NULL);
828 smum_send_msg_to_smc_with_parameter(hwmgr,
829 PPSMC_MSG_SetSoftMaxGfxClk,
830 data->gfx_min_freq_limit/100,
831 NULL);
832 smum_send_msg_to_smc_with_parameter(hwmgr,
833 PPSMC_MSG_SetHardMinFclkByFreq,
834 min_mclk,
835 NULL);
836 smum_send_msg_to_smc_with_parameter(hwmgr,
837 PPSMC_MSG_SetSoftMaxFclkByFreq,
838 min_mclk,
839 NULL);
840 break;
841 case AMD_DPM_FORCED_LEVEL_MANUAL:
842 data->fine_grain_enabled = 1;
843 break;
844 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
845 default:
846 break;
847 }
848 return 0;
849 }
850
smu10_dpm_get_mclk(struct pp_hwmgr * hwmgr,bool low)851 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
852 {
853 struct smu10_hwmgr *data;
854
855 if (hwmgr == NULL)
856 return -EINVAL;
857
858 data = (struct smu10_hwmgr *)(hwmgr->backend);
859
860 if (low)
861 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
862 else
863 return data->clock_vol_info.vdd_dep_on_fclk->entries[
864 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
865 }
866
smu10_dpm_get_sclk(struct pp_hwmgr * hwmgr,bool low)867 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
868 {
869 struct smu10_hwmgr *data;
870
871 if (hwmgr == NULL)
872 return -EINVAL;
873
874 data = (struct smu10_hwmgr *)(hwmgr->backend);
875
876 if (low)
877 return data->gfx_min_freq_limit;
878 else
879 return data->gfx_max_freq_limit;
880 }
881
smu10_dpm_patch_boot_state(struct pp_hwmgr * hwmgr,struct pp_hw_power_state * hw_ps)882 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
883 struct pp_hw_power_state *hw_ps)
884 {
885 return 0;
886 }
887
smu10_dpm_get_pp_table_entry_callback(struct pp_hwmgr * hwmgr,struct pp_hw_power_state * hw_ps,unsigned int index,const void * clock_info)888 static int smu10_dpm_get_pp_table_entry_callback(
889 struct pp_hwmgr *hwmgr,
890 struct pp_hw_power_state *hw_ps,
891 unsigned int index,
892 const void *clock_info)
893 {
894 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
895
896 smu10_ps->levels[index].engine_clock = 0;
897
898 smu10_ps->levels[index].vddc_index = 0;
899 smu10_ps->level = index + 1;
900
901 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
902 smu10_ps->levels[index].ds_divider_index = 5;
903 smu10_ps->levels[index].ss_divider_index = 5;
904 }
905
906 return 0;
907 }
908
smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr * hwmgr)909 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
910 {
911 int result;
912 unsigned long ret = 0;
913
914 result = pp_tables_get_num_of_entries(hwmgr, &ret);
915
916 return result ? 0 : ret;
917 }
918
smu10_dpm_get_pp_table_entry(struct pp_hwmgr * hwmgr,unsigned long entry,struct pp_power_state * ps)919 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
920 unsigned long entry, struct pp_power_state *ps)
921 {
922 int result;
923 struct smu10_power_state *smu10_ps;
924
925 ps->hardware.magic = SMU10_Magic;
926
927 smu10_ps = cast_smu10_ps(&(ps->hardware));
928
929 result = pp_tables_get_entry(hwmgr, entry, ps,
930 smu10_dpm_get_pp_table_entry_callback);
931
932 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
933 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
934
935 return result;
936 }
937
smu10_get_power_state_size(struct pp_hwmgr * hwmgr)938 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
939 {
940 return sizeof(struct smu10_power_state);
941 }
942
smu10_set_cpu_power_state(struct pp_hwmgr * hwmgr)943 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
944 {
945 return 0;
946 }
947
948
smu10_store_cc6_data(struct pp_hwmgr * hwmgr,uint32_t separation_time,bool cc6_disable,bool pstate_disable,bool pstate_switch_disable)949 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
950 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
951 {
952 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
953
954 if (separation_time != data->separation_time ||
955 cc6_disable != data->cc6_disable ||
956 pstate_disable != data->pstate_disable) {
957 data->separation_time = separation_time;
958 data->cc6_disable = cc6_disable;
959 data->pstate_disable = pstate_disable;
960 data->cc6_setting_changed = true;
961 }
962 return 0;
963 }
964
smu10_get_dal_power_level(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * info)965 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
966 struct amd_pp_simple_clock_info *info)
967 {
968 return -EINVAL;
969 }
970
smu10_force_clock_level(struct pp_hwmgr * hwmgr,enum pp_clock_type type,uint32_t mask)971 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
972 enum pp_clock_type type, uint32_t mask)
973 {
974 struct smu10_hwmgr *data = hwmgr->backend;
975 struct smu10_voltage_dependency_table *mclk_table =
976 data->clock_vol_info.vdd_dep_on_fclk;
977 uint32_t low, high;
978
979 low = mask ? (ffs(mask) - 1) : 0;
980 high = mask ? (fls(mask) - 1) : 0;
981
982 switch (type) {
983 case PP_SCLK:
984 if (low > 2 || high > 2) {
985 pr_info("Currently sclk only support 3 levels on RV\n");
986 return -EINVAL;
987 }
988
989 smum_send_msg_to_smc_with_parameter(hwmgr,
990 PPSMC_MSG_SetHardMinGfxClk,
991 low == 2 ? data->gfx_max_freq_limit/100 :
992 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
993 data->gfx_min_freq_limit/100,
994 NULL);
995
996 smum_send_msg_to_smc_with_parameter(hwmgr,
997 PPSMC_MSG_SetSoftMaxGfxClk,
998 high == 0 ? data->gfx_min_freq_limit/100 :
999 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
1000 data->gfx_max_freq_limit/100,
1001 NULL);
1002 break;
1003
1004 case PP_MCLK:
1005 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
1006 return -EINVAL;
1007
1008 smum_send_msg_to_smc_with_parameter(hwmgr,
1009 PPSMC_MSG_SetHardMinFclkByFreq,
1010 mclk_table->entries[low].clk/100,
1011 NULL);
1012
1013 smum_send_msg_to_smc_with_parameter(hwmgr,
1014 PPSMC_MSG_SetSoftMaxFclkByFreq,
1015 mclk_table->entries[high].clk/100,
1016 NULL);
1017 break;
1018
1019 case PP_PCIE:
1020 default:
1021 break;
1022 }
1023 return 0;
1024 }
1025
smu10_emit_clock_levels(struct pp_hwmgr * hwmgr,enum pp_clock_type type,char * buf,int * offset)1026 static int smu10_emit_clock_levels(struct pp_hwmgr *hwmgr,
1027 enum pp_clock_type type, char *buf,
1028 int *offset)
1029 {
1030 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
1031 struct smu10_voltage_dependency_table *mclk_table =
1032 data->clock_vol_info.vdd_dep_on_fclk;
1033 uint32_t i, now, size = *offset;
1034 uint32_t min_freq, max_freq = 0;
1035 int ret = 0;
1036
1037 switch (type) {
1038 case PP_SCLK:
1039 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
1040 if (ret)
1041 return ret;
1042
1043 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
1044 if (now == data->gfx_max_freq_limit/100)
1045 i = 2;
1046 else if (now == data->gfx_min_freq_limit/100)
1047 i = 0;
1048 else
1049 i = 1;
1050
1051 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1052 data->gfx_min_freq_limit / 100,
1053 i == 0 ? "*" : "");
1054 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1055 i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
1056 i == 1 ? "*" : "");
1057 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n",
1058 data->gfx_max_freq_limit / 100,
1059 i == 2 ? "*" : "");
1060 break;
1061 case PP_MCLK:
1062 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
1063 if (ret)
1064 return ret;
1065
1066 for (i = 0; i < mclk_table->count; i++)
1067 size += sysfs_emit_at(
1068 buf, size, "%d: %uMhz %s\n", i,
1069 mclk_table->entries[i].clk / 100,
1070 ((mclk_table->entries[i].clk / 100) == now) ?
1071 "*" :
1072 "");
1073 break;
1074 case OD_SCLK:
1075 if (hwmgr->od_enabled) {
1076 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1077 if (ret)
1078 return ret;
1079 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1080 if (ret)
1081 return ret;
1082
1083 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1084 size += sysfs_emit_at(
1085 buf, size, "0: %10uMhz\n",
1086 (data->gfx_actual_soft_min_freq > 0) ?
1087 data->gfx_actual_soft_min_freq :
1088 min_freq);
1089 size += sysfs_emit_at(
1090 buf, size, "1: %10uMhz\n",
1091 (data->gfx_actual_soft_max_freq > 0) ?
1092 data->gfx_actual_soft_max_freq :
1093 max_freq);
1094 }
1095 break;
1096 case OD_RANGE:
1097 if (hwmgr->od_enabled) {
1098 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1099 if (ret)
1100 return ret;
1101 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1102 if (ret)
1103 return ret;
1104
1105 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1106 size += sysfs_emit_at(buf, size,
1107 "SCLK: %7uMHz %10uMHz\n",
1108 min_freq, max_freq);
1109 }
1110 break;
1111 default:
1112 break;
1113 }
1114
1115 *offset = size;
1116
1117 return 0;
1118 }
1119
smu10_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)1120 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1121 PHM_PerformanceLevelDesignation designation, uint32_t index,
1122 PHM_PerformanceLevel *level)
1123 {
1124 struct smu10_hwmgr *data;
1125
1126 if (level == NULL || hwmgr == NULL || state == NULL)
1127 return -EINVAL;
1128
1129 data = (struct smu10_hwmgr *)(hwmgr->backend);
1130
1131 if (index == 0) {
1132 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
1133 level->coreClock = data->gfx_min_freq_limit;
1134 } else {
1135 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
1136 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
1137 level->coreClock = data->gfx_max_freq_limit;
1138 }
1139
1140 level->nonLocalMemoryFreq = 0;
1141 level->nonLocalMemoryWidth = 0;
1142
1143 return 0;
1144 }
1145
smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,struct pp_clock_info * clock_info)1146 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1147 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1148 {
1149 const struct smu10_power_state *ps = cast_const_smu10_ps(state);
1150
1151 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
1152 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
1153
1154 return 0;
1155 }
1156
1157 #define MEM_FREQ_LOW_LATENCY 25000
1158 #define MEM_FREQ_HIGH_LATENCY 80000
1159 #define MEM_LATENCY_HIGH 245
1160 #define MEM_LATENCY_LOW 35
1161 #define MEM_LATENCY_ERR 0xFFFF
1162
1163
smu10_get_mem_latency(struct pp_hwmgr * hwmgr,uint32_t clock)1164 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1165 uint32_t clock)
1166 {
1167 if (clock >= MEM_FREQ_LOW_LATENCY &&
1168 clock < MEM_FREQ_HIGH_LATENCY)
1169 return MEM_LATENCY_HIGH;
1170 else if (clock >= MEM_FREQ_HIGH_LATENCY)
1171 return MEM_LATENCY_LOW;
1172 else
1173 return MEM_LATENCY_ERR;
1174 }
1175
smu10_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)1176 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1177 enum amd_pp_clock_type type,
1178 struct pp_clock_levels_with_latency *clocks)
1179 {
1180 uint32_t i;
1181 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1182 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1183 struct smu10_voltage_dependency_table *pclk_vol_table;
1184 bool latency_required = false;
1185
1186 if (pinfo == NULL)
1187 return -EINVAL;
1188
1189 switch (type) {
1190 case amd_pp_mem_clock:
1191 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1192 latency_required = true;
1193 break;
1194 case amd_pp_f_clock:
1195 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1196 latency_required = true;
1197 break;
1198 case amd_pp_dcf_clock:
1199 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1200 break;
1201 case amd_pp_disp_clock:
1202 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1203 break;
1204 case amd_pp_phy_clock:
1205 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1206 break;
1207 case amd_pp_dpp_clock:
1208 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1209 break;
1210 default:
1211 return -EINVAL;
1212 }
1213
1214 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1215 return -EINVAL;
1216
1217 clocks->num_levels = 0;
1218 for (i = 0; i < pclk_vol_table->count; i++) {
1219 if (pclk_vol_table->entries[i].clk) {
1220 clocks->data[clocks->num_levels].clocks_in_khz =
1221 pclk_vol_table->entries[i].clk * 10;
1222 clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1223 smu10_get_mem_latency(hwmgr,
1224 pclk_vol_table->entries[i].clk) :
1225 0;
1226 clocks->num_levels++;
1227 }
1228 }
1229
1230 return 0;
1231 }
1232
smu10_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)1233 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1234 enum amd_pp_clock_type type,
1235 struct pp_clock_levels_with_voltage *clocks)
1236 {
1237 uint32_t i;
1238 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1239 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1240 struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1241
1242 if (pinfo == NULL)
1243 return -EINVAL;
1244
1245 switch (type) {
1246 case amd_pp_mem_clock:
1247 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1248 break;
1249 case amd_pp_f_clock:
1250 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1251 break;
1252 case amd_pp_dcf_clock:
1253 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1254 break;
1255 case amd_pp_soc_clock:
1256 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1257 break;
1258 case amd_pp_disp_clock:
1259 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1260 break;
1261 case amd_pp_phy_clock:
1262 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1263 break;
1264 default:
1265 return -EINVAL;
1266 }
1267
1268 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1269 return -EINVAL;
1270
1271 clocks->num_levels = 0;
1272 for (i = 0; i < pclk_vol_table->count; i++) {
1273 if (pclk_vol_table->entries[i].clk) {
1274 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1275 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1276 clocks->num_levels++;
1277 }
1278 }
1279
1280 return 0;
1281 }
1282
1283
1284
smu10_get_max_high_clocks(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * clocks)1285 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1286 {
1287 clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1288 return 0;
1289 }
1290
smu10_thermal_get_temperature(struct pp_hwmgr * hwmgr)1291 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1292 {
1293 struct amdgpu_device *adev = hwmgr->adev;
1294 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1295 int cur_temp =
1296 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1297
1298 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1299 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1300 else
1301 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1302
1303 return cur_temp;
1304 }
1305
smu10_read_sensor(struct pp_hwmgr * hwmgr,int idx,void * value,int * size)1306 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1307 void *value, int *size)
1308 {
1309 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1310 struct amdgpu_device *adev = hwmgr->adev;
1311 uint32_t sclk, mclk, activity_percent;
1312 bool has_gfx_busy;
1313 int ret = 0;
1314
1315 /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */
1316 if ((adev->apu_flags & AMD_APU_IS_PICASSO) &&
1317 (hwmgr->smu_version >= 0x41e3b))
1318 has_gfx_busy = true;
1319 else if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1320 (hwmgr->smu_version >= 0x1e5500))
1321 has_gfx_busy = true;
1322 else
1323 has_gfx_busy = false;
1324
1325 switch (idx) {
1326 case AMDGPU_PP_SENSOR_GFX_SCLK:
1327 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1328 if (ret)
1329 break;
1330 /* in units of 10KHZ */
1331 *((uint32_t *)value) = sclk * 100;
1332 *size = 4;
1333 break;
1334 case AMDGPU_PP_SENSOR_GFX_MCLK:
1335 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1336 if (ret)
1337 break;
1338 /* in units of 10KHZ */
1339 *((uint32_t *)value) = mclk * 100;
1340 *size = 4;
1341 break;
1342 case AMDGPU_PP_SENSOR_GPU_TEMP:
1343 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1344 break;
1345 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1346 *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
1347 *size = 4;
1348 break;
1349 case AMDGPU_PP_SENSOR_GPU_LOAD:
1350 if (!has_gfx_busy)
1351 ret = -EOPNOTSUPP;
1352 else {
1353 ret = smum_send_msg_to_smc(hwmgr,
1354 PPSMC_MSG_GetGfxBusy,
1355 &activity_percent);
1356 if (!ret)
1357 *((uint32_t *)value) = min(activity_percent, (u32)100);
1358 else
1359 ret = -EIO;
1360 }
1361 break;
1362 default:
1363 ret = -EOPNOTSUPP;
1364 break;
1365 }
1366
1367 return ret;
1368 }
1369
smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)1370 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1371 void *clock_ranges)
1372 {
1373 struct smu10_hwmgr *data = hwmgr->backend;
1374 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1375 Watermarks_t *table = &(data->water_marks_table);
1376 struct amdgpu_device *adev = hwmgr->adev;
1377 int i;
1378
1379 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1380
1381 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1382 for (i = 0; i < NUM_WM_RANGES; i++)
1383 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
1384
1385 for (i = 0; i < NUM_WM_RANGES; i++)
1386 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
1387 }
1388
1389 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1390 data->water_marks_exist = true;
1391 return 0;
1392 }
1393
smu10_smus_notify_pwe(struct pp_hwmgr * hwmgr)1394 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1395 {
1396
1397 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1398 }
1399
smu10_powergate_mmhub(struct pp_hwmgr * hwmgr)1400 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1401 {
1402 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1403 }
1404
smu10_powergate_sdma(struct pp_hwmgr * hwmgr,bool gate)1405 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1406 {
1407 if (gate)
1408 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1409 else
1410 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1411 }
1412
smu10_powergate_vcn(struct pp_hwmgr * hwmgr,bool bgate)1413 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1414 {
1415 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1416
1417 if (bgate) {
1418 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1419 AMD_IP_BLOCK_TYPE_VCN,
1420 AMD_PG_STATE_GATE);
1421 smum_send_msg_to_smc_with_parameter(hwmgr,
1422 PPSMC_MSG_PowerDownVcn, 0, NULL);
1423 smu10_data->vcn_power_gated = true;
1424 } else {
1425 smum_send_msg_to_smc_with_parameter(hwmgr,
1426 PPSMC_MSG_PowerUpVcn, 0, NULL);
1427 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1428 AMD_IP_BLOCK_TYPE_VCN,
1429 AMD_PG_STATE_UNGATE);
1430 smu10_data->vcn_power_gated = false;
1431 }
1432 }
1433
conv_power_profile_to_pplib_workload(int power_profile)1434 static int conv_power_profile_to_pplib_workload(int power_profile)
1435 {
1436 int pplib_workload = 0;
1437
1438 switch (power_profile) {
1439 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1440 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1441 break;
1442 case PP_SMC_POWER_PROFILE_VIDEO:
1443 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1444 break;
1445 case PP_SMC_POWER_PROFILE_VR:
1446 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1447 break;
1448 case PP_SMC_POWER_PROFILE_COMPUTE:
1449 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1450 break;
1451 case PP_SMC_POWER_PROFILE_CUSTOM:
1452 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
1453 break;
1454 }
1455
1456 return pplib_workload;
1457 }
1458
smu10_get_power_profile_mode(struct pp_hwmgr * hwmgr,char * buf)1459 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1460 {
1461 uint32_t i, size = 0;
1462 static const uint8_t
1463 profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1464 {70, 60, 1, 3,},
1465 {90, 60, 0, 0,},
1466 {70, 60, 0, 0,},
1467 {70, 90, 0, 0,},
1468 {30, 60, 0, 6,},
1469 };
1470 static const char *title[6] = {"NUM",
1471 "MODE_NAME",
1472 "BUSY_SET_POINT",
1473 "FPS",
1474 "USE_RLC_BUSY",
1475 "MIN_ACTIVE_LEVEL"};
1476
1477 if (!buf)
1478 return -EINVAL;
1479
1480 phm_get_sysfs_buf(&buf, &size);
1481
1482 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n", title[0],
1483 title[1], title[2], title[3], title[4], title[5]);
1484
1485 for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1486 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n",
1487 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1488 profile_mode_setting[i][0], profile_mode_setting[i][1],
1489 profile_mode_setting[i][2], profile_mode_setting[i][3]);
1490
1491 return size;
1492 }
1493
smu10_is_raven1_refresh(struct pp_hwmgr * hwmgr)1494 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1495 {
1496 struct amdgpu_device *adev = hwmgr->adev;
1497 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1498 (hwmgr->smu_version >= 0x41e2b))
1499 return true;
1500 else
1501 return false;
1502 }
1503
smu10_set_power_profile_mode(struct pp_hwmgr * hwmgr,long * input,uint32_t size)1504 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1505 {
1506 int workload_type = 0;
1507 int result = 0;
1508
1509 if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1510 pr_err("Invalid power profile mode %ld\n", input[size]);
1511 return -EINVAL;
1512 }
1513 if (hwmgr->power_profile_mode == input[size])
1514 return 0;
1515
1516 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1517 workload_type =
1518 conv_power_profile_to_pplib_workload(input[size]);
1519 if (workload_type &&
1520 smu10_is_raven1_refresh(hwmgr) &&
1521 !hwmgr->gfxoff_state_changed_by_workload) {
1522 smu10_gfx_off_control(hwmgr, false);
1523 hwmgr->gfxoff_state_changed_by_workload = true;
1524 }
1525 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1526 1 << workload_type,
1527 NULL);
1528 if (!result)
1529 hwmgr->power_profile_mode = input[size];
1530 if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1531 smu10_gfx_off_control(hwmgr, true);
1532 hwmgr->gfxoff_state_changed_by_workload = false;
1533 }
1534
1535 return 0;
1536 }
1537
smu10_asic_reset(struct pp_hwmgr * hwmgr,enum SMU_ASIC_RESET_MODE mode)1538 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1539 {
1540 return smum_send_msg_to_smc_with_parameter(hwmgr,
1541 PPSMC_MSG_DeviceDriverReset,
1542 mode,
1543 NULL);
1544 }
1545
smu10_set_fine_grain_clk_vol(struct pp_hwmgr * hwmgr,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)1546 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
1547 enum PP_OD_DPM_TABLE_COMMAND type,
1548 long *input, uint32_t size)
1549 {
1550 uint32_t min_freq, max_freq = 0;
1551 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1552 int ret = 0;
1553
1554 if (!hwmgr->od_enabled) {
1555 pr_err("Fine grain not support\n");
1556 return -EINVAL;
1557 }
1558
1559 if (!smu10_data->fine_grain_enabled) {
1560 pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1561 return -EINVAL;
1562 }
1563
1564 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
1565 if (size != 2) {
1566 pr_err("Input parameter number not correct\n");
1567 return -EINVAL;
1568 }
1569
1570 if (input[0] == 0) {
1571 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1572 if (ret)
1573 return ret;
1574
1575 if (input[1] < min_freq) {
1576 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1577 input[1], min_freq);
1578 return -EINVAL;
1579 }
1580 smu10_data->gfx_actual_soft_min_freq = input[1];
1581 } else if (input[0] == 1) {
1582 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1583 if (ret)
1584 return ret;
1585
1586 if (input[1] > max_freq) {
1587 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1588 input[1], max_freq);
1589 return -EINVAL;
1590 }
1591 smu10_data->gfx_actual_soft_max_freq = input[1];
1592 } else {
1593 return -EINVAL;
1594 }
1595 } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
1596 if (size != 0) {
1597 pr_err("Input parameter number not correct\n");
1598 return -EINVAL;
1599 }
1600 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1601 if (ret)
1602 return ret;
1603 smu10_data->gfx_actual_soft_min_freq = min_freq;
1604
1605 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1606 if (ret)
1607 return ret;
1608
1609 smu10_data->gfx_actual_soft_max_freq = max_freq;
1610 } else if (type == PP_OD_COMMIT_DPM_TABLE) {
1611 if (size != 0) {
1612 pr_err("Input parameter number not correct\n");
1613 return -EINVAL;
1614 }
1615
1616 if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) {
1617 pr_err("The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1618 smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq);
1619 return -EINVAL;
1620 }
1621
1622 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1623 PPSMC_MSG_SetHardMinGfxClk,
1624 smu10_data->gfx_actual_soft_min_freq,
1625 NULL);
1626 if (ret)
1627 return ret;
1628
1629 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1630 PPSMC_MSG_SetSoftMaxGfxClk,
1631 smu10_data->gfx_actual_soft_max_freq,
1632 NULL);
1633 if (ret)
1634 return ret;
1635 } else {
1636 return -EINVAL;
1637 }
1638
1639 return 0;
1640 }
1641
smu10_gfx_state_change(struct pp_hwmgr * hwmgr,uint32_t state)1642 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
1643 {
1644 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
1645
1646 return 0;
1647 }
1648
1649 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1650 .backend_init = smu10_hwmgr_backend_init,
1651 .backend_fini = smu10_hwmgr_backend_fini,
1652 .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1653 .force_dpm_level = smu10_dpm_force_dpm_level,
1654 .get_power_state_size = smu10_get_power_state_size,
1655 .powergate_uvd = smu10_powergate_vcn,
1656 .powergate_vce = NULL,
1657 .get_mclk = smu10_dpm_get_mclk,
1658 .get_sclk = smu10_dpm_get_sclk,
1659 .patch_boot_state = smu10_dpm_patch_boot_state,
1660 .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1661 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1662 .set_cpu_power_state = smu10_set_cpu_power_state,
1663 .store_cc6_data = smu10_store_cc6_data,
1664 .force_clock_level = smu10_force_clock_level,
1665 .emit_clock_levels = smu10_emit_clock_levels,
1666 .get_dal_power_level = smu10_get_dal_power_level,
1667 .get_performance_level = smu10_get_performance_level,
1668 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1669 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1670 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1671 .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1672 .get_max_high_clocks = smu10_get_max_high_clocks,
1673 .read_sensor = smu10_read_sensor,
1674 .set_active_display_count = smu10_set_active_display_count,
1675 .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1676 .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1677 .power_off_asic = smu10_power_off_asic,
1678 .asic_setup = smu10_setup_asic_task,
1679 .power_state_set = smu10_set_power_state_tasks,
1680 .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1681 .powergate_mmhub = smu10_powergate_mmhub,
1682 .smus_notify_pwe = smu10_smus_notify_pwe,
1683 .display_clock_voltage_request = smu10_display_clock_voltage_request,
1684 .powergate_gfx = smu10_gfx_off_control,
1685 .powergate_sdma = smu10_powergate_sdma,
1686 .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1687 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1688 .set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq,
1689 .set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq,
1690 .get_power_profile_mode = smu10_get_power_profile_mode,
1691 .set_power_profile_mode = smu10_set_power_profile_mode,
1692 .asic_reset = smu10_asic_reset,
1693 .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
1694 .gfx_state_change = smu10_gfx_state_change,
1695 };
1696
smu10_init_function_pointers(struct pp_hwmgr * hwmgr)1697 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1698 {
1699 hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1700 hwmgr->pptable_func = &pptable_funcs;
1701 return 0;
1702 }
1703