1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/atomic.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/firmware.h> 9 #include <linux/interrupt.h> 10 #include <linux/kobject.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/miscdevice.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/sched/signal.h> 21 #include <linux/sysfs.h> 22 #include <linux/types.h> 23 #include <linux/gcd.h> 24 #include <sound/dmaengine_pcm.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/tlv.h> 29 #include <sound/core.h> 30 31 #include "fsl_easrc.h" 32 #include "imx-pcm.h" 33 34 #define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 35 SNDRV_PCM_FMTBIT_U16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE | \ 37 SNDRV_PCM_FMTBIT_S24_3LE | \ 38 SNDRV_PCM_FMTBIT_U24_LE | \ 39 SNDRV_PCM_FMTBIT_U24_3LE | \ 40 SNDRV_PCM_FMTBIT_S32_LE | \ 41 SNDRV_PCM_FMTBIT_U32_LE | \ 42 SNDRV_PCM_FMTBIT_S20_3LE | \ 43 SNDRV_PCM_FMTBIT_U20_3LE | \ 44 SNDRV_PCM_FMTBIT_FLOAT_LE) 45 46 static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol, 47 struct snd_ctl_elem_value *ucontrol) 48 { 49 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 50 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp); 51 struct fsl_easrc_priv *easrc_priv = easrc->private; 52 struct soc_mreg_control *mc = 53 (struct soc_mreg_control *)kcontrol->private_value; 54 unsigned int regval = ucontrol->value.integer.value[0]; 55 int ret; 56 57 if (regval < EASRC_WIDTH_16_BIT || regval > EASRC_WIDTH_24_BIT) 58 return -EINVAL; 59 60 ret = (easrc_priv->bps_iec958[mc->regbase] != regval); 61 62 easrc_priv->bps_iec958[mc->regbase] = regval; 63 64 return ret; 65 } 66 67 static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol, 68 struct snd_ctl_elem_value *ucontrol) 69 { 70 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 71 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp); 72 struct fsl_easrc_priv *easrc_priv = easrc->private; 73 struct soc_mreg_control *mc = 74 (struct soc_mreg_control *)kcontrol->private_value; 75 76 ucontrol->value.integer.value[0] = easrc_priv->bps_iec958[mc->regbase]; 77 78 return 0; 79 } 80 81 static int fsl_easrc_iec958_info(struct snd_kcontrol *kcontrol, 82 struct snd_ctl_elem_info *uinfo) 83 { 84 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 85 uinfo->count = 1; 86 return 0; 87 } 88 89 static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol, 90 struct snd_ctl_elem_value *ucontrol) 91 { 92 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 93 struct soc_mreg_control *mc = 94 (struct soc_mreg_control *)kcontrol->private_value; 95 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(component); 96 unsigned int *regval = (unsigned int *)ucontrol->value.iec958.status; 97 int ret; 98 99 ret = regmap_read(easrc->regmap, REG_EASRC_CS0(mc->regbase), ®val[0]); 100 if (ret) 101 return ret; 102 103 ret = regmap_read(easrc->regmap, REG_EASRC_CS1(mc->regbase), ®val[1]); 104 if (ret) 105 return ret; 106 107 ret = regmap_read(easrc->regmap, REG_EASRC_CS2(mc->regbase), ®val[2]); 108 if (ret) 109 return ret; 110 111 ret = regmap_read(easrc->regmap, REG_EASRC_CS3(mc->regbase), ®val[3]); 112 if (ret) 113 return ret; 114 115 ret = regmap_read(easrc->regmap, REG_EASRC_CS4(mc->regbase), ®val[4]); 116 if (ret) 117 return ret; 118 119 ret = regmap_read(easrc->regmap, REG_EASRC_CS5(mc->regbase), ®val[5]); 120 if (ret) 121 return ret; 122 123 return 0; 124 } 125 126 static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol, 127 struct snd_ctl_elem_value *ucontrol) 128 { 129 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 130 struct soc_mreg_control *mc = 131 (struct soc_mreg_control *)kcontrol->private_value; 132 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(component); 133 unsigned int *regval = (unsigned int *)ucontrol->value.iec958.status; 134 bool changed, changed_all = false; 135 int ret; 136 137 ret = pm_runtime_resume_and_get(component->dev); 138 if (ret) 139 return ret; 140 141 ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS0(mc->regbase), 142 GENMASK(31, 0), regval[0], &changed); 143 if (ret != 0) 144 goto err; 145 changed_all |= changed; 146 147 ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS1(mc->regbase), 148 GENMASK(31, 0), regval[1], &changed); 149 if (ret != 0) 150 goto err; 151 changed_all |= changed; 152 153 ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS2(mc->regbase), 154 GENMASK(31, 0), regval[2], &changed); 155 if (ret != 0) 156 goto err; 157 changed_all |= changed; 158 159 ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS3(mc->regbase), 160 GENMASK(31, 0), regval[3], &changed); 161 if (ret != 0) 162 goto err; 163 changed_all |= changed; 164 165 ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS4(mc->regbase), 166 GENMASK(31, 0), regval[4], &changed); 167 if (ret != 0) 168 goto err; 169 changed_all |= changed; 170 171 ret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS5(mc->regbase), 172 GENMASK(31, 0), regval[5], &changed); 173 if (ret != 0) 174 goto err; 175 changed_all |= changed; 176 err: 177 pm_runtime_put_autosuspend(component->dev); 178 179 if (ret != 0) 180 return ret; 181 else 182 return changed_all; 183 } 184 185 #define SOC_SINGLE_REG_RW(xname, xreg) \ 186 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \ 187 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 188 .info = fsl_easrc_iec958_info, .get = fsl_easrc_get_reg, \ 189 .put = fsl_easrc_set_reg, \ 190 .private_value = (unsigned long)&(struct soc_mreg_control) \ 191 { .regbase = xreg, .regcount = 1, .nbits = 32, \ 192 .invert = 0, .min = 0, .max = 0xffffffff, } } 193 194 #define SOC_SINGLE_VAL_RW(xname, xreg) \ 195 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \ 196 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 197 .info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \ 198 .put = fsl_easrc_iec958_put_bits, \ 199 .private_value = (unsigned long)&(struct soc_mreg_control) \ 200 { .regbase = xreg, .regcount = 1, .nbits = 32, \ 201 .invert = 0, .min = 0, .max = 2, } } 202 203 static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = { 204 SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0), 205 SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0), 206 SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0), 207 SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0), 208 209 SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0), 210 SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0), 211 SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0), 212 SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0), 213 214 SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0), 215 SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1), 216 SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2), 217 SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3), 218 219 SOC_SINGLE_REG_RW("Context 0 IEC958 CS", 0), 220 SOC_SINGLE_REG_RW("Context 1 IEC958 CS", 1), 221 SOC_SINGLE_REG_RW("Context 2 IEC958 CS", 2), 222 SOC_SINGLE_REG_RW("Context 3 IEC958 CS", 3), 223 }; 224 225 /* 226 * fsl_easrc_set_rs_ratio 227 * 228 * According to the resample taps, calculate the resample ratio 229 * ratio = in_rate / out_rate 230 */ 231 static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx) 232 { 233 struct fsl_asrc *easrc = ctx->asrc; 234 struct fsl_easrc_priv *easrc_priv = easrc->private; 235 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 236 unsigned int in_rate = ctx_priv->in_params.norm_rate; 237 unsigned int out_rate = ctx_priv->out_params.norm_rate; 238 unsigned int frac_bits; 239 u64 val; 240 u32 *r; 241 242 switch (easrc_priv->rs_num_taps) { 243 case EASRC_RS_32_TAPS: 244 /* integer bits = 5; */ 245 frac_bits = 39; 246 break; 247 case EASRC_RS_64_TAPS: 248 /* integer bits = 6; */ 249 frac_bits = 38; 250 break; 251 case EASRC_RS_128_TAPS: 252 /* integer bits = 7; */ 253 frac_bits = 37; 254 break; 255 default: 256 return -EINVAL; 257 } 258 259 val = (u64)in_rate << frac_bits; 260 do_div(val, out_rate); 261 r = (uint32_t *)&val; 262 263 if (r[1] & 0xFFFFF000) { 264 dev_err(&easrc->pdev->dev, "ratio exceed range\n"); 265 return -EINVAL; 266 } 267 268 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index), 269 EASRC_RRL_RS_RL(r[0])); 270 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index), 271 EASRC_RRH_RS_RH(r[1])); 272 273 return 0; 274 } 275 276 /* Normalize input and output sample rates */ 277 static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx) 278 { 279 struct fsl_easrc_ctx_priv *ctx_priv; 280 int a, b; 281 282 if (!ctx) 283 return; 284 285 ctx_priv = ctx->private; 286 287 a = ctx_priv->in_params.sample_rate; 288 b = ctx_priv->out_params.sample_rate; 289 290 a = gcd(a, b); 291 292 /* Divide by gcd to normalize the rate */ 293 ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a; 294 ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a; 295 } 296 297 /* Resets the pointer of the coeff memory pointers */ 298 static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc, 299 unsigned int ctx_id, int mem_type) 300 { 301 struct device *dev; 302 u32 reg, mask, val; 303 304 if (!easrc) 305 return -ENODEV; 306 307 dev = &easrc->pdev->dev; 308 309 switch (mem_type) { 310 case EASRC_PF_COEFF_MEM: 311 /* This resets the prefilter memory pointer addr */ 312 if (ctx_id >= EASRC_CTX_MAX_NUM) { 313 dev_err(dev, "Invalid context id[%d]\n", ctx_id); 314 return -EINVAL; 315 } 316 317 reg = REG_EASRC_CCE1(ctx_id); 318 mask = EASRC_CCE1_COEF_MEM_RST_MASK; 319 val = EASRC_CCE1_COEF_MEM_RST; 320 break; 321 case EASRC_RS_COEFF_MEM: 322 /* This resets the resampling memory pointer addr */ 323 reg = REG_EASRC_CRCC; 324 mask = EASRC_CRCC_RS_CPR_MASK; 325 val = EASRC_CRCC_RS_CPR; 326 break; 327 default: 328 dev_err(dev, "Unknown memory type\n"); 329 return -EINVAL; 330 } 331 332 /* 333 * To reset the write pointer back to zero, the register field 334 * ASRC_CTX_CTRL_EXT1x[PF_COEFF_MEM_RST] can be toggled from 335 * 0x0 to 0x1 to 0x0. 336 */ 337 regmap_update_bits(easrc->regmap, reg, mask, 0); 338 regmap_update_bits(easrc->regmap, reg, mask, val); 339 regmap_update_bits(easrc->regmap, reg, mask, 0); 340 341 return 0; 342 } 343 344 static inline uint32_t bits_taps_to_val(unsigned int t) 345 { 346 switch (t) { 347 case EASRC_RS_32_TAPS: 348 return 32; 349 case EASRC_RS_64_TAPS: 350 return 64; 351 case EASRC_RS_128_TAPS: 352 return 128; 353 } 354 355 return 0; 356 } 357 358 static int fsl_easrc_resampler_config(struct fsl_asrc *easrc) 359 { 360 struct device *dev = &easrc->pdev->dev; 361 struct fsl_easrc_priv *easrc_priv = easrc->private; 362 struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr; 363 struct interp_params *interp = easrc_priv->interp; 364 struct interp_params *selected_interp = NULL; 365 unsigned int num_coeff; 366 unsigned int i; 367 u64 *coef; 368 u32 *r; 369 int ret; 370 371 if (!hdr) { 372 dev_err(dev, "firmware not loaded!\n"); 373 return -ENODEV; 374 } 375 376 for (i = 0; i < hdr->interp_scen; i++) { 377 if ((interp[i].num_taps - 1) != 378 bits_taps_to_val(easrc_priv->rs_num_taps)) 379 continue; 380 381 coef = interp[i].coeff; 382 selected_interp = &interp[i]; 383 dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n", 384 selected_interp->num_taps, 385 selected_interp->num_phases); 386 break; 387 } 388 389 if (!selected_interp) { 390 dev_err(dev, "failed to get interpreter configuration\n"); 391 return -EINVAL; 392 } 393 394 /* 395 * RS_LOW - first half of center tap of the sinc function 396 * RS_HIGH - second half of center tap of the sinc function 397 * This is due to the fact the resampling function must be 398 * symetrical - i.e. odd number of taps 399 */ 400 r = (uint32_t *)&selected_interp->center_tap; 401 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0])); 402 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1])); 403 404 /* 405 * Write Number of Resampling Coefficient Taps 406 * 00b - 32-Tap Resampling Filter 407 * 01b - 64-Tap Resampling Filter 408 * 10b - 128-Tap Resampling Filter 409 * 11b - N/A 410 */ 411 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC, 412 EASRC_CRCC_RS_TAPS_MASK, 413 EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps)); 414 415 /* Reset prefilter coefficient pointer back to 0 */ 416 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM); 417 if (ret) 418 return ret; 419 420 /* 421 * When the filter is programmed to run in: 422 * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase 423 * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase 424 * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase 425 * This means the number of writes is constant no matter 426 * the mode we are using 427 */ 428 num_coeff = 16 * 128 * 4; 429 430 for (i = 0; i < num_coeff; i++) { 431 r = (uint32_t *)&coef[i]; 432 regmap_write(easrc->regmap, REG_EASRC_CRCM, 433 EASRC_CRCM_RS_CWD(r[0])); 434 regmap_write(easrc->regmap, REG_EASRC_CRCM, 435 EASRC_CRCM_RS_CWD(r[1])); 436 } 437 438 return 0; 439 } 440 441 /** 442 * fsl_easrc_normalize_filter - Scale filter coefficients (64 bits float) 443 * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]: 444 * scale it by multiplying filter coefficients by 2^31 445 * For input int[16, 24, 32] -> output float32 446 * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31 447 * input: 448 * @easrc: Structure pointer of fsl_asrc 449 * @infilter : Pointer to non-scaled input filter 450 * @shift: The multiply factor 451 * output: 452 * @outfilter: scaled filter 453 */ 454 static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc, 455 u64 *infilter, 456 u64 *outfilter, 457 int shift) 458 { 459 struct device *dev = &easrc->pdev->dev; 460 u64 coef = *infilter; 461 s64 exp = (coef & 0x7ff0000000000000ll) >> 52; 462 u64 outcoef; 463 464 /* 465 * If exponent is zero (value == 0), or 7ff (value == NaNs) 466 * dont touch the content 467 */ 468 if (exp == 0 || exp == 0x7ff) { 469 *outfilter = coef; 470 return 0; 471 } 472 473 /* coef * 2^shift ==> exp + shift */ 474 exp += shift; 475 476 if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) { 477 dev_err(dev, "coef out of range\n"); 478 return -EINVAL; 479 } 480 481 outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52); 482 *outfilter = outcoef; 483 484 return 0; 485 } 486 487 static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id, 488 u64 *coef, int n_taps, int shift) 489 { 490 struct device *dev = &easrc->pdev->dev; 491 int ret = 0; 492 int i; 493 u32 *r; 494 u64 tmp; 495 496 /* If STx_NUM_TAPS is set to 0x0 then return */ 497 if (!n_taps) 498 return 0; 499 500 if (!coef) { 501 dev_err(dev, "coef table is NULL\n"); 502 return -EINVAL; 503 } 504 505 /* 506 * When switching between stages, the address pointer 507 * should be reset back to 0x0 before performing a write 508 */ 509 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM); 510 if (ret) 511 return ret; 512 513 for (i = 0; i < (n_taps + 1) / 2; i++) { 514 ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift); 515 if (ret) 516 return ret; 517 518 r = (uint32_t *)&tmp; 519 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), 520 EASRC_PCF_CD(r[0])); 521 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), 522 EASRC_PCF_CD(r[1])); 523 } 524 525 return 0; 526 } 527 528 static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc, 529 unsigned int ctx_id) 530 { 531 struct prefil_params *prefil, *selected_prefil = NULL; 532 struct fsl_easrc_ctx_priv *ctx_priv; 533 struct fsl_easrc_priv *easrc_priv; 534 struct asrc_firmware_hdr *hdr; 535 struct fsl_asrc_pair *ctx; 536 struct device *dev; 537 u32 inrate, outrate, offset = 0; 538 u32 in_s_rate, out_s_rate; 539 snd_pcm_format_t in_s_fmt, out_s_fmt; 540 int ret, i; 541 542 if (!easrc) 543 return -ENODEV; 544 545 dev = &easrc->pdev->dev; 546 547 if (ctx_id >= EASRC_CTX_MAX_NUM) { 548 dev_err(dev, "Invalid context id[%d]\n", ctx_id); 549 return -EINVAL; 550 } 551 552 easrc_priv = easrc->private; 553 554 ctx = easrc->pair[ctx_id]; 555 ctx_priv = ctx->private; 556 557 in_s_rate = ctx_priv->in_params.sample_rate; 558 out_s_rate = ctx_priv->out_params.sample_rate; 559 in_s_fmt = ctx_priv->in_params.sample_format; 560 out_s_fmt = ctx_priv->out_params.sample_format; 561 562 ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2; 563 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; 564 565 ctx_priv->st1_num_taps = 0; 566 ctx_priv->st2_num_taps = 0; 567 568 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0); 569 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0); 570 571 /* 572 * The audio float point data range is (-1, 1), the asrc would output 573 * all zero for float point input and integer output case, that is to 574 * drop the fractional part of the data directly. 575 * 576 * In order to support float to int conversion or int to float 577 * conversion we need to do special operation on the coefficient to 578 * enlarge/reduce the data to the expected range. 579 * 580 * For float to int case: 581 * Up sampling: 582 * 1. Create a 1 tap filter with center tap (only tap) of 2^31 583 * in 64 bits floating point. 584 * double value = (double)(((uint64_t)1) << 31) 585 * 2. Program 1 tap prefilter with center tap above. 586 * 587 * Down sampling, 588 * 1. If the filter is single stage filter, add "shift" to the exponent 589 * of stage 1 coefficients. 590 * 2. If the filter is two stage filter , add "shift" to the exponent 591 * of stage 2 coefficients. 592 * 593 * The "shift" is 31, same for int16, int24, int32 case. 594 * 595 * For int to float case: 596 * Up sampling: 597 * 1. Create a 1 tap filter with center tap (only tap) of 2^-31 598 * in 64 bits floating point. 599 * 2. Program 1 tap prefilter with center tap above. 600 * 601 * Down sampling, 602 * 1. If the filter is single stage filter, subtract "shift" to the 603 * exponent of stage 1 coefficients. 604 * 2. If the filter is two stage filter , subtract "shift" to the 605 * exponent of stage 2 coefficients. 606 * 607 * The "shift" is 15,23,31, different for int16, int24, int32 case. 608 * 609 */ 610 if (out_s_rate >= in_s_rate) { 611 if (out_s_rate == in_s_rate) 612 regmap_update_bits(easrc->regmap, 613 REG_EASRC_CCE1(ctx_id), 614 EASRC_CCE1_RS_BYPASS_MASK, 615 EASRC_CCE1_RS_BYPASS); 616 617 ctx_priv->st1_num_taps = 1; 618 ctx_priv->st1_coeff = &easrc_priv->const_coeff; 619 ctx_priv->st1_num_exp = 1; 620 ctx_priv->st2_num_taps = 0; 621 622 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE && 623 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) 624 ctx_priv->st1_addexp = 31; 625 else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE && 626 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) 627 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; 628 } else { 629 inrate = ctx_priv->in_params.norm_rate; 630 outrate = ctx_priv->out_params.norm_rate; 631 632 hdr = easrc_priv->firmware_hdr; 633 prefil = easrc_priv->prefil; 634 635 for (i = 0; i < hdr->prefil_scen; i++) { 636 if (inrate == prefil[i].insr && 637 outrate == prefil[i].outsr) { 638 selected_prefil = &prefil[i]; 639 dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n", 640 selected_prefil->insr, 641 selected_prefil->outsr, 642 selected_prefil->st1_taps, 643 selected_prefil->st2_taps); 644 break; 645 } 646 } 647 648 if (!selected_prefil) { 649 dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n", 650 in_s_rate, inrate, 651 out_s_rate, outrate); 652 return -EINVAL; 653 } 654 655 /* 656 * In prefilter coeff array, first st1_num_taps represent the 657 * stage1 prefilter coefficients followed by next st2_num_taps 658 * representing stage 2 coefficients 659 */ 660 ctx_priv->st1_num_taps = selected_prefil->st1_taps; 661 ctx_priv->st1_coeff = selected_prefil->coeff; 662 ctx_priv->st1_num_exp = selected_prefil->st1_exp; 663 664 offset = ((selected_prefil->st1_taps + 1) / 2); 665 ctx_priv->st2_num_taps = selected_prefil->st2_taps; 666 ctx_priv->st2_coeff = selected_prefil->coeff + offset; 667 668 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE && 669 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) { 670 /* only change stage2 coefficient for 2 stage case */ 671 if (ctx_priv->st2_num_taps > 0) 672 ctx_priv->st2_addexp = 31; 673 else 674 ctx_priv->st1_addexp = 31; 675 } else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE && 676 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) { 677 if (ctx_priv->st2_num_taps > 0) 678 ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp; 679 else 680 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; 681 } 682 } 683 684 ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp + 685 ctx_priv->st2_num_taps / 2; 686 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; 687 688 if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0) 689 ctx_priv->out_missed_sample += 1; 690 /* 691 * To modify the value of a prefilter coefficient, the user must 692 * perform a write to the register ASRC_PRE_COEFF_FIFOn[COEFF_DATA] 693 * while the respective context RUN_EN bit is set to 0b0 694 */ 695 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), 696 EASRC_CC_EN_MASK, 0); 697 698 if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { 699 dev_err(dev, "ST1 taps [%d] mus be lower than %d\n", 700 ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS); 701 ret = -EINVAL; 702 goto ctx_error; 703 } 704 705 /* Update ctx ST1_NUM_TAPS in Context Control Extended 2 register */ 706 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), 707 EASRC_CCE2_ST1_TAPS_MASK, 708 EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1)); 709 710 /* Prefilter Coefficient Write Select to write in ST1 coeff */ 711 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 712 EASRC_CCE1_COEF_WS_MASK, 713 EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT); 714 715 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id, 716 ctx_priv->st1_coeff, 717 ctx_priv->st1_num_taps, 718 ctx_priv->st1_addexp); 719 if (ret) 720 goto ctx_error; 721 722 if (ctx_priv->st2_num_taps > 0) { 723 if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { 724 dev_err(dev, "ST2 taps [%d] mus be lower than %d\n", 725 ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS); 726 ret = -EINVAL; 727 goto ctx_error; 728 } 729 730 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 731 EASRC_CCE1_PF_TSEN_MASK, 732 EASRC_CCE1_PF_TSEN); 733 /* 734 * Enable prefilter stage1 writeback floating point 735 * which is used for FLOAT_LE case 736 */ 737 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 738 EASRC_CCE1_PF_ST1_WBFP_MASK, 739 EASRC_CCE1_PF_ST1_WBFP); 740 741 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 742 EASRC_CCE1_PF_EXP_MASK, 743 EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1)); 744 745 /* Update ctx ST2_NUM_TAPS in Context Control Extended 2 reg */ 746 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), 747 EASRC_CCE2_ST2_TAPS_MASK, 748 EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1)); 749 750 /* Prefilter Coefficient Write Select to write in ST2 coeff */ 751 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 752 EASRC_CCE1_COEF_WS_MASK, 753 EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT); 754 755 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id, 756 ctx_priv->st2_coeff, 757 ctx_priv->st2_num_taps, 758 ctx_priv->st2_addexp); 759 if (ret) 760 goto ctx_error; 761 } 762 763 return 0; 764 765 ctx_error: 766 return ret; 767 } 768 769 static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx, 770 struct fsl_easrc_slot *slot) 771 { 772 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 773 int st1_mem_alloc = 0, st2_mem_alloc = 0; 774 int pf_mem_alloc = 0; 775 int max_channels = 8 - slot->num_channel; 776 int channels = 0; 777 778 if (ctx_priv->st1_num_taps > 0) { 779 if (ctx_priv->st2_num_taps > 0) 780 st1_mem_alloc = 781 (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1; 782 else 783 st1_mem_alloc = ctx_priv->st1_num_taps; 784 } 785 786 if (ctx_priv->st2_num_taps > 0) 787 st2_mem_alloc = ctx_priv->st2_num_taps; 788 789 pf_mem_alloc = st1_mem_alloc + st2_mem_alloc; 790 791 if (pf_mem_alloc != 0) 792 channels = (6144 - slot->pf_mem_used) / pf_mem_alloc; 793 else 794 channels = 8; 795 796 if (channels < max_channels) 797 max_channels = channels; 798 799 return max_channels; 800 } 801 802 static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx, 803 struct fsl_easrc_slot *slot, 804 unsigned int slot_ctx_idx, 805 unsigned int *req_channels, 806 unsigned int *start_channel, 807 unsigned int *avail_channel) 808 { 809 struct fsl_asrc *easrc = ctx->asrc; 810 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 811 int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc; 812 unsigned int reg0, reg1, reg2, reg3; 813 unsigned int addr; 814 815 if (slot->slot_index == 0) { 816 reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx); 817 reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx); 818 reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx); 819 reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx); 820 } else { 821 reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx); 822 reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx); 823 reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx); 824 reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx); 825 } 826 827 if (*req_channels <= *avail_channel) { 828 slot->num_channel = *req_channels; 829 *req_channels = 0; 830 } else { 831 slot->num_channel = *avail_channel; 832 *req_channels -= *avail_channel; 833 } 834 835 slot->min_channel = *start_channel; 836 slot->max_channel = *start_channel + slot->num_channel - 1; 837 slot->ctx_index = ctx->index; 838 slot->busy = true; 839 *start_channel += slot->num_channel; 840 841 regmap_update_bits(easrc->regmap, reg0, 842 EASRC_DPCS0R0_MAXCH_MASK, 843 EASRC_DPCS0R0_MAXCH(slot->max_channel)); 844 845 regmap_update_bits(easrc->regmap, reg0, 846 EASRC_DPCS0R0_MINCH_MASK, 847 EASRC_DPCS0R0_MINCH(slot->min_channel)); 848 849 regmap_update_bits(easrc->regmap, reg0, 850 EASRC_DPCS0R0_NUMCH_MASK, 851 EASRC_DPCS0R0_NUMCH(slot->num_channel - 1)); 852 853 regmap_update_bits(easrc->regmap, reg0, 854 EASRC_DPCS0R0_CTXNUM_MASK, 855 EASRC_DPCS0R0_CTXNUM(slot->ctx_index)); 856 857 if (ctx_priv->st1_num_taps > 0) { 858 if (ctx_priv->st2_num_taps > 0) 859 st1_mem_alloc = 860 (ctx_priv->st1_num_taps - 1) * slot->num_channel * 861 ctx_priv->st1_num_exp + slot->num_channel; 862 else 863 st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel; 864 865 slot->pf_mem_used = st1_mem_alloc; 866 regmap_update_bits(easrc->regmap, reg2, 867 EASRC_DPCS0R2_ST1_MA_MASK, 868 EASRC_DPCS0R2_ST1_MA(st1_mem_alloc)); 869 870 if (slot->slot_index == 1) 871 addr = PREFILTER_MEM_LEN - st1_mem_alloc; 872 else 873 addr = 0; 874 875 regmap_update_bits(easrc->regmap, reg2, 876 EASRC_DPCS0R2_ST1_SA_MASK, 877 EASRC_DPCS0R2_ST1_SA(addr)); 878 } 879 880 if (ctx_priv->st2_num_taps > 0) { 881 st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1); 882 883 regmap_update_bits(easrc->regmap, reg1, 884 EASRC_DPCS0R1_ST1_EXP_MASK, 885 EASRC_DPCS0R1_ST1_EXP(st1_chanxexp)); 886 887 st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps; 888 slot->pf_mem_used += st2_mem_alloc; 889 regmap_update_bits(easrc->regmap, reg3, 890 EASRC_DPCS0R3_ST2_MA_MASK, 891 EASRC_DPCS0R3_ST2_MA(st2_mem_alloc)); 892 893 if (slot->slot_index == 1) 894 addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc; 895 else 896 addr = st1_mem_alloc; 897 898 regmap_update_bits(easrc->regmap, reg3, 899 EASRC_DPCS0R3_ST2_SA_MASK, 900 EASRC_DPCS0R3_ST2_SA(addr)); 901 } 902 903 regmap_update_bits(easrc->regmap, reg0, 904 EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN); 905 906 return 0; 907 } 908 909 /* 910 * fsl_easrc_config_slot 911 * 912 * A single context can be split amongst any of the 4 context processing pipes 913 * in the design. 914 * The total number of channels consumed within the context processor must be 915 * less than or equal to 8. if a single context is configured to contain more 916 * than 8 channels then it must be distributed across multiple context 917 * processing pipe slots. 918 * 919 */ 920 static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id) 921 { 922 struct fsl_easrc_priv *easrc_priv = easrc->private; 923 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; 924 int req_channels = ctx->channels; 925 int start_channel = 0, avail_channel; 926 struct fsl_easrc_slot *slot0, *slot1; 927 struct fsl_easrc_slot *slota, *slotb; 928 int i, ret; 929 930 if (req_channels <= 0) 931 return -EINVAL; 932 933 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) { 934 slot0 = &easrc_priv->slot[i][0]; 935 slot1 = &easrc_priv->slot[i][1]; 936 937 if (slot0->busy && slot1->busy) { 938 continue; 939 } else if ((slot0->busy && slot0->ctx_index == ctx->index) || 940 (slot1->busy && slot1->ctx_index == ctx->index)) { 941 continue; 942 } else if (!slot0->busy) { 943 slota = slot0; 944 slotb = slot1; 945 slota->slot_index = 0; 946 } else if (!slot1->busy) { 947 slota = slot1; 948 slotb = slot0; 949 slota->slot_index = 1; 950 } 951 952 if (!slota || !slotb) 953 continue; 954 955 avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb); 956 if (avail_channel <= 0) 957 continue; 958 959 ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels, 960 &start_channel, &avail_channel); 961 if (ret) 962 return ret; 963 964 if (req_channels > 0) 965 continue; 966 else 967 break; 968 } 969 970 if (req_channels > 0) { 971 dev_err(&easrc->pdev->dev, "no avail slot.\n"); 972 return -EINVAL; 973 } 974 975 return 0; 976 } 977 978 /* 979 * fsl_easrc_release_slot 980 * 981 * Clear the slot configuration 982 */ 983 static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id) 984 { 985 struct fsl_easrc_priv *easrc_priv = easrc->private; 986 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; 987 int i; 988 989 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) { 990 if (easrc_priv->slot[i][0].busy && 991 easrc_priv->slot[i][0].ctx_index == ctx->index) { 992 easrc_priv->slot[i][0].busy = false; 993 easrc_priv->slot[i][0].num_channel = 0; 994 easrc_priv->slot[i][0].pf_mem_used = 0; 995 /* set registers */ 996 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0); 997 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0); 998 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0); 999 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0); 1000 } 1001 1002 if (easrc_priv->slot[i][1].busy && 1003 easrc_priv->slot[i][1].ctx_index == ctx->index) { 1004 easrc_priv->slot[i][1].busy = false; 1005 easrc_priv->slot[i][1].num_channel = 0; 1006 easrc_priv->slot[i][1].pf_mem_used = 0; 1007 /* set registers */ 1008 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0); 1009 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0); 1010 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0); 1011 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0); 1012 } 1013 } 1014 1015 return 0; 1016 } 1017 1018 /* 1019 * fsl_easrc_config_context 1020 * 1021 * Configure the register relate with context. 1022 */ 1023 static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id) 1024 { 1025 struct fsl_easrc_ctx_priv *ctx_priv; 1026 struct fsl_asrc_pair *ctx; 1027 struct device *dev; 1028 int ret; 1029 1030 if (!easrc) 1031 return -ENODEV; 1032 1033 dev = &easrc->pdev->dev; 1034 1035 if (ctx_id >= EASRC_CTX_MAX_NUM) { 1036 dev_err(dev, "Invalid context id[%d]\n", ctx_id); 1037 return -EINVAL; 1038 } 1039 1040 ctx = easrc->pair[ctx_id]; 1041 1042 ctx_priv = ctx->private; 1043 1044 fsl_easrc_normalize_rates(ctx); 1045 1046 ret = fsl_easrc_set_rs_ratio(ctx); 1047 if (ret) 1048 return ret; 1049 1050 /* Initialize the context coeficients */ 1051 ret = fsl_easrc_prefilter_config(easrc, ctx->index); 1052 if (ret) 1053 return ret; 1054 1055 scoped_guard(spinlock_irqsave, &easrc->lock) 1056 ret = fsl_easrc_config_slot(easrc, ctx->index); 1057 if (ret) 1058 return ret; 1059 1060 /* 1061 * Both prefilter and resampling filters can use following 1062 * initialization modes: 1063 * 2 - zero-fil mode 1064 * 1 - replication mode 1065 * 0 - software control 1066 */ 1067 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 1068 EASRC_CCE1_RS_INIT_MASK, 1069 EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode)); 1070 1071 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 1072 EASRC_CCE1_PF_INIT_MASK, 1073 EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode)); 1074 1075 /* 1076 * Context Input FIFO Watermark 1077 * DMA request is generated when input FIFO < FIFO_WTMK 1078 */ 1079 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), 1080 EASRC_CC_FIFO_WTMK_MASK, 1081 EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk)); 1082 1083 /* 1084 * Context Output FIFO Watermark 1085 * DMA request is generated when output FIFO > FIFO_WTMK 1086 * So we set fifo_wtmk -1 to register. 1087 */ 1088 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id), 1089 EASRC_COC_FIFO_WTMK_MASK, 1090 EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1)); 1091 1092 /* Number of channels */ 1093 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), 1094 EASRC_CC_CHEN_MASK, 1095 EASRC_CC_CHEN(ctx->channels - 1)); 1096 return 0; 1097 } 1098 1099 static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx, 1100 struct fsl_easrc_data_fmt *fmt, 1101 snd_pcm_format_t raw_fmt) 1102 { 1103 struct fsl_asrc *easrc = ctx->asrc; 1104 struct fsl_easrc_priv *easrc_priv = easrc->private; 1105 int ret; 1106 1107 if (!fmt) 1108 return -EINVAL; 1109 1110 /* 1111 * Context Input Floating Point Format 1112 * 0 - Integer Format 1113 * 1 - Single Precision FP Format 1114 */ 1115 fmt->floating_point = !snd_pcm_format_linear(raw_fmt); 1116 fmt->sample_pos = 0; 1117 fmt->iec958 = 0; 1118 1119 /* Get the data width */ 1120 switch (snd_pcm_format_width(raw_fmt)) { 1121 case 16: 1122 fmt->width = EASRC_WIDTH_16_BIT; 1123 fmt->addexp = 15; 1124 break; 1125 case 20: 1126 fmt->width = EASRC_WIDTH_20_BIT; 1127 fmt->addexp = 19; 1128 break; 1129 case 24: 1130 fmt->width = EASRC_WIDTH_24_BIT; 1131 fmt->addexp = 23; 1132 break; 1133 case 32: 1134 fmt->width = EASRC_WIDTH_32_BIT; 1135 fmt->addexp = 31; 1136 break; 1137 default: 1138 return -EINVAL; 1139 } 1140 1141 switch (raw_fmt) { 1142 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 1143 fmt->width = easrc_priv->bps_iec958[ctx->index]; 1144 fmt->iec958 = 1; 1145 fmt->floating_point = 0; 1146 if (fmt->width == EASRC_WIDTH_16_BIT) { 1147 fmt->sample_pos = 12; 1148 fmt->addexp = 15; 1149 } else if (fmt->width == EASRC_WIDTH_20_BIT) { 1150 fmt->sample_pos = 8; 1151 fmt->addexp = 19; 1152 } else if (fmt->width == EASRC_WIDTH_24_BIT) { 1153 fmt->sample_pos = 4; 1154 fmt->addexp = 23; 1155 } 1156 break; 1157 default: 1158 break; 1159 } 1160 1161 /* 1162 * Data Endianness 1163 * 0 - Little-Endian 1164 * 1 - Big-Endian 1165 */ 1166 ret = snd_pcm_format_big_endian(raw_fmt); 1167 if (ret < 0) 1168 return ret; 1169 1170 fmt->endianness = ret; 1171 1172 /* 1173 * Input Data sign 1174 * 0b - Signed Format 1175 * 1b - Unsigned Format 1176 */ 1177 fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0; 1178 1179 return 0; 1180 } 1181 1182 static int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx, 1183 snd_pcm_format_t *in_raw_format, 1184 snd_pcm_format_t *out_raw_format) 1185 { 1186 struct fsl_asrc *easrc = ctx->asrc; 1187 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 1188 struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt; 1189 struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt; 1190 int ret = 0; 1191 1192 /* Get the bitfield values for input data format */ 1193 if (in_raw_format && out_raw_format) { 1194 ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format); 1195 if (ret) 1196 return ret; 1197 } 1198 1199 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1200 EASRC_CC_BPS_MASK, 1201 EASRC_CC_BPS(in_fmt->width)); 1202 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1203 EASRC_CC_ENDIANNESS_MASK, 1204 in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT); 1205 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1206 EASRC_CC_FMT_MASK, 1207 in_fmt->floating_point << EASRC_CC_FMT_SHIFT); 1208 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1209 EASRC_CC_INSIGN_MASK, 1210 in_fmt->unsign << EASRC_CC_INSIGN_SHIFT); 1211 1212 /* In Sample Position */ 1213 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1214 EASRC_CC_SAMPLE_POS_MASK, 1215 EASRC_CC_SAMPLE_POS(in_fmt->sample_pos)); 1216 1217 /* Get the bitfield values for input data format */ 1218 if (in_raw_format && out_raw_format) { 1219 ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format); 1220 if (ret) 1221 return ret; 1222 } 1223 1224 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1225 EASRC_COC_BPS_MASK, 1226 EASRC_COC_BPS(out_fmt->width)); 1227 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1228 EASRC_COC_ENDIANNESS_MASK, 1229 out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT); 1230 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1231 EASRC_COC_FMT_MASK, 1232 out_fmt->floating_point << EASRC_COC_FMT_SHIFT); 1233 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1234 EASRC_COC_OUTSIGN_MASK, 1235 out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT); 1236 1237 /* Out Sample Position */ 1238 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1239 EASRC_COC_SAMPLE_POS_MASK, 1240 EASRC_COC_SAMPLE_POS(out_fmt->sample_pos)); 1241 1242 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1243 EASRC_COC_IEC_EN_MASK, 1244 out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT); 1245 1246 return ret; 1247 } 1248 1249 /* 1250 * The ASRC provides interleaving support in hardware to ensure that a 1251 * variety of sample sources can be internally combined 1252 * to conform with this format. Interleaving parameters are accessed 1253 * through the ASRC_CTRL_IN_ACCESSa and ASRC_CTRL_OUT_ACCESSa registers 1254 */ 1255 static int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx) 1256 { 1257 struct fsl_easrc_ctx_priv *ctx_priv; 1258 struct fsl_asrc *easrc; 1259 1260 if (!ctx) 1261 return -ENODEV; 1262 1263 easrc = ctx->asrc; 1264 ctx_priv = ctx->private; 1265 1266 /* input interleaving parameters */ 1267 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), 1268 EASRC_CIA_ITER_MASK, 1269 EASRC_CIA_ITER(ctx_priv->in_params.iterations)); 1270 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), 1271 EASRC_CIA_GRLEN_MASK, 1272 EASRC_CIA_GRLEN(ctx_priv->in_params.group_len)); 1273 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), 1274 EASRC_CIA_ACCLEN_MASK, 1275 EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len)); 1276 1277 /* output interleaving parameters */ 1278 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), 1279 EASRC_COA_ITER_MASK, 1280 EASRC_COA_ITER(ctx_priv->out_params.iterations)); 1281 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), 1282 EASRC_COA_GRLEN_MASK, 1283 EASRC_COA_GRLEN(ctx_priv->out_params.group_len)); 1284 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), 1285 EASRC_COA_ACCLEN_MASK, 1286 EASRC_COA_ACCLEN(ctx_priv->out_params.access_len)); 1287 1288 return 0; 1289 } 1290 1291 /* 1292 * Request one of the available contexts 1293 * 1294 * Returns a negative number on error and >=0 as context id 1295 * on success 1296 */ 1297 static int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx) 1298 { 1299 enum asrc_pair_index index = ASRC_INVALID_PAIR; 1300 struct fsl_asrc *easrc = ctx->asrc; 1301 struct device *dev; 1302 int ret = 0; 1303 int i; 1304 1305 dev = &easrc->pdev->dev; 1306 1307 guard(spinlock_irqsave)(&easrc->lock); 1308 1309 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) { 1310 if (easrc->pair[i]) 1311 continue; 1312 1313 index = i; 1314 break; 1315 } 1316 1317 if (index == ASRC_INVALID_PAIR) { 1318 dev_err(dev, "all contexts are busy\n"); 1319 ret = -EBUSY; 1320 } else if (channels > easrc->channel_avail) { 1321 dev_err(dev, "can't give the required channels: %d\n", 1322 channels); 1323 ret = -EINVAL; 1324 } else { 1325 ctx->index = index; 1326 ctx->channels = channels; 1327 easrc->pair[index] = ctx; 1328 easrc->channel_avail -= channels; 1329 } 1330 1331 return ret; 1332 } 1333 1334 /* 1335 * Release the context 1336 * 1337 * This function is mainly doing the revert thing in request context 1338 */ 1339 static void fsl_easrc_release_context(struct fsl_asrc_pair *ctx) 1340 { 1341 struct fsl_asrc *easrc; 1342 1343 if (!ctx) 1344 return; 1345 1346 easrc = ctx->asrc; 1347 1348 guard(spinlock_irqsave)(&easrc->lock); 1349 1350 fsl_easrc_release_slot(easrc, ctx->index); 1351 1352 easrc->channel_avail += ctx->channels; 1353 easrc->pair[ctx->index] = NULL; 1354 } 1355 1356 /* 1357 * Start the context 1358 * 1359 * Enable the DMA request and context 1360 */ 1361 static int fsl_easrc_start_context(struct fsl_asrc_pair *ctx) 1362 { 1363 struct fsl_asrc *easrc = ctx->asrc; 1364 1365 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1366 EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE); 1367 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1368 EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE); 1369 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1370 EASRC_CC_EN_MASK, EASRC_CC_EN); 1371 return 0; 1372 } 1373 1374 /* 1375 * Stop the context 1376 * 1377 * Disable the DMA request and context 1378 */ 1379 static int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx) 1380 { 1381 struct fsl_asrc *easrc = ctx->asrc; 1382 int val, i; 1383 int size; 1384 int retry = 200; 1385 1386 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val); 1387 1388 if (val & EASRC_CC_EN_MASK) { 1389 regmap_update_bits(easrc->regmap, 1390 REG_EASRC_CC(ctx->index), 1391 EASRC_CC_STOP_MASK, EASRC_CC_STOP); 1392 do { 1393 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val); 1394 val &= EASRC_SFS_NSGO_MASK; 1395 size = val >> EASRC_SFS_NSGO_SHIFT; 1396 1397 /* Read FIFO, drop the data */ 1398 for (i = 0; i < size * ctx->channels; i++) 1399 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val); 1400 /* Check RUN_STOP_DONE */ 1401 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); 1402 if (val & EASRC_IRQF_RSD(1 << ctx->index)) { 1403 /*Clear RUN_STOP_DONE*/ 1404 regmap_write_bits(easrc->regmap, 1405 REG_EASRC_IRQF, 1406 EASRC_IRQF_RSD(1 << ctx->index), 1407 EASRC_IRQF_RSD(1 << ctx->index)); 1408 break; 1409 } 1410 udelay(100); 1411 } while (--retry); 1412 1413 if (retry == 0) 1414 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n"); 1415 } 1416 1417 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1418 EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0); 1419 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1420 EASRC_CC_FWMDE_MASK, 0); 1421 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1422 EASRC_COC_FWMDE_MASK, 0); 1423 return 0; 1424 } 1425 1426 static struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx, 1427 bool dir) 1428 { 1429 struct fsl_asrc *easrc = ctx->asrc; 1430 enum asrc_pair_index index = ctx->index; 1431 char name[8]; 1432 1433 /* Example of dma name: ctx0_rx */ 1434 sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't'); 1435 1436 return dma_request_chan(&easrc->pdev->dev, name); 1437 }; 1438 1439 static const unsigned int easrc_rates[] = { 1440 8000, 11025, 12000, 16000, 1441 22050, 24000, 32000, 44100, 1442 48000, 64000, 88200, 96000, 1443 128000, 176400, 192000, 256000, 1444 352800, 384000, 705600, 768000, 1445 }; 1446 1447 static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = { 1448 .count = ARRAY_SIZE(easrc_rates), 1449 .list = easrc_rates, 1450 }; 1451 1452 static int fsl_easrc_startup(struct snd_pcm_substream *substream, 1453 struct snd_soc_dai *dai) 1454 { 1455 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1456 SNDRV_PCM_HW_PARAM_RATE, 1457 &easrc_rate_constraints); 1458 } 1459 1460 static int fsl_easrc_trigger(struct snd_pcm_substream *substream, 1461 int cmd, struct snd_soc_dai *dai) 1462 { 1463 struct snd_pcm_runtime *runtime = substream->runtime; 1464 struct fsl_asrc_pair *ctx = runtime->private_data; 1465 int ret; 1466 1467 switch (cmd) { 1468 case SNDRV_PCM_TRIGGER_START: 1469 case SNDRV_PCM_TRIGGER_RESUME: 1470 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1471 ret = fsl_easrc_start_context(ctx); 1472 if (ret) 1473 return ret; 1474 break; 1475 case SNDRV_PCM_TRIGGER_STOP: 1476 case SNDRV_PCM_TRIGGER_SUSPEND: 1477 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1478 ret = fsl_easrc_stop_context(ctx); 1479 if (ret) 1480 return ret; 1481 break; 1482 default: 1483 return -EINVAL; 1484 } 1485 1486 return 0; 1487 } 1488 1489 static int fsl_easrc_hw_params(struct snd_pcm_substream *substream, 1490 struct snd_pcm_hw_params *params, 1491 struct snd_soc_dai *dai) 1492 { 1493 struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai); 1494 struct snd_pcm_runtime *runtime = substream->runtime; 1495 struct device *dev = &easrc->pdev->dev; 1496 struct fsl_asrc_pair *ctx = runtime->private_data; 1497 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 1498 unsigned int channels = params_channels(params); 1499 unsigned int rate = params_rate(params); 1500 snd_pcm_format_t format = params_format(params); 1501 int ret; 1502 1503 ret = fsl_easrc_request_context(channels, ctx); 1504 if (ret) { 1505 dev_err(dev, "failed to request context\n"); 1506 return ret; 1507 } 1508 1509 ctx_priv->ctx_streams |= BIT(substream->stream); 1510 1511 /* 1512 * Set the input and output ratio so we can compute 1513 * the resampling ratio in RS_LOW/HIGH 1514 */ 1515 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1516 ctx_priv->in_params.sample_rate = rate; 1517 ctx_priv->in_params.sample_format = format; 1518 ctx_priv->out_params.sample_rate = easrc->asrc_rate; 1519 ctx_priv->out_params.sample_format = easrc->asrc_format; 1520 } else { 1521 ctx_priv->out_params.sample_rate = rate; 1522 ctx_priv->out_params.sample_format = format; 1523 ctx_priv->in_params.sample_rate = easrc->asrc_rate; 1524 ctx_priv->in_params.sample_format = easrc->asrc_format; 1525 } 1526 1527 ctx->channels = channels; 1528 ctx_priv->in_params.fifo_wtmk = 0x20; 1529 ctx_priv->out_params.fifo_wtmk = 0x20; 1530 1531 /* 1532 * Do only rate conversion and keep the same format for input 1533 * and output data 1534 */ 1535 ret = fsl_easrc_set_ctx_format(ctx, 1536 &ctx_priv->in_params.sample_format, 1537 &ctx_priv->out_params.sample_format); 1538 if (ret) { 1539 dev_err(dev, "failed to set format %d", ret); 1540 return ret; 1541 } 1542 1543 ret = fsl_easrc_config_context(easrc, ctx->index); 1544 if (ret) { 1545 dev_err(dev, "failed to config context\n"); 1546 return ret; 1547 } 1548 1549 ctx_priv->in_params.iterations = 1; 1550 ctx_priv->in_params.group_len = ctx->channels; 1551 ctx_priv->in_params.access_len = ctx->channels; 1552 ctx_priv->out_params.iterations = 1; 1553 ctx_priv->out_params.group_len = ctx->channels; 1554 ctx_priv->out_params.access_len = ctx->channels; 1555 1556 ret = fsl_easrc_set_ctx_organziation(ctx); 1557 if (ret) { 1558 dev_err(dev, "failed to set fifo organization\n"); 1559 return ret; 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int fsl_easrc_hw_free(struct snd_pcm_substream *substream, 1566 struct snd_soc_dai *dai) 1567 { 1568 struct snd_pcm_runtime *runtime = substream->runtime; 1569 struct fsl_asrc_pair *ctx = runtime->private_data; 1570 struct fsl_easrc_ctx_priv *ctx_priv; 1571 1572 if (!ctx) 1573 return -EINVAL; 1574 1575 ctx_priv = ctx->private; 1576 1577 if (ctx_priv->ctx_streams & BIT(substream->stream)) { 1578 ctx_priv->ctx_streams &= ~BIT(substream->stream); 1579 fsl_easrc_release_context(ctx); 1580 } 1581 1582 return 0; 1583 } 1584 1585 static const struct snd_soc_dai_ops fsl_easrc_dai_ops = { 1586 .startup = fsl_easrc_startup, 1587 .trigger = fsl_easrc_trigger, 1588 .hw_params = fsl_easrc_hw_params, 1589 .hw_free = fsl_easrc_hw_free, 1590 }; 1591 1592 static struct snd_soc_dai_driver fsl_easrc_dai[] = { 1593 { 1594 .name = "easrc-0", 1595 .playback = { 1596 .stream_name = "ASRC-Playback", 1597 .channels_min = 1, 1598 .channels_max = 32, 1599 .rate_min = 8000, 1600 .rate_max = 768000, 1601 .rates = SNDRV_PCM_RATE_KNOT, 1602 .formats = FSL_EASRC_FORMATS, 1603 }, 1604 .capture = { 1605 .stream_name = "ASRC-Capture", 1606 .channels_min = 1, 1607 .channels_max = 32, 1608 .rate_min = 8000, 1609 .rate_max = 768000, 1610 .rates = SNDRV_PCM_RATE_KNOT, 1611 .formats = FSL_EASRC_FORMATS | 1612 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1613 }, 1614 .ops = &fsl_easrc_dai_ops, 1615 }, 1616 { 1617 .name = "easrc-1", 1618 .playback = { 1619 .stream_name = "ASRC1-Playback", 1620 .channels_min = 1, 1621 .channels_max = 32, 1622 .rate_min = 8000, 1623 .rate_max = 768000, 1624 .rates = SNDRV_PCM_RATE_KNOT, 1625 .formats = FSL_EASRC_FORMATS, 1626 }, 1627 .capture = { 1628 .stream_name = "ASRC1-Capture", 1629 .channels_min = 1, 1630 .channels_max = 32, 1631 .rate_min = 8000, 1632 .rate_max = 768000, 1633 .rates = SNDRV_PCM_RATE_KNOT, 1634 .formats = FSL_EASRC_FORMATS | 1635 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1636 }, 1637 .ops = &fsl_easrc_dai_ops, 1638 }, 1639 { 1640 .name = "easrc-2", 1641 .playback = { 1642 .stream_name = "ASRC2-Playback", 1643 .channels_min = 1, 1644 .channels_max = 32, 1645 .rate_min = 8000, 1646 .rate_max = 768000, 1647 .rates = SNDRV_PCM_RATE_KNOT, 1648 .formats = FSL_EASRC_FORMATS, 1649 }, 1650 .capture = { 1651 .stream_name = "ASRC2-Capture", 1652 .channels_min = 1, 1653 .channels_max = 32, 1654 .rate_min = 8000, 1655 .rate_max = 768000, 1656 .rates = SNDRV_PCM_RATE_KNOT, 1657 .formats = FSL_EASRC_FORMATS | 1658 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1659 }, 1660 .ops = &fsl_easrc_dai_ops, 1661 }, 1662 { 1663 .name = "easrc-3", 1664 .playback = { 1665 .stream_name = "ASRC3-Playback", 1666 .channels_min = 1, 1667 .channels_max = 32, 1668 .rate_min = 8000, 1669 .rate_max = 768000, 1670 .rates = SNDRV_PCM_RATE_KNOT, 1671 .formats = FSL_EASRC_FORMATS, 1672 }, 1673 .capture = { 1674 .stream_name = "ASRC3-Capture", 1675 .channels_min = 1, 1676 .channels_max = 32, 1677 .rate_min = 8000, 1678 .rate_max = 768000, 1679 .rates = SNDRV_PCM_RATE_KNOT, 1680 .formats = FSL_EASRC_FORMATS | 1681 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1682 }, 1683 .ops = &fsl_easrc_dai_ops, 1684 }, 1685 }; 1686 1687 static const struct snd_soc_component_driver fsl_easrc_component = { 1688 .name = "fsl-easrc-dai", 1689 .controls = fsl_easrc_snd_controls, 1690 .num_controls = ARRAY_SIZE(fsl_easrc_snd_controls), 1691 .legacy_dai_naming = 1, 1692 #ifdef CONFIG_DEBUG_FS 1693 .debugfs_prefix = "easrc", 1694 #endif 1695 }; 1696 1697 static const struct reg_default fsl_easrc_reg_defaults[] = { 1698 {REG_EASRC_WRFIFO(0), 0x00000000}, 1699 {REG_EASRC_WRFIFO(1), 0x00000000}, 1700 {REG_EASRC_WRFIFO(2), 0x00000000}, 1701 {REG_EASRC_WRFIFO(3), 0x00000000}, 1702 {REG_EASRC_RDFIFO(0), 0x00000000}, 1703 {REG_EASRC_RDFIFO(1), 0x00000000}, 1704 {REG_EASRC_RDFIFO(2), 0x00000000}, 1705 {REG_EASRC_RDFIFO(3), 0x00000000}, 1706 {REG_EASRC_CC(0), 0x00000000}, 1707 {REG_EASRC_CC(1), 0x00000000}, 1708 {REG_EASRC_CC(2), 0x00000000}, 1709 {REG_EASRC_CC(3), 0x00000000}, 1710 {REG_EASRC_CCE1(0), 0x00000000}, 1711 {REG_EASRC_CCE1(1), 0x00000000}, 1712 {REG_EASRC_CCE1(2), 0x00000000}, 1713 {REG_EASRC_CCE1(3), 0x00000000}, 1714 {REG_EASRC_CCE2(0), 0x00000000}, 1715 {REG_EASRC_CCE2(1), 0x00000000}, 1716 {REG_EASRC_CCE2(2), 0x00000000}, 1717 {REG_EASRC_CCE2(3), 0x00000000}, 1718 {REG_EASRC_CIA(0), 0x00000000}, 1719 {REG_EASRC_CIA(1), 0x00000000}, 1720 {REG_EASRC_CIA(2), 0x00000000}, 1721 {REG_EASRC_CIA(3), 0x00000000}, 1722 {REG_EASRC_DPCS0R0(0), 0x00000000}, 1723 {REG_EASRC_DPCS0R0(1), 0x00000000}, 1724 {REG_EASRC_DPCS0R0(2), 0x00000000}, 1725 {REG_EASRC_DPCS0R0(3), 0x00000000}, 1726 {REG_EASRC_DPCS0R1(0), 0x00000000}, 1727 {REG_EASRC_DPCS0R1(1), 0x00000000}, 1728 {REG_EASRC_DPCS0R1(2), 0x00000000}, 1729 {REG_EASRC_DPCS0R1(3), 0x00000000}, 1730 {REG_EASRC_DPCS0R2(0), 0x00000000}, 1731 {REG_EASRC_DPCS0R2(1), 0x00000000}, 1732 {REG_EASRC_DPCS0R2(2), 0x00000000}, 1733 {REG_EASRC_DPCS0R2(3), 0x00000000}, 1734 {REG_EASRC_DPCS0R3(0), 0x00000000}, 1735 {REG_EASRC_DPCS0R3(1), 0x00000000}, 1736 {REG_EASRC_DPCS0R3(2), 0x00000000}, 1737 {REG_EASRC_DPCS0R3(3), 0x00000000}, 1738 {REG_EASRC_DPCS1R0(0), 0x00000000}, 1739 {REG_EASRC_DPCS1R0(1), 0x00000000}, 1740 {REG_EASRC_DPCS1R0(2), 0x00000000}, 1741 {REG_EASRC_DPCS1R0(3), 0x00000000}, 1742 {REG_EASRC_DPCS1R1(0), 0x00000000}, 1743 {REG_EASRC_DPCS1R1(1), 0x00000000}, 1744 {REG_EASRC_DPCS1R1(2), 0x00000000}, 1745 {REG_EASRC_DPCS1R1(3), 0x00000000}, 1746 {REG_EASRC_DPCS1R2(0), 0x00000000}, 1747 {REG_EASRC_DPCS1R2(1), 0x00000000}, 1748 {REG_EASRC_DPCS1R2(2), 0x00000000}, 1749 {REG_EASRC_DPCS1R2(3), 0x00000000}, 1750 {REG_EASRC_DPCS1R3(0), 0x00000000}, 1751 {REG_EASRC_DPCS1R3(1), 0x00000000}, 1752 {REG_EASRC_DPCS1R3(2), 0x00000000}, 1753 {REG_EASRC_DPCS1R3(3), 0x00000000}, 1754 {REG_EASRC_COC(0), 0x00000000}, 1755 {REG_EASRC_COC(1), 0x00000000}, 1756 {REG_EASRC_COC(2), 0x00000000}, 1757 {REG_EASRC_COC(3), 0x00000000}, 1758 {REG_EASRC_COA(0), 0x00000000}, 1759 {REG_EASRC_COA(1), 0x00000000}, 1760 {REG_EASRC_COA(2), 0x00000000}, 1761 {REG_EASRC_COA(3), 0x00000000}, 1762 {REG_EASRC_SFS(0), 0x00000000}, 1763 {REG_EASRC_SFS(1), 0x00000000}, 1764 {REG_EASRC_SFS(2), 0x00000000}, 1765 {REG_EASRC_SFS(3), 0x00000000}, 1766 {REG_EASRC_RRL(0), 0x00000000}, 1767 {REG_EASRC_RRH(0), 0x00000000}, 1768 {REG_EASRC_RRL(1), 0x00000000}, 1769 {REG_EASRC_RRH(1), 0x00000000}, 1770 {REG_EASRC_RRL(2), 0x00000000}, 1771 {REG_EASRC_RRH(2), 0x00000000}, 1772 {REG_EASRC_RRL(3), 0x00000000}, 1773 {REG_EASRC_RRH(3), 0x00000000}, 1774 {REG_EASRC_RUC(0), 0x00000000}, 1775 {REG_EASRC_RUC(1), 0x00000000}, 1776 {REG_EASRC_RUC(2), 0x00000000}, 1777 {REG_EASRC_RUC(3), 0x00000000}, 1778 {REG_EASRC_RUR(0), 0x7FFFFFFF}, 1779 {REG_EASRC_RUR(1), 0x7FFFFFFF}, 1780 {REG_EASRC_RUR(2), 0x7FFFFFFF}, 1781 {REG_EASRC_RUR(3), 0x7FFFFFFF}, 1782 {REG_EASRC_RCTCL, 0x00000000}, 1783 {REG_EASRC_RCTCH, 0x00000000}, 1784 {REG_EASRC_PCF(0), 0x00000000}, 1785 {REG_EASRC_PCF(1), 0x00000000}, 1786 {REG_EASRC_PCF(2), 0x00000000}, 1787 {REG_EASRC_PCF(3), 0x00000000}, 1788 {REG_EASRC_CRCM, 0x00000000}, 1789 {REG_EASRC_CRCC, 0x00000000}, 1790 {REG_EASRC_IRQC, 0x00000FFF}, 1791 {REG_EASRC_IRQF, 0x00000000}, 1792 {REG_EASRC_CS0(0), 0x00000000}, 1793 {REG_EASRC_CS0(1), 0x00000000}, 1794 {REG_EASRC_CS0(2), 0x00000000}, 1795 {REG_EASRC_CS0(3), 0x00000000}, 1796 {REG_EASRC_CS1(0), 0x00000000}, 1797 {REG_EASRC_CS1(1), 0x00000000}, 1798 {REG_EASRC_CS1(2), 0x00000000}, 1799 {REG_EASRC_CS1(3), 0x00000000}, 1800 {REG_EASRC_CS2(0), 0x00000000}, 1801 {REG_EASRC_CS2(1), 0x00000000}, 1802 {REG_EASRC_CS2(2), 0x00000000}, 1803 {REG_EASRC_CS2(3), 0x00000000}, 1804 {REG_EASRC_CS3(0), 0x00000000}, 1805 {REG_EASRC_CS3(1), 0x00000000}, 1806 {REG_EASRC_CS3(2), 0x00000000}, 1807 {REG_EASRC_CS3(3), 0x00000000}, 1808 {REG_EASRC_CS4(0), 0x00000000}, 1809 {REG_EASRC_CS4(1), 0x00000000}, 1810 {REG_EASRC_CS4(2), 0x00000000}, 1811 {REG_EASRC_CS4(3), 0x00000000}, 1812 {REG_EASRC_CS5(0), 0x00000000}, 1813 {REG_EASRC_CS5(1), 0x00000000}, 1814 {REG_EASRC_CS5(2), 0x00000000}, 1815 {REG_EASRC_CS5(3), 0x00000000}, 1816 {REG_EASRC_DBGC, 0x00000000}, 1817 {REG_EASRC_DBGS, 0x00000000}, 1818 }; 1819 1820 static const struct regmap_range fsl_easrc_readable_ranges[] = { 1821 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH), 1822 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)), 1823 regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS), 1824 }; 1825 1826 static const struct regmap_access_table fsl_easrc_readable_table = { 1827 .yes_ranges = fsl_easrc_readable_ranges, 1828 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges), 1829 }; 1830 1831 static const struct regmap_range fsl_easrc_writeable_ranges[] = { 1832 regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)), 1833 regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)), 1834 regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH), 1835 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC), 1836 }; 1837 1838 static const struct regmap_access_table fsl_easrc_writeable_table = { 1839 .yes_ranges = fsl_easrc_writeable_ranges, 1840 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges), 1841 }; 1842 1843 static const struct regmap_range fsl_easrc_volatileable_ranges[] = { 1844 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)), 1845 regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)), 1846 regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF), 1847 regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS), 1848 }; 1849 1850 static const struct regmap_access_table fsl_easrc_volatileable_table = { 1851 .yes_ranges = fsl_easrc_volatileable_ranges, 1852 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges), 1853 }; 1854 1855 static const struct regmap_config fsl_easrc_regmap_config = { 1856 .reg_bits = 32, 1857 .reg_stride = 4, 1858 .val_bits = 32, 1859 1860 .max_register = REG_EASRC_DBGS, 1861 .reg_defaults = fsl_easrc_reg_defaults, 1862 .num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults), 1863 .rd_table = &fsl_easrc_readable_table, 1864 .wr_table = &fsl_easrc_writeable_table, 1865 .volatile_table = &fsl_easrc_volatileable_table, 1866 .cache_type = REGCACHE_MAPLE, 1867 }; 1868 1869 #ifdef DEBUG 1870 static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc) 1871 { 1872 struct fsl_easrc_priv *easrc_priv = easrc->private; 1873 struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr; 1874 struct interp_params *interp = easrc_priv->interp; 1875 struct prefil_params *prefil = easrc_priv->prefil; 1876 struct device *dev = &easrc->pdev->dev; 1877 int i; 1878 1879 if (firm->magic != FIRMWARE_MAGIC) { 1880 dev_err(dev, "Wrong magic. Something went wrong!"); 1881 return; 1882 } 1883 1884 dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version); 1885 dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen); 1886 dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen); 1887 dev_dbg(dev, "\nInterpolation scenarios:\n"); 1888 1889 for (i = 0; i < firm->interp_scen; i++) { 1890 if (interp[i].magic != FIRMWARE_MAGIC) { 1891 dev_dbg(dev, "%d. wrong interp magic: %x\n", 1892 i, interp[i].magic); 1893 continue; 1894 } 1895 dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i, 1896 interp[i].num_taps, interp[i].num_phases, 1897 interp[i].center_tap); 1898 } 1899 1900 for (i = 0; i < firm->prefil_scen; i++) { 1901 if (prefil[i].magic != FIRMWARE_MAGIC) { 1902 dev_dbg(dev, "%d. wrong prefil magic: %x\n", 1903 i, prefil[i].magic); 1904 continue; 1905 } 1906 dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i, 1907 prefil[i].insr, prefil[i].outsr, 1908 prefil[i].st1_taps, prefil[i].st2_taps); 1909 } 1910 1911 dev_dbg(dev, "end of firmware dump\n"); 1912 } 1913 #endif 1914 1915 static int fsl_easrc_get_firmware(struct fsl_asrc *easrc) 1916 { 1917 struct fsl_easrc_priv *easrc_priv; 1918 const struct firmware **fw_p; 1919 u32 pnum, inum, offset; 1920 const u8 *data; 1921 int ret; 1922 1923 if (!easrc) 1924 return -EINVAL; 1925 1926 easrc_priv = easrc->private; 1927 fw_p = &easrc_priv->fw; 1928 1929 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev); 1930 if (ret) 1931 return ret; 1932 1933 data = easrc_priv->fw->data; 1934 1935 easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data; 1936 pnum = easrc_priv->firmware_hdr->prefil_scen; 1937 inum = easrc_priv->firmware_hdr->interp_scen; 1938 1939 if (inum) { 1940 offset = sizeof(struct asrc_firmware_hdr); 1941 easrc_priv->interp = (struct interp_params *)(data + offset); 1942 } 1943 1944 if (pnum) { 1945 offset = sizeof(struct asrc_firmware_hdr) + 1946 inum * sizeof(struct interp_params); 1947 easrc_priv->prefil = (struct prefil_params *)(data + offset); 1948 } 1949 1950 #ifdef DEBUG 1951 fsl_easrc_dump_firmware(easrc); 1952 #endif 1953 1954 return 0; 1955 } 1956 1957 static irqreturn_t fsl_easrc_isr(int irq, void *dev_id) 1958 { 1959 struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id; 1960 struct device *dev = &easrc->pdev->dev; 1961 int val; 1962 1963 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); 1964 1965 if (val & EASRC_IRQF_OER_MASK) 1966 dev_dbg(dev, "output FIFO underflow\n"); 1967 1968 if (val & EASRC_IRQF_IFO_MASK) 1969 dev_dbg(dev, "input FIFO overflow\n"); 1970 1971 return IRQ_HANDLED; 1972 } 1973 1974 static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index) 1975 { 1976 return REG_EASRC_FIFO(dir, index); 1977 } 1978 1979 /* Get sample numbers in FIFO */ 1980 static unsigned int fsl_easrc_get_output_fifo_size(struct fsl_asrc_pair *pair) 1981 { 1982 struct fsl_asrc *asrc = pair->asrc; 1983 enum asrc_pair_index index = pair->index; 1984 u32 val; 1985 1986 regmap_read(asrc->regmap, REG_EASRC_SFS(index), &val); 1987 val &= EASRC_SFS_NSGO_MASK; 1988 1989 return val >> EASRC_SFS_NSGO_SHIFT; 1990 } 1991 1992 static int fsl_easrc_m2m_prepare(struct fsl_asrc_pair *pair) 1993 { 1994 struct fsl_easrc_ctx_priv *ctx_priv = pair->private; 1995 struct fsl_asrc *asrc = pair->asrc; 1996 struct device *dev = &asrc->pdev->dev; 1997 int ret; 1998 1999 ctx_priv->in_params.sample_rate = pair->rate[IN]; 2000 ctx_priv->in_params.sample_format = pair->sample_format[IN]; 2001 ctx_priv->out_params.sample_rate = pair->rate[OUT]; 2002 ctx_priv->out_params.sample_format = pair->sample_format[OUT]; 2003 2004 ctx_priv->in_params.fifo_wtmk = FSL_EASRC_INPUTFIFO_WML; 2005 ctx_priv->out_params.fifo_wtmk = FSL_EASRC_OUTPUTFIFO_WML; 2006 /* Fill the right half of the re-sampler with zeros */ 2007 ctx_priv->rs_init_mode = 0x2; 2008 /* Zero fill the right half of the prefilter */ 2009 ctx_priv->pf_init_mode = 0x2; 2010 2011 ret = fsl_easrc_set_ctx_format(pair, 2012 &ctx_priv->in_params.sample_format, 2013 &ctx_priv->out_params.sample_format); 2014 if (ret) { 2015 dev_err(dev, "failed to set context format: %d\n", ret); 2016 return ret; 2017 } 2018 2019 ret = fsl_easrc_config_context(asrc, pair->index); 2020 if (ret) { 2021 dev_err(dev, "failed to config context %d\n", ret); 2022 return ret; 2023 } 2024 2025 ctx_priv->in_params.iterations = 1; 2026 ctx_priv->in_params.group_len = pair->channels; 2027 ctx_priv->in_params.access_len = pair->channels; 2028 ctx_priv->out_params.iterations = 1; 2029 ctx_priv->out_params.group_len = pair->channels; 2030 ctx_priv->out_params.access_len = pair->channels; 2031 2032 ret = fsl_easrc_set_ctx_organziation(pair); 2033 if (ret) { 2034 dev_err(dev, "failed to set fifo organization\n"); 2035 return ret; 2036 } 2037 2038 /* The context start flag */ 2039 pair->first_convert = 1; 2040 return 0; 2041 } 2042 2043 static int fsl_easrc_m2m_start(struct fsl_asrc_pair *pair) 2044 { 2045 /* start context once */ 2046 if (pair->first_convert) { 2047 fsl_easrc_start_context(pair); 2048 pair->first_convert = 0; 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int fsl_easrc_m2m_stop(struct fsl_asrc_pair *pair) 2055 { 2056 /* Stop pair/context */ 2057 if (!pair->first_convert) { 2058 fsl_easrc_stop_context(pair); 2059 pair->first_convert = 1; 2060 } 2061 2062 return 0; 2063 } 2064 2065 /* calculate capture data length according to output data length and sample rate */ 2066 static int fsl_easrc_m2m_calc_out_len(struct fsl_asrc_pair *pair, int input_buffer_length) 2067 { 2068 struct fsl_asrc *easrc = pair->asrc; 2069 struct fsl_easrc_priv *easrc_priv = easrc->private; 2070 struct fsl_easrc_ctx_priv *ctx_priv = pair->private; 2071 unsigned int in_rate = ctx_priv->in_params.norm_rate; 2072 unsigned int out_rate = ctx_priv->out_params.norm_rate; 2073 unsigned int channels = pair->channels; 2074 unsigned int in_samples, out_samples; 2075 unsigned int in_width, out_width; 2076 unsigned int out_length; 2077 unsigned int frac_bits; 2078 u64 val1, val2; 2079 2080 switch (easrc_priv->rs_num_taps) { 2081 case EASRC_RS_32_TAPS: 2082 /* integer bits = 5; */ 2083 frac_bits = 39; 2084 break; 2085 case EASRC_RS_64_TAPS: 2086 /* integer bits = 6; */ 2087 frac_bits = 38; 2088 break; 2089 case EASRC_RS_128_TAPS: 2090 /* integer bits = 7; */ 2091 frac_bits = 37; 2092 break; 2093 default: 2094 return -EINVAL; 2095 } 2096 2097 val1 = (u64)in_rate << frac_bits; 2098 do_div(val1, out_rate); 2099 val1 += (s64)ctx_priv->ratio_mod << (frac_bits - 31); 2100 2101 in_width = snd_pcm_format_physical_width(ctx_priv->in_params.sample_format) / 8; 2102 out_width = snd_pcm_format_physical_width(ctx_priv->out_params.sample_format) / 8; 2103 2104 ctx_priv->in_filled_len += input_buffer_length; 2105 if (ctx_priv->in_filled_len <= ctx_priv->in_filled_sample * in_width * channels) { 2106 out_length = 0; 2107 } else { 2108 in_samples = ctx_priv->in_filled_len / (in_width * channels) - 2109 ctx_priv->in_filled_sample; 2110 2111 /* right shift 12 bit to make ratio in 32bit space */ 2112 val2 = (u64)in_samples << (frac_bits - 12); 2113 val1 = val1 >> 12; 2114 val2 = div64_u64(val2, val1); 2115 out_samples = val2; 2116 2117 out_length = out_samples * out_width * channels; 2118 ctx_priv->in_filled_len = ctx_priv->in_filled_sample * in_width * channels; 2119 } 2120 2121 return out_length; 2122 } 2123 2124 static int fsl_easrc_m2m_get_maxburst(u8 dir, struct fsl_asrc_pair *pair) 2125 { 2126 struct fsl_easrc_ctx_priv *ctx_priv = pair->private; 2127 2128 if (dir == IN) 2129 return ctx_priv->in_params.fifo_wtmk * pair->channels; 2130 else 2131 return ctx_priv->out_params.fifo_wtmk * pair->channels; 2132 } 2133 2134 static int fsl_easrc_m2m_pair_suspend(struct fsl_asrc_pair *pair) 2135 { 2136 fsl_easrc_stop_context(pair); 2137 2138 return 0; 2139 } 2140 2141 static int fsl_easrc_m2m_pair_resume(struct fsl_asrc_pair *pair) 2142 { 2143 struct fsl_easrc_ctx_priv *ctx_priv = pair->private; 2144 2145 pair->first_convert = 1; 2146 ctx_priv->in_filled_len = 0; 2147 2148 return 0; 2149 } 2150 2151 /* val is Q31 */ 2152 static int fsl_easrc_m2m_set_ratio_mod(struct fsl_asrc_pair *pair, int val) 2153 { 2154 struct fsl_easrc_ctx_priv *ctx_priv = pair->private; 2155 struct fsl_asrc *easrc = pair->asrc; 2156 struct fsl_easrc_priv *easrc_priv = easrc->private; 2157 unsigned int frac_bits; 2158 2159 ctx_priv->ratio_mod += val; 2160 2161 switch (easrc_priv->rs_num_taps) { 2162 case EASRC_RS_32_TAPS: 2163 /* integer bits = 5; */ 2164 frac_bits = 39; 2165 break; 2166 case EASRC_RS_64_TAPS: 2167 /* integer bits = 6; */ 2168 frac_bits = 38; 2169 break; 2170 case EASRC_RS_128_TAPS: 2171 /* integer bits = 7; */ 2172 frac_bits = 37; 2173 break; 2174 default: 2175 return -EINVAL; 2176 } 2177 2178 val <<= (frac_bits - 31); 2179 regmap_write(easrc->regmap, REG_EASRC_RUC(pair->index), EASRC_RSUC_RS_RM(val)); 2180 2181 return 0; 2182 } 2183 2184 static int fsl_easrc_m2m_get_cap(struct fsl_asrc_m2m_cap *cap) 2185 { 2186 cap->fmt_in = FSL_EASRC_FORMATS; 2187 cap->fmt_out = FSL_EASRC_FORMATS | SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 2188 cap->rate_in = easrc_rates; 2189 cap->rate_in_count = ARRAY_SIZE(easrc_rates); 2190 cap->rate_out = easrc_rates; 2191 cap->rate_out_count = ARRAY_SIZE(easrc_rates); 2192 cap->chan_min = 1; 2193 cap->chan_max = 32; 2194 return 0; 2195 } 2196 2197 static const struct of_device_id fsl_easrc_dt_ids[] = { 2198 { .compatible = "fsl,imx8mn-easrc",}, 2199 {} 2200 }; 2201 MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids); 2202 2203 static int fsl_easrc_probe(struct platform_device *pdev) 2204 { 2205 struct fsl_easrc_priv *easrc_priv; 2206 struct device *dev = &pdev->dev; 2207 struct fsl_asrc *easrc; 2208 struct resource *res; 2209 struct device_node *np; 2210 void __iomem *regs; 2211 u32 asrc_fmt = 0; 2212 int ret, irq; 2213 2214 easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL); 2215 if (!easrc) 2216 return -ENOMEM; 2217 2218 easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL); 2219 if (!easrc_priv) 2220 return -ENOMEM; 2221 2222 easrc->pdev = pdev; 2223 easrc->private = easrc_priv; 2224 np = dev->of_node; 2225 2226 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2227 if (IS_ERR(regs)) 2228 return PTR_ERR(regs); 2229 2230 easrc->paddr = res->start; 2231 2232 easrc->regmap = devm_regmap_init_mmio(dev, regs, &fsl_easrc_regmap_config); 2233 if (IS_ERR(easrc->regmap)) { 2234 dev_err(dev, "failed to init regmap"); 2235 return PTR_ERR(easrc->regmap); 2236 } 2237 2238 irq = platform_get_irq(pdev, 0); 2239 if (irq < 0) 2240 return irq; 2241 2242 ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0, 2243 dev_name(dev), easrc); 2244 if (ret) { 2245 dev_err(dev, "failed to claim irq %u: %d\n", irq, ret); 2246 return ret; 2247 } 2248 2249 easrc->mem_clk = devm_clk_get(dev, "mem"); 2250 if (IS_ERR(easrc->mem_clk)) { 2251 dev_err(dev, "failed to get mem clock\n"); 2252 return PTR_ERR(easrc->mem_clk); 2253 } 2254 2255 /* Set default value */ 2256 easrc->channel_avail = 32; 2257 easrc->get_dma_channel = fsl_easrc_get_dma_channel; 2258 easrc->request_pair = fsl_easrc_request_context; 2259 easrc->release_pair = fsl_easrc_release_context; 2260 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr; 2261 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv); 2262 easrc->m2m_prepare = fsl_easrc_m2m_prepare; 2263 easrc->m2m_start = fsl_easrc_m2m_start; 2264 easrc->m2m_stop = fsl_easrc_m2m_stop; 2265 easrc->get_output_fifo_size = fsl_easrc_get_output_fifo_size; 2266 easrc->m2m_calc_out_len = fsl_easrc_m2m_calc_out_len; 2267 easrc->m2m_get_maxburst = fsl_easrc_m2m_get_maxburst; 2268 easrc->m2m_pair_suspend = fsl_easrc_m2m_pair_suspend; 2269 easrc->m2m_pair_resume = fsl_easrc_m2m_pair_resume; 2270 easrc->m2m_set_ratio_mod = fsl_easrc_m2m_set_ratio_mod; 2271 easrc->m2m_get_cap = fsl_easrc_m2m_get_cap; 2272 2273 easrc_priv->rs_num_taps = EASRC_RS_32_TAPS; 2274 easrc_priv->const_coeff = 0x3FF0000000000000; 2275 2276 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate); 2277 if (ret) { 2278 dev_err(dev, "failed to asrc rate\n"); 2279 return ret; 2280 } 2281 2282 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt); 2283 easrc->asrc_format = asrc_fmt; 2284 if (ret) { 2285 dev_err(dev, "failed to asrc format\n"); 2286 return ret; 2287 } 2288 2289 if (!(FSL_EASRC_FORMATS & (pcm_format_to_bits(easrc->asrc_format)))) { 2290 dev_warn(dev, "unsupported format, switching to S24_LE\n"); 2291 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 2292 } 2293 2294 ret = of_property_read_string(np, "firmware-name", 2295 &easrc_priv->fw_name); 2296 if (ret) { 2297 dev_err(dev, "failed to get firmware name\n"); 2298 return ret; 2299 } 2300 2301 platform_set_drvdata(pdev, easrc); 2302 pm_runtime_enable(dev); 2303 2304 spin_lock_init(&easrc->lock); 2305 2306 regcache_cache_only(easrc->regmap, true); 2307 2308 ret = devm_snd_soc_register_component(dev, &fsl_easrc_component, 2309 fsl_easrc_dai, ARRAY_SIZE(fsl_easrc_dai)); 2310 if (ret) { 2311 dev_err(dev, "failed to register ASoC DAI\n"); 2312 goto err_pm_disable; 2313 } 2314 2315 ret = devm_snd_soc_register_component(dev, &fsl_asrc_component, 2316 NULL, 0); 2317 if (ret) { 2318 dev_err(&pdev->dev, "failed to register ASoC platform\n"); 2319 goto err_pm_disable; 2320 } 2321 2322 ret = fsl_asrc_m2m_init(easrc); 2323 if (ret) { 2324 dev_err(&pdev->dev, "failed to init m2m device %d\n", ret); 2325 goto err_pm_disable; 2326 } 2327 2328 return 0; 2329 2330 err_pm_disable: 2331 pm_runtime_disable(&pdev->dev); 2332 return ret; 2333 } 2334 2335 static void fsl_easrc_remove(struct platform_device *pdev) 2336 { 2337 struct fsl_asrc *easrc = dev_get_drvdata(&pdev->dev); 2338 2339 fsl_asrc_m2m_exit(easrc); 2340 2341 pm_runtime_disable(&pdev->dev); 2342 } 2343 2344 static int fsl_easrc_runtime_suspend(struct device *dev) 2345 { 2346 struct fsl_asrc *easrc = dev_get_drvdata(dev); 2347 struct fsl_easrc_priv *easrc_priv = easrc->private; 2348 2349 regcache_cache_only(easrc->regmap, true); 2350 2351 clk_disable_unprepare(easrc->mem_clk); 2352 2353 scoped_guard(spinlock_irqsave, &easrc->lock) 2354 easrc_priv->firmware_loaded = 0; 2355 2356 return 0; 2357 } 2358 2359 static int fsl_easrc_runtime_resume(struct device *dev) 2360 { 2361 struct fsl_asrc *easrc = dev_get_drvdata(dev); 2362 struct fsl_easrc_priv *easrc_priv = easrc->private; 2363 struct fsl_easrc_ctx_priv *ctx_priv; 2364 struct fsl_asrc_pair *ctx; 2365 int ret; 2366 int i; 2367 2368 ret = clk_prepare_enable(easrc->mem_clk); 2369 if (ret) 2370 return ret; 2371 2372 regcache_cache_only(easrc->regmap, false); 2373 regcache_mark_dirty(easrc->regmap); 2374 regcache_sync(easrc->regmap); 2375 2376 scoped_guard(spinlock_irqsave, &easrc->lock) { 2377 if (easrc_priv->firmware_loaded) 2378 return 0; 2379 easrc_priv->firmware_loaded = 1; 2380 } 2381 2382 ret = fsl_easrc_get_firmware(easrc); 2383 if (ret) { 2384 dev_err(dev, "failed to get firmware\n"); 2385 goto disable_mem_clk; 2386 } 2387 2388 /* 2389 * Write Resampling Coefficients 2390 * The coefficient RAM must be configured prior to beginning of 2391 * any context processing within the ASRC 2392 */ 2393 ret = fsl_easrc_resampler_config(easrc); 2394 if (ret) { 2395 dev_err(dev, "resampler config failed\n"); 2396 goto disable_mem_clk; 2397 } 2398 2399 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) { 2400 ctx = easrc->pair[i]; 2401 if (!ctx) 2402 continue; 2403 2404 ctx_priv = ctx->private; 2405 fsl_easrc_set_rs_ratio(ctx); 2406 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * 2407 ctx_priv->out_params.sample_rate / 2408 ctx_priv->in_params.sample_rate; 2409 if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate 2410 % ctx_priv->in_params.sample_rate != 0) 2411 ctx_priv->out_missed_sample += 1; 2412 2413 ret = fsl_easrc_write_pf_coeff_mem(easrc, i, 2414 ctx_priv->st1_coeff, 2415 ctx_priv->st1_num_taps, 2416 ctx_priv->st1_addexp); 2417 if (ret) 2418 goto disable_mem_clk; 2419 2420 ret = fsl_easrc_write_pf_coeff_mem(easrc, i, 2421 ctx_priv->st2_coeff, 2422 ctx_priv->st2_num_taps, 2423 ctx_priv->st2_addexp); 2424 if (ret) 2425 goto disable_mem_clk; 2426 } 2427 2428 return 0; 2429 disable_mem_clk: 2430 clk_disable_unprepare(easrc->mem_clk); 2431 return ret; 2432 } 2433 2434 static int fsl_easrc_suspend(struct device *dev) 2435 { 2436 struct fsl_asrc *easrc = dev_get_drvdata(dev); 2437 int ret; 2438 2439 fsl_asrc_m2m_suspend(easrc); 2440 ret = pm_runtime_force_suspend(dev); 2441 return ret; 2442 } 2443 2444 static int fsl_easrc_resume(struct device *dev) 2445 { 2446 struct fsl_asrc *easrc = dev_get_drvdata(dev); 2447 int ret; 2448 2449 ret = pm_runtime_force_resume(dev); 2450 fsl_asrc_m2m_resume(easrc); 2451 return ret; 2452 } 2453 2454 static const struct dev_pm_ops fsl_easrc_pm_ops = { 2455 RUNTIME_PM_OPS(fsl_easrc_runtime_suspend, fsl_easrc_runtime_resume, NULL) 2456 SYSTEM_SLEEP_PM_OPS(fsl_easrc_suspend, fsl_easrc_resume) 2457 }; 2458 2459 static struct platform_driver fsl_easrc_driver = { 2460 .probe = fsl_easrc_probe, 2461 .remove = fsl_easrc_remove, 2462 .driver = { 2463 .name = "fsl-easrc", 2464 .pm = pm_ptr(&fsl_easrc_pm_ops), 2465 .of_match_table = fsl_easrc_dt_ids, 2466 }, 2467 }; 2468 module_platform_driver(fsl_easrc_driver); 2469 2470 MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver"); 2471 MODULE_LICENSE("GPL v2"); 2472