1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale QMC HDLC Device Driver
4 *
5 * Copyright 2023 CS GROUP France
6 *
7 * Author: Herve Codina <herve.codina@bootlin.com>
8 */
9
10 #include <linux/array_size.h>
11 #include <linux/bug.h>
12 #include <linux/cleanup.h>
13 #include <linux/bitmap.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/framer/framer.h>
18 #include <linux/hdlc.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/types.h>
25
26 #include <soc/fsl/qe/qmc.h>
27
28 struct qmc_hdlc_desc {
29 struct net_device *netdev;
30 struct sk_buff *skb; /* NULL if the descriptor is not in use */
31 dma_addr_t dma_addr;
32 size_t dma_size;
33 };
34
35 struct qmc_hdlc {
36 struct device *dev;
37 struct qmc_chan *qmc_chan;
38 struct net_device *netdev;
39 struct framer *framer;
40 struct mutex carrier_lock; /* Protect carrier detection */
41 struct notifier_block nb;
42 bool is_crc32;
43 spinlock_t tx_lock; /* Protect tx descriptors */
44 struct qmc_hdlc_desc tx_descs[8];
45 unsigned int tx_out;
46 struct qmc_hdlc_desc rx_descs[4];
47 u32 slot_map;
48 };
49
netdev_to_qmc_hdlc(struct net_device * netdev)50 static struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
51 {
52 return dev_to_hdlc(netdev)->priv;
53 }
54
qmc_hdlc_framer_set_carrier(struct qmc_hdlc * qmc_hdlc)55 static int qmc_hdlc_framer_set_carrier(struct qmc_hdlc *qmc_hdlc)
56 {
57 struct framer_status framer_status;
58 int ret;
59
60 if (!qmc_hdlc->framer)
61 return 0;
62
63 guard(mutex)(&qmc_hdlc->carrier_lock);
64
65 ret = framer_get_status(qmc_hdlc->framer, &framer_status);
66 if (ret) {
67 dev_err(qmc_hdlc->dev, "get framer status failed (%d)\n", ret);
68 return ret;
69 }
70 if (framer_status.link_is_on)
71 netif_carrier_on(qmc_hdlc->netdev);
72 else
73 netif_carrier_off(qmc_hdlc->netdev);
74
75 return 0;
76 }
77
qmc_hdlc_framer_notifier(struct notifier_block * nb,unsigned long action,void * data)78 static int qmc_hdlc_framer_notifier(struct notifier_block *nb, unsigned long action,
79 void *data)
80 {
81 struct qmc_hdlc *qmc_hdlc = container_of(nb, struct qmc_hdlc, nb);
82 int ret;
83
84 if (action != FRAMER_EVENT_STATUS)
85 return NOTIFY_DONE;
86
87 ret = qmc_hdlc_framer_set_carrier(qmc_hdlc);
88 return ret ? NOTIFY_DONE : NOTIFY_OK;
89 }
90
qmc_hdlc_framer_start(struct qmc_hdlc * qmc_hdlc)91 static int qmc_hdlc_framer_start(struct qmc_hdlc *qmc_hdlc)
92 {
93 struct framer_status framer_status;
94 int ret;
95
96 if (!qmc_hdlc->framer)
97 return 0;
98
99 ret = framer_power_on(qmc_hdlc->framer);
100 if (ret) {
101 dev_err(qmc_hdlc->dev, "framer power-on failed (%d)\n", ret);
102 return ret;
103 }
104
105 /* Be sure that get_status is supported */
106 ret = framer_get_status(qmc_hdlc->framer, &framer_status);
107 if (ret) {
108 dev_err(qmc_hdlc->dev, "get framer status failed (%d)\n", ret);
109 goto framer_power_off;
110 }
111
112 qmc_hdlc->nb.notifier_call = qmc_hdlc_framer_notifier;
113 ret = framer_notifier_register(qmc_hdlc->framer, &qmc_hdlc->nb);
114 if (ret) {
115 dev_err(qmc_hdlc->dev, "framer notifier register failed (%d)\n", ret);
116 goto framer_power_off;
117 }
118
119 return 0;
120
121 framer_power_off:
122 framer_power_off(qmc_hdlc->framer);
123 return ret;
124 }
125
qmc_hdlc_framer_stop(struct qmc_hdlc * qmc_hdlc)126 static void qmc_hdlc_framer_stop(struct qmc_hdlc *qmc_hdlc)
127 {
128 if (!qmc_hdlc->framer)
129 return;
130
131 framer_notifier_unregister(qmc_hdlc->framer, &qmc_hdlc->nb);
132 framer_power_off(qmc_hdlc->framer);
133 }
134
qmc_hdlc_framer_set_iface(struct qmc_hdlc * qmc_hdlc,int if_iface,const te1_settings * te1)135 static int qmc_hdlc_framer_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface,
136 const te1_settings *te1)
137 {
138 struct framer_config config;
139 int ret;
140
141 if (!qmc_hdlc->framer)
142 return 0;
143
144 ret = framer_get_config(qmc_hdlc->framer, &config);
145 if (ret)
146 return ret;
147
148 switch (if_iface) {
149 case IF_IFACE_E1:
150 config.iface = FRAMER_IFACE_E1;
151 break;
152 case IF_IFACE_T1:
153 config.iface = FRAMER_IFACE_T1;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 switch (te1->clock_type) {
160 case CLOCK_DEFAULT:
161 /* Keep current value */
162 break;
163 case CLOCK_EXT:
164 config.clock_type = FRAMER_CLOCK_EXT;
165 break;
166 case CLOCK_INT:
167 config.clock_type = FRAMER_CLOCK_INT;
168 break;
169 default:
170 return -EINVAL;
171 }
172 config.line_clock_rate = te1->clock_rate;
173
174 return framer_set_config(qmc_hdlc->framer, &config);
175 }
176
qmc_hdlc_framer_get_iface(struct qmc_hdlc * qmc_hdlc,int * if_iface,te1_settings * te1)177 static int qmc_hdlc_framer_get_iface(struct qmc_hdlc *qmc_hdlc, int *if_iface, te1_settings *te1)
178 {
179 struct framer_config config;
180 int ret;
181
182 if (!qmc_hdlc->framer) {
183 *if_iface = IF_IFACE_E1;
184 return 0;
185 }
186
187 ret = framer_get_config(qmc_hdlc->framer, &config);
188 if (ret)
189 return ret;
190
191 switch (config.iface) {
192 case FRAMER_IFACE_E1:
193 *if_iface = IF_IFACE_E1;
194 break;
195 case FRAMER_IFACE_T1:
196 *if_iface = IF_IFACE_T1;
197 break;
198 }
199
200 if (!te1)
201 return 0; /* Only iface type requested */
202
203 switch (config.clock_type) {
204 case FRAMER_CLOCK_EXT:
205 te1->clock_type = CLOCK_EXT;
206 break;
207 case FRAMER_CLOCK_INT:
208 te1->clock_type = CLOCK_INT;
209 break;
210 default:
211 return -EINVAL;
212 }
213 te1->clock_rate = config.line_clock_rate;
214 return 0;
215 }
216
qmc_hdlc_framer_init(struct qmc_hdlc * qmc_hdlc)217 static int qmc_hdlc_framer_init(struct qmc_hdlc *qmc_hdlc)
218 {
219 int ret;
220
221 if (!qmc_hdlc->framer)
222 return 0;
223
224 ret = framer_init(qmc_hdlc->framer);
225 if (ret) {
226 dev_err(qmc_hdlc->dev, "framer init failed (%d)\n", ret);
227 return ret;
228 }
229
230 return 0;
231 }
232
qmc_hdlc_framer_exit(struct qmc_hdlc * qmc_hdlc)233 static void qmc_hdlc_framer_exit(struct qmc_hdlc *qmc_hdlc)
234 {
235 if (!qmc_hdlc->framer)
236 return;
237
238 framer_exit(qmc_hdlc->framer);
239 }
240
241 static int qmc_hdlc_recv_queue(struct qmc_hdlc *qmc_hdlc, struct qmc_hdlc_desc *desc, size_t size);
242
243 #define QMC_HDLC_RX_ERROR_FLAGS \
244 (QMC_RX_FLAG_HDLC_OVF | QMC_RX_FLAG_HDLC_UNA | \
245 QMC_RX_FLAG_HDLC_CRC | QMC_RX_FLAG_HDLC_ABORT)
246
qmc_hcld_recv_complete(void * context,size_t length,unsigned int flags)247 static void qmc_hcld_recv_complete(void *context, size_t length, unsigned int flags)
248 {
249 struct qmc_hdlc_desc *desc = context;
250 struct net_device *netdev;
251 struct qmc_hdlc *qmc_hdlc;
252 size_t crc_size;
253 int ret;
254
255 netdev = desc->netdev;
256 qmc_hdlc = netdev_to_qmc_hdlc(netdev);
257
258 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size, DMA_FROM_DEVICE);
259
260 if (flags & QMC_HDLC_RX_ERROR_FLAGS) {
261 netdev->stats.rx_errors++;
262 if (flags & QMC_RX_FLAG_HDLC_OVF) /* Data overflow */
263 netdev->stats.rx_over_errors++;
264 if (flags & QMC_RX_FLAG_HDLC_UNA) /* bits received not multiple of 8 */
265 netdev->stats.rx_frame_errors++;
266 if (flags & QMC_RX_FLAG_HDLC_ABORT) /* Received an abort sequence */
267 netdev->stats.rx_frame_errors++;
268 if (flags & QMC_RX_FLAG_HDLC_CRC) /* CRC error */
269 netdev->stats.rx_crc_errors++;
270 kfree_skb(desc->skb);
271 goto re_queue;
272 }
273
274 /* Discard the CRC */
275 crc_size = qmc_hdlc->is_crc32 ? 4 : 2;
276 if (length < crc_size) {
277 netdev->stats.rx_length_errors++;
278 kfree_skb(desc->skb);
279 goto re_queue;
280 }
281 length -= crc_size;
282
283 netdev->stats.rx_packets++;
284 netdev->stats.rx_bytes += length;
285
286 skb_put(desc->skb, length);
287 desc->skb->protocol = hdlc_type_trans(desc->skb, netdev);
288 netif_rx(desc->skb);
289
290 re_queue:
291 /* Re-queue a transfer using the same descriptor */
292 ret = qmc_hdlc_recv_queue(qmc_hdlc, desc, desc->dma_size);
293 if (ret) {
294 dev_err(qmc_hdlc->dev, "queue recv desc failed (%d)\n", ret);
295 netdev->stats.rx_errors++;
296 }
297 }
298
qmc_hdlc_recv_queue(struct qmc_hdlc * qmc_hdlc,struct qmc_hdlc_desc * desc,size_t size)299 static int qmc_hdlc_recv_queue(struct qmc_hdlc *qmc_hdlc, struct qmc_hdlc_desc *desc, size_t size)
300 {
301 int ret;
302
303 desc->skb = dev_alloc_skb(size);
304 if (!desc->skb)
305 return -ENOMEM;
306
307 desc->dma_size = size;
308 desc->dma_addr = dma_map_single(qmc_hdlc->dev, desc->skb->data,
309 desc->dma_size, DMA_FROM_DEVICE);
310 ret = dma_mapping_error(qmc_hdlc->dev, desc->dma_addr);
311 if (ret)
312 goto free_skb;
313
314 ret = qmc_chan_read_submit(qmc_hdlc->qmc_chan, desc->dma_addr, desc->dma_size,
315 qmc_hcld_recv_complete, desc);
316 if (ret)
317 goto dma_unmap;
318
319 return 0;
320
321 dma_unmap:
322 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size, DMA_FROM_DEVICE);
323 free_skb:
324 kfree_skb(desc->skb);
325 desc->skb = NULL;
326 return ret;
327 }
328
qmc_hdlc_xmit_complete(void * context)329 static void qmc_hdlc_xmit_complete(void *context)
330 {
331 struct qmc_hdlc_desc *desc = context;
332 struct net_device *netdev;
333 struct qmc_hdlc *qmc_hdlc;
334 struct sk_buff *skb;
335
336 netdev = desc->netdev;
337 qmc_hdlc = netdev_to_qmc_hdlc(netdev);
338
339 scoped_guard(spinlock_irqsave, &qmc_hdlc->tx_lock) {
340 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size, DMA_TO_DEVICE);
341 skb = desc->skb;
342 desc->skb = NULL; /* Release the descriptor */
343 if (netif_queue_stopped(netdev))
344 netif_wake_queue(netdev);
345 }
346
347 netdev->stats.tx_packets++;
348 netdev->stats.tx_bytes += skb->len;
349
350 dev_consume_skb_any(skb);
351 }
352
qmc_hdlc_xmit_queue(struct qmc_hdlc * qmc_hdlc,struct qmc_hdlc_desc * desc)353 static int qmc_hdlc_xmit_queue(struct qmc_hdlc *qmc_hdlc, struct qmc_hdlc_desc *desc)
354 {
355 int ret;
356
357 desc->dma_addr = dma_map_single(qmc_hdlc->dev, desc->skb->data,
358 desc->dma_size, DMA_TO_DEVICE);
359 ret = dma_mapping_error(qmc_hdlc->dev, desc->dma_addr);
360 if (ret) {
361 dev_err(qmc_hdlc->dev, "failed to map skb\n");
362 return ret;
363 }
364
365 ret = qmc_chan_write_submit(qmc_hdlc->qmc_chan, desc->dma_addr, desc->dma_size,
366 qmc_hdlc_xmit_complete, desc);
367 if (ret) {
368 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size, DMA_TO_DEVICE);
369 dev_err(qmc_hdlc->dev, "qmc chan write returns %d\n", ret);
370 return ret;
371 }
372
373 return 0;
374 }
375
qmc_hdlc_xmit(struct sk_buff * skb,struct net_device * netdev)376 static netdev_tx_t qmc_hdlc_xmit(struct sk_buff *skb, struct net_device *netdev)
377 {
378 struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
379 struct qmc_hdlc_desc *desc;
380 int err;
381
382 guard(spinlock_irqsave)(&qmc_hdlc->tx_lock);
383
384 desc = &qmc_hdlc->tx_descs[qmc_hdlc->tx_out];
385 if (WARN_ONCE(desc->skb, "No tx descriptors available\n")) {
386 /* Should never happen.
387 * Previous xmit should have already stopped the queue.
388 */
389 netif_stop_queue(netdev);
390 return NETDEV_TX_BUSY;
391 }
392
393 desc->netdev = netdev;
394 desc->dma_size = skb->len;
395 desc->skb = skb;
396 err = qmc_hdlc_xmit_queue(qmc_hdlc, desc);
397 if (err) {
398 desc->skb = NULL; /* Release the descriptor */
399 if (err == -EBUSY) {
400 netif_stop_queue(netdev);
401 return NETDEV_TX_BUSY;
402 }
403 dev_kfree_skb(skb);
404 netdev->stats.tx_dropped++;
405 return NETDEV_TX_OK;
406 }
407
408 qmc_hdlc->tx_out = (qmc_hdlc->tx_out + 1) % ARRAY_SIZE(qmc_hdlc->tx_descs);
409
410 if (qmc_hdlc->tx_descs[qmc_hdlc->tx_out].skb)
411 netif_stop_queue(netdev);
412
413 return NETDEV_TX_OK;
414 }
415
qmc_hdlc_xlate_slot_map(struct qmc_hdlc * qmc_hdlc,u32 slot_map,struct qmc_chan_ts_info * ts_info)416 static int qmc_hdlc_xlate_slot_map(struct qmc_hdlc *qmc_hdlc,
417 u32 slot_map, struct qmc_chan_ts_info *ts_info)
418 {
419 DECLARE_BITMAP(ts_mask_avail, 64);
420 DECLARE_BITMAP(ts_mask, 64);
421 DECLARE_BITMAP(map, 64);
422
423 /* Tx and Rx available masks must be identical */
424 if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
425 dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
426 ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
427 return -EINVAL;
428 }
429
430 bitmap_from_u64(ts_mask_avail, ts_info->rx_ts_mask_avail);
431 bitmap_from_u64(map, slot_map);
432 bitmap_scatter(ts_mask, map, ts_mask_avail, 64);
433
434 if (bitmap_weight(ts_mask, 64) != bitmap_weight(map, 64)) {
435 dev_err(qmc_hdlc->dev, "Cannot translate timeslots %64pb -> (%64pb, %64pb)\n",
436 map, ts_mask_avail, ts_mask);
437 return -EINVAL;
438 }
439
440 bitmap_to_arr64(&ts_info->tx_ts_mask, ts_mask, 64);
441 ts_info->rx_ts_mask = ts_info->tx_ts_mask;
442 return 0;
443 }
444
qmc_hdlc_xlate_ts_info(struct qmc_hdlc * qmc_hdlc,const struct qmc_chan_ts_info * ts_info,u32 * slot_map)445 static int qmc_hdlc_xlate_ts_info(struct qmc_hdlc *qmc_hdlc,
446 const struct qmc_chan_ts_info *ts_info, u32 *slot_map)
447 {
448 DECLARE_BITMAP(ts_mask_avail, 64);
449 DECLARE_BITMAP(ts_mask, 64);
450 DECLARE_BITMAP(map, 64);
451 u32 slot_array[2];
452
453 /* Tx and Rx masks and available masks must be identical */
454 if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
455 dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
456 ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
457 return -EINVAL;
458 }
459 if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) {
460 dev_err(qmc_hdlc->dev, "tx and rx timeslots mismatch (0x%llx, 0x%llx)\n",
461 ts_info->rx_ts_mask, ts_info->tx_ts_mask);
462 return -EINVAL;
463 }
464
465 bitmap_from_u64(ts_mask_avail, ts_info->rx_ts_mask_avail);
466 bitmap_from_u64(ts_mask, ts_info->rx_ts_mask);
467 bitmap_gather(map, ts_mask, ts_mask_avail, 64);
468
469 if (bitmap_weight(ts_mask, 64) != bitmap_weight(map, 64)) {
470 dev_err(qmc_hdlc->dev, "Cannot translate timeslots (%64pb, %64pb) -> %64pb\n",
471 ts_mask_avail, ts_mask, map);
472 return -EINVAL;
473 }
474
475 bitmap_to_arr32(slot_array, map, 64);
476 if (slot_array[1]) {
477 dev_err(qmc_hdlc->dev, "Slot map out of 32bit (%64pb, %64pb) -> %64pb\n",
478 ts_mask_avail, ts_mask, map);
479 return -EINVAL;
480 }
481
482 *slot_map = slot_array[0];
483 return 0;
484 }
485
qmc_hdlc_set_iface(struct qmc_hdlc * qmc_hdlc,int if_iface,const te1_settings * te1)486 static int qmc_hdlc_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface, const te1_settings *te1)
487 {
488 struct qmc_chan_ts_info ts_info;
489 int ret;
490
491 ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, &ts_info);
492 if (ret) {
493 dev_err(qmc_hdlc->dev, "get QMC channel ts info failed %d\n", ret);
494 return ret;
495 }
496 ret = qmc_hdlc_xlate_slot_map(qmc_hdlc, te1->slot_map, &ts_info);
497 if (ret)
498 return ret;
499
500 ret = qmc_chan_set_ts_info(qmc_hdlc->qmc_chan, &ts_info);
501 if (ret) {
502 dev_err(qmc_hdlc->dev, "set QMC channel ts info failed %d\n", ret);
503 return ret;
504 }
505
506 qmc_hdlc->slot_map = te1->slot_map;
507
508 ret = qmc_hdlc_framer_set_iface(qmc_hdlc, if_iface, te1);
509 if (ret) {
510 dev_err(qmc_hdlc->dev, "framer set iface failed %d\n", ret);
511 return ret;
512 }
513
514 return 0;
515 }
516
qmc_hdlc_ioctl(struct net_device * netdev,struct if_settings * ifs)517 static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
518 {
519 struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
520 te1_settings te1;
521 int ret;
522
523 switch (ifs->type) {
524 case IF_GET_IFACE:
525 if (ifs->size < sizeof(te1)) {
526 /* Retrieve type only */
527 ret = qmc_hdlc_framer_get_iface(qmc_hdlc, &ifs->type, NULL);
528 if (ret)
529 return ret;
530
531 if (!ifs->size)
532 return 0; /* only type requested */
533
534 ifs->size = sizeof(te1); /* data size wanted */
535 return -ENOBUFS;
536 }
537
538 memset(&te1, 0, sizeof(te1));
539
540 /* Retrieve info from framer */
541 ret = qmc_hdlc_framer_get_iface(qmc_hdlc, &ifs->type, &te1);
542 if (ret)
543 return ret;
544
545 /* Update slot_map */
546 te1.slot_map = qmc_hdlc->slot_map;
547
548 if (copy_to_user(ifs->ifs_ifsu.te1, &te1, sizeof(te1)))
549 return -EFAULT;
550 return 0;
551
552 case IF_IFACE_E1:
553 case IF_IFACE_T1:
554 if (!capable(CAP_NET_ADMIN))
555 return -EPERM;
556
557 if (netdev->flags & IFF_UP)
558 return -EBUSY;
559
560 if (copy_from_user(&te1, ifs->ifs_ifsu.te1, sizeof(te1)))
561 return -EFAULT;
562
563 return qmc_hdlc_set_iface(qmc_hdlc, ifs->type, &te1);
564
565 default:
566 return hdlc_ioctl(netdev, ifs);
567 }
568 }
569
qmc_hdlc_open(struct net_device * netdev)570 static int qmc_hdlc_open(struct net_device *netdev)
571 {
572 struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
573 struct qmc_chan_param chan_param;
574 struct qmc_hdlc_desc *desc;
575 int ret;
576 int i;
577
578 ret = qmc_hdlc_framer_start(qmc_hdlc);
579 if (ret)
580 return ret;
581
582 ret = hdlc_open(netdev);
583 if (ret)
584 goto framer_stop;
585
586 /* Update carrier */
587 qmc_hdlc_framer_set_carrier(qmc_hdlc);
588
589 chan_param.mode = QMC_HDLC;
590 /* HDLC_MAX_MRU + 4 for the CRC
591 * HDLC_MAX_MRU + 4 + 8 for the CRC and some extraspace needed by the QMC
592 */
593 chan_param.hdlc.max_rx_buf_size = HDLC_MAX_MRU + 4 + 8;
594 chan_param.hdlc.max_rx_frame_size = HDLC_MAX_MRU + 4;
595 chan_param.hdlc.is_crc32 = qmc_hdlc->is_crc32;
596 ret = qmc_chan_set_param(qmc_hdlc->qmc_chan, &chan_param);
597 if (ret) {
598 dev_err(qmc_hdlc->dev, "failed to set param (%d)\n", ret);
599 goto hdlc_close;
600 }
601
602 /* Queue as many recv descriptors as possible */
603 for (i = 0; i < ARRAY_SIZE(qmc_hdlc->rx_descs); i++) {
604 desc = &qmc_hdlc->rx_descs[i];
605
606 desc->netdev = netdev;
607 ret = qmc_hdlc_recv_queue(qmc_hdlc, desc, chan_param.hdlc.max_rx_buf_size);
608 if (ret == -EBUSY && i != 0)
609 break; /* We use all the QMC chan capability */
610 if (ret)
611 goto free_desc;
612 }
613
614 ret = qmc_chan_start(qmc_hdlc->qmc_chan, QMC_CHAN_ALL);
615 if (ret) {
616 dev_err(qmc_hdlc->dev, "qmc chan start failed (%d)\n", ret);
617 goto free_desc;
618 }
619
620 netif_start_queue(netdev);
621
622 return 0;
623
624 free_desc:
625 qmc_chan_reset(qmc_hdlc->qmc_chan, QMC_CHAN_ALL);
626 while (i--) {
627 desc = &qmc_hdlc->rx_descs[i];
628 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size,
629 DMA_FROM_DEVICE);
630 kfree_skb(desc->skb);
631 desc->skb = NULL;
632 }
633 hdlc_close:
634 hdlc_close(netdev);
635 framer_stop:
636 qmc_hdlc_framer_stop(qmc_hdlc);
637 return ret;
638 }
639
qmc_hdlc_close(struct net_device * netdev)640 static int qmc_hdlc_close(struct net_device *netdev)
641 {
642 struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
643 struct qmc_hdlc_desc *desc;
644 int i;
645
646 qmc_chan_stop(qmc_hdlc->qmc_chan, QMC_CHAN_ALL);
647 qmc_chan_reset(qmc_hdlc->qmc_chan, QMC_CHAN_ALL);
648
649 netif_stop_queue(netdev);
650
651 for (i = 0; i < ARRAY_SIZE(qmc_hdlc->tx_descs); i++) {
652 desc = &qmc_hdlc->tx_descs[i];
653 if (!desc->skb)
654 continue;
655 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size,
656 DMA_TO_DEVICE);
657 kfree_skb(desc->skb);
658 desc->skb = NULL;
659 }
660
661 for (i = 0; i < ARRAY_SIZE(qmc_hdlc->rx_descs); i++) {
662 desc = &qmc_hdlc->rx_descs[i];
663 if (!desc->skb)
664 continue;
665 dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size,
666 DMA_FROM_DEVICE);
667 kfree_skb(desc->skb);
668 desc->skb = NULL;
669 }
670
671 hdlc_close(netdev);
672 qmc_hdlc_framer_stop(qmc_hdlc);
673 return 0;
674 }
675
qmc_hdlc_attach(struct net_device * netdev,unsigned short encoding,unsigned short parity)676 static int qmc_hdlc_attach(struct net_device *netdev, unsigned short encoding,
677 unsigned short parity)
678 {
679 struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
680
681 if (encoding != ENCODING_NRZ)
682 return -EINVAL;
683
684 switch (parity) {
685 case PARITY_CRC16_PR1_CCITT:
686 qmc_hdlc->is_crc32 = false;
687 break;
688 case PARITY_CRC32_PR1_CCITT:
689 qmc_hdlc->is_crc32 = true;
690 break;
691 default:
692 dev_err(qmc_hdlc->dev, "unsupported parity %u\n", parity);
693 return -EINVAL;
694 }
695
696 return 0;
697 }
698
699 static const struct net_device_ops qmc_hdlc_netdev_ops = {
700 .ndo_open = qmc_hdlc_open,
701 .ndo_stop = qmc_hdlc_close,
702 .ndo_start_xmit = hdlc_start_xmit,
703 .ndo_siocwandev = qmc_hdlc_ioctl,
704 };
705
qmc_hdlc_probe(struct platform_device * pdev)706 static int qmc_hdlc_probe(struct platform_device *pdev)
707 {
708 struct device *dev = &pdev->dev;
709 struct qmc_chan_ts_info ts_info;
710 struct qmc_hdlc *qmc_hdlc;
711 struct qmc_chan_info info;
712 hdlc_device *hdlc;
713 int ret;
714
715 qmc_hdlc = devm_kzalloc(dev, sizeof(*qmc_hdlc), GFP_KERNEL);
716 if (!qmc_hdlc)
717 return -ENOMEM;
718
719 qmc_hdlc->dev = dev;
720 spin_lock_init(&qmc_hdlc->tx_lock);
721 mutex_init(&qmc_hdlc->carrier_lock);
722
723 qmc_hdlc->qmc_chan = devm_qmc_chan_get_bychild(dev, dev->of_node);
724 if (IS_ERR(qmc_hdlc->qmc_chan))
725 return dev_err_probe(dev, PTR_ERR(qmc_hdlc->qmc_chan),
726 "get QMC channel failed\n");
727
728 ret = qmc_chan_get_info(qmc_hdlc->qmc_chan, &info);
729 if (ret)
730 return dev_err_probe(dev, ret, "get QMC channel info failed\n");
731
732 if (info.mode != QMC_HDLC)
733 return dev_err_probe(dev, -EINVAL, "QMC chan mode %d is not QMC_HDLC\n",
734 info.mode);
735
736 ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, &ts_info);
737 if (ret)
738 return dev_err_probe(dev, ret, "get QMC channel ts info failed\n");
739
740 ret = qmc_hdlc_xlate_ts_info(qmc_hdlc, &ts_info, &qmc_hdlc->slot_map);
741 if (ret)
742 return ret;
743
744 qmc_hdlc->framer = devm_framer_optional_get(dev, "fsl,framer");
745 if (IS_ERR(qmc_hdlc->framer))
746 return PTR_ERR(qmc_hdlc->framer);
747
748 ret = qmc_hdlc_framer_init(qmc_hdlc);
749 if (ret)
750 return ret;
751
752 qmc_hdlc->netdev = alloc_hdlcdev(qmc_hdlc);
753 if (!qmc_hdlc->netdev) {
754 ret = -ENOMEM;
755 goto framer_exit;
756 }
757
758 hdlc = dev_to_hdlc(qmc_hdlc->netdev);
759 hdlc->attach = qmc_hdlc_attach;
760 hdlc->xmit = qmc_hdlc_xmit;
761 SET_NETDEV_DEV(qmc_hdlc->netdev, dev);
762 qmc_hdlc->netdev->tx_queue_len = ARRAY_SIZE(qmc_hdlc->tx_descs);
763 qmc_hdlc->netdev->netdev_ops = &qmc_hdlc_netdev_ops;
764 ret = register_hdlc_device(qmc_hdlc->netdev);
765 if (ret) {
766 dev_err_probe(dev, ret, "failed to register hdlc device\n");
767 goto free_netdev;
768 }
769
770 platform_set_drvdata(pdev, qmc_hdlc);
771 return 0;
772
773 free_netdev:
774 free_netdev(qmc_hdlc->netdev);
775 framer_exit:
776 qmc_hdlc_framer_exit(qmc_hdlc);
777 return ret;
778 }
779
qmc_hdlc_remove(struct platform_device * pdev)780 static void qmc_hdlc_remove(struct platform_device *pdev)
781 {
782 struct qmc_hdlc *qmc_hdlc = platform_get_drvdata(pdev);
783
784 unregister_hdlc_device(qmc_hdlc->netdev);
785 free_netdev(qmc_hdlc->netdev);
786 qmc_hdlc_framer_exit(qmc_hdlc);
787 }
788
789 static const struct of_device_id qmc_hdlc_id_table[] = {
790 { .compatible = "fsl,qmc-hdlc" },
791 {} /* sentinel */
792 };
793 MODULE_DEVICE_TABLE(of, qmc_hdlc_id_table);
794
795 static struct platform_driver qmc_hdlc_driver = {
796 .driver = {
797 .name = "fsl-qmc-hdlc",
798 .of_match_table = qmc_hdlc_id_table,
799 },
800 .probe = qmc_hdlc_probe,
801 .remove = qmc_hdlc_remove,
802 };
803 module_platform_driver(qmc_hdlc_driver);
804
805 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
806 MODULE_DESCRIPTION("QMC HDLC driver");
807 MODULE_LICENSE("GPL");
808