1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ESWIN PCIe Root Complex driver
4 *
5 * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.
6 *
7 * Authors: Yu Ning <ningyu@eswincomputing.com>
8 * Senchuan Zhang <zhangsenchuan@eswincomputing.com>
9 * Yanghui Ou <ouyanghui@eswincomputing.com>
10 */
11
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/resource.h>
20 #include <linux/reset.h>
21 #include <linux/types.h>
22
23 #include "pcie-designware.h"
24
25 /* ELBI registers */
26 #define PCIEELBI_CTRL0_OFFSET 0x0
27 #define PCIEELBI_STATUS0_OFFSET 0x100
28
29 /* LTSSM register fields */
30 #define PCIEELBI_APP_LTSSM_ENABLE BIT(5)
31
32 /* APP_HOLD_PHY_RST register fields */
33 #define PCIEELBI_APP_HOLD_PHY_RST BIT(6)
34
35 /* PM_SEL_AUX_CLK register fields */
36 #define PCIEELBI_PM_SEL_AUX_CLK BIT(16)
37
38 /* DEV_TYPE register fields */
39 #define PCIEELBI_CTRL0_DEV_TYPE GENMASK(3, 0)
40
41 /* Vendor and device ID value */
42 #define PCI_VENDOR_ID_ESWIN 0x1fe1
43 #define PCI_DEVICE_ID_ESWIN_EIC7700 0x2030
44
45 #define ESWIN_NUM_RSTS ARRAY_SIZE(eswin_pcie_rsts)
46
47 static const char * const eswin_pcie_rsts[] = {
48 "pwr",
49 "dbi",
50 };
51
52 struct eswin_pcie_data {
53 bool skip_l23;
54 };
55
56 struct eswin_pcie_port {
57 struct list_head list;
58 struct reset_control *perst;
59 int num_lanes;
60 };
61
62 struct eswin_pcie {
63 struct dw_pcie pci;
64 struct clk_bulk_data *clks;
65 struct reset_control_bulk_data resets[ESWIN_NUM_RSTS];
66 struct list_head ports;
67 const struct eswin_pcie_data *data;
68 int num_clks;
69 };
70
71 #define to_eswin_pcie(x) dev_get_drvdata((x)->dev)
72
eswin_pcie_start_link(struct dw_pcie * pci)73 static int eswin_pcie_start_link(struct dw_pcie *pci)
74 {
75 u32 val;
76
77 /* Enable LTSSM */
78 val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
79 val |= PCIEELBI_APP_LTSSM_ENABLE;
80 writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
81
82 return 0;
83 }
84
eswin_pcie_link_up(struct dw_pcie * pci)85 static bool eswin_pcie_link_up(struct dw_pcie *pci)
86 {
87 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
88 u16 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
89
90 return val & PCI_EXP_LNKSTA_DLLLA;
91 }
92
eswin_pcie_perst_reset(struct eswin_pcie_port * port,struct eswin_pcie * pcie)93 static int eswin_pcie_perst_reset(struct eswin_pcie_port *port,
94 struct eswin_pcie *pcie)
95 {
96 int ret;
97
98 ret = reset_control_assert(port->perst);
99 if (ret) {
100 dev_err(pcie->pci.dev, "Failed to assert PERST#\n");
101 return ret;
102 }
103
104 /* Ensure that PERST# has been asserted for at least 100 ms */
105 msleep(PCIE_T_PVPERL_MS);
106
107 ret = reset_control_deassert(port->perst);
108 if (ret) {
109 dev_err(pcie->pci.dev, "Failed to deassert PERST#\n");
110 return ret;
111 }
112
113 return 0;
114 }
115
eswin_pcie_assert(struct eswin_pcie * pcie)116 static void eswin_pcie_assert(struct eswin_pcie *pcie)
117 {
118 struct eswin_pcie_port *port;
119
120 list_for_each_entry(port, &pcie->ports, list)
121 reset_control_assert(port->perst);
122 reset_control_bulk_assert(ESWIN_NUM_RSTS, pcie->resets);
123 }
124
eswin_pcie_parse_port(struct eswin_pcie * pcie,struct device_node * node)125 static int eswin_pcie_parse_port(struct eswin_pcie *pcie,
126 struct device_node *node)
127 {
128 struct device *dev = pcie->pci.dev;
129 struct eswin_pcie_port *port;
130
131 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
132 if (!port)
133 return -ENOMEM;
134
135 port->perst = of_reset_control_get_exclusive(node, "perst");
136 if (IS_ERR(port->perst)) {
137 dev_err(dev, "Failed to get PERST# reset\n");
138 return PTR_ERR(port->perst);
139 }
140
141 /*
142 * TODO: Since the Root Port node is separated out by pcie devicetree,
143 * the DWC core initialization code can't parse the num-lanes attribute
144 * in the Root Port. Before entering the DWC core initialization code,
145 * the platform driver code parses the Root Port node. The ESWIN only
146 * supports one Root Port node, and the num-lanes attribute is suitable
147 * for the case of one Root Port.
148 */
149 if (!of_property_read_u32(node, "num-lanes", &port->num_lanes))
150 pcie->pci.num_lanes = port->num_lanes;
151
152 INIT_LIST_HEAD(&port->list);
153 list_add_tail(&port->list, &pcie->ports);
154
155 return 0;
156 }
157
eswin_pcie_parse_ports(struct eswin_pcie * pcie)158 static int eswin_pcie_parse_ports(struct eswin_pcie *pcie)
159 {
160 struct eswin_pcie_port *port, *tmp;
161 struct device *dev = pcie->pci.dev;
162 int ret;
163
164 for_each_available_child_of_node_scoped(dev->of_node, of_port) {
165 ret = eswin_pcie_parse_port(pcie, of_port);
166 if (ret)
167 goto err_port;
168 }
169
170 return 0;
171
172 err_port:
173 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
174 reset_control_put(port->perst);
175 list_del(&port->list);
176 }
177
178 return ret;
179 }
180
eswin_pcie_host_init(struct dw_pcie_rp * pp)181 static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
182 {
183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
184 struct eswin_pcie *pcie = to_eswin_pcie(pci);
185 struct eswin_pcie_port *port, *tmp;
186 u32 val;
187 int ret;
188
189 ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
190 if (ret)
191 return ret;
192
193 /*
194 * The PWR and DBI reset signals are respectively used to reset the
195 * PCIe controller and the DBI register.
196 *
197 * The PERST# signal is a reset signal that simultaneously controls the
198 * PCIe controller, PHY, and Endpoint. Before configuring the PHY, the
199 * PERST# signal must first be deasserted.
200 *
201 * The external reference clock is supplied simultaneously to the PHY
202 * and EP. When the PHY is configurable, the entire chip already has
203 * stable power and reference clock. The PHY will be ready within 20ms
204 * after writing app_hold_phy_rst register bit of ELBI register space.
205 */
206 ret = reset_control_bulk_deassert(ESWIN_NUM_RSTS, pcie->resets);
207 if (ret) {
208 dev_err(pcie->pci.dev, "Failed to deassert resets\n");
209 goto err_deassert;
210 }
211
212 /* Configure Root Port type */
213 val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
214 FIELD_MODIFY(PCIEELBI_CTRL0_DEV_TYPE, &val, PCI_EXP_TYPE_ROOT_PORT);
215 writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
216
217 list_for_each_entry(port, &pcie->ports, list) {
218 ret = eswin_pcie_perst_reset(port, pcie);
219 if (ret)
220 goto err_perst;
221 }
222
223 /* Configure app_hold_phy_rst */
224 val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
225 val &= ~PCIEELBI_APP_HOLD_PHY_RST;
226 writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
227
228 /* The maximum waiting time for the clock switch lock is 20ms */
229 ret = readl_poll_timeout(pci->elbi_base + PCIEELBI_STATUS0_OFFSET, val,
230 !(val & PCIEELBI_PM_SEL_AUX_CLK), 1000,
231 20000);
232 if (ret) {
233 dev_err(pci->dev, "Timeout waiting for PM_SEL_AUX_CLK ready\n");
234 goto err_phy_init;
235 }
236
237 /*
238 * Configure ESWIN VID:DID for Root Port as the default values are
239 * invalid.
240 */
241 dw_pcie_dbi_ro_wr_en(pci);
242 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_ESWIN);
243 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_ESWIN_EIC7700);
244 dw_pcie_dbi_ro_wr_dis(pci);
245
246 return 0;
247
248 err_phy_init:
249 list_for_each_entry(port, &pcie->ports, list)
250 reset_control_assert(port->perst);
251 err_perst:
252 reset_control_bulk_assert(ESWIN_NUM_RSTS, pcie->resets);
253 err_deassert:
254 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
255 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
256 reset_control_put(port->perst);
257 list_del(&port->list);
258 }
259
260 return ret;
261 }
262
eswin_pcie_host_deinit(struct dw_pcie_rp * pp)263 static void eswin_pcie_host_deinit(struct dw_pcie_rp *pp)
264 {
265 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
266 struct eswin_pcie *pcie = to_eswin_pcie(pci);
267
268 eswin_pcie_assert(pcie);
269 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
270 }
271
eswin_pcie_pme_turn_off(struct dw_pcie_rp * pp)272 static void eswin_pcie_pme_turn_off(struct dw_pcie_rp *pp)
273 {
274 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
275 struct eswin_pcie *pcie = to_eswin_pcie(pci);
276
277 /*
278 * The ESWIN EIC7700 SoC lacks hardware support for the L2/L3 low-power
279 * link states. It cannot enter the L2/L3 Ready state through the
280 * PME_Turn_Off/PME_To_Ack handshake protocol. To avoid this problem,
281 * the skip_l23_ready has been set.
282 */
283 pp->skip_l23_ready = pcie->data->skip_l23;
284 }
285
286 static const struct dw_pcie_host_ops eswin_pcie_host_ops = {
287 .init = eswin_pcie_host_init,
288 .deinit = eswin_pcie_host_deinit,
289 .pme_turn_off = eswin_pcie_pme_turn_off,
290 };
291
292 static const struct dw_pcie_ops dw_pcie_ops = {
293 .start_link = eswin_pcie_start_link,
294 .link_up = eswin_pcie_link_up,
295 };
296
eswin_pcie_probe(struct platform_device * pdev)297 static int eswin_pcie_probe(struct platform_device *pdev)
298 {
299 const struct eswin_pcie_data *data;
300 struct eswin_pcie_port *port, *tmp;
301 struct device *dev = &pdev->dev;
302 struct eswin_pcie *pcie;
303 struct dw_pcie *pci;
304 int ret, i;
305
306 data = of_device_get_match_data(dev);
307 if (!data)
308 return dev_err_probe(dev, -ENODATA, "No platform data\n");
309
310 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
311 if (!pcie)
312 return -ENOMEM;
313
314 INIT_LIST_HEAD(&pcie->ports);
315
316 pci = &pcie->pci;
317 pci->dev = dev;
318 pci->ops = &dw_pcie_ops;
319 pci->pp.ops = &eswin_pcie_host_ops;
320 pcie->data = data;
321
322 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
323 if (pcie->num_clks < 0)
324 return dev_err_probe(dev, pcie->num_clks,
325 "Failed to get pcie clocks\n");
326
327 for (i = 0; i < ESWIN_NUM_RSTS; i++)
328 pcie->resets[i].id = eswin_pcie_rsts[i];
329
330 ret = devm_reset_control_bulk_get_exclusive(dev, ESWIN_NUM_RSTS,
331 pcie->resets);
332 if (ret)
333 return dev_err_probe(dev, ret, "Failed to get resets\n");
334
335 ret = eswin_pcie_parse_ports(pcie);
336 if (ret)
337 return dev_err_probe(dev, ret, "Failed to parse Root Port\n");
338
339 platform_set_drvdata(pdev, pcie);
340
341 pm_runtime_no_callbacks(dev);
342 devm_pm_runtime_enable(dev);
343 ret = pm_runtime_get_sync(dev);
344 if (ret < 0)
345 goto err_pm_runtime_put;
346
347 ret = dw_pcie_host_init(&pci->pp);
348 if (ret) {
349 dev_err(dev, "Failed to init host\n");
350 goto err_init;
351 }
352
353 return 0;
354
355 err_pm_runtime_put:
356 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
357 reset_control_put(port->perst);
358 list_del(&port->list);
359 }
360 err_init:
361 pm_runtime_put(dev);
362
363 return ret;
364 }
365
eswin_pcie_suspend_noirq(struct device * dev)366 static int eswin_pcie_suspend_noirq(struct device *dev)
367 {
368 struct eswin_pcie *pcie = dev_get_drvdata(dev);
369
370 return dw_pcie_suspend_noirq(&pcie->pci);
371 }
372
eswin_pcie_resume_noirq(struct device * dev)373 static int eswin_pcie_resume_noirq(struct device *dev)
374 {
375 struct eswin_pcie *pcie = dev_get_drvdata(dev);
376
377 return dw_pcie_resume_noirq(&pcie->pci);
378 }
379
380 static DEFINE_NOIRQ_DEV_PM_OPS(eswin_pcie_pm, eswin_pcie_suspend_noirq,
381 eswin_pcie_resume_noirq);
382
383 static const struct eswin_pcie_data eswin_eic7700_data = {
384 .skip_l23 = true,
385 };
386
387 static const struct of_device_id eswin_pcie_of_match[] = {
388 { .compatible = "eswin,eic7700-pcie", .data = &eswin_eic7700_data },
389 {}
390 };
391
392 static struct platform_driver eswin_pcie_driver = {
393 .probe = eswin_pcie_probe,
394 .driver = {
395 .name = "eswin-pcie",
396 .of_match_table = eswin_pcie_of_match,
397 .suppress_bind_attrs = true,
398 .pm = &eswin_pcie_pm,
399 },
400 };
401 builtin_platform_driver(eswin_pcie_driver);
402
403 MODULE_DESCRIPTION("ESWIN PCIe Root Complex driver");
404 MODULE_AUTHOR("Yu Ning <ningyu@eswincomputing.com>");
405 MODULE_AUTHOR("Senchuan Zhang <zhangsenchuan@eswincomputing.com>");
406 MODULE_AUTHOR("Yanghui Ou <ouyanghui@eswincomputing.com>");
407 MODULE_LICENSE("GPL");
408