1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* DSA Driver for MaxLinear GSW1xx switch devices
3 *
4 * Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
5 * Copyright (C) 2023 - 2024 MaxLinear Inc.
6 * Copyright (C) 2022 Snap One, LLC. All rights reserved.
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8 * Copyright (C) 2012 John Crispin <john@phrozen.org>
9 * Copyright (C) 2010 Lantiq Deutschland
10 */
11
12 #include <linux/bits.h>
13 #include <linux/delay.h>
14 #include <linux/jiffies.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/of_mdio.h>
18 #include <linux/phy/phy-common-props.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/workqueue.h>
22 #include <net/dsa.h>
23
24 #include "lantiq_gswip.h"
25 #include "mxl-gsw1xx.h"
26 #include "mxl-gsw1xx_pce.h"
27
28 struct gsw1xx_priv {
29 struct mdio_device *mdio_dev;
30 int smdio_badr;
31 struct regmap *sgmii;
32 struct regmap *gpio;
33 struct regmap *clk;
34 struct regmap *shell;
35 struct phylink_pcs pcs;
36 struct delayed_work clear_raneg;
37 phy_interface_t tbi_interface;
38 struct gswip_priv gswip;
39 };
40
gsw1xx_config_smdio_badr(struct gsw1xx_priv * priv,unsigned int reg)41 static int gsw1xx_config_smdio_badr(struct gsw1xx_priv *priv,
42 unsigned int reg)
43 {
44 struct mii_bus *bus = priv->mdio_dev->bus;
45 int sw_addr = priv->mdio_dev->addr;
46 int smdio_badr = priv->smdio_badr;
47 int res;
48
49 if (smdio_badr == GSW1XX_SMDIO_BADR_UNKNOWN ||
50 reg - smdio_badr >= GSW1XX_SMDIO_BADR ||
51 smdio_badr > reg) {
52 /* Configure the Switch Base Address */
53 smdio_badr = reg & ~GENMASK(3, 0);
54 res = __mdiobus_write(bus, sw_addr, GSW1XX_SMDIO_BADR, smdio_badr);
55 if (res < 0) {
56 dev_err(&priv->mdio_dev->dev,
57 "%s: Error %d, configuring switch base\n",
58 __func__, res);
59 return res;
60 }
61 priv->smdio_badr = smdio_badr;
62 }
63
64 return smdio_badr;
65 }
66
gsw1xx_regmap_read(void * context,unsigned int reg,unsigned int * val)67 static int gsw1xx_regmap_read(void *context, unsigned int reg,
68 unsigned int *val)
69 {
70 struct gsw1xx_priv *priv = context;
71 struct mii_bus *bus = priv->mdio_dev->bus;
72 int sw_addr = priv->mdio_dev->addr;
73 int smdio_badr;
74 int res;
75
76 smdio_badr = gsw1xx_config_smdio_badr(priv, reg);
77 if (smdio_badr < 0)
78 return smdio_badr;
79
80 res = __mdiobus_read(bus, sw_addr, reg - smdio_badr);
81 if (res < 0) {
82 dev_err(&priv->mdio_dev->dev, "%s: Error %d reading 0x%x\n",
83 __func__, res, reg);
84 return res;
85 }
86
87 *val = res;
88
89 return 0;
90 }
91
gsw1xx_regmap_write(void * context,unsigned int reg,unsigned int val)92 static int gsw1xx_regmap_write(void *context, unsigned int reg,
93 unsigned int val)
94 {
95 struct gsw1xx_priv *priv = context;
96 struct mii_bus *bus = priv->mdio_dev->bus;
97 int sw_addr = priv->mdio_dev->addr;
98 int smdio_badr;
99 int res;
100
101 smdio_badr = gsw1xx_config_smdio_badr(priv, reg);
102 if (smdio_badr < 0)
103 return smdio_badr;
104
105 res = __mdiobus_write(bus, sw_addr, reg - smdio_badr, val);
106 if (res < 0)
107 dev_err(&priv->mdio_dev->dev,
108 "%s: Error %d, writing 0x%x:0x%x\n", __func__, res, reg,
109 val);
110
111 return res;
112 }
113
114 static const struct regmap_bus gsw1xx_regmap_bus = {
115 .reg_write = gsw1xx_regmap_write,
116 .reg_read = gsw1xx_regmap_read,
117 };
118
gsw1xx_mdio_regmap_lock(void * mdio_lock)119 static void gsw1xx_mdio_regmap_lock(void *mdio_lock)
120 {
121 mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
122 }
123
gsw1xx_mdio_regmap_unlock(void * mdio_lock)124 static void gsw1xx_mdio_regmap_unlock(void *mdio_lock)
125 {
126 mutex_unlock(mdio_lock);
127 }
128
gsw1xx_pcs_inband_caps(struct phylink_pcs * pcs,phy_interface_t interface)129 static unsigned int gsw1xx_pcs_inband_caps(struct phylink_pcs *pcs,
130 phy_interface_t interface)
131 {
132 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
133 }
134
pcs_to_gsw1xx(struct phylink_pcs * pcs)135 static struct gsw1xx_priv *pcs_to_gsw1xx(struct phylink_pcs *pcs)
136 {
137 return container_of(pcs, struct gsw1xx_priv, pcs);
138 }
139
gsw1xx_pcs_enable(struct phylink_pcs * pcs)140 static int gsw1xx_pcs_enable(struct phylink_pcs *pcs)
141 {
142 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
143
144 /* Deassert SGMII shell reset */
145 return regmap_clear_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
146 GSW1XX_RST_REQ_SGMII_SHELL);
147 }
148
gsw1xx_pcs_disable(struct phylink_pcs * pcs)149 static void gsw1xx_pcs_disable(struct phylink_pcs *pcs)
150 {
151 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
152
153 cancel_delayed_work_sync(&priv->clear_raneg);
154
155 /* Assert SGMII shell reset (will also clear RANEG bit) */
156 regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
157 GSW1XX_RST_REQ_SGMII_SHELL);
158
159 priv->tbi_interface = PHY_INTERFACE_MODE_NA;
160 }
161
gsw1xx_pcs_get_state(struct phylink_pcs * pcs,unsigned int neg_mode,struct phylink_link_state * state)162 static void gsw1xx_pcs_get_state(struct phylink_pcs *pcs,
163 unsigned int neg_mode,
164 struct phylink_link_state *state)
165 {
166 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
167 int ret;
168 u32 val;
169
170 ret = regmap_read(priv->sgmii, GSW1XX_SGMII_TBI_TBISTAT, &val);
171 if (ret < 0)
172 return;
173
174 state->link = !!(val & GSW1XX_SGMII_TBI_TBISTAT_LINK);
175 state->an_complete = !!(val & GSW1XX_SGMII_TBI_TBISTAT_AN_COMPLETE);
176
177 ret = regmap_read(priv->sgmii, GSW1XX_SGMII_TBI_LPSTAT, &val);
178 if (ret < 0)
179 return;
180
181 state->duplex = (val & GSW1XX_SGMII_TBI_LPSTAT_DUPLEX) ?
182 DUPLEX_FULL : DUPLEX_HALF;
183 if (val & GSW1XX_SGMII_TBI_LPSTAT_PAUSE_RX)
184 state->pause |= MLO_PAUSE_RX;
185
186 if (val & GSW1XX_SGMII_TBI_LPSTAT_PAUSE_TX)
187 state->pause |= MLO_PAUSE_TX;
188
189 switch (FIELD_GET(GSW1XX_SGMII_TBI_LPSTAT_SPEED, val)) {
190 case GSW1XX_SGMII_TBI_LPSTAT_SPEED_10:
191 state->speed = SPEED_10;
192 break;
193 case GSW1XX_SGMII_TBI_LPSTAT_SPEED_100:
194 state->speed = SPEED_100;
195 break;
196 case GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000:
197 state->speed = SPEED_1000;
198 break;
199 case GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII:
200 if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
201 state->speed = SPEED_1000;
202 else if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
203 state->speed = SPEED_2500;
204 else
205 state->speed = SPEED_UNKNOWN;
206 break;
207 }
208 }
209
gsw1xx_pcs_phy_xaui_write(struct gsw1xx_priv * priv,u16 addr,u16 data)210 static int gsw1xx_pcs_phy_xaui_write(struct gsw1xx_priv *priv, u16 addr,
211 u16 data)
212 {
213 int ret, val;
214
215 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_D, data);
216 if (ret < 0)
217 return ret;
218
219 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_A, addr);
220 if (ret < 0)
221 return ret;
222
223 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_C,
224 GSW1XX_SGMII_PHY_WRITE |
225 GSW1XX_SGMII_PHY_RESET_N);
226 if (ret < 0)
227 return ret;
228
229 return regmap_read_poll_timeout(priv->sgmii, GSW1XX_SGMII_PHY_C,
230 val, val & GSW1XX_SGMII_PHY_STATUS,
231 1000, 100000);
232 }
233
gsw1xx_pcs_reset(struct gsw1xx_priv * priv,phy_interface_t interface)234 static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv, phy_interface_t interface)
235 {
236 struct dsa_port *sgmii_port;
237 unsigned int pol;
238 int ret;
239 u16 val;
240
241 sgmii_port = dsa_to_port(priv->gswip.ds, GSW1XX_SGMII_PORT);
242 if (!sgmii_port)
243 return -EINVAL;
244
245 /* Assert and deassert SGMII shell reset */
246 ret = regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
247 GSW1XX_RST_REQ_SGMII_SHELL);
248 if (ret < 0)
249 return ret;
250
251 ret = regmap_clear_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
252 GSW1XX_RST_REQ_SGMII_SHELL);
253 if (ret < 0)
254 return ret;
255
256 /* Hardware Bringup FSM Enable */
257 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_HWBU_CTRL,
258 GSW1XX_SGMII_PHY_HWBU_CTRL_EN_HWBU_FSM |
259 GSW1XX_SGMII_PHY_HWBU_CTRL_HW_FSM_EN);
260 if (ret < 0)
261 return ret;
262
263 /* Configure SGMII PHY Receiver */
264 val = FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_EQ,
265 GSW1XX_SGMII_PHY_RX0_CFG2_EQ_DEF) |
266 GSW1XX_SGMII_PHY_RX0_CFG2_LOS_EN |
267 GSW1XX_SGMII_PHY_RX0_CFG2_TERM_EN |
268 FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT,
269 GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF);
270
271 ret = phy_get_manual_rx_polarity(of_fwnode_handle(sgmii_port->dn),
272 phy_modes(interface), &pol);
273 if (ret)
274 return ret;
275
276 /* RX lane seems to be inverted internally, so bit
277 * GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal
278 * (ie. non-inverted) operation matching the chips external pins as
279 * described in datasheets dated 2023-11-08, ie. pin B20 (RX0_P) being
280 * the positive signal and pin B21 (RX0_M) being the negative signal of
281 * the differential input pair.
282 */
283 if (pol == PHY_POL_NORMAL)
284 val |= GSW1XX_SGMII_PHY_RX0_CFG2_INVERT;
285
286 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val);
287 if (ret < 0)
288 return ret;
289
290 val = FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL,
291 GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF);
292
293 ret = phy_get_manual_tx_polarity(of_fwnode_handle(sgmii_port->dn),
294 phy_modes(interface), &pol);
295 if (ret)
296 return ret;
297
298 if (pol == PHY_POL_INVERT)
299 val |= GSW1XX_SGMII_PHY_TX0_CFG3_INVERT;
300
301 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val);
302 if (ret < 0)
303 return ret;
304
305 /* Reset and Release TBI */
306 val = GSW1XX_SGMII_TBI_TBICTL_INITTBI | GSW1XX_SGMII_TBI_TBICTL_ENTBI |
307 GSW1XX_SGMII_TBI_TBICTL_CRSTRR | GSW1XX_SGMII_TBI_TBICTL_CRSOFF;
308 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TBICTL, val);
309 if (ret < 0)
310 return ret;
311 val &= ~GSW1XX_SGMII_TBI_TBICTL_INITTBI;
312 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TBICTL, val);
313 if (ret < 0)
314 return ret;
315
316 /* Release Tx Data Buffers */
317 ret = regmap_set_bits(priv->sgmii, GSW1XX_SGMII_PCS_TXB_CTL,
318 GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB);
319 if (ret < 0)
320 return ret;
321 ret = regmap_clear_bits(priv->sgmii, GSW1XX_SGMII_PCS_TXB_CTL,
322 GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB);
323 if (ret < 0)
324 return ret;
325
326 /* Release Rx Data Buffers */
327 ret = regmap_set_bits(priv->sgmii, GSW1XX_SGMII_PCS_RXB_CTL,
328 GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB);
329 if (ret < 0)
330 return ret;
331 return regmap_clear_bits(priv->sgmii, GSW1XX_SGMII_PCS_RXB_CTL,
332 GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB);
333 }
334
gsw1xx_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)335 static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
336 phy_interface_t interface,
337 const unsigned long *advertising,
338 bool permit_pause_to_mac)
339 {
340 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
341 u16 txaneg, anegctl, nco_ctrl;
342 bool reconf = false;
343 int ret = 0;
344
345 /* do not unnecessarily disrupt link and skip resetting the hardware in
346 * case the PCS has previously been successfully configured for this
347 * interface mode
348 */
349 if (priv->tbi_interface == interface)
350 reconf = true;
351
352 /* mark PCS configuration as incomplete */
353 priv->tbi_interface = PHY_INTERFACE_MODE_NA;
354
355 if (!reconf)
356 ret = gsw1xx_pcs_reset(priv, interface);
357
358 if (ret)
359 return ret;
360
361 /* override bootstrap pin settings
362 * OVRANEG sets ANEG Mode, Enable ANEG and restart ANEG to be
363 * taken from bits ANMODE, ANEGEN, RANEG of the ANEGCTL register.
364 * OVERABL sets ability bits in tx_config_reg to be taken from
365 * the TXANEGH and TXANEGL registers.
366 */
367 anegctl = GSW1XX_SGMII_TBI_ANEGCTL_OVRANEG |
368 GSW1XX_SGMII_TBI_ANEGCTL_OVRABL;
369
370 switch (phylink_get_link_timer_ns(interface)) {
371 case 10000:
372 anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
373 GSW1XX_SGMII_TBI_ANEGCTL_LT_10US);
374 break;
375 case 1600000:
376 anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
377 GSW1XX_SGMII_TBI_ANEGCTL_LT_1_6MS);
378 break;
379 case 5000000:
380 anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
381 GSW1XX_SGMII_TBI_ANEGCTL_LT_5MS);
382 break;
383 case 10000000:
384 anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_LT,
385 GSW1XX_SGMII_TBI_ANEGCTL_LT_10MS);
386 break;
387 default:
388 return -EINVAL;
389 }
390
391 if (neg_mode & PHYLINK_PCS_NEG_INBAND)
392 anegctl |= GSW1XX_SGMII_TBI_ANEGCTL_ANEGEN;
393
394 txaneg = phylink_mii_c22_pcs_encode_advertisement(interface, advertising);
395
396 if (interface == PHY_INTERFACE_MODE_SGMII) {
397 /* lacking a defined reverse-SGMII interface mode this
398 * driver only supports SGMII (MAC side) for now
399 */
400 anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_ANMODE,
401 GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_MAC);
402 txaneg |= ADVERTISE_LPACK;
403 } else if (interface == PHY_INTERFACE_MODE_1000BASEX ||
404 interface == PHY_INTERFACE_MODE_2500BASEX) {
405 anegctl |= FIELD_PREP(GSW1XX_SGMII_TBI_ANEGCTL_ANMODE,
406 GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_1000BASEX);
407 } else {
408 dev_err(priv->gswip.dev, "%s: wrong interface mode %s\n",
409 __func__, phy_modes(interface));
410 return -EINVAL;
411 }
412
413 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TXANEGH,
414 FIELD_GET(GENMASK(15, 8), txaneg));
415 if (ret < 0)
416 return ret;
417 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_TXANEGL,
418 FIELD_GET(GENMASK(7, 0), txaneg));
419 if (ret < 0)
420 return ret;
421 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL, anegctl);
422 if (ret < 0)
423 return ret;
424
425 if (!reconf) {
426 /* setup SerDes clock speed */
427 if (interface == PHY_INTERFACE_MODE_2500BASEX)
428 nco_ctrl = GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2;
429 else
430 nco_ctrl = GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1;
431
432 ret = regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL,
433 GSW1XX_SGMII_HSP_MASK |
434 GSW1XX_SGMII_SEL,
435 nco_ctrl);
436 if (ret)
437 return ret;
438
439 ret = gsw1xx_pcs_phy_xaui_write(priv, 0x30, 0x80);
440 if (ret)
441 return ret;
442 }
443
444 /* PCS configuration has now been completed, store mode to prevent
445 * disrupting the link in case of future calls of this function for the
446 * same interface mode.
447 */
448 priv->tbi_interface = interface;
449
450 return 0;
451 }
452
gsw1xx_pcs_clear_raneg(struct work_struct * work)453 static void gsw1xx_pcs_clear_raneg(struct work_struct *work)
454 {
455 struct gsw1xx_priv *priv =
456 container_of(work, struct gsw1xx_priv, clear_raneg.work);
457
458 regmap_clear_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
459 GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
460 }
461
gsw1xx_pcs_an_restart(struct phylink_pcs * pcs)462 static void gsw1xx_pcs_an_restart(struct phylink_pcs *pcs)
463 {
464 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
465
466 cancel_delayed_work_sync(&priv->clear_raneg);
467
468 regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
469 GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
470
471 /* despite being documented as self-clearing, the RANEG bit
472 * sometimes remains set, preventing auto-negotiation from happening.
473 * MaxLinear advises to manually clear the bit after 10ms.
474 */
475 schedule_delayed_work(&priv->clear_raneg, msecs_to_jiffies(10));
476 }
477
gsw1xx_pcs_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)478 static void gsw1xx_pcs_link_up(struct phylink_pcs *pcs,
479 unsigned int neg_mode,
480 phy_interface_t interface, int speed,
481 int duplex)
482 {
483 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
484 u16 lpstat;
485
486 /* When in-band AN is enabled hardware will set lpstat */
487 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
488 return;
489
490 /* Force speed and duplex settings */
491 if (interface == PHY_INTERFACE_MODE_SGMII) {
492 if (speed == SPEED_10)
493 lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
494 GSW1XX_SGMII_TBI_LPSTAT_SPEED_10);
495 else if (speed == SPEED_100)
496 lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
497 GSW1XX_SGMII_TBI_LPSTAT_SPEED_100);
498 else
499 lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
500 GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000);
501 } else {
502 lpstat = FIELD_PREP(GSW1XX_SGMII_TBI_LPSTAT_SPEED,
503 GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII);
504 }
505
506 if (duplex == DUPLEX_FULL)
507 lpstat |= GSW1XX_SGMII_TBI_LPSTAT_DUPLEX;
508
509 regmap_write(priv->sgmii, GSW1XX_SGMII_TBI_LPSTAT, lpstat);
510 }
511
512 static const struct phylink_pcs_ops gsw1xx_pcs_ops = {
513 .pcs_inband_caps = gsw1xx_pcs_inband_caps,
514 .pcs_enable = gsw1xx_pcs_enable,
515 .pcs_disable = gsw1xx_pcs_disable,
516 .pcs_get_state = gsw1xx_pcs_get_state,
517 .pcs_config = gsw1xx_pcs_config,
518 .pcs_an_restart = gsw1xx_pcs_an_restart,
519 .pcs_link_up = gsw1xx_pcs_link_up,
520 };
521
gsw1xx_phylink_get_lpi_caps(struct phylink_config * config)522 static void gsw1xx_phylink_get_lpi_caps(struct phylink_config *config)
523 {
524 config->lpi_capabilities = MAC_100FD | MAC_1000FD;
525 config->lpi_timer_default = 20;
526 memcpy(config->lpi_interfaces, config->supported_interfaces,
527 sizeof(config->lpi_interfaces));
528 }
529
gsw1xx_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)530 static void gsw1xx_phylink_get_caps(struct dsa_switch *ds, int port,
531 struct phylink_config *config)
532 {
533 struct gswip_priv *priv = ds->priv;
534
535 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
536 MAC_10 | MAC_100 | MAC_1000;
537
538 switch (port) {
539 case 0 ... 3: /* built-in PHYs */
540 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
541 config->supported_interfaces);
542 break;
543
544 case 4: /* SGMII */
545 __set_bit(PHY_INTERFACE_MODE_SGMII,
546 config->supported_interfaces);
547 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
548 config->supported_interfaces);
549 if (priv->hw_info->supports_2500m) {
550 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
551 config->supported_interfaces);
552 config->mac_capabilities |= MAC_2500FD;
553 }
554 return; /* no support for EEE on SGMII port */
555
556 case 5: /* RGMII or RMII */
557 __set_bit(PHY_INTERFACE_MODE_RMII,
558 config->supported_interfaces);
559 phy_interface_set_rgmii(config->supported_interfaces);
560 break;
561 }
562
563 gsw1xx_phylink_get_lpi_caps(config);
564 }
565
gsw150_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)566 static void gsw150_phylink_get_caps(struct dsa_switch *ds, int port,
567 struct phylink_config *config)
568 {
569 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
570 MAC_10 | MAC_100 | MAC_1000;
571
572 switch (port) {
573 case 0 ... 4: /* built-in PHYs */
574 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
575 config->supported_interfaces);
576 break;
577
578 case 5: /* GMII or RGMII */
579 __set_bit(PHY_INTERFACE_MODE_GMII,
580 config->supported_interfaces);
581 fallthrough;
582
583 case 6: /* RGMII */
584 phy_interface_set_rgmii(config->supported_interfaces);
585 break;
586 }
587
588 gsw1xx_phylink_get_lpi_caps(config);
589 }
590
gsw1xx_phylink_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)591 static struct phylink_pcs *gsw1xx_phylink_mac_select_pcs(struct phylink_config *config,
592 phy_interface_t interface)
593 {
594 struct dsa_port *dp = dsa_phylink_to_port(config);
595 struct gswip_priv *gswip_priv = dp->ds->priv;
596 struct gsw1xx_priv *gsw1xx_priv = container_of(gswip_priv,
597 struct gsw1xx_priv,
598 gswip);
599
600 switch (dp->index) {
601 case GSW1XX_SGMII_PORT:
602 return &gsw1xx_priv->pcs;
603 default:
604 return NULL;
605 }
606 }
607
gsw1xx_rmii_slew_rate(const struct device_node * np,struct gsw1xx_priv * priv,const char * prop,u16 mask)608 static int gsw1xx_rmii_slew_rate(const struct device_node *np, struct gsw1xx_priv *priv,
609 const char *prop, u16 mask)
610 {
611 u32 rate;
612 int ret;
613
614 ret = of_property_read_u32(np, prop, &rate);
615 /* Optional property */
616 if (ret == -EINVAL)
617 return 0;
618 if (ret < 0 || rate > 1) {
619 dev_err(&priv->mdio_dev->dev, "Invalid %s value\n", prop);
620 return (ret < 0) ? ret : -EINVAL;
621 }
622
623 return regmap_update_bits(priv->shell, GSW1XX_SHELL_RGMII_SLEW_CFG, mask, mask * rate);
624 }
625
gsw1xx_port_setup(struct dsa_switch * ds,int port)626 static int gsw1xx_port_setup(struct dsa_switch *ds, int port)
627 {
628 struct dsa_port *dp = dsa_to_port(ds, port);
629 struct device_node *np = dp->dn;
630 struct gsw1xx_priv *gsw1xx_priv;
631 struct gswip_priv *gswip_priv;
632
633 if (dp->index != GSW1XX_MII_PORT)
634 return 0;
635
636 gswip_priv = ds->priv;
637 gsw1xx_priv = container_of(gswip_priv, struct gsw1xx_priv, gswip);
638
639 return gsw1xx_rmii_slew_rate(np, gsw1xx_priv,
640 "maxlinear,slew-rate-txc", RGMII_SLEW_CFG_DRV_TXC) ?:
641 gsw1xx_rmii_slew_rate(np, gsw1xx_priv,
642 "maxlinear,slew-rate-txd", RGMII_SLEW_CFG_DRV_TXD);
643 }
644
gsw1xx_regmap_init(struct gsw1xx_priv * priv,const char * name,unsigned int reg_base,unsigned int max_register)645 static struct regmap *gsw1xx_regmap_init(struct gsw1xx_priv *priv,
646 const char *name,
647 unsigned int reg_base,
648 unsigned int max_register)
649 {
650 const struct regmap_config config = {
651 .name = name,
652 .reg_bits = 16,
653 .val_bits = 16,
654 .reg_base = reg_base,
655 .max_register = max_register,
656 .lock = gsw1xx_mdio_regmap_lock,
657 .unlock = gsw1xx_mdio_regmap_unlock,
658 .lock_arg = &priv->mdio_dev->bus->mdio_lock,
659 };
660
661 return devm_regmap_init(&priv->mdio_dev->dev, &gsw1xx_regmap_bus,
662 priv, &config);
663 }
664
gsw1xx_serdes_pcs_init(struct gsw1xx_priv * priv)665 static int gsw1xx_serdes_pcs_init(struct gsw1xx_priv *priv)
666 {
667 /* do nothing if the chip doesn't have a SerDes PCS */
668 if (!priv->gswip.hw_info->mac_select_pcs)
669 return 0;
670
671 priv->pcs.ops = &gsw1xx_pcs_ops;
672 priv->pcs.poll = true;
673 __set_bit(PHY_INTERFACE_MODE_SGMII,
674 priv->pcs.supported_interfaces);
675 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
676 priv->pcs.supported_interfaces);
677 if (priv->gswip.hw_info->supports_2500m)
678 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
679 priv->pcs.supported_interfaces);
680 priv->tbi_interface = PHY_INTERFACE_MODE_NA;
681
682 /* assert SGMII reset to power down SGMII unit */
683 return regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ,
684 GSW1XX_RST_REQ_SGMII_SHELL);
685 }
686
gsw1xx_probe(struct mdio_device * mdiodev)687 static int gsw1xx_probe(struct mdio_device *mdiodev)
688 {
689 struct device *dev = &mdiodev->dev;
690 struct gsw1xx_priv *priv;
691 u32 version, val;
692 u8 shellver;
693 u16 pnum;
694 int ret;
695
696 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
697 if (!priv)
698 return -ENOMEM;
699
700 priv->mdio_dev = mdiodev;
701 priv->smdio_badr = GSW1XX_SMDIO_BADR_UNKNOWN;
702
703 priv->gswip.dev = dev;
704 priv->gswip.hw_info = of_device_get_match_data(dev);
705 if (!priv->gswip.hw_info)
706 return -EINVAL;
707
708 priv->gswip.gswip = gsw1xx_regmap_init(priv, "switch",
709 GSW1XX_SWITCH_BASE, 0xfff);
710 if (IS_ERR(priv->gswip.gswip))
711 return PTR_ERR(priv->gswip.gswip);
712
713 priv->gswip.mdio = gsw1xx_regmap_init(priv, "mdio", GSW1XX_MMDIO_BASE,
714 0xff);
715 if (IS_ERR(priv->gswip.mdio))
716 return PTR_ERR(priv->gswip.mdio);
717
718 priv->gswip.mii = gsw1xx_regmap_init(priv, "mii", GSW1XX_RGMII_BASE,
719 0xff);
720 if (IS_ERR(priv->gswip.mii))
721 return PTR_ERR(priv->gswip.mii);
722
723 priv->sgmii = gsw1xx_regmap_init(priv, "sgmii", GSW1XX_SGMII_BASE,
724 0xfff);
725 if (IS_ERR(priv->sgmii))
726 return PTR_ERR(priv->sgmii);
727
728 priv->gpio = gsw1xx_regmap_init(priv, "gpio", GSW1XX_GPIO_BASE, 0xff);
729 if (IS_ERR(priv->gpio))
730 return PTR_ERR(priv->gpio);
731
732 priv->clk = gsw1xx_regmap_init(priv, "clk", GSW1XX_CLK_BASE, 0xff);
733 if (IS_ERR(priv->clk))
734 return PTR_ERR(priv->clk);
735
736 priv->shell = gsw1xx_regmap_init(priv, "shell", GSW1XX_SHELL_BASE,
737 0xff);
738 if (IS_ERR(priv->shell))
739 return PTR_ERR(priv->shell);
740
741 ret = regmap_read(priv->shell, GSW1XX_SHELL_MANU_ID, &val);
742 if (ret < 0)
743 return ret;
744
745 /* validate chip ID */
746 if (FIELD_GET(GSW1XX_SHELL_MANU_ID_FIX1, val) != 1)
747 return -ENODEV;
748
749 if (FIELD_GET(GSW1XX_SHELL_MANU_ID_MANID, val) !=
750 GSW1XX_SHELL_MANU_ID_MANID_VAL)
751 return -ENODEV;
752
753 pnum = FIELD_GET(GSW1XX_SHELL_MANU_ID_PNUML, val);
754
755 ret = regmap_read(priv->shell, GSW1XX_SHELL_PNUM_ID, &val);
756 if (ret < 0)
757 return ret;
758
759 pnum |= FIELD_GET(GSW1XX_SHELL_PNUM_ID_PNUMM, val) << 4;
760 shellver = FIELD_GET(GSW1XX_SHELL_PNUM_ID_VER, val);
761
762 ret = gsw1xx_serdes_pcs_init(priv);
763 if (ret < 0)
764 return ret;
765
766 /* configure GPIO pin-mux for MMDIO in case of external PHY connected to
767 * SGMII or RGMII as slave interface
768 */
769 regmap_set_bits(priv->gpio, GPIO_ALTSEL0, 3);
770 regmap_set_bits(priv->gpio, GPIO_ALTSEL1, 3);
771
772 ret = regmap_read(priv->gswip.gswip, GSWIP_VERSION, &version);
773 if (ret)
774 return ret;
775
776 INIT_DELAYED_WORK(&priv->clear_raneg, gsw1xx_pcs_clear_raneg);
777
778 ret = gswip_probe_common(&priv->gswip, version);
779 if (ret)
780 return ret;
781
782 dev_info(dev, "standalone switch part number 0x%x v1.%u\n", pnum, shellver);
783
784 dev_set_drvdata(dev, &priv->gswip);
785
786 return 0;
787 }
788
gsw1xx_remove(struct mdio_device * mdiodev)789 static void gsw1xx_remove(struct mdio_device *mdiodev)
790 {
791 struct gswip_priv *priv = dev_get_drvdata(&mdiodev->dev);
792 struct gsw1xx_priv *gsw1xx_priv;
793
794 if (!priv)
795 return;
796
797 dsa_unregister_switch(priv->ds);
798
799 gsw1xx_priv = container_of(priv, struct gsw1xx_priv, gswip);
800 cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
801 }
802
gsw1xx_shutdown(struct mdio_device * mdiodev)803 static void gsw1xx_shutdown(struct mdio_device *mdiodev)
804 {
805 struct gswip_priv *priv = dev_get_drvdata(&mdiodev->dev);
806 struct gsw1xx_priv *gsw1xx_priv;
807
808 if (!priv)
809 return;
810
811 dsa_switch_shutdown(priv->ds);
812
813 dev_set_drvdata(&mdiodev->dev, NULL);
814
815 gsw1xx_priv = container_of(priv, struct gsw1xx_priv, gswip);
816 cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
817 }
818
819 static const struct gswip_hw_info gsw12x_data = {
820 .max_ports = GSW1XX_PORTS,
821 .allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT),
822 .mii_cfg = {
823 [0 ... GSW1XX_MII_PORT - 1] = -1,
824 [GSW1XX_MII_PORT] = GSWIP_MII_CFGp(0),
825 [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1,
826 },
827 .mii_pcdu = {
828 [0 ... GSW1XX_MII_PORT - 1] = -1,
829 [GSW1XX_MII_PORT] = GSWIP_MII_PCDU0,
830 [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1,
831 },
832 .mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
833 .phylink_get_caps = &gsw1xx_phylink_get_caps,
834 .supports_2500m = true,
835 .port_setup = gsw1xx_port_setup,
836 .pce_microcode = &gsw1xx_pce_microcode,
837 .pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
838 .tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
839 };
840
841 static const struct gswip_hw_info gsw140_data = {
842 .max_ports = GSW1XX_PORTS,
843 .allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT),
844 .mii_cfg = {
845 [0 ... GSW1XX_MII_PORT - 1] = -1,
846 [GSW1XX_MII_PORT] = GSWIP_MII_CFGp(0),
847 [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1,
848 },
849 .mii_pcdu = {
850 [0 ... GSW1XX_MII_PORT - 1] = -1,
851 [GSW1XX_MII_PORT] = GSWIP_MII_PCDU0,
852 [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1,
853 },
854 .mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
855 .phylink_get_caps = &gsw1xx_phylink_get_caps,
856 .supports_2500m = true,
857 .port_setup = gsw1xx_port_setup,
858 .pce_microcode = &gsw1xx_pce_microcode,
859 .pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
860 .tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
861 };
862
863 static const struct gswip_hw_info gsw141_data = {
864 .max_ports = GSW1XX_PORTS,
865 .allowed_cpu_ports = BIT(GSW1XX_MII_PORT) | BIT(GSW1XX_SGMII_PORT),
866 .mii_cfg = {
867 [0 ... GSW1XX_MII_PORT - 1] = -1,
868 [GSW1XX_MII_PORT] = GSWIP_MII_CFGp(0),
869 [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1,
870 },
871 .mii_pcdu = {
872 [0 ... GSW1XX_MII_PORT - 1] = -1,
873 [GSW1XX_MII_PORT] = GSWIP_MII_PCDU0,
874 [GSW1XX_MII_PORT + 1 ... GSWIP_MAX_PORTS - 1] = -1,
875 },
876 .mac_select_pcs = gsw1xx_phylink_mac_select_pcs,
877 .phylink_get_caps = gsw1xx_phylink_get_caps,
878 .port_setup = gsw1xx_port_setup,
879 .pce_microcode = &gsw1xx_pce_microcode,
880 .pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
881 .tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
882 };
883
884 static const struct gswip_hw_info gsw150_data = {
885 .max_ports = GSW150_PORTS,
886 .allowed_cpu_ports = BIT(5) | BIT(6),
887 .mii_cfg = {
888 [0 ... 4] = -1,
889 [5] = 0,
890 [6] = 10,
891 },
892 .mii_pcdu = {
893 [0 ... 4] = -1,
894 [5] = 1,
895 [6] = 11,
896 },
897 .phylink_get_caps = gsw150_phylink_get_caps,
898 /* There is only a single RGMII_SLEW_CFG register in GSW150 and it is
899 * unknown if RGMII slew configuration affects both RGMII ports
900 * or only port 5. Use .port_setup which assumes it affects port 5
901 * for now.
902 */
903 .port_setup = gsw1xx_port_setup,
904 .pce_microcode = &gsw1xx_pce_microcode,
905 .pce_microcode_size = ARRAY_SIZE(gsw1xx_pce_microcode),
906 .tag_protocol = DSA_TAG_PROTO_MXL_GSW1XX,
907 };
908
909 /*
910 * GSW125 is the industrial temperature version of GSW120.
911 * GSW145 is the industrial temperature version of GSW140.
912 */
913 static const struct of_device_id gsw1xx_of_match[] = {
914 { .compatible = "intel,gsw150", .data = &gsw150_data },
915 { .compatible = "lantiq,peb7084", .data = &gsw150_data },
916 { .compatible = "maxlinear,gsw120", .data = &gsw12x_data },
917 { .compatible = "maxlinear,gsw125", .data = &gsw12x_data },
918 { .compatible = "maxlinear,gsw140", .data = &gsw140_data },
919 { .compatible = "maxlinear,gsw141", .data = &gsw141_data },
920 { .compatible = "maxlinear,gsw145", .data = &gsw140_data },
921 { /* sentinel */ },
922 };
923
924 MODULE_DEVICE_TABLE(of, gsw1xx_of_match);
925
926 static struct mdio_driver gsw1xx_driver = {
927 .probe = gsw1xx_probe,
928 .remove = gsw1xx_remove,
929 .shutdown = gsw1xx_shutdown,
930 .mdiodrv.driver = {
931 .name = "mxl-gsw1xx",
932 .of_match_table = gsw1xx_of_match,
933 },
934 };
935
936 mdio_module_driver(gsw1xx_driver);
937
938 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
939 MODULE_DESCRIPTION("Driver for Intel/MaxLinear GSW1xx Ethernet switch");
940 MODULE_LICENSE("GPL");
941