1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/acpi.h>
5 #include <linux/device.h>
6 #include <linux/etherdevice.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/pci.h>
14 #include <linux/platform_device.h>
15 #include <linux/if_vlan.h>
16 #include <linux/crash_dump.h>
17
18 #include <net/rtnetlink.h>
19
20 #include "hclge_cmd.h"
21 #include "hclge_dcb.h"
22 #include "hclge_main.h"
23 #include "hclge_mbx.h"
24 #include "hclge_mdio.h"
25 #include "hclge_regs.h"
26 #include "hclge_tm.h"
27 #include "hclge_err.h"
28 #include "hnae3.h"
29 #include "hclge_devlink.h"
30 #include "hclge_comm_cmd.h"
31
32 #include "hclge_trace.h"
33
34 #define HCLGE_NAME "hclge"
35
36 #define HCLGE_BUF_SIZE_UNIT 256U
37 #define HCLGE_BUF_MUL_BY 2
38 #define HCLGE_BUF_DIV_BY 2
39 #define NEED_RESERVE_TC_NUM 2
40 #define BUF_MAX_PERCENT 100
41 #define BUF_RESERVE_PERCENT 90
42
43 #define HCLGE_RESET_MAX_FAIL_CNT 5
44 #define HCLGE_RESET_SYNC_TIME 100
45 #define HCLGE_PF_RESET_SYNC_TIME 20
46 #define HCLGE_PF_RESET_SYNC_CNT 1500
47
48 #define HCLGE_LINK_STATUS_MS 10
49
50 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
51 static int hclge_init_vlan_config(struct hclge_dev *hdev);
52 static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
53 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
54 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle);
55 static void hclge_rfs_filter_expire(struct hclge_dev *hdev);
56 static int hclge_clear_arfs_rules(struct hclge_dev *hdev);
57 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
58 unsigned long *addr);
59 static int hclge_set_default_loopback(struct hclge_dev *hdev);
60
61 static void hclge_sync_mac_table(struct hclge_dev *hdev);
62 static void hclge_restore_hw_table(struct hclge_dev *hdev);
63 static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
64 static void hclge_sync_fd_table(struct hclge_dev *hdev);
65 static void hclge_update_fec_stats(struct hclge_dev *hdev);
66 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
67 int wait_cnt);
68 static int hclge_update_port_info(struct hclge_dev *hdev);
69
70 static struct hnae3_ae_algo ae_algo;
71
72 static struct workqueue_struct *hclge_wq;
73
74 static const struct pci_device_id ae_algo_pci_tbl[] = {
75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
83 /* required last entry */
84 {0, }
85 };
86
87 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
88
89 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
90 "External Loopback test",
91 "App Loopback test",
92 "Serdes serial Loopback test",
93 "Serdes parallel Loopback test",
94 "Phy Loopback test"
95 };
96
97 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
98 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
100 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
102 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)},
104 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)},
106 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
108 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
109 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
110 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
112 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
114 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
116 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
118 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
120 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
122 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
124 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
126 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
128 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)},
130 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)},
132 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)},
134 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)},
136 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)},
138 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)},
140 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
141 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)},
142 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
143 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)},
144 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
146 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
148 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
150 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
152 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
154 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
156 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
158 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
160 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
162 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)},
164 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)},
166 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)},
168 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)},
170 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)},
172 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)},
174 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
175 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)},
176 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
177 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)},
178 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
180 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
182 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
184 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
186 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
188 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
190 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
192 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
194 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
196 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
198 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
200 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
202 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
204 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
206 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
208 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
210 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
212 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
214 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
216 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
218 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
220 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
222 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
224 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
226 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
228 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
230 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
232 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
234 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
236 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
238 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
240 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
242 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
244 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
246 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
248 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
250 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
252 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
254 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
256 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
258 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
260 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
262 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
264 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
266 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
268 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
270 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
272 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
274 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
275 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
276 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
277 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
278
279 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
281 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
283 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
285 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
287 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
289 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
291 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
293 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
295 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
297 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
299 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
301 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
303 };
304
305 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
306 {
307 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
308 .ethter_type = cpu_to_le16(ETH_P_LLDP),
309 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e},
310 .i_port_bitmap = 0x1,
311 },
312 };
313
314 static const struct key_info meta_data_key_info[] = {
315 { PACKET_TYPE_ID, 6 },
316 { IP_FRAGEMENT, 1 },
317 { ROCE_TYPE, 1 },
318 { NEXT_KEY, 5 },
319 { VLAN_NUMBER, 2 },
320 { SRC_VPORT, 12 },
321 { DST_VPORT, 12 },
322 { TUNNEL_PACKET, 1 },
323 };
324
325 static const struct key_info tuple_key_info[] = {
326 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
327 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
328 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
329 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
330 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
331 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
332 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
333 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
334 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 },
335 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 },
336 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
337 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
338 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
339 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
340 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
341 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
342 { INNER_DST_MAC, 48, KEY_OPT_MAC,
343 offsetof(struct hclge_fd_rule, tuples.dst_mac),
344 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) },
345 { INNER_SRC_MAC, 48, KEY_OPT_MAC,
346 offsetof(struct hclge_fd_rule, tuples.src_mac),
347 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) },
348 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16,
349 offsetof(struct hclge_fd_rule, tuples.vlan_tag1),
350 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) },
351 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
352 { INNER_ETH_TYPE, 16, KEY_OPT_LE16,
353 offsetof(struct hclge_fd_rule, tuples.ether_proto),
354 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) },
355 { INNER_L2_RSV, 16, KEY_OPT_LE16,
356 offsetof(struct hclge_fd_rule, tuples.l2_user_def),
357 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) },
358 { INNER_IP_TOS, 8, KEY_OPT_U8,
359 offsetof(struct hclge_fd_rule, tuples.ip_tos),
360 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) },
361 { INNER_IP_PROTO, 8, KEY_OPT_U8,
362 offsetof(struct hclge_fd_rule, tuples.ip_proto),
363 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) },
364 { INNER_SRC_IP, 32, KEY_OPT_IP,
365 offsetof(struct hclge_fd_rule, tuples.src_ip),
366 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) },
367 { INNER_DST_IP, 32, KEY_OPT_IP,
368 offsetof(struct hclge_fd_rule, tuples.dst_ip),
369 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) },
370 { INNER_L3_RSV, 16, KEY_OPT_LE16,
371 offsetof(struct hclge_fd_rule, tuples.l3_user_def),
372 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) },
373 { INNER_SRC_PORT, 16, KEY_OPT_LE16,
374 offsetof(struct hclge_fd_rule, tuples.src_port),
375 offsetof(struct hclge_fd_rule, tuples_mask.src_port) },
376 { INNER_DST_PORT, 16, KEY_OPT_LE16,
377 offsetof(struct hclge_fd_rule, tuples.dst_port),
378 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) },
379 { INNER_L4_RSV, 32, KEY_OPT_LE32,
380 offsetof(struct hclge_fd_rule, tuples.l4_user_def),
381 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) },
382 };
383
384 /**
385 * hclge_cmd_send - send command to command queue
386 * @hw: pointer to the hw struct
387 * @desc: prefilled descriptor for describing the command
388 * @num : the number of descriptors to be sent
389 *
390 * This is the main send command for command queue, it
391 * sends the queue, cleans the queue, etc
392 **/
hclge_cmd_send(struct hclge_hw * hw,struct hclge_desc * desc,int num)393 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
394 {
395 return hclge_comm_cmd_send(&hw->hw, desc, num);
396 }
397
hclge_trace_cmd_send(struct hclge_comm_hw * hw,struct hclge_desc * desc,int num,bool is_special)398 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
399 int num, bool is_special)
400 {
401 int i;
402
403 trace_hclge_pf_cmd_send(hw, desc, 0, num);
404
405 if (!is_special) {
406 for (i = 1; i < num; i++)
407 trace_hclge_pf_cmd_send(hw, &desc[i], i, num);
408 } else {
409 for (i = 1; i < num; i++)
410 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i],
411 i, num);
412 }
413 }
414
hclge_trace_cmd_get(struct hclge_comm_hw * hw,struct hclge_desc * desc,int num,bool is_special)415 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc,
416 int num, bool is_special)
417 {
418 int i;
419
420 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))
421 return;
422
423 trace_hclge_pf_cmd_get(hw, desc, 0, num);
424
425 if (!is_special) {
426 for (i = 1; i < num; i++)
427 trace_hclge_pf_cmd_get(hw, &desc[i], i, num);
428 } else {
429 for (i = 1; i < num; i++)
430 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i],
431 i, num);
432 }
433 }
434
435 static const struct hclge_comm_cmq_ops hclge_cmq_ops = {
436 .trace_cmd_send = hclge_trace_cmd_send,
437 .trace_cmd_get = hclge_trace_cmd_get,
438 };
439
hclge_mac_update_stats_defective(struct hclge_dev * hdev)440 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
441 {
442 #define HCLGE_MAC_CMD_NUM 21
443
444 u64 *data = (u64 *)(&hdev->mac_stats);
445 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
446 __le64 *desc_data;
447 u32 data_size;
448 int ret;
449 u32 i;
450
451 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
452 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
453 if (ret) {
454 dev_err(&hdev->pdev->dev,
455 "Get MAC pkt stats fail, status = %d.\n", ret);
456
457 return ret;
458 }
459
460 /* The first desc has a 64-bit header, so data size need to minus 1 */
461 data_size = sizeof(desc) / (sizeof(u64)) - 1;
462
463 desc_data = (__le64 *)(&desc[0].data[0]);
464 for (i = 0; i < data_size; i++) {
465 /* data memory is continuous becase only the first desc has a
466 * header in this command
467 */
468 *data += le64_to_cpu(*desc_data);
469 data++;
470 desc_data++;
471 }
472
473 return 0;
474 }
475
hclge_mac_update_stats_complete(struct hclge_dev * hdev)476 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev)
477 {
478 #define HCLGE_REG_NUM_PER_DESC 4
479
480 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;
481 u64 *data = (u64 *)(&hdev->mac_stats);
482 struct hclge_desc *desc;
483 __le64 *desc_data;
484 u32 data_size;
485 u32 desc_num;
486 int ret;
487 u32 i;
488
489 /* The first desc has a 64-bit header, so need to consider it */
490 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
491
492 /* This may be called inside atomic sections,
493 * so GFP_ATOMIC is more suitable here
494 */
495 desc = kzalloc_objs(struct hclge_desc, desc_num, GFP_ATOMIC);
496 if (!desc)
497 return -ENOMEM;
498
499 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
500 ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
501 if (ret) {
502 kfree(desc);
503 return ret;
504 }
505
506 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);
507
508 desc_data = (__le64 *)(&desc[0].data[0]);
509 for (i = 0; i < data_size; i++) {
510 /* data memory is continuous becase only the first desc has a
511 * header in this command
512 */
513 *data += le64_to_cpu(*desc_data);
514 data++;
515 desc_data++;
516 }
517
518 kfree(desc);
519
520 return 0;
521 }
522
hclge_mac_query_reg_num(struct hclge_dev * hdev,u32 * reg_num)523 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
524 {
525 struct hclge_desc desc;
526 int ret;
527
528 /* Driver needs total register number of both valid registers and
529 * reserved registers, but the old firmware only returns number
530 * of valid registers in device V2. To be compatible with these
531 * devices, driver uses a fixed value.
532 */
533 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
534 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
535 return 0;
536 }
537
538 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
539 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
540 if (ret) {
541 dev_err(&hdev->pdev->dev,
542 "failed to query mac statistic reg number, ret = %d\n",
543 ret);
544 return ret;
545 }
546
547 *reg_num = le32_to_cpu(desc.data[0]);
548 if (*reg_num == 0) {
549 dev_err(&hdev->pdev->dev,
550 "mac statistic reg number is invalid!\n");
551 return -ENODATA;
552 }
553
554 return 0;
555 }
556
hclge_mac_update_stats(struct hclge_dev * hdev)557 int hclge_mac_update_stats(struct hclge_dev *hdev)
558 {
559 /* The firmware supports the new statistics acquisition method */
560 if (hdev->ae_dev->dev_specs.mac_stats_num)
561 return hclge_mac_update_stats_complete(hdev);
562 else
563 return hclge_mac_update_stats_defective(hdev);
564 }
565
hclge_comm_get_count(struct hclge_dev * hdev,const struct hclge_comm_stats_str strs[],u32 size)566 static int hclge_comm_get_count(struct hclge_dev *hdev,
567 const struct hclge_comm_stats_str strs[],
568 u32 size)
569 {
570 int count = 0;
571 u32 i;
572
573 for (i = 0; i < size; i++)
574 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num)
575 count++;
576
577 return count;
578 }
579
hclge_comm_get_stats(struct hclge_dev * hdev,const struct hclge_comm_stats_str strs[],int size,u64 * data)580 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev,
581 const struct hclge_comm_stats_str strs[],
582 int size, u64 *data)
583 {
584 u64 *buf = data;
585 int i;
586
587 for (i = 0; i < size; i++) {
588 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
589 continue;
590
591 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset);
592 buf++;
593 }
594
595 return buf;
596 }
597
hclge_comm_get_strings(struct hclge_dev * hdev,u32 stringset,const struct hclge_comm_stats_str strs[],int size,u8 ** data)598 static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset,
599 const struct hclge_comm_stats_str strs[],
600 int size, u8 **data)
601 {
602 int i;
603
604 if (stringset != ETH_SS_STATS)
605 return;
606
607 for (i = 0; i < size; i++) {
608 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
609 continue;
610
611 ethtool_puts(data, strs[i].desc);
612 }
613 }
614
hclge_update_stats_for_all(struct hclge_dev * hdev)615 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
616 {
617 struct hnae3_handle *handle;
618 int status;
619
620 handle = &hdev->vport[0].nic;
621 if (handle->client) {
622 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
623 if (status) {
624 dev_err(&hdev->pdev->dev,
625 "Update TQPS stats fail, status = %d.\n",
626 status);
627 }
628 }
629
630 hclge_update_fec_stats(hdev);
631
632 status = hclge_mac_update_stats(hdev);
633 if (status)
634 dev_err(&hdev->pdev->dev,
635 "Update MAC stats fail, status = %d.\n", status);
636 }
637
hclge_update_stats(struct hnae3_handle * handle)638 static void hclge_update_stats(struct hnae3_handle *handle)
639 {
640 struct hclge_vport *vport = hclge_get_vport(handle);
641 struct hclge_dev *hdev = vport->back;
642 int status;
643
644 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
645 return;
646
647 status = hclge_mac_update_stats(hdev);
648 if (status)
649 dev_err(&hdev->pdev->dev,
650 "Update MAC stats fail, status = %d.\n",
651 status);
652
653 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
654 if (status)
655 dev_err(&hdev->pdev->dev,
656 "Update TQPS stats fail, status = %d.\n",
657 status);
658
659 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
660 }
661
hclge_get_sset_count(struct hnae3_handle * handle,int stringset)662 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
663 {
664 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
665 HNAE3_SUPPORT_PHY_LOOPBACK | \
666 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
667 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \
668 HNAE3_SUPPORT_EXTERNAL_LOOPBACK)
669
670 struct hclge_vport *vport = hclge_get_vport(handle);
671 struct hclge_dev *hdev = vport->back;
672 int count = 0;
673
674 /* Loopback test support rules:
675 * mac: only GE mode support
676 * serdes: all mac mode will support include GE/XGE/LGE/CGE
677 * phy: only support when phy device exist on board
678 */
679 if (stringset == ETH_SS_TEST) {
680 /* clear loopback bit flags at first */
681 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
682 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
683 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
684 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
685 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
686 count += 1;
687 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
688 }
689
690 if (hdev->ae_dev->dev_specs.hilink_version !=
691 HCLGE_HILINK_H60) {
692 count += 1;
693 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
694 }
695
696 count += 1;
697 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
698 count += 1;
699 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK;
700
701 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
702 hdev->hw.mac.phydev->drv->set_loopback) ||
703 hnae3_dev_phy_imp_supported(hdev)) {
704 count += 1;
705 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
706 }
707 } else if (stringset == ETH_SS_STATS) {
708 count = hclge_comm_get_count(hdev, g_mac_stats_string,
709 ARRAY_SIZE(g_mac_stats_string)) +
710 hclge_comm_tqps_get_sset_count(handle);
711 }
712
713 return count;
714 }
715
hclge_get_strings(struct hnae3_handle * handle,u32 stringset,u8 ** data)716 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
717 u8 **data)
718 {
719 struct hclge_vport *vport = hclge_get_vport(handle);
720 struct hclge_dev *hdev = vport->back;
721 const char *str;
722 int size;
723
724 if (stringset == ETH_SS_STATS) {
725 size = ARRAY_SIZE(g_mac_stats_string);
726 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string,
727 size, data);
728 hclge_comm_tqps_get_strings(handle, data);
729 } else if (stringset == ETH_SS_TEST) {
730 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) {
731 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL];
732 ethtool_puts(data, str);
733 }
734 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
735 str = hns3_nic_test_strs[HNAE3_LOOP_APP];
736 ethtool_puts(data, str);
737 }
738 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
739 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES];
740 ethtool_puts(data, str);
741 }
742 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
743 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES];
744 ethtool_puts(data, str);
745 }
746 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
747 str = hns3_nic_test_strs[HNAE3_LOOP_PHY];
748 ethtool_puts(data, str);
749 }
750 }
751 }
752
hclge_get_stats(struct hnae3_handle * handle,u64 * data)753 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
754 {
755 struct hclge_vport *vport = hclge_get_vport(handle);
756 struct hclge_dev *hdev = vport->back;
757 u64 *p;
758
759 p = hclge_comm_get_stats(hdev, g_mac_stats_string,
760 ARRAY_SIZE(g_mac_stats_string), data);
761 p = hclge_comm_tqps_get_stats(handle, p);
762 }
763
hclge_get_mac_stat(struct hnae3_handle * handle,struct hns3_mac_stats * mac_stats)764 static void hclge_get_mac_stat(struct hnae3_handle *handle,
765 struct hns3_mac_stats *mac_stats)
766 {
767 struct hclge_vport *vport = hclge_get_vport(handle);
768 struct hclge_dev *hdev = vport->back;
769
770 hclge_update_stats(handle);
771
772 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num;
773 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num;
774 }
775
hclge_parse_func_status(struct hclge_dev * hdev,struct hclge_func_status_cmd * status)776 static int hclge_parse_func_status(struct hclge_dev *hdev,
777 struct hclge_func_status_cmd *status)
778 {
779 #define HCLGE_MAC_ID_MASK 0xF
780
781 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
782 return -EINVAL;
783
784 /* Set the pf to main pf */
785 if (status->pf_state & HCLGE_PF_STATE_MAIN)
786 hdev->flag |= HCLGE_FLAG_MAIN;
787 else
788 hdev->flag &= ~HCLGE_FLAG_MAIN;
789
790 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK;
791 return 0;
792 }
793
hclge_query_function_status(struct hclge_dev * hdev)794 static int hclge_query_function_status(struct hclge_dev *hdev)
795 {
796 #define HCLGE_QUERY_MAX_CNT 5
797
798 struct hclge_func_status_cmd *req;
799 struct hclge_desc desc;
800 int timeout = 0;
801 int ret;
802
803 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
804 req = (struct hclge_func_status_cmd *)desc.data;
805
806 do {
807 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
808 if (ret) {
809 dev_err(&hdev->pdev->dev,
810 "query function status failed %d.\n", ret);
811 return ret;
812 }
813
814 /* Check pf reset is done */
815 if (req->pf_state)
816 break;
817 usleep_range(1000, 2000);
818 } while (timeout++ < HCLGE_QUERY_MAX_CNT);
819
820 return hclge_parse_func_status(hdev, req);
821 }
822
hclge_query_pf_resource(struct hclge_dev * hdev)823 static int hclge_query_pf_resource(struct hclge_dev *hdev)
824 {
825 struct hclge_pf_res_cmd *req;
826 struct hclge_desc desc;
827 int ret;
828
829 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
830 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
831 if (ret) {
832 dev_err(&hdev->pdev->dev,
833 "query pf resource failed %d.\n", ret);
834 return ret;
835 }
836
837 req = (struct hclge_pf_res_cmd *)desc.data;
838 hdev->num_tqps = le16_to_cpu(req->tqp_num) +
839 le16_to_cpu(req->ext_tqp_num);
840 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
841
842 if (req->tx_buf_size)
843 hdev->tx_buf_size =
844 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
845 else
846 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
847
848 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
849
850 if (req->dv_buf_size)
851 hdev->dv_buf_size =
852 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
853 else
854 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
855
856 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
857
858 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic);
859 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
860 dev_err(&hdev->pdev->dev,
861 "only %u msi resources available, not enough for pf(min:2).\n",
862 hdev->num_nic_msi);
863 return -EINVAL;
864 }
865
866 if (hnae3_dev_roce_supported(hdev)) {
867 hdev->num_roce_msi =
868 le16_to_cpu(req->pf_intr_vector_number_roce);
869
870 /* PF should have NIC vectors and Roce vectors,
871 * NIC vectors are queued before Roce vectors.
872 */
873 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
874 } else {
875 hdev->num_msi = hdev->num_nic_msi;
876 }
877
878 return 0;
879 }
880
hclge_parse_speed(u8 speed_cmd,u32 * speed)881 static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
882 {
883 switch (speed_cmd) {
884 case HCLGE_FW_MAC_SPEED_10M:
885 *speed = HCLGE_MAC_SPEED_10M;
886 break;
887 case HCLGE_FW_MAC_SPEED_100M:
888 *speed = HCLGE_MAC_SPEED_100M;
889 break;
890 case HCLGE_FW_MAC_SPEED_1G:
891 *speed = HCLGE_MAC_SPEED_1G;
892 break;
893 case HCLGE_FW_MAC_SPEED_10G:
894 *speed = HCLGE_MAC_SPEED_10G;
895 break;
896 case HCLGE_FW_MAC_SPEED_25G:
897 *speed = HCLGE_MAC_SPEED_25G;
898 break;
899 case HCLGE_FW_MAC_SPEED_40G:
900 *speed = HCLGE_MAC_SPEED_40G;
901 break;
902 case HCLGE_FW_MAC_SPEED_50G:
903 *speed = HCLGE_MAC_SPEED_50G;
904 break;
905 case HCLGE_FW_MAC_SPEED_100G:
906 *speed = HCLGE_MAC_SPEED_100G;
907 break;
908 case HCLGE_FW_MAC_SPEED_200G:
909 *speed = HCLGE_MAC_SPEED_200G;
910 break;
911 default:
912 return -EINVAL;
913 }
914
915 return 0;
916 }
917
918 static const struct hclge_speed_bit_map speed_bit_map[] = {
919 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT},
920 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT},
921 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT},
922 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
923 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
924 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
925 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},
926 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},
927 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS},
928 };
929
hclge_get_speed_bit(u32 speed,u32 * speed_bit)930 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
931 {
932 u16 i;
933
934 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) {
935 if (speed == speed_bit_map[i].speed) {
936 *speed_bit = speed_bit_map[i].speed_bit;
937 return 0;
938 }
939 }
940
941 return -EINVAL;
942 }
943
hclge_check_port_speed(struct hnae3_handle * handle,u32 speed)944 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
945 {
946 struct hclge_vport *vport = hclge_get_vport(handle);
947 struct hclge_dev *hdev = vport->back;
948 u32 speed_ability = hdev->hw.mac.speed_ability;
949 u32 speed_bit = 0;
950 int ret;
951
952 ret = hclge_get_speed_bit(speed, &speed_bit);
953 if (ret)
954 return ret;
955
956 if (speed_bit & speed_ability)
957 return 0;
958
959 return -EINVAL;
960 }
961
hclge_update_fec_support(struct hclge_mac * mac)962 static void hclge_update_fec_support(struct hclge_mac *mac)
963 {
964 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
965 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
966 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported);
967 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
968
969 if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
970 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
971 mac->supported);
972 if (mac->fec_ability & BIT(HNAE3_FEC_RS))
973 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
974 mac->supported);
975 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS))
976 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
977 mac->supported);
978 if (mac->fec_ability & BIT(HNAE3_FEC_NONE))
979 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
980 mac->supported);
981 }
982
983 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = {
984 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},
985 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},
986 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
987 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT},
988 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},
989 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},
990 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},
991 {HCLGE_SUPPORT_200G_R4_EXT_BIT,
992 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},
993 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},
994 };
995
996 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = {
997 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},
998 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},
999 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT},
1000 {HCLGE_SUPPORT_100G_R4_BIT,
1001 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},
1002 {HCLGE_SUPPORT_100G_R2_BIT,
1003 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},
1004 {HCLGE_SUPPORT_200G_R4_EXT_BIT,
1005 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},
1006 {HCLGE_SUPPORT_200G_R4_BIT,
1007 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},
1008 };
1009
1010 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = {
1011 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},
1012 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},
1013 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
1014 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT},
1015 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},
1016 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},
1017 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},
1018 {HCLGE_SUPPORT_200G_R4_EXT_BIT,
1019 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},
1020 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},
1021 };
1022
1023 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = {
1024 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
1025 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
1026 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
1027 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT},
1028 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},
1029 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},
1030 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},
1031 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},
1032 {HCLGE_SUPPORT_200G_R4_EXT_BIT,
1033 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},
1034 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},
1035 };
1036
hclge_convert_setting_sr(u16 speed_ability,unsigned long * link_mode)1037 static void hclge_convert_setting_sr(u16 speed_ability,
1038 unsigned long *link_mode)
1039 {
1040 int i;
1041
1042 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) {
1043 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit)
1044 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode,
1045 link_mode);
1046 }
1047 }
1048
hclge_convert_setting_lr(u16 speed_ability,unsigned long * link_mode)1049 static void hclge_convert_setting_lr(u16 speed_ability,
1050 unsigned long *link_mode)
1051 {
1052 int i;
1053
1054 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) {
1055 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit)
1056 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode,
1057 link_mode);
1058 }
1059 }
1060
hclge_convert_setting_cr(u16 speed_ability,unsigned long * link_mode)1061 static void hclge_convert_setting_cr(u16 speed_ability,
1062 unsigned long *link_mode)
1063 {
1064 int i;
1065
1066 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) {
1067 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit)
1068 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode,
1069 link_mode);
1070 }
1071 }
1072
hclge_convert_setting_kr(u16 speed_ability,unsigned long * link_mode)1073 static void hclge_convert_setting_kr(u16 speed_ability,
1074 unsigned long *link_mode)
1075 {
1076 int i;
1077
1078 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) {
1079 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit)
1080 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode,
1081 link_mode);
1082 }
1083 }
1084
hclge_convert_setting_fec(struct hclge_mac * mac)1085 static void hclge_convert_setting_fec(struct hclge_mac *mac)
1086 {
1087 /* If firmware has reported fec_ability, don't need to convert by speed */
1088 if (mac->fec_ability)
1089 goto out;
1090
1091 switch (mac->speed) {
1092 case HCLGE_MAC_SPEED_10G:
1093 case HCLGE_MAC_SPEED_40G:
1094 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) |
1095 BIT(HNAE3_FEC_NONE);
1096 break;
1097 case HCLGE_MAC_SPEED_25G:
1098 case HCLGE_MAC_SPEED_50G:
1099 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
1100 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE);
1101 break;
1102 case HCLGE_MAC_SPEED_100G:
1103 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1104 BIT(HNAE3_FEC_NONE);
1105 break;
1106 case HCLGE_MAC_SPEED_200G:
1107 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1108 BIT(HNAE3_FEC_LLRS);
1109 break;
1110 default:
1111 mac->fec_ability = 0;
1112 break;
1113 }
1114
1115 out:
1116 hclge_update_fec_support(mac);
1117 }
1118
hclge_parse_fiber_link_mode(struct hclge_dev * hdev,u16 speed_ability)1119 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
1120 u16 speed_ability)
1121 {
1122 struct hclge_mac *mac = &hdev->hw.mac;
1123
1124 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1125 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1126 mac->supported);
1127
1128 hclge_convert_setting_sr(speed_ability, mac->supported);
1129 hclge_convert_setting_lr(speed_ability, mac->supported);
1130 hclge_convert_setting_cr(speed_ability, mac->supported);
1131 if (hnae3_dev_fec_supported(hdev))
1132 hclge_convert_setting_fec(mac);
1133
1134 if (hnae3_dev_pause_supported(hdev))
1135 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1136
1137 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
1138 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1139 }
1140
hclge_parse_backplane_link_mode(struct hclge_dev * hdev,u16 speed_ability)1141 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
1142 u16 speed_ability)
1143 {
1144 struct hclge_mac *mac = &hdev->hw.mac;
1145
1146 hclge_convert_setting_kr(speed_ability, mac->supported);
1147 if (hnae3_dev_fec_supported(hdev))
1148 hclge_convert_setting_fec(mac);
1149
1150 if (hnae3_dev_pause_supported(hdev))
1151 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1152
1153 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported);
1154 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1155 }
1156
hclge_parse_copper_link_mode(struct hclge_dev * hdev,u16 speed_ability)1157 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
1158 u16 speed_ability)
1159 {
1160 unsigned long *supported = hdev->hw.mac.supported;
1161
1162 /* default to support all speed for GE port */
1163 if (!speed_ability)
1164 speed_ability = HCLGE_SUPPORT_GE;
1165
1166 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1167 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1168 supported);
1169
1170 if (speed_ability & HCLGE_SUPPORT_100M_BIT) {
1171 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1172 supported);
1173 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1174 supported);
1175 }
1176
1177 if (speed_ability & HCLGE_SUPPORT_10M_BIT) {
1178 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
1179 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
1180 }
1181
1182 if (hnae3_dev_pause_supported(hdev)) {
1183 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1184 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
1185 }
1186
1187 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
1188 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
1189 }
1190
hclge_parse_link_mode(struct hclge_dev * hdev,u16 speed_ability)1191 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability)
1192 {
1193 u8 media_type = hdev->hw.mac.media_type;
1194
1195 if (media_type == HNAE3_MEDIA_TYPE_FIBER)
1196 hclge_parse_fiber_link_mode(hdev, speed_ability);
1197 else if (media_type == HNAE3_MEDIA_TYPE_COPPER)
1198 hclge_parse_copper_link_mode(hdev, speed_ability);
1199 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE)
1200 hclge_parse_backplane_link_mode(hdev, speed_ability);
1201 }
1202
hclge_get_max_speed(u16 speed_ability)1203 static u32 hclge_get_max_speed(u16 speed_ability)
1204 {
1205 if (speed_ability & HCLGE_SUPPORT_200G_BITS)
1206 return HCLGE_MAC_SPEED_200G;
1207
1208 if (speed_ability & HCLGE_SUPPORT_100G_BITS)
1209 return HCLGE_MAC_SPEED_100G;
1210
1211 if (speed_ability & HCLGE_SUPPORT_50G_BITS)
1212 return HCLGE_MAC_SPEED_50G;
1213
1214 if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1215 return HCLGE_MAC_SPEED_40G;
1216
1217 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1218 return HCLGE_MAC_SPEED_25G;
1219
1220 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1221 return HCLGE_MAC_SPEED_10G;
1222
1223 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1224 return HCLGE_MAC_SPEED_1G;
1225
1226 if (speed_ability & HCLGE_SUPPORT_100M_BIT)
1227 return HCLGE_MAC_SPEED_100M;
1228
1229 if (speed_ability & HCLGE_SUPPORT_10M_BIT)
1230 return HCLGE_MAC_SPEED_10M;
1231
1232 return HCLGE_MAC_SPEED_1G;
1233 }
1234
hclge_parse_cfg(struct hclge_cfg * cfg,struct hclge_desc * desc)1235 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1236 {
1237 #define HCLGE_TX_SPARE_SIZE_UNIT 4096
1238 #define SPEED_ABILITY_EXT_SHIFT 8
1239
1240 struct hclge_cfg_param_cmd *req;
1241 u64 mac_addr_tmp_high;
1242 u16 speed_ability_ext;
1243 u64 mac_addr_tmp;
1244 unsigned int i;
1245
1246 req = (struct hclge_cfg_param_cmd *)desc[0].data;
1247
1248 /* get the configuration */
1249 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1250 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1251 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1252 HCLGE_CFG_TQP_DESC_N_M,
1253 HCLGE_CFG_TQP_DESC_N_S);
1254
1255 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1256 HCLGE_CFG_PHY_ADDR_M,
1257 HCLGE_CFG_PHY_ADDR_S);
1258 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1259 HCLGE_CFG_MEDIA_TP_M,
1260 HCLGE_CFG_MEDIA_TP_S);
1261 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1262 HCLGE_CFG_RX_BUF_LEN_M,
1263 HCLGE_CFG_RX_BUF_LEN_S);
1264 /* get mac_address */
1265 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1266 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1267 HCLGE_CFG_MAC_ADDR_H_M,
1268 HCLGE_CFG_MAC_ADDR_H_S);
1269
1270 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1271
1272 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1273 HCLGE_CFG_DEFAULT_SPEED_M,
1274 HCLGE_CFG_DEFAULT_SPEED_S);
1275 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1276 HCLGE_CFG_RSS_SIZE_M,
1277 HCLGE_CFG_RSS_SIZE_S);
1278
1279 for (i = 0; i < ETH_ALEN; i++)
1280 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1281
1282 req = (struct hclge_cfg_param_cmd *)desc[1].data;
1283 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1284
1285 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1286 HCLGE_CFG_SPEED_ABILITY_M,
1287 HCLGE_CFG_SPEED_ABILITY_S);
1288 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]),
1289 HCLGE_CFG_SPEED_ABILITY_EXT_M,
1290 HCLGE_CFG_SPEED_ABILITY_EXT_S);
1291 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT;
1292
1293 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]),
1294 HCLGE_CFG_VLAN_FLTR_CAP_M,
1295 HCLGE_CFG_VLAN_FLTR_CAP_S);
1296
1297 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
1298 HCLGE_CFG_UMV_TBL_SPACE_M,
1299 HCLGE_CFG_UMV_TBL_SPACE_S);
1300
1301 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]),
1302 HCLGE_CFG_PF_RSS_SIZE_M,
1303 HCLGE_CFG_PF_RSS_SIZE_S);
1304
1305 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a
1306 * power of 2, instead of reading out directly. This would
1307 * be more flexible for future changes and expansions.
1308 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S,
1309 * it does not make sense if PF's field is 0. In this case, PF and VF
1310 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S.
1311 */
1312 cfg->pf_rss_size_max = cfg->pf_rss_size_max ?
1313 1U << cfg->pf_rss_size_max :
1314 cfg->vf_rss_size_max;
1315
1316 /* The unit of the tx spare buffer size queried from configuration
1317 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
1318 * needed here.
1319 */
1320 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
1321 HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
1322 HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
1323 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
1324 }
1325
1326 /* hclge_get_cfg: query the static parameter from flash
1327 * @hdev: pointer to struct hclge_dev
1328 * @hcfg: the config structure to be getted
1329 */
hclge_get_cfg(struct hclge_dev * hdev,struct hclge_cfg * hcfg)1330 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1331 {
1332 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1333 struct hclge_cfg_param_cmd *req;
1334 unsigned int i;
1335 int ret;
1336
1337 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1338 u32 offset = 0;
1339
1340 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1341 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1342 true);
1343 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1344 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1345 /* Len should be united by 4 bytes when send to hardware */
1346 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1347 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1348 req->offset = cpu_to_le32(offset);
1349 }
1350
1351 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1352 if (ret) {
1353 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1354 return ret;
1355 }
1356
1357 hclge_parse_cfg(hcfg, desc);
1358
1359 return 0;
1360 }
1361
hclge_set_default_dev_specs(struct hclge_dev * hdev)1362 static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
1363 {
1364 #define HCLGE_MAX_NON_TSO_BD_NUM 8U
1365
1366 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1367
1368 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1369 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1370 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1371 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
1372 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
1373 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME;
1374 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM;
1375 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1376 ae_dev->dev_specs.tnl_num = 0;
1377 }
1378
hclge_parse_dev_specs(struct hclge_dev * hdev,struct hclge_desc * desc)1379 static void hclge_parse_dev_specs(struct hclge_dev *hdev,
1380 struct hclge_desc *desc)
1381 {
1382 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1383 struct hclge_dev_specs_0_cmd *req0;
1384 struct hclge_dev_specs_1_cmd *req1;
1385
1386 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
1387 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
1388
1389 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
1390 ae_dev->dev_specs.rss_ind_tbl_size =
1391 le16_to_cpu(req0->rss_ind_tbl_size);
1392 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
1393 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
1394 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
1395 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num);
1396 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
1397 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
1398 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size);
1399 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size);
1400 ae_dev->dev_specs.tnl_num = req1->tnl_num;
1401 ae_dev->dev_specs.hilink_version = req1->hilink_version;
1402 }
1403
hclge_check_dev_specs(struct hclge_dev * hdev)1404 static void hclge_check_dev_specs(struct hclge_dev *hdev)
1405 {
1406 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
1407
1408 if (!dev_specs->max_non_tso_bd_num)
1409 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1410 if (!dev_specs->rss_ind_tbl_size)
1411 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1412 if (!dev_specs->rss_key_size)
1413 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1414 if (!dev_specs->max_tm_rate)
1415 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;
1416 if (!dev_specs->max_qset_num)
1417 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM;
1418 if (!dev_specs->max_int_gl)
1419 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL;
1420 if (!dev_specs->max_frm_size)
1421 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME;
1422 if (!dev_specs->umv_size)
1423 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1424 }
1425
hclge_query_mac_stats_num(struct hclge_dev * hdev)1426 static int hclge_query_mac_stats_num(struct hclge_dev *hdev)
1427 {
1428 u32 reg_num = 0;
1429 int ret;
1430
1431 ret = hclge_mac_query_reg_num(hdev, ®_num);
1432 if (ret && ret != -EOPNOTSUPP)
1433 return ret;
1434
1435 hdev->ae_dev->dev_specs.mac_stats_num = reg_num;
1436 return 0;
1437 }
1438
hclge_query_dev_specs(struct hclge_dev * hdev)1439 static int hclge_query_dev_specs(struct hclge_dev *hdev)
1440 {
1441 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
1442 int ret;
1443 int i;
1444
1445 ret = hclge_query_mac_stats_num(hdev);
1446 if (ret)
1447 return ret;
1448
1449 /* set default specifications as devices lower than version V3 do not
1450 * support querying specifications from firmware.
1451 */
1452 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
1453 hclge_set_default_dev_specs(hdev);
1454 return 0;
1455 }
1456
1457 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1458 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
1459 true);
1460 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1461 }
1462 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
1463
1464 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM);
1465 if (ret)
1466 return ret;
1467
1468 hclge_parse_dev_specs(hdev, desc);
1469 hclge_check_dev_specs(hdev);
1470
1471 return 0;
1472 }
1473
hclge_get_cap(struct hclge_dev * hdev)1474 static int hclge_get_cap(struct hclge_dev *hdev)
1475 {
1476 int ret;
1477
1478 ret = hclge_query_function_status(hdev);
1479 if (ret) {
1480 dev_err(&hdev->pdev->dev,
1481 "query function status error %d.\n", ret);
1482 return ret;
1483 }
1484
1485 /* get pf resource */
1486 return hclge_query_pf_resource(hdev);
1487 }
1488
hclge_init_kdump_kernel_config(struct hclge_dev * hdev)1489 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev)
1490 {
1491 #define HCLGE_MIN_TX_DESC 64
1492 #define HCLGE_MIN_RX_DESC 64
1493
1494 if (!is_kdump_kernel())
1495 return;
1496
1497 dev_info(&hdev->pdev->dev,
1498 "Running kdump kernel. Using minimal resources\n");
1499
1500 /* minimal queue pairs equals to the number of vports */
1501 hdev->num_tqps = hdev->num_req_vfs + 1;
1502 hdev->num_tx_desc = HCLGE_MIN_TX_DESC;
1503 hdev->num_rx_desc = HCLGE_MIN_RX_DESC;
1504 }
1505
hclge_init_tc_config(struct hclge_dev * hdev)1506 static void hclge_init_tc_config(struct hclge_dev *hdev)
1507 {
1508 unsigned int i;
1509
1510 if (hdev->tc_max > HNAE3_MAX_TC ||
1511 hdev->tc_max < 1) {
1512 dev_warn(&hdev->pdev->dev, "TC num = %u.\n",
1513 hdev->tc_max);
1514 hdev->tc_max = 1;
1515 }
1516
1517 /* Dev does not support DCB */
1518 if (!hnae3_dev_dcb_supported(hdev)) {
1519 hdev->tc_max = 1;
1520 hdev->pfc_max = 0;
1521 } else {
1522 hdev->pfc_max = hdev->tc_max;
1523 }
1524
1525 hdev->tm_info.num_tc = 1;
1526
1527 /* Currently not support uncontiuous tc */
1528 for (i = 0; i < hdev->tm_info.num_tc; i++)
1529 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1530
1531 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1532 }
1533
hclge_configure(struct hclge_dev * hdev)1534 static int hclge_configure(struct hclge_dev *hdev)
1535 {
1536 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1537 struct hclge_cfg cfg;
1538 int ret;
1539
1540 ret = hclge_get_cfg(hdev, &cfg);
1541 if (ret)
1542 return ret;
1543
1544 hdev->base_tqp_pid = 0;
1545 hdev->vf_rss_size_max = cfg.vf_rss_size_max;
1546 hdev->pf_rss_size_max = cfg.pf_rss_size_max;
1547 hdev->rx_buf_len = cfg.rx_buf_len;
1548 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1549 hdev->hw.mac.media_type = cfg.media_type;
1550 hdev->hw.mac.phy_addr = cfg.phy_addr;
1551 hdev->num_tx_desc = cfg.tqp_desc_num;
1552 hdev->num_rx_desc = cfg.tqp_desc_num;
1553 hdev->tm_info.num_pg = 1;
1554 hdev->tc_max = cfg.tc_num;
1555 hdev->tm_info.hw_pfc_map = 0;
1556 if (cfg.umv_space)
1557 hdev->wanted_umv_size = cfg.umv_space;
1558 else
1559 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size;
1560 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
1561 hdev->gro_en = true;
1562 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
1563 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
1564
1565 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
1566 hdev->fd_en = true;
1567 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
1568 }
1569
1570 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1571 if (ret) {
1572 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n",
1573 cfg.default_speed, ret);
1574 return ret;
1575 }
1576 hdev->hw.mac.req_speed = hdev->hw.mac.speed;
1577 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE;
1578 hdev->hw.mac.req_duplex = DUPLEX_FULL;
1579
1580 hclge_parse_link_mode(hdev, cfg.speed_ability);
1581
1582 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability);
1583
1584 hclge_init_tc_config(hdev);
1585 hclge_init_kdump_kernel_config(hdev);
1586
1587 return ret;
1588 }
1589
hclge_config_tso(struct hclge_dev * hdev,u16 tso_mss_min,u16 tso_mss_max)1590 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
1591 u16 tso_mss_max)
1592 {
1593 struct hclge_cfg_tso_status_cmd *req;
1594 struct hclge_desc desc;
1595
1596 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1597
1598 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1599 req->tso_mss_min = cpu_to_le16(tso_mss_min);
1600 req->tso_mss_max = cpu_to_le16(tso_mss_max);
1601
1602 return hclge_cmd_send(&hdev->hw, &desc, 1);
1603 }
1604
hclge_config_gro(struct hclge_dev * hdev)1605 static int hclge_config_gro(struct hclge_dev *hdev)
1606 {
1607 struct hclge_cfg_gro_status_cmd *req;
1608 struct hclge_desc desc;
1609 int ret;
1610
1611 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))
1612 return 0;
1613
1614 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1615 req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1616
1617 req->gro_en = hdev->gro_en ? 1 : 0;
1618
1619 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1620 if (ret)
1621 dev_err(&hdev->pdev->dev,
1622 "GRO hardware config cmd failed, ret = %d\n", ret);
1623
1624 return ret;
1625 }
1626
hclge_alloc_tqps(struct hclge_dev * hdev)1627 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1628 {
1629 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1630 struct hclge_comm_tqp *tqp;
1631 int i;
1632
1633 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1634 sizeof(struct hclge_comm_tqp), GFP_KERNEL);
1635 if (!hdev->htqp)
1636 return -ENOMEM;
1637
1638 tqp = hdev->htqp;
1639
1640 for (i = 0; i < hdev->num_tqps; i++) {
1641 tqp->dev = &hdev->pdev->dev;
1642 tqp->index = i;
1643
1644 tqp->q.ae_algo = &ae_algo;
1645 tqp->q.buf_size = hdev->rx_buf_len;
1646 tqp->q.tx_desc_num = hdev->num_tx_desc;
1647 tqp->q.rx_desc_num = hdev->num_rx_desc;
1648
1649 /* need an extended offset to configure queues >=
1650 * HCLGE_TQP_MAX_SIZE_DEV_V2
1651 */
1652 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
1653 tqp->q.io_base = hdev->hw.hw.io_base +
1654 HCLGE_TQP_REG_OFFSET +
1655 i * HCLGE_TQP_REG_SIZE;
1656 else
1657 tqp->q.io_base = hdev->hw.hw.io_base +
1658 HCLGE_TQP_REG_OFFSET +
1659 HCLGE_TQP_EXT_REG_OFFSET +
1660 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
1661 HCLGE_TQP_REG_SIZE;
1662
1663 /* when device supports tx push and has device memory,
1664 * the queue can execute push mode or doorbell mode on
1665 * device memory.
1666 */
1667 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
1668 tqp->q.mem_base = hdev->hw.hw.mem_base +
1669 HCLGE_TQP_MEM_OFFSET(hdev, i);
1670
1671 tqp++;
1672 }
1673
1674 return 0;
1675 }
1676
hclge_map_tqps_to_func(struct hclge_dev * hdev,u16 func_id,u16 tqp_pid,u16 tqp_vid,bool is_pf)1677 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1678 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1679 {
1680 struct hclge_tqp_map_cmd *req;
1681 struct hclge_desc desc;
1682 int ret;
1683
1684 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1685
1686 req = (struct hclge_tqp_map_cmd *)desc.data;
1687 req->tqp_id = cpu_to_le16(tqp_pid);
1688 req->tqp_vf = func_id;
1689 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B;
1690 if (!is_pf)
1691 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B;
1692 req->tqp_vid = cpu_to_le16(tqp_vid);
1693
1694 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1695 if (ret)
1696 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1697
1698 return ret;
1699 }
1700
hclge_assign_tqp(struct hclge_vport * vport,u16 num_tqps)1701 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1702 {
1703 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1704 struct hclge_dev *hdev = vport->back;
1705 int i, alloced;
1706
1707 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1708 alloced < num_tqps; i++) {
1709 if (!hdev->htqp[i].alloced) {
1710 hdev->htqp[i].q.handle = &vport->nic;
1711 hdev->htqp[i].q.tqp_index = alloced;
1712 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc;
1713 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc;
1714 kinfo->tqp[alloced] = &hdev->htqp[i].q;
1715 hdev->htqp[i].alloced = true;
1716 alloced++;
1717 }
1718 }
1719 vport->alloc_tqps = alloced;
1720 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max,
1721 vport->alloc_tqps / hdev->tm_info.num_tc);
1722
1723 /* ensure one to one mapping between irq and queue at default */
1724 kinfo->rss_size = min_t(u16, kinfo->rss_size,
1725 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1726
1727 return 0;
1728 }
1729
hclge_knic_setup(struct hclge_vport * vport,u16 num_tqps,u16 num_tx_desc,u16 num_rx_desc)1730 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
1731 u16 num_tx_desc, u16 num_rx_desc)
1732
1733 {
1734 struct hnae3_handle *nic = &vport->nic;
1735 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1736 struct hclge_dev *hdev = vport->back;
1737 int ret;
1738
1739 kinfo->num_tx_desc = num_tx_desc;
1740 kinfo->num_rx_desc = num_rx_desc;
1741
1742 kinfo->rx_buf_len = hdev->rx_buf_len;
1743 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
1744
1745 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1746 sizeof(struct hnae3_queue *), GFP_KERNEL);
1747 if (!kinfo->tqp)
1748 return -ENOMEM;
1749
1750 ret = hclge_assign_tqp(vport, num_tqps);
1751 if (ret)
1752 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1753
1754 return ret;
1755 }
1756
hclge_map_tqp_to_vport(struct hclge_dev * hdev,struct hclge_vport * vport)1757 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1758 struct hclge_vport *vport)
1759 {
1760 struct hnae3_handle *nic = &vport->nic;
1761 struct hnae3_knic_private_info *kinfo;
1762 u16 i;
1763
1764 kinfo = &nic->kinfo;
1765 for (i = 0; i < vport->alloc_tqps; i++) {
1766 struct hclge_comm_tqp *q =
1767 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q);
1768 bool is_pf;
1769 int ret;
1770
1771 is_pf = !(vport->vport_id);
1772 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1773 i, is_pf);
1774 if (ret)
1775 return ret;
1776 }
1777
1778 return 0;
1779 }
1780
hclge_map_tqp(struct hclge_dev * hdev)1781 static int hclge_map_tqp(struct hclge_dev *hdev)
1782 {
1783 struct hclge_vport *vport = hdev->vport;
1784 u16 i, num_vport;
1785
1786 num_vport = hdev->num_req_vfs + 1;
1787 for (i = 0; i < num_vport; i++) {
1788 int ret;
1789
1790 ret = hclge_map_tqp_to_vport(hdev, vport);
1791 if (ret)
1792 return ret;
1793
1794 vport++;
1795 }
1796
1797 return 0;
1798 }
1799
hclge_vport_setup(struct hclge_vport * vport,u16 num_tqps)1800 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1801 {
1802 struct hnae3_handle *nic = &vport->nic;
1803 struct hclge_dev *hdev = vport->back;
1804 int ret;
1805
1806 nic->pdev = hdev->pdev;
1807 nic->ae_algo = &ae_algo;
1808 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits,
1809 MAX_NUMNODES);
1810 nic->kinfo.io_base = hdev->hw.hw.io_base;
1811
1812 ret = hclge_knic_setup(vport, num_tqps,
1813 hdev->num_tx_desc, hdev->num_rx_desc);
1814 if (ret)
1815 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret);
1816
1817 return ret;
1818 }
1819
hclge_alloc_vport(struct hclge_dev * hdev)1820 static int hclge_alloc_vport(struct hclge_dev *hdev)
1821 {
1822 struct pci_dev *pdev = hdev->pdev;
1823 struct hclge_vport *vport;
1824 u32 tqp_main_vport;
1825 u32 tqp_per_vport;
1826 int num_vport, i;
1827 int ret;
1828
1829 /* We need to alloc a vport for main NIC of PF */
1830 num_vport = hdev->num_req_vfs + 1;
1831
1832 if (hdev->num_tqps < num_vport) {
1833 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
1834 hdev->num_tqps, num_vport);
1835 return -EINVAL;
1836 }
1837
1838 /* Alloc the same number of TQPs for every vport */
1839 tqp_per_vport = hdev->num_tqps / num_vport;
1840 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1841
1842 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1843 GFP_KERNEL);
1844 if (!vport)
1845 return -ENOMEM;
1846
1847 hdev->vport = vport;
1848 hdev->num_alloc_vport = num_vport;
1849
1850 if (IS_ENABLED(CONFIG_PCI_IOV))
1851 hdev->num_alloc_vfs = hdev->num_req_vfs;
1852
1853 for (i = 0; i < num_vport; i++) {
1854 vport->back = hdev;
1855 vport->vport_id = i;
1856 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO;
1857 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1858 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE;
1859 vport->port_base_vlan_cfg.tbl_sta = true;
1860 vport->rxvlan_cfg.rx_vlan_offload_en = true;
1861 vport->req_vlan_fltr_en = true;
1862 INIT_LIST_HEAD(&vport->vlan_list);
1863 INIT_LIST_HEAD(&vport->uc_mac_list);
1864 INIT_LIST_HEAD(&vport->mc_mac_list);
1865 spin_lock_init(&vport->mac_list_lock);
1866
1867 if (i == 0)
1868 ret = hclge_vport_setup(vport, tqp_main_vport);
1869 else
1870 ret = hclge_vport_setup(vport, tqp_per_vport);
1871 if (ret) {
1872 dev_err(&pdev->dev,
1873 "vport setup failed for vport %d, %d\n",
1874 i, ret);
1875 return ret;
1876 }
1877
1878 vport++;
1879 }
1880
1881 return 0;
1882 }
1883
hclge_cmd_alloc_tx_buff(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)1884 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1885 struct hclge_pkt_buf_alloc *buf_alloc)
1886 {
1887 /* TX buffer size is unit by 128 byte */
1888 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1889 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1890 struct hclge_tx_buff_alloc_cmd *req;
1891 struct hclge_desc desc;
1892 int ret;
1893 u8 i;
1894
1895 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1896
1897 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1898 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1899 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1900
1901 req->tx_pkt_buff[i] =
1902 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1903 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1904 }
1905
1906 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1907 if (ret)
1908 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1909 ret);
1910
1911 return ret;
1912 }
1913
hclge_tx_buffer_alloc(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)1914 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1915 struct hclge_pkt_buf_alloc *buf_alloc)
1916 {
1917 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1918
1919 if (ret)
1920 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1921
1922 return ret;
1923 }
1924
hclge_get_tc_num(struct hclge_dev * hdev)1925 static u32 hclge_get_tc_num(struct hclge_dev *hdev)
1926 {
1927 unsigned int i;
1928 u32 cnt = 0;
1929
1930 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1931 if (hdev->hw_tc_map & BIT(i))
1932 cnt++;
1933 return cnt;
1934 }
1935
1936 /* Get the number of pfc enabled TCs, which have private buffer */
hclge_get_pfc_priv_num(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)1937 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1938 struct hclge_pkt_buf_alloc *buf_alloc)
1939 {
1940 struct hclge_priv_buf *priv;
1941 unsigned int i;
1942 int cnt = 0;
1943
1944 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1945 priv = &buf_alloc->priv_buf[i];
1946 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1947 priv->enable)
1948 cnt++;
1949 }
1950
1951 return cnt;
1952 }
1953
1954 /* Get the number of pfc disabled TCs, which have private buffer */
hclge_get_no_pfc_priv_num(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)1955 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1956 struct hclge_pkt_buf_alloc *buf_alloc)
1957 {
1958 struct hclge_priv_buf *priv;
1959 unsigned int i;
1960 int cnt = 0;
1961
1962 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1963 priv = &buf_alloc->priv_buf[i];
1964 if (hdev->hw_tc_map & BIT(i) &&
1965 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1966 priv->enable)
1967 cnt++;
1968 }
1969
1970 return cnt;
1971 }
1972
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc * buf_alloc)1973 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1974 {
1975 struct hclge_priv_buf *priv;
1976 u32 rx_priv = 0;
1977 int i;
1978
1979 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1980 priv = &buf_alloc->priv_buf[i];
1981 if (priv->enable)
1982 rx_priv += priv->buf_size;
1983 }
1984 return rx_priv;
1985 }
1986
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc * buf_alloc)1987 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1988 {
1989 u32 i, total_tx_size = 0;
1990
1991 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1992 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1993
1994 return total_tx_size;
1995 }
1996
hclge_is_rx_buf_ok(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc,u32 rx_all)1997 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1998 struct hclge_pkt_buf_alloc *buf_alloc,
1999 u32 rx_all)
2000 {
2001 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2002 u32 tc_num = hclge_get_tc_num(hdev);
2003 u32 shared_buf, aligned_mps;
2004 u32 rx_priv;
2005 int i;
2006
2007 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2008
2009 if (hnae3_dev_dcb_supported(hdev))
2010 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps +
2011 hdev->dv_buf_size;
2012 else
2013 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
2014 + hdev->dv_buf_size;
2015
2016 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2017 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
2018 HCLGE_BUF_SIZE_UNIT);
2019
2020 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
2021 if (rx_all < rx_priv + shared_std)
2022 return false;
2023
2024 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
2025 buf_alloc->s_buf.buf_size = shared_buf;
2026 if (hnae3_dev_dcb_supported(hdev)) {
2027 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
2028 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2029 - roundup(aligned_mps / HCLGE_BUF_DIV_BY,
2030 HCLGE_BUF_SIZE_UNIT);
2031 } else {
2032 buf_alloc->s_buf.self.high = aligned_mps +
2033 HCLGE_NON_DCB_ADDITIONAL_BUF;
2034 buf_alloc->s_buf.self.low = aligned_mps;
2035 }
2036
2037 if (hnae3_dev_dcb_supported(hdev)) {
2038 hi_thrd = shared_buf - hdev->dv_buf_size;
2039
2040 if (tc_num <= NEED_RESERVE_TC_NUM)
2041 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2042 / BUF_MAX_PERCENT;
2043
2044 if (tc_num)
2045 hi_thrd = hi_thrd / tc_num;
2046
2047 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps);
2048 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT);
2049 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY;
2050 } else {
2051 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF;
2052 lo_thrd = aligned_mps;
2053 }
2054
2055 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2056 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2057 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2058 }
2059
2060 return true;
2061 }
2062
hclge_tx_buffer_calc(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2063 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
2064 struct hclge_pkt_buf_alloc *buf_alloc)
2065 {
2066 u32 i, total_size;
2067
2068 total_size = hdev->pkt_buf_size;
2069
2070 /* alloc tx buffer for all enabled tc */
2071 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2072 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2073
2074 if (hdev->hw_tc_map & BIT(i)) {
2075 if (total_size < hdev->tx_buf_size)
2076 return -ENOMEM;
2077
2078 priv->tx_buf_size = hdev->tx_buf_size;
2079 } else {
2080 priv->tx_buf_size = 0;
2081 }
2082
2083 total_size -= priv->tx_buf_size;
2084 }
2085
2086 return 0;
2087 }
2088
hclge_rx_buf_calc_all(struct hclge_dev * hdev,bool max,struct hclge_pkt_buf_alloc * buf_alloc)2089 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max,
2090 struct hclge_pkt_buf_alloc *buf_alloc)
2091 {
2092 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2093 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2094 unsigned int i;
2095
2096 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2097 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2098
2099 priv->enable = 0;
2100 priv->wl.low = 0;
2101 priv->wl.high = 0;
2102 priv->buf_size = 0;
2103
2104 if (!(hdev->hw_tc_map & BIT(i)))
2105 continue;
2106
2107 priv->enable = 1;
2108
2109 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
2110 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT;
2111 priv->wl.high = roundup(priv->wl.low + aligned_mps,
2112 HCLGE_BUF_SIZE_UNIT);
2113 } else {
2114 priv->wl.low = 0;
2115 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) :
2116 aligned_mps;
2117 }
2118
2119 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
2120 }
2121
2122 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2123 }
2124
hclge_drop_nopfc_buf_till_fit(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2125 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev,
2126 struct hclge_pkt_buf_alloc *buf_alloc)
2127 {
2128 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2129 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
2130 int i;
2131
2132 /* let the last to be cleared first */
2133 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2134 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2135 unsigned int mask = BIT((unsigned int)i);
2136
2137 if (hdev->hw_tc_map & mask &&
2138 !(hdev->tm_info.hw_pfc_map & mask)) {
2139 /* Clear the no pfc TC private buffer */
2140 priv->wl.low = 0;
2141 priv->wl.high = 0;
2142 priv->buf_size = 0;
2143 priv->enable = 0;
2144 no_pfc_priv_num--;
2145 }
2146
2147 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2148 no_pfc_priv_num == 0)
2149 break;
2150 }
2151
2152 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2153 }
2154
hclge_drop_pfc_buf_till_fit(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2155 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev,
2156 struct hclge_pkt_buf_alloc *buf_alloc)
2157 {
2158 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2159 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
2160 int i;
2161
2162 /* let the last to be cleared first */
2163 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2164 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2165 unsigned int mask = BIT((unsigned int)i);
2166
2167 if (hdev->hw_tc_map & mask &&
2168 hdev->tm_info.hw_pfc_map & mask) {
2169 /* Reduce the number of pfc TC with private buffer */
2170 priv->wl.low = 0;
2171 priv->enable = 0;
2172 priv->wl.high = 0;
2173 priv->buf_size = 0;
2174 pfc_priv_num--;
2175 }
2176
2177 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2178 pfc_priv_num == 0)
2179 break;
2180 }
2181
2182 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2183 }
2184
hclge_only_alloc_priv_buff(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2185 static bool hclge_only_alloc_priv_buff(struct hclge_dev *hdev,
2186 struct hclge_pkt_buf_alloc *buf_alloc)
2187 {
2188 #define COMPENSATE_BUFFER 0x3C00
2189 #define COMPENSATE_HALF_MPS_NUM 5
2190 #define PRIV_WL_GAP 0x1800
2191
2192 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2193 u32 tc_num = hclge_get_tc_num(hdev);
2194 u32 half_mps = hdev->mps >> 1;
2195 u32 min_rx_priv;
2196 unsigned int i;
2197
2198 if (tc_num)
2199 rx_priv = rx_priv / tc_num;
2200
2201 if (tc_num <= NEED_RESERVE_TC_NUM)
2202 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2203
2204 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER +
2205 COMPENSATE_HALF_MPS_NUM * half_mps;
2206 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT);
2207 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT);
2208 if (rx_priv < min_rx_priv)
2209 return false;
2210
2211 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2212 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2213
2214 priv->enable = 0;
2215 priv->wl.low = 0;
2216 priv->wl.high = 0;
2217 priv->buf_size = 0;
2218
2219 if (!(hdev->hw_tc_map & BIT(i)))
2220 continue;
2221
2222 priv->enable = 1;
2223 priv->buf_size = rx_priv;
2224 priv->wl.high = rx_priv - hdev->dv_buf_size;
2225 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2226 }
2227
2228 buf_alloc->s_buf.buf_size = 0;
2229
2230 return true;
2231 }
2232
2233 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
2234 * @hdev: pointer to struct hclge_dev
2235 * @buf_alloc: pointer to buffer calculation data
2236 * @return: 0: calculate successful, negative: fail
2237 */
hclge_rx_buffer_calc(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2238 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
2239 struct hclge_pkt_buf_alloc *buf_alloc)
2240 {
2241 /* When DCB is not supported, rx private buffer is not allocated. */
2242 if (!hnae3_dev_dcb_supported(hdev)) {
2243 u32 rx_all = hdev->pkt_buf_size;
2244
2245 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
2246 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
2247 return -ENOMEM;
2248
2249 return 0;
2250 }
2251
2252 if (hclge_only_alloc_priv_buff(hdev, buf_alloc))
2253 return 0;
2254
2255 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc))
2256 return 0;
2257
2258 /* try to decrease the buffer size */
2259 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc))
2260 return 0;
2261
2262 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc))
2263 return 0;
2264
2265 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc))
2266 return 0;
2267
2268 return -ENOMEM;
2269 }
2270
hclge_rx_priv_buf_alloc(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2271 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
2272 struct hclge_pkt_buf_alloc *buf_alloc)
2273 {
2274 struct hclge_rx_priv_buff_cmd *req;
2275 struct hclge_desc desc;
2276 int ret;
2277 int i;
2278
2279 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
2280 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
2281
2282 /* Alloc private buffer TCs */
2283 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2284 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2285
2286 req->buf_num[i] =
2287 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
2288 req->buf_num[i] |=
2289 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
2290 }
2291
2292 req->shared_buf =
2293 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
2294 (1 << HCLGE_TC0_PRI_BUF_EN_B));
2295
2296 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2297 if (ret)
2298 dev_err(&hdev->pdev->dev,
2299 "rx private buffer alloc cmd failed %d\n", ret);
2300
2301 return ret;
2302 }
2303
hclge_rx_priv_wl_config(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2304 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
2305 struct hclge_pkt_buf_alloc *buf_alloc)
2306 {
2307 struct hclge_rx_priv_wl_buf *req;
2308 struct hclge_priv_buf *priv;
2309 struct hclge_desc desc[2];
2310 int i, j;
2311 int ret;
2312
2313 for (i = 0; i < 2; i++) {
2314 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
2315 false);
2316 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
2317
2318 /* The first descriptor set the NEXT bit to 1 */
2319 if (i == 0)
2320 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2321 else
2322 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2323
2324 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2325 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
2326
2327 priv = &buf_alloc->priv_buf[idx];
2328 req->tc_wl[j].high =
2329 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
2330 req->tc_wl[j].high |=
2331 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2332 req->tc_wl[j].low =
2333 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
2334 req->tc_wl[j].low |=
2335 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2336 }
2337 }
2338
2339 /* Send 2 descriptor at one time */
2340 ret = hclge_cmd_send(&hdev->hw, desc, 2);
2341 if (ret)
2342 dev_err(&hdev->pdev->dev,
2343 "rx private waterline config cmd failed %d\n",
2344 ret);
2345 return ret;
2346 }
2347
hclge_common_thrd_config(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2348 static int hclge_common_thrd_config(struct hclge_dev *hdev,
2349 struct hclge_pkt_buf_alloc *buf_alloc)
2350 {
2351 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
2352 struct hclge_rx_com_thrd *req;
2353 struct hclge_desc desc[2];
2354 struct hclge_tc_thrd *tc;
2355 int i, j;
2356 int ret;
2357
2358 for (i = 0; i < 2; i++) {
2359 hclge_cmd_setup_basic_desc(&desc[i],
2360 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
2361 req = (struct hclge_rx_com_thrd *)desc[i].data;
2362
2363 /* The first descriptor set the NEXT bit to 1 */
2364 if (i == 0)
2365 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2366 else
2367 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2368
2369 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2370 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
2371
2372 req->com_thrd[j].high =
2373 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
2374 req->com_thrd[j].high |=
2375 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2376 req->com_thrd[j].low =
2377 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
2378 req->com_thrd[j].low |=
2379 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2380 }
2381 }
2382
2383 /* Send 2 descriptors at one time */
2384 ret = hclge_cmd_send(&hdev->hw, desc, 2);
2385 if (ret)
2386 dev_err(&hdev->pdev->dev,
2387 "common threshold config cmd failed %d\n", ret);
2388 return ret;
2389 }
2390
hclge_common_wl_config(struct hclge_dev * hdev,struct hclge_pkt_buf_alloc * buf_alloc)2391 static int hclge_common_wl_config(struct hclge_dev *hdev,
2392 struct hclge_pkt_buf_alloc *buf_alloc)
2393 {
2394 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
2395 struct hclge_rx_com_wl *req;
2396 struct hclge_desc desc;
2397 int ret;
2398
2399 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
2400
2401 req = (struct hclge_rx_com_wl *)desc.data;
2402 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
2403 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2404
2405 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
2406 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2407
2408 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2409 if (ret)
2410 dev_err(&hdev->pdev->dev,
2411 "common waterline config cmd failed %d\n", ret);
2412
2413 return ret;
2414 }
2415
hclge_buffer_alloc(struct hclge_dev * hdev)2416 int hclge_buffer_alloc(struct hclge_dev *hdev)
2417 {
2418 struct hclge_pkt_buf_alloc *pkt_buf;
2419 int ret;
2420
2421 pkt_buf = kzalloc_obj(*pkt_buf);
2422 if (!pkt_buf)
2423 return -ENOMEM;
2424
2425 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
2426 if (ret) {
2427 dev_err(&hdev->pdev->dev,
2428 "could not calc tx buffer size for all TCs %d\n", ret);
2429 goto out;
2430 }
2431
2432 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
2433 if (ret) {
2434 dev_err(&hdev->pdev->dev,
2435 "could not alloc tx buffers %d\n", ret);
2436 goto out;
2437 }
2438
2439 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
2440 if (ret) {
2441 dev_err(&hdev->pdev->dev,
2442 "could not calc rx priv buffer size for all TCs %d\n",
2443 ret);
2444 goto out;
2445 }
2446
2447 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
2448 if (ret) {
2449 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2450 ret);
2451 goto out;
2452 }
2453
2454 if (hnae3_dev_dcb_supported(hdev)) {
2455 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2456 if (ret) {
2457 dev_err(&hdev->pdev->dev,
2458 "could not configure rx private waterline %d\n",
2459 ret);
2460 goto out;
2461 }
2462
2463 ret = hclge_common_thrd_config(hdev, pkt_buf);
2464 if (ret) {
2465 dev_err(&hdev->pdev->dev,
2466 "could not configure common threshold %d\n",
2467 ret);
2468 goto out;
2469 }
2470 }
2471
2472 ret = hclge_common_wl_config(hdev, pkt_buf);
2473 if (ret)
2474 dev_err(&hdev->pdev->dev,
2475 "could not configure common waterline %d\n", ret);
2476
2477 out:
2478 kfree(pkt_buf);
2479 return ret;
2480 }
2481
hclge_init_roce_base_info(struct hclge_vport * vport)2482 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2483 {
2484 struct hnae3_handle *roce = &vport->roce;
2485 struct hnae3_handle *nic = &vport->nic;
2486 struct hclge_dev *hdev = vport->back;
2487
2488 roce->rinfo.num_vectors = vport->back->num_roce_msi;
2489
2490 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
2491 return -EINVAL;
2492
2493 roce->rinfo.base_vector = hdev->num_nic_msi;
2494
2495 roce->rinfo.netdev = nic->kinfo.netdev;
2496 roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2497 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2498
2499 roce->pdev = nic->pdev;
2500 roce->ae_algo = nic->ae_algo;
2501 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits,
2502 MAX_NUMNODES);
2503
2504 return 0;
2505 }
2506
hclge_init_msi(struct hclge_dev * hdev)2507 static int hclge_init_msi(struct hclge_dev *hdev)
2508 {
2509 struct pci_dev *pdev = hdev->pdev;
2510 int vectors;
2511 int i;
2512
2513 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2514 hdev->num_msi,
2515 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2516 if (vectors < 0) {
2517 dev_err(&pdev->dev,
2518 "failed(%d) to allocate MSI/MSI-X vectors\n",
2519 vectors);
2520 return vectors;
2521 }
2522 if (vectors < hdev->num_msi)
2523 dev_warn(&hdev->pdev->dev,
2524 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2525 hdev->num_msi, vectors);
2526
2527 hdev->num_msi = vectors;
2528 hdev->num_msi_left = vectors;
2529
2530 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2531 sizeof(u16), GFP_KERNEL);
2532 if (!hdev->vector_status) {
2533 pci_free_irq_vectors(pdev);
2534 return -ENOMEM;
2535 }
2536
2537 for (i = 0; i < hdev->num_msi; i++)
2538 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2539
2540 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2541 sizeof(int), GFP_KERNEL);
2542 if (!hdev->vector_irq) {
2543 pci_free_irq_vectors(pdev);
2544 return -ENOMEM;
2545 }
2546
2547 return 0;
2548 }
2549
hclge_check_speed_dup(u8 duplex,int speed)2550 static u8 hclge_check_speed_dup(u8 duplex, int speed)
2551 {
2552 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
2553 duplex = HCLGE_MAC_FULL;
2554
2555 return duplex;
2556 }
2557
2558 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = {
2559 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M},
2560 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M},
2561 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G},
2562 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G},
2563 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G},
2564 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G},
2565 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G},
2566 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G},
2567 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G},
2568 };
2569
hclge_convert_to_fw_speed(u32 speed_drv,u32 * speed_fw)2570 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw)
2571 {
2572 u16 i;
2573
2574 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) {
2575 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) {
2576 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw;
2577 return 0;
2578 }
2579 }
2580
2581 return -EINVAL;
2582 }
2583
hclge_cfg_mac_speed_dup_hw(struct hclge_dev * hdev,int speed,u8 duplex,u8 lane_num)2584 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
2585 u8 duplex, u8 lane_num)
2586 {
2587 struct hclge_config_mac_speed_dup_cmd *req;
2588 struct hclge_desc desc;
2589 u32 speed_fw;
2590 int ret;
2591
2592 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2593
2594 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2595
2596 if (duplex)
2597 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1);
2598
2599 ret = hclge_convert_to_fw_speed(speed, &speed_fw);
2600 if (ret) {
2601 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2602 return ret;
2603 }
2604
2605 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S,
2606 speed_fw);
2607 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2608 1);
2609 req->lane_num = lane_num;
2610
2611 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2612 if (ret) {
2613 dev_err(&hdev->pdev->dev,
2614 "mac speed/duplex config cmd failed %d.\n", ret);
2615 return ret;
2616 }
2617
2618 return 0;
2619 }
2620
hclge_cfg_mac_speed_dup(struct hclge_dev * hdev,int speed,u8 duplex,u8 lane_num)2621 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num)
2622 {
2623 struct hclge_mac *mac = &hdev->hw.mac;
2624 int ret;
2625
2626 duplex = hclge_check_speed_dup(duplex, speed);
2627 if (!mac->support_autoneg && mac->speed == (u32)speed &&
2628 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0))
2629 return 0;
2630
2631 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
2632 if (ret)
2633 return ret;
2634
2635 hdev->hw.mac.speed = speed;
2636 hdev->hw.mac.duplex = duplex;
2637 if (!lane_num)
2638 hdev->hw.mac.lane_num = lane_num;
2639
2640 return 0;
2641 }
2642
hclge_cfg_mac_speed_dup_h(struct hnae3_handle * handle,int speed,u8 duplex,u8 lane_num)2643 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2644 u8 duplex, u8 lane_num)
2645 {
2646 struct hclge_vport *vport = hclge_get_vport(handle);
2647 struct hclge_dev *hdev = vport->back;
2648 int ret;
2649
2650 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num);
2651
2652 if (ret)
2653 return ret;
2654
2655 hdev->hw.mac.req_speed = (u32)speed;
2656 hdev->hw.mac.req_duplex = duplex;
2657
2658 return 0;
2659 }
2660
hclge_set_autoneg_en(struct hclge_dev * hdev,bool enable)2661 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2662 {
2663 struct hclge_config_auto_neg_cmd *req;
2664 struct hclge_desc desc;
2665 u32 flag = 0;
2666 int ret;
2667
2668 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2669
2670 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2671 if (enable)
2672 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U);
2673 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2674
2675 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2676 if (ret)
2677 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2678 ret);
2679
2680 return ret;
2681 }
2682
hclge_set_autoneg(struct hnae3_handle * handle,bool enable)2683 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2684 {
2685 struct hclge_vport *vport = hclge_get_vport(handle);
2686 struct hclge_dev *hdev = vport->back;
2687
2688 if (!hdev->hw.mac.support_autoneg) {
2689 if (enable) {
2690 dev_err(&hdev->pdev->dev,
2691 "autoneg is not supported by current port\n");
2692 return -EOPNOTSUPP;
2693 } else {
2694 return 0;
2695 }
2696 }
2697
2698 return hclge_set_autoneg_en(hdev, enable);
2699 }
2700
hclge_get_autoneg(struct hnae3_handle * handle)2701 static int hclge_get_autoneg(struct hnae3_handle *handle)
2702 {
2703 struct hclge_vport *vport = hclge_get_vport(handle);
2704 struct hclge_dev *hdev = vport->back;
2705 struct phy_device *phydev = hdev->hw.mac.phydev;
2706
2707 if (phydev)
2708 return phydev->autoneg;
2709
2710 return hdev->hw.mac.autoneg;
2711 }
2712
hclge_restart_autoneg(struct hnae3_handle * handle)2713 static int hclge_restart_autoneg(struct hnae3_handle *handle)
2714 {
2715 struct hclge_vport *vport = hclge_get_vport(handle);
2716 struct hclge_dev *hdev = vport->back;
2717 int ret;
2718
2719 dev_dbg(&hdev->pdev->dev, "restart autoneg\n");
2720
2721 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2722 if (ret)
2723 return ret;
2724 return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2725 }
2726
hclge_halt_autoneg(struct hnae3_handle * handle,bool halt)2727 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt)
2728 {
2729 struct hclge_vport *vport = hclge_get_vport(handle);
2730 struct hclge_dev *hdev = vport->back;
2731
2732 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg)
2733 return hclge_set_autoneg_en(hdev, !halt);
2734
2735 return 0;
2736 }
2737
hclge_parse_fec_stats_lanes(struct hclge_dev * hdev,struct hclge_desc * desc,u32 desc_len)2738 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev,
2739 struct hclge_desc *desc, u32 desc_len)
2740 {
2741 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2;
2742 u32 desc_index = 0;
2743 u32 data_index = 0;
2744 u32 i;
2745
2746 for (i = 0; i < lane_size; i++) {
2747 if (data_index >= HCLGE_DESC_DATA_LEN) {
2748 desc_index++;
2749 data_index = 0;
2750 }
2751
2752 if (desc_index >= desc_len)
2753 return;
2754
2755 hdev->fec_stats.per_lanes[i] +=
2756 le32_to_cpu(desc[desc_index].data[data_index]);
2757 data_index++;
2758 }
2759 }
2760
hclge_parse_fec_stats(struct hclge_dev * hdev,struct hclge_desc * desc,u32 desc_len)2761 static void hclge_parse_fec_stats(struct hclge_dev *hdev,
2762 struct hclge_desc *desc, u32 desc_len)
2763 {
2764 struct hclge_query_fec_stats_cmd *req;
2765
2766 req = (struct hclge_query_fec_stats_cmd *)desc[0].data;
2767
2768 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num;
2769 hdev->fec_stats.rs_corr_blocks +=
2770 le32_to_cpu(req->rs_fec_corr_blocks);
2771 hdev->fec_stats.rs_uncorr_blocks +=
2772 le32_to_cpu(req->rs_fec_uncorr_blocks);
2773 hdev->fec_stats.rs_error_blocks +=
2774 le32_to_cpu(req->rs_fec_error_blocks);
2775 hdev->fec_stats.base_r_corr_blocks +=
2776 le32_to_cpu(req->base_r_fec_corr_blocks);
2777 hdev->fec_stats.base_r_uncorr_blocks +=
2778 le32_to_cpu(req->base_r_fec_uncorr_blocks);
2779
2780 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1);
2781 }
2782
hclge_update_fec_stats_hw(struct hclge_dev * hdev)2783 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev)
2784 {
2785 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM];
2786 int ret;
2787 u32 i;
2788
2789 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) {
2790 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS,
2791 true);
2792 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1))
2793 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2794 }
2795
2796 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM);
2797 if (ret)
2798 return ret;
2799
2800 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM);
2801
2802 return 0;
2803 }
2804
hclge_update_fec_stats(struct hclge_dev * hdev)2805 static void hclge_update_fec_stats(struct hclge_dev *hdev)
2806 {
2807 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2808 int ret;
2809
2810 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) ||
2811 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state))
2812 return;
2813
2814 ret = hclge_update_fec_stats_hw(hdev);
2815 if (ret)
2816 dev_err(&hdev->pdev->dev,
2817 "failed to update fec stats, ret = %d\n", ret);
2818
2819 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state);
2820 }
2821
hclge_get_fec_stats_total(struct hclge_dev * hdev,struct ethtool_fec_stats * fec_stats)2822 static void hclge_get_fec_stats_total(struct hclge_dev *hdev,
2823 struct ethtool_fec_stats *fec_stats)
2824 {
2825 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks;
2826 fec_stats->uncorrectable_blocks.total =
2827 hdev->fec_stats.rs_uncorr_blocks;
2828 }
2829
hclge_get_fec_stats_lanes(struct hclge_dev * hdev,struct ethtool_fec_stats * fec_stats)2830 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev,
2831 struct ethtool_fec_stats *fec_stats)
2832 {
2833 u32 i;
2834
2835 if (hdev->fec_stats.base_r_lane_num == 0 ||
2836 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) {
2837 dev_err(&hdev->pdev->dev,
2838 "fec stats lane number(%llu) is invalid\n",
2839 hdev->fec_stats.base_r_lane_num);
2840 return;
2841 }
2842
2843 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) {
2844 fec_stats->corrected_blocks.lanes[i] =
2845 hdev->fec_stats.base_r_corr_per_lanes[i];
2846 fec_stats->uncorrectable_blocks.lanes[i] =
2847 hdev->fec_stats.base_r_uncorr_per_lanes[i];
2848 }
2849 }
2850
hclge_comm_get_fec_stats(struct hclge_dev * hdev,struct ethtool_fec_stats * fec_stats)2851 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev,
2852 struct ethtool_fec_stats *fec_stats)
2853 {
2854 u32 fec_mode = hdev->hw.mac.fec_mode;
2855
2856 switch (fec_mode) {
2857 case BIT(HNAE3_FEC_RS):
2858 case BIT(HNAE3_FEC_LLRS):
2859 hclge_get_fec_stats_total(hdev, fec_stats);
2860 break;
2861 case BIT(HNAE3_FEC_BASER):
2862 hclge_get_fec_stats_lanes(hdev, fec_stats);
2863 break;
2864 default:
2865 dev_err(&hdev->pdev->dev,
2866 "fec stats is not supported by current fec mode(0x%x)\n",
2867 fec_mode);
2868 break;
2869 }
2870 }
2871
hclge_get_fec_stats(struct hnae3_handle * handle,struct ethtool_fec_stats * fec_stats)2872 static void hclge_get_fec_stats(struct hnae3_handle *handle,
2873 struct ethtool_fec_stats *fec_stats)
2874 {
2875 struct hclge_vport *vport = hclge_get_vport(handle);
2876 struct hclge_dev *hdev = vport->back;
2877 u32 fec_mode = hdev->hw.mac.fec_mode;
2878
2879 if (fec_mode == BIT(HNAE3_FEC_NONE) ||
2880 fec_mode == BIT(HNAE3_FEC_AUTO) ||
2881 fec_mode == BIT(HNAE3_FEC_USER_DEF))
2882 return;
2883
2884 hclge_update_fec_stats(hdev);
2885
2886 hclge_comm_get_fec_stats(hdev, fec_stats);
2887 }
2888
hclge_set_fec_hw(struct hclge_dev * hdev,u32 fec_mode)2889 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
2890 {
2891 struct hclge_config_fec_cmd *req;
2892 struct hclge_desc desc;
2893 int ret;
2894
2895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false);
2896
2897 req = (struct hclge_config_fec_cmd *)desc.data;
2898 if (fec_mode & BIT(HNAE3_FEC_AUTO))
2899 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1);
2900 if (fec_mode & BIT(HNAE3_FEC_RS))
2901 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2902 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS);
2903 if (fec_mode & BIT(HNAE3_FEC_LLRS))
2904 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2905 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS);
2906 if (fec_mode & BIT(HNAE3_FEC_BASER))
2907 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2908 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER);
2909
2910 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2911 if (ret)
2912 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret);
2913
2914 return ret;
2915 }
2916
hclge_set_fec(struct hnae3_handle * handle,u32 fec_mode)2917 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode)
2918 {
2919 struct hclge_vport *vport = hclge_get_vport(handle);
2920 struct hclge_dev *hdev = vport->back;
2921 struct hclge_mac *mac = &hdev->hw.mac;
2922 int ret;
2923
2924 if (fec_mode && !(mac->fec_ability & fec_mode)) {
2925 dev_err(&hdev->pdev->dev, "unsupported fec mode\n");
2926 return -EINVAL;
2927 }
2928
2929 ret = hclge_set_fec_hw(hdev, fec_mode);
2930 if (ret)
2931 return ret;
2932
2933 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF);
2934 return 0;
2935 }
2936
hclge_get_fec(struct hnae3_handle * handle,u8 * fec_ability,u8 * fec_mode)2937 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability,
2938 u8 *fec_mode)
2939 {
2940 struct hclge_vport *vport = hclge_get_vport(handle);
2941 struct hclge_dev *hdev = vport->back;
2942 struct hclge_mac *mac = &hdev->hw.mac;
2943
2944 if (fec_ability)
2945 *fec_ability = mac->fec_ability;
2946 if (fec_mode)
2947 *fec_mode = mac->fec_mode;
2948 }
2949
hclge_mac_init(struct hclge_dev * hdev)2950 static int hclge_mac_init(struct hclge_dev *hdev)
2951 {
2952 struct hclge_mac *mac = &hdev->hw.mac;
2953 int ret;
2954
2955 hdev->support_sfp_query = true;
2956
2957 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2958 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2959
2960 if (hdev->hw.mac.support_autoneg) {
2961 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg);
2962 if (ret)
2963 return ret;
2964 }
2965
2966 if (!hdev->hw.mac.autoneg) {
2967 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed,
2968 hdev->hw.mac.req_duplex,
2969 hdev->hw.mac.lane_num);
2970 if (ret)
2971 return ret;
2972 }
2973
2974 mac->link = 0;
2975
2976 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) {
2977 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode);
2978 if (ret)
2979 return ret;
2980 }
2981
2982 ret = hclge_set_mac_mtu(hdev, hdev->mps);
2983 if (ret) {
2984 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2985 return ret;
2986 }
2987
2988 ret = hclge_set_default_loopback(hdev);
2989 if (ret)
2990 return ret;
2991
2992 ret = hclge_buffer_alloc(hdev);
2993 if (ret)
2994 dev_err(&hdev->pdev->dev,
2995 "allocate buffer fail, ret=%d\n", ret);
2996
2997 return ret;
2998 }
2999
hclge_mbx_task_schedule(struct hclge_dev * hdev)3000 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
3001 {
3002 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3003 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) {
3004 hdev->last_mbx_scheduled = jiffies;
3005 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
3006 }
3007 }
3008
hclge_reset_task_schedule(struct hclge_dev * hdev)3009 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
3010 {
3011 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3012 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
3013 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) {
3014 hdev->last_rst_scheduled = jiffies;
3015 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
3016 }
3017 }
3018
hclge_errhand_task_schedule(struct hclge_dev * hdev)3019 static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
3020 {
3021 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3022 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
3023 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
3024 }
3025
hclge_task_schedule(struct hclge_dev * hdev,unsigned long delay_time)3026 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time)
3027 {
3028 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3029 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
3030 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time);
3031 }
3032
hclge_get_mac_link_status(struct hclge_dev * hdev,int * link_status)3033 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status)
3034 {
3035 struct hclge_link_status_cmd *req;
3036 struct hclge_desc desc;
3037 int ret;
3038
3039 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
3040 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3041 if (ret) {
3042 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
3043 ret);
3044 return ret;
3045 }
3046
3047 req = (struct hclge_link_status_cmd *)desc.data;
3048 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ?
3049 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
3050
3051 return 0;
3052 }
3053
hclge_get_mac_phy_link(struct hclge_dev * hdev,int * link_status)3054 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status)
3055 {
3056 struct phy_device *phydev = hdev->hw.mac.phydev;
3057
3058 *link_status = HCLGE_LINK_STATUS_DOWN;
3059
3060 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
3061 return 0;
3062
3063 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link))
3064 return 0;
3065
3066 return hclge_get_mac_link_status(hdev, link_status);
3067 }
3068
hclge_push_link_status(struct hclge_dev * hdev)3069 static void hclge_push_link_status(struct hclge_dev *hdev)
3070 {
3071 struct hclge_vport *vport;
3072 int ret;
3073 u16 i;
3074
3075 for (i = 0; i < pci_num_vf(hdev->pdev); i++) {
3076 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
3077
3078 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) ||
3079 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO)
3080 continue;
3081
3082 ret = hclge_push_vf_link_status(vport);
3083 if (ret) {
3084 dev_err(&hdev->pdev->dev,
3085 "failed to push link status to vf%u, ret = %d\n",
3086 i, ret);
3087 }
3088 }
3089 }
3090
hclge_update_link_status(struct hclge_dev * hdev)3091 static void hclge_update_link_status(struct hclge_dev *hdev)
3092 {
3093 struct hnae3_handle *handle = &hdev->vport[0].nic;
3094 struct hnae3_client *client = hdev->nic_client;
3095 int state;
3096 int ret;
3097
3098 if (!client)
3099 return;
3100
3101 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state))
3102 return;
3103
3104 ret = hclge_get_mac_phy_link(hdev, &state);
3105 if (ret) {
3106 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3107 return;
3108 }
3109
3110 if (state != hdev->hw.mac.link) {
3111 hdev->hw.mac.link = state;
3112 if (state == HCLGE_LINK_STATUS_UP)
3113 hclge_update_port_info(hdev);
3114
3115 client->ops->link_status_change(handle, state);
3116 hclge_config_mac_tnl_int(hdev, state);
3117
3118 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) {
3119 struct hnae3_handle *rhandle = &hdev->vport[0].roce;
3120 struct hnae3_client *rclient = hdev->roce_client;
3121
3122 if (rclient && rclient->ops->link_status_change)
3123 rclient->ops->link_status_change(rhandle,
3124 state);
3125 }
3126
3127 hclge_push_link_status(hdev);
3128 }
3129
3130 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3131 }
3132
hclge_update_speed_advertising(struct hclge_mac * mac)3133 static void hclge_update_speed_advertising(struct hclge_mac *mac)
3134 {
3135 u32 speed_ability;
3136
3137 if (hclge_get_speed_bit(mac->speed, &speed_ability))
3138 return;
3139
3140 switch (mac->module_type) {
3141 case HNAE3_MODULE_TYPE_FIBRE_LR:
3142 hclge_convert_setting_lr(speed_ability, mac->advertising);
3143 break;
3144 case HNAE3_MODULE_TYPE_FIBRE_SR:
3145 case HNAE3_MODULE_TYPE_AOC:
3146 hclge_convert_setting_sr(speed_ability, mac->advertising);
3147 break;
3148 case HNAE3_MODULE_TYPE_CR:
3149 hclge_convert_setting_cr(speed_ability, mac->advertising);
3150 break;
3151 case HNAE3_MODULE_TYPE_KR:
3152 hclge_convert_setting_kr(speed_ability, mac->advertising);
3153 break;
3154 default:
3155 break;
3156 }
3157 }
3158
hclge_update_fec_advertising(struct hclge_mac * mac)3159 static void hclge_update_fec_advertising(struct hclge_mac *mac)
3160 {
3161 if (mac->fec_mode & BIT(HNAE3_FEC_RS))
3162 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
3163 mac->advertising);
3164 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS))
3165 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
3166 mac->advertising);
3167 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
3168 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
3169 mac->advertising);
3170 else
3171 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
3172 mac->advertising);
3173 }
3174
hclge_update_pause_advertising(struct hclge_dev * hdev)3175 static void hclge_update_pause_advertising(struct hclge_dev *hdev)
3176 {
3177 struct hclge_mac *mac = &hdev->hw.mac;
3178 bool rx_en, tx_en;
3179
3180 switch (hdev->fc_mode_last_time) {
3181 case HCLGE_FC_RX_PAUSE:
3182 rx_en = true;
3183 tx_en = false;
3184 break;
3185 case HCLGE_FC_TX_PAUSE:
3186 rx_en = false;
3187 tx_en = true;
3188 break;
3189 case HCLGE_FC_FULL:
3190 rx_en = true;
3191 tx_en = true;
3192 break;
3193 default:
3194 rx_en = false;
3195 tx_en = false;
3196 break;
3197 }
3198
3199 linkmode_set_pause(mac->advertising, tx_en, rx_en);
3200 }
3201
hclge_update_advertising(struct hclge_dev * hdev)3202 static void hclge_update_advertising(struct hclge_dev *hdev)
3203 {
3204 struct hclge_mac *mac = &hdev->hw.mac;
3205
3206 linkmode_zero(mac->advertising);
3207 hclge_update_speed_advertising(mac);
3208 hclge_update_fec_advertising(mac);
3209 hclge_update_pause_advertising(hdev);
3210 }
3211
hclge_update_port_capability(struct hclge_dev * hdev,struct hclge_mac * mac)3212 static void hclge_update_port_capability(struct hclge_dev *hdev,
3213 struct hclge_mac *mac)
3214 {
3215 if (hnae3_dev_fec_supported(hdev))
3216 hclge_convert_setting_fec(mac);
3217
3218 /* firmware can not identify back plane type, the media type
3219 * read from configuration can help deal it
3220 */
3221 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE &&
3222 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN)
3223 mac->module_type = HNAE3_MODULE_TYPE_KR;
3224 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3225 mac->module_type = HNAE3_MODULE_TYPE_TP;
3226
3227 if (mac->support_autoneg) {
3228 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported);
3229 linkmode_copy(mac->advertising, mac->supported);
3230 } else {
3231 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3232 mac->supported);
3233 hclge_update_advertising(hdev);
3234 }
3235 }
3236
hclge_get_sfp_speed(struct hclge_dev * hdev,u32 * speed)3237 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
3238 {
3239 struct hclge_sfp_info_cmd *resp;
3240 struct hclge_desc desc;
3241 int ret;
3242
3243 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3244 resp = (struct hclge_sfp_info_cmd *)desc.data;
3245 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3246 if (ret == -EOPNOTSUPP) {
3247 dev_warn(&hdev->pdev->dev,
3248 "IMP do not support get SFP speed %d\n", ret);
3249 return ret;
3250 } else if (ret) {
3251 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
3252 return ret;
3253 }
3254
3255 *speed = le32_to_cpu(resp->speed);
3256
3257 return 0;
3258 }
3259
hclge_get_sfp_info(struct hclge_dev * hdev,struct hclge_mac * mac)3260 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
3261 {
3262 struct hclge_sfp_info_cmd *resp;
3263 struct hclge_desc desc;
3264 int ret;
3265
3266 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3267 resp = (struct hclge_sfp_info_cmd *)desc.data;
3268
3269 resp->query_type = QUERY_ACTIVE_SPEED;
3270
3271 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3272 if (ret == -EOPNOTSUPP) {
3273 dev_warn(&hdev->pdev->dev,
3274 "IMP does not support get SFP info %d\n", ret);
3275 return ret;
3276 } else if (ret) {
3277 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret);
3278 return ret;
3279 }
3280
3281 /* In some case, mac speed get from IMP may be 0, it shouldn't be
3282 * set to mac->speed.
3283 */
3284 if (!le32_to_cpu(resp->speed))
3285 return 0;
3286
3287 mac->speed = le32_to_cpu(resp->speed);
3288 /* if resp->speed_ability is 0, it means it's an old version
3289 * firmware, do not update these params
3290 */
3291 if (resp->speed_ability) {
3292 mac->module_type = le32_to_cpu(resp->module_type);
3293 mac->speed_ability = le32_to_cpu(resp->speed_ability);
3294 mac->autoneg = resp->autoneg;
3295 mac->support_autoneg = resp->autoneg_ability;
3296 mac->speed_type = QUERY_ACTIVE_SPEED;
3297 mac->lane_num = resp->lane_num;
3298 if (!resp->active_fec)
3299 mac->fec_mode = 0;
3300 else
3301 mac->fec_mode = BIT(resp->active_fec);
3302 mac->fec_ability = resp->fec_ability;
3303 } else {
3304 mac->speed_type = QUERY_SFP_SPEED;
3305 }
3306
3307 return 0;
3308 }
3309
hclge_get_phy_link_ksettings(struct hnae3_handle * handle,struct ethtool_link_ksettings * cmd)3310 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
3311 struct ethtool_link_ksettings *cmd)
3312 {
3313 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3314 struct hclge_vport *vport = hclge_get_vport(handle);
3315 struct hclge_phy_link_ksetting_0_cmd *req0;
3316 struct hclge_phy_link_ksetting_1_cmd *req1;
3317 u32 supported, advertising, lp_advertising;
3318 struct hclge_dev *hdev = vport->back;
3319 int ret;
3320
3321 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3322 true);
3323 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3324 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3325 true);
3326
3327 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3328 if (ret) {
3329 dev_err(&hdev->pdev->dev,
3330 "failed to get phy link ksetting, ret = %d.\n", ret);
3331 return ret;
3332 }
3333
3334 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3335 cmd->base.autoneg = req0->autoneg;
3336 cmd->base.speed = le32_to_cpu(req0->speed);
3337 cmd->base.duplex = req0->duplex;
3338 cmd->base.port = req0->port;
3339 cmd->base.transceiver = req0->transceiver;
3340 cmd->base.phy_address = req0->phy_address;
3341 cmd->base.eth_tp_mdix = req0->eth_tp_mdix;
3342 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl;
3343 supported = le32_to_cpu(req0->supported);
3344 advertising = le32_to_cpu(req0->advertising);
3345 lp_advertising = le32_to_cpu(req0->lp_advertising);
3346 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3347 supported);
3348 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3349 advertising);
3350 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
3351 lp_advertising);
3352
3353 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3354 cmd->base.master_slave_cfg = req1->master_slave_cfg;
3355 cmd->base.master_slave_state = req1->master_slave_state;
3356
3357 return 0;
3358 }
3359
3360 static int
hclge_set_phy_link_ksettings(struct hnae3_handle * handle,const struct ethtool_link_ksettings * cmd)3361 hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
3362 const struct ethtool_link_ksettings *cmd)
3363 {
3364 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3365 struct hclge_vport *vport = hclge_get_vport(handle);
3366 struct hclge_phy_link_ksetting_0_cmd *req0;
3367 struct hclge_phy_link_ksetting_1_cmd *req1;
3368 struct hclge_dev *hdev = vport->back;
3369 u32 advertising;
3370 int ret;
3371
3372 if (cmd->base.autoneg == AUTONEG_DISABLE &&
3373 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) ||
3374 (cmd->base.duplex != DUPLEX_HALF &&
3375 cmd->base.duplex != DUPLEX_FULL)))
3376 return -EINVAL;
3377
3378 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3379 false);
3380 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3381 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3382 false);
3383
3384 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3385 req0->autoneg = cmd->base.autoneg;
3386 req0->speed = cpu_to_le32(cmd->base.speed);
3387 req0->duplex = cmd->base.duplex;
3388 ethtool_convert_link_mode_to_legacy_u32(&advertising,
3389 cmd->link_modes.advertising);
3390 req0->advertising = cpu_to_le32(advertising);
3391 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
3392
3393 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3394 req1->master_slave_cfg = cmd->base.master_slave_cfg;
3395
3396 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3397 if (ret) {
3398 dev_err(&hdev->pdev->dev,
3399 "failed to set phy link ksettings, ret = %d.\n", ret);
3400 return ret;
3401 }
3402
3403 hdev->hw.mac.req_autoneg = cmd->base.autoneg;
3404 hdev->hw.mac.req_speed = cmd->base.speed;
3405 hdev->hw.mac.req_duplex = cmd->base.duplex;
3406 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising);
3407
3408 return 0;
3409 }
3410
hclge_update_tp_port_info(struct hclge_dev * hdev)3411 static int hclge_update_tp_port_info(struct hclge_dev *hdev)
3412 {
3413 struct ethtool_link_ksettings cmd;
3414 int ret;
3415
3416 if (!hnae3_dev_phy_imp_supported(hdev))
3417 return 0;
3418
3419 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd);
3420 if (ret)
3421 return ret;
3422
3423 hdev->hw.mac.autoneg = cmd.base.autoneg;
3424 hdev->hw.mac.speed = cmd.base.speed;
3425 hdev->hw.mac.duplex = cmd.base.duplex;
3426 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising);
3427
3428 return 0;
3429 }
3430
hclge_tp_port_init(struct hclge_dev * hdev)3431 static int hclge_tp_port_init(struct hclge_dev *hdev)
3432 {
3433 struct ethtool_link_ksettings cmd;
3434
3435 if (!hnae3_dev_phy_imp_supported(hdev))
3436 return 0;
3437
3438 cmd.base.autoneg = hdev->hw.mac.req_autoneg;
3439 cmd.base.speed = hdev->hw.mac.req_speed;
3440 cmd.base.duplex = hdev->hw.mac.req_duplex;
3441 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising);
3442
3443 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd);
3444 }
3445
hclge_update_port_info(struct hclge_dev * hdev)3446 static int hclge_update_port_info(struct hclge_dev *hdev)
3447 {
3448 struct hclge_mac *mac = &hdev->hw.mac;
3449 u32 speed;
3450 int ret;
3451
3452 /* get the port info from SFP cmd if not copper port */
3453 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3454 return hclge_update_tp_port_info(hdev);
3455
3456 /* if IMP does not support get SFP/qSFP info, return directly */
3457 if (!hdev->support_sfp_query)
3458 return 0;
3459
3460 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3461 speed = mac->speed;
3462 ret = hclge_get_sfp_info(hdev, mac);
3463 } else {
3464 speed = HCLGE_MAC_SPEED_UNKNOWN;
3465 ret = hclge_get_sfp_speed(hdev, &speed);
3466 }
3467
3468 if (ret == -EOPNOTSUPP) {
3469 hdev->support_sfp_query = false;
3470 return ret;
3471 } else if (ret) {
3472 return ret;
3473 }
3474
3475 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3476 if (mac->speed_type == QUERY_ACTIVE_SPEED) {
3477 hclge_update_port_capability(hdev, mac);
3478 if (mac->speed != speed)
3479 (void)hclge_tm_port_shaper_cfg(hdev);
3480 return 0;
3481 }
3482 return hclge_cfg_mac_speed_dup(hdev, mac->speed,
3483 HCLGE_MAC_FULL, mac->lane_num);
3484 } else {
3485 if (speed == HCLGE_MAC_SPEED_UNKNOWN)
3486 return 0; /* do nothing if no SFP */
3487
3488 /* must config full duplex for SFP */
3489 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0);
3490 }
3491 }
3492
hclge_get_status(struct hnae3_handle * handle)3493 static int hclge_get_status(struct hnae3_handle *handle)
3494 {
3495 struct hclge_vport *vport = hclge_get_vport(handle);
3496 struct hclge_dev *hdev = vport->back;
3497
3498 hclge_update_link_status(hdev);
3499
3500 return hdev->hw.mac.link;
3501 }
3502
hclge_get_vf_vport(struct hclge_dev * hdev,int vf)3503 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
3504 {
3505 if (!pci_num_vf(hdev->pdev)) {
3506 dev_err(&hdev->pdev->dev,
3507 "SRIOV is disabled, can not get vport(%d) info.\n", vf);
3508 return NULL;
3509 }
3510
3511 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) {
3512 dev_err(&hdev->pdev->dev,
3513 "vf id(%d) is out of range(0 <= vfid < %d)\n",
3514 vf, pci_num_vf(hdev->pdev));
3515 return NULL;
3516 }
3517
3518 /* VF start from 1 in vport */
3519 vf += HCLGE_VF_VPORT_START_NUM;
3520 return &hdev->vport[vf];
3521 }
3522
hclge_get_vf_config(struct hnae3_handle * handle,int vf,struct ifla_vf_info * ivf)3523 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf,
3524 struct ifla_vf_info *ivf)
3525 {
3526 struct hclge_vport *vport = hclge_get_vport(handle);
3527 struct hclge_dev *hdev = vport->back;
3528
3529 vport = hclge_get_vf_vport(hdev, vf);
3530 if (!vport)
3531 return -EINVAL;
3532
3533 ivf->vf = vf;
3534 ivf->linkstate = vport->vf_info.link_state;
3535 ivf->spoofchk = vport->vf_info.spoofchk;
3536 ivf->trusted = vport->vf_info.trusted;
3537 ivf->min_tx_rate = 0;
3538 ivf->max_tx_rate = vport->vf_info.max_tx_rate;
3539 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag;
3540 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto);
3541 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos;
3542 ether_addr_copy(ivf->mac, vport->vf_info.mac);
3543
3544 return 0;
3545 }
3546
hclge_set_vf_link_state(struct hnae3_handle * handle,int vf,int link_state)3547 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
3548 int link_state)
3549 {
3550 struct hclge_vport *vport = hclge_get_vport(handle);
3551 struct hclge_dev *hdev = vport->back;
3552 int link_state_old;
3553 int ret;
3554
3555 vport = hclge_get_vf_vport(hdev, vf);
3556 if (!vport)
3557 return -EINVAL;
3558
3559 link_state_old = vport->vf_info.link_state;
3560 vport->vf_info.link_state = link_state;
3561
3562 /* return success directly if the VF is unalive, VF will
3563 * query link state itself when it starts work.
3564 */
3565 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3566 return 0;
3567
3568 ret = hclge_push_vf_link_status(vport);
3569 if (ret) {
3570 vport->vf_info.link_state = link_state_old;
3571 dev_err(&hdev->pdev->dev,
3572 "failed to push vf%d link status, ret = %d\n", vf, ret);
3573 }
3574
3575 return ret;
3576 }
3577
hclge_set_reset_pending(struct hclge_dev * hdev,enum hnae3_reset_type reset_type)3578 static void hclge_set_reset_pending(struct hclge_dev *hdev,
3579 enum hnae3_reset_type reset_type)
3580 {
3581 /* When an incorrect reset type is executed, the get_reset_level
3582 * function generates the HNAE3_NONE_RESET flag. As a result, this
3583 * type do not need to pending.
3584 */
3585 if (reset_type != HNAE3_NONE_RESET)
3586 set_bit(reset_type, &hdev->reset_pending);
3587 }
3588
hclge_check_event_cause(struct hclge_dev * hdev,u32 * clearval)3589 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
3590 {
3591 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
3592
3593 /* fetch the events from their corresponding regs */
3594 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
3595 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
3596 hw_err_src_reg = hclge_read_dev(&hdev->hw,
3597 HCLGE_RAS_PF_OTHER_INT_STS_REG);
3598
3599 /* Assumption: If by any chance reset and mailbox events are reported
3600 * together then we will only process reset event in this go and will
3601 * defer the processing of the mailbox events. Since, we would have not
3602 * cleared RX CMDQ event this time we would receive again another
3603 * interrupt from H/W just for the mailbox.
3604 *
3605 * check for vector0 reset event sources
3606 */
3607 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
3608 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
3609 hclge_set_reset_pending(hdev, HNAE3_IMP_RESET);
3610 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3611 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
3612 hdev->rst_stats.imp_rst_cnt++;
3613 return HCLGE_VECTOR0_EVENT_RST;
3614 }
3615
3616 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
3617 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
3618 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3619 hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET);
3620 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
3621 hdev->rst_stats.global_rst_cnt++;
3622 return HCLGE_VECTOR0_EVENT_RST;
3623 }
3624
3625 /* check for vector0 msix event and hardware error event source */
3626 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
3627 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
3628 return HCLGE_VECTOR0_EVENT_ERR;
3629
3630 /* check for vector0 ptp event source */
3631 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) {
3632 *clearval = msix_src_reg;
3633 return HCLGE_VECTOR0_EVENT_PTP;
3634 }
3635
3636 /* check for vector0 mailbox(=CMDQ RX) event source */
3637 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
3638 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
3639 *clearval = cmdq_src_reg;
3640 return HCLGE_VECTOR0_EVENT_MBX;
3641 }
3642
3643 /* print other vector0 event source */
3644 dev_info(&hdev->pdev->dev,
3645 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",
3646 cmdq_src_reg, hw_err_src_reg, msix_src_reg);
3647
3648 return HCLGE_VECTOR0_EVENT_OTHER;
3649 }
3650
hclge_clear_event_cause(struct hclge_dev * hdev,u32 event_type,u32 regclr)3651 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
3652 u32 regclr)
3653 {
3654 #define HCLGE_IMP_RESET_DELAY 5
3655
3656 switch (event_type) {
3657 case HCLGE_VECTOR0_EVENT_PTP:
3658 case HCLGE_VECTOR0_EVENT_RST:
3659 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
3660 mdelay(HCLGE_IMP_RESET_DELAY);
3661
3662 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
3663 break;
3664 case HCLGE_VECTOR0_EVENT_MBX:
3665 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
3666 break;
3667 default:
3668 break;
3669 }
3670 }
3671
hclge_clear_all_event_cause(struct hclge_dev * hdev)3672 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
3673 {
3674 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
3675 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
3676 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
3677 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
3678 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
3679 }
3680
hclge_enable_vector(struct hclge_misc_vector * vector,bool enable)3681 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
3682 {
3683 writel(enable ? 1 : 0, vector->addr);
3684 }
3685
hclge_misc_irq_handle(int irq,void * data)3686 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
3687 {
3688 struct hclge_dev *hdev = data;
3689 unsigned long flags;
3690 u32 clearval = 0;
3691 u32 event_cause;
3692
3693 hclge_enable_vector(&hdev->misc_vector, false);
3694 event_cause = hclge_check_event_cause(hdev, &clearval);
3695
3696 /* vector 0 interrupt is shared with reset and mailbox source events. */
3697 switch (event_cause) {
3698 case HCLGE_VECTOR0_EVENT_ERR:
3699 hclge_errhand_task_schedule(hdev);
3700 break;
3701 case HCLGE_VECTOR0_EVENT_RST:
3702 hclge_reset_task_schedule(hdev);
3703 break;
3704 case HCLGE_VECTOR0_EVENT_PTP:
3705 spin_lock_irqsave(&hdev->ptp->lock, flags);
3706 hclge_ptp_clean_tx_hwts(hdev);
3707 spin_unlock_irqrestore(&hdev->ptp->lock, flags);
3708 break;
3709 case HCLGE_VECTOR0_EVENT_MBX:
3710 /* If we are here then,
3711 * 1. Either we are not handling any mbx task and we are not
3712 * scheduled as well
3713 * OR
3714 * 2. We could be handling a mbx task but nothing more is
3715 * scheduled.
3716 * In both cases, we should schedule mbx task as there are more
3717 * mbx messages reported by this interrupt.
3718 */
3719 hclge_mbx_task_schedule(hdev);
3720 break;
3721 default:
3722 dev_warn(&hdev->pdev->dev,
3723 "received unknown or unhandled event of vector0\n");
3724 break;
3725 }
3726
3727 hclge_clear_event_cause(hdev, event_cause, clearval);
3728
3729 /* Enable interrupt if it is not caused by reset event or error event */
3730 if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
3731 event_cause == HCLGE_VECTOR0_EVENT_MBX ||
3732 event_cause == HCLGE_VECTOR0_EVENT_OTHER)
3733 hclge_enable_vector(&hdev->misc_vector, true);
3734
3735 return IRQ_HANDLED;
3736 }
3737
hclge_free_vector(struct hclge_dev * hdev,int vector_id)3738 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
3739 {
3740 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
3741 dev_warn(&hdev->pdev->dev,
3742 "vector(vector_id %d) has been freed.\n", vector_id);
3743 return;
3744 }
3745
3746 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
3747 hdev->num_msi_left += 1;
3748 hdev->num_msi_used -= 1;
3749 }
3750
hclge_get_misc_vector(struct hclge_dev * hdev)3751 static void hclge_get_misc_vector(struct hclge_dev *hdev)
3752 {
3753 struct hclge_misc_vector *vector = &hdev->misc_vector;
3754
3755 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
3756
3757 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
3758 hdev->vector_status[0] = 0;
3759
3760 hdev->num_msi_left -= 1;
3761 hdev->num_msi_used += 1;
3762 }
3763
hclge_misc_irq_init(struct hclge_dev * hdev)3764 static int hclge_misc_irq_init(struct hclge_dev *hdev)
3765 {
3766 int ret;
3767
3768 hclge_get_misc_vector(hdev);
3769
3770 /* this would be explicitly freed in the end */
3771 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
3772 HCLGE_NAME, pci_name(hdev->pdev));
3773 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
3774 IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev);
3775 if (ret) {
3776 hclge_free_vector(hdev, 0);
3777 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
3778 hdev->misc_vector.vector_irq);
3779 }
3780
3781 return ret;
3782 }
3783
hclge_misc_irq_uninit(struct hclge_dev * hdev)3784 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
3785 {
3786 free_irq(hdev->misc_vector.vector_irq, hdev);
3787 hclge_free_vector(hdev, 0);
3788 }
3789
hclge_notify_client(struct hclge_dev * hdev,enum hnae3_reset_notify_type type)3790 int hclge_notify_client(struct hclge_dev *hdev,
3791 enum hnae3_reset_notify_type type)
3792 {
3793 struct hnae3_handle *handle = &hdev->vport[0].nic;
3794 struct hnae3_client *client = hdev->nic_client;
3795 int ret;
3796
3797 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client)
3798 return 0;
3799
3800 if (!client->ops->reset_notify)
3801 return -EOPNOTSUPP;
3802
3803 ret = client->ops->reset_notify(handle, type);
3804 if (ret)
3805 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
3806 type, ret);
3807
3808 return ret;
3809 }
3810
hclge_notify_roce_client(struct hclge_dev * hdev,enum hnae3_reset_notify_type type)3811 static int hclge_notify_roce_client(struct hclge_dev *hdev,
3812 enum hnae3_reset_notify_type type)
3813 {
3814 struct hnae3_handle *handle = &hdev->vport[0].roce;
3815 struct hnae3_client *client = hdev->roce_client;
3816 int ret;
3817
3818 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client)
3819 return 0;
3820
3821 if (!client->ops->reset_notify)
3822 return -EOPNOTSUPP;
3823
3824 ret = client->ops->reset_notify(handle, type);
3825 if (ret)
3826 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
3827 type, ret);
3828
3829 return ret;
3830 }
3831
hclge_reset_wait(struct hclge_dev * hdev)3832 static int hclge_reset_wait(struct hclge_dev *hdev)
3833 {
3834 #define HCLGE_RESET_WATI_MS 100
3835 #define HCLGE_RESET_WAIT_CNT 350
3836
3837 u32 val, reg, reg_bit;
3838 u32 cnt = 0;
3839
3840 switch (hdev->reset_type) {
3841 case HNAE3_IMP_RESET:
3842 reg = HCLGE_GLOBAL_RESET_REG;
3843 reg_bit = HCLGE_IMP_RESET_BIT;
3844 break;
3845 case HNAE3_GLOBAL_RESET:
3846 reg = HCLGE_GLOBAL_RESET_REG;
3847 reg_bit = HCLGE_GLOBAL_RESET_BIT;
3848 break;
3849 case HNAE3_FUNC_RESET:
3850 reg = HCLGE_FUN_RST_ING;
3851 reg_bit = HCLGE_FUN_RST_ING_B;
3852 break;
3853 default:
3854 dev_err(&hdev->pdev->dev,
3855 "Wait for unsupported reset type: %d\n",
3856 hdev->reset_type);
3857 return -EINVAL;
3858 }
3859
3860 val = hclge_read_dev(&hdev->hw, reg);
3861 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
3862 msleep(HCLGE_RESET_WATI_MS);
3863 val = hclge_read_dev(&hdev->hw, reg);
3864 cnt++;
3865 }
3866
3867 if (cnt >= HCLGE_RESET_WAIT_CNT) {
3868 dev_warn(&hdev->pdev->dev,
3869 "Wait for reset timeout: %d\n", hdev->reset_type);
3870 return -EBUSY;
3871 }
3872
3873 return 0;
3874 }
3875
hclge_set_vf_rst(struct hclge_dev * hdev,int func_id,bool reset)3876 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
3877 {
3878 struct hclge_vf_rst_cmd *req;
3879 struct hclge_desc desc;
3880
3881 req = (struct hclge_vf_rst_cmd *)desc.data;
3882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
3883 req->dest_vfid = func_id;
3884
3885 if (reset)
3886 req->vf_rst = 0x1;
3887
3888 return hclge_cmd_send(&hdev->hw, &desc, 1);
3889 }
3890
hclge_set_all_vf_rst(struct hclge_dev * hdev,bool reset)3891 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
3892 {
3893 int i;
3894
3895 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) {
3896 struct hclge_vport *vport = &hdev->vport[i];
3897 int ret;
3898
3899 /* Send cmd to set/clear VF's FUNC_RST_ING */
3900 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
3901 if (ret) {
3902 dev_err(&hdev->pdev->dev,
3903 "set vf(%u) rst failed %d!\n",
3904 vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3905 ret);
3906 return ret;
3907 }
3908
3909 if (!reset ||
3910 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state))
3911 continue;
3912
3913 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) &&
3914 hdev->reset_type == HNAE3_FUNC_RESET) {
3915 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET,
3916 &vport->need_notify);
3917 continue;
3918 }
3919
3920 /* Inform VF to process the reset.
3921 * hclge_inform_reset_assert_to_vf may fail if VF
3922 * driver is not loaded.
3923 */
3924 ret = hclge_inform_reset_assert_to_vf(vport);
3925 if (ret)
3926 dev_warn(&hdev->pdev->dev,
3927 "inform reset to vf(%u) failed %d!\n",
3928 vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3929 ret);
3930 }
3931
3932 return 0;
3933 }
3934
hclge_mailbox_service_task(struct hclge_dev * hdev)3935 static void hclge_mailbox_service_task(struct hclge_dev *hdev)
3936 {
3937 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) ||
3938 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) ||
3939 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3940 return;
3941
3942 if (time_is_before_jiffies(hdev->last_mbx_scheduled +
3943 HCLGE_MBX_SCHED_TIMEOUT))
3944 dev_warn(&hdev->pdev->dev,
3945 "mbx service task is scheduled after %ums on cpu%u!\n",
3946 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
3947 smp_processor_id());
3948
3949 hclge_mbx_handler(hdev);
3950
3951 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3952 }
3953
hclge_func_reset_sync_vf(struct hclge_dev * hdev)3954 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
3955 {
3956 struct hclge_pf_rst_sync_cmd *req;
3957 struct hclge_desc desc;
3958 int cnt = 0;
3959 int ret;
3960
3961 req = (struct hclge_pf_rst_sync_cmd *)desc.data;
3962 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true);
3963
3964 do {
3965 /* vf need to down netdev by mbx during PF or FLR reset */
3966 hclge_mailbox_service_task(hdev);
3967
3968 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3969 /* for compatible with old firmware, wait
3970 * 100 ms for VF to stop IO
3971 */
3972 if (ret == -EOPNOTSUPP) {
3973 msleep(HCLGE_RESET_SYNC_TIME);
3974 return;
3975 } else if (ret) {
3976 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
3977 ret);
3978 return;
3979 } else if (req->all_vf_ready) {
3980 return;
3981 }
3982 msleep(HCLGE_PF_RESET_SYNC_TIME);
3983 hclge_comm_cmd_reuse_desc(&desc, true);
3984 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
3985
3986 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
3987 }
3988
hclge_report_hw_error(struct hclge_dev * hdev,enum hnae3_hw_error_type type)3989 void hclge_report_hw_error(struct hclge_dev *hdev,
3990 enum hnae3_hw_error_type type)
3991 {
3992 struct hnae3_client *client = hdev->nic_client;
3993
3994 if (!client || !client->ops->process_hw_error ||
3995 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
3996 return;
3997
3998 client->ops->process_hw_error(&hdev->vport[0].nic, type);
3999 }
4000
hclge_handle_imp_error(struct hclge_dev * hdev)4001 static void hclge_handle_imp_error(struct hclge_dev *hdev)
4002 {
4003 u32 reg_val;
4004
4005 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4006 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) {
4007 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR);
4008 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B);
4009 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
4010 }
4011
4012 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) {
4013 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR);
4014 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B);
4015 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
4016 }
4017 }
4018
hclge_func_reset_cmd(struct hclge_dev * hdev,int func_id)4019 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4020 {
4021 struct hclge_desc desc;
4022 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
4023 int ret;
4024
4025 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
4026 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4027 req->fun_reset_vfid = func_id;
4028
4029 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4030 if (ret)
4031 dev_err(&hdev->pdev->dev,
4032 "send function reset cmd fail, status =%d\n", ret);
4033
4034 return ret;
4035 }
4036
hclge_do_reset(struct hclge_dev * hdev)4037 static void hclge_do_reset(struct hclge_dev *hdev)
4038 {
4039 struct hnae3_handle *handle = &hdev->vport[0].nic;
4040 struct pci_dev *pdev = hdev->pdev;
4041 u32 val;
4042
4043 if (hclge_get_hw_reset_stat(handle)) {
4044 dev_info(&pdev->dev, "hardware reset not finish\n");
4045 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n",
4046 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING),
4047 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
4048 return;
4049 }
4050
4051 switch (hdev->reset_type) {
4052 case HNAE3_IMP_RESET:
4053 dev_info(&pdev->dev, "IMP reset requested\n");
4054 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4055 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1);
4056 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val);
4057 break;
4058 case HNAE3_GLOBAL_RESET:
4059 dev_info(&pdev->dev, "global reset requested\n");
4060 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
4061 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4062 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
4063 break;
4064 case HNAE3_FUNC_RESET:
4065 dev_info(&pdev->dev, "PF reset requested\n");
4066 /* schedule again to check later */
4067 hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET);
4068 hclge_reset_task_schedule(hdev);
4069 break;
4070 default:
4071 dev_warn(&pdev->dev,
4072 "unsupported reset type: %d\n", hdev->reset_type);
4073 break;
4074 }
4075 }
4076
hclge_get_reset_level(struct hnae3_ae_dev * ae_dev,unsigned long * addr)4077 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
4078 unsigned long *addr)
4079 {
4080 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
4081 struct hclge_dev *hdev = ae_dev->priv;
4082
4083 /* return the highest priority reset level amongst all */
4084 if (test_bit(HNAE3_IMP_RESET, addr)) {
4085 rst_level = HNAE3_IMP_RESET;
4086 clear_bit(HNAE3_IMP_RESET, addr);
4087 clear_bit(HNAE3_GLOBAL_RESET, addr);
4088 clear_bit(HNAE3_FUNC_RESET, addr);
4089 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
4090 rst_level = HNAE3_GLOBAL_RESET;
4091 clear_bit(HNAE3_GLOBAL_RESET, addr);
4092 clear_bit(HNAE3_FUNC_RESET, addr);
4093 } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
4094 rst_level = HNAE3_FUNC_RESET;
4095 clear_bit(HNAE3_FUNC_RESET, addr);
4096 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
4097 rst_level = HNAE3_FLR_RESET;
4098 clear_bit(HNAE3_FLR_RESET, addr);
4099 }
4100
4101 clear_bit(HNAE3_NONE_RESET, addr);
4102
4103 if (hdev->reset_type != HNAE3_NONE_RESET &&
4104 rst_level < hdev->reset_type)
4105 return HNAE3_NONE_RESET;
4106
4107 return rst_level;
4108 }
4109
hclge_clear_reset_cause(struct hclge_dev * hdev)4110 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
4111 {
4112 u32 clearval = 0;
4113
4114 switch (hdev->reset_type) {
4115 case HNAE3_IMP_RESET:
4116 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
4117 break;
4118 case HNAE3_GLOBAL_RESET:
4119 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
4120 break;
4121 default:
4122 break;
4123 }
4124
4125 if (!clearval)
4126 return;
4127
4128 /* For revision 0x20, the reset interrupt source
4129 * can only be cleared after hardware reset done
4130 */
4131 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
4132 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
4133 clearval);
4134
4135 hclge_enable_vector(&hdev->misc_vector, true);
4136 }
4137
hclge_reset_handshake(struct hclge_dev * hdev,bool enable)4138 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
4139 {
4140 u32 reg_val;
4141
4142 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
4143 if (enable)
4144 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
4145 else
4146 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
4147
4148 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
4149 }
4150
hclge_func_reset_notify_vf(struct hclge_dev * hdev)4151 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
4152 {
4153 int ret;
4154
4155 ret = hclge_set_all_vf_rst(hdev, true);
4156 if (ret)
4157 return ret;
4158
4159 hclge_func_reset_sync_vf(hdev);
4160
4161 return 0;
4162 }
4163
hclge_reset_prepare_wait(struct hclge_dev * hdev)4164 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
4165 {
4166 u32 reg_val;
4167 int ret = 0;
4168
4169 switch (hdev->reset_type) {
4170 case HNAE3_FUNC_RESET:
4171 ret = hclge_func_reset_notify_vf(hdev);
4172 if (ret)
4173 return ret;
4174
4175 ret = hclge_func_reset_cmd(hdev, 0);
4176 if (ret) {
4177 dev_err(&hdev->pdev->dev,
4178 "asserting function reset fail %d!\n", ret);
4179 return ret;
4180 }
4181
4182 /* After performaning pf reset, it is not necessary to do the
4183 * mailbox handling or send any command to firmware, because
4184 * any mailbox handling or command to firmware is only valid
4185 * after hclge_comm_cmd_init is called.
4186 */
4187 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
4188 hdev->rst_stats.pf_rst_cnt++;
4189 break;
4190 case HNAE3_FLR_RESET:
4191 ret = hclge_func_reset_notify_vf(hdev);
4192 if (ret)
4193 return ret;
4194 break;
4195 case HNAE3_IMP_RESET:
4196 hclge_handle_imp_error(hdev);
4197 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4198 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
4199 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
4200 break;
4201 default:
4202 break;
4203 }
4204
4205 /* inform hardware that preparatory work is done */
4206 msleep(HCLGE_RESET_SYNC_TIME);
4207 hclge_reset_handshake(hdev, true);
4208 dev_info(&hdev->pdev->dev, "prepare wait ok\n");
4209
4210 return ret;
4211 }
4212
hclge_show_rst_info(struct hclge_dev * hdev)4213 static void hclge_show_rst_info(struct hclge_dev *hdev)
4214 {
4215 char *buf;
4216
4217 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL);
4218 if (!buf)
4219 return;
4220
4221 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN);
4222
4223 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf);
4224
4225 kfree(buf);
4226 }
4227
hclge_reset_err_handle(struct hclge_dev * hdev)4228 static bool hclge_reset_err_handle(struct hclge_dev *hdev)
4229 {
4230 #define MAX_RESET_FAIL_CNT 5
4231
4232 if (hdev->reset_pending) {
4233 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
4234 hdev->reset_pending);
4235 return true;
4236 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
4237 HCLGE_RESET_INT_M) {
4238 dev_info(&hdev->pdev->dev,
4239 "reset failed because new reset interrupt\n");
4240 hclge_clear_reset_cause(hdev);
4241 return false;
4242 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
4243 hdev->rst_stats.reset_fail_cnt++;
4244 hclge_set_reset_pending(hdev, hdev->reset_type);
4245 dev_info(&hdev->pdev->dev,
4246 "re-schedule reset task(%u)\n",
4247 hdev->rst_stats.reset_fail_cnt);
4248 return true;
4249 }
4250
4251 hclge_clear_reset_cause(hdev);
4252
4253 /* recover the handshake status when reset fail */
4254 hclge_reset_handshake(hdev, true);
4255
4256 dev_err(&hdev->pdev->dev, "Reset fail!\n");
4257
4258 hclge_show_rst_info(hdev);
4259
4260 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4261
4262 return false;
4263 }
4264
hclge_update_reset_level(struct hclge_dev * hdev)4265 static void hclge_update_reset_level(struct hclge_dev *hdev)
4266 {
4267 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4268 enum hnae3_reset_type reset_level;
4269
4270 /* reset request will not be set during reset, so clear
4271 * pending reset request to avoid unnecessary reset
4272 * caused by the same reason.
4273 */
4274 hclge_get_reset_level(ae_dev, &hdev->reset_request);
4275
4276 /* if default_reset_request has a higher level reset request,
4277 * it should be handled as soon as possible. since some errors
4278 * need this kind of reset to fix.
4279 */
4280 reset_level = hclge_get_reset_level(ae_dev,
4281 &hdev->default_reset_request);
4282 if (reset_level != HNAE3_NONE_RESET)
4283 set_bit(reset_level, &hdev->reset_request);
4284 }
4285
hclge_set_rst_done(struct hclge_dev * hdev)4286 static int hclge_set_rst_done(struct hclge_dev *hdev)
4287 {
4288 struct hclge_pf_rst_done_cmd *req;
4289 struct hclge_desc desc;
4290 int ret;
4291
4292 req = (struct hclge_pf_rst_done_cmd *)desc.data;
4293 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false);
4294 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT;
4295
4296 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4297 /* To be compatible with the old firmware, which does not support
4298 * command HCLGE_OPC_PF_RST_DONE, just print a warning and
4299 * return success
4300 */
4301 if (ret == -EOPNOTSUPP) {
4302 dev_warn(&hdev->pdev->dev,
4303 "current firmware does not support command(0x%x)!\n",
4304 HCLGE_OPC_PF_RST_DONE);
4305 return 0;
4306 } else if (ret) {
4307 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n",
4308 ret);
4309 }
4310
4311 return ret;
4312 }
4313
hclge_reset_prepare_up(struct hclge_dev * hdev)4314 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
4315 {
4316 int ret = 0;
4317
4318 switch (hdev->reset_type) {
4319 case HNAE3_FUNC_RESET:
4320 case HNAE3_FLR_RESET:
4321 ret = hclge_set_all_vf_rst(hdev, false);
4322 break;
4323 case HNAE3_GLOBAL_RESET:
4324 case HNAE3_IMP_RESET:
4325 ret = hclge_set_rst_done(hdev);
4326 break;
4327 default:
4328 break;
4329 }
4330
4331 /* clear up the handshake status after re-initialize done */
4332 hclge_reset_handshake(hdev, false);
4333
4334 return ret;
4335 }
4336
hclge_reset_stack(struct hclge_dev * hdev)4337 static int hclge_reset_stack(struct hclge_dev *hdev)
4338 {
4339 int ret;
4340
4341 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
4342 if (ret)
4343 return ret;
4344
4345 ret = hclge_reset_ae_dev(hdev->ae_dev);
4346 if (ret)
4347 return ret;
4348
4349 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
4350 }
4351
hclge_reset_prepare(struct hclge_dev * hdev)4352 static int hclge_reset_prepare(struct hclge_dev *hdev)
4353 {
4354 int ret;
4355
4356 hdev->rst_stats.reset_cnt++;
4357 /* perform reset of the stack & ae device for a client */
4358 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
4359 if (ret)
4360 return ret;
4361
4362 rtnl_lock();
4363 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
4364 rtnl_unlock();
4365 if (ret)
4366 return ret;
4367
4368 return hclge_reset_prepare_wait(hdev);
4369 }
4370
hclge_reset_rebuild(struct hclge_dev * hdev)4371 static int hclge_reset_rebuild(struct hclge_dev *hdev)
4372 {
4373 int ret;
4374
4375 hdev->rst_stats.hw_reset_done_cnt++;
4376
4377 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
4378 if (ret)
4379 return ret;
4380
4381 rtnl_lock();
4382 ret = hclge_reset_stack(hdev);
4383 rtnl_unlock();
4384 if (ret)
4385 return ret;
4386
4387 hclge_clear_reset_cause(hdev);
4388
4389 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
4390 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
4391 * times
4392 */
4393 if (ret &&
4394 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
4395 return ret;
4396
4397 ret = hclge_reset_prepare_up(hdev);
4398 if (ret)
4399 return ret;
4400
4401 rtnl_lock();
4402 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
4403 rtnl_unlock();
4404 if (ret)
4405 return ret;
4406
4407 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
4408 if (ret)
4409 return ret;
4410
4411 hdev->last_reset_time = jiffies;
4412 hdev->rst_stats.reset_fail_cnt = 0;
4413 hdev->rst_stats.reset_done_cnt++;
4414 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4415
4416 hclge_update_reset_level(hdev);
4417
4418 return 0;
4419 }
4420
hclge_reset(struct hclge_dev * hdev)4421 static void hclge_reset(struct hclge_dev *hdev)
4422 {
4423 if (hclge_reset_prepare(hdev))
4424 goto err_reset;
4425
4426 if (hclge_reset_wait(hdev))
4427 goto err_reset;
4428
4429 if (hclge_reset_rebuild(hdev))
4430 goto err_reset;
4431
4432 return;
4433
4434 err_reset:
4435 if (hclge_reset_err_handle(hdev))
4436 hclge_reset_task_schedule(hdev);
4437 }
4438
hclge_reset_event(struct pci_dev * pdev,struct hnae3_handle * handle)4439 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
4440 {
4441 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4442 struct hclge_dev *hdev = ae_dev->priv;
4443
4444 /* We might end up getting called broadly because of 2 below cases:
4445 * 1. Recoverable error was conveyed through APEI and only way to bring
4446 * normalcy is to reset.
4447 * 2. A new reset request from the stack due to timeout
4448 *
4449 * check if this is a new reset request and we are not here just because
4450 * last reset attempt did not succeed and watchdog hit us again. We will
4451 * know this if last reset request did not occur very recently (watchdog
4452 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
4453 * In case of new request we reset the "reset level" to PF reset.
4454 * And if it is a repeat reset request of the most recent one then we
4455 * want to make sure we throttle the reset request. Therefore, we will
4456 * not allow it again before 3*HZ times.
4457 */
4458
4459 if (time_before(jiffies, (hdev->last_reset_time +
4460 HCLGE_RESET_INTERVAL))) {
4461 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
4462 return;
4463 }
4464
4465 if (hdev->default_reset_request) {
4466 hdev->reset_level =
4467 hclge_get_reset_level(ae_dev,
4468 &hdev->default_reset_request);
4469 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) {
4470 hdev->reset_level = HNAE3_FUNC_RESET;
4471 }
4472
4473 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n",
4474 hdev->reset_level);
4475
4476 /* request reset & schedule reset task */
4477 set_bit(hdev->reset_level, &hdev->reset_request);
4478 hclge_reset_task_schedule(hdev);
4479
4480 if (hdev->reset_level < HNAE3_GLOBAL_RESET)
4481 hdev->reset_level++;
4482 }
4483
hclge_set_def_reset_request(struct hnae3_ae_dev * ae_dev,enum hnae3_reset_type rst_type)4484 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
4485 enum hnae3_reset_type rst_type)
4486 {
4487 #define HCLGE_SUPPORT_RESET_TYPE \
4488 (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \
4489 BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET))
4490
4491 struct hclge_dev *hdev = ae_dev->priv;
4492
4493 if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) {
4494 /* To prevent reset triggered by hclge_reset_event */
4495 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
4496 dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n",
4497 rst_type);
4498 return;
4499 }
4500
4501 set_bit(rst_type, &hdev->default_reset_request);
4502 }
4503
hclge_reset_timer(struct timer_list * t)4504 static void hclge_reset_timer(struct timer_list *t)
4505 {
4506 struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer);
4507
4508 /* if default_reset_request has no value, it means that this reset
4509 * request has already be handled, so just return here
4510 */
4511 if (!hdev->default_reset_request)
4512 return;
4513
4514 dev_info(&hdev->pdev->dev,
4515 "triggering reset in reset timer\n");
4516 hclge_reset_event(hdev->pdev, NULL);
4517 }
4518
hclge_reset_subtask(struct hclge_dev * hdev)4519 static void hclge_reset_subtask(struct hclge_dev *hdev)
4520 {
4521 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4522
4523 /* check if there is any ongoing reset in the hardware. This status can
4524 * be checked from reset_pending. If there is then, we need to wait for
4525 * hardware to complete reset.
4526 * a. If we are able to figure out in reasonable time that hardware
4527 * has fully resetted then, we can proceed with driver, client
4528 * reset.
4529 * b. else, we can come back later to check this status so re-sched
4530 * now.
4531 */
4532 hdev->last_reset_time = jiffies;
4533 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
4534 if (hdev->reset_type != HNAE3_NONE_RESET)
4535 hclge_reset(hdev);
4536
4537 /* check if we got any *new* reset requests to be honored */
4538 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
4539 if (hdev->reset_type != HNAE3_NONE_RESET)
4540 hclge_do_reset(hdev);
4541
4542 hdev->reset_type = HNAE3_NONE_RESET;
4543 }
4544
hclge_handle_err_reset_request(struct hclge_dev * hdev)4545 static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
4546 {
4547 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4548 enum hnae3_reset_type reset_type;
4549
4550 if (ae_dev->hw_err_reset_req) {
4551 reset_type = hclge_get_reset_level(ae_dev,
4552 &ae_dev->hw_err_reset_req);
4553 hclge_set_def_reset_request(ae_dev, reset_type);
4554 }
4555
4556 if (hdev->default_reset_request && ae_dev->ops->reset_event)
4557 ae_dev->ops->reset_event(hdev->pdev, NULL);
4558
4559 /* enable interrupt after error handling complete */
4560 hclge_enable_vector(&hdev->misc_vector, true);
4561 }
4562
hclge_handle_err_recovery(struct hclge_dev * hdev)4563 static void hclge_handle_err_recovery(struct hclge_dev *hdev)
4564 {
4565 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4566
4567 ae_dev->hw_err_reset_req = 0;
4568
4569 if (hclge_find_error_source(hdev)) {
4570 hclge_handle_error_info_log(ae_dev);
4571 hclge_handle_mac_tnl(hdev);
4572 hclge_handle_vf_queue_err_ras(hdev);
4573 }
4574
4575 hclge_handle_err_reset_request(hdev);
4576 }
4577
hclge_misc_err_recovery(struct hclge_dev * hdev)4578 static void hclge_misc_err_recovery(struct hclge_dev *hdev)
4579 {
4580 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4581 struct device *dev = &hdev->pdev->dev;
4582 u32 msix_sts_reg;
4583
4584 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
4585 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
4586 if (hclge_handle_hw_msix_error
4587 (hdev, &hdev->default_reset_request))
4588 dev_info(dev, "received msix interrupt 0x%x\n",
4589 msix_sts_reg);
4590 }
4591
4592 hclge_handle_hw_ras_error(ae_dev);
4593
4594 hclge_handle_err_reset_request(hdev);
4595 }
4596
hclge_errhand_service_task(struct hclge_dev * hdev)4597 static void hclge_errhand_service_task(struct hclge_dev *hdev)
4598 {
4599 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
4600 return;
4601
4602 if (hnae3_dev_ras_imp_supported(hdev))
4603 hclge_handle_err_recovery(hdev);
4604 else
4605 hclge_misc_err_recovery(hdev);
4606 }
4607
hclge_reset_service_task(struct hclge_dev * hdev)4608 static void hclge_reset_service_task(struct hclge_dev *hdev)
4609 {
4610 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
4611 return;
4612
4613 if (time_is_before_jiffies(hdev->last_rst_scheduled +
4614 HCLGE_RESET_SCHED_TIMEOUT))
4615 dev_warn(&hdev->pdev->dev,
4616 "reset service task is scheduled after %ums on cpu%u!\n",
4617 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
4618 smp_processor_id());
4619
4620 down(&hdev->reset_sem);
4621 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4622
4623 hclge_reset_subtask(hdev);
4624
4625 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4626 up(&hdev->reset_sem);
4627 }
4628
hclge_update_vport_alive(struct hclge_dev * hdev)4629 static void hclge_update_vport_alive(struct hclge_dev *hdev)
4630 {
4631 #define HCLGE_ALIVE_SECONDS_NORMAL 8
4632
4633 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ;
4634 int i;
4635
4636 /* start from vport 1 for PF is always alive */
4637 for (i = 1; i < hdev->num_alloc_vport; i++) {
4638 struct hclge_vport *vport = &hdev->vport[i];
4639
4640 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) ||
4641 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
4642 continue;
4643 if (time_after(jiffies, vport->last_active_jiffies +
4644 alive_time)) {
4645 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
4646 dev_warn(&hdev->pdev->dev,
4647 "VF %u heartbeat timeout\n",
4648 i - HCLGE_VF_VPORT_START_NUM);
4649 }
4650 }
4651 }
4652
hclge_periodic_service_task(struct hclge_dev * hdev)4653 static void hclge_periodic_service_task(struct hclge_dev *hdev)
4654 {
4655 unsigned long delta = round_jiffies_relative(HZ);
4656
4657 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
4658 return;
4659
4660 /* Always handle the link updating to make sure link state is
4661 * updated when it is triggered by mbx.
4662 */
4663 hclge_update_link_status(hdev);
4664 hclge_sync_mac_table(hdev);
4665 hclge_sync_promisc_mode(hdev);
4666 hclge_sync_fd_table(hdev);
4667
4668 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
4669 delta = jiffies - hdev->last_serv_processed;
4670
4671 if (delta < round_jiffies_relative(HZ)) {
4672 delta = round_jiffies_relative(HZ) - delta;
4673 goto out;
4674 }
4675 }
4676
4677 hdev->serv_processed_cnt++;
4678 hclge_update_vport_alive(hdev);
4679
4680 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) {
4681 hdev->last_serv_processed = jiffies;
4682 goto out;
4683 }
4684
4685 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL))
4686 hclge_update_stats_for_all(hdev);
4687
4688 hclge_update_port_info(hdev);
4689 hclge_sync_vlan_filter(hdev);
4690
4691 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL))
4692 hclge_rfs_filter_expire(hdev);
4693
4694 hdev->last_serv_processed = jiffies;
4695
4696 out:
4697 hclge_task_schedule(hdev, delta);
4698 }
4699
hclge_ptp_service_task(struct hclge_dev * hdev)4700 static void hclge_ptp_service_task(struct hclge_dev *hdev)
4701 {
4702 unsigned long flags;
4703
4704 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) ||
4705 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) ||
4706 !time_is_before_jiffies(hdev->ptp->tx_start + HZ))
4707 return;
4708
4709 /* to prevent concurrence with the irq handler */
4710 spin_lock_irqsave(&hdev->ptp->lock, flags);
4711
4712 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
4713 * handler may handle it just before spin_lock_irqsave().
4714 */
4715 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
4716 hclge_ptp_clean_tx_hwts(hdev);
4717
4718 spin_unlock_irqrestore(&hdev->ptp->lock, flags);
4719 }
4720
hclge_service_task(struct work_struct * work)4721 static void hclge_service_task(struct work_struct *work)
4722 {
4723 struct hclge_dev *hdev =
4724 container_of(work, struct hclge_dev, service_task.work);
4725
4726 hclge_errhand_service_task(hdev);
4727 hclge_reset_service_task(hdev);
4728 hclge_ptp_service_task(hdev);
4729 hclge_mailbox_service_task(hdev);
4730 hclge_periodic_service_task(hdev);
4731
4732 /* Handle error recovery, reset and mbx again in case periodical task
4733 * delays the handling by calling hclge_task_schedule() in
4734 * hclge_periodic_service_task().
4735 */
4736 hclge_errhand_service_task(hdev);
4737 hclge_reset_service_task(hdev);
4738 hclge_mailbox_service_task(hdev);
4739 }
4740
hclge_get_vport(struct hnae3_handle * handle)4741 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
4742 {
4743 /* VF handle has no client */
4744 if (!handle->client)
4745 return container_of(handle, struct hclge_vport, nic);
4746 else if (handle->client->type == HNAE3_CLIENT_ROCE)
4747 return container_of(handle, struct hclge_vport, roce);
4748 else
4749 return container_of(handle, struct hclge_vport, nic);
4750 }
4751
hclge_get_vector_info(struct hclge_dev * hdev,u16 idx,struct hnae3_vector_info * vector_info)4752 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
4753 struct hnae3_vector_info *vector_info)
4754 {
4755 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64
4756
4757 vector_info->vector = pci_irq_vector(hdev->pdev, idx);
4758
4759 /* need an extend offset to config vector >= 64 */
4760 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
4761 vector_info->io_addr = hdev->hw.hw.io_base +
4762 HCLGE_VECTOR_REG_BASE +
4763 (idx - 1) * HCLGE_VECTOR_REG_OFFSET;
4764 else
4765 vector_info->io_addr = hdev->hw.hw.io_base +
4766 HCLGE_VECTOR_EXT_REG_BASE +
4767 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4768 HCLGE_VECTOR_REG_OFFSET_H +
4769 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4770 HCLGE_VECTOR_REG_OFFSET;
4771
4772 hdev->vector_status[idx] = hdev->vport[0].vport_id;
4773 hdev->vector_irq[idx] = vector_info->vector;
4774 }
4775
hclge_get_vector(struct hnae3_handle * handle,u16 vector_num,struct hnae3_vector_info * vector_info)4776 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
4777 struct hnae3_vector_info *vector_info)
4778 {
4779 struct hclge_vport *vport = hclge_get_vport(handle);
4780 struct hnae3_vector_info *vector = vector_info;
4781 struct hclge_dev *hdev = vport->back;
4782 int alloc = 0;
4783 u16 i = 0;
4784 u16 j;
4785
4786 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
4787 vector_num = min(hdev->num_msi_left, vector_num);
4788
4789 for (j = 0; j < vector_num; j++) {
4790 while (++i < hdev->num_nic_msi) {
4791 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
4792 hclge_get_vector_info(hdev, i, vector);
4793 vector++;
4794 alloc++;
4795
4796 break;
4797 }
4798 }
4799 }
4800 hdev->num_msi_left -= alloc;
4801 hdev->num_msi_used += alloc;
4802
4803 return alloc;
4804 }
4805
hclge_get_vector_index(struct hclge_dev * hdev,int vector)4806 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
4807 {
4808 int i;
4809
4810 for (i = 0; i < hdev->num_msi; i++)
4811 if (vector == hdev->vector_irq[i])
4812 return i;
4813
4814 return -EINVAL;
4815 }
4816
hclge_put_vector(struct hnae3_handle * handle,int vector)4817 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
4818 {
4819 struct hclge_vport *vport = hclge_get_vport(handle);
4820 struct hclge_dev *hdev = vport->back;
4821 int vector_id;
4822
4823 vector_id = hclge_get_vector_index(hdev, vector);
4824 if (vector_id < 0) {
4825 dev_err(&hdev->pdev->dev,
4826 "Get vector index fail. vector = %d\n", vector);
4827 return vector_id;
4828 }
4829
4830 hclge_free_vector(hdev, vector_id);
4831
4832 return 0;
4833 }
4834
hclge_get_rss(struct hnae3_handle * handle,u32 * indir,u8 * key,u8 * hfunc)4835 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
4836 u8 *key, u8 *hfunc)
4837 {
4838 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4839 struct hclge_vport *vport = hclge_get_vport(handle);
4840 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg;
4841
4842 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
4843
4844 hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
4845 ae_dev->dev_specs.rss_ind_tbl_size);
4846
4847 return 0;
4848 }
4849
hclge_set_rss(struct hnae3_handle * handle,const u32 * indir,const u8 * key,const u8 hfunc)4850 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
4851 const u8 *key, const u8 hfunc)
4852 {
4853 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4854 struct hclge_vport *vport = hclge_get_vport(handle);
4855 struct hclge_dev *hdev = vport->back;
4856 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
4857 int ret, i;
4858
4859 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc);
4860 if (ret) {
4861 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
4862 return ret;
4863 }
4864
4865 /* Update the shadow RSS table with user specified qids */
4866 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
4867 rss_cfg->rss_indirection_tbl[i] = indir[i];
4868
4869 /* Update the hardware */
4870 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw,
4871 rss_cfg->rss_indirection_tbl);
4872 }
4873
hclge_set_rss_tuple(struct hnae3_handle * handle,const struct ethtool_rxfh_fields * nfc)4874 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
4875 const struct ethtool_rxfh_fields *nfc)
4876 {
4877 struct hclge_vport *vport = hclge_get_vport(handle);
4878 struct hclge_dev *hdev = vport->back;
4879 int ret;
4880
4881 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
4882 &hdev->rss_cfg, nfc);
4883 if (ret) {
4884 dev_err(&hdev->pdev->dev,
4885 "failed to set rss tuple, ret = %d.\n", ret);
4886 return ret;
4887 }
4888
4889 return 0;
4890 }
4891
hclge_get_rss_tuple(struct hnae3_handle * handle,struct ethtool_rxfh_fields * nfc)4892 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
4893 struct ethtool_rxfh_fields *nfc)
4894 {
4895 struct hclge_vport *vport = hclge_get_vport(handle);
4896 u8 tuple_sets;
4897 int ret;
4898
4899 nfc->data = 0;
4900
4901 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type,
4902 &tuple_sets);
4903 if (ret || !tuple_sets)
4904 return ret;
4905
4906 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
4907
4908 return 0;
4909 }
4910
hclge_get_tc_size(struct hnae3_handle * handle)4911 static int hclge_get_tc_size(struct hnae3_handle *handle)
4912 {
4913 struct hclge_vport *vport = hclge_get_vport(handle);
4914 struct hclge_dev *hdev = vport->back;
4915
4916 return hdev->pf_rss_size_max;
4917 }
4918
hclge_init_rss_tc_mode(struct hclge_dev * hdev)4919 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev)
4920 {
4921 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
4922 struct hclge_vport *vport = hdev->vport;
4923 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
4924 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0};
4925 u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
4926 struct hnae3_tc_info *tc_info;
4927 u16 roundup_size;
4928 u16 rss_size;
4929 int i;
4930
4931 tc_info = &vport->nic.kinfo.tc_info;
4932 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
4933 rss_size = tc_info->tqp_count[i];
4934 tc_valid[i] = 0;
4935
4936 if (!(hdev->hw_tc_map & BIT(i)))
4937 continue;
4938
4939 /* tc_size set to hardware is the log2 of roundup power of two
4940 * of rss_size, the acutal queue size is limited by indirection
4941 * table.
4942 */
4943 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size ||
4944 rss_size == 0) {
4945 dev_err(&hdev->pdev->dev,
4946 "Configure rss tc size failed, invalid TC_SIZE = %u\n",
4947 rss_size);
4948 return -EINVAL;
4949 }
4950
4951 roundup_size = roundup_pow_of_two(rss_size);
4952 roundup_size = ilog2(roundup_size);
4953
4954 tc_valid[i] = 1;
4955 tc_size[i] = roundup_size;
4956 tc_offset[i] = tc_info->tqp_offset[i];
4957 }
4958
4959 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
4960 tc_size);
4961 }
4962
hclge_rss_init_hw(struct hclge_dev * hdev)4963 int hclge_rss_init_hw(struct hclge_dev *hdev)
4964 {
4965 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl;
4966 u8 *key = hdev->rss_cfg.rss_hash_key;
4967 u8 hfunc = hdev->rss_cfg.rss_algo;
4968 int ret;
4969
4970 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
4971 rss_indir);
4972 if (ret)
4973 return ret;
4974
4975 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key);
4976 if (ret)
4977 return ret;
4978
4979 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg);
4980 if (ret)
4981 return ret;
4982
4983 return hclge_init_rss_tc_mode(hdev);
4984 }
4985
hclge_bind_ring_with_vector(struct hclge_vport * vport,int vector_id,bool en,struct hnae3_ring_chain_node * ring_chain)4986 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
4987 int vector_id, bool en,
4988 struct hnae3_ring_chain_node *ring_chain)
4989 {
4990 struct hclge_dev *hdev = vport->back;
4991 struct hnae3_ring_chain_node *node;
4992 struct hclge_desc desc;
4993 struct hclge_ctrl_vector_chain_cmd *req =
4994 (struct hclge_ctrl_vector_chain_cmd *)desc.data;
4995 enum hclge_comm_cmd_status status;
4996 enum hclge_opcode_type op;
4997 u16 tqp_type_and_id;
4998 int i;
4999
5000 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
5001 hclge_cmd_setup_basic_desc(&desc, op, false);
5002 req->int_vector_id_l = hnae3_get_field(vector_id,
5003 HCLGE_VECTOR_ID_L_M,
5004 HCLGE_VECTOR_ID_L_S);
5005 req->int_vector_id_h = hnae3_get_field(vector_id,
5006 HCLGE_VECTOR_ID_H_M,
5007 HCLGE_VECTOR_ID_H_S);
5008
5009 i = 0;
5010 for (node = ring_chain; node; node = node->next) {
5011 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
5012 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
5013 HCLGE_INT_TYPE_S,
5014 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
5015 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
5016 HCLGE_TQP_ID_S, node->tqp_index);
5017 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
5018 HCLGE_INT_GL_IDX_S,
5019 hnae3_get_field(node->int_gl_idx,
5020 HNAE3_RING_GL_IDX_M,
5021 HNAE3_RING_GL_IDX_S));
5022 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
5023 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
5024 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
5025 req->vfid = vport->vport_id;
5026
5027 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5028 if (status) {
5029 dev_err(&hdev->pdev->dev,
5030 "Map TQP fail, status is %d.\n",
5031 status);
5032 return -EIO;
5033 }
5034 i = 0;
5035
5036 hclge_cmd_setup_basic_desc(&desc,
5037 op,
5038 false);
5039 req->int_vector_id_l =
5040 hnae3_get_field(vector_id,
5041 HCLGE_VECTOR_ID_L_M,
5042 HCLGE_VECTOR_ID_L_S);
5043 req->int_vector_id_h =
5044 hnae3_get_field(vector_id,
5045 HCLGE_VECTOR_ID_H_M,
5046 HCLGE_VECTOR_ID_H_S);
5047 }
5048 }
5049
5050 if (i > 0) {
5051 req->int_cause_num = i;
5052 req->vfid = vport->vport_id;
5053 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5054 if (status) {
5055 dev_err(&hdev->pdev->dev,
5056 "Map TQP fail, status is %d.\n", status);
5057 return -EIO;
5058 }
5059 }
5060
5061 return 0;
5062 }
5063
hclge_map_ring_to_vector(struct hnae3_handle * handle,int vector,struct hnae3_ring_chain_node * ring_chain)5064 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector,
5065 struct hnae3_ring_chain_node *ring_chain)
5066 {
5067 struct hclge_vport *vport = hclge_get_vport(handle);
5068 struct hclge_dev *hdev = vport->back;
5069 int vector_id;
5070
5071 vector_id = hclge_get_vector_index(hdev, vector);
5072 if (vector_id < 0) {
5073 dev_err(&hdev->pdev->dev,
5074 "failed to get vector index. vector=%d\n", vector);
5075 return vector_id;
5076 }
5077
5078 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
5079 }
5080
hclge_unmap_ring_frm_vector(struct hnae3_handle * handle,int vector,struct hnae3_ring_chain_node * ring_chain)5081 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector,
5082 struct hnae3_ring_chain_node *ring_chain)
5083 {
5084 struct hclge_vport *vport = hclge_get_vport(handle);
5085 struct hclge_dev *hdev = vport->back;
5086 int vector_id, ret;
5087
5088 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5089 return 0;
5090
5091 vector_id = hclge_get_vector_index(hdev, vector);
5092 if (vector_id < 0) {
5093 dev_err(&handle->pdev->dev,
5094 "Get vector index fail. ret =%d\n", vector_id);
5095 return vector_id;
5096 }
5097
5098 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
5099 if (ret)
5100 dev_err(&handle->pdev->dev,
5101 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
5102 vector_id, ret);
5103
5104 return ret;
5105 }
5106
hclge_cmd_set_promisc_mode(struct hclge_dev * hdev,u8 vf_id,bool en_uc,bool en_mc,bool en_bc)5107 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id,
5108 bool en_uc, bool en_mc, bool en_bc)
5109 {
5110 struct hclge_vport *vport = &hdev->vport[vf_id];
5111 struct hnae3_handle *handle = &vport->nic;
5112 struct hclge_promisc_cfg_cmd *req;
5113 struct hclge_desc desc;
5114 bool uc_tx_en = en_uc;
5115 u8 promisc_cfg = 0;
5116 int ret;
5117
5118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
5119
5120 req = (struct hclge_promisc_cfg_cmd *)desc.data;
5121 req->vf_id = vf_id;
5122
5123 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags))
5124 uc_tx_en = false;
5125
5126 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0);
5127 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0);
5128 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0);
5129 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0);
5130 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0);
5131 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0);
5132 req->extend_promisc = promisc_cfg;
5133
5134 /* to be compatible with DEVICE_VERSION_V1/2 */
5135 promisc_cfg = 0;
5136 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0);
5137 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0);
5138 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0);
5139 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1);
5140 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1);
5141 req->promisc = promisc_cfg;
5142
5143 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5144 if (ret)
5145 dev_err(&hdev->pdev->dev,
5146 "failed to set vport %u promisc mode, ret = %d.\n",
5147 vf_id, ret);
5148
5149 return ret;
5150 }
5151
hclge_set_vport_promisc_mode(struct hclge_vport * vport,bool en_uc_pmc,bool en_mc_pmc,bool en_bc_pmc)5152 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
5153 bool en_mc_pmc, bool en_bc_pmc)
5154 {
5155 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id,
5156 en_uc_pmc, en_mc_pmc, en_bc_pmc);
5157 }
5158
hclge_set_promisc_mode(struct hnae3_handle * handle,bool en_uc_pmc,bool en_mc_pmc)5159 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
5160 bool en_mc_pmc)
5161 {
5162 struct hclge_vport *vport = hclge_get_vport(handle);
5163 struct hclge_dev *hdev = vport->back;
5164 bool en_bc_pmc = true;
5165
5166 /* For device whose version below V2, if broadcast promisc enabled,
5167 * vlan filter is always bypassed. So broadcast promisc should be
5168 * disabled until user enable promisc mode
5169 */
5170 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
5171 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
5172
5173 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc,
5174 en_bc_pmc);
5175 }
5176
hclge_request_update_promisc_mode(struct hnae3_handle * handle)5177 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
5178 {
5179 struct hclge_vport *vport = hclge_get_vport(handle);
5180
5181 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
5182 }
5183
hclge_sync_fd_state(struct hclge_dev * hdev)5184 static void hclge_sync_fd_state(struct hclge_dev *hdev)
5185 {
5186 if (hlist_empty(&hdev->fd_rule_list))
5187 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
5188 }
5189
hclge_fd_inc_rule_cnt(struct hclge_dev * hdev,u16 location)5190 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location)
5191 {
5192 if (!test_bit(location, hdev->fd_bmap)) {
5193 set_bit(location, hdev->fd_bmap);
5194 hdev->hclge_fd_rule_num++;
5195 }
5196 }
5197
hclge_fd_dec_rule_cnt(struct hclge_dev * hdev,u16 location)5198 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location)
5199 {
5200 if (test_bit(location, hdev->fd_bmap)) {
5201 clear_bit(location, hdev->fd_bmap);
5202 hdev->hclge_fd_rule_num--;
5203 }
5204 }
5205
hclge_fd_free_node(struct hclge_dev * hdev,struct hclge_fd_rule * rule)5206 static void hclge_fd_free_node(struct hclge_dev *hdev,
5207 struct hclge_fd_rule *rule)
5208 {
5209 hlist_del(&rule->rule_node);
5210 kfree(rule);
5211 hclge_sync_fd_state(hdev);
5212 }
5213
hclge_update_fd_rule_node(struct hclge_dev * hdev,struct hclge_fd_rule * old_rule,struct hclge_fd_rule * new_rule,enum HCLGE_FD_NODE_STATE state)5214 static void hclge_update_fd_rule_node(struct hclge_dev *hdev,
5215 struct hclge_fd_rule *old_rule,
5216 struct hclge_fd_rule *new_rule,
5217 enum HCLGE_FD_NODE_STATE state)
5218 {
5219 switch (state) {
5220 case HCLGE_FD_TO_ADD:
5221 case HCLGE_FD_ACTIVE:
5222 /* 1) if the new state is TO_ADD, just replace the old rule
5223 * with the same location, no matter its state, because the
5224 * new rule will be configured to the hardware.
5225 * 2) if the new state is ACTIVE, it means the new rule
5226 * has been configured to the hardware, so just replace
5227 * the old rule node with the same location.
5228 * 3) for it doesn't add a new node to the list, so it's
5229 * unnecessary to update the rule number and fd_bmap.
5230 */
5231 new_rule->rule_node.next = old_rule->rule_node.next;
5232 new_rule->rule_node.pprev = old_rule->rule_node.pprev;
5233 memcpy(old_rule, new_rule, sizeof(*old_rule));
5234 kfree(new_rule);
5235 break;
5236 case HCLGE_FD_DELETED:
5237 hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5238 hclge_fd_free_node(hdev, old_rule);
5239 break;
5240 case HCLGE_FD_TO_DEL:
5241 /* if new request is TO_DEL, and old rule is existent
5242 * 1) the state of old rule is TO_DEL, we need do nothing,
5243 * because we delete rule by location, other rule content
5244 * is unncessary.
5245 * 2) the state of old rule is ACTIVE, we need to change its
5246 * state to TO_DEL, so the rule will be deleted when periodic
5247 * task being scheduled.
5248 * 3) the state of old rule is TO_ADD, it means the rule hasn't
5249 * been added to hardware, so we just delete the rule node from
5250 * fd_rule_list directly.
5251 */
5252 if (old_rule->state == HCLGE_FD_TO_ADD) {
5253 hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5254 hclge_fd_free_node(hdev, old_rule);
5255 return;
5256 }
5257 old_rule->state = HCLGE_FD_TO_DEL;
5258 break;
5259 }
5260 }
5261
hclge_find_fd_rule(struct hlist_head * hlist,u16 location,struct hclge_fd_rule ** parent)5262 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist,
5263 u16 location,
5264 struct hclge_fd_rule **parent)
5265 {
5266 struct hclge_fd_rule *rule;
5267 struct hlist_node *node;
5268
5269 hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
5270 if (rule->location == location)
5271 return rule;
5272 else if (rule->location > location)
5273 return NULL;
5274 /* record the parent node, use to keep the nodes in fd_rule_list
5275 * in ascend order.
5276 */
5277 *parent = rule;
5278 }
5279
5280 return NULL;
5281 }
5282
5283 /* insert fd rule node in ascend order according to rule->location */
hclge_fd_insert_rule_node(struct hlist_head * hlist,struct hclge_fd_rule * rule,struct hclge_fd_rule * parent)5284 static void hclge_fd_insert_rule_node(struct hlist_head *hlist,
5285 struct hclge_fd_rule *rule,
5286 struct hclge_fd_rule *parent)
5287 {
5288 INIT_HLIST_NODE(&rule->rule_node);
5289
5290 if (parent)
5291 hlist_add_behind(&rule->rule_node, &parent->rule_node);
5292 else
5293 hlist_add_head(&rule->rule_node, hlist);
5294 }
5295
hclge_fd_set_user_def_cmd(struct hclge_dev * hdev,struct hclge_fd_user_def_cfg * cfg)5296 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev,
5297 struct hclge_fd_user_def_cfg *cfg)
5298 {
5299 struct hclge_fd_user_def_cfg_cmd *req;
5300 struct hclge_desc desc;
5301 u16 data = 0;
5302 int ret;
5303
5304 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false);
5305
5306 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data;
5307
5308 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0);
5309 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5310 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset);
5311 req->ol2_cfg = cpu_to_le16(data);
5312
5313 data = 0;
5314 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0);
5315 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5316 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset);
5317 req->ol3_cfg = cpu_to_le16(data);
5318
5319 data = 0;
5320 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0);
5321 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5322 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset);
5323 req->ol4_cfg = cpu_to_le16(data);
5324
5325 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5326 if (ret)
5327 dev_err(&hdev->pdev->dev,
5328 "failed to set fd user def data, ret= %d\n", ret);
5329 return ret;
5330 }
5331
hclge_sync_fd_user_def_cfg(struct hclge_dev * hdev,bool locked)5332 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked)
5333 {
5334 int ret;
5335
5336 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state))
5337 return;
5338
5339 if (!locked)
5340 spin_lock_bh(&hdev->fd_rule_lock);
5341
5342 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg);
5343 if (ret)
5344 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5345
5346 if (!locked)
5347 spin_unlock_bh(&hdev->fd_rule_lock);
5348 }
5349
hclge_fd_check_user_def_refcnt(struct hclge_dev * hdev,struct hclge_fd_rule * rule)5350 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev,
5351 struct hclge_fd_rule *rule)
5352 {
5353 struct hlist_head *hlist = &hdev->fd_rule_list;
5354 struct hclge_fd_rule *fd_rule, *parent = NULL;
5355 struct hclge_fd_user_def_info *info, *old_info;
5356 struct hclge_fd_user_def_cfg *cfg;
5357
5358 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5359 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5360 return 0;
5361
5362 /* for valid layer is start from 1, so need minus 1 to get the cfg */
5363 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5364 info = &rule->ep.user_def;
5365
5366 if (!cfg->ref_cnt || cfg->offset == info->offset)
5367 return 0;
5368
5369 if (cfg->ref_cnt > 1)
5370 goto error;
5371
5372 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent);
5373 if (fd_rule) {
5374 old_info = &fd_rule->ep.user_def;
5375 if (info->layer == old_info->layer)
5376 return 0;
5377 }
5378
5379 error:
5380 dev_err(&hdev->pdev->dev,
5381 "No available offset for layer%d fd rule, each layer only support one user def offset.\n",
5382 info->layer + 1);
5383 return -ENOSPC;
5384 }
5385
hclge_fd_inc_user_def_refcnt(struct hclge_dev * hdev,struct hclge_fd_rule * rule)5386 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev,
5387 struct hclge_fd_rule *rule)
5388 {
5389 struct hclge_fd_user_def_cfg *cfg;
5390
5391 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5392 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5393 return;
5394
5395 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5396 if (!cfg->ref_cnt) {
5397 cfg->offset = rule->ep.user_def.offset;
5398 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5399 }
5400 cfg->ref_cnt++;
5401 }
5402
hclge_fd_dec_user_def_refcnt(struct hclge_dev * hdev,struct hclge_fd_rule * rule)5403 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev,
5404 struct hclge_fd_rule *rule)
5405 {
5406 struct hclge_fd_user_def_cfg *cfg;
5407
5408 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5409 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5410 return;
5411
5412 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5413 if (!cfg->ref_cnt)
5414 return;
5415
5416 cfg->ref_cnt--;
5417 if (!cfg->ref_cnt) {
5418 cfg->offset = 0;
5419 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5420 }
5421 }
5422
hclge_update_fd_list(struct hclge_dev * hdev,enum HCLGE_FD_NODE_STATE state,u16 location,struct hclge_fd_rule * new_rule)5423 static void hclge_update_fd_list(struct hclge_dev *hdev,
5424 enum HCLGE_FD_NODE_STATE state, u16 location,
5425 struct hclge_fd_rule *new_rule)
5426 {
5427 struct hlist_head *hlist = &hdev->fd_rule_list;
5428 struct hclge_fd_rule *fd_rule, *parent = NULL;
5429
5430 fd_rule = hclge_find_fd_rule(hlist, location, &parent);
5431 if (fd_rule) {
5432 hclge_fd_dec_user_def_refcnt(hdev, fd_rule);
5433 if (state == HCLGE_FD_ACTIVE)
5434 hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5435 hclge_sync_fd_user_def_cfg(hdev, true);
5436
5437 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state);
5438 return;
5439 }
5440
5441 /* it's unlikely to fail here, because we have checked the rule
5442 * exist before.
5443 */
5444 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) {
5445 dev_warn(&hdev->pdev->dev,
5446 "failed to delete fd rule %u, it's inexistent\n",
5447 location);
5448 return;
5449 }
5450
5451 hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5452 hclge_sync_fd_user_def_cfg(hdev, true);
5453
5454 hclge_fd_insert_rule_node(hlist, new_rule, parent);
5455 hclge_fd_inc_rule_cnt(hdev, new_rule->location);
5456
5457 if (state == HCLGE_FD_TO_ADD) {
5458 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
5459 hclge_task_schedule(hdev, 0);
5460 }
5461 }
5462
hclge_get_fd_mode(struct hclge_dev * hdev,u8 * fd_mode)5463 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
5464 {
5465 struct hclge_get_fd_mode_cmd *req;
5466 struct hclge_desc desc;
5467 int ret;
5468
5469 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
5470
5471 req = (struct hclge_get_fd_mode_cmd *)desc.data;
5472
5473 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5474 if (ret) {
5475 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
5476 return ret;
5477 }
5478
5479 *fd_mode = req->mode;
5480
5481 return ret;
5482 }
5483
hclge_get_fd_allocation(struct hclge_dev * hdev,u32 * stage1_entry_num,u32 * stage2_entry_num,u16 * stage1_counter_num,u16 * stage2_counter_num)5484 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
5485 u32 *stage1_entry_num,
5486 u32 *stage2_entry_num,
5487 u16 *stage1_counter_num,
5488 u16 *stage2_counter_num)
5489 {
5490 struct hclge_get_fd_allocation_cmd *req;
5491 struct hclge_desc desc;
5492 int ret;
5493
5494 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
5495
5496 req = (struct hclge_get_fd_allocation_cmd *)desc.data;
5497
5498 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5499 if (ret) {
5500 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
5501 ret);
5502 return ret;
5503 }
5504
5505 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
5506 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
5507 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
5508 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
5509
5510 return ret;
5511 }
5512
hclge_set_fd_key_config(struct hclge_dev * hdev,enum HCLGE_FD_STAGE stage_num)5513 static int hclge_set_fd_key_config(struct hclge_dev *hdev,
5514 enum HCLGE_FD_STAGE stage_num)
5515 {
5516 struct hclge_set_fd_key_config_cmd *req;
5517 struct hclge_fd_key_cfg *stage;
5518 struct hclge_desc desc;
5519 int ret;
5520
5521 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
5522
5523 req = (struct hclge_set_fd_key_config_cmd *)desc.data;
5524 stage = &hdev->fd_cfg.key_cfg[stage_num];
5525 req->stage = stage_num;
5526 req->key_select = stage->key_sel;
5527 req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
5528 req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
5529 req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
5530 req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
5531 req->tuple_mask = cpu_to_le32(~stage->tuple_active);
5532 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
5533
5534 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5535 if (ret)
5536 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
5537
5538 return ret;
5539 }
5540
hclge_fd_disable_user_def(struct hclge_dev * hdev)5541 static void hclge_fd_disable_user_def(struct hclge_dev *hdev)
5542 {
5543 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg;
5544
5545 spin_lock_bh(&hdev->fd_rule_lock);
5546 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg));
5547 spin_unlock_bh(&hdev->fd_rule_lock);
5548
5549 hclge_fd_set_user_def_cmd(hdev, cfg);
5550 }
5551
hclge_init_fd_config(struct hclge_dev * hdev)5552 static int hclge_init_fd_config(struct hclge_dev *hdev)
5553 {
5554 #define LOW_2_WORDS 0x03
5555 struct hclge_fd_key_cfg *key_cfg;
5556 int ret;
5557
5558 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
5559 return 0;
5560
5561 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
5562 if (ret)
5563 return ret;
5564
5565 switch (hdev->fd_cfg.fd_mode) {
5566 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
5567 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
5568 break;
5569 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
5570 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
5571 break;
5572 default:
5573 dev_err(&hdev->pdev->dev,
5574 "Unsupported flow director mode %u\n",
5575 hdev->fd_cfg.fd_mode);
5576 return -EOPNOTSUPP;
5577 }
5578
5579 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
5580 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE;
5581 key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
5582 key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
5583 key_cfg->outer_sipv6_word_en = 0;
5584 key_cfg->outer_dipv6_word_en = 0;
5585
5586 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
5587 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
5588 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5589 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5590
5591 /* If use max 400bit key, we can support tuples for ether type */
5592 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5593 key_cfg->tuple_active |=
5594 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
5595 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5596 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
5597 }
5598
5599 /* roce_type is used to filter roce frames
5600 * dst_vport is used to specify the rule
5601 */
5602 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
5603
5604 ret = hclge_get_fd_allocation(hdev,
5605 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
5606 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
5607 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
5608 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
5609 if (ret)
5610 return ret;
5611
5612 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
5613 }
5614
hclge_fd_tcam_config(struct hclge_dev * hdev,u8 stage,bool sel_x,int loc,u8 * key,bool is_add)5615 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
5616 int loc, u8 *key, bool is_add)
5617 {
5618 struct hclge_fd_tcam_config_1_cmd *req1;
5619 struct hclge_fd_tcam_config_2_cmd *req2;
5620 struct hclge_fd_tcam_config_3_cmd *req3;
5621 struct hclge_desc desc[3];
5622 int ret;
5623
5624 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
5625 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5626 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
5627 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5628 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
5629
5630 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
5631 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
5632 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
5633
5634 req1->stage = stage;
5635 req1->xy_sel = sel_x ? 1 : 0;
5636 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
5637 req1->index = cpu_to_le32(loc);
5638 req1->entry_vld = sel_x ? is_add : 0;
5639
5640 if (key) {
5641 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
5642 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
5643 sizeof(req2->tcam_data));
5644 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
5645 sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
5646 }
5647
5648 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5649 if (ret)
5650 dev_err(&hdev->pdev->dev,
5651 "config tcam key fail, ret=%d\n",
5652 ret);
5653
5654 return ret;
5655 }
5656
hclge_fd_ad_config(struct hclge_dev * hdev,u8 stage,int loc,struct hclge_fd_ad_data * action)5657 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
5658 struct hclge_fd_ad_data *action)
5659 {
5660 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
5661 struct hclge_fd_ad_config_cmd *req;
5662 struct hclge_desc desc;
5663 u64 ad_data = 0;
5664 int ret;
5665
5666 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
5667
5668 req = (struct hclge_fd_ad_config_cmd *)desc.data;
5669 req->index = cpu_to_le32(loc);
5670 req->stage = stage;
5671
5672 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
5673 action->write_rule_id_to_bd);
5674 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
5675 action->rule_id);
5676 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
5677 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B,
5678 action->override_tc);
5679 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
5680 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
5681 }
5682 hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B,
5683 action->queue_id >= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 1 : 0);
5684 hnae3_set_bit(ad_data, HCLGE_FD_AD_COUNTER_NUM_H_B,
5685 action->counter_id >= HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 ?
5686 1 : 0);
5687 ad_data <<= 32;
5688 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
5689 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
5690 action->forward_to_direct_queue);
5691 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S,
5692 action->queue_id);
5693 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
5694 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_L_M,
5695 HCLGE_FD_AD_COUNTER_NUM_L_S, action->counter_id);
5696 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
5697 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
5698 action->next_input_key);
5699
5700 req->ad_data = cpu_to_le64(ad_data);
5701 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5702 if (ret)
5703 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
5704
5705 return ret;
5706 }
5707
hclge_fd_convert_tuple(u32 tuple_bit,u8 * key_x,u8 * key_y,struct hclge_fd_rule * rule)5708 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
5709 struct hclge_fd_rule *rule)
5710 {
5711 int offset, moffset, ip_offset;
5712 enum HCLGE_FD_KEY_OPT key_opt;
5713 u16 tmp_x_s, tmp_y_s;
5714 u32 tmp_x_l, tmp_y_l;
5715 u8 *p = (u8 *)rule;
5716 int i;
5717
5718 if (rule->unused_tuple & BIT(tuple_bit))
5719 return true;
5720
5721 key_opt = tuple_key_info[tuple_bit].key_opt;
5722 offset = tuple_key_info[tuple_bit].offset;
5723 moffset = tuple_key_info[tuple_bit].moffset;
5724
5725 switch (key_opt) {
5726 case KEY_OPT_U8:
5727 calc_x(*key_x, p[offset], p[moffset]);
5728 calc_y(*key_y, p[offset], p[moffset]);
5729
5730 return true;
5731 case KEY_OPT_LE16:
5732 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5733 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5734 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
5735 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
5736
5737 return true;
5738 case KEY_OPT_LE32:
5739 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5740 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5741 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5742 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5743
5744 return true;
5745 case KEY_OPT_MAC:
5746 for (i = 0; i < ETH_ALEN; i++) {
5747 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i],
5748 p[moffset + i]);
5749 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i],
5750 p[moffset + i]);
5751 }
5752
5753 return true;
5754 case KEY_OPT_IP:
5755 ip_offset = IPV4_INDEX * sizeof(u32);
5756 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]),
5757 *(u32 *)(&p[moffset + ip_offset]));
5758 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]),
5759 *(u32 *)(&p[moffset + ip_offset]));
5760 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5761 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5762
5763 return true;
5764 default:
5765 return false;
5766 }
5767 }
5768
hclge_get_port_number(enum HLCGE_PORT_TYPE port_type,u8 pf_id,u8 vf_id,u8 network_port_id)5769 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
5770 u8 vf_id, u8 network_port_id)
5771 {
5772 u32 port_number = 0;
5773
5774 if (port_type == HOST_PORT) {
5775 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
5776 pf_id);
5777 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
5778 vf_id);
5779 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
5780 } else {
5781 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
5782 HCLGE_NETWORK_PORT_ID_S, network_port_id);
5783 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
5784 }
5785
5786 return port_number;
5787 }
5788
hclge_fd_convert_meta_data(struct hclge_fd_key_cfg * key_cfg,__le32 * key_x,__le32 * key_y,struct hclge_fd_rule * rule)5789 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
5790 __le32 *key_x, __le32 *key_y,
5791 struct hclge_fd_rule *rule)
5792 {
5793 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
5794 u8 cur_pos = 0, tuple_size, shift_bits;
5795 unsigned int i;
5796
5797 for (i = 0; i < MAX_META_DATA; i++) {
5798 tuple_size = meta_data_key_info[i].key_length;
5799 tuple_bit = key_cfg->meta_data_active & BIT(i);
5800
5801 switch (tuple_bit) {
5802 case BIT(ROCE_TYPE):
5803 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
5804 cur_pos += tuple_size;
5805 break;
5806 case BIT(DST_VPORT):
5807 port_number = hclge_get_port_number(HOST_PORT, 0,
5808 rule->vf_id, 0);
5809 hnae3_set_field(meta_data,
5810 GENMASK(cur_pos + tuple_size, cur_pos),
5811 cur_pos, port_number);
5812 cur_pos += tuple_size;
5813 break;
5814 default:
5815 break;
5816 }
5817 }
5818
5819 calc_x(tmp_x, meta_data, 0xFFFFFFFF);
5820 calc_y(tmp_y, meta_data, 0xFFFFFFFF);
5821 shift_bits = sizeof(meta_data) * 8 - cur_pos;
5822
5823 *key_x = cpu_to_le32(tmp_x << shift_bits);
5824 *key_y = cpu_to_le32(tmp_y << shift_bits);
5825 }
5826
5827 /* A complete key is combined with meta data key and tuple key.
5828 * Meta data key is stored at the MSB region, and tuple key is stored at
5829 * the LSB region, unused bits will be filled 0.
5830 */
hclge_config_key(struct hclge_dev * hdev,u8 stage,struct hclge_fd_rule * rule)5831 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
5832 struct hclge_fd_rule *rule)
5833 {
5834 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
5835 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
5836 u8 *cur_key_x, *cur_key_y;
5837 u8 meta_data_region;
5838 u8 tuple_size;
5839 int ret;
5840 u32 i;
5841
5842 memset(key_x, 0, sizeof(key_x));
5843 memset(key_y, 0, sizeof(key_y));
5844 cur_key_x = key_x;
5845 cur_key_y = key_y;
5846
5847 for (i = 0; i < MAX_TUPLE; i++) {
5848 bool tuple_valid;
5849
5850 tuple_size = tuple_key_info[i].key_length / 8;
5851 if (!(key_cfg->tuple_active & BIT(i)))
5852 continue;
5853
5854 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x,
5855 cur_key_y, rule);
5856 if (tuple_valid) {
5857 cur_key_x += tuple_size;
5858 cur_key_y += tuple_size;
5859 }
5860 }
5861
5862 meta_data_region = hdev->fd_cfg.max_key_length / 8 -
5863 MAX_META_DATA_LENGTH / 8;
5864
5865 hclge_fd_convert_meta_data(key_cfg,
5866 (__le32 *)(key_x + meta_data_region),
5867 (__le32 *)(key_y + meta_data_region),
5868 rule);
5869
5870 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
5871 true);
5872 if (ret) {
5873 dev_err(&hdev->pdev->dev,
5874 "fd key_y config fail, loc=%u, ret=%d\n",
5875 rule->queue_id, ret);
5876 return ret;
5877 }
5878
5879 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
5880 true);
5881 if (ret)
5882 dev_err(&hdev->pdev->dev,
5883 "fd key_x config fail, loc=%u, ret=%d\n",
5884 rule->queue_id, ret);
5885 return ret;
5886 }
5887
hclge_config_action(struct hclge_dev * hdev,u8 stage,struct hclge_fd_rule * rule)5888 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
5889 struct hclge_fd_rule *rule)
5890 {
5891 struct hclge_vport *vport = hdev->vport;
5892 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5893 struct hclge_fd_ad_data ad_data;
5894
5895 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data));
5896 ad_data.ad_id = rule->location;
5897
5898 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5899 ad_data.drop_packet = true;
5900 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) {
5901 ad_data.override_tc = true;
5902 ad_data.queue_id =
5903 kinfo->tc_info.tqp_offset[rule->cls_flower.tc];
5904 ad_data.tc_size =
5905 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]);
5906 } else {
5907 ad_data.forward_to_direct_queue = true;
5908 ad_data.queue_id = rule->queue_id;
5909 }
5910
5911 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) {
5912 ad_data.use_counter = true;
5913 ad_data.counter_id = rule->vf_id %
5914 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
5915 } else {
5916 ad_data.use_counter = false;
5917 ad_data.counter_id = 0;
5918 }
5919
5920 ad_data.use_next_stage = false;
5921 ad_data.next_input_key = 0;
5922
5923 ad_data.write_rule_id_to_bd = true;
5924 ad_data.rule_id = rule->location;
5925
5926 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
5927 }
5928
hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec * spec,u32 * unused_tuple)5929 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec,
5930 u32 *unused_tuple)
5931 {
5932 if (!spec || !unused_tuple)
5933 return -EINVAL;
5934
5935 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5936
5937 if (!spec->ip4src)
5938 *unused_tuple |= BIT(INNER_SRC_IP);
5939
5940 if (!spec->ip4dst)
5941 *unused_tuple |= BIT(INNER_DST_IP);
5942
5943 if (!spec->psrc)
5944 *unused_tuple |= BIT(INNER_SRC_PORT);
5945
5946 if (!spec->pdst)
5947 *unused_tuple |= BIT(INNER_DST_PORT);
5948
5949 if (!spec->tos)
5950 *unused_tuple |= BIT(INNER_IP_TOS);
5951
5952 return 0;
5953 }
5954
hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec * spec,u32 * unused_tuple)5955 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec,
5956 u32 *unused_tuple)
5957 {
5958 if (!spec || !unused_tuple)
5959 return -EINVAL;
5960
5961 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5962 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5963
5964 if (!spec->ip4src)
5965 *unused_tuple |= BIT(INNER_SRC_IP);
5966
5967 if (!spec->ip4dst)
5968 *unused_tuple |= BIT(INNER_DST_IP);
5969
5970 if (!spec->tos)
5971 *unused_tuple |= BIT(INNER_IP_TOS);
5972
5973 if (!spec->proto)
5974 *unused_tuple |= BIT(INNER_IP_PROTO);
5975
5976 if (spec->l4_4_bytes)
5977 return -EOPNOTSUPP;
5978
5979 if (spec->ip_ver != ETH_RX_NFC_IP4)
5980 return -EOPNOTSUPP;
5981
5982 return 0;
5983 }
5984
hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec * spec,u32 * unused_tuple)5985 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
5986 u32 *unused_tuple)
5987 {
5988 if (!spec || !unused_tuple)
5989 return -EINVAL;
5990
5991 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5992
5993 /* check whether src/dst ip address used */
5994 if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5995 *unused_tuple |= BIT(INNER_SRC_IP);
5996
5997 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5998 *unused_tuple |= BIT(INNER_DST_IP);
5999
6000 if (!spec->psrc)
6001 *unused_tuple |= BIT(INNER_SRC_PORT);
6002
6003 if (!spec->pdst)
6004 *unused_tuple |= BIT(INNER_DST_PORT);
6005
6006 if (!spec->tclass)
6007 *unused_tuple |= BIT(INNER_IP_TOS);
6008
6009 return 0;
6010 }
6011
hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec * spec,u32 * unused_tuple)6012 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
6013 u32 *unused_tuple)
6014 {
6015 if (!spec || !unused_tuple)
6016 return -EINVAL;
6017
6018 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
6019 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
6020
6021 /* check whether src/dst ip address used */
6022 if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
6023 *unused_tuple |= BIT(INNER_SRC_IP);
6024
6025 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
6026 *unused_tuple |= BIT(INNER_DST_IP);
6027
6028 if (!spec->l4_proto)
6029 *unused_tuple |= BIT(INNER_IP_PROTO);
6030
6031 if (!spec->tclass)
6032 *unused_tuple |= BIT(INNER_IP_TOS);
6033
6034 if (spec->l4_4_bytes)
6035 return -EOPNOTSUPP;
6036
6037 return 0;
6038 }
6039
hclge_fd_check_ether_tuple(struct ethhdr * spec,u32 * unused_tuple)6040 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple)
6041 {
6042 if (!spec || !unused_tuple)
6043 return -EINVAL;
6044
6045 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
6046 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
6047 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
6048
6049 if (is_zero_ether_addr(spec->h_source))
6050 *unused_tuple |= BIT(INNER_SRC_MAC);
6051
6052 if (is_zero_ether_addr(spec->h_dest))
6053 *unused_tuple |= BIT(INNER_DST_MAC);
6054
6055 if (!spec->h_proto)
6056 *unused_tuple |= BIT(INNER_ETH_TYPE);
6057
6058 return 0;
6059 }
6060
hclge_fd_check_ext_tuple(struct hclge_dev * hdev,struct ethtool_rx_flow_spec * fs,u32 * unused_tuple)6061 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev,
6062 struct ethtool_rx_flow_spec *fs,
6063 u32 *unused_tuple)
6064 {
6065 if (fs->flow_type & FLOW_EXT) {
6066 if (fs->h_ext.vlan_etype) {
6067 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n");
6068 return -EOPNOTSUPP;
6069 }
6070
6071 if (!fs->h_ext.vlan_tci)
6072 *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
6073
6074 if (fs->m_ext.vlan_tci &&
6075 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) {
6076 dev_err(&hdev->pdev->dev,
6077 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n",
6078 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1);
6079 return -EINVAL;
6080 }
6081 } else {
6082 *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
6083 }
6084
6085 if (fs->flow_type & FLOW_MAC_EXT) {
6086 if (hdev->fd_cfg.fd_mode !=
6087 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
6088 dev_err(&hdev->pdev->dev,
6089 "FLOW_MAC_EXT is not supported in current fd mode!\n");
6090 return -EOPNOTSUPP;
6091 }
6092
6093 if (is_zero_ether_addr(fs->h_ext.h_dest))
6094 *unused_tuple |= BIT(INNER_DST_MAC);
6095 else
6096 *unused_tuple &= ~BIT(INNER_DST_MAC);
6097 }
6098
6099 return 0;
6100 }
6101
hclge_fd_get_user_def_layer(u32 flow_type,u32 * unused_tuple,struct hclge_fd_user_def_info * info)6102 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple,
6103 struct hclge_fd_user_def_info *info)
6104 {
6105 switch (flow_type) {
6106 case ETHER_FLOW:
6107 info->layer = HCLGE_FD_USER_DEF_L2;
6108 *unused_tuple &= ~BIT(INNER_L2_RSV);
6109 break;
6110 case IP_USER_FLOW:
6111 case IPV6_USER_FLOW:
6112 info->layer = HCLGE_FD_USER_DEF_L3;
6113 *unused_tuple &= ~BIT(INNER_L3_RSV);
6114 break;
6115 case TCP_V4_FLOW:
6116 case UDP_V4_FLOW:
6117 case TCP_V6_FLOW:
6118 case UDP_V6_FLOW:
6119 info->layer = HCLGE_FD_USER_DEF_L4;
6120 *unused_tuple &= ~BIT(INNER_L4_RSV);
6121 break;
6122 default:
6123 return -EOPNOTSUPP;
6124 }
6125
6126 return 0;
6127 }
6128
hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec * fs)6129 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs)
6130 {
6131 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0;
6132 }
6133
hclge_fd_parse_user_def_field(struct hclge_dev * hdev,struct ethtool_rx_flow_spec * fs,u32 * unused_tuple,struct hclge_fd_user_def_info * info)6134 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev,
6135 struct ethtool_rx_flow_spec *fs,
6136 u32 *unused_tuple,
6137 struct hclge_fd_user_def_info *info)
6138 {
6139 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active;
6140 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6141 u16 data, offset, data_mask, offset_mask;
6142 int ret;
6143
6144 info->layer = HCLGE_FD_USER_DEF_NONE;
6145 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
6146
6147 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs))
6148 return 0;
6149
6150 /* user-def data from ethtool is 64 bit value, the bit0~15 is used
6151 * for data, and bit32~47 is used for offset.
6152 */
6153 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6154 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6155 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6156 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6157
6158 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) {
6159 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
6160 return -EOPNOTSUPP;
6161 }
6162
6163 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) {
6164 dev_err(&hdev->pdev->dev,
6165 "user-def offset[%u] should be no more than %u\n",
6166 offset, HCLGE_FD_MAX_USER_DEF_OFFSET);
6167 return -EINVAL;
6168 }
6169
6170 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
6171 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n");
6172 return -EINVAL;
6173 }
6174
6175 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info);
6176 if (ret) {
6177 dev_err(&hdev->pdev->dev,
6178 "unsupported flow type for user-def bytes, ret = %d\n",
6179 ret);
6180 return ret;
6181 }
6182
6183 info->data = data;
6184 info->data_mask = data_mask;
6185 info->offset = offset;
6186
6187 return 0;
6188 }
6189
hclge_fd_check_spec(struct hclge_dev * hdev,struct ethtool_rx_flow_spec * fs,u32 * unused_tuple,struct hclge_fd_user_def_info * info)6190 static int hclge_fd_check_spec(struct hclge_dev *hdev,
6191 struct ethtool_rx_flow_spec *fs,
6192 u32 *unused_tuple,
6193 struct hclge_fd_user_def_info *info)
6194 {
6195 u32 flow_type;
6196 int ret;
6197
6198 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
6199 dev_err(&hdev->pdev->dev,
6200 "failed to config fd rules, invalid rule location: %u, max is %u\n.",
6201 fs->location,
6202 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1);
6203 return -EINVAL;
6204 }
6205
6206 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info);
6207 if (ret)
6208 return ret;
6209
6210 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6211 switch (flow_type) {
6212 case SCTP_V4_FLOW:
6213 case TCP_V4_FLOW:
6214 case UDP_V4_FLOW:
6215 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec,
6216 unused_tuple);
6217 break;
6218 case IP_USER_FLOW:
6219 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
6220 unused_tuple);
6221 break;
6222 case SCTP_V6_FLOW:
6223 case TCP_V6_FLOW:
6224 case UDP_V6_FLOW:
6225 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec,
6226 unused_tuple);
6227 break;
6228 case IPV6_USER_FLOW:
6229 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
6230 unused_tuple);
6231 break;
6232 case ETHER_FLOW:
6233 if (hdev->fd_cfg.fd_mode !=
6234 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
6235 dev_err(&hdev->pdev->dev,
6236 "ETHER_FLOW is not supported in current fd mode!\n");
6237 return -EOPNOTSUPP;
6238 }
6239
6240 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec,
6241 unused_tuple);
6242 break;
6243 default:
6244 dev_err(&hdev->pdev->dev,
6245 "unsupported protocol type, protocol type = %#x\n",
6246 flow_type);
6247 return -EOPNOTSUPP;
6248 }
6249
6250 if (ret) {
6251 dev_err(&hdev->pdev->dev,
6252 "failed to check flow union tuple, ret = %d\n",
6253 ret);
6254 return ret;
6255 }
6256
6257 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple);
6258 }
6259
hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule,u8 ip_proto)6260 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs,
6261 struct hclge_fd_rule *rule, u8 ip_proto)
6262 {
6263 rule->tuples.src_ip[IPV4_INDEX] =
6264 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
6265 rule->tuples_mask.src_ip[IPV4_INDEX] =
6266 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
6267
6268 rule->tuples.dst_ip[IPV4_INDEX] =
6269 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
6270 rule->tuples_mask.dst_ip[IPV4_INDEX] =
6271 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
6272
6273 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
6274 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
6275
6276 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
6277 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
6278
6279 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
6280 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
6281
6282 rule->tuples.ether_proto = ETH_P_IP;
6283 rule->tuples_mask.ether_proto = 0xFFFF;
6284
6285 rule->tuples.ip_proto = ip_proto;
6286 rule->tuples_mask.ip_proto = 0xFF;
6287 }
6288
hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule)6289 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs,
6290 struct hclge_fd_rule *rule)
6291 {
6292 rule->tuples.src_ip[IPV4_INDEX] =
6293 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
6294 rule->tuples_mask.src_ip[IPV4_INDEX] =
6295 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
6296
6297 rule->tuples.dst_ip[IPV4_INDEX] =
6298 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
6299 rule->tuples_mask.dst_ip[IPV4_INDEX] =
6300 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
6301
6302 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
6303 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
6304
6305 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
6306 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
6307
6308 rule->tuples.ether_proto = ETH_P_IP;
6309 rule->tuples_mask.ether_proto = 0xFFFF;
6310 }
6311
hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule,u8 ip_proto)6312 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs,
6313 struct hclge_fd_rule *rule, u8 ip_proto)
6314 {
6315 ipv6_addr_be32_to_cpu(rule->tuples.src_ip,
6316 fs->h_u.tcp_ip6_spec.ip6src);
6317 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip,
6318 fs->m_u.tcp_ip6_spec.ip6src);
6319
6320 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip,
6321 fs->h_u.tcp_ip6_spec.ip6dst);
6322 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip,
6323 fs->m_u.tcp_ip6_spec.ip6dst);
6324
6325 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
6326 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
6327
6328 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
6329 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
6330
6331 rule->tuples.ether_proto = ETH_P_IPV6;
6332 rule->tuples_mask.ether_proto = 0xFFFF;
6333
6334 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6335 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6336
6337 rule->tuples.ip_proto = ip_proto;
6338 rule->tuples_mask.ip_proto = 0xFF;
6339 }
6340
hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule)6341 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs,
6342 struct hclge_fd_rule *rule)
6343 {
6344 ipv6_addr_be32_to_cpu(rule->tuples.src_ip,
6345 fs->h_u.usr_ip6_spec.ip6src);
6346 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip,
6347 fs->m_u.usr_ip6_spec.ip6src);
6348
6349 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip,
6350 fs->h_u.usr_ip6_spec.ip6dst);
6351 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip,
6352 fs->m_u.usr_ip6_spec.ip6dst);
6353
6354 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
6355 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
6356
6357 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6358 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6359
6360 rule->tuples.ether_proto = ETH_P_IPV6;
6361 rule->tuples_mask.ether_proto = 0xFFFF;
6362 }
6363
hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule)6364 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs,
6365 struct hclge_fd_rule *rule)
6366 {
6367 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source);
6368 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source);
6369
6370 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest);
6371 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest);
6372
6373 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto);
6374 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto);
6375 }
6376
hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info * info,struct hclge_fd_rule * rule)6377 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info,
6378 struct hclge_fd_rule *rule)
6379 {
6380 switch (info->layer) {
6381 case HCLGE_FD_USER_DEF_L2:
6382 rule->tuples.l2_user_def = info->data;
6383 rule->tuples_mask.l2_user_def = info->data_mask;
6384 break;
6385 case HCLGE_FD_USER_DEF_L3:
6386 rule->tuples.l3_user_def = info->data;
6387 rule->tuples_mask.l3_user_def = info->data_mask;
6388 break;
6389 case HCLGE_FD_USER_DEF_L4:
6390 rule->tuples.l4_user_def = (u32)info->data << 16;
6391 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16;
6392 break;
6393 default:
6394 break;
6395 }
6396
6397 rule->ep.user_def = *info;
6398 }
6399
hclge_fd_get_tuple(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule,struct hclge_fd_user_def_info * info)6400 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs,
6401 struct hclge_fd_rule *rule,
6402 struct hclge_fd_user_def_info *info)
6403 {
6404 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6405
6406 switch (flow_type) {
6407 case SCTP_V4_FLOW:
6408 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP);
6409 break;
6410 case TCP_V4_FLOW:
6411 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP);
6412 break;
6413 case UDP_V4_FLOW:
6414 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP);
6415 break;
6416 case IP_USER_FLOW:
6417 hclge_fd_get_ip4_tuple(fs, rule);
6418 break;
6419 case SCTP_V6_FLOW:
6420 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP);
6421 break;
6422 case TCP_V6_FLOW:
6423 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP);
6424 break;
6425 case UDP_V6_FLOW:
6426 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP);
6427 break;
6428 case IPV6_USER_FLOW:
6429 hclge_fd_get_ip6_tuple(fs, rule);
6430 break;
6431 case ETHER_FLOW:
6432 hclge_fd_get_ether_tuple(fs, rule);
6433 break;
6434 default:
6435 return -EOPNOTSUPP;
6436 }
6437
6438 if (fs->flow_type & FLOW_EXT) {
6439 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
6440 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
6441 hclge_fd_get_user_def_tuple(info, rule);
6442 }
6443
6444 if (fs->flow_type & FLOW_MAC_EXT) {
6445 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
6446 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
6447 }
6448
6449 return 0;
6450 }
6451
hclge_fd_config_rule(struct hclge_dev * hdev,struct hclge_fd_rule * rule)6452 static int hclge_fd_config_rule(struct hclge_dev *hdev,
6453 struct hclge_fd_rule *rule)
6454 {
6455 int ret;
6456
6457 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
6458 if (ret)
6459 return ret;
6460
6461 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
6462 }
6463
hclge_add_fd_entry_common(struct hclge_dev * hdev,struct hclge_fd_rule * rule)6464 static int hclge_add_fd_entry_common(struct hclge_dev *hdev,
6465 struct hclge_fd_rule *rule)
6466 {
6467 int ret;
6468
6469 spin_lock_bh(&hdev->fd_rule_lock);
6470
6471 if (hdev->fd_active_type != rule->rule_type &&
6472 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6473 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) {
6474 dev_err(&hdev->pdev->dev,
6475 "mode conflict(new type %d, active type %d), please delete existent rules first\n",
6476 rule->rule_type, hdev->fd_active_type);
6477 spin_unlock_bh(&hdev->fd_rule_lock);
6478 return -EINVAL;
6479 }
6480
6481 ret = hclge_fd_check_user_def_refcnt(hdev, rule);
6482 if (ret)
6483 goto out;
6484
6485 ret = hclge_clear_arfs_rules(hdev);
6486 if (ret)
6487 goto out;
6488
6489 ret = hclge_fd_config_rule(hdev, rule);
6490 if (ret)
6491 goto out;
6492
6493 rule->state = HCLGE_FD_ACTIVE;
6494 hdev->fd_active_type = rule->rule_type;
6495 hclge_update_fd_list(hdev, rule->state, rule->location, rule);
6496
6497 out:
6498 spin_unlock_bh(&hdev->fd_rule_lock);
6499 return ret;
6500 }
6501
hclge_is_cls_flower_active(struct hnae3_handle * handle)6502 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle)
6503 {
6504 struct hclge_vport *vport = hclge_get_vport(handle);
6505 struct hclge_dev *hdev = vport->back;
6506
6507 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE;
6508 }
6509
hclge_fd_parse_ring_cookie(struct hclge_dev * hdev,u64 ring_cookie,u16 * vport_id,u8 * action,u16 * queue_id)6510 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie,
6511 u16 *vport_id, u8 *action, u16 *queue_id)
6512 {
6513 struct hclge_vport *vport = hdev->vport;
6514
6515 if (ring_cookie == RX_CLS_FLOW_DISC) {
6516 *action = HCLGE_FD_ACTION_DROP_PACKET;
6517 } else {
6518 u32 ring = ethtool_get_flow_spec_ring(ring_cookie);
6519 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie);
6520 u16 tqps;
6521
6522 /* To keep consistent with user's configuration, minus 1 when
6523 * printing 'vf', because vf id from ethtool is added 1 for vf.
6524 */
6525 if (vf > hdev->num_req_vfs) {
6526 dev_err(&hdev->pdev->dev,
6527 "Error: vf id (%u) should be less than %u\n",
6528 vf - 1U, hdev->num_req_vfs);
6529 return -EINVAL;
6530 }
6531
6532 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
6533 tqps = hdev->vport[vf].nic.kinfo.num_tqps;
6534
6535 if (ring >= tqps) {
6536 dev_err(&hdev->pdev->dev,
6537 "Error: queue id (%u) > max tqp num (%u)\n",
6538 ring, tqps - 1U);
6539 return -EINVAL;
6540 }
6541
6542 *action = HCLGE_FD_ACTION_SELECT_QUEUE;
6543 *queue_id = ring;
6544 }
6545
6546 return 0;
6547 }
6548
hclge_add_fd_entry(struct hnae3_handle * handle,struct ethtool_rxnfc * cmd)6549 static int hclge_add_fd_entry(struct hnae3_handle *handle,
6550 struct ethtool_rxnfc *cmd)
6551 {
6552 struct hclge_vport *vport = hclge_get_vport(handle);
6553 struct hclge_dev *hdev = vport->back;
6554 struct hclge_fd_user_def_info info;
6555 u16 dst_vport_id = 0, q_index = 0;
6556 struct ethtool_rx_flow_spec *fs;
6557 struct hclge_fd_rule *rule;
6558 u32 unused = 0;
6559 u8 action;
6560 int ret;
6561
6562 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
6563 dev_err(&hdev->pdev->dev,
6564 "flow table director is not supported\n");
6565 return -EOPNOTSUPP;
6566 }
6567
6568 if (!hdev->fd_en) {
6569 dev_err(&hdev->pdev->dev,
6570 "please enable flow director first\n");
6571 return -EOPNOTSUPP;
6572 }
6573
6574 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6575
6576 ret = hclge_fd_check_spec(hdev, fs, &unused, &info);
6577 if (ret)
6578 return ret;
6579
6580 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id,
6581 &action, &q_index);
6582 if (ret)
6583 return ret;
6584
6585 rule = kzalloc_obj(*rule);
6586 if (!rule)
6587 return -ENOMEM;
6588
6589 ret = hclge_fd_get_tuple(fs, rule, &info);
6590 if (ret) {
6591 kfree(rule);
6592 return ret;
6593 }
6594
6595 rule->flow_type = fs->flow_type;
6596 rule->location = fs->location;
6597 rule->unused_tuple = unused;
6598 rule->vf_id = dst_vport_id;
6599 rule->queue_id = q_index;
6600 rule->action = action;
6601 rule->rule_type = HCLGE_FD_EP_ACTIVE;
6602
6603 ret = hclge_add_fd_entry_common(hdev, rule);
6604 if (ret)
6605 kfree(rule);
6606
6607 return ret;
6608 }
6609
hclge_del_fd_entry(struct hnae3_handle * handle,struct ethtool_rxnfc * cmd)6610 static int hclge_del_fd_entry(struct hnae3_handle *handle,
6611 struct ethtool_rxnfc *cmd)
6612 {
6613 struct hclge_vport *vport = hclge_get_vport(handle);
6614 struct hclge_dev *hdev = vport->back;
6615 struct ethtool_rx_flow_spec *fs;
6616 int ret;
6617
6618 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6619 return -EOPNOTSUPP;
6620
6621 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6622
6623 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6624 return -EINVAL;
6625
6626 spin_lock_bh(&hdev->fd_rule_lock);
6627 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6628 !test_bit(fs->location, hdev->fd_bmap)) {
6629 dev_err(&hdev->pdev->dev,
6630 "Delete fail, rule %u is inexistent\n", fs->location);
6631 spin_unlock_bh(&hdev->fd_rule_lock);
6632 return -ENOENT;
6633 }
6634
6635 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location,
6636 NULL, false);
6637 if (ret)
6638 goto out;
6639
6640 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL);
6641
6642 out:
6643 spin_unlock_bh(&hdev->fd_rule_lock);
6644 return ret;
6645 }
6646
hclge_clear_fd_rules_in_list(struct hclge_dev * hdev,bool clear_list)6647 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev,
6648 bool clear_list)
6649 {
6650 struct hclge_fd_rule *rule;
6651 struct hlist_node *node;
6652 u16 location;
6653
6654 spin_lock_bh(&hdev->fd_rule_lock);
6655
6656 for_each_set_bit(location, hdev->fd_bmap,
6657 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6658 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location,
6659 NULL, false);
6660
6661 if (clear_list) {
6662 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
6663 rule_node) {
6664 hlist_del(&rule->rule_node);
6665 kfree(rule);
6666 }
6667 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
6668 hdev->hclge_fd_rule_num = 0;
6669 bitmap_zero(hdev->fd_bmap,
6670 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
6671 }
6672
6673 spin_unlock_bh(&hdev->fd_rule_lock);
6674 }
6675
hclge_del_all_fd_entries(struct hclge_dev * hdev)6676 static void hclge_del_all_fd_entries(struct hclge_dev *hdev)
6677 {
6678 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6679 return;
6680
6681 hclge_clear_fd_rules_in_list(hdev, true);
6682 hclge_fd_disable_user_def(hdev);
6683 }
6684
hclge_restore_fd_entries(struct hnae3_handle * handle)6685 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
6686 {
6687 struct hclge_vport *vport = hclge_get_vport(handle);
6688 struct hclge_dev *hdev = vport->back;
6689 struct hclge_fd_rule *rule;
6690 struct hlist_node *node;
6691
6692 /* Return ok here, because reset error handling will check this
6693 * return value. If error is returned here, the reset process will
6694 * fail.
6695 */
6696 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6697 return 0;
6698
6699 /* if fd is disabled, should not restore it when reset */
6700 if (!hdev->fd_en)
6701 return 0;
6702
6703 spin_lock_bh(&hdev->fd_rule_lock);
6704 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6705 if (rule->state == HCLGE_FD_ACTIVE)
6706 rule->state = HCLGE_FD_TO_ADD;
6707 }
6708 spin_unlock_bh(&hdev->fd_rule_lock);
6709 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6710
6711 return 0;
6712 }
6713
hclge_get_fd_rule_cnt(struct hnae3_handle * handle,struct ethtool_rxnfc * cmd)6714 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
6715 struct ethtool_rxnfc *cmd)
6716 {
6717 struct hclge_vport *vport = hclge_get_vport(handle);
6718 struct hclge_dev *hdev = vport->back;
6719
6720 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle))
6721 return -EOPNOTSUPP;
6722
6723 cmd->rule_cnt = hdev->hclge_fd_rule_num;
6724 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6725
6726 return 0;
6727 }
6728
hclge_fd_get_tcpip4_info(struct hclge_fd_rule * rule,struct ethtool_tcpip4_spec * spec,struct ethtool_tcpip4_spec * spec_mask)6729 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule,
6730 struct ethtool_tcpip4_spec *spec,
6731 struct ethtool_tcpip4_spec *spec_mask)
6732 {
6733 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6734 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6735 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6736
6737 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6738 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6739 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6740
6741 spec->psrc = cpu_to_be16(rule->tuples.src_port);
6742 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6743 0 : cpu_to_be16(rule->tuples_mask.src_port);
6744
6745 spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6746 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6747 0 : cpu_to_be16(rule->tuples_mask.dst_port);
6748
6749 spec->tos = rule->tuples.ip_tos;
6750 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6751 0 : rule->tuples_mask.ip_tos;
6752 }
6753
hclge_fd_get_ip4_info(struct hclge_fd_rule * rule,struct ethtool_usrip4_spec * spec,struct ethtool_usrip4_spec * spec_mask)6754 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule,
6755 struct ethtool_usrip4_spec *spec,
6756 struct ethtool_usrip4_spec *spec_mask)
6757 {
6758 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6759 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6760 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6761
6762 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6763 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6764 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6765
6766 spec->tos = rule->tuples.ip_tos;
6767 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6768 0 : rule->tuples_mask.ip_tos;
6769
6770 spec->proto = rule->tuples.ip_proto;
6771 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6772 0 : rule->tuples_mask.ip_proto;
6773
6774 spec->ip_ver = ETH_RX_NFC_IP4;
6775 }
6776
hclge_fd_get_tcpip6_info(struct hclge_fd_rule * rule,struct ethtool_tcpip6_spec * spec,struct ethtool_tcpip6_spec * spec_mask)6777 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule,
6778 struct ethtool_tcpip6_spec *spec,
6779 struct ethtool_tcpip6_spec *spec_mask)
6780 {
6781 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip);
6782 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip);
6783 if (rule->unused_tuple & BIT(INNER_SRC_IP))
6784 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6785 else
6786 ipv6_addr_cpu_to_be32(spec_mask->ip6src,
6787 rule->tuples_mask.src_ip);
6788
6789 if (rule->unused_tuple & BIT(INNER_DST_IP))
6790 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6791 else
6792 ipv6_addr_cpu_to_be32(spec_mask->ip6dst,
6793 rule->tuples_mask.dst_ip);
6794
6795 spec->tclass = rule->tuples.ip_tos;
6796 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6797 0 : rule->tuples_mask.ip_tos;
6798
6799 spec->psrc = cpu_to_be16(rule->tuples.src_port);
6800 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6801 0 : cpu_to_be16(rule->tuples_mask.src_port);
6802
6803 spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6804 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6805 0 : cpu_to_be16(rule->tuples_mask.dst_port);
6806 }
6807
hclge_fd_get_ip6_info(struct hclge_fd_rule * rule,struct ethtool_usrip6_spec * spec,struct ethtool_usrip6_spec * spec_mask)6808 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule,
6809 struct ethtool_usrip6_spec *spec,
6810 struct ethtool_usrip6_spec *spec_mask)
6811 {
6812 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip);
6813 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip);
6814 if (rule->unused_tuple & BIT(INNER_SRC_IP))
6815 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6816 else
6817 ipv6_addr_cpu_to_be32(spec_mask->ip6src,
6818 rule->tuples_mask.src_ip);
6819
6820 if (rule->unused_tuple & BIT(INNER_DST_IP))
6821 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6822 else
6823 ipv6_addr_cpu_to_be32(spec_mask->ip6dst,
6824 rule->tuples_mask.dst_ip);
6825
6826 spec->tclass = rule->tuples.ip_tos;
6827 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6828 0 : rule->tuples_mask.ip_tos;
6829
6830 spec->l4_proto = rule->tuples.ip_proto;
6831 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6832 0 : rule->tuples_mask.ip_proto;
6833 }
6834
hclge_fd_get_ether_info(struct hclge_fd_rule * rule,struct ethhdr * spec,struct ethhdr * spec_mask)6835 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule,
6836 struct ethhdr *spec,
6837 struct ethhdr *spec_mask)
6838 {
6839 ether_addr_copy(spec->h_source, rule->tuples.src_mac);
6840 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac);
6841
6842 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
6843 eth_zero_addr(spec_mask->h_source);
6844 else
6845 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac);
6846
6847 if (rule->unused_tuple & BIT(INNER_DST_MAC))
6848 eth_zero_addr(spec_mask->h_dest);
6849 else
6850 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac);
6851
6852 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto);
6853 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
6854 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
6855 }
6856
hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule)6857 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs,
6858 struct hclge_fd_rule *rule)
6859 {
6860 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) ==
6861 HCLGE_FD_TUPLE_USER_DEF_TUPLES) {
6862 fs->h_ext.data[0] = 0;
6863 fs->h_ext.data[1] = 0;
6864 fs->m_ext.data[0] = 0;
6865 fs->m_ext.data[1] = 0;
6866 } else {
6867 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset);
6868 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data);
6869 fs->m_ext.data[0] =
6870 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK);
6871 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask);
6872 }
6873 }
6874
hclge_fd_get_ext_info(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule)6875 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs,
6876 struct hclge_fd_rule *rule)
6877 {
6878 if (fs->flow_type & FLOW_EXT) {
6879 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
6880 fs->m_ext.vlan_tci =
6881 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
6882 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1);
6883
6884 hclge_fd_get_user_def_info(fs, rule);
6885 }
6886
6887 if (fs->flow_type & FLOW_MAC_EXT) {
6888 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
6889 if (rule->unused_tuple & BIT(INNER_DST_MAC))
6890 eth_zero_addr(fs->m_u.ether_spec.h_dest);
6891 else
6892 ether_addr_copy(fs->m_u.ether_spec.h_dest,
6893 rule->tuples_mask.dst_mac);
6894 }
6895 }
6896
hclge_get_fd_rule(struct hclge_dev * hdev,u16 location)6897 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev,
6898 u16 location)
6899 {
6900 struct hclge_fd_rule *rule = NULL;
6901 struct hlist_node *node2;
6902
6903 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
6904 if (rule->location == location)
6905 return rule;
6906 else if (rule->location > location)
6907 return NULL;
6908 }
6909
6910 return NULL;
6911 }
6912
hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec * fs,struct hclge_fd_rule * rule)6913 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs,
6914 struct hclge_fd_rule *rule)
6915 {
6916 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
6917 fs->ring_cookie = RX_CLS_FLOW_DISC;
6918 } else {
6919 u64 vf_id;
6920
6921 fs->ring_cookie = rule->queue_id;
6922 vf_id = rule->vf_id;
6923 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
6924 fs->ring_cookie |= vf_id;
6925 }
6926 }
6927
hclge_get_fd_rule_info(struct hnae3_handle * handle,struct ethtool_rxnfc * cmd)6928 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
6929 struct ethtool_rxnfc *cmd)
6930 {
6931 struct hclge_vport *vport = hclge_get_vport(handle);
6932 struct hclge_fd_rule *rule = NULL;
6933 struct hclge_dev *hdev = vport->back;
6934 struct ethtool_rx_flow_spec *fs;
6935
6936 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6937 return -EOPNOTSUPP;
6938
6939 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6940
6941 spin_lock_bh(&hdev->fd_rule_lock);
6942
6943 rule = hclge_get_fd_rule(hdev, fs->location);
6944 if (!rule) {
6945 spin_unlock_bh(&hdev->fd_rule_lock);
6946 return -ENOENT;
6947 }
6948
6949 fs->flow_type = rule->flow_type;
6950 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
6951 case SCTP_V4_FLOW:
6952 case TCP_V4_FLOW:
6953 case UDP_V4_FLOW:
6954 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec,
6955 &fs->m_u.tcp_ip4_spec);
6956 break;
6957 case IP_USER_FLOW:
6958 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
6959 &fs->m_u.usr_ip4_spec);
6960 break;
6961 case SCTP_V6_FLOW:
6962 case TCP_V6_FLOW:
6963 case UDP_V6_FLOW:
6964 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec,
6965 &fs->m_u.tcp_ip6_spec);
6966 break;
6967 case IPV6_USER_FLOW:
6968 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
6969 &fs->m_u.usr_ip6_spec);
6970 break;
6971 /* The flow type of fd rule has been checked before adding in to rule
6972 * list. As other flow types have been handled, it must be ETHER_FLOW
6973 * for the default case
6974 */
6975 default:
6976 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec,
6977 &fs->m_u.ether_spec);
6978 break;
6979 }
6980
6981 hclge_fd_get_ext_info(fs, rule);
6982
6983 hclge_fd_get_ring_cookie(fs, rule);
6984
6985 spin_unlock_bh(&hdev->fd_rule_lock);
6986
6987 return 0;
6988 }
6989
hclge_get_all_rules(struct hnae3_handle * handle,struct ethtool_rxnfc * cmd,u32 * rule_locs)6990 static int hclge_get_all_rules(struct hnae3_handle *handle,
6991 struct ethtool_rxnfc *cmd, u32 *rule_locs)
6992 {
6993 struct hclge_vport *vport = hclge_get_vport(handle);
6994 struct hclge_dev *hdev = vport->back;
6995 struct hclge_fd_rule *rule;
6996 struct hlist_node *node2;
6997 u32 cnt = 0;
6998
6999 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7000 return -EOPNOTSUPP;
7001
7002 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
7003
7004 spin_lock_bh(&hdev->fd_rule_lock);
7005 hlist_for_each_entry_safe(rule, node2,
7006 &hdev->fd_rule_list, rule_node) {
7007 if (cnt == cmd->rule_cnt) {
7008 spin_unlock_bh(&hdev->fd_rule_lock);
7009 return -EMSGSIZE;
7010 }
7011
7012 if (rule->state == HCLGE_FD_TO_DEL)
7013 continue;
7014
7015 rule_locs[cnt] = rule->location;
7016 cnt++;
7017 }
7018
7019 spin_unlock_bh(&hdev->fd_rule_lock);
7020
7021 cmd->rule_cnt = cnt;
7022
7023 return 0;
7024 }
7025
hclge_fd_get_flow_tuples(const struct flow_keys * fkeys,struct hclge_fd_rule_tuples * tuples)7026 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys,
7027 struct hclge_fd_rule_tuples *tuples)
7028 {
7029 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32
7030 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32
7031
7032 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto);
7033 tuples->ip_proto = fkeys->basic.ip_proto;
7034 tuples->dst_port = be16_to_cpu(fkeys->ports.dst);
7035
7036 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
7037 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src);
7038 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst);
7039 } else {
7040 int i;
7041
7042 for (i = 0; i < IPV6_ADDR_WORDS; i++) {
7043 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]);
7044 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]);
7045 }
7046 }
7047 }
7048
7049 /* traverse all rules, check whether an existed rule has the same tuples */
7050 static struct hclge_fd_rule *
hclge_fd_search_flow_keys(struct hclge_dev * hdev,const struct hclge_fd_rule_tuples * tuples)7051 hclge_fd_search_flow_keys(struct hclge_dev *hdev,
7052 const struct hclge_fd_rule_tuples *tuples)
7053 {
7054 struct hclge_fd_rule *rule = NULL;
7055 struct hlist_node *node;
7056
7057 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7058 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples)))
7059 return rule;
7060 }
7061
7062 return NULL;
7063 }
7064
hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples * tuples,struct hclge_fd_rule * rule)7065 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples,
7066 struct hclge_fd_rule *rule)
7067 {
7068 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
7069 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) |
7070 BIT(INNER_SRC_PORT);
7071 rule->action = 0;
7072 rule->vf_id = 0;
7073 rule->rule_type = HCLGE_FD_ARFS_ACTIVE;
7074 rule->state = HCLGE_FD_TO_ADD;
7075 if (tuples->ether_proto == ETH_P_IP) {
7076 if (tuples->ip_proto == IPPROTO_TCP)
7077 rule->flow_type = TCP_V4_FLOW;
7078 else
7079 rule->flow_type = UDP_V4_FLOW;
7080 } else {
7081 if (tuples->ip_proto == IPPROTO_TCP)
7082 rule->flow_type = TCP_V6_FLOW;
7083 else
7084 rule->flow_type = UDP_V6_FLOW;
7085 }
7086 memcpy(&rule->tuples, tuples, sizeof(rule->tuples));
7087 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask));
7088 }
7089
hclge_add_fd_entry_by_arfs(struct hnae3_handle * handle,u16 queue_id,u16 flow_id,struct flow_keys * fkeys)7090 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
7091 u16 flow_id, struct flow_keys *fkeys)
7092 {
7093 struct hclge_vport *vport = hclge_get_vport(handle);
7094 struct hclge_fd_rule_tuples new_tuples = {};
7095 struct hclge_dev *hdev = vport->back;
7096 struct hclge_fd_rule *rule;
7097 u16 bit_id;
7098
7099 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7100 return -EOPNOTSUPP;
7101
7102 /* when there is already fd rule existed add by user,
7103 * arfs should not work
7104 */
7105 spin_lock_bh(&hdev->fd_rule_lock);
7106 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE &&
7107 hdev->fd_active_type != HCLGE_FD_RULE_NONE) {
7108 spin_unlock_bh(&hdev->fd_rule_lock);
7109 return -EOPNOTSUPP;
7110 }
7111
7112 hclge_fd_get_flow_tuples(fkeys, &new_tuples);
7113
7114 /* check is there flow director filter existed for this flow,
7115 * if not, create a new filter for it;
7116 * if filter exist with different queue id, modify the filter;
7117 * if filter exist with same queue id, do nothing
7118 */
7119 rule = hclge_fd_search_flow_keys(hdev, &new_tuples);
7120 if (!rule) {
7121 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM);
7122 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7123 spin_unlock_bh(&hdev->fd_rule_lock);
7124 return -ENOSPC;
7125 }
7126
7127 rule = kzalloc_obj(*rule, GFP_ATOMIC);
7128 if (!rule) {
7129 spin_unlock_bh(&hdev->fd_rule_lock);
7130 return -ENOMEM;
7131 }
7132
7133 rule->location = bit_id;
7134 rule->arfs.flow_id = flow_id;
7135 rule->queue_id = queue_id;
7136 hclge_fd_build_arfs_rule(&new_tuples, rule);
7137 hclge_update_fd_list(hdev, rule->state, rule->location, rule);
7138 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE;
7139 } else if (rule->queue_id != queue_id) {
7140 rule->queue_id = queue_id;
7141 rule->state = HCLGE_FD_TO_ADD;
7142 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7143 hclge_task_schedule(hdev, 0);
7144 }
7145 spin_unlock_bh(&hdev->fd_rule_lock);
7146 return rule->location;
7147 }
7148
hclge_rfs_filter_expire(struct hclge_dev * hdev)7149 static void hclge_rfs_filter_expire(struct hclge_dev *hdev)
7150 {
7151 #ifdef CONFIG_RFS_ACCEL
7152 struct hnae3_handle *handle = &hdev->vport[0].nic;
7153 struct hclge_fd_rule *rule;
7154 struct hlist_node *node;
7155
7156 spin_lock_bh(&hdev->fd_rule_lock);
7157 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) {
7158 spin_unlock_bh(&hdev->fd_rule_lock);
7159 return;
7160 }
7161 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7162 if (rule->state != HCLGE_FD_ACTIVE)
7163 continue;
7164 if (rps_may_expire_flow(handle->netdev, rule->queue_id,
7165 rule->arfs.flow_id, rule->location)) {
7166 rule->state = HCLGE_FD_TO_DEL;
7167 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7168 }
7169 }
7170 spin_unlock_bh(&hdev->fd_rule_lock);
7171 #endif
7172 }
7173
7174 /* make sure being called after lock up with fd_rule_lock */
hclge_clear_arfs_rules(struct hclge_dev * hdev)7175 static int hclge_clear_arfs_rules(struct hclge_dev *hdev)
7176 {
7177 #ifdef CONFIG_RFS_ACCEL
7178 struct hclge_fd_rule *rule;
7179 struct hlist_node *node;
7180 int ret;
7181
7182 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE)
7183 return 0;
7184
7185 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7186 switch (rule->state) {
7187 case HCLGE_FD_TO_DEL:
7188 case HCLGE_FD_ACTIVE:
7189 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7190 rule->location, NULL, false);
7191 if (ret)
7192 return ret;
7193 fallthrough;
7194 case HCLGE_FD_TO_ADD:
7195 hclge_fd_dec_rule_cnt(hdev, rule->location);
7196 hlist_del(&rule->rule_node);
7197 kfree(rule);
7198 break;
7199 default:
7200 break;
7201 }
7202 }
7203 hclge_sync_fd_state(hdev);
7204
7205 #endif
7206 return 0;
7207 }
7208
hclge_get_cls_key_basic(const struct flow_rule * flow,struct hclge_fd_rule * rule)7209 static void hclge_get_cls_key_basic(const struct flow_rule *flow,
7210 struct hclge_fd_rule *rule)
7211 {
7212 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) {
7213 struct flow_match_basic match;
7214 u16 ethtype_key, ethtype_mask;
7215
7216 flow_rule_match_basic(flow, &match);
7217 ethtype_key = ntohs(match.key->n_proto);
7218 ethtype_mask = ntohs(match.mask->n_proto);
7219
7220 if (ethtype_key == ETH_P_ALL) {
7221 ethtype_key = 0;
7222 ethtype_mask = 0;
7223 }
7224 rule->tuples.ether_proto = ethtype_key;
7225 rule->tuples_mask.ether_proto = ethtype_mask;
7226 rule->tuples.ip_proto = match.key->ip_proto;
7227 rule->tuples_mask.ip_proto = match.mask->ip_proto;
7228 } else {
7229 rule->unused_tuple |= BIT(INNER_IP_PROTO);
7230 rule->unused_tuple |= BIT(INNER_ETH_TYPE);
7231 }
7232 }
7233
hclge_get_cls_key_mac(const struct flow_rule * flow,struct hclge_fd_rule * rule)7234 static void hclge_get_cls_key_mac(const struct flow_rule *flow,
7235 struct hclge_fd_rule *rule)
7236 {
7237 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
7238 struct flow_match_eth_addrs match;
7239
7240 flow_rule_match_eth_addrs(flow, &match);
7241 ether_addr_copy(rule->tuples.dst_mac, match.key->dst);
7242 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst);
7243 ether_addr_copy(rule->tuples.src_mac, match.key->src);
7244 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src);
7245 } else {
7246 rule->unused_tuple |= BIT(INNER_DST_MAC);
7247 rule->unused_tuple |= BIT(INNER_SRC_MAC);
7248 }
7249 }
7250
hclge_get_cls_key_vlan(const struct flow_rule * flow,struct hclge_fd_rule * rule)7251 static void hclge_get_cls_key_vlan(const struct flow_rule *flow,
7252 struct hclge_fd_rule *rule)
7253 {
7254 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) {
7255 struct flow_match_vlan match;
7256
7257 flow_rule_match_vlan(flow, &match);
7258 rule->tuples.vlan_tag1 = match.key->vlan_id |
7259 (match.key->vlan_priority << VLAN_PRIO_SHIFT);
7260 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id |
7261 (match.mask->vlan_priority << VLAN_PRIO_SHIFT);
7262 } else {
7263 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST);
7264 }
7265 }
7266
hclge_get_cls_key_ip(const struct flow_rule * flow,struct hclge_fd_rule * rule,struct netlink_ext_ack * extack)7267 static int hclge_get_cls_key_ip(const struct flow_rule *flow,
7268 struct hclge_fd_rule *rule,
7269 struct netlink_ext_ack *extack)
7270 {
7271 u16 addr_type = 0;
7272
7273 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) {
7274 struct flow_match_control match;
7275
7276 flow_rule_match_control(flow, &match);
7277 addr_type = match.key->addr_type;
7278
7279 if (flow_rule_has_control_flags(match.mask->flags, extack))
7280 return -EOPNOTSUPP;
7281 }
7282
7283 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
7284 struct flow_match_ipv4_addrs match;
7285
7286 flow_rule_match_ipv4_addrs(flow, &match);
7287 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src);
7288 rule->tuples_mask.src_ip[IPV4_INDEX] =
7289 be32_to_cpu(match.mask->src);
7290 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst);
7291 rule->tuples_mask.dst_ip[IPV4_INDEX] =
7292 be32_to_cpu(match.mask->dst);
7293 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
7294 struct flow_match_ipv6_addrs match;
7295
7296 flow_rule_match_ipv6_addrs(flow, &match);
7297 ipv6_addr_be32_to_cpu(rule->tuples.src_ip,
7298 match.key->src.s6_addr32);
7299 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip,
7300 match.mask->src.s6_addr32);
7301 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip,
7302 match.key->dst.s6_addr32);
7303 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip,
7304 match.mask->dst.s6_addr32);
7305 } else {
7306 rule->unused_tuple |= BIT(INNER_SRC_IP);
7307 rule->unused_tuple |= BIT(INNER_DST_IP);
7308 }
7309
7310 return 0;
7311 }
7312
hclge_get_cls_key_port(const struct flow_rule * flow,struct hclge_fd_rule * rule)7313 static void hclge_get_cls_key_port(const struct flow_rule *flow,
7314 struct hclge_fd_rule *rule)
7315 {
7316 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) {
7317 struct flow_match_ports match;
7318
7319 flow_rule_match_ports(flow, &match);
7320
7321 rule->tuples.src_port = be16_to_cpu(match.key->src);
7322 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src);
7323 rule->tuples.dst_port = be16_to_cpu(match.key->dst);
7324 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst);
7325 } else {
7326 rule->unused_tuple |= BIT(INNER_SRC_PORT);
7327 rule->unused_tuple |= BIT(INNER_DST_PORT);
7328 }
7329 }
7330
hclge_parse_cls_flower(struct hclge_dev * hdev,struct flow_cls_offload * cls_flower,struct hclge_fd_rule * rule)7331 static int hclge_parse_cls_flower(struct hclge_dev *hdev,
7332 struct flow_cls_offload *cls_flower,
7333 struct hclge_fd_rule *rule)
7334 {
7335 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower);
7336 struct netlink_ext_ack *extack = cls_flower->common.extack;
7337 struct flow_dissector *dissector = flow->match.dissector;
7338 int ret;
7339
7340 if (dissector->used_keys &
7341 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
7342 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
7343 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
7344 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
7345 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
7346 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
7347 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) {
7348 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n",
7349 dissector->used_keys);
7350 return -EOPNOTSUPP;
7351 }
7352
7353 hclge_get_cls_key_basic(flow, rule);
7354 hclge_get_cls_key_mac(flow, rule);
7355 hclge_get_cls_key_vlan(flow, rule);
7356
7357 ret = hclge_get_cls_key_ip(flow, rule, extack);
7358 if (ret)
7359 return ret;
7360
7361 hclge_get_cls_key_port(flow, rule);
7362
7363 return 0;
7364 }
7365
hclge_check_cls_flower(struct hclge_dev * hdev,struct flow_cls_offload * cls_flower,int tc)7366 static int hclge_check_cls_flower(struct hclge_dev *hdev,
7367 struct flow_cls_offload *cls_flower, int tc)
7368 {
7369 u32 prio = cls_flower->common.prio;
7370
7371 if (tc < 0 || tc > hdev->tc_max) {
7372 dev_err(&hdev->pdev->dev, "invalid traffic class\n");
7373 return -EINVAL;
7374 }
7375
7376 if (prio == 0 ||
7377 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7378 dev_err(&hdev->pdev->dev,
7379 "prio %u should be in range[1, %u]\n",
7380 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
7381 return -EINVAL;
7382 }
7383
7384 if (test_bit(prio - 1, hdev->fd_bmap)) {
7385 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio);
7386 return -EINVAL;
7387 }
7388 return 0;
7389 }
7390
hclge_add_cls_flower(struct hnae3_handle * handle,struct flow_cls_offload * cls_flower,int tc)7391 static int hclge_add_cls_flower(struct hnae3_handle *handle,
7392 struct flow_cls_offload *cls_flower,
7393 int tc)
7394 {
7395 struct hclge_vport *vport = hclge_get_vport(handle);
7396 struct hclge_dev *hdev = vport->back;
7397 struct hclge_fd_rule *rule;
7398 int ret;
7399
7400 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
7401 dev_err(&hdev->pdev->dev,
7402 "cls flower is not supported\n");
7403 return -EOPNOTSUPP;
7404 }
7405
7406 ret = hclge_check_cls_flower(hdev, cls_flower, tc);
7407 if (ret) {
7408 dev_err(&hdev->pdev->dev,
7409 "failed to check cls flower params, ret = %d\n", ret);
7410 return ret;
7411 }
7412
7413 rule = kzalloc_obj(*rule);
7414 if (!rule)
7415 return -ENOMEM;
7416
7417 ret = hclge_parse_cls_flower(hdev, cls_flower, rule);
7418 if (ret) {
7419 kfree(rule);
7420 return ret;
7421 }
7422
7423 rule->action = HCLGE_FD_ACTION_SELECT_TC;
7424 rule->cls_flower.tc = tc;
7425 rule->location = cls_flower->common.prio - 1;
7426 rule->vf_id = 0;
7427 rule->cls_flower.cookie = cls_flower->cookie;
7428 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE;
7429
7430 ret = hclge_add_fd_entry_common(hdev, rule);
7431 if (ret)
7432 kfree(rule);
7433
7434 return ret;
7435 }
7436
hclge_find_cls_flower(struct hclge_dev * hdev,unsigned long cookie)7437 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev,
7438 unsigned long cookie)
7439 {
7440 struct hclge_fd_rule *rule;
7441 struct hlist_node *node;
7442
7443 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7444 if (rule->cls_flower.cookie == cookie)
7445 return rule;
7446 }
7447
7448 return NULL;
7449 }
7450
hclge_del_cls_flower(struct hnae3_handle * handle,struct flow_cls_offload * cls_flower)7451 static int hclge_del_cls_flower(struct hnae3_handle *handle,
7452 struct flow_cls_offload *cls_flower)
7453 {
7454 struct hclge_vport *vport = hclge_get_vport(handle);
7455 struct hclge_dev *hdev = vport->back;
7456 struct hclge_fd_rule *rule;
7457 int ret;
7458
7459 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7460 return -EOPNOTSUPP;
7461
7462 spin_lock_bh(&hdev->fd_rule_lock);
7463
7464 rule = hclge_find_cls_flower(hdev, cls_flower->cookie);
7465 if (!rule) {
7466 spin_unlock_bh(&hdev->fd_rule_lock);
7467 return -EINVAL;
7468 }
7469
7470 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,
7471 NULL, false);
7472 if (ret) {
7473 /* if tcam config fail, set rule state to TO_DEL,
7474 * so the rule will be deleted when periodic
7475 * task being scheduled.
7476 */
7477 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL);
7478 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7479 spin_unlock_bh(&hdev->fd_rule_lock);
7480 return ret;
7481 }
7482
7483 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL);
7484 spin_unlock_bh(&hdev->fd_rule_lock);
7485
7486 return 0;
7487 }
7488
hclge_sync_fd_list(struct hclge_dev * hdev,struct hlist_head * hlist)7489 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist)
7490 {
7491 struct hclge_fd_rule *rule;
7492 struct hlist_node *node;
7493 int ret = 0;
7494
7495 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state))
7496 return;
7497
7498 spin_lock_bh(&hdev->fd_rule_lock);
7499
7500 hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
7501 switch (rule->state) {
7502 case HCLGE_FD_TO_ADD:
7503 ret = hclge_fd_config_rule(hdev, rule);
7504 if (ret)
7505 goto out;
7506 rule->state = HCLGE_FD_ACTIVE;
7507 break;
7508 case HCLGE_FD_TO_DEL:
7509 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7510 rule->location, NULL, false);
7511 if (ret)
7512 goto out;
7513 hclge_fd_dec_rule_cnt(hdev, rule->location);
7514 hclge_fd_free_node(hdev, rule);
7515 break;
7516 default:
7517 break;
7518 }
7519 }
7520
7521 out:
7522 if (ret)
7523 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7524
7525 spin_unlock_bh(&hdev->fd_rule_lock);
7526 }
7527
hclge_sync_fd_table(struct hclge_dev * hdev)7528 static void hclge_sync_fd_table(struct hclge_dev *hdev)
7529 {
7530 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7531 return;
7532
7533 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) {
7534 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE;
7535
7536 hclge_clear_fd_rules_in_list(hdev, clear_list);
7537 }
7538
7539 hclge_sync_fd_user_def_cfg(hdev, false);
7540
7541 hclge_sync_fd_list(hdev, &hdev->fd_rule_list);
7542 }
7543
hclge_get_hw_reset_stat(struct hnae3_handle * handle)7544 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
7545 {
7546 struct hclge_vport *vport = hclge_get_vport(handle);
7547 struct hclge_dev *hdev = vport->back;
7548
7549 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
7550 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
7551 }
7552
hclge_get_cmdq_stat(struct hnae3_handle * handle)7553 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle)
7554 {
7555 struct hclge_vport *vport = hclge_get_vport(handle);
7556 struct hclge_dev *hdev = vport->back;
7557
7558 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
7559 }
7560
hclge_ae_dev_resetting(struct hnae3_handle * handle)7561 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
7562 {
7563 struct hclge_vport *vport = hclge_get_vport(handle);
7564 struct hclge_dev *hdev = vport->back;
7565
7566 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7567 }
7568
hclge_ae_dev_reset_cnt(struct hnae3_handle * handle)7569 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
7570 {
7571 struct hclge_vport *vport = hclge_get_vport(handle);
7572 struct hclge_dev *hdev = vport->back;
7573
7574 return hdev->rst_stats.hw_reset_done_cnt;
7575 }
7576
hclge_enable_fd(struct hnae3_handle * handle,bool enable)7577 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
7578 {
7579 struct hclge_vport *vport = hclge_get_vport(handle);
7580 struct hclge_dev *hdev = vport->back;
7581
7582 hdev->fd_en = enable;
7583
7584 if (!enable)
7585 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state);
7586 else
7587 hclge_restore_fd_entries(handle);
7588
7589 hclge_task_schedule(hdev, 0);
7590 }
7591
hclge_cfg_mac_mode(struct hclge_dev * hdev,bool enable)7592 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
7593 {
7594 #define HCLGE_LINK_STATUS_WAIT_CNT 3
7595
7596 struct hclge_desc desc;
7597 struct hclge_config_mac_mode_cmd *req =
7598 (struct hclge_config_mac_mode_cmd *)desc.data;
7599 u32 loop_en = 0;
7600 int ret;
7601
7602 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
7603
7604 if (enable) {
7605 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U);
7606 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U);
7607 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U);
7608 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U);
7609 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U);
7610 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U);
7611 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U);
7612 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U);
7613 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U);
7614 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U);
7615 }
7616
7617 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7618
7619 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7620 if (ret) {
7621 dev_err(&hdev->pdev->dev,
7622 "mac enable fail, ret =%d.\n", ret);
7623 return;
7624 }
7625
7626 if (!enable)
7627 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN,
7628 HCLGE_LINK_STATUS_WAIT_CNT);
7629 }
7630
hclge_config_switch_param(struct hclge_dev * hdev,int vfid,u8 switch_param,u8 param_mask)7631 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
7632 u8 switch_param, u8 param_mask)
7633 {
7634 struct hclge_mac_vlan_switch_cmd *req;
7635 struct hclge_desc desc;
7636 u32 func_id;
7637 int ret;
7638
7639 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0);
7640 req = (struct hclge_mac_vlan_switch_cmd *)desc.data;
7641
7642 /* read current config parameter */
7643 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM,
7644 true);
7645 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL;
7646 req->func_id = cpu_to_le32(func_id);
7647
7648 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7649 if (ret) {
7650 dev_err(&hdev->pdev->dev,
7651 "read mac vlan switch parameter fail, ret = %d\n", ret);
7652 return ret;
7653 }
7654
7655 /* modify and write new config parameter */
7656 hclge_comm_cmd_reuse_desc(&desc, false);
7657 req->switch_param = (req->switch_param & param_mask) | switch_param;
7658 req->param_mask = param_mask;
7659
7660 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7661 if (ret)
7662 dev_err(&hdev->pdev->dev,
7663 "set mac vlan switch parameter fail, ret = %d\n", ret);
7664 return ret;
7665 }
7666
hclge_phy_link_status_wait(struct hclge_dev * hdev,int link_ret)7667 static void hclge_phy_link_status_wait(struct hclge_dev *hdev,
7668 int link_ret)
7669 {
7670 #define HCLGE_PHY_LINK_STATUS_NUM 200
7671
7672 struct phy_device *phydev = hdev->hw.mac.phydev;
7673 int i = 0;
7674 int ret;
7675
7676 do {
7677 ret = phy_read_status(phydev);
7678 if (ret) {
7679 dev_err(&hdev->pdev->dev,
7680 "phy update link status fail, ret = %d\n", ret);
7681 return;
7682 }
7683
7684 if (phydev->link == link_ret)
7685 break;
7686
7687 msleep(HCLGE_LINK_STATUS_MS);
7688 } while (++i < HCLGE_PHY_LINK_STATUS_NUM);
7689 }
7690
hclge_mac_link_status_wait(struct hclge_dev * hdev,int link_ret,int wait_cnt)7691 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
7692 int wait_cnt)
7693 {
7694 int link_status;
7695 int i = 0;
7696 int ret;
7697
7698 do {
7699 ret = hclge_get_mac_link_status(hdev, &link_status);
7700 if (ret)
7701 return ret;
7702 if (link_status == link_ret)
7703 return 0;
7704
7705 msleep(HCLGE_LINK_STATUS_MS);
7706 } while (++i < wait_cnt);
7707 return -EBUSY;
7708 }
7709
hclge_mac_phy_link_status_wait(struct hclge_dev * hdev,bool en,bool is_phy)7710 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
7711 bool is_phy)
7712 {
7713 #define HCLGE_MAC_LINK_STATUS_NUM 100
7714
7715 int link_ret;
7716
7717 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
7718
7719 if (is_phy)
7720 hclge_phy_link_status_wait(hdev, link_ret);
7721
7722 return hclge_mac_link_status_wait(hdev, link_ret,
7723 HCLGE_MAC_LINK_STATUS_NUM);
7724 }
7725
hclge_set_app_loopback(struct hclge_dev * hdev,bool en)7726 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
7727 {
7728 struct hclge_config_mac_mode_cmd *req;
7729 struct hclge_desc desc;
7730 u32 loop_en;
7731 int ret;
7732
7733 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
7734 /* 1 Read out the MAC mode config at first */
7735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
7736 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7737 if (ret) {
7738 dev_err(&hdev->pdev->dev,
7739 "mac loopback get fail, ret =%d.\n", ret);
7740 return ret;
7741 }
7742
7743 /* 2 Then setup the loopback flag */
7744 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
7745 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
7746
7747 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7748
7749 /* 3 Config mac work mode with loopback flag
7750 * and its original configure parameters
7751 */
7752 hclge_comm_cmd_reuse_desc(&desc, false);
7753 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7754 if (ret)
7755 dev_err(&hdev->pdev->dev,
7756 "mac loopback set fail, ret =%d.\n", ret);
7757 return ret;
7758 }
7759
hclge_cfg_common_loopback_cmd_send(struct hclge_dev * hdev,bool en,enum hnae3_loop loop_mode)7760 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en,
7761 enum hnae3_loop loop_mode)
7762 {
7763 struct hclge_common_lb_cmd *req;
7764 struct hclge_desc desc;
7765 u8 loop_mode_b;
7766 int ret;
7767
7768 req = (struct hclge_common_lb_cmd *)desc.data;
7769 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false);
7770
7771 switch (loop_mode) {
7772 case HNAE3_LOOP_SERIAL_SERDES:
7773 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
7774 break;
7775 case HNAE3_LOOP_PARALLEL_SERDES:
7776 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
7777 break;
7778 case HNAE3_LOOP_PHY:
7779 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B;
7780 break;
7781 default:
7782 dev_err(&hdev->pdev->dev,
7783 "unsupported loopback mode %d\n", loop_mode);
7784 return -ENOTSUPP;
7785 }
7786
7787 req->mask = loop_mode_b;
7788 if (en)
7789 req->enable = loop_mode_b;
7790
7791 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7792 if (ret)
7793 dev_err(&hdev->pdev->dev,
7794 "failed to send loopback cmd, loop_mode = %d, ret = %d\n",
7795 loop_mode, ret);
7796
7797 return ret;
7798 }
7799
hclge_cfg_common_loopback_wait(struct hclge_dev * hdev)7800 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev)
7801 {
7802 #define HCLGE_COMMON_LB_RETRY_MS 10
7803 #define HCLGE_COMMON_LB_RETRY_NUM 100
7804
7805 struct hclge_common_lb_cmd *req;
7806 struct hclge_desc desc;
7807 u32 i = 0;
7808 int ret;
7809
7810 req = (struct hclge_common_lb_cmd *)desc.data;
7811
7812 do {
7813 msleep(HCLGE_COMMON_LB_RETRY_MS);
7814 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
7815 true);
7816 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7817 if (ret) {
7818 dev_err(&hdev->pdev->dev,
7819 "failed to get loopback done status, ret = %d\n",
7820 ret);
7821 return ret;
7822 }
7823 } while (++i < HCLGE_COMMON_LB_RETRY_NUM &&
7824 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B));
7825
7826 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) {
7827 dev_err(&hdev->pdev->dev, "wait loopback timeout\n");
7828 return -EBUSY;
7829 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) {
7830 dev_err(&hdev->pdev->dev, "failed to do loopback test\n");
7831 return -EIO;
7832 }
7833
7834 return 0;
7835 }
7836
hclge_cfg_common_loopback(struct hclge_dev * hdev,bool en,enum hnae3_loop loop_mode)7837 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en,
7838 enum hnae3_loop loop_mode)
7839 {
7840 int ret;
7841
7842 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode);
7843 if (ret)
7844 return ret;
7845
7846 return hclge_cfg_common_loopback_wait(hdev);
7847 }
7848
hclge_set_common_loopback(struct hclge_dev * hdev,bool en,enum hnae3_loop loop_mode)7849 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en,
7850 enum hnae3_loop loop_mode)
7851 {
7852 int ret;
7853
7854 ret = hclge_cfg_common_loopback(hdev, en, loop_mode);
7855 if (ret)
7856 return ret;
7857
7858 hclge_cfg_mac_mode(hdev, en);
7859
7860 ret = hclge_mac_phy_link_status_wait(hdev, en, false);
7861 if (ret)
7862 dev_err(&hdev->pdev->dev,
7863 "serdes loopback config mac mode timeout\n");
7864
7865 return ret;
7866 }
7867
hclge_enable_phy_loopback(struct hclge_dev * hdev,struct phy_device * phydev)7868 static int hclge_enable_phy_loopback(struct hclge_dev *hdev,
7869 struct phy_device *phydev)
7870 {
7871 int ret;
7872
7873 if (!phydev->suspended) {
7874 ret = phy_suspend(phydev);
7875 if (ret)
7876 return ret;
7877 }
7878
7879 ret = phy_resume(phydev);
7880 if (ret)
7881 return ret;
7882
7883 return phy_loopback(phydev, true, 0);
7884 }
7885
hclge_disable_phy_loopback(struct hclge_dev * hdev,struct phy_device * phydev)7886 static int hclge_disable_phy_loopback(struct hclge_dev *hdev,
7887 struct phy_device *phydev)
7888 {
7889 int ret;
7890
7891 ret = phy_loopback(phydev, false, 0);
7892 if (ret)
7893 return ret;
7894
7895 return phy_suspend(phydev);
7896 }
7897
hclge_set_phy_loopback(struct hclge_dev * hdev,bool en)7898 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
7899 {
7900 struct phy_device *phydev = hdev->hw.mac.phydev;
7901 int ret;
7902
7903 if (!phydev) {
7904 if (hnae3_dev_phy_imp_supported(hdev))
7905 return hclge_set_common_loopback(hdev, en,
7906 HNAE3_LOOP_PHY);
7907 return -ENOTSUPP;
7908 }
7909
7910 if (en)
7911 ret = hclge_enable_phy_loopback(hdev, phydev);
7912 else
7913 ret = hclge_disable_phy_loopback(hdev, phydev);
7914 if (ret) {
7915 dev_err(&hdev->pdev->dev,
7916 "set phy loopback fail, ret = %d\n", ret);
7917 return ret;
7918 }
7919
7920 hclge_cfg_mac_mode(hdev, en);
7921
7922 ret = hclge_mac_phy_link_status_wait(hdev, en, true);
7923 if (ret)
7924 dev_err(&hdev->pdev->dev,
7925 "phy loopback config mac mode timeout\n");
7926
7927 return ret;
7928 }
7929
hclge_tqp_enable_cmd_send(struct hclge_dev * hdev,u16 tqp_id,u16 stream_id,bool enable)7930 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id,
7931 u16 stream_id, bool enable)
7932 {
7933 struct hclge_desc desc;
7934 struct hclge_cfg_com_tqp_queue_cmd *req =
7935 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
7936
7937 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
7938 req->tqp_id = cpu_to_le16(tqp_id);
7939 req->stream_id = cpu_to_le16(stream_id);
7940 if (enable)
7941 req->enable |= 1U << HCLGE_TQP_ENABLE_B;
7942
7943 return hclge_cmd_send(&hdev->hw, &desc, 1);
7944 }
7945
hclge_tqp_enable(struct hnae3_handle * handle,bool enable)7946 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable)
7947 {
7948 struct hclge_vport *vport = hclge_get_vport(handle);
7949 struct hclge_dev *hdev = vport->back;
7950 int ret;
7951 u16 i;
7952
7953 for (i = 0; i < handle->kinfo.num_tqps; i++) {
7954 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable);
7955 if (ret)
7956 return ret;
7957 }
7958 return 0;
7959 }
7960
hclge_set_loopback(struct hnae3_handle * handle,enum hnae3_loop loop_mode,bool en)7961 static int hclge_set_loopback(struct hnae3_handle *handle,
7962 enum hnae3_loop loop_mode, bool en)
7963 {
7964 struct hclge_vport *vport = hclge_get_vport(handle);
7965 struct hclge_dev *hdev = vport->back;
7966 int ret = 0;
7967
7968 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By
7969 * default, SSU loopback is enabled, so if the SMAC and the DMAC are
7970 * the same, the packets are looped back in the SSU. If SSU loopback
7971 * is disabled, packets can reach MAC even if SMAC is the same as DMAC.
7972 */
7973 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
7974 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
7975
7976 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
7977 HCLGE_SWITCH_ALW_LPBK_MASK);
7978 if (ret)
7979 return ret;
7980 }
7981
7982 switch (loop_mode) {
7983 case HNAE3_LOOP_APP:
7984 ret = hclge_set_app_loopback(hdev, en);
7985 break;
7986 case HNAE3_LOOP_SERIAL_SERDES:
7987 case HNAE3_LOOP_PARALLEL_SERDES:
7988 ret = hclge_set_common_loopback(hdev, en, loop_mode);
7989 break;
7990 case HNAE3_LOOP_PHY:
7991 ret = hclge_set_phy_loopback(hdev, en);
7992 break;
7993 case HNAE3_LOOP_EXTERNAL:
7994 break;
7995 default:
7996 ret = -ENOTSUPP;
7997 dev_err(&hdev->pdev->dev,
7998 "loop_mode %d is not supported\n", loop_mode);
7999 break;
8000 }
8001
8002 if (ret)
8003 return ret;
8004
8005 ret = hclge_tqp_enable(handle, en);
8006 if (ret)
8007 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n",
8008 str_enable_disable(en), ret);
8009
8010 return ret;
8011 }
8012
hclge_set_default_loopback(struct hclge_dev * hdev)8013 static int hclge_set_default_loopback(struct hclge_dev *hdev)
8014 {
8015 int ret;
8016
8017 ret = hclge_set_app_loopback(hdev, false);
8018 if (ret)
8019 return ret;
8020
8021 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
8022 if (ret)
8023 return ret;
8024
8025 return hclge_cfg_common_loopback(hdev, false,
8026 HNAE3_LOOP_PARALLEL_SERDES);
8027 }
8028
hclge_flush_link_update(struct hclge_dev * hdev)8029 static void hclge_flush_link_update(struct hclge_dev *hdev)
8030 {
8031 #define HCLGE_FLUSH_LINK_TIMEOUT 100000
8032
8033 unsigned long last = hdev->serv_processed_cnt;
8034 int i = 0;
8035
8036 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) &&
8037 i++ < HCLGE_FLUSH_LINK_TIMEOUT &&
8038 last == hdev->serv_processed_cnt)
8039 usleep_range(1, 1);
8040 }
8041
hclge_set_timer_task(struct hnae3_handle * handle,bool enable)8042 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
8043 {
8044 struct hclge_vport *vport = hclge_get_vport(handle);
8045 struct hclge_dev *hdev = vport->back;
8046
8047 if (enable) {
8048 hclge_task_schedule(hdev, 0);
8049 } else {
8050 /* Set the DOWN flag here to disable link updating */
8051 set_bit(HCLGE_STATE_DOWN, &hdev->state);
8052
8053 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */
8054 hclge_flush_link_update(hdev);
8055 }
8056 }
8057
hclge_ae_start(struct hnae3_handle * handle)8058 static int hclge_ae_start(struct hnae3_handle *handle)
8059 {
8060 struct hclge_vport *vport = hclge_get_vport(handle);
8061 struct hclge_dev *hdev = vport->back;
8062
8063 /* mac enable */
8064 hclge_cfg_mac_mode(hdev, true);
8065 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
8066 hdev->hw.mac.link = 0;
8067
8068 /* reset tqp stats */
8069 hclge_comm_reset_tqp_stats(handle);
8070
8071 hclge_mac_start_phy(hdev);
8072
8073 return 0;
8074 }
8075
hclge_ae_stop(struct hnae3_handle * handle)8076 static void hclge_ae_stop(struct hnae3_handle *handle)
8077 {
8078 struct hclge_vport *vport = hclge_get_vport(handle);
8079 struct hclge_dev *hdev = vport->back;
8080
8081 set_bit(HCLGE_STATE_DOWN, &hdev->state);
8082 spin_lock_bh(&hdev->fd_rule_lock);
8083 hclge_clear_arfs_rules(hdev);
8084 spin_unlock_bh(&hdev->fd_rule_lock);
8085
8086 /* If it is not PF reset or FLR, the firmware will disable the MAC,
8087 * so it only need to stop phy here.
8088 */
8089 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
8090 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
8091 HCLGE_PFC_DISABLE);
8092 if (hdev->reset_type != HNAE3_FUNC_RESET &&
8093 hdev->reset_type != HNAE3_FLR_RESET) {
8094 hclge_mac_stop_phy(hdev);
8095 hclge_update_link_status(hdev);
8096 return;
8097 }
8098 }
8099
8100 hclge_reset_tqp(handle);
8101
8102 hclge_config_mac_tnl_int(hdev, false);
8103
8104 /* Mac disable */
8105 hclge_cfg_mac_mode(hdev, false);
8106
8107 hclge_mac_stop_phy(hdev);
8108
8109 /* reset tqp stats */
8110 hclge_comm_reset_tqp_stats(handle);
8111 hclge_update_link_status(hdev);
8112 }
8113
hclge_vport_start(struct hclge_vport * vport)8114 int hclge_vport_start(struct hclge_vport *vport)
8115 {
8116 struct hclge_dev *hdev = vport->back;
8117
8118 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
8119 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8120 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
8121 vport->last_active_jiffies = jiffies;
8122 vport->need_notify = 0;
8123
8124 if (test_bit(vport->vport_id, hdev->vport_config_block)) {
8125 if (vport->vport_id) {
8126 hclge_restore_mac_table_common(vport);
8127 hclge_restore_vport_vlan_table(vport);
8128 } else {
8129 hclge_restore_hw_table(hdev);
8130 }
8131 }
8132
8133 clear_bit(vport->vport_id, hdev->vport_config_block);
8134
8135 return 0;
8136 }
8137
hclge_vport_stop(struct hclge_vport * vport)8138 void hclge_vport_stop(struct hclge_vport *vport)
8139 {
8140 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
8141 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8142 vport->need_notify = 0;
8143 }
8144
hclge_client_start(struct hnae3_handle * handle)8145 static int hclge_client_start(struct hnae3_handle *handle)
8146 {
8147 struct hclge_vport *vport = hclge_get_vport(handle);
8148
8149 return hclge_vport_start(vport);
8150 }
8151
hclge_client_stop(struct hnae3_handle * handle)8152 static void hclge_client_stop(struct hnae3_handle *handle)
8153 {
8154 struct hclge_vport *vport = hclge_get_vport(handle);
8155
8156 hclge_vport_stop(vport);
8157 }
8158
hclge_get_mac_vlan_cmd_status(struct hclge_vport * vport,u16 cmdq_resp,u8 resp_code,enum hclge_mac_vlan_tbl_opcode op)8159 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
8160 u16 cmdq_resp, u8 resp_code,
8161 enum hclge_mac_vlan_tbl_opcode op)
8162 {
8163 struct hclge_dev *hdev = vport->back;
8164
8165 if (cmdq_resp) {
8166 dev_err(&hdev->pdev->dev,
8167 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n",
8168 cmdq_resp);
8169 return -EIO;
8170 }
8171
8172 if (op == HCLGE_MAC_VLAN_ADD) {
8173 if (!resp_code || resp_code == 1)
8174 return 0;
8175 else if (resp_code == HCLGE_ADD_UC_OVERFLOW ||
8176 resp_code == HCLGE_ADD_MC_OVERFLOW)
8177 return -ENOSPC;
8178
8179 dev_err(&hdev->pdev->dev,
8180 "add mac addr failed for undefined, code=%u.\n",
8181 resp_code);
8182 return -EIO;
8183 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
8184 if (!resp_code) {
8185 return 0;
8186 } else if (resp_code == 1) {
8187 dev_dbg(&hdev->pdev->dev,
8188 "remove mac addr failed for miss.\n");
8189 return -ENOENT;
8190 }
8191
8192 dev_err(&hdev->pdev->dev,
8193 "remove mac addr failed for undefined, code=%u.\n",
8194 resp_code);
8195 return -EIO;
8196 } else if (op == HCLGE_MAC_VLAN_LKUP) {
8197 if (!resp_code) {
8198 return 0;
8199 } else if (resp_code == 1) {
8200 dev_dbg(&hdev->pdev->dev,
8201 "lookup mac addr failed for miss.\n");
8202 return -ENOENT;
8203 }
8204
8205 dev_err(&hdev->pdev->dev,
8206 "lookup mac addr failed for undefined, code=%u.\n",
8207 resp_code);
8208 return -EIO;
8209 }
8210
8211 dev_err(&hdev->pdev->dev,
8212 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op);
8213
8214 return -EINVAL;
8215 }
8216
hclge_update_desc_vfid(struct hclge_desc * desc,int vfid,bool clr)8217 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
8218 {
8219 #define HCLGE_VF_NUM_IN_FIRST_DESC 192
8220
8221 unsigned int word_num;
8222 unsigned int bit_num;
8223
8224 if (vfid > 255 || vfid < 0)
8225 return -EIO;
8226
8227 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) {
8228 word_num = vfid / 32;
8229 bit_num = vfid % 32;
8230 if (clr)
8231 desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num));
8232 else
8233 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
8234 } else {
8235 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
8236 bit_num = vfid % 32;
8237 if (clr)
8238 desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num));
8239 else
8240 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
8241 }
8242
8243 return 0;
8244 }
8245
hclge_is_all_function_id_zero(struct hclge_desc * desc)8246 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
8247 {
8248 #define HCLGE_DESC_NUMBER 3
8249 #define HCLGE_FUNC_NUMBER_PER_DESC 6
8250 int i, j;
8251
8252 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
8253 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
8254 if (desc[i].data[j])
8255 return false;
8256
8257 return true;
8258 }
8259
hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd * new_req,const u8 * addr,bool is_mc)8260 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
8261 const u8 *addr, bool is_mc)
8262 {
8263 const unsigned char *mac_addr = addr;
8264 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
8265 (mac_addr[0]) | (mac_addr[1] << 8);
8266 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
8267
8268 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8269 if (is_mc) {
8270 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
8271 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8272 }
8273
8274 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
8275 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
8276 }
8277
hclge_remove_mac_vlan_tbl(struct hclge_vport * vport,struct hclge_mac_vlan_tbl_entry_cmd * req)8278 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
8279 struct hclge_mac_vlan_tbl_entry_cmd *req)
8280 {
8281 struct hclge_dev *hdev = vport->back;
8282 struct hclge_desc desc;
8283 u8 resp_code;
8284 u16 retval;
8285 int ret;
8286
8287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
8288
8289 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8290
8291 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8292 if (ret) {
8293 dev_err(&hdev->pdev->dev,
8294 "del mac addr failed for cmd_send, ret =%d.\n",
8295 ret);
8296 return ret;
8297 }
8298 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8299 retval = le16_to_cpu(desc.retval);
8300
8301 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8302 HCLGE_MAC_VLAN_REMOVE);
8303 }
8304
hclge_lookup_mac_vlan_tbl(struct hclge_vport * vport,struct hclge_mac_vlan_tbl_entry_cmd * req,struct hclge_desc * desc,bool is_mc)8305 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
8306 struct hclge_mac_vlan_tbl_entry_cmd *req,
8307 struct hclge_desc *desc,
8308 bool is_mc)
8309 {
8310 struct hclge_dev *hdev = vport->back;
8311 u8 resp_code;
8312 u16 retval;
8313 int ret;
8314
8315 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
8316 if (is_mc) {
8317 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8318 memcpy(desc[0].data,
8319 req,
8320 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8321 hclge_cmd_setup_basic_desc(&desc[1],
8322 HCLGE_OPC_MAC_VLAN_ADD,
8323 true);
8324 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8325 hclge_cmd_setup_basic_desc(&desc[2],
8326 HCLGE_OPC_MAC_VLAN_ADD,
8327 true);
8328 ret = hclge_cmd_send(&hdev->hw, desc, 3);
8329 } else {
8330 memcpy(desc[0].data,
8331 req,
8332 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8333 ret = hclge_cmd_send(&hdev->hw, desc, 1);
8334 }
8335 if (ret) {
8336 dev_err(&hdev->pdev->dev,
8337 "lookup mac addr failed for cmd_send, ret =%d.\n",
8338 ret);
8339 return ret;
8340 }
8341 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
8342 retval = le16_to_cpu(desc[0].retval);
8343
8344 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8345 HCLGE_MAC_VLAN_LKUP);
8346 }
8347
hclge_add_mac_vlan_tbl(struct hclge_vport * vport,struct hclge_mac_vlan_tbl_entry_cmd * req,struct hclge_desc * mc_desc)8348 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
8349 struct hclge_mac_vlan_tbl_entry_cmd *req,
8350 struct hclge_desc *mc_desc)
8351 {
8352 struct hclge_dev *hdev = vport->back;
8353 int cfg_status;
8354 u8 resp_code;
8355 u16 retval;
8356 int ret;
8357
8358 if (!mc_desc) {
8359 struct hclge_desc desc;
8360
8361 hclge_cmd_setup_basic_desc(&desc,
8362 HCLGE_OPC_MAC_VLAN_ADD,
8363 false);
8364 memcpy(desc.data, req,
8365 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8366 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8367 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8368 retval = le16_to_cpu(desc.retval);
8369
8370 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8371 resp_code,
8372 HCLGE_MAC_VLAN_ADD);
8373 } else {
8374 hclge_comm_cmd_reuse_desc(&mc_desc[0], false);
8375 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8376 hclge_comm_cmd_reuse_desc(&mc_desc[1], false);
8377 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8378 hclge_comm_cmd_reuse_desc(&mc_desc[2], false);
8379 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT);
8380 memcpy(mc_desc[0].data, req,
8381 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8382 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
8383 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
8384 retval = le16_to_cpu(mc_desc[0].retval);
8385
8386 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8387 resp_code,
8388 HCLGE_MAC_VLAN_ADD);
8389 }
8390
8391 if (ret) {
8392 dev_err(&hdev->pdev->dev,
8393 "add mac addr failed for cmd_send, ret =%d.\n",
8394 ret);
8395 return ret;
8396 }
8397
8398 return cfg_status;
8399 }
8400
hclge_set_umv_space(struct hclge_dev * hdev,u16 space_size,u16 * allocated_size)8401 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
8402 u16 *allocated_size)
8403 {
8404 struct hclge_umv_spc_alc_cmd *req;
8405 struct hclge_desc desc;
8406 int ret;
8407
8408 req = (struct hclge_umv_spc_alc_cmd *)desc.data;
8409 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
8410
8411 req->space_size = cpu_to_le32(space_size);
8412
8413 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8414 if (ret) {
8415 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n",
8416 ret);
8417 return ret;
8418 }
8419
8420 *allocated_size = le32_to_cpu(desc.data[1]);
8421
8422 return 0;
8423 }
8424
hclge_init_umv_space(struct hclge_dev * hdev)8425 static int hclge_init_umv_space(struct hclge_dev *hdev)
8426 {
8427 u16 allocated_size = 0;
8428 int ret;
8429
8430 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size);
8431 if (ret)
8432 return ret;
8433
8434 if (allocated_size < hdev->wanted_umv_size)
8435 dev_warn(&hdev->pdev->dev,
8436 "failed to alloc umv space, want %u, get %u\n",
8437 hdev->wanted_umv_size, allocated_size);
8438
8439 hdev->max_umv_size = allocated_size;
8440 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1);
8441 hdev->share_umv_size = hdev->priv_umv_size +
8442 hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8443
8444 if (hdev->ae_dev->dev_specs.mc_mac_size)
8445 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps);
8446
8447 return 0;
8448 }
8449
hclge_reset_umv_space(struct hclge_dev * hdev)8450 static void hclge_reset_umv_space(struct hclge_dev *hdev)
8451 {
8452 struct hclge_vport *vport;
8453 int i;
8454
8455 for (i = 0; i < hdev->num_alloc_vport; i++) {
8456 vport = &hdev->vport[i];
8457 vport->used_umv_num = 0;
8458 }
8459
8460 mutex_lock(&hdev->vport_lock);
8461 hdev->share_umv_size = hdev->priv_umv_size +
8462 hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8463 mutex_unlock(&hdev->vport_lock);
8464
8465 hdev->used_mc_mac_num = 0;
8466 }
8467
hclge_is_umv_space_full(struct hclge_vport * vport,bool need_lock)8468 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock)
8469 {
8470 struct hclge_dev *hdev = vport->back;
8471 bool is_full;
8472
8473 if (need_lock)
8474 mutex_lock(&hdev->vport_lock);
8475
8476 is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
8477 hdev->share_umv_size == 0);
8478
8479 if (need_lock)
8480 mutex_unlock(&hdev->vport_lock);
8481
8482 return is_full;
8483 }
8484
hclge_update_umv_space(struct hclge_vport * vport,bool is_free)8485 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
8486 {
8487 struct hclge_dev *hdev = vport->back;
8488
8489 if (is_free) {
8490 if (vport->used_umv_num > hdev->priv_umv_size)
8491 hdev->share_umv_size++;
8492
8493 if (vport->used_umv_num > 0)
8494 vport->used_umv_num--;
8495 } else {
8496 if (vport->used_umv_num >= hdev->priv_umv_size &&
8497 hdev->share_umv_size > 0)
8498 hdev->share_umv_size--;
8499 vport->used_umv_num++;
8500 }
8501 }
8502
hclge_find_mac_node(struct list_head * list,const u8 * mac_addr)8503 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list,
8504 const u8 *mac_addr)
8505 {
8506 struct hclge_mac_node *mac_node, *tmp;
8507
8508 list_for_each_entry_safe(mac_node, tmp, list, node)
8509 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
8510 return mac_node;
8511
8512 return NULL;
8513 }
8514
hclge_update_mac_node(struct hclge_mac_node * mac_node,enum HCLGE_MAC_NODE_STATE state)8515 static void hclge_update_mac_node(struct hclge_mac_node *mac_node,
8516 enum HCLGE_MAC_NODE_STATE state)
8517 {
8518 switch (state) {
8519 /* from set_rx_mode or tmp_add_list */
8520 case HCLGE_MAC_TO_ADD:
8521 if (mac_node->state == HCLGE_MAC_TO_DEL)
8522 mac_node->state = HCLGE_MAC_ACTIVE;
8523 break;
8524 /* only from set_rx_mode */
8525 case HCLGE_MAC_TO_DEL:
8526 if (mac_node->state == HCLGE_MAC_TO_ADD) {
8527 list_del(&mac_node->node);
8528 kfree(mac_node);
8529 } else {
8530 mac_node->state = HCLGE_MAC_TO_DEL;
8531 }
8532 break;
8533 /* only from tmp_add_list, the mac_node->state won't be
8534 * ACTIVE.
8535 */
8536 case HCLGE_MAC_ACTIVE:
8537 if (mac_node->state == HCLGE_MAC_TO_ADD)
8538 mac_node->state = HCLGE_MAC_ACTIVE;
8539
8540 break;
8541 }
8542 }
8543
hclge_update_mac_list(struct hclge_vport * vport,enum HCLGE_MAC_NODE_STATE state,enum HCLGE_MAC_ADDR_TYPE mac_type,const unsigned char * addr)8544 int hclge_update_mac_list(struct hclge_vport *vport,
8545 enum HCLGE_MAC_NODE_STATE state,
8546 enum HCLGE_MAC_ADDR_TYPE mac_type,
8547 const unsigned char *addr)
8548 {
8549 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8550 struct hclge_dev *hdev = vport->back;
8551 struct hclge_mac_node *mac_node;
8552 struct list_head *list;
8553
8554 list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8555 &vport->uc_mac_list : &vport->mc_mac_list;
8556
8557 spin_lock_bh(&vport->mac_list_lock);
8558
8559 /* if the mac addr is already in the mac list, no need to add a new
8560 * one into it, just check the mac addr state, convert it to a new
8561 * state, or just remove it, or do nothing.
8562 */
8563 mac_node = hclge_find_mac_node(list, addr);
8564 if (mac_node) {
8565 hclge_update_mac_node(mac_node, state);
8566 spin_unlock_bh(&vport->mac_list_lock);
8567 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8568 return 0;
8569 }
8570
8571 /* if this address is never added, unnecessary to delete */
8572 if (state == HCLGE_MAC_TO_DEL) {
8573 spin_unlock_bh(&vport->mac_list_lock);
8574 hnae3_format_mac_addr(format_mac_addr, addr);
8575 dev_err(&hdev->pdev->dev,
8576 "failed to delete address %s from mac list\n",
8577 format_mac_addr);
8578 return -ENOENT;
8579 }
8580
8581 mac_node = kzalloc_obj(*mac_node, GFP_ATOMIC);
8582 if (!mac_node) {
8583 spin_unlock_bh(&vport->mac_list_lock);
8584 return -ENOMEM;
8585 }
8586
8587 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8588
8589 mac_node->state = state;
8590 ether_addr_copy(mac_node->mac_addr, addr);
8591 list_add_tail(&mac_node->node, list);
8592
8593 spin_unlock_bh(&vport->mac_list_lock);
8594
8595 return 0;
8596 }
8597
hclge_add_uc_addr(struct hnae3_handle * handle,const unsigned char * addr)8598 static int hclge_add_uc_addr(struct hnae3_handle *handle,
8599 const unsigned char *addr)
8600 {
8601 struct hclge_vport *vport = hclge_get_vport(handle);
8602
8603 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC,
8604 addr);
8605 }
8606
hclge_add_uc_addr_common(struct hclge_vport * vport,const unsigned char * addr)8607 int hclge_add_uc_addr_common(struct hclge_vport *vport,
8608 const unsigned char *addr)
8609 {
8610 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8611 struct hclge_dev *hdev = vport->back;
8612 struct hclge_mac_vlan_tbl_entry_cmd req;
8613 struct hclge_desc desc;
8614 u16 egress_port = 0;
8615 int ret;
8616
8617 /* mac addr check */
8618 if (is_zero_ether_addr(addr) ||
8619 is_broadcast_ether_addr(addr) ||
8620 is_multicast_ether_addr(addr)) {
8621 hnae3_format_mac_addr(format_mac_addr, addr);
8622 dev_err(&hdev->pdev->dev,
8623 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n",
8624 format_mac_addr, is_zero_ether_addr(addr),
8625 is_broadcast_ether_addr(addr),
8626 is_multicast_ether_addr(addr));
8627 return -EINVAL;
8628 }
8629
8630 memset(&req, 0, sizeof(req));
8631
8632 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
8633 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
8634
8635 req.egress_port = cpu_to_le16(egress_port);
8636
8637 hclge_prepare_mac_addr(&req, addr, false);
8638
8639 /* Lookup the mac address in the mac_vlan table, and add
8640 * it if the entry is inexistent. Repeated unicast entry
8641 * is not allowed in the mac vlan table.
8642 */
8643 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
8644 if (ret == -ENOENT) {
8645 mutex_lock(&hdev->vport_lock);
8646 if (!hclge_is_umv_space_full(vport, false)) {
8647 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
8648 if (!ret)
8649 hclge_update_umv_space(vport, false);
8650 mutex_unlock(&hdev->vport_lock);
8651 return ret;
8652 }
8653 mutex_unlock(&hdev->vport_lock);
8654
8655 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE))
8656 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
8657 hdev->priv_umv_size);
8658
8659 return -ENOSPC;
8660 }
8661
8662 /* check if we just hit the duplicate */
8663 if (!ret)
8664 return -EEXIST;
8665
8666 return ret;
8667 }
8668
hclge_rm_uc_addr(struct hnae3_handle * handle,const unsigned char * addr)8669 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
8670 const unsigned char *addr)
8671 {
8672 struct hclge_vport *vport = hclge_get_vport(handle);
8673
8674 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC,
8675 addr);
8676 }
8677
hclge_rm_uc_addr_common(struct hclge_vport * vport,const unsigned char * addr)8678 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
8679 const unsigned char *addr)
8680 {
8681 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8682 struct hclge_dev *hdev = vport->back;
8683 struct hclge_mac_vlan_tbl_entry_cmd req;
8684 int ret;
8685
8686 /* mac addr check */
8687 if (is_zero_ether_addr(addr) ||
8688 is_broadcast_ether_addr(addr) ||
8689 is_multicast_ether_addr(addr)) {
8690 hnae3_format_mac_addr(format_mac_addr, addr);
8691 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n",
8692 format_mac_addr);
8693 return -EINVAL;
8694 }
8695
8696 memset(&req, 0, sizeof(req));
8697 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
8698 hclge_prepare_mac_addr(&req, addr, false);
8699 ret = hclge_remove_mac_vlan_tbl(vport, &req);
8700 if (!ret || ret == -ENOENT) {
8701 mutex_lock(&hdev->vport_lock);
8702 hclge_update_umv_space(vport, true);
8703 mutex_unlock(&hdev->vport_lock);
8704 return 0;
8705 }
8706
8707 return ret;
8708 }
8709
hclge_add_mc_addr(struct hnae3_handle * handle,const unsigned char * addr)8710 static int hclge_add_mc_addr(struct hnae3_handle *handle,
8711 const unsigned char *addr)
8712 {
8713 struct hclge_vport *vport = hclge_get_vport(handle);
8714
8715 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC,
8716 addr);
8717 }
8718
hclge_add_mc_addr_common(struct hclge_vport * vport,const unsigned char * addr)8719 int hclge_add_mc_addr_common(struct hclge_vport *vport,
8720 const unsigned char *addr)
8721 {
8722 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8723 struct hclge_dev *hdev = vport->back;
8724 struct hclge_mac_vlan_tbl_entry_cmd req;
8725 struct hclge_desc desc[3];
8726 bool is_new_addr = false;
8727 int status;
8728
8729 /* mac addr check */
8730 if (!is_multicast_ether_addr(addr)) {
8731 hnae3_format_mac_addr(format_mac_addr, addr);
8732 dev_err(&hdev->pdev->dev,
8733 "Add mc mac err! invalid mac:%s.\n",
8734 format_mac_addr);
8735 return -EINVAL;
8736 }
8737 memset(&req, 0, sizeof(req));
8738 hclge_prepare_mac_addr(&req, addr, true);
8739 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8740 if (status) {
8741 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) &&
8742 hdev->used_mc_mac_num >=
8743 hdev->ae_dev->dev_specs.mc_mac_size)
8744 goto err_no_space;
8745
8746 is_new_addr = true;
8747
8748 /* This mac addr do not exist, add new entry for it */
8749 memset(desc[0].data, 0, sizeof(desc[0].data));
8750 memset(desc[1].data, 0, sizeof(desc[0].data));
8751 memset(desc[2].data, 0, sizeof(desc[0].data));
8752 }
8753 status = hclge_update_desc_vfid(desc, vport->vport_id, false);
8754 if (status)
8755 return status;
8756 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8757 if (status == -ENOSPC)
8758 goto err_no_space;
8759 else if (!status && is_new_addr)
8760 hdev->used_mc_mac_num++;
8761
8762 return status;
8763
8764 err_no_space:
8765 /* if already overflow, not to print each time */
8766 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
8767 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8768 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
8769 }
8770
8771 return -ENOSPC;
8772 }
8773
hclge_rm_mc_addr(struct hnae3_handle * handle,const unsigned char * addr)8774 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
8775 const unsigned char *addr)
8776 {
8777 struct hclge_vport *vport = hclge_get_vport(handle);
8778
8779 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC,
8780 addr);
8781 }
8782
hclge_rm_mc_addr_common(struct hclge_vport * vport,const unsigned char * addr)8783 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
8784 const unsigned char *addr)
8785 {
8786 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8787 struct hclge_dev *hdev = vport->back;
8788 struct hclge_mac_vlan_tbl_entry_cmd req;
8789 enum hclge_comm_cmd_status status;
8790 struct hclge_desc desc[3];
8791
8792 /* mac addr check */
8793 if (!is_multicast_ether_addr(addr)) {
8794 hnae3_format_mac_addr(format_mac_addr, addr);
8795 dev_dbg(&hdev->pdev->dev,
8796 "Remove mc mac err! invalid mac:%s.\n",
8797 format_mac_addr);
8798 return -EINVAL;
8799 }
8800
8801 memset(&req, 0, sizeof(req));
8802 hclge_prepare_mac_addr(&req, addr, true);
8803 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8804 if (!status) {
8805 /* This mac addr exist, remove this handle's VFID for it */
8806 status = hclge_update_desc_vfid(desc, vport->vport_id, true);
8807 if (status)
8808 return status;
8809
8810 if (hclge_is_all_function_id_zero(desc)) {
8811 /* All the vfid is zero, so need to delete this entry */
8812 status = hclge_remove_mac_vlan_tbl(vport, &req);
8813 if (!status)
8814 hdev->used_mc_mac_num--;
8815 } else {
8816 /* Not all the vfid is zero, update the vfid */
8817 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8818 }
8819 } else if (status == -ENOENT) {
8820 status = 0;
8821 }
8822
8823 return status;
8824 }
8825
hclge_sync_vport_mac_list(struct hclge_vport * vport,struct list_head * list,enum HCLGE_MAC_ADDR_TYPE mac_type)8826 static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
8827 struct list_head *list,
8828 enum HCLGE_MAC_ADDR_TYPE mac_type)
8829 {
8830 int (*sync)(struct hclge_vport *vport, const unsigned char *addr);
8831 struct hclge_mac_node *mac_node, *tmp;
8832 int ret;
8833
8834 if (mac_type == HCLGE_MAC_ADDR_UC)
8835 sync = hclge_add_uc_addr_common;
8836 else
8837 sync = hclge_add_mc_addr_common;
8838
8839 list_for_each_entry_safe(mac_node, tmp, list, node) {
8840 ret = sync(vport, mac_node->mac_addr);
8841 if (!ret) {
8842 mac_node->state = HCLGE_MAC_ACTIVE;
8843 } else {
8844 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8845 &vport->state);
8846
8847 /* If one unicast mac address is existing in hardware,
8848 * we need to try whether other unicast mac addresses
8849 * are new addresses that can be added.
8850 * Multicast mac address can be reusable, even though
8851 * there is no space to add new multicast mac address,
8852 * we should check whether other mac addresses are
8853 * existing in hardware for reuse.
8854 */
8855 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
8856 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
8857 break;
8858 }
8859 }
8860 }
8861
hclge_unsync_vport_mac_list(struct hclge_vport * vport,struct list_head * list,enum HCLGE_MAC_ADDR_TYPE mac_type)8862 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport,
8863 struct list_head *list,
8864 enum HCLGE_MAC_ADDR_TYPE mac_type)
8865 {
8866 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8867 struct hclge_mac_node *mac_node, *tmp;
8868 int ret;
8869
8870 if (mac_type == HCLGE_MAC_ADDR_UC)
8871 unsync = hclge_rm_uc_addr_common;
8872 else
8873 unsync = hclge_rm_mc_addr_common;
8874
8875 list_for_each_entry_safe(mac_node, tmp, list, node) {
8876 ret = unsync(vport, mac_node->mac_addr);
8877 if (!ret || ret == -ENOENT) {
8878 list_del(&mac_node->node);
8879 kfree(mac_node);
8880 } else {
8881 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8882 &vport->state);
8883 break;
8884 }
8885 }
8886 }
8887
hclge_sync_from_add_list(struct list_head * add_list,struct list_head * mac_list)8888 static bool hclge_sync_from_add_list(struct list_head *add_list,
8889 struct list_head *mac_list)
8890 {
8891 struct hclge_mac_node *mac_node, *tmp, *new_node;
8892 bool all_added = true;
8893
8894 list_for_each_entry_safe(mac_node, tmp, add_list, node) {
8895 if (mac_node->state == HCLGE_MAC_TO_ADD)
8896 all_added = false;
8897
8898 /* if the mac address from tmp_add_list is not in the
8899 * uc/mc_mac_list, it means have received a TO_DEL request
8900 * during the time window of adding the mac address into mac
8901 * table. if mac_node state is ACTIVE, then change it to TO_DEL,
8902 * then it will be removed at next time. else it must be TO_ADD,
8903 * this address hasn't been added into mac table,
8904 * so just remove the mac node.
8905 */
8906 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8907 if (new_node) {
8908 hclge_update_mac_node(new_node, mac_node->state);
8909 list_del(&mac_node->node);
8910 kfree(mac_node);
8911 } else if (mac_node->state == HCLGE_MAC_ACTIVE) {
8912 mac_node->state = HCLGE_MAC_TO_DEL;
8913 list_move_tail(&mac_node->node, mac_list);
8914 } else {
8915 list_del(&mac_node->node);
8916 kfree(mac_node);
8917 }
8918 }
8919
8920 return all_added;
8921 }
8922
hclge_sync_from_del_list(struct list_head * del_list,struct list_head * mac_list)8923 static void hclge_sync_from_del_list(struct list_head *del_list,
8924 struct list_head *mac_list)
8925 {
8926 struct hclge_mac_node *mac_node, *tmp, *new_node;
8927
8928 list_for_each_entry_safe(mac_node, tmp, del_list, node) {
8929 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8930 if (new_node) {
8931 /* If the mac addr exists in the mac list, it means
8932 * received a new TO_ADD request during the time window
8933 * of configuring the mac address. For the mac node
8934 * state is TO_ADD, and the address is already in the
8935 * in the hardware(due to delete fail), so we just need
8936 * to change the mac node state to ACTIVE.
8937 */
8938 new_node->state = HCLGE_MAC_ACTIVE;
8939 list_del(&mac_node->node);
8940 kfree(mac_node);
8941 } else {
8942 list_move_tail(&mac_node->node, mac_list);
8943 }
8944 }
8945 }
8946
hclge_update_overflow_flags(struct hclge_vport * vport,enum HCLGE_MAC_ADDR_TYPE mac_type,bool is_all_added)8947 static void hclge_update_overflow_flags(struct hclge_vport *vport,
8948 enum HCLGE_MAC_ADDR_TYPE mac_type,
8949 bool is_all_added)
8950 {
8951 if (mac_type == HCLGE_MAC_ADDR_UC) {
8952 if (is_all_added)
8953 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE;
8954 else if (hclge_is_umv_space_full(vport, true))
8955 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE;
8956 } else {
8957 if (is_all_added)
8958 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE;
8959 else
8960 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8961 }
8962 }
8963
hclge_sync_vport_mac_table(struct hclge_vport * vport,enum HCLGE_MAC_ADDR_TYPE mac_type)8964 static void hclge_sync_vport_mac_table(struct hclge_vport *vport,
8965 enum HCLGE_MAC_ADDR_TYPE mac_type)
8966 {
8967 struct hclge_mac_node *mac_node, *tmp, *new_node;
8968 struct list_head tmp_add_list, tmp_del_list;
8969 struct list_head *list;
8970 bool all_added;
8971
8972 INIT_LIST_HEAD(&tmp_add_list);
8973 INIT_LIST_HEAD(&tmp_del_list);
8974
8975 /* move the mac addr to the tmp_add_list and tmp_del_list, then
8976 * we can add/delete these mac addr outside the spin lock
8977 */
8978 list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8979 &vport->uc_mac_list : &vport->mc_mac_list;
8980
8981 spin_lock_bh(&vport->mac_list_lock);
8982
8983 list_for_each_entry_safe(mac_node, tmp, list, node) {
8984 switch (mac_node->state) {
8985 case HCLGE_MAC_TO_DEL:
8986 list_move_tail(&mac_node->node, &tmp_del_list);
8987 break;
8988 case HCLGE_MAC_TO_ADD:
8989 new_node = kzalloc_obj(*new_node, GFP_ATOMIC);
8990 if (!new_node)
8991 goto stop_traverse;
8992 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
8993 new_node->state = mac_node->state;
8994 list_add_tail(&new_node->node, &tmp_add_list);
8995 break;
8996 default:
8997 break;
8998 }
8999 }
9000
9001 stop_traverse:
9002 spin_unlock_bh(&vport->mac_list_lock);
9003
9004 /* delete first, in order to get max mac table space for adding */
9005 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
9006 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
9007
9008 /* if some mac addresses were added/deleted fail, move back to the
9009 * mac_list, and retry at next time.
9010 */
9011 spin_lock_bh(&vport->mac_list_lock);
9012
9013 hclge_sync_from_del_list(&tmp_del_list, list);
9014 all_added = hclge_sync_from_add_list(&tmp_add_list, list);
9015
9016 spin_unlock_bh(&vport->mac_list_lock);
9017
9018 hclge_update_overflow_flags(vport, mac_type, all_added);
9019 }
9020
hclge_need_sync_mac_table(struct hclge_vport * vport)9021 static bool hclge_need_sync_mac_table(struct hclge_vport *vport)
9022 {
9023 struct hclge_dev *hdev = vport->back;
9024
9025 if (test_bit(vport->vport_id, hdev->vport_config_block))
9026 return false;
9027
9028 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state))
9029 return true;
9030
9031 return false;
9032 }
9033
hclge_sync_mac_table(struct hclge_dev * hdev)9034 static void hclge_sync_mac_table(struct hclge_dev *hdev)
9035 {
9036 int i;
9037
9038 for (i = 0; i < hdev->num_alloc_vport; i++) {
9039 struct hclge_vport *vport = &hdev->vport[i];
9040
9041 if (!hclge_need_sync_mac_table(vport))
9042 continue;
9043
9044 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC);
9045 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC);
9046 }
9047 }
9048
hclge_build_del_list(struct list_head * list,bool is_del_list,struct list_head * tmp_del_list)9049 static void hclge_build_del_list(struct list_head *list,
9050 bool is_del_list,
9051 struct list_head *tmp_del_list)
9052 {
9053 struct hclge_mac_node *mac_cfg, *tmp;
9054
9055 list_for_each_entry_safe(mac_cfg, tmp, list, node) {
9056 switch (mac_cfg->state) {
9057 case HCLGE_MAC_TO_DEL:
9058 case HCLGE_MAC_ACTIVE:
9059 list_move_tail(&mac_cfg->node, tmp_del_list);
9060 break;
9061 case HCLGE_MAC_TO_ADD:
9062 if (is_del_list) {
9063 list_del(&mac_cfg->node);
9064 kfree(mac_cfg);
9065 }
9066 break;
9067 }
9068 }
9069 }
9070
hclge_unsync_del_list(struct hclge_vport * vport,int (* unsync)(struct hclge_vport * vport,const unsigned char * addr),bool is_del_list,struct list_head * tmp_del_list)9071 static void hclge_unsync_del_list(struct hclge_vport *vport,
9072 int (*unsync)(struct hclge_vport *vport,
9073 const unsigned char *addr),
9074 bool is_del_list,
9075 struct list_head *tmp_del_list)
9076 {
9077 struct hclge_mac_node *mac_cfg, *tmp;
9078 int ret;
9079
9080 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) {
9081 ret = unsync(vport, mac_cfg->mac_addr);
9082 if (!ret || ret == -ENOENT) {
9083 /* clear all mac addr from hardware, but remain these
9084 * mac addr in the mac list, and restore them after
9085 * vf reset finished.
9086 */
9087 if (!is_del_list &&
9088 mac_cfg->state == HCLGE_MAC_ACTIVE) {
9089 mac_cfg->state = HCLGE_MAC_TO_ADD;
9090 } else {
9091 list_del(&mac_cfg->node);
9092 kfree(mac_cfg);
9093 }
9094 } else if (is_del_list) {
9095 mac_cfg->state = HCLGE_MAC_TO_DEL;
9096 }
9097 }
9098 }
9099
hclge_rm_vport_all_mac_table(struct hclge_vport * vport,bool is_del_list,enum HCLGE_MAC_ADDR_TYPE mac_type)9100 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
9101 enum HCLGE_MAC_ADDR_TYPE mac_type)
9102 {
9103 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
9104 struct hclge_dev *hdev = vport->back;
9105 struct list_head tmp_del_list, *list;
9106
9107 if (mac_type == HCLGE_MAC_ADDR_UC) {
9108 list = &vport->uc_mac_list;
9109 unsync = hclge_rm_uc_addr_common;
9110 } else {
9111 list = &vport->mc_mac_list;
9112 unsync = hclge_rm_mc_addr_common;
9113 }
9114
9115 INIT_LIST_HEAD(&tmp_del_list);
9116
9117 if (!is_del_list)
9118 set_bit(vport->vport_id, hdev->vport_config_block);
9119
9120 spin_lock_bh(&vport->mac_list_lock);
9121
9122 hclge_build_del_list(list, is_del_list, &tmp_del_list);
9123
9124 spin_unlock_bh(&vport->mac_list_lock);
9125
9126 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list);
9127
9128 spin_lock_bh(&vport->mac_list_lock);
9129
9130 hclge_sync_from_del_list(&tmp_del_list, list);
9131
9132 spin_unlock_bh(&vport->mac_list_lock);
9133 }
9134
9135 /* remove all mac address when uninitailize */
hclge_uninit_vport_mac_list(struct hclge_vport * vport,enum HCLGE_MAC_ADDR_TYPE mac_type)9136 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport,
9137 enum HCLGE_MAC_ADDR_TYPE mac_type)
9138 {
9139 struct hclge_mac_node *mac_node, *tmp;
9140 struct hclge_dev *hdev = vport->back;
9141 struct list_head tmp_del_list, *list;
9142
9143 INIT_LIST_HEAD(&tmp_del_list);
9144
9145 list = (mac_type == HCLGE_MAC_ADDR_UC) ?
9146 &vport->uc_mac_list : &vport->mc_mac_list;
9147
9148 spin_lock_bh(&vport->mac_list_lock);
9149
9150 list_for_each_entry_safe(mac_node, tmp, list, node) {
9151 switch (mac_node->state) {
9152 case HCLGE_MAC_TO_DEL:
9153 case HCLGE_MAC_ACTIVE:
9154 list_move_tail(&mac_node->node, &tmp_del_list);
9155 break;
9156 case HCLGE_MAC_TO_ADD:
9157 list_del(&mac_node->node);
9158 kfree(mac_node);
9159 break;
9160 }
9161 }
9162
9163 spin_unlock_bh(&vport->mac_list_lock);
9164
9165 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
9166
9167 if (!list_empty(&tmp_del_list))
9168 dev_warn(&hdev->pdev->dev,
9169 "uninit %s mac list for vport %u not completely.\n",
9170 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc",
9171 vport->vport_id);
9172
9173 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) {
9174 list_del(&mac_node->node);
9175 kfree(mac_node);
9176 }
9177 }
9178
hclge_uninit_mac_table(struct hclge_dev * hdev)9179 static void hclge_uninit_mac_table(struct hclge_dev *hdev)
9180 {
9181 struct hclge_vport *vport;
9182 int i;
9183
9184 for (i = 0; i < hdev->num_alloc_vport; i++) {
9185 vport = &hdev->vport[i];
9186 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC);
9187 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC);
9188 }
9189 }
9190
hclge_get_mac_ethertype_cmd_status(struct hclge_dev * hdev,u16 cmdq_resp,u8 resp_code)9191 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
9192 u16 cmdq_resp, u8 resp_code)
9193 {
9194 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
9195 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
9196 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
9197 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
9198
9199 int return_status;
9200
9201 if (cmdq_resp) {
9202 dev_err(&hdev->pdev->dev,
9203 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
9204 cmdq_resp);
9205 return -EIO;
9206 }
9207
9208 switch (resp_code) {
9209 case HCLGE_ETHERTYPE_SUCCESS_ADD:
9210 case HCLGE_ETHERTYPE_ALREADY_ADD:
9211 return_status = 0;
9212 break;
9213 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
9214 dev_err(&hdev->pdev->dev,
9215 "add mac ethertype failed for manager table overflow.\n");
9216 return_status = -EIO;
9217 break;
9218 case HCLGE_ETHERTYPE_KEY_CONFLICT:
9219 dev_err(&hdev->pdev->dev,
9220 "add mac ethertype failed for key conflict.\n");
9221 return_status = -EIO;
9222 break;
9223 default:
9224 dev_err(&hdev->pdev->dev,
9225 "add mac ethertype failed for undefined, code=%u.\n",
9226 resp_code);
9227 return_status = -EIO;
9228 }
9229
9230 return return_status;
9231 }
9232
hclge_set_vf_mac(struct hnae3_handle * handle,int vf,u8 * mac_addr)9233 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
9234 u8 *mac_addr)
9235 {
9236 struct hclge_vport *vport = hclge_get_vport(handle);
9237 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9238 struct hclge_dev *hdev = vport->back;
9239
9240 vport = hclge_get_vf_vport(hdev, vf);
9241 if (!vport)
9242 return -EINVAL;
9243
9244 hnae3_format_mac_addr(format_mac_addr, mac_addr);
9245 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) {
9246 dev_info(&hdev->pdev->dev,
9247 "Specified MAC(=%s) is same as before, no change committed!\n",
9248 format_mac_addr);
9249 return 0;
9250 }
9251
9252 ether_addr_copy(vport->vf_info.mac, mac_addr);
9253
9254 /* there is a timewindow for PF to know VF unalive, it may
9255 * cause send mailbox fail, but it doesn't matter, VF will
9256 * query it when reinit.
9257 */
9258 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
9259 dev_info(&hdev->pdev->dev,
9260 "MAC of VF %d has been set to %s, and it will be reinitialized!\n",
9261 vf, format_mac_addr);
9262 (void)hclge_inform_reset_assert_to_vf(vport);
9263 return 0;
9264 }
9265
9266 dev_info(&hdev->pdev->dev,
9267 "MAC of VF %d has been set to %s, will be active after VF reset\n",
9268 vf, format_mac_addr);
9269 return 0;
9270 }
9271
hclge_add_mgr_tbl(struct hclge_dev * hdev,const struct hclge_mac_mgr_tbl_entry_cmd * req)9272 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
9273 const struct hclge_mac_mgr_tbl_entry_cmd *req)
9274 {
9275 struct hclge_desc desc;
9276 u8 resp_code;
9277 u16 retval;
9278 int ret;
9279
9280 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
9281 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
9282
9283 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9284 if (ret) {
9285 dev_err(&hdev->pdev->dev,
9286 "add mac ethertype failed for cmd_send, ret =%d.\n",
9287 ret);
9288 return ret;
9289 }
9290
9291 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
9292 retval = le16_to_cpu(desc.retval);
9293
9294 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
9295 }
9296
init_mgr_tbl(struct hclge_dev * hdev)9297 static int init_mgr_tbl(struct hclge_dev *hdev)
9298 {
9299 int ret;
9300 u32 i;
9301
9302 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
9303 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
9304 if (ret) {
9305 dev_err(&hdev->pdev->dev,
9306 "add mac ethertype failed, ret =%d.\n",
9307 ret);
9308 return ret;
9309 }
9310 }
9311
9312 return 0;
9313 }
9314
hclge_get_mac_addr(struct hnae3_handle * handle,u8 * p)9315 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
9316 {
9317 struct hclge_vport *vport = hclge_get_vport(handle);
9318 struct hclge_dev *hdev = vport->back;
9319
9320 ether_addr_copy(p, hdev->hw.mac.mac_addr);
9321 }
9322
hclge_update_mac_node_for_dev_addr(struct hclge_vport * vport,const u8 * old_addr,const u8 * new_addr)9323 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
9324 const u8 *old_addr, const u8 *new_addr)
9325 {
9326 struct list_head *list = &vport->uc_mac_list;
9327 struct hclge_mac_node *old_node, *new_node;
9328
9329 new_node = hclge_find_mac_node(list, new_addr);
9330 if (!new_node) {
9331 new_node = kzalloc_obj(*new_node, GFP_ATOMIC);
9332 if (!new_node)
9333 return -ENOMEM;
9334
9335 new_node->state = HCLGE_MAC_TO_ADD;
9336 ether_addr_copy(new_node->mac_addr, new_addr);
9337 list_add(&new_node->node, list);
9338 } else {
9339 if (new_node->state == HCLGE_MAC_TO_DEL)
9340 new_node->state = HCLGE_MAC_ACTIVE;
9341
9342 /* make sure the new addr is in the list head, avoid dev
9343 * addr may be not re-added into mac table for the umv space
9344 * limitation after global/imp reset which will clear mac
9345 * table by hardware.
9346 */
9347 list_move(&new_node->node, list);
9348 }
9349
9350 if (old_addr && !ether_addr_equal(old_addr, new_addr)) {
9351 old_node = hclge_find_mac_node(list, old_addr);
9352 if (old_node) {
9353 if (old_node->state == HCLGE_MAC_TO_ADD) {
9354 list_del(&old_node->node);
9355 kfree(old_node);
9356 } else {
9357 old_node->state = HCLGE_MAC_TO_DEL;
9358 }
9359 }
9360 }
9361
9362 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
9363
9364 return 0;
9365 }
9366
hclge_set_mac_addr(struct hnae3_handle * handle,const void * p,bool is_first)9367 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p,
9368 bool is_first)
9369 {
9370 const unsigned char *new_addr = (const unsigned char *)p;
9371 struct hclge_vport *vport = hclge_get_vport(handle);
9372 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9373 struct hclge_dev *hdev = vport->back;
9374 unsigned char *old_addr = NULL;
9375 int ret;
9376
9377 /* mac addr check */
9378 if (is_zero_ether_addr(new_addr) ||
9379 is_broadcast_ether_addr(new_addr) ||
9380 is_multicast_ether_addr(new_addr)) {
9381 hnae3_format_mac_addr(format_mac_addr, new_addr);
9382 dev_err(&hdev->pdev->dev,
9383 "change uc mac err! invalid mac: %s.\n",
9384 format_mac_addr);
9385 return -EINVAL;
9386 }
9387
9388 ret = hclge_pause_addr_cfg(hdev, new_addr);
9389 if (ret) {
9390 dev_err(&hdev->pdev->dev,
9391 "failed to configure mac pause address, ret = %d\n",
9392 ret);
9393 return ret;
9394 }
9395
9396 if (!is_first)
9397 old_addr = hdev->hw.mac.mac_addr;
9398
9399 spin_lock_bh(&vport->mac_list_lock);
9400 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr);
9401 if (ret) {
9402 hnae3_format_mac_addr(format_mac_addr, new_addr);
9403 dev_err(&hdev->pdev->dev,
9404 "failed to change the mac addr:%s, ret = %d\n",
9405 format_mac_addr, ret);
9406 spin_unlock_bh(&vport->mac_list_lock);
9407
9408 if (!is_first)
9409 hclge_pause_addr_cfg(hdev, old_addr);
9410
9411 return ret;
9412 }
9413 /* we must update dev addr with spin lock protect, preventing dev addr
9414 * being removed by set_rx_mode path.
9415 */
9416 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
9417 spin_unlock_bh(&vport->mac_list_lock);
9418
9419 hclge_task_schedule(hdev, 0);
9420
9421 return 0;
9422 }
9423
hclge_mii_ioctl(struct hclge_dev * hdev,struct ifreq * ifr,int cmd)9424 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
9425 {
9426 struct mii_ioctl_data *data = if_mii(ifr);
9427
9428 if (!hnae3_dev_phy_imp_supported(hdev))
9429 return -EOPNOTSUPP;
9430
9431 switch (cmd) {
9432 case SIOCGMIIPHY:
9433 data->phy_id = hdev->hw.mac.phy_addr;
9434 /* this command reads phy id and register at the same time */
9435 fallthrough;
9436 case SIOCGMIIREG:
9437 return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out);
9438
9439 case SIOCSMIIREG:
9440 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);
9441 default:
9442 return -EOPNOTSUPP;
9443 }
9444 }
9445
hclge_do_ioctl(struct hnae3_handle * handle,struct ifreq * ifr,int cmd)9446 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
9447 int cmd)
9448 {
9449 struct hclge_vport *vport = hclge_get_vport(handle);
9450 struct hclge_dev *hdev = vport->back;
9451
9452 if (!hdev->hw.mac.phydev)
9453 return hclge_mii_ioctl(hdev, ifr, cmd);
9454
9455 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
9456 }
9457
hclge_set_port_vlan_filter_bypass(struct hclge_dev * hdev,u8 vf_id,bool bypass_en)9458 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id,
9459 bool bypass_en)
9460 {
9461 struct hclge_port_vlan_filter_bypass_cmd *req;
9462 struct hclge_desc desc;
9463 int ret;
9464
9465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false);
9466 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data;
9467 req->vf_id = vf_id;
9468 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B,
9469 bypass_en ? 1 : 0);
9470
9471 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9472 if (ret)
9473 dev_err(&hdev->pdev->dev,
9474 "failed to set vport%u port vlan filter bypass state, ret = %d.\n",
9475 vf_id, ret);
9476
9477 return ret;
9478 }
9479
hclge_set_vlan_filter_ctrl(struct hclge_dev * hdev,u8 vlan_type,u8 fe_type,bool filter_en,u8 vf_id)9480 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
9481 u8 fe_type, bool filter_en, u8 vf_id)
9482 {
9483 struct hclge_vlan_filter_ctrl_cmd *req;
9484 struct hclge_desc desc;
9485 int ret;
9486
9487 /* read current vlan filter parameter */
9488 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
9489 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
9490 req->vlan_type = vlan_type;
9491 req->vf_id = vf_id;
9492
9493 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9494 if (ret) {
9495 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n",
9496 vf_id, ret);
9497 return ret;
9498 }
9499
9500 /* modify and write new config parameter */
9501 hclge_comm_cmd_reuse_desc(&desc, false);
9502 req->vlan_fe = filter_en ?
9503 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type);
9504
9505 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9506 if (ret)
9507 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n",
9508 vf_id, ret);
9509
9510 return ret;
9511 }
9512
hclge_set_vport_vlan_filter(struct hclge_vport * vport,bool enable)9513 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable)
9514 {
9515 struct hclge_dev *hdev = vport->back;
9516 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
9517 int ret;
9518
9519 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9520 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9521 HCLGE_FILTER_FE_EGRESS_V1_B,
9522 enable, vport->vport_id);
9523
9524 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9525 HCLGE_FILTER_FE_EGRESS, enable,
9526 vport->vport_id);
9527 if (ret)
9528 return ret;
9529
9530 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
9531 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
9532 !enable);
9533 } else if (!vport->vport_id) {
9534 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
9535 enable = false;
9536
9537 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9538 HCLGE_FILTER_FE_INGRESS,
9539 enable, 0);
9540 }
9541
9542 return ret;
9543 }
9544
hclge_need_enable_vport_vlan_filter(struct hclge_vport * vport)9545 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport)
9546 {
9547 struct hnae3_handle *handle = &vport->nic;
9548 struct hclge_vport_vlan_cfg *vlan, *tmp;
9549 struct hclge_dev *hdev = vport->back;
9550
9551 if (vport->vport_id) {
9552 if (vport->port_base_vlan_cfg.state !=
9553 HNAE3_PORT_BASE_VLAN_DISABLE)
9554 return true;
9555
9556 if (vport->vf_info.trusted && vport->vf_info.request_uc_en)
9557 return false;
9558 } else if (handle->netdev_flags & HNAE3_USER_UPE) {
9559 return false;
9560 }
9561
9562 if (!vport->req_vlan_fltr_en)
9563 return false;
9564
9565 /* compatible with former device, always enable vlan filter */
9566 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
9567 return true;
9568
9569 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node)
9570 if (vlan->vlan_id != 0)
9571 return true;
9572
9573 return false;
9574 }
9575
__hclge_enable_vport_vlan_filter(struct hclge_vport * vport,bool request_en)9576 static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport,
9577 bool request_en)
9578 {
9579 bool need_en;
9580 int ret;
9581
9582 need_en = hclge_need_enable_vport_vlan_filter(vport);
9583 if (need_en == vport->cur_vlan_fltr_en)
9584 return 0;
9585
9586 ret = hclge_set_vport_vlan_filter(vport, need_en);
9587 if (ret)
9588 return ret;
9589
9590 vport->cur_vlan_fltr_en = need_en;
9591
9592 return 0;
9593 }
9594
hclge_enable_vport_vlan_filter(struct hclge_vport * vport,bool request_en)9595 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en)
9596 {
9597 struct hclge_dev *hdev = vport->back;
9598 int ret;
9599
9600 mutex_lock(&hdev->vport_lock);
9601 vport->req_vlan_fltr_en = request_en;
9602 ret = __hclge_enable_vport_vlan_filter(vport, request_en);
9603 mutex_unlock(&hdev->vport_lock);
9604
9605 return ret;
9606 }
9607
hclge_enable_vlan_filter(struct hnae3_handle * handle,bool enable)9608 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
9609 {
9610 struct hclge_vport *vport = hclge_get_vport(handle);
9611
9612 return hclge_enable_vport_vlan_filter(vport, enable);
9613 }
9614
hclge_set_vf_vlan_filter_cmd(struct hclge_dev * hdev,u16 vfid,bool is_kill,u16 vlan,struct hclge_desc * desc)9615 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
9616 bool is_kill, u16 vlan,
9617 struct hclge_desc *desc)
9618 {
9619 struct hclge_vlan_filter_vf_cfg_cmd *req0;
9620 struct hclge_vlan_filter_vf_cfg_cmd *req1;
9621 u8 vf_byte_val;
9622 u8 vf_byte_off;
9623 int ret;
9624
9625 hclge_cmd_setup_basic_desc(&desc[0],
9626 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9627 hclge_cmd_setup_basic_desc(&desc[1],
9628 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9629
9630 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
9631
9632 vf_byte_off = vfid / 8;
9633 vf_byte_val = 1 << (vfid % 8);
9634
9635 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9636 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
9637
9638 req0->vlan_id = cpu_to_le16(vlan);
9639 req0->vlan_cfg = is_kill;
9640
9641 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
9642 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
9643 else
9644 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
9645
9646 ret = hclge_cmd_send(&hdev->hw, desc, 2);
9647 if (ret) {
9648 dev_err(&hdev->pdev->dev,
9649 "Send vf vlan command fail, ret =%d.\n",
9650 ret);
9651 return ret;
9652 }
9653
9654 return 0;
9655 }
9656
hclge_check_vf_vlan_cmd_status(struct hclge_dev * hdev,u16 vfid,bool is_kill,struct hclge_desc * desc)9657 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid,
9658 bool is_kill, struct hclge_desc *desc)
9659 {
9660 struct hclge_vlan_filter_vf_cfg_cmd *req;
9661
9662 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9663
9664 if (!is_kill) {
9665 #define HCLGE_VF_VLAN_NO_ENTRY 2
9666 if (!req->resp_code || req->resp_code == 1)
9667 return 0;
9668
9669 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
9670 set_bit(vfid, hdev->vf_vlan_full);
9671 dev_warn(&hdev->pdev->dev,
9672 "vf vlan table is full, vf vlan filter is disabled\n");
9673 return 0;
9674 }
9675
9676 dev_err(&hdev->pdev->dev,
9677 "Add vf vlan filter fail, ret =%u.\n",
9678 req->resp_code);
9679 } else {
9680 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1
9681 if (!req->resp_code)
9682 return 0;
9683
9684 /* vf vlan filter is disabled when vf vlan table is full,
9685 * then new vlan id will not be added into vf vlan table.
9686 * Just return 0 without warning, avoid massive verbose
9687 * print logs when unload.
9688 */
9689 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
9690 return 0;
9691
9692 dev_err(&hdev->pdev->dev,
9693 "Kill vf vlan filter fail, ret =%u.\n",
9694 req->resp_code);
9695 }
9696
9697 return -EIO;
9698 }
9699
hclge_set_vf_vlan_common(struct hclge_dev * hdev,u16 vfid,bool is_kill,u16 vlan)9700 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
9701 bool is_kill, u16 vlan)
9702 {
9703 struct hclge_vport *vport = &hdev->vport[vfid];
9704 struct hclge_desc desc[2];
9705 int ret;
9706
9707 /* if vf vlan table is full, firmware will close vf vlan filter, it
9708 * is unable and unnecessary to add new vlan id to vf vlan filter.
9709 * If spoof check is enable, and vf vlan is full, it shouldn't add
9710 * new vlan, because tx packets with these vlan id will be dropped.
9711 */
9712 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
9713 if (vport->vf_info.spoofchk && vlan) {
9714 dev_err(&hdev->pdev->dev,
9715 "Can't add vlan due to spoof check is on and vf vlan table is full\n");
9716 return -EPERM;
9717 }
9718 return 0;
9719 }
9720
9721 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
9722 if (ret)
9723 return ret;
9724
9725 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc);
9726 }
9727
hclge_set_port_vlan_filter(struct hclge_dev * hdev,__be16 proto,u16 vlan_id,bool is_kill)9728 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
9729 u16 vlan_id, bool is_kill)
9730 {
9731 struct hclge_vlan_filter_pf_cfg_cmd *req;
9732 struct hclge_desc desc;
9733 u8 vlan_offset_byte_val;
9734 u8 vlan_offset_byte;
9735 u8 vlan_offset_160;
9736 int ret;
9737
9738 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
9739
9740 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP;
9741 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) /
9742 HCLGE_VLAN_BYTE_SIZE;
9743 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE);
9744
9745 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
9746 req->vlan_offset = vlan_offset_160;
9747 req->vlan_cfg = is_kill;
9748 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
9749
9750 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9751 if (ret)
9752 dev_err(&hdev->pdev->dev,
9753 "port vlan command, send fail, ret =%d.\n", ret);
9754 return ret;
9755 }
9756
hclge_need_update_port_vlan(struct hclge_dev * hdev,u16 vport_id,u16 vlan_id,bool is_kill)9757 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id,
9758 u16 vlan_id, bool is_kill)
9759 {
9760 /* vlan 0 may be added twice when 8021q module is enabled */
9761 if (!is_kill && !vlan_id &&
9762 test_bit(vport_id, hdev->vlan_table[vlan_id]))
9763 return false;
9764
9765 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
9766 dev_warn(&hdev->pdev->dev,
9767 "Add port vlan failed, vport %u is already in vlan %u\n",
9768 vport_id, vlan_id);
9769 return false;
9770 }
9771
9772 if (is_kill &&
9773 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
9774 dev_warn(&hdev->pdev->dev,
9775 "Delete port vlan failed, vport %u is not in vlan %u\n",
9776 vport_id, vlan_id);
9777 return false;
9778 }
9779
9780 return true;
9781 }
9782
hclge_set_vlan_filter_hw(struct hclge_dev * hdev,__be16 proto,u16 vport_id,u16 vlan_id,bool is_kill)9783 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
9784 u16 vport_id, u16 vlan_id,
9785 bool is_kill)
9786 {
9787 u16 vport_idx, vport_num = 0;
9788 int ret;
9789
9790 if (is_kill && !vlan_id)
9791 return 0;
9792
9793 if (vlan_id >= VLAN_N_VID)
9794 return -EINVAL;
9795
9796 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
9797 if (ret) {
9798 dev_err(&hdev->pdev->dev,
9799 "Set %u vport vlan filter config fail, ret =%d.\n",
9800 vport_id, ret);
9801 return ret;
9802 }
9803
9804 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill))
9805 return 0;
9806
9807 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
9808 vport_num++;
9809
9810 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
9811 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
9812 is_kill);
9813
9814 return ret;
9815 }
9816
hclge_set_vlan_tx_offload_cfg(struct hclge_vport * vport)9817 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
9818 {
9819 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
9820 struct hclge_vport_vtag_tx_cfg_cmd *req;
9821 struct hclge_dev *hdev = vport->back;
9822 struct hclge_desc desc;
9823 u16 bmap_index;
9824 int status;
9825
9826 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
9827
9828 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
9829 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
9830 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
9831 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
9832 vcfg->accept_tag1 ? 1 : 0);
9833 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
9834 vcfg->accept_untag1 ? 1 : 0);
9835 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
9836 vcfg->accept_tag2 ? 1 : 0);
9837 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
9838 vcfg->accept_untag2 ? 1 : 0);
9839 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
9840 vcfg->insert_tag1_en ? 1 : 0);
9841 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
9842 vcfg->insert_tag2_en ? 1 : 0);
9843 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B,
9844 vcfg->tag_shift_mode_en ? 1 : 0);
9845 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
9846
9847 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9848 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9849 HCLGE_VF_NUM_PER_BYTE;
9850 req->vf_bitmap[bmap_index] =
9851 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9852
9853 status = hclge_cmd_send(&hdev->hw, &desc, 1);
9854 if (status)
9855 dev_err(&hdev->pdev->dev,
9856 "Send port txvlan cfg command fail, ret =%d\n",
9857 status);
9858
9859 return status;
9860 }
9861
hclge_set_vlan_rx_offload_cfg(struct hclge_vport * vport)9862 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
9863 {
9864 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
9865 struct hclge_vport_vtag_rx_cfg_cmd *req;
9866 struct hclge_dev *hdev = vport->back;
9867 struct hclge_desc desc;
9868 u16 bmap_index;
9869 int status;
9870
9871 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
9872
9873 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
9874 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
9875 vcfg->strip_tag1_en ? 1 : 0);
9876 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
9877 vcfg->strip_tag2_en ? 1 : 0);
9878 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
9879 vcfg->vlan1_vlan_prionly ? 1 : 0);
9880 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
9881 vcfg->vlan2_vlan_prionly ? 1 : 0);
9882 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B,
9883 vcfg->strip_tag1_discard_en ? 1 : 0);
9884 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B,
9885 vcfg->strip_tag2_discard_en ? 1 : 0);
9886
9887 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9888 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9889 HCLGE_VF_NUM_PER_BYTE;
9890 req->vf_bitmap[bmap_index] =
9891 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9892
9893 status = hclge_cmd_send(&hdev->hw, &desc, 1);
9894 if (status)
9895 dev_err(&hdev->pdev->dev,
9896 "Send port rxvlan cfg command fail, ret =%d\n",
9897 status);
9898
9899 return status;
9900 }
9901
hclge_vlan_offload_cfg(struct hclge_vport * vport,u16 port_base_vlan_state,u16 vlan_tag,u8 qos)9902 static int hclge_vlan_offload_cfg(struct hclge_vport *vport,
9903 u16 port_base_vlan_state,
9904 u16 vlan_tag, u8 qos)
9905 {
9906 int ret;
9907
9908 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9909 vport->txvlan_cfg.accept_tag1 = true;
9910 vport->txvlan_cfg.insert_tag1_en = false;
9911 vport->txvlan_cfg.default_tag1 = 0;
9912 } else {
9913 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev);
9914
9915 vport->txvlan_cfg.accept_tag1 =
9916 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3;
9917 vport->txvlan_cfg.insert_tag1_en = true;
9918 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) |
9919 vlan_tag;
9920 }
9921
9922 vport->txvlan_cfg.accept_untag1 = true;
9923
9924 /* accept_tag2 and accept_untag2 are not supported on
9925 * pdev revision(0x20), new revision support them,
9926 * this two fields can not be configured by user.
9927 */
9928 vport->txvlan_cfg.accept_tag2 = true;
9929 vport->txvlan_cfg.accept_untag2 = true;
9930 vport->txvlan_cfg.insert_tag2_en = false;
9931 vport->txvlan_cfg.default_tag2 = 0;
9932 vport->txvlan_cfg.tag_shift_mode_en = true;
9933
9934 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9935 vport->rxvlan_cfg.strip_tag1_en = false;
9936 vport->rxvlan_cfg.strip_tag2_en =
9937 vport->rxvlan_cfg.rx_vlan_offload_en;
9938 vport->rxvlan_cfg.strip_tag2_discard_en = false;
9939 } else {
9940 vport->rxvlan_cfg.strip_tag1_en =
9941 vport->rxvlan_cfg.rx_vlan_offload_en;
9942 vport->rxvlan_cfg.strip_tag2_en = true;
9943 vport->rxvlan_cfg.strip_tag2_discard_en = true;
9944 }
9945
9946 vport->rxvlan_cfg.strip_tag1_discard_en = false;
9947 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
9948 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
9949
9950 ret = hclge_set_vlan_tx_offload_cfg(vport);
9951 if (ret)
9952 return ret;
9953
9954 return hclge_set_vlan_rx_offload_cfg(vport);
9955 }
9956
hclge_set_vlan_protocol_type(struct hclge_dev * hdev)9957 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
9958 {
9959 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
9960 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
9961 struct hclge_desc desc;
9962 int status;
9963
9964 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
9965 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
9966 rx_req->ot_fst_vlan_type =
9967 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
9968 rx_req->ot_sec_vlan_type =
9969 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
9970 rx_req->in_fst_vlan_type =
9971 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
9972 rx_req->in_sec_vlan_type =
9973 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
9974
9975 status = hclge_cmd_send(&hdev->hw, &desc, 1);
9976 if (status) {
9977 dev_err(&hdev->pdev->dev,
9978 "Send rxvlan protocol type command fail, ret =%d\n",
9979 status);
9980 return status;
9981 }
9982
9983 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
9984
9985 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
9986 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
9987 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
9988
9989 status = hclge_cmd_send(&hdev->hw, &desc, 1);
9990 if (status)
9991 dev_err(&hdev->pdev->dev,
9992 "Send txvlan protocol type command fail, ret =%d\n",
9993 status);
9994
9995 return status;
9996 }
9997
hclge_init_vlan_filter(struct hclge_dev * hdev)9998 static int hclge_init_vlan_filter(struct hclge_dev *hdev)
9999 {
10000 struct hclge_vport *vport;
10001 bool enable = true;
10002 int ret;
10003 int i;
10004
10005 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
10006 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
10007 HCLGE_FILTER_FE_EGRESS_V1_B,
10008 true, 0);
10009
10010 /* for revision 0x21, vf vlan filter is per function */
10011 for (i = 0; i < hdev->num_alloc_vport; i++) {
10012 vport = &hdev->vport[i];
10013 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
10014 HCLGE_FILTER_FE_EGRESS, true,
10015 vport->vport_id);
10016 if (ret)
10017 return ret;
10018 vport->cur_vlan_fltr_en = true;
10019 }
10020
10021 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) &&
10022 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps))
10023 enable = false;
10024
10025 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
10026 HCLGE_FILTER_FE_INGRESS, enable, 0);
10027 }
10028
hclge_init_vlan_type(struct hclge_dev * hdev)10029 static int hclge_init_vlan_type(struct hclge_dev *hdev)
10030 {
10031 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q;
10032 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q;
10033 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q;
10034 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q;
10035 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q;
10036 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q;
10037
10038 return hclge_set_vlan_protocol_type(hdev);
10039 }
10040
hclge_init_vport_vlan_offload(struct hclge_dev * hdev)10041 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev)
10042 {
10043 struct hclge_port_base_vlan_config *cfg;
10044 struct hclge_vport *vport;
10045 int ret;
10046 int i;
10047
10048 for (i = 0; i < hdev->num_alloc_vport; i++) {
10049 vport = &hdev->vport[i];
10050 cfg = &vport->port_base_vlan_cfg;
10051
10052 ret = hclge_vlan_offload_cfg(vport, cfg->state,
10053 cfg->vlan_info.vlan_tag,
10054 cfg->vlan_info.qos);
10055 if (ret)
10056 return ret;
10057 }
10058 return 0;
10059 }
10060
hclge_init_vlan_config(struct hclge_dev * hdev)10061 static int hclge_init_vlan_config(struct hclge_dev *hdev)
10062 {
10063 struct hnae3_handle *handle = &hdev->vport[0].nic;
10064 int ret;
10065
10066 ret = hclge_init_vlan_filter(hdev);
10067 if (ret)
10068 return ret;
10069
10070 ret = hclge_init_vlan_type(hdev);
10071 if (ret)
10072 return ret;
10073
10074 ret = hclge_init_vport_vlan_offload(hdev);
10075 if (ret)
10076 return ret;
10077
10078 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
10079 }
10080
hclge_add_vport_vlan_table(struct hclge_vport * vport,u16 vlan_id,bool writen_to_tbl)10081 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
10082 bool writen_to_tbl)
10083 {
10084 struct hclge_vport_vlan_cfg *vlan, *tmp;
10085 struct hclge_dev *hdev = vport->back;
10086
10087 mutex_lock(&hdev->vport_lock);
10088
10089 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10090 if (vlan->vlan_id == vlan_id) {
10091 mutex_unlock(&hdev->vport_lock);
10092 return;
10093 }
10094 }
10095
10096 vlan = kzalloc_obj(*vlan);
10097 if (!vlan) {
10098 mutex_unlock(&hdev->vport_lock);
10099 return;
10100 }
10101
10102 vlan->hd_tbl_status = writen_to_tbl;
10103 vlan->vlan_id = vlan_id;
10104
10105 list_add_tail(&vlan->node, &vport->vlan_list);
10106 mutex_unlock(&hdev->vport_lock);
10107 }
10108
hclge_add_vport_all_vlan_table(struct hclge_vport * vport)10109 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport)
10110 {
10111 struct hclge_vport_vlan_cfg *vlan, *tmp;
10112 struct hclge_dev *hdev = vport->back;
10113 int ret;
10114
10115 mutex_lock(&hdev->vport_lock);
10116
10117 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10118 if (!vlan->hd_tbl_status) {
10119 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10120 vport->vport_id,
10121 vlan->vlan_id, false);
10122 if (ret) {
10123 dev_err(&hdev->pdev->dev,
10124 "restore vport vlan list failed, ret=%d\n",
10125 ret);
10126
10127 mutex_unlock(&hdev->vport_lock);
10128 return ret;
10129 }
10130 }
10131 vlan->hd_tbl_status = true;
10132 }
10133
10134 mutex_unlock(&hdev->vport_lock);
10135
10136 return 0;
10137 }
10138
hclge_rm_vport_vlan_table(struct hclge_vport * vport,u16 vlan_id,bool is_write_tbl)10139 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
10140 bool is_write_tbl)
10141 {
10142 struct hclge_vport_vlan_cfg *vlan, *tmp;
10143 struct hclge_dev *hdev = vport->back;
10144
10145 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10146 if (vlan->vlan_id == vlan_id) {
10147 if (is_write_tbl && vlan->hd_tbl_status)
10148 hclge_set_vlan_filter_hw(hdev,
10149 htons(ETH_P_8021Q),
10150 vport->vport_id,
10151 vlan_id,
10152 true);
10153
10154 list_del(&vlan->node);
10155 kfree(vlan);
10156 break;
10157 }
10158 }
10159 }
10160
hclge_rm_vport_all_vlan_table(struct hclge_vport * vport,bool is_del_list)10161 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list)
10162 {
10163 struct hclge_vport_vlan_cfg *vlan, *tmp;
10164 struct hclge_dev *hdev = vport->back;
10165
10166 mutex_lock(&hdev->vport_lock);
10167
10168 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10169 if (vlan->hd_tbl_status)
10170 hclge_set_vlan_filter_hw(hdev,
10171 htons(ETH_P_8021Q),
10172 vport->vport_id,
10173 vlan->vlan_id,
10174 true);
10175
10176 vlan->hd_tbl_status = false;
10177 if (is_del_list) {
10178 list_del(&vlan->node);
10179 kfree(vlan);
10180 }
10181 }
10182 clear_bit(vport->vport_id, hdev->vf_vlan_full);
10183 mutex_unlock(&hdev->vport_lock);
10184 }
10185
hclge_uninit_vport_vlan_table(struct hclge_dev * hdev)10186 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
10187 {
10188 struct hclge_vport_vlan_cfg *vlan, *tmp;
10189 struct hclge_vport *vport;
10190 int i;
10191
10192 mutex_lock(&hdev->vport_lock);
10193
10194 for (i = 0; i < hdev->num_alloc_vport; i++) {
10195 vport = &hdev->vport[i];
10196 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10197 list_del(&vlan->node);
10198 kfree(vlan);
10199 }
10200 }
10201
10202 mutex_unlock(&hdev->vport_lock);
10203 }
10204
hclge_restore_vport_port_base_vlan_config(struct hclge_dev * hdev)10205 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev)
10206 {
10207 struct hclge_vlan_info *vlan_info;
10208 struct hclge_vport *vport;
10209 u16 vlan_proto;
10210 u16 vlan_id;
10211 u16 state;
10212 int vf_id;
10213 int ret;
10214
10215 /* PF should restore all vfs port base vlan */
10216 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) {
10217 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM];
10218 vlan_info = vport->port_base_vlan_cfg.tbl_sta ?
10219 &vport->port_base_vlan_cfg.vlan_info :
10220 &vport->port_base_vlan_cfg.old_vlan_info;
10221
10222 vlan_id = vlan_info->vlan_tag;
10223 vlan_proto = vlan_info->vlan_proto;
10224 state = vport->port_base_vlan_cfg.state;
10225
10226 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) {
10227 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]);
10228 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto),
10229 vport->vport_id,
10230 vlan_id, false);
10231 vport->port_base_vlan_cfg.tbl_sta = ret == 0;
10232 }
10233 }
10234 }
10235
hclge_restore_vport_vlan_table(struct hclge_vport * vport)10236 void hclge_restore_vport_vlan_table(struct hclge_vport *vport)
10237 {
10238 struct hclge_vport_vlan_cfg *vlan, *tmp;
10239 struct hclge_dev *hdev = vport->back;
10240 int ret;
10241
10242 mutex_lock(&hdev->vport_lock);
10243
10244 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10245 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10246 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10247 vport->vport_id,
10248 vlan->vlan_id, false);
10249 if (ret)
10250 break;
10251 vlan->hd_tbl_status = true;
10252 }
10253 }
10254
10255 mutex_unlock(&hdev->vport_lock);
10256 }
10257
10258 /* For global reset and imp reset, hardware will clear the mac table,
10259 * so we change the mac address state from ACTIVE to TO_ADD, then they
10260 * can be restored in the service task after reset complete. Furtherly,
10261 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to
10262 * be restored after reset, so just remove these mac nodes from mac_list.
10263 */
hclge_mac_node_convert_for_reset(struct list_head * list)10264 static void hclge_mac_node_convert_for_reset(struct list_head *list)
10265 {
10266 struct hclge_mac_node *mac_node, *tmp;
10267
10268 list_for_each_entry_safe(mac_node, tmp, list, node) {
10269 if (mac_node->state == HCLGE_MAC_ACTIVE) {
10270 mac_node->state = HCLGE_MAC_TO_ADD;
10271 } else if (mac_node->state == HCLGE_MAC_TO_DEL) {
10272 list_del(&mac_node->node);
10273 kfree(mac_node);
10274 }
10275 }
10276 }
10277
hclge_restore_mac_table_common(struct hclge_vport * vport)10278 void hclge_restore_mac_table_common(struct hclge_vport *vport)
10279 {
10280 spin_lock_bh(&vport->mac_list_lock);
10281
10282 hclge_mac_node_convert_for_reset(&vport->uc_mac_list);
10283 hclge_mac_node_convert_for_reset(&vport->mc_mac_list);
10284 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
10285
10286 spin_unlock_bh(&vport->mac_list_lock);
10287 }
10288
hclge_restore_hw_table(struct hclge_dev * hdev)10289 static void hclge_restore_hw_table(struct hclge_dev *hdev)
10290 {
10291 struct hclge_vport *vport = &hdev->vport[0];
10292 struct hnae3_handle *handle = &vport->nic;
10293
10294 hclge_restore_mac_table_common(vport);
10295 hclge_restore_vport_port_base_vlan_config(hdev);
10296 hclge_restore_vport_vlan_table(vport);
10297 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
10298 hclge_restore_fd_entries(handle);
10299 }
10300
hclge_en_hw_strip_rxvtag(struct hnae3_handle * handle,bool enable)10301 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
10302 {
10303 struct hclge_vport *vport = hclge_get_vport(handle);
10304
10305 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10306 vport->rxvlan_cfg.strip_tag1_en = false;
10307 vport->rxvlan_cfg.strip_tag2_en = enable;
10308 vport->rxvlan_cfg.strip_tag2_discard_en = false;
10309 } else {
10310 vport->rxvlan_cfg.strip_tag1_en = enable;
10311 vport->rxvlan_cfg.strip_tag2_en = true;
10312 vport->rxvlan_cfg.strip_tag2_discard_en = true;
10313 }
10314
10315 vport->rxvlan_cfg.strip_tag1_discard_en = false;
10316 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
10317 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
10318 vport->rxvlan_cfg.rx_vlan_offload_en = enable;
10319
10320 return hclge_set_vlan_rx_offload_cfg(vport);
10321 }
10322
hclge_set_vport_vlan_fltr_change(struct hclge_vport * vport)10323 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport)
10324 {
10325 struct hclge_dev *hdev = vport->back;
10326
10327 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
10328 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state);
10329 }
10330
hclge_update_vlan_filter_entries(struct hclge_vport * vport,u16 port_base_vlan_state,struct hclge_vlan_info * new_info,struct hclge_vlan_info * old_info)10331 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport,
10332 u16 port_base_vlan_state,
10333 struct hclge_vlan_info *new_info,
10334 struct hclge_vlan_info *old_info)
10335 {
10336 struct hclge_dev *hdev = vport->back;
10337 int ret;
10338
10339 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) {
10340 hclge_rm_vport_all_vlan_table(vport, false);
10341 /* force clear VLAN 0 */
10342 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0);
10343 if (ret)
10344 return ret;
10345 return hclge_set_vlan_filter_hw(hdev,
10346 htons(new_info->vlan_proto),
10347 vport->vport_id,
10348 new_info->vlan_tag,
10349 false);
10350 }
10351
10352 vport->port_base_vlan_cfg.tbl_sta = false;
10353
10354 /* force add VLAN 0 */
10355 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0);
10356 if (ret)
10357 return ret;
10358
10359 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto),
10360 vport->vport_id, old_info->vlan_tag,
10361 true);
10362 if (ret)
10363 return ret;
10364
10365 return hclge_add_vport_all_vlan_table(vport);
10366 }
10367
hclge_need_update_vlan_filter(const struct hclge_vlan_info * new_cfg,const struct hclge_vlan_info * old_cfg)10368 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg,
10369 const struct hclge_vlan_info *old_cfg)
10370 {
10371 if (new_cfg->vlan_tag != old_cfg->vlan_tag)
10372 return true;
10373
10374 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0))
10375 return true;
10376
10377 return false;
10378 }
10379
hclge_modify_port_base_vlan_tag(struct hclge_vport * vport,struct hclge_vlan_info * new_info,struct hclge_vlan_info * old_info)10380 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
10381 struct hclge_vlan_info *new_info,
10382 struct hclge_vlan_info *old_info)
10383 {
10384 struct hclge_dev *hdev = vport->back;
10385 int ret;
10386
10387 /* add new VLAN tag */
10388 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto),
10389 vport->vport_id, new_info->vlan_tag,
10390 false);
10391 if (ret)
10392 return ret;
10393
10394 vport->port_base_vlan_cfg.tbl_sta = false;
10395 /* remove old VLAN tag */
10396 if (old_info->vlan_tag == 0)
10397 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
10398 true, 0);
10399 else
10400 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10401 vport->vport_id,
10402 old_info->vlan_tag, true);
10403 if (ret)
10404 dev_err(&hdev->pdev->dev,
10405 "failed to clear vport%u port base vlan %u, ret = %d.\n",
10406 vport->vport_id, old_info->vlan_tag, ret);
10407
10408 return ret;
10409 }
10410
hclge_update_port_base_vlan_cfg(struct hclge_vport * vport,u16 state,struct hclge_vlan_info * vlan_info)10411 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
10412 struct hclge_vlan_info *vlan_info)
10413 {
10414 struct hnae3_handle *nic = &vport->nic;
10415 struct hclge_vlan_info *old_vlan_info;
10416 int ret;
10417
10418 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10419
10420 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag,
10421 vlan_info->qos);
10422 if (ret)
10423 return ret;
10424
10425 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info))
10426 goto out;
10427
10428 if (state == HNAE3_PORT_BASE_VLAN_MODIFY)
10429 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info,
10430 old_vlan_info);
10431 else
10432 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info,
10433 old_vlan_info);
10434 if (ret)
10435 return ret;
10436
10437 out:
10438 vport->port_base_vlan_cfg.state = state;
10439 if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
10440 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE;
10441 else
10442 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
10443
10444 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info;
10445 vport->port_base_vlan_cfg.vlan_info = *vlan_info;
10446 vport->port_base_vlan_cfg.tbl_sta = true;
10447 hclge_set_vport_vlan_fltr_change(vport);
10448
10449 return 0;
10450 }
10451
hclge_get_port_base_vlan_state(struct hclge_vport * vport,enum hnae3_port_base_vlan_state state,u16 vlan,u8 qos)10452 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport,
10453 enum hnae3_port_base_vlan_state state,
10454 u16 vlan, u8 qos)
10455 {
10456 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10457 if (!vlan && !qos)
10458 return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10459
10460 return HNAE3_PORT_BASE_VLAN_ENABLE;
10461 }
10462
10463 if (!vlan && !qos)
10464 return HNAE3_PORT_BASE_VLAN_DISABLE;
10465
10466 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan &&
10467 vport->port_base_vlan_cfg.vlan_info.qos == qos)
10468 return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10469
10470 return HNAE3_PORT_BASE_VLAN_MODIFY;
10471 }
10472
hclge_set_vf_vlan_filter(struct hnae3_handle * handle,int vfid,u16 vlan,u8 qos,__be16 proto)10473 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
10474 u16 vlan, u8 qos, __be16 proto)
10475 {
10476 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
10477 struct hclge_vport *vport = hclge_get_vport(handle);
10478 struct hclge_dev *hdev = vport->back;
10479 struct hclge_vlan_info vlan_info;
10480 u16 state;
10481 int ret;
10482
10483 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
10484 return -EOPNOTSUPP;
10485
10486 vport = hclge_get_vf_vport(hdev, vfid);
10487 if (!vport)
10488 return -EINVAL;
10489
10490 /* qos is a 3 bits value, so can not be bigger than 7 */
10491 if (vlan > VLAN_N_VID - 1 || qos > 7)
10492 return -EINVAL;
10493 if (proto != htons(ETH_P_8021Q))
10494 return -EPROTONOSUPPORT;
10495
10496 state = hclge_get_port_base_vlan_state(vport,
10497 vport->port_base_vlan_cfg.state,
10498 vlan, qos);
10499 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE)
10500 return 0;
10501
10502 vlan_info.vlan_tag = vlan;
10503 vlan_info.qos = qos;
10504 vlan_info.vlan_proto = ntohs(proto);
10505
10506 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info);
10507 if (ret) {
10508 dev_err(&hdev->pdev->dev,
10509 "failed to update port base vlan for vf %d, ret = %d\n",
10510 vfid, ret);
10511 return ret;
10512 }
10513
10514 /* there is a timewindow for PF to know VF unalive, it may
10515 * cause send mailbox fail, but it doesn't matter, VF will
10516 * query it when reinit.
10517 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based
10518 * VLAN state.
10519 */
10520 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
10521 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
10522 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
10523 vport->vport_id,
10524 state,
10525 &vlan_info);
10526 else
10527 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
10528 &vport->need_notify);
10529 }
10530 return 0;
10531 }
10532
hclge_clear_vf_vlan(struct hclge_dev * hdev)10533 static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
10534 {
10535 struct hclge_vlan_info *vlan_info;
10536 struct hclge_vport *vport;
10537 int ret;
10538 int vf;
10539
10540 /* clear port base vlan for all vf */
10541 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
10542 vport = &hdev->vport[vf];
10543 vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10544
10545 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10546 vport->vport_id,
10547 vlan_info->vlan_tag, true);
10548 if (ret)
10549 dev_err(&hdev->pdev->dev,
10550 "failed to clear vf vlan for vf%d, ret = %d\n",
10551 vf - HCLGE_VF_VPORT_START_NUM, ret);
10552 }
10553 }
10554
hclge_set_vlan_filter(struct hnae3_handle * handle,__be16 proto,u16 vlan_id,bool is_kill)10555 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
10556 u16 vlan_id, bool is_kill)
10557 {
10558 struct hclge_vport *vport = hclge_get_vport(handle);
10559 struct hclge_dev *hdev = vport->back;
10560 bool writen_to_tbl = false;
10561 int ret = 0;
10562
10563 if (vlan_id >= VLAN_N_VID)
10564 return -EINVAL;
10565
10566 /* When device is resetting or reset failed, firmware is unable to
10567 * handle mailbox. Just record the vlan id, and remove it after
10568 * reset finished.
10569 */
10570 mutex_lock(&hdev->vport_lock);
10571 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10572 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) {
10573 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10574 mutex_unlock(&hdev->vport_lock);
10575 return -EBUSY;
10576 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) {
10577 clear_bit(vlan_id, vport->vlan_del_fail_bmap);
10578 }
10579 mutex_unlock(&hdev->vport_lock);
10580
10581 /* when port base vlan enabled, we use port base vlan as the vlan
10582 * filter entry. In this case, we don't update vlan filter table
10583 * when user add new vlan or remove exist vlan, just update the vport
10584 * vlan list. The vlan id in vlan list will be writen in vlan filter
10585 * table until port base vlan disabled
10586 */
10587 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10588 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id,
10589 vlan_id, is_kill);
10590 writen_to_tbl = true;
10591 }
10592
10593 if (!ret) {
10594 if (!is_kill) {
10595 hclge_add_vport_vlan_table(vport, vlan_id,
10596 writen_to_tbl);
10597 } else if (is_kill && vlan_id != 0) {
10598 mutex_lock(&hdev->vport_lock);
10599 hclge_rm_vport_vlan_table(vport, vlan_id, false);
10600 mutex_unlock(&hdev->vport_lock);
10601 }
10602 } else if (is_kill) {
10603 /* when remove hw vlan filter failed, record the vlan id,
10604 * and try to remove it from hw later, to be consistence
10605 * with stack
10606 */
10607 mutex_lock(&hdev->vport_lock);
10608 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10609 mutex_unlock(&hdev->vport_lock);
10610 }
10611
10612 hclge_set_vport_vlan_fltr_change(vport);
10613
10614 return ret;
10615 }
10616
hclge_sync_vlan_fltr_state(struct hclge_dev * hdev)10617 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev)
10618 {
10619 struct hclge_vport *vport;
10620 int ret;
10621 u16 i;
10622
10623 for (i = 0; i < hdev->num_alloc_vport; i++) {
10624 vport = &hdev->vport[i];
10625 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10626 &vport->state))
10627 continue;
10628
10629 mutex_lock(&hdev->vport_lock);
10630 ret = __hclge_enable_vport_vlan_filter(vport,
10631 vport->req_vlan_fltr_en);
10632 if (ret) {
10633 dev_err(&hdev->pdev->dev,
10634 "failed to sync vlan filter state for vport%u, ret = %d\n",
10635 vport->vport_id, ret);
10636 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10637 &vport->state);
10638 mutex_unlock(&hdev->vport_lock);
10639 return;
10640 }
10641 mutex_unlock(&hdev->vport_lock);
10642 }
10643 }
10644
hclge_sync_vlan_filter(struct hclge_dev * hdev)10645 static void hclge_sync_vlan_filter(struct hclge_dev *hdev)
10646 {
10647 #define HCLGE_MAX_SYNC_COUNT 60
10648
10649 int i, ret, sync_cnt = 0;
10650 u16 vlan_id;
10651
10652 mutex_lock(&hdev->vport_lock);
10653 /* start from vport 1 for PF is always alive */
10654 for (i = 0; i < hdev->num_alloc_vport; i++) {
10655 struct hclge_vport *vport = &hdev->vport[i];
10656
10657 vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10658 VLAN_N_VID);
10659 while (vlan_id != VLAN_N_VID) {
10660 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10661 vport->vport_id, vlan_id,
10662 true);
10663 if (ret && ret != -EINVAL) {
10664 mutex_unlock(&hdev->vport_lock);
10665 return;
10666 }
10667
10668 clear_bit(vlan_id, vport->vlan_del_fail_bmap);
10669 hclge_rm_vport_vlan_table(vport, vlan_id, false);
10670 hclge_set_vport_vlan_fltr_change(vport);
10671
10672 sync_cnt++;
10673 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) {
10674 mutex_unlock(&hdev->vport_lock);
10675 return;
10676 }
10677
10678 vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10679 VLAN_N_VID);
10680 }
10681 }
10682 mutex_unlock(&hdev->vport_lock);
10683
10684 hclge_sync_vlan_fltr_state(hdev);
10685 }
10686
hclge_set_mac_mtu(struct hclge_dev * hdev,int new_mps)10687 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
10688 {
10689 struct hclge_config_max_frm_size_cmd *req;
10690 struct hclge_desc desc;
10691
10692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
10693
10694 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
10695 req->max_frm_size = cpu_to_le16(new_mps);
10696 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
10697
10698 return hclge_cmd_send(&hdev->hw, &desc, 1);
10699 }
10700
hclge_set_mtu(struct hnae3_handle * handle,int new_mtu)10701 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
10702 {
10703 struct hclge_vport *vport = hclge_get_vport(handle);
10704
10705 return hclge_set_vport_mtu(vport, new_mtu);
10706 }
10707
hclge_set_vport_mtu(struct hclge_vport * vport,int new_mtu)10708 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
10709 {
10710 struct hclge_dev *hdev = vport->back;
10711 int i, max_frm_size, ret;
10712
10713 /* HW supprt 2 layer vlan */
10714 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
10715 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
10716 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size)
10717 return -EINVAL;
10718
10719 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
10720 mutex_lock(&hdev->vport_lock);
10721 /* VF's mps must fit within hdev->mps */
10722 if (vport->vport_id && (u32)max_frm_size > hdev->mps) {
10723 mutex_unlock(&hdev->vport_lock);
10724 return -EINVAL;
10725 } else if (vport->vport_id) {
10726 vport->mps = max_frm_size;
10727 mutex_unlock(&hdev->vport_lock);
10728 return 0;
10729 }
10730
10731 /* PF's mps must be greater then VF's mps */
10732 for (i = 1; i < hdev->num_alloc_vport; i++)
10733 if ((u32)max_frm_size < hdev->vport[i].mps) {
10734 dev_err(&hdev->pdev->dev,
10735 "failed to set pf mtu for less than vport %d, mps = %u.\n",
10736 i, hdev->vport[i].mps);
10737 mutex_unlock(&hdev->vport_lock);
10738 return -EINVAL;
10739 }
10740
10741 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
10742
10743 ret = hclge_set_mac_mtu(hdev, max_frm_size);
10744 if (ret) {
10745 dev_err(&hdev->pdev->dev,
10746 "Change mtu fail, ret =%d\n", ret);
10747 goto out;
10748 }
10749
10750 hdev->mps = max_frm_size;
10751 vport->mps = max_frm_size;
10752
10753 ret = hclge_buffer_alloc(hdev);
10754 if (ret)
10755 dev_err(&hdev->pdev->dev,
10756 "Allocate buffer fail, ret =%d\n", ret);
10757
10758 out:
10759 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
10760 mutex_unlock(&hdev->vport_lock);
10761 return ret;
10762 }
10763
hclge_reset_tqp_cmd_send(struct hclge_dev * hdev,u16 queue_id,bool enable)10764 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id,
10765 bool enable)
10766 {
10767 struct hclge_reset_tqp_queue_cmd *req;
10768 struct hclge_desc desc;
10769 int ret;
10770
10771 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
10772
10773 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10774 req->tqp_id = cpu_to_le16(queue_id);
10775 if (enable)
10776 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U);
10777
10778 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10779 if (ret) {
10780 dev_err(&hdev->pdev->dev,
10781 "Send tqp reset cmd error, status =%d\n", ret);
10782 return ret;
10783 }
10784
10785 return 0;
10786 }
10787
hclge_get_reset_status(struct hclge_dev * hdev,u16 queue_id,u8 * reset_status)10788 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id,
10789 u8 *reset_status)
10790 {
10791 struct hclge_reset_tqp_queue_cmd *req;
10792 struct hclge_desc desc;
10793 int ret;
10794
10795 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
10796
10797 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10798 req->tqp_id = cpu_to_le16(queue_id);
10799
10800 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10801 if (ret) {
10802 dev_err(&hdev->pdev->dev,
10803 "Get reset status error, status =%d\n", ret);
10804 return ret;
10805 }
10806
10807 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
10808
10809 return 0;
10810 }
10811
hclge_covert_handle_qid_global(struct hnae3_handle * handle,u16 queue_id)10812 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
10813 {
10814 struct hclge_comm_tqp *tqp;
10815 struct hnae3_queue *queue;
10816
10817 queue = handle->kinfo.tqp[queue_id];
10818 tqp = container_of(queue, struct hclge_comm_tqp, q);
10819
10820 return tqp->index;
10821 }
10822
hclge_reset_tqp_cmd(struct hnae3_handle * handle)10823 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle)
10824 {
10825 struct hclge_vport *vport = hclge_get_vport(handle);
10826 struct hclge_dev *hdev = vport->back;
10827 u16 reset_try_times = 0;
10828 u8 reset_status;
10829 u16 queue_gid;
10830 int ret;
10831 u16 i;
10832
10833 for (i = 0; i < handle->kinfo.num_tqps; i++) {
10834 queue_gid = hclge_covert_handle_qid_global(handle, i);
10835 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true);
10836 if (ret) {
10837 dev_err(&hdev->pdev->dev,
10838 "failed to send reset tqp cmd, ret = %d\n",
10839 ret);
10840 return ret;
10841 }
10842
10843 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
10844 ret = hclge_get_reset_status(hdev, queue_gid,
10845 &reset_status);
10846 if (ret)
10847 return ret;
10848
10849 if (reset_status)
10850 break;
10851
10852 /* Wait for tqp hw reset */
10853 usleep_range(1000, 1200);
10854 }
10855
10856 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
10857 dev_err(&hdev->pdev->dev,
10858 "wait for tqp hw reset timeout\n");
10859 return -ETIME;
10860 }
10861
10862 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false);
10863 if (ret) {
10864 dev_err(&hdev->pdev->dev,
10865 "failed to deassert soft reset, ret = %d\n",
10866 ret);
10867 return ret;
10868 }
10869 reset_try_times = 0;
10870 }
10871 return 0;
10872 }
10873
hclge_reset_rcb(struct hnae3_handle * handle)10874 static int hclge_reset_rcb(struct hnae3_handle *handle)
10875 {
10876 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U
10877 #define HCLGE_RESET_RCB_SUCCESS 1U
10878
10879 struct hclge_vport *vport = hclge_get_vport(handle);
10880 struct hclge_dev *hdev = vport->back;
10881 struct hclge_reset_cmd *req;
10882 struct hclge_desc desc;
10883 u8 return_status;
10884 u16 queue_gid;
10885 int ret;
10886
10887 queue_gid = hclge_covert_handle_qid_global(handle, 0);
10888
10889 req = (struct hclge_reset_cmd *)desc.data;
10890 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
10891 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1);
10892 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid);
10893 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps);
10894
10895 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10896 if (ret) {
10897 dev_err(&hdev->pdev->dev,
10898 "failed to send rcb reset cmd, ret = %d\n", ret);
10899 return ret;
10900 }
10901
10902 return_status = req->fun_reset_rcb_return_status;
10903 if (return_status == HCLGE_RESET_RCB_SUCCESS)
10904 return 0;
10905
10906 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) {
10907 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n",
10908 return_status);
10909 return -EIO;
10910 }
10911
10912 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd
10913 * again to reset all tqps
10914 */
10915 return hclge_reset_tqp_cmd(handle);
10916 }
10917
hclge_reset_tqp(struct hnae3_handle * handle)10918 int hclge_reset_tqp(struct hnae3_handle *handle)
10919 {
10920 struct hclge_vport *vport = hclge_get_vport(handle);
10921 struct hclge_dev *hdev = vport->back;
10922 int ret;
10923
10924 /* only need to disable PF's tqp */
10925 if (!vport->vport_id) {
10926 ret = hclge_tqp_enable(handle, false);
10927 if (ret) {
10928 dev_err(&hdev->pdev->dev,
10929 "failed to disable tqp, ret = %d\n", ret);
10930 return ret;
10931 }
10932 }
10933
10934 return hclge_reset_rcb(handle);
10935 }
10936
hclge_get_fw_version(struct hnae3_handle * handle)10937 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
10938 {
10939 struct hclge_vport *vport = hclge_get_vport(handle);
10940 struct hclge_dev *hdev = vport->back;
10941
10942 return hdev->fw_version;
10943 }
10944
hclge_query_scc_version(struct hclge_dev * hdev,u32 * scc_version)10945 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version)
10946 {
10947 struct hclge_comm_query_scc_cmd *resp;
10948 struct hclge_desc desc;
10949 int ret;
10950
10951 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1);
10952 resp = (struct hclge_comm_query_scc_cmd *)desc.data;
10953
10954 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10955 if (ret)
10956 return ret;
10957
10958 *scc_version = le32_to_cpu(resp->scc_version);
10959
10960 return 0;
10961 }
10962
hclge_set_flowctrl_adv(struct hclge_dev * hdev,u32 rx_en,u32 tx_en)10963 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10964 {
10965 struct phy_device *phydev = hdev->hw.mac.phydev;
10966
10967 if (!phydev)
10968 return;
10969
10970 phy_set_asym_pause(phydev, rx_en, tx_en);
10971 }
10972
hclge_cfg_pauseparam(struct hclge_dev * hdev,u32 rx_en,u32 tx_en)10973 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10974 {
10975 int ret;
10976
10977 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
10978 return 0;
10979
10980 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
10981 if (ret)
10982 dev_err(&hdev->pdev->dev,
10983 "configure pauseparam error, ret = %d.\n", ret);
10984
10985 return ret;
10986 }
10987
hclge_cfg_flowctrl(struct hclge_dev * hdev)10988 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
10989 {
10990 struct phy_device *phydev = hdev->hw.mac.phydev;
10991 u16 remote_advertising = 0;
10992 u16 local_advertising;
10993 u32 rx_pause, tx_pause;
10994 u8 flowctl;
10995
10996 if (!phydev->link)
10997 return 0;
10998
10999 if (!phydev->autoneg)
11000 return hclge_mac_pause_setup_hw(hdev);
11001
11002 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
11003
11004 if (phydev->pause)
11005 remote_advertising = LPA_PAUSE_CAP;
11006
11007 if (phydev->asym_pause)
11008 remote_advertising |= LPA_PAUSE_ASYM;
11009
11010 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
11011 remote_advertising);
11012 tx_pause = flowctl & FLOW_CTRL_TX;
11013 rx_pause = flowctl & FLOW_CTRL_RX;
11014
11015 if (phydev->duplex == HCLGE_MAC_HALF) {
11016 tx_pause = 0;
11017 rx_pause = 0;
11018 }
11019
11020 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
11021 }
11022
hclge_get_pauseparam(struct hnae3_handle * handle,u32 * auto_neg,u32 * rx_en,u32 * tx_en)11023 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
11024 u32 *rx_en, u32 *tx_en)
11025 {
11026 struct hclge_vport *vport = hclge_get_vport(handle);
11027 struct hclge_dev *hdev = vport->back;
11028 u8 media_type = hdev->hw.mac.media_type;
11029
11030 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ?
11031 hclge_get_autoneg(handle) : 0;
11032
11033 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
11034 *rx_en = 0;
11035 *tx_en = 0;
11036 return;
11037 }
11038
11039 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
11040 *rx_en = 1;
11041 *tx_en = 0;
11042 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
11043 *tx_en = 1;
11044 *rx_en = 0;
11045 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
11046 *rx_en = 1;
11047 *tx_en = 1;
11048 } else {
11049 *rx_en = 0;
11050 *tx_en = 0;
11051 }
11052 }
11053
hclge_record_user_pauseparam(struct hclge_dev * hdev,u32 rx_en,u32 tx_en)11054 static void hclge_record_user_pauseparam(struct hclge_dev *hdev,
11055 u32 rx_en, u32 tx_en)
11056 {
11057 if (rx_en && tx_en)
11058 hdev->fc_mode_last_time = HCLGE_FC_FULL;
11059 else if (rx_en && !tx_en)
11060 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
11061 else if (!rx_en && tx_en)
11062 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
11063 else
11064 hdev->fc_mode_last_time = HCLGE_FC_NONE;
11065
11066 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
11067 }
11068
hclge_set_pauseparam(struct hnae3_handle * handle,u32 auto_neg,u32 rx_en,u32 tx_en)11069 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
11070 u32 rx_en, u32 tx_en)
11071 {
11072 struct hclge_vport *vport = hclge_get_vport(handle);
11073 struct hclge_dev *hdev = vport->back;
11074 struct phy_device *phydev = hdev->hw.mac.phydev;
11075 u32 fc_autoneg;
11076
11077 if (phydev || hnae3_dev_phy_imp_supported(hdev)) {
11078 fc_autoneg = hclge_get_autoneg(handle);
11079 if (auto_neg != fc_autoneg) {
11080 dev_info(&hdev->pdev->dev,
11081 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
11082 return -EOPNOTSUPP;
11083 }
11084 }
11085
11086 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
11087 dev_info(&hdev->pdev->dev,
11088 "Priority flow control enabled. Cannot set link flow control.\n");
11089 return -EOPNOTSUPP;
11090 }
11091
11092 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
11093
11094 hclge_record_user_pauseparam(hdev, rx_en, tx_en);
11095
11096 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
11097 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
11098
11099 if (phydev)
11100 return phy_start_aneg(phydev);
11101
11102 return -EOPNOTSUPP;
11103 }
11104
hclge_get_ksettings_an_result(struct hnae3_handle * handle,u8 * auto_neg,u32 * speed,u8 * duplex,u32 * lane_num)11105 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
11106 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num)
11107 {
11108 struct hclge_vport *vport = hclge_get_vport(handle);
11109 struct hclge_dev *hdev = vport->back;
11110
11111 if (speed)
11112 *speed = hdev->hw.mac.speed;
11113 if (duplex)
11114 *duplex = hdev->hw.mac.duplex;
11115 if (auto_neg)
11116 *auto_neg = hdev->hw.mac.autoneg;
11117 if (lane_num)
11118 *lane_num = hdev->hw.mac.lane_num;
11119 }
11120
hclge_get_media_type(struct hnae3_handle * handle,u8 * media_type,u8 * module_type)11121 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
11122 u8 *module_type)
11123 {
11124 struct hclge_vport *vport = hclge_get_vport(handle);
11125 struct hclge_dev *hdev = vport->back;
11126
11127 /* When nic is down, the service task is not running, doesn't update
11128 * the port information per second. Query the port information before
11129 * return the media type, ensure getting the correct media information.
11130 */
11131 hclge_update_port_info(hdev);
11132
11133 if (media_type)
11134 *media_type = hdev->hw.mac.media_type;
11135
11136 if (module_type)
11137 *module_type = hdev->hw.mac.module_type;
11138 }
11139
hclge_get_mdix_mode(struct hnae3_handle * handle,u8 * tp_mdix_ctrl,u8 * tp_mdix)11140 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
11141 u8 *tp_mdix_ctrl, u8 *tp_mdix)
11142 {
11143 struct hclge_vport *vport = hclge_get_vport(handle);
11144 struct hclge_dev *hdev = vport->back;
11145 struct phy_device *phydev = hdev->hw.mac.phydev;
11146 int mdix_ctrl, mdix, is_resolved;
11147 unsigned int retval;
11148
11149 if (!phydev) {
11150 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
11151 *tp_mdix = ETH_TP_MDI_INVALID;
11152 return;
11153 }
11154
11155 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
11156
11157 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
11158 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
11159 HCLGE_PHY_MDIX_CTRL_S);
11160
11161 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
11162 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
11163 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
11164
11165 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
11166
11167 switch (mdix_ctrl) {
11168 case 0x0:
11169 *tp_mdix_ctrl = ETH_TP_MDI;
11170 break;
11171 case 0x1:
11172 *tp_mdix_ctrl = ETH_TP_MDI_X;
11173 break;
11174 case 0x3:
11175 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
11176 break;
11177 default:
11178 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
11179 break;
11180 }
11181
11182 if (!is_resolved)
11183 *tp_mdix = ETH_TP_MDI_INVALID;
11184 else if (mdix)
11185 *tp_mdix = ETH_TP_MDI_X;
11186 else
11187 *tp_mdix = ETH_TP_MDI;
11188 }
11189
hclge_info_show(struct hclge_dev * hdev)11190 static void hclge_info_show(struct hclge_dev *hdev)
11191 {
11192 struct hnae3_handle *handle = &hdev->vport->nic;
11193 struct device *dev = &hdev->pdev->dev;
11194
11195 dev_info(dev, "PF info begin:\n");
11196
11197 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
11198 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
11199 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
11200 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
11201 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs);
11202 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
11203 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size);
11204 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size);
11205 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size);
11206 dev_info(dev, "This is %s PF\n",
11207 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main");
11208 dev_info(dev, "DCB %s\n",
11209 str_enable_disable(handle->kinfo.tc_info.dcb_ets_active));
11210 dev_info(dev, "MQPRIO %s\n",
11211 str_enable_disable(handle->kinfo.tc_info.mqprio_active));
11212 dev_info(dev, "Default tx spare buffer size: %u\n",
11213 hdev->tx_spare_buf_size);
11214
11215 dev_info(dev, "PF info end.\n");
11216 }
11217
hclge_init_nic_client_instance(struct hnae3_ae_dev * ae_dev,struct hclge_vport * vport)11218 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
11219 struct hclge_vport *vport)
11220 {
11221 struct hnae3_client *client = vport->nic.client;
11222 struct hclge_dev *hdev = ae_dev->priv;
11223 u32 rst_cnt = hdev->rst_stats.reset_cnt;
11224 int ret;
11225
11226 ret = client->ops->init_instance(&vport->nic);
11227 if (ret)
11228 return ret;
11229
11230 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11231 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11232 rst_cnt != hdev->rst_stats.reset_cnt) {
11233 ret = -EBUSY;
11234 goto init_nic_err;
11235 }
11236
11237 /* Enable nic hw error interrupts */
11238 ret = hclge_config_nic_hw_error(hdev, true);
11239 if (ret) {
11240 dev_err(&ae_dev->pdev->dev,
11241 "fail(%d) to enable hw error interrupts\n", ret);
11242 goto init_nic_err;
11243 }
11244
11245 hnae3_set_client_init_flag(client, ae_dev, 1);
11246
11247 if (netif_msg_drv(&hdev->vport->nic))
11248 hclge_info_show(hdev);
11249
11250 return ret;
11251
11252 init_nic_err:
11253 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11254 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11255 msleep(HCLGE_WAIT_RESET_DONE);
11256
11257 client->ops->uninit_instance(&vport->nic, 0);
11258
11259 return ret;
11260 }
11261
hclge_init_roce_client_instance(struct hnae3_ae_dev * ae_dev,struct hclge_vport * vport)11262 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
11263 struct hclge_vport *vport)
11264 {
11265 struct hclge_dev *hdev = ae_dev->priv;
11266 struct hnae3_client *client;
11267 u32 rst_cnt;
11268 int ret;
11269
11270 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
11271 !hdev->nic_client)
11272 return 0;
11273
11274 client = hdev->roce_client;
11275 ret = hclge_init_roce_base_info(vport);
11276 if (ret)
11277 return ret;
11278
11279 rst_cnt = hdev->rst_stats.reset_cnt;
11280 ret = client->ops->init_instance(&vport->roce);
11281 if (ret)
11282 return ret;
11283
11284 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11285 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11286 rst_cnt != hdev->rst_stats.reset_cnt) {
11287 ret = -EBUSY;
11288 goto init_roce_err;
11289 }
11290
11291 /* Enable roce ras interrupts */
11292 ret = hclge_config_rocee_ras_interrupt(hdev, true);
11293 if (ret) {
11294 dev_err(&ae_dev->pdev->dev,
11295 "fail(%d) to enable roce ras interrupts\n", ret);
11296 goto init_roce_err;
11297 }
11298
11299 hnae3_set_client_init_flag(client, ae_dev, 1);
11300
11301 return 0;
11302
11303 init_roce_err:
11304 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11305 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11306 msleep(HCLGE_WAIT_RESET_DONE);
11307
11308 hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11309
11310 return ret;
11311 }
11312
hclge_init_client_instance(struct hnae3_client * client,struct hnae3_ae_dev * ae_dev)11313 static int hclge_init_client_instance(struct hnae3_client *client,
11314 struct hnae3_ae_dev *ae_dev)
11315 {
11316 struct hclge_dev *hdev = ae_dev->priv;
11317 struct hclge_vport *vport = &hdev->vport[0];
11318 int ret;
11319
11320 switch (client->type) {
11321 case HNAE3_CLIENT_KNIC:
11322 hdev->nic_client = client;
11323 vport->nic.client = client;
11324 ret = hclge_init_nic_client_instance(ae_dev, vport);
11325 if (ret)
11326 goto clear_nic;
11327
11328 ret = hclge_init_roce_client_instance(ae_dev, vport);
11329 if (ret)
11330 goto clear_roce;
11331
11332 break;
11333 case HNAE3_CLIENT_ROCE:
11334 if (hnae3_dev_roce_supported(hdev)) {
11335 hdev->roce_client = client;
11336 vport->roce.client = client;
11337 }
11338
11339 ret = hclge_init_roce_client_instance(ae_dev, vport);
11340 if (ret)
11341 goto clear_roce;
11342
11343 break;
11344 default:
11345 return -EINVAL;
11346 }
11347
11348 return 0;
11349
11350 clear_nic:
11351 hdev->nic_client = NULL;
11352 vport->nic.client = NULL;
11353 return ret;
11354 clear_roce:
11355 hdev->roce_client = NULL;
11356 vport->roce.client = NULL;
11357 return ret;
11358 }
11359
hclge_uninit_need_wait(struct hclge_dev * hdev)11360 static bool hclge_uninit_need_wait(struct hclge_dev *hdev)
11361 {
11362 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11363 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
11364 }
11365
hclge_uninit_client_instance(struct hnae3_client * client,struct hnae3_ae_dev * ae_dev)11366 static void hclge_uninit_client_instance(struct hnae3_client *client,
11367 struct hnae3_ae_dev *ae_dev)
11368 {
11369 struct hclge_dev *hdev = ae_dev->priv;
11370 struct hclge_vport *vport = &hdev->vport[0];
11371
11372 if (hdev->roce_client) {
11373 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11374 while (hclge_uninit_need_wait(hdev))
11375 msleep(HCLGE_WAIT_RESET_DONE);
11376
11377 hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11378 hdev->roce_client = NULL;
11379 vport->roce.client = NULL;
11380 }
11381 if (client->type == HNAE3_CLIENT_ROCE)
11382 return;
11383 if (hdev->nic_client && client->ops->uninit_instance) {
11384 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11385 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11386 msleep(HCLGE_WAIT_RESET_DONE);
11387
11388 client->ops->uninit_instance(&vport->nic, 0);
11389 hdev->nic_client = NULL;
11390 vport->nic.client = NULL;
11391 }
11392 }
11393
hclge_dev_mem_map(struct hclge_dev * hdev)11394 static int hclge_dev_mem_map(struct hclge_dev *hdev)
11395 {
11396 struct pci_dev *pdev = hdev->pdev;
11397 struct hclge_hw *hw = &hdev->hw;
11398
11399 /* for device does not have device memory, return directly */
11400 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
11401 return 0;
11402
11403 hw->hw.mem_base =
11404 devm_ioremap_wc(&pdev->dev,
11405 pci_resource_start(pdev, HCLGE_MEM_BAR),
11406 pci_resource_len(pdev, HCLGE_MEM_BAR));
11407 if (!hw->hw.mem_base) {
11408 dev_err(&pdev->dev, "failed to map device memory\n");
11409 return -EFAULT;
11410 }
11411
11412 return 0;
11413 }
11414
hclge_pci_init(struct hclge_dev * hdev)11415 static int hclge_pci_init(struct hclge_dev *hdev)
11416 {
11417 struct pci_dev *pdev = hdev->pdev;
11418 struct hclge_hw *hw;
11419 int ret;
11420
11421 ret = pci_enable_device(pdev);
11422 if (ret) {
11423 dev_err(&pdev->dev, "failed to enable PCI device\n");
11424 return ret;
11425 }
11426
11427 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
11428 if (ret) {
11429 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11430 if (ret) {
11431 dev_err(&pdev->dev,
11432 "can't set consistent PCI DMA\n");
11433 goto err_disable_device;
11434 }
11435 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
11436 }
11437
11438 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
11439 if (ret) {
11440 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
11441 goto err_disable_device;
11442 }
11443
11444 pci_set_master(pdev);
11445 hw = &hdev->hw;
11446 hw->hw.io_base = pcim_iomap(pdev, 2, 0);
11447 if (!hw->hw.io_base) {
11448 dev_err(&pdev->dev, "Can't map configuration register space\n");
11449 ret = -ENOMEM;
11450 goto err_release_regions;
11451 }
11452
11453 ret = hclge_dev_mem_map(hdev);
11454 if (ret)
11455 goto err_unmap_io_base;
11456
11457 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
11458
11459 return 0;
11460
11461 err_unmap_io_base:
11462 pcim_iounmap(pdev, hdev->hw.hw.io_base);
11463 err_release_regions:
11464 pci_release_regions(pdev);
11465 err_disable_device:
11466 pci_disable_device(pdev);
11467
11468 return ret;
11469 }
11470
hclge_pci_uninit(struct hclge_dev * hdev)11471 static void hclge_pci_uninit(struct hclge_dev *hdev)
11472 {
11473 struct pci_dev *pdev = hdev->pdev;
11474
11475 if (hdev->hw.hw.mem_base)
11476 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
11477
11478 pcim_iounmap(pdev, hdev->hw.hw.io_base);
11479 pci_free_irq_vectors(pdev);
11480 pci_release_regions(pdev);
11481 pci_disable_device(pdev);
11482 }
11483
hclge_state_init(struct hclge_dev * hdev)11484 static void hclge_state_init(struct hclge_dev *hdev)
11485 {
11486 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
11487 set_bit(HCLGE_STATE_DOWN, &hdev->state);
11488 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
11489 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11490 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
11491 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
11492 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
11493 }
11494
hclge_state_uninit(struct hclge_dev * hdev)11495 static void hclge_state_uninit(struct hclge_dev *hdev)
11496 {
11497 set_bit(HCLGE_STATE_DOWN, &hdev->state);
11498 set_bit(HCLGE_STATE_REMOVING, &hdev->state);
11499
11500 if (hdev->reset_timer.function)
11501 timer_delete_sync(&hdev->reset_timer);
11502 if (hdev->service_task.work.func)
11503 cancel_delayed_work_sync(&hdev->service_task);
11504 }
11505
hclge_reset_prepare_general(struct hnae3_ae_dev * ae_dev,enum hnae3_reset_type rst_type)11506 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
11507 enum hnae3_reset_type rst_type)
11508 {
11509 #define HCLGE_RESET_RETRY_WAIT_MS 500
11510 #define HCLGE_RESET_RETRY_CNT 5
11511
11512 struct hclge_dev *hdev = ae_dev->priv;
11513 int retry_cnt = 0;
11514 int ret;
11515
11516 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
11517 down(&hdev->reset_sem);
11518 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11519 hdev->reset_type = rst_type;
11520 ret = hclge_reset_prepare(hdev);
11521 if (!ret && !hdev->reset_pending)
11522 break;
11523
11524 dev_err(&hdev->pdev->dev,
11525 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
11526 ret, hdev->reset_pending, retry_cnt);
11527 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11528 up(&hdev->reset_sem);
11529 msleep(HCLGE_RESET_RETRY_WAIT_MS);
11530 }
11531
11532 /* disable misc vector before reset done */
11533 hclge_enable_vector(&hdev->misc_vector, false);
11534 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
11535
11536 if (hdev->reset_type == HNAE3_FLR_RESET)
11537 hdev->rst_stats.flr_rst_cnt++;
11538 }
11539
hclge_reset_done(struct hnae3_ae_dev * ae_dev)11540 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev)
11541 {
11542 struct hclge_dev *hdev = ae_dev->priv;
11543 int ret;
11544
11545 hclge_enable_vector(&hdev->misc_vector, true);
11546
11547 ret = hclge_reset_rebuild(hdev);
11548 if (ret)
11549 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret);
11550
11551 hdev->reset_type = HNAE3_NONE_RESET;
11552 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11553 up(&hdev->reset_sem);
11554 }
11555
hclge_clear_resetting_state(struct hclge_dev * hdev)11556 static void hclge_clear_resetting_state(struct hclge_dev *hdev)
11557 {
11558 u16 i;
11559
11560 for (i = 0; i < hdev->num_alloc_vport; i++) {
11561 struct hclge_vport *vport = &hdev->vport[i];
11562 int ret;
11563
11564 /* Send cmd to clear vport's FUNC_RST_ING */
11565 ret = hclge_set_vf_rst(hdev, vport->vport_id, false);
11566 if (ret)
11567 dev_warn(&hdev->pdev->dev,
11568 "clear vport(%u) rst failed %d!\n",
11569 vport->vport_id, ret);
11570 }
11571 }
11572
hclge_clear_hw_resource(struct hclge_dev * hdev)11573 static int hclge_clear_hw_resource(struct hclge_dev *hdev)
11574 {
11575 struct hclge_desc desc;
11576 int ret;
11577
11578 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false);
11579
11580 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11581 /* This new command is only supported by new firmware, it will
11582 * fail with older firmware. Error value -EOPNOSUPP can only be
11583 * returned by older firmware running this command, to keep code
11584 * backward compatible we will override this value and return
11585 * success.
11586 */
11587 if (ret && ret != -EOPNOTSUPP) {
11588 dev_err(&hdev->pdev->dev,
11589 "failed to clear hw resource, ret = %d\n", ret);
11590 return ret;
11591 }
11592 return 0;
11593 }
11594
hclge_init_rxd_adv_layout(struct hclge_dev * hdev)11595 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev)
11596 {
11597 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11598 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1);
11599 }
11600
hclge_uninit_rxd_adv_layout(struct hclge_dev * hdev)11601 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev)
11602 {
11603 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11604 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0);
11605 }
11606
hclge_get_wol_info(struct hnae3_handle * handle)11607 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle)
11608 {
11609 struct hclge_vport *vport = hclge_get_vport(handle);
11610
11611 return &vport->back->hw.mac.wol;
11612 }
11613
hclge_get_wol_supported_mode(struct hclge_dev * hdev,u32 * wol_supported)11614 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev,
11615 u32 *wol_supported)
11616 {
11617 struct hclge_query_wol_supported_cmd *wol_supported_cmd;
11618 struct hclge_desc desc;
11619 int ret;
11620
11621 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE,
11622 true);
11623 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data;
11624
11625 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11626 if (ret) {
11627 dev_err(&hdev->pdev->dev,
11628 "failed to query wol supported, ret = %d\n", ret);
11629 return ret;
11630 }
11631
11632 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode);
11633
11634 return 0;
11635 }
11636
hclge_set_wol_cfg(struct hclge_dev * hdev,struct hclge_wol_info * wol_info)11637 static int hclge_set_wol_cfg(struct hclge_dev *hdev,
11638 struct hclge_wol_info *wol_info)
11639 {
11640 struct hclge_wol_cfg_cmd *wol_cfg_cmd;
11641 struct hclge_desc desc;
11642 int ret;
11643
11644 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false);
11645 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data;
11646 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode);
11647 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size;
11648 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX);
11649
11650 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11651 if (ret)
11652 dev_err(&hdev->pdev->dev,
11653 "failed to set wol config, ret = %d\n", ret);
11654
11655 return ret;
11656 }
11657
hclge_update_wol(struct hclge_dev * hdev)11658 static int hclge_update_wol(struct hclge_dev *hdev)
11659 {
11660 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
11661
11662 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
11663 return 0;
11664
11665 return hclge_set_wol_cfg(hdev, wol_info);
11666 }
11667
hclge_init_wol(struct hclge_dev * hdev)11668 static int hclge_init_wol(struct hclge_dev *hdev)
11669 {
11670 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
11671 int ret;
11672
11673 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
11674 return 0;
11675
11676 memset(wol_info, 0, sizeof(struct hclge_wol_info));
11677 ret = hclge_get_wol_supported_mode(hdev,
11678 &wol_info->wol_support_mode);
11679 if (ret) {
11680 wol_info->wol_support_mode = 0;
11681 return ret;
11682 }
11683
11684 return hclge_update_wol(hdev);
11685 }
11686
hclge_get_wol(struct hnae3_handle * handle,struct ethtool_wolinfo * wol)11687 static void hclge_get_wol(struct hnae3_handle *handle,
11688 struct ethtool_wolinfo *wol)
11689 {
11690 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
11691
11692 wol->supported = wol_info->wol_support_mode;
11693 wol->wolopts = wol_info->wol_current_mode;
11694 if (wol_info->wol_current_mode & WAKE_MAGICSECURE)
11695 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX);
11696 }
11697
hclge_set_wol(struct hnae3_handle * handle,struct ethtool_wolinfo * wol)11698 static int hclge_set_wol(struct hnae3_handle *handle,
11699 struct ethtool_wolinfo *wol)
11700 {
11701 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
11702 struct hclge_vport *vport = hclge_get_vport(handle);
11703 u32 wol_mode;
11704 int ret;
11705
11706 wol_mode = wol->wolopts;
11707 if (wol_mode & ~wol_info->wol_support_mode)
11708 return -EINVAL;
11709
11710 wol_info->wol_current_mode = wol_mode;
11711 if (wol_mode & WAKE_MAGICSECURE) {
11712 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX);
11713 wol_info->wol_sopass_size = SOPASS_MAX;
11714 } else {
11715 wol_info->wol_sopass_size = 0;
11716 }
11717
11718 ret = hclge_set_wol_cfg(vport->back, wol_info);
11719 if (ret)
11720 wol_info->wol_current_mode = 0;
11721
11722 return ret;
11723 }
11724
hclge_init_ae_dev(struct hnae3_ae_dev * ae_dev)11725 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
11726 {
11727 struct pci_dev *pdev = ae_dev->pdev;
11728 struct hclge_dev *hdev;
11729 int ret;
11730
11731 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
11732 if (!hdev)
11733 return -ENOMEM;
11734
11735 hdev->pdev = pdev;
11736 hdev->ae_dev = ae_dev;
11737 hdev->reset_type = HNAE3_NONE_RESET;
11738 hdev->reset_level = HNAE3_FUNC_RESET;
11739 ae_dev->priv = hdev;
11740
11741 /* HW supprt 2 layer vlan */
11742 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
11743
11744 mutex_init(&hdev->vport_lock);
11745 spin_lock_init(&hdev->fd_rule_lock);
11746 sema_init(&hdev->reset_sem, 1);
11747
11748 ret = hclge_pci_init(hdev);
11749 if (ret)
11750 goto out;
11751
11752 /* Firmware command queue initialize */
11753 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
11754 if (ret)
11755 goto err_pci_uninit;
11756
11757 /* Firmware command initialize */
11758 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops);
11759 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11760 true, hdev->reset_pending);
11761 if (ret)
11762 goto err_cmd_uninit;
11763
11764 ret = hclge_clear_hw_resource(hdev);
11765 if (ret)
11766 goto err_cmd_uninit;
11767
11768 ret = hclge_get_cap(hdev);
11769 if (ret)
11770 goto err_cmd_uninit;
11771
11772 ret = hclge_query_dev_specs(hdev);
11773 if (ret) {
11774 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
11775 ret);
11776 goto err_cmd_uninit;
11777 }
11778
11779 ret = hclge_configure(hdev);
11780 if (ret) {
11781 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
11782 goto err_cmd_uninit;
11783 }
11784
11785 ret = hclge_init_msi(hdev);
11786 if (ret) {
11787 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
11788 goto err_cmd_uninit;
11789 }
11790
11791 ret = hclge_misc_irq_init(hdev);
11792 if (ret)
11793 goto err_msi_uninit;
11794
11795 ret = hclge_alloc_tqps(hdev);
11796 if (ret) {
11797 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
11798 goto err_msi_irq_uninit;
11799 }
11800
11801 ret = hclge_alloc_vport(hdev);
11802 if (ret)
11803 goto err_msi_irq_uninit;
11804
11805 ret = hclge_map_tqp(hdev);
11806 if (ret)
11807 goto err_msi_irq_uninit;
11808
11809 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
11810 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
11811 if (hnae3_dev_phy_imp_supported(hdev))
11812 ret = hclge_update_tp_port_info(hdev);
11813 else
11814 ret = hclge_mac_mdio_config(hdev);
11815
11816 if (ret)
11817 goto err_msi_irq_uninit;
11818 }
11819
11820 ret = hclge_init_umv_space(hdev);
11821 if (ret)
11822 goto err_mdiobus_unreg;
11823
11824 ret = hclge_mac_init(hdev);
11825 if (ret) {
11826 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11827 goto err_mdiobus_unreg;
11828 }
11829
11830 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11831 if (ret) {
11832 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11833 goto err_mdiobus_unreg;
11834 }
11835
11836 ret = hclge_config_gro(hdev);
11837 if (ret)
11838 goto err_mdiobus_unreg;
11839
11840 ret = hclge_init_vlan_config(hdev);
11841 if (ret) {
11842 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
11843 goto err_mdiobus_unreg;
11844 }
11845
11846 ret = hclge_tm_schd_init(hdev);
11847 if (ret) {
11848 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
11849 goto err_mdiobus_unreg;
11850 }
11851
11852 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev,
11853 &hdev->rss_cfg);
11854 if (ret) {
11855 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
11856 goto err_mdiobus_unreg;
11857 }
11858
11859 ret = hclge_rss_init_hw(hdev);
11860 if (ret) {
11861 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
11862 goto err_mdiobus_unreg;
11863 }
11864
11865 ret = init_mgr_tbl(hdev);
11866 if (ret) {
11867 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
11868 goto err_mdiobus_unreg;
11869 }
11870
11871 ret = hclge_init_fd_config(hdev);
11872 if (ret) {
11873 dev_err(&pdev->dev,
11874 "fd table init fail, ret=%d\n", ret);
11875 goto err_mdiobus_unreg;
11876 }
11877
11878 ret = hclge_ptp_init(hdev);
11879 if (ret)
11880 goto err_mdiobus_unreg;
11881
11882 ret = hclge_update_port_info(hdev);
11883 if (ret)
11884 goto err_ptp_uninit;
11885
11886 INIT_KFIFO(hdev->mac_tnl_log);
11887
11888 hclge_dcb_ops_set(hdev);
11889
11890 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
11891 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task);
11892
11893 hclge_clear_all_event_cause(hdev);
11894 hclge_clear_resetting_state(hdev);
11895
11896 /* Log and clear the hw errors those already occurred */
11897 if (hnae3_dev_ras_imp_supported(hdev))
11898 hclge_handle_occurred_error(hdev);
11899 else
11900 hclge_handle_all_hns_hw_errors(ae_dev);
11901
11902 /* request delayed reset for the error recovery because an immediate
11903 * global reset on a PF affecting pending initialization of other PFs
11904 */
11905 if (ae_dev->hw_err_reset_req) {
11906 enum hnae3_reset_type reset_level;
11907
11908 reset_level = hclge_get_reset_level(ae_dev,
11909 &ae_dev->hw_err_reset_req);
11910 hclge_set_def_reset_request(ae_dev, reset_level);
11911 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
11912 }
11913
11914 hclge_init_rxd_adv_layout(hdev);
11915
11916 ret = hclge_init_wol(hdev);
11917 if (ret)
11918 dev_warn(&pdev->dev,
11919 "failed to wake on lan init, ret = %d\n", ret);
11920
11921 ret = hclge_devlink_init(hdev);
11922 if (ret)
11923 goto err_ptp_uninit;
11924
11925 hclge_state_init(hdev);
11926 hdev->last_reset_time = jiffies;
11927
11928 /* Enable MISC vector(vector0) */
11929 enable_irq(hdev->misc_vector.vector_irq);
11930 hclge_enable_vector(&hdev->misc_vector, true);
11931
11932 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n",
11933 HCLGE_DRIVER_NAME);
11934
11935 hclge_task_schedule(hdev, round_jiffies_relative(HZ));
11936 return 0;
11937
11938 err_ptp_uninit:
11939 hclge_ptp_uninit(hdev);
11940 err_mdiobus_unreg:
11941 if (hdev->hw.mac.phydev)
11942 mdiobus_unregister(hdev->hw.mac.mdio_bus);
11943 err_msi_irq_uninit:
11944 hclge_misc_irq_uninit(hdev);
11945 err_msi_uninit:
11946 pci_free_irq_vectors(pdev);
11947 err_cmd_uninit:
11948 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
11949 err_pci_uninit:
11950 pcim_iounmap(pdev, hdev->hw.hw.io_base);
11951 pci_release_regions(pdev);
11952 pci_disable_device(pdev);
11953 out:
11954 mutex_destroy(&hdev->vport_lock);
11955 return ret;
11956 }
11957
hclge_stats_clear(struct hclge_dev * hdev)11958 static void hclge_stats_clear(struct hclge_dev *hdev)
11959 {
11960 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats));
11961 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats));
11962 }
11963
hclge_set_mac_spoofchk(struct hclge_dev * hdev,int vf,bool enable)11964 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11965 {
11966 return hclge_config_switch_param(hdev, vf, enable,
11967 HCLGE_SWITCH_ANTI_SPOOF_MASK);
11968 }
11969
hclge_set_vlan_spoofchk(struct hclge_dev * hdev,int vf,bool enable)11970 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11971 {
11972 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
11973 HCLGE_FILTER_FE_NIC_INGRESS_B,
11974 enable, vf);
11975 }
11976
hclge_set_vf_spoofchk_hw(struct hclge_dev * hdev,int vf,bool enable)11977 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable)
11978 {
11979 int ret;
11980
11981 ret = hclge_set_mac_spoofchk(hdev, vf, enable);
11982 if (ret) {
11983 dev_err(&hdev->pdev->dev,
11984 "Set vf %d mac spoof check %s failed, ret=%d\n",
11985 vf, str_on_off(enable), ret);
11986 return ret;
11987 }
11988
11989 ret = hclge_set_vlan_spoofchk(hdev, vf, enable);
11990 if (ret)
11991 dev_err(&hdev->pdev->dev,
11992 "Set vf %d vlan spoof check %s failed, ret=%d\n",
11993 vf, str_on_off(enable), ret);
11994
11995 return ret;
11996 }
11997
hclge_set_vf_spoofchk(struct hnae3_handle * handle,int vf,bool enable)11998 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
11999 bool enable)
12000 {
12001 struct hclge_vport *vport = hclge_get_vport(handle);
12002 struct hclge_dev *hdev = vport->back;
12003 u32 new_spoofchk = enable ? 1 : 0;
12004 int ret;
12005
12006 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
12007 return -EOPNOTSUPP;
12008
12009 vport = hclge_get_vf_vport(hdev, vf);
12010 if (!vport)
12011 return -EINVAL;
12012
12013 if (vport->vf_info.spoofchk == new_spoofchk)
12014 return 0;
12015
12016 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full))
12017 dev_warn(&hdev->pdev->dev,
12018 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n",
12019 vf);
12020 else if (enable && hclge_is_umv_space_full(vport, true))
12021 dev_warn(&hdev->pdev->dev,
12022 "vf %d mac table is full, enable spoof check may cause its packet send fail\n",
12023 vf);
12024
12025 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable);
12026 if (ret)
12027 return ret;
12028
12029 vport->vf_info.spoofchk = new_spoofchk;
12030 return 0;
12031 }
12032
hclge_reset_vport_spoofchk(struct hclge_dev * hdev)12033 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
12034 {
12035 struct hclge_vport *vport = hdev->vport;
12036 int ret;
12037 int i;
12038
12039 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
12040 return 0;
12041
12042 /* resume the vf spoof check state after reset */
12043 for (i = 0; i < hdev->num_alloc_vport; i++) {
12044 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id,
12045 vport->vf_info.spoofchk);
12046 if (ret)
12047 return ret;
12048
12049 vport++;
12050 }
12051
12052 return 0;
12053 }
12054
hclge_set_vf_trust(struct hnae3_handle * handle,int vf,bool enable)12055 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable)
12056 {
12057 struct hclge_vport *vport = hclge_get_vport(handle);
12058 struct hclge_dev *hdev = vport->back;
12059 u32 new_trusted = enable ? 1 : 0;
12060
12061 vport = hclge_get_vf_vport(hdev, vf);
12062 if (!vport)
12063 return -EINVAL;
12064
12065 if (vport->vf_info.trusted == new_trusted)
12066 return 0;
12067
12068 vport->vf_info.trusted = new_trusted;
12069 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12070 hclge_task_schedule(hdev, 0);
12071
12072 return 0;
12073 }
12074
hclge_reset_vf_rate(struct hclge_dev * hdev)12075 static void hclge_reset_vf_rate(struct hclge_dev *hdev)
12076 {
12077 int ret;
12078 int vf;
12079
12080 /* reset vf rate to default value */
12081 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
12082 struct hclge_vport *vport = &hdev->vport[vf];
12083
12084 vport->vf_info.max_tx_rate = 0;
12085 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate);
12086 if (ret)
12087 dev_err(&hdev->pdev->dev,
12088 "vf%d failed to reset to default, ret=%d\n",
12089 vf - HCLGE_VF_VPORT_START_NUM, ret);
12090 }
12091 }
12092
hclge_vf_rate_param_check(struct hclge_dev * hdev,int min_tx_rate,int max_tx_rate)12093 static int hclge_vf_rate_param_check(struct hclge_dev *hdev,
12094 int min_tx_rate, int max_tx_rate)
12095 {
12096 if (min_tx_rate != 0 ||
12097 max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) {
12098 dev_err(&hdev->pdev->dev,
12099 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n",
12100 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed);
12101 return -EINVAL;
12102 }
12103
12104 return 0;
12105 }
12106
hclge_set_vf_rate(struct hnae3_handle * handle,int vf,int min_tx_rate,int max_tx_rate,bool force)12107 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf,
12108 int min_tx_rate, int max_tx_rate, bool force)
12109 {
12110 struct hclge_vport *vport = hclge_get_vport(handle);
12111 struct hclge_dev *hdev = vport->back;
12112 int ret;
12113
12114 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate);
12115 if (ret)
12116 return ret;
12117
12118 vport = hclge_get_vf_vport(hdev, vf);
12119 if (!vport)
12120 return -EINVAL;
12121
12122 if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate)
12123 return 0;
12124
12125 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate);
12126 if (ret)
12127 return ret;
12128
12129 vport->vf_info.max_tx_rate = max_tx_rate;
12130
12131 return 0;
12132 }
12133
hclge_resume_vf_rate(struct hclge_dev * hdev)12134 static int hclge_resume_vf_rate(struct hclge_dev *hdev)
12135 {
12136 struct hnae3_handle *handle = &hdev->vport->nic;
12137 struct hclge_vport *vport;
12138 int ret;
12139 int vf;
12140
12141 /* resume the vf max_tx_rate after reset */
12142 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) {
12143 vport = hclge_get_vf_vport(hdev, vf);
12144 if (!vport)
12145 return -EINVAL;
12146
12147 /* zero means max rate, after reset, firmware already set it to
12148 * max rate, so just continue.
12149 */
12150 if (!vport->vf_info.max_tx_rate)
12151 continue;
12152
12153 ret = hclge_set_vf_rate(handle, vf, 0,
12154 vport->vf_info.max_tx_rate, true);
12155 if (ret) {
12156 dev_err(&hdev->pdev->dev,
12157 "vf%d failed to resume tx_rate:%u, ret=%d\n",
12158 vf, vport->vf_info.max_tx_rate, ret);
12159 return ret;
12160 }
12161 }
12162
12163 return 0;
12164 }
12165
hclge_reset_vport_state(struct hclge_dev * hdev)12166 static void hclge_reset_vport_state(struct hclge_dev *hdev)
12167 {
12168 struct hclge_vport *vport = hdev->vport;
12169 int i;
12170
12171 for (i = 0; i < hdev->num_alloc_vport; i++) {
12172 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
12173 vport++;
12174 }
12175 }
12176
hclge_reset_ae_dev(struct hnae3_ae_dev * ae_dev)12177 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
12178 {
12179 struct hclge_dev *hdev = ae_dev->priv;
12180 struct pci_dev *pdev = ae_dev->pdev;
12181 int ret;
12182
12183 set_bit(HCLGE_STATE_DOWN, &hdev->state);
12184
12185 hclge_stats_clear(hdev);
12186 /* NOTE: pf reset needn't to clear or restore pf and vf table entry.
12187 * so here should not clean table in memory.
12188 */
12189 if (hdev->reset_type == HNAE3_IMP_RESET ||
12190 hdev->reset_type == HNAE3_GLOBAL_RESET) {
12191 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
12192 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
12193 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport);
12194 hclge_reset_umv_space(hdev);
12195 }
12196
12197 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
12198 true, hdev->reset_pending);
12199 if (ret) {
12200 dev_err(&pdev->dev, "Cmd queue init failed\n");
12201 return ret;
12202 }
12203
12204 ret = hclge_map_tqp(hdev);
12205 if (ret) {
12206 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
12207 return ret;
12208 }
12209
12210 ret = hclge_mac_init(hdev);
12211 if (ret) {
12212 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
12213 return ret;
12214 }
12215
12216 ret = hclge_tp_port_init(hdev);
12217 if (ret) {
12218 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
12219 ret);
12220 return ret;
12221 }
12222
12223 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
12224 if (ret) {
12225 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
12226 return ret;
12227 }
12228
12229 ret = hclge_config_gro(hdev);
12230 if (ret)
12231 return ret;
12232
12233 ret = hclge_init_vlan_config(hdev);
12234 if (ret) {
12235 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
12236 return ret;
12237 }
12238
12239 hclge_reset_tc_config(hdev);
12240
12241 ret = hclge_tm_init_hw(hdev, true);
12242 if (ret) {
12243 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
12244 return ret;
12245 }
12246
12247 ret = hclge_rss_init_hw(hdev);
12248 if (ret) {
12249 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
12250 return ret;
12251 }
12252
12253 ret = init_mgr_tbl(hdev);
12254 if (ret) {
12255 dev_err(&pdev->dev,
12256 "failed to reinit manager table, ret = %d\n", ret);
12257 return ret;
12258 }
12259
12260 ret = hclge_init_fd_config(hdev);
12261 if (ret) {
12262 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret);
12263 return ret;
12264 }
12265
12266 ret = hclge_ptp_init(hdev);
12267 if (ret)
12268 return ret;
12269
12270 /* Log and clear the hw errors those already occurred */
12271 if (hnae3_dev_ras_imp_supported(hdev))
12272 hclge_handle_occurred_error(hdev);
12273 else
12274 hclge_handle_all_hns_hw_errors(ae_dev);
12275
12276 /* Re-enable the hw error interrupts because
12277 * the interrupts get disabled on global reset.
12278 */
12279 ret = hclge_config_nic_hw_error(hdev, true);
12280 if (ret) {
12281 dev_err(&pdev->dev,
12282 "fail(%d) to re-enable NIC hw error interrupts\n",
12283 ret);
12284 return ret;
12285 }
12286
12287 if (hdev->roce_client) {
12288 ret = hclge_config_rocee_ras_interrupt(hdev, true);
12289 if (ret) {
12290 dev_err(&pdev->dev,
12291 "fail(%d) to re-enable roce ras interrupts\n",
12292 ret);
12293 return ret;
12294 }
12295 }
12296
12297 hclge_reset_vport_state(hdev);
12298 ret = hclge_reset_vport_spoofchk(hdev);
12299 if (ret)
12300 return ret;
12301
12302 ret = hclge_resume_vf_rate(hdev);
12303 if (ret)
12304 return ret;
12305
12306 hclge_init_rxd_adv_layout(hdev);
12307
12308 ret = hclge_update_wol(hdev);
12309 if (ret)
12310 dev_warn(&pdev->dev,
12311 "failed to update wol config, ret = %d\n", ret);
12312
12313 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
12314 HCLGE_DRIVER_NAME);
12315
12316 return 0;
12317 }
12318
hclge_uninit_ae_dev(struct hnae3_ae_dev * ae_dev)12319 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
12320 {
12321 struct hclge_dev *hdev = ae_dev->priv;
12322 struct hclge_mac *mac = &hdev->hw.mac;
12323
12324 hclge_reset_vf_rate(hdev);
12325 hclge_clear_vf_vlan(hdev);
12326 hclge_state_uninit(hdev);
12327 hclge_ptp_uninit(hdev);
12328 hclge_uninit_rxd_adv_layout(hdev);
12329 hclge_uninit_mac_table(hdev);
12330 hclge_del_all_fd_entries(hdev);
12331
12332 if (mac->phydev)
12333 mdiobus_unregister(mac->mdio_bus);
12334
12335 /* Disable MISC vector(vector0) */
12336 hclge_enable_vector(&hdev->misc_vector, false);
12337 disable_irq(hdev->misc_vector.vector_irq);
12338
12339 /* Disable all hw interrupts */
12340 hclge_config_mac_tnl_int(hdev, false);
12341 hclge_config_nic_hw_error(hdev, false);
12342 hclge_config_rocee_ras_interrupt(hdev, false);
12343
12344 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
12345 hclge_misc_irq_uninit(hdev);
12346 hclge_devlink_uninit(hdev);
12347 hclge_pci_uninit(hdev);
12348 hclge_uninit_vport_vlan_table(hdev);
12349 mutex_destroy(&hdev->vport_lock);
12350 ae_dev->priv = NULL;
12351 }
12352
hclge_get_max_channels(struct hnae3_handle * handle)12353 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
12354 {
12355 struct hclge_vport *vport = hclge_get_vport(handle);
12356 struct hclge_dev *hdev = vport->back;
12357
12358 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps);
12359 }
12360
hclge_get_channels(struct hnae3_handle * handle,struct ethtool_channels * ch)12361 static void hclge_get_channels(struct hnae3_handle *handle,
12362 struct ethtool_channels *ch)
12363 {
12364 ch->max_combined = hclge_get_max_channels(handle);
12365 ch->other_count = 1;
12366 ch->max_other = 1;
12367 ch->combined_count = handle->kinfo.rss_size;
12368 }
12369
hclge_get_tqps_and_rss_info(struct hnae3_handle * handle,u16 * alloc_tqps,u16 * max_rss_size)12370 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
12371 u16 *alloc_tqps, u16 *max_rss_size)
12372 {
12373 struct hclge_vport *vport = hclge_get_vport(handle);
12374 struct hclge_dev *hdev = vport->back;
12375
12376 *alloc_tqps = vport->alloc_tqps;
12377 *max_rss_size = hdev->pf_rss_size_max;
12378 }
12379
hclge_set_rss_tc_mode_cfg(struct hnae3_handle * handle)12380 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle)
12381 {
12382 struct hclge_vport *vport = hclge_get_vport(handle);
12383 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
12384 struct hclge_dev *hdev = vport->back;
12385 u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
12386 u16 tc_valid[HCLGE_MAX_TC_NUM];
12387 u16 roundup_size;
12388 unsigned int i;
12389
12390 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size);
12391 roundup_size = ilog2(roundup_size);
12392 /* Set the RSS TC mode according to the new RSS size */
12393 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
12394 tc_valid[i] = 0;
12395
12396 if (!(hdev->hw_tc_map & BIT(i)))
12397 continue;
12398
12399 tc_valid[i] = 1;
12400 tc_size[i] = roundup_size;
12401 tc_offset[i] = vport->nic.kinfo.rss_size * i;
12402 }
12403
12404 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
12405 tc_size);
12406 }
12407
hclge_set_channels(struct hnae3_handle * handle,u32 new_tqps_num,bool rxfh_configured)12408 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
12409 bool rxfh_configured)
12410 {
12411 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
12412 struct hclge_vport *vport = hclge_get_vport(handle);
12413 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
12414 struct hclge_dev *hdev = vport->back;
12415 u16 cur_rss_size = kinfo->rss_size;
12416 u16 cur_tqps = kinfo->num_tqps;
12417 u32 *rss_indir;
12418 unsigned int i;
12419 int ret;
12420
12421 kinfo->req_rss_size = new_tqps_num;
12422
12423 ret = hclge_tm_vport_map_update(hdev);
12424 if (ret) {
12425 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
12426 return ret;
12427 }
12428
12429 ret = hclge_set_rss_tc_mode_cfg(handle);
12430 if (ret)
12431 return ret;
12432
12433 /* RSS indirection table has been configured by user */
12434 if (rxfh_configured)
12435 goto out;
12436
12437 /* Reinitializes the rss indirect table according to the new RSS size */
12438 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32),
12439 GFP_KERNEL);
12440 if (!rss_indir)
12441 return -ENOMEM;
12442
12443 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
12444 rss_indir[i] = i % kinfo->rss_size;
12445
12446 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
12447 if (ret)
12448 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
12449 ret);
12450
12451 kfree(rss_indir);
12452
12453 out:
12454 if (!ret)
12455 dev_info(&hdev->pdev->dev,
12456 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
12457 cur_rss_size, kinfo->rss_size,
12458 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
12459
12460 return ret;
12461 }
12462
hclge_set_led_status(struct hclge_dev * hdev,u8 locate_led_status)12463 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
12464 {
12465 struct hclge_set_led_state_cmd *req;
12466 struct hclge_desc desc;
12467 int ret;
12468
12469 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
12470
12471 req = (struct hclge_set_led_state_cmd *)desc.data;
12472 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
12473 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
12474
12475 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12476 if (ret)
12477 dev_err(&hdev->pdev->dev,
12478 "Send set led state cmd error, ret =%d\n", ret);
12479
12480 return ret;
12481 }
12482
12483 enum hclge_led_status {
12484 HCLGE_LED_OFF,
12485 HCLGE_LED_ON,
12486 HCLGE_LED_NO_CHANGE = 0xFF,
12487 };
12488
hclge_set_led_id(struct hnae3_handle * handle,enum ethtool_phys_id_state status)12489 static int hclge_set_led_id(struct hnae3_handle *handle,
12490 enum ethtool_phys_id_state status)
12491 {
12492 struct hclge_vport *vport = hclge_get_vport(handle);
12493 struct hclge_dev *hdev = vport->back;
12494
12495 switch (status) {
12496 case ETHTOOL_ID_ACTIVE:
12497 return hclge_set_led_status(hdev, HCLGE_LED_ON);
12498 case ETHTOOL_ID_INACTIVE:
12499 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
12500 default:
12501 return -EINVAL;
12502 }
12503 }
12504
hclge_get_link_mode(struct hnae3_handle * handle,unsigned long * supported,unsigned long * advertising)12505 static void hclge_get_link_mode(struct hnae3_handle *handle,
12506 unsigned long *supported,
12507 unsigned long *advertising)
12508 {
12509 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
12510 struct hclge_vport *vport = hclge_get_vport(handle);
12511 struct hclge_dev *hdev = vport->back;
12512 unsigned int idx = 0;
12513
12514 for (; idx < size; idx++) {
12515 supported[idx] = hdev->hw.mac.supported[idx];
12516 advertising[idx] = hdev->hw.mac.advertising[idx];
12517 }
12518 }
12519
hclge_gro_en(struct hnae3_handle * handle,bool enable)12520 static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
12521 {
12522 struct hclge_vport *vport = hclge_get_vport(handle);
12523 struct hclge_dev *hdev = vport->back;
12524 bool gro_en_old = hdev->gro_en;
12525 int ret;
12526
12527 hdev->gro_en = enable;
12528 ret = hclge_config_gro(hdev);
12529 if (ret)
12530 hdev->gro_en = gro_en_old;
12531
12532 return ret;
12533 }
12534
hclge_sync_vport_promisc_mode(struct hclge_vport * vport)12535 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport)
12536 {
12537 struct hnae3_handle *handle = &vport->nic;
12538 struct hclge_dev *hdev = vport->back;
12539 bool uc_en = false;
12540 bool mc_en = false;
12541 u8 tmp_flags;
12542 bool bc_en;
12543 int ret;
12544
12545 if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
12546 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12547 vport->last_promisc_flags = vport->overflow_promisc_flags;
12548 }
12549
12550 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12551 &vport->state))
12552 return 0;
12553
12554 /* for PF */
12555 if (!vport->vport_id) {
12556 tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
12557 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
12558 tmp_flags & HNAE3_MPE);
12559 if (!ret)
12560 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
12561 &vport->state);
12562 else
12563 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12564 &vport->state);
12565 return ret;
12566 }
12567
12568 /* for VF */
12569 if (vport->vf_info.trusted) {
12570 uc_en = vport->vf_info.request_uc_en > 0 ||
12571 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE;
12572 mc_en = vport->vf_info.request_mc_en > 0 ||
12573 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE;
12574 }
12575 bc_en = vport->vf_info.request_bc_en > 0;
12576
12577 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
12578 mc_en, bc_en);
12579 if (ret) {
12580 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12581 return ret;
12582 }
12583 hclge_set_vport_vlan_fltr_change(vport);
12584
12585 return 0;
12586 }
12587
hclge_sync_promisc_mode(struct hclge_dev * hdev)12588 static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
12589 {
12590 struct hclge_vport *vport;
12591 int ret;
12592 u16 i;
12593
12594 for (i = 0; i < hdev->num_alloc_vport; i++) {
12595 vport = &hdev->vport[i];
12596
12597 ret = hclge_sync_vport_promisc_mode(vport);
12598 if (ret)
12599 return;
12600 }
12601 }
12602
hclge_module_existed(struct hclge_dev * hdev)12603 static bool hclge_module_existed(struct hclge_dev *hdev)
12604 {
12605 struct hclge_desc desc;
12606 u32 existed;
12607 int ret;
12608
12609 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true);
12610 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12611 if (ret) {
12612 dev_err(&hdev->pdev->dev,
12613 "failed to get SFP exist state, ret = %d\n", ret);
12614 return false;
12615 }
12616
12617 existed = le32_to_cpu(desc.data[0]);
12618
12619 return existed != 0;
12620 }
12621
12622 /* need 6 bds(total 140 bytes) in one reading
12623 * return the number of bytes actually read, 0 means read failed.
12624 */
hclge_get_sfp_eeprom_info(struct hclge_dev * hdev,u32 offset,u32 len,u8 * data)12625 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
12626 u32 len, u8 *data)
12627 {
12628 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM];
12629 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0;
12630 u16 read_len;
12631 u16 copy_len;
12632 int ret;
12633 int i;
12634
12635 /* setup all 6 bds to read module eeprom info. */
12636 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12637 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM,
12638 true);
12639
12640 /* bd0~bd4 need next flag */
12641 if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
12642 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12643 }
12644
12645 /* setup bd0, this bd contains offset and read length. */
12646 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data;
12647 sfp_info_bd0->offset = cpu_to_le16((u16)offset);
12648 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN);
12649 sfp_info_bd0->read_len = cpu_to_le16(read_len);
12650
12651 ret = hclge_cmd_send(&hdev->hw, desc, i);
12652 if (ret) {
12653 dev_err(&hdev->pdev->dev,
12654 "failed to get SFP eeprom info, ret = %d\n", ret);
12655 return 0;
12656 }
12657
12658 /* copy sfp info from bd0 to out buffer. */
12659 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN);
12660 memcpy(data, sfp_info_bd0->data, copy_len);
12661 read_len = copy_len;
12662
12663 /* copy sfp info from bd1~bd5 to out buffer if needed. */
12664 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12665 if (read_len >= len)
12666 return read_len;
12667
12668 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN);
12669 memcpy(data + read_len, desc[i].data, copy_len);
12670 read_len += copy_len;
12671 }
12672
12673 return read_len;
12674 }
12675
hclge_get_module_eeprom(struct hnae3_handle * handle,u32 offset,u32 len,u8 * data)12676 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset,
12677 u32 len, u8 *data)
12678 {
12679 struct hclge_vport *vport = hclge_get_vport(handle);
12680 struct hclge_dev *hdev = vport->back;
12681 u32 read_len = 0;
12682 u16 data_len;
12683
12684 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
12685 return -EOPNOTSUPP;
12686
12687 if (!hclge_module_existed(hdev))
12688 return -ENXIO;
12689
12690 while (read_len < len) {
12691 data_len = hclge_get_sfp_eeprom_info(hdev,
12692 offset + read_len,
12693 len - read_len,
12694 data + read_len);
12695 if (!data_len)
12696 return -EIO;
12697
12698 read_len += data_len;
12699 }
12700
12701 return 0;
12702 }
12703
hclge_get_link_diagnosis_info(struct hnae3_handle * handle,u32 * status_code)12704 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
12705 u32 *status_code)
12706 {
12707 struct hclge_vport *vport = hclge_get_vport(handle);
12708 struct hclge_dev *hdev = vport->back;
12709 struct hclge_desc desc;
12710 int ret;
12711
12712 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
12713 return -EOPNOTSUPP;
12714
12715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
12716 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12717 if (ret) {
12718 dev_err(&hdev->pdev->dev,
12719 "failed to query link diagnosis info, ret = %d\n", ret);
12720 return ret;
12721 }
12722
12723 *status_code = le32_to_cpu(desc.data[0]);
12724 return 0;
12725 }
12726
12727 /* After disable sriov, VF still has some config and info need clean,
12728 * which configed by PF.
12729 */
hclge_clear_vport_vf_info(struct hclge_vport * vport,int vfid)12730 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
12731 {
12732 struct hclge_dev *hdev = vport->back;
12733 struct hclge_vlan_info vlan_info;
12734 int ret;
12735
12736 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
12737 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
12738 vport->need_notify = 0;
12739 vport->mps = 0;
12740
12741 /* after disable sriov, clean VF rate configured by PF */
12742 ret = hclge_tm_qs_shaper_cfg(vport, 0);
12743 if (ret)
12744 dev_err(&hdev->pdev->dev,
12745 "failed to clean vf%d rate config, ret = %d\n",
12746 vfid, ret);
12747
12748 vlan_info.vlan_tag = 0;
12749 vlan_info.qos = 0;
12750 vlan_info.vlan_proto = ETH_P_8021Q;
12751 ret = hclge_update_port_base_vlan_cfg(vport,
12752 HNAE3_PORT_BASE_VLAN_DISABLE,
12753 &vlan_info);
12754 if (ret)
12755 dev_err(&hdev->pdev->dev,
12756 "failed to clean vf%d port base vlan, ret = %d\n",
12757 vfid, ret);
12758
12759 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false);
12760 if (ret)
12761 dev_err(&hdev->pdev->dev,
12762 "failed to clean vf%d spoof config, ret = %d\n",
12763 vfid, ret);
12764
12765 memset(&vport->vf_info, 0, sizeof(vport->vf_info));
12766 }
12767
hclge_clean_vport_config(struct hnae3_ae_dev * ae_dev,int num_vfs)12768 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs)
12769 {
12770 struct hclge_dev *hdev = ae_dev->priv;
12771 struct hclge_vport *vport;
12772 int i;
12773
12774 for (i = 0; i < num_vfs; i++) {
12775 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
12776
12777 hclge_clear_vport_vf_info(vport, i);
12778 }
12779 }
12780
hclge_get_dscp_prio(struct hnae3_handle * h,u8 dscp,u8 * tc_mode,u8 * priority)12781 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode,
12782 u8 *priority)
12783 {
12784 struct hclge_vport *vport = hclge_get_vport(h);
12785
12786 if (dscp >= HNAE3_MAX_DSCP)
12787 return -EINVAL;
12788
12789 if (tc_mode)
12790 *tc_mode = vport->nic.kinfo.tc_map_mode;
12791 if (priority)
12792 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
12793 vport->nic.kinfo.dscp_prio[dscp];
12794
12795 return 0;
12796 }
12797
12798 static const struct hnae3_ae_ops hclge_ops = {
12799 .init_ae_dev = hclge_init_ae_dev,
12800 .uninit_ae_dev = hclge_uninit_ae_dev,
12801 .reset_prepare = hclge_reset_prepare_general,
12802 .reset_done = hclge_reset_done,
12803 .init_client_instance = hclge_init_client_instance,
12804 .uninit_client_instance = hclge_uninit_client_instance,
12805 .map_ring_to_vector = hclge_map_ring_to_vector,
12806 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
12807 .get_vector = hclge_get_vector,
12808 .put_vector = hclge_put_vector,
12809 .set_promisc_mode = hclge_set_promisc_mode,
12810 .request_update_promisc_mode = hclge_request_update_promisc_mode,
12811 .set_loopback = hclge_set_loopback,
12812 .start = hclge_ae_start,
12813 .stop = hclge_ae_stop,
12814 .client_start = hclge_client_start,
12815 .client_stop = hclge_client_stop,
12816 .get_status = hclge_get_status,
12817 .get_ksettings_an_result = hclge_get_ksettings_an_result,
12818 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
12819 .get_media_type = hclge_get_media_type,
12820 .check_port_speed = hclge_check_port_speed,
12821 .get_fec_stats = hclge_get_fec_stats,
12822 .get_fec = hclge_get_fec,
12823 .set_fec = hclge_set_fec,
12824 .get_rss_key_size = hclge_comm_get_rss_key_size,
12825 .get_rss = hclge_get_rss,
12826 .set_rss = hclge_set_rss,
12827 .set_rss_tuple = hclge_set_rss_tuple,
12828 .get_rss_tuple = hclge_get_rss_tuple,
12829 .get_tc_size = hclge_get_tc_size,
12830 .get_mac_addr = hclge_get_mac_addr,
12831 .set_mac_addr = hclge_set_mac_addr,
12832 .do_ioctl = hclge_do_ioctl,
12833 .add_uc_addr = hclge_add_uc_addr,
12834 .rm_uc_addr = hclge_rm_uc_addr,
12835 .add_mc_addr = hclge_add_mc_addr,
12836 .rm_mc_addr = hclge_rm_mc_addr,
12837 .set_autoneg = hclge_set_autoneg,
12838 .get_autoneg = hclge_get_autoneg,
12839 .restart_autoneg = hclge_restart_autoneg,
12840 .halt_autoneg = hclge_halt_autoneg,
12841 .get_pauseparam = hclge_get_pauseparam,
12842 .set_pauseparam = hclge_set_pauseparam,
12843 .set_mtu = hclge_set_mtu,
12844 .reset_queue = hclge_reset_tqp,
12845 .get_stats = hclge_get_stats,
12846 .get_mac_stats = hclge_get_mac_stat,
12847 .update_stats = hclge_update_stats,
12848 .get_strings = hclge_get_strings,
12849 .get_sset_count = hclge_get_sset_count,
12850 .get_fw_version = hclge_get_fw_version,
12851 .get_mdix_mode = hclge_get_mdix_mode,
12852 .enable_vlan_filter = hclge_enable_vlan_filter,
12853 .set_vlan_filter = hclge_set_vlan_filter,
12854 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
12855 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
12856 .reset_event = hclge_reset_event,
12857 .get_reset_level = hclge_get_reset_level,
12858 .set_default_reset_request = hclge_set_def_reset_request,
12859 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
12860 .set_channels = hclge_set_channels,
12861 .get_channels = hclge_get_channels,
12862 .get_regs_len = hclge_get_regs_len,
12863 .get_regs = hclge_get_regs,
12864 .set_led_id = hclge_set_led_id,
12865 .get_link_mode = hclge_get_link_mode,
12866 .add_fd_entry = hclge_add_fd_entry,
12867 .del_fd_entry = hclge_del_fd_entry,
12868 .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
12869 .get_fd_rule_info = hclge_get_fd_rule_info,
12870 .get_fd_all_rules = hclge_get_all_rules,
12871 .enable_fd = hclge_enable_fd,
12872 .add_arfs_entry = hclge_add_fd_entry_by_arfs,
12873 .dbg_get_read_func = hclge_dbg_get_read_func,
12874 .handle_hw_ras_error = hclge_handle_hw_ras_error,
12875 .get_hw_reset_stat = hclge_get_hw_reset_stat,
12876 .ae_dev_resetting = hclge_ae_dev_resetting,
12877 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
12878 .set_gro_en = hclge_gro_en,
12879 .get_global_queue_id = hclge_covert_handle_qid_global,
12880 .set_timer_task = hclge_set_timer_task,
12881 .mac_connect_phy = hclge_mac_connect_phy,
12882 .mac_disconnect_phy = hclge_mac_disconnect_phy,
12883 .get_vf_config = hclge_get_vf_config,
12884 .set_vf_link_state = hclge_set_vf_link_state,
12885 .set_vf_spoofchk = hclge_set_vf_spoofchk,
12886 .set_vf_trust = hclge_set_vf_trust,
12887 .set_vf_rate = hclge_set_vf_rate,
12888 .set_vf_mac = hclge_set_vf_mac,
12889 .get_module_eeprom = hclge_get_module_eeprom,
12890 .get_cmdq_stat = hclge_get_cmdq_stat,
12891 .add_cls_flower = hclge_add_cls_flower,
12892 .del_cls_flower = hclge_del_cls_flower,
12893 .cls_flower_active = hclge_is_cls_flower_active,
12894 .get_phy_link_ksettings = hclge_get_phy_link_ksettings,
12895 .set_phy_link_ksettings = hclge_set_phy_link_ksettings,
12896 .set_tx_hwts_info = hclge_ptp_set_tx_info,
12897 .get_rx_hwts = hclge_ptp_get_rx_hwts,
12898 .get_ts_info = hclge_ptp_get_ts_info,
12899 .get_link_diagnosis_info = hclge_get_link_diagnosis_info,
12900 .clean_vf_config = hclge_clean_vport_config,
12901 .get_dscp_prio = hclge_get_dscp_prio,
12902 .get_wol = hclge_get_wol,
12903 .set_wol = hclge_set_wol,
12904 .hwtstamp_get = hclge_ptp_get_cfg,
12905 .hwtstamp_set = hclge_ptp_set_cfg,
12906 };
12907
12908 static struct hnae3_ae_algo ae_algo = {
12909 .ops = &hclge_ops,
12910 .pdev_id_table = ae_algo_pci_tbl,
12911 };
12912
hclge_init(void)12913 static int __init hclge_init(void)
12914 {
12915 pr_debug("%s is initializing\n", HCLGE_NAME);
12916
12917 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0,
12918 HCLGE_NAME);
12919 if (!hclge_wq) {
12920 pr_err("%s: failed to create workqueue\n", HCLGE_NAME);
12921 return -ENOMEM;
12922 }
12923
12924 hnae3_register_ae_algo(&ae_algo);
12925
12926 return 0;
12927 }
12928
hclge_exit(void)12929 static void __exit hclge_exit(void)
12930 {
12931 hnae3_acquire_unload_lock();
12932 hnae3_unregister_ae_algo_prepare(&ae_algo);
12933 hnae3_unregister_ae_algo(&ae_algo);
12934 destroy_workqueue(hclge_wq);
12935 hnae3_release_unload_lock();
12936 }
12937 module_init(hclge_init);
12938 module_exit(hclge_exit);
12939
12940 MODULE_LICENSE("GPL");
12941 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
12942 MODULE_DESCRIPTION("HCLGE Driver");
12943 MODULE_VERSION(HCLGE_MOD_VERSION);
12944