1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1363.c 4 * Copyright (C) 2008-2010 Jonathan Cameron 5 * 6 * based on linux/drivers/i2c/chips/max123x 7 * Copyright (C) 2002-2004 Stefan Eletzhofer 8 * 9 * based on linux/drivers/acron/char/pcf8583.c 10 * Copyright (C) 2000 Russell King 11 * 12 * Driver for max1363 and similar chips. 13 */ 14 15 #include <linux/interrupt.h> 16 #include <linux/cleanup.h> 17 #include <linux/device.h> 18 #include <linux/kernel.h> 19 #include <linux/sysfs.h> 20 #include <linux/list.h> 21 #include <linux/i2c.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/err.h> 25 #include <linux/module.h> 26 #include <linux/property.h> 27 #include <linux/unaligned.h> 28 29 #include <linux/iio/iio.h> 30 #include <linux/iio/sysfs.h> 31 #include <linux/iio/events.h> 32 #include <linux/iio/buffer.h> 33 #include <linux/iio/kfifo_buf.h> 34 #include <linux/iio/trigger_consumer.h> 35 #include <linux/iio/triggered_buffer.h> 36 37 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80) 38 39 /* There is a fair bit more defined here than currently 40 * used, but the intention is to support everything these 41 * chips do in the long run */ 42 43 /* see data sheets */ 44 /* max1363 and max1236, max1237, max1238, max1239 */ 45 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00 46 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20 47 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40 48 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60 49 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10 50 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00 51 52 /* think about including max11600 etc - more settings */ 53 #define MAX1363_SETUP_EXT_CLOCK 0x08 54 #define MAX1363_SETUP_INT_CLOCK 0x00 55 #define MAX1363_SETUP_UNIPOLAR 0x00 56 #define MAX1363_SETUP_BIPOLAR 0x04 57 #define MAX1363_SETUP_RESET 0x00 58 #define MAX1363_SETUP_NORESET 0x02 59 /* max1363 only - though don't care on others. 60 * For now monitor modes are not implemented as the relevant 61 * line is not connected on my test board. 62 * The definitions are here as I intend to add this soon. 63 */ 64 #define MAX1363_SETUP_MONITOR_SETUP 0x01 65 66 /* Specific to the max1363 */ 67 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4)) 68 #define MAX1363_MON_INT_ENABLE 0x01 69 70 /* defined for readability reasons */ 71 /* All chips */ 72 #define MAX1363_CONFIG_BYTE(a) ((a)) 73 74 #define MAX1363_CONFIG_SE 0x01 75 #define MAX1363_CONFIG_DE 0x00 76 #define MAX1363_CONFIG_SCAN_TO_CS 0x00 77 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20 78 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40 79 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60 80 /* max123{6-9} only */ 81 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40 82 83 /* max1363 only - merely part of channel selects or don't care for others */ 84 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18 85 86 #define MAX1363_CHANNEL_SEL(a) ((a) << 1) 87 88 /* max1363 strictly 0x06 - but doesn't matter */ 89 #define MAX1363_CHANNEL_SEL_MASK 0x1E 90 #define MAX1363_SCAN_MASK 0x60 91 #define MAX1363_SE_DE_MASK 0x01 92 93 #define MAX1363_MAX_CHANNELS 25 94 /** 95 * struct max1363_mode - scan mode information 96 * @conf: The corresponding value of the configuration register 97 * @modemask: Bit mask corresponding to channels enabled in this mode 98 */ 99 struct max1363_mode { 100 int8_t conf; 101 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS); 102 }; 103 104 /* This must be maintained along side the max1363_mode_table in max1363_core */ 105 enum max1363_modes { 106 /* Single read of a single channel */ 107 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 108 /* Differential single read */ 109 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 110 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 111 /* Scan to channel and mid to channel where overlapping */ 112 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6, 113 s6to7, s0to7, s6to8, s0to8, s6to9, 114 s0to9, s6to10, s0to10, s6to11, s0to11, 115 /* Differential scan to channel and mid to channel where overlapping */ 116 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9, 117 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2, 118 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8, 119 d7m6to11m10, d1m0to11m10, 120 }; 121 122 /** 123 * struct max1363_chip_info - chip specific information 124 * @info: iio core function callbacks structure 125 * @channels: channel specification 126 * @num_channels: number of channels 127 * @mode_list: array of available scan modes 128 * @default_mode: the scan mode in which the chip starts up 129 * @int_vref_mv: the internal reference voltage 130 * @num_modes: number of modes 131 * @bits: accuracy of the adc in bits 132 */ 133 struct max1363_chip_info { 134 const struct iio_info *info; 135 const struct iio_chan_spec *channels; 136 int num_channels; 137 const enum max1363_modes *mode_list; 138 enum max1363_modes default_mode; 139 u16 int_vref_mv; 140 u8 num_modes; 141 u8 bits; 142 }; 143 144 /** 145 * struct max1363_state - driver instance specific data 146 * @client: i2c_client 147 * @setupbyte: cache of current device setup byte 148 * @configbyte: cache of current device config byte 149 * @chip_info: chip model specific constants, available modes, etc. 150 * @current_mode: the scan mode of this chip 151 * @lock: lock to ensure state is consistent 152 * @monitor_on: whether monitor mode is enabled 153 * @monitor_speed: parameter corresponding to device monitor speed setting 154 * @mask_high: bitmask for enabled high thresholds 155 * @mask_low: bitmask for enabled low thresholds 156 * @thresh_high: high threshold values 157 * @thresh_low: low threshold values 158 * @vref: Reference voltage regulator 159 * @vref_uv: Actual (external or internal) reference voltage 160 * @send: function used to send data to the chip 161 * @recv: function used to receive data from the chip 162 * @data: buffer to store channel data and timestamp 163 */ 164 struct max1363_state { 165 struct i2c_client *client; 166 u8 setupbyte; 167 u8 configbyte; 168 const struct max1363_chip_info *chip_info; 169 const struct max1363_mode *current_mode; 170 struct mutex lock; 171 172 /* Using monitor modes and buffer at the same time is 173 currently not supported */ 174 bool monitor_on; 175 unsigned int monitor_speed:3; 176 u8 mask_high; 177 u8 mask_low; 178 /* 4x unipolar first then the fours bipolar ones */ 179 s16 thresh_high[8]; 180 s16 thresh_low[8]; 181 struct regulator *vref; 182 u32 vref_uv; 183 int (*send)(const struct i2c_client *client, 184 const char *buf, int count); 185 int (*recv)(const struct i2c_client *client, 186 char *buf, int count); 187 struct { 188 u8 buf[MAX1363_MAX_CHANNELS * 2]; 189 aligned_s64 ts; 190 } data; 191 }; 192 193 #define MAX1363_MODE_SINGLE(_num, _mask) { \ 194 .conf = MAX1363_CHANNEL_SEL(_num) \ 195 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 196 | MAX1363_CONFIG_SE, \ 197 .modemask[0] = _mask, \ 198 } 199 200 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \ 201 .conf = MAX1363_CHANNEL_SEL(_num) \ 202 | MAX1363_CONFIG_SCAN_TO_CS \ 203 | MAX1363_CONFIG_SE, \ 204 .modemask[0] = _mask, \ 205 } 206 207 /* note not available for max1363 hence naming */ 208 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \ 209 .conf = MAX1363_CHANNEL_SEL(_num) \ 210 | MAX1236_SCAN_MID_TO_CHANNEL \ 211 | MAX1363_CONFIG_SE, \ 212 .modemask[0] = _mask \ 213 } 214 215 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \ 216 .conf = MAX1363_CHANNEL_SEL(_nump) \ 217 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 218 | MAX1363_CONFIG_DE, \ 219 .modemask[0] = _mask \ 220 } 221 222 /* Can't think how to automate naming so specify for now */ 223 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \ 224 .conf = MAX1363_CHANNEL_SEL(_num) \ 225 | MAX1363_CONFIG_SCAN_TO_CS \ 226 | MAX1363_CONFIG_DE, \ 227 .modemask[0] = _mask \ 228 } 229 230 /* note only available for max1363 hence naming */ 231 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \ 232 .conf = MAX1363_CHANNEL_SEL(_num) \ 233 | MAX1236_SCAN_MID_TO_CHANNEL \ 234 | MAX1363_CONFIG_SE, \ 235 .modemask[0] = _mask \ 236 } 237 238 static const struct max1363_mode max1363_mode_table[] = { 239 /* All of the single channel options first */ 240 MAX1363_MODE_SINGLE(0, 1 << 0), 241 MAX1363_MODE_SINGLE(1, 1 << 1), 242 MAX1363_MODE_SINGLE(2, 1 << 2), 243 MAX1363_MODE_SINGLE(3, 1 << 3), 244 MAX1363_MODE_SINGLE(4, 1 << 4), 245 MAX1363_MODE_SINGLE(5, 1 << 5), 246 MAX1363_MODE_SINGLE(6, 1 << 6), 247 MAX1363_MODE_SINGLE(7, 1 << 7), 248 MAX1363_MODE_SINGLE(8, 1 << 8), 249 MAX1363_MODE_SINGLE(9, 1 << 9), 250 MAX1363_MODE_SINGLE(10, 1 << 10), 251 MAX1363_MODE_SINGLE(11, 1 << 11), 252 253 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12), 254 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13), 255 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14), 256 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15), 257 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16), 258 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17), 259 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18), 260 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19), 261 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20), 262 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21), 263 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22), 264 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23), 265 266 /* The multichannel scans next */ 267 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003), 268 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007), 269 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C), 270 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F), 271 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F), 272 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F), 273 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F), 274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0), 275 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF), 276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0), 277 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF), 278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0), 279 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF), 280 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0), 281 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF), 282 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0), 283 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF), 284 285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000), 286 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000), 287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000), 288 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000), 289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000), 290 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000), 291 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000), 292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000), 293 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000), 294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000), 295 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000), 296 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000), 297 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000), 298 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000), 299 }; 300 301 static const struct max1363_mode 302 *max1363_match_mode(const unsigned long *mask, 303 const struct max1363_chip_info *ci) 304 { 305 int i; 306 if (mask) 307 for (i = 0; i < ci->num_modes; i++) 308 if (bitmap_subset(mask, 309 max1363_mode_table[ci->mode_list[i]]. 310 modemask, 311 MAX1363_MAX_CHANNELS)) 312 return &max1363_mode_table[ci->mode_list[i]]; 313 return NULL; 314 } 315 316 static int max1363_smbus_send(const struct i2c_client *client, const char *buf, 317 int count) 318 { 319 int i, err; 320 321 for (i = err = 0; err == 0 && i < count; ++i) 322 err = i2c_smbus_write_byte(client, buf[i]); 323 324 return err ? err : count; 325 } 326 327 static int max1363_smbus_recv(const struct i2c_client *client, char *buf, 328 int count) 329 { 330 int i, ret; 331 332 for (i = 0; i < count; ++i) { 333 ret = i2c_smbus_read_byte(client); 334 if (ret < 0) 335 return ret; 336 buf[i] = ret; 337 } 338 339 return count; 340 } 341 342 static int max1363_write_basic_config(struct max1363_state *st) 343 { 344 u8 tx_buf[2] = { st->setupbyte, st->configbyte }; 345 346 return st->send(st->client, tx_buf, 2); 347 } 348 349 static int max1363_set_scan_mode(struct max1363_state *st) 350 { 351 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 352 | MAX1363_SCAN_MASK 353 | MAX1363_SE_DE_MASK); 354 st->configbyte |= st->current_mode->conf; 355 356 return max1363_write_basic_config(st); 357 } 358 359 static int max1363_read_single_chan(struct iio_dev *indio_dev, 360 struct iio_chan_spec const *chan, 361 int *val, 362 long m) 363 { 364 s32 data; 365 u8 rxbuf[2]; 366 struct max1363_state *st = iio_priv(indio_dev); 367 struct i2c_client *client = st->client; 368 369 guard(mutex)(&st->lock); 370 371 /* 372 * If monitor mode is enabled, the method for reading a single 373 * channel will have to be rather different and has not yet 374 * been implemented. 375 * 376 * Also, cannot read directly if buffered capture enabled. 377 */ 378 if (st->monitor_on) 379 return -EBUSY; 380 381 /* Check to see if current scan mode is correct */ 382 if (st->current_mode != &max1363_mode_table[chan->address]) { 383 int ret; 384 385 /* Update scan mode if needed */ 386 st->current_mode = &max1363_mode_table[chan->address]; 387 ret = max1363_set_scan_mode(st); 388 if (ret < 0) 389 return ret; 390 } 391 if (st->chip_info->bits != 8) { 392 /* Get reading */ 393 data = st->recv(client, rxbuf, 2); 394 if (data < 0) 395 return data; 396 397 data = get_unaligned_be16(rxbuf) & 398 ((1 << st->chip_info->bits) - 1); 399 } else { 400 /* Get reading */ 401 data = st->recv(client, rxbuf, 1); 402 if (data < 0) 403 return data; 404 405 data = rxbuf[0]; 406 } 407 408 /* 409 * Differential channels are bipolar and the device returns the sample 410 * in two's complement, so sign-extend it from the resolution bit. 411 */ 412 if (chan->differential) 413 data = sign_extend32(data, st->chip_info->bits - 1); 414 415 *val = data; 416 417 return 0; 418 } 419 420 static int max1363_read_raw(struct iio_dev *indio_dev, 421 struct iio_chan_spec const *chan, 422 int *val, 423 int *val2, 424 long m) 425 { 426 struct max1363_state *st = iio_priv(indio_dev); 427 int ret; 428 429 switch (m) { 430 case IIO_CHAN_INFO_RAW: 431 if (!iio_device_claim_direct(indio_dev)) 432 return -EBUSY; 433 434 ret = max1363_read_single_chan(indio_dev, chan, val, m); 435 iio_device_release_direct(indio_dev); 436 if (ret < 0) 437 return ret; 438 return IIO_VAL_INT; 439 case IIO_CHAN_INFO_SCALE: 440 *val = st->vref_uv / 1000; 441 *val2 = st->chip_info->bits; 442 return IIO_VAL_FRACTIONAL_LOG2; 443 default: 444 return -EINVAL; 445 } 446 return 0; 447 } 448 449 /* Applies to max1363 */ 450 static const enum max1363_modes max1363_mode_list[] = { 451 _s0, _s1, _s2, _s3, 452 s0to1, s0to2, s0to3, 453 d0m1, d2m3, d1m0, d3m2, 454 d0m1to2m3, d1m0to3m2, 455 }; 456 457 static const struct iio_event_spec max1363_events[] = { 458 { 459 .type = IIO_EV_TYPE_THRESH, 460 .dir = IIO_EV_DIR_RISING, 461 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 462 BIT(IIO_EV_INFO_ENABLE), 463 }, { 464 .type = IIO_EV_TYPE_THRESH, 465 .dir = IIO_EV_DIR_FALLING, 466 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 467 BIT(IIO_EV_INFO_ENABLE), 468 }, 469 }; 470 471 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ 472 { \ 473 .type = IIO_VOLTAGE, \ 474 .indexed = 1, \ 475 .channel = num, \ 476 .address = addr, \ 477 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 478 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 479 .datasheet_name = "AIN"#num, \ 480 .scan_type = { \ 481 .sign = 'u', \ 482 .realbits = bits, \ 483 .storagebits = (bits > 8) ? 16 : 8, \ 484 .endianness = IIO_BE, \ 485 }, \ 486 .scan_index = si, \ 487 .event_spec = ev_spec, \ 488 .num_event_specs = num_ev_spec, \ 489 } 490 491 /* bipolar channel */ 492 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ 493 { \ 494 .type = IIO_VOLTAGE, \ 495 .differential = 1, \ 496 .indexed = 1, \ 497 .channel = num, \ 498 .channel2 = num2, \ 499 .address = addr, \ 500 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 501 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 502 .datasheet_name = "AIN"#num"-AIN"#num2, \ 503 .scan_type = { \ 504 .sign = 's', \ 505 .realbits = bits, \ 506 .storagebits = (bits > 8) ? 16 : 8, \ 507 .endianness = IIO_BE, \ 508 }, \ 509 .scan_index = si, \ 510 .event_spec = ev_spec, \ 511 .num_event_specs = num_ev_spec, \ 512 } 513 514 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \ 515 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \ 516 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \ 517 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \ 518 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \ 519 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, ev_spec, num_ev_spec), \ 520 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, ev_spec, num_ev_spec), \ 521 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, ev_spec, num_ev_spec), \ 522 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, ev_spec, num_ev_spec), \ 523 IIO_CHAN_SOFT_TIMESTAMP(8) \ 524 } 525 526 static const struct iio_chan_spec max1036_channels[] = 527 MAX1363_4X_CHANS(8, NULL, 0); 528 static const struct iio_chan_spec max1136_channels[] = 529 MAX1363_4X_CHANS(10, NULL, 0); 530 static const struct iio_chan_spec max1236_channels[] = 531 MAX1363_4X_CHANS(12, NULL, 0); 532 static const struct iio_chan_spec max1361_channels[] = 533 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events)); 534 static const struct iio_chan_spec max1363_channels[] = 535 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events)); 536 537 /* Applies to max1236, max1237 */ 538 static const enum max1363_modes max1236_mode_list[] = { 539 _s0, _s1, _s2, _s3, 540 s0to1, s0to2, s2to3, s0to3, 541 d0m1, d2m3, d1m0, d3m2, 542 d0m1to2m3, d1m0to3m2, 543 }; 544 545 /* Applies to max1238, max1239 */ 546 static const enum max1363_modes max1238_mode_list[] = { 547 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 548 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, 549 s6to7, s6to8, s6to9, s6to10, s6to11, 550 s0to7, s0to8, s0to9, s0to10, s0to11, 551 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 552 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 553 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9, 554 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2, 555 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8, 556 d7m6to11m10, d1m0to11m10, 557 }; 558 559 #define MAX1363_12X_CHANS(bits) { \ 560 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 561 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 562 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 563 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 564 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 565 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 566 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 567 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 568 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \ 569 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \ 570 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \ 571 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \ 572 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \ 573 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \ 574 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \ 575 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \ 576 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \ 577 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \ 578 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \ 579 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \ 580 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \ 581 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \ 582 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \ 583 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \ 584 IIO_CHAN_SOFT_TIMESTAMP(24) \ 585 } 586 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8); 587 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10); 588 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12); 589 590 static const enum max1363_modes max11607_mode_list[] = { 591 _s0, _s1, _s2, _s3, 592 s0to1, s0to2, s2to3, 593 s0to3, 594 d0m1, d2m3, d1m0, d3m2, 595 d0m1to2m3, d1m0to3m2, 596 }; 597 598 static const enum max1363_modes max11608_mode_list[] = { 599 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, 600 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s6to7, s0to7, 601 d0m1, d2m3, d4m5, d6m7, 602 d1m0, d3m2, d5m4, d7m6, 603 d0m1to2m3, d0m1to4m5, d0m1to6m7, 604 d1m0to3m2, d1m0to5m4, d1m0to7m6, 605 }; 606 607 #define MAX1363_8X_CHANS(bits) { \ 608 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 609 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 610 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 611 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 612 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 613 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 614 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 615 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 616 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \ 617 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \ 618 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \ 619 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \ 620 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \ 621 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \ 622 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \ 623 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \ 624 IIO_CHAN_SOFT_TIMESTAMP(16) \ 625 } 626 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8); 627 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10); 628 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12); 629 630 static const enum max1363_modes max11644_mode_list[] = { 631 _s0, _s1, s0to1, d0m1, d1m0, 632 }; 633 634 #define MAX1363_2X_CHANS(bits) { \ 635 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 636 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 637 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \ 638 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \ 639 IIO_CHAN_SOFT_TIMESTAMP(4) \ 640 } 641 642 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 643 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 644 645 enum { 646 max1361, 647 max1362, 648 max1363, 649 max1364, 650 max1036, 651 max1037, 652 max1038, 653 max1039, 654 max1136, 655 max1137, 656 max1138, 657 max1139, 658 max1236, 659 max1237, 660 max1238, 661 max1239, 662 max11600, 663 max11601, 664 max11602, 665 max11603, 666 max11604, 667 max11605, 668 max11606, 669 max11607, 670 max11608, 671 max11609, 672 max11610, 673 max11611, 674 max11612, 675 max11613, 676 max11614, 677 max11615, 678 max11616, 679 max11617, 680 max11644, 681 max11645, 682 max11646, 683 max11647, 684 }; 685 686 static const int max1363_monitor_speeds[] = { 687 133000, 665000, 33300, 16600, 688 8300, 4200, 2000, 1000, 689 }; 690 691 static ssize_t max1363_monitor_show_freq(struct device *dev, 692 struct device_attribute *attr, 693 char *buf) 694 { 695 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev)); 696 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]); 697 } 698 699 static ssize_t max1363_monitor_store_freq(struct device *dev, 700 struct device_attribute *attr, 701 const char *buf, 702 size_t len) 703 { 704 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 705 struct max1363_state *st = iio_priv(indio_dev); 706 int i, ret; 707 unsigned long val; 708 bool found = false; 709 710 ret = kstrtoul(buf, 10, &val); 711 if (ret) 712 return -EINVAL; 713 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++) 714 if (val == max1363_monitor_speeds[i]) { 715 found = true; 716 break; 717 } 718 if (!found) 719 return -EINVAL; 720 721 scoped_guard(mutex, &st->lock) 722 st->monitor_speed = i; 723 724 return 0; 725 } 726 727 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, 728 max1363_monitor_show_freq, 729 max1363_monitor_store_freq); 730 731 static IIO_CONST_ATTR(sampling_frequency_available, 732 "133000 665000 33300 16600 8300 4200 2000 1000"); 733 734 static int max1363_read_thresh(struct iio_dev *indio_dev, 735 const struct iio_chan_spec *chan, enum iio_event_type type, 736 enum iio_event_direction dir, enum iio_event_info info, int *val, 737 int *val2) 738 { 739 struct max1363_state *st = iio_priv(indio_dev); 740 if (dir == IIO_EV_DIR_FALLING) 741 *val = st->thresh_low[chan->channel]; 742 else 743 *val = st->thresh_high[chan->channel]; 744 return IIO_VAL_INT; 745 } 746 747 static int max1363_write_thresh(struct iio_dev *indio_dev, 748 const struct iio_chan_spec *chan, enum iio_event_type type, 749 enum iio_event_direction dir, enum iio_event_info info, int val, 750 int val2) 751 { 752 struct max1363_state *st = iio_priv(indio_dev); 753 /* make it handle signed correctly as well */ 754 switch (st->chip_info->bits) { 755 case 10: 756 if (val > 0x3FF) 757 return -EINVAL; 758 break; 759 case 12: 760 if (val > 0xFFF) 761 return -EINVAL; 762 break; 763 } 764 765 switch (dir) { 766 case IIO_EV_DIR_FALLING: 767 st->thresh_low[chan->channel] = val; 768 break; 769 case IIO_EV_DIR_RISING: 770 st->thresh_high[chan->channel] = val; 771 break; 772 default: 773 return -EINVAL; 774 } 775 776 return 0; 777 } 778 779 static const u64 max1363_event_codes[] = { 780 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 781 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 782 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 783 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 784 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 785 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 786 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 787 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 788 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 789 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 790 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 791 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 792 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 793 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 794 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 795 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 796 }; 797 798 static irqreturn_t max1363_event_handler(int irq, void *private) 799 { 800 struct iio_dev *indio_dev = private; 801 struct max1363_state *st = iio_priv(indio_dev); 802 s64 timestamp = iio_get_time_ns(indio_dev); 803 unsigned long mask, loc; 804 u8 rx; 805 u8 tx[2] = { st->setupbyte, 806 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 }; 807 808 st->recv(st->client, &rx, 1); 809 mask = rx; 810 for_each_set_bit(loc, &mask, 8) 811 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp); 812 st->send(st->client, tx, 2); 813 814 return IRQ_HANDLED; 815 } 816 817 static int max1363_read_event_config(struct iio_dev *indio_dev, 818 const struct iio_chan_spec *chan, enum iio_event_type type, 819 enum iio_event_direction dir) 820 { 821 struct max1363_state *st = iio_priv(indio_dev); 822 int val; 823 int number = chan->channel; 824 825 guard(mutex)(&st->lock); 826 if (dir == IIO_EV_DIR_FALLING) 827 val = (1 << number) & st->mask_low; 828 else 829 val = (1 << number) & st->mask_high; 830 831 return val; 832 } 833 834 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled) 835 { 836 int ret, i = 3, j; 837 unsigned long numelements; 838 int len; 839 const long *modemask; 840 841 if (!enabled) { 842 /* transition to buffered capture is not currently supported */ 843 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP; 844 st->configbyte &= ~MAX1363_SCAN_MASK; 845 st->monitor_on = false; 846 return max1363_write_basic_config(st); 847 } 848 849 /* Ensure we are in the relevant mode */ 850 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP; 851 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 852 | MAX1363_SCAN_MASK 853 | MAX1363_SE_DE_MASK); 854 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE; 855 if ((st->mask_low | st->mask_high) & 0x0F) { 856 st->configbyte |= max1363_mode_table[s0to3].conf; 857 modemask = max1363_mode_table[s0to3].modemask; 858 } else if ((st->mask_low | st->mask_high) & 0x30) { 859 st->configbyte |= max1363_mode_table[d0m1to2m3].conf; 860 modemask = max1363_mode_table[d0m1to2m3].modemask; 861 } else { 862 st->configbyte |= max1363_mode_table[d1m0to3m2].conf; 863 modemask = max1363_mode_table[d1m0to3m2].modemask; 864 } 865 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS); 866 len = 3 * numelements + 3; 867 u8 *tx_buf __free(kfree) = kmalloc(len, GFP_KERNEL); 868 if (!tx_buf) 869 return -ENOMEM; 870 871 tx_buf[0] = st->configbyte; 872 tx_buf[1] = st->setupbyte; 873 tx_buf[2] = (st->monitor_speed << 1); 874 875 /* 876 * So we need to do yet another bit of nefarious scan mode 877 * setup to match what we need. 878 */ 879 for (j = 0; j < 8; j++) 880 if (test_bit(j, modemask)) { 881 /* Establish the mode is in the scan */ 882 if (st->mask_low & (1 << j)) { 883 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF; 884 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0; 885 } else if (j < 4) { 886 tx_buf[i] = 0; 887 tx_buf[i + 1] = 0; 888 } else { 889 tx_buf[i] = 0x80; 890 tx_buf[i + 1] = 0; 891 } 892 if (st->mask_high & (1 << j)) { 893 tx_buf[i + 1] |= 894 (st->thresh_high[j] >> 8) & 0x0F; 895 tx_buf[i + 2] = st->thresh_high[j] & 0xFF; 896 } else if (j < 4) { 897 tx_buf[i + 1] |= 0x0F; 898 tx_buf[i + 2] = 0xFF; 899 } else { 900 tx_buf[i + 1] |= 0x07; 901 tx_buf[i + 2] = 0xFF; 902 } 903 i += 3; 904 } 905 906 907 ret = st->send(st->client, tx_buf, len); 908 if (ret < 0) 909 return ret; 910 if (ret != len) 911 return -EIO; 912 913 /* 914 * Now that we hopefully have sensible thresholds in place it is 915 * time to turn the interrupts on. 916 * It is unclear from the data sheet if this should be necessary 917 * (i.e. whether monitor mode setup is atomic) but it appears to 918 * be in practice. 919 */ 920 tx_buf[0] = st->setupbyte; 921 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0; 922 ret = st->send(st->client, tx_buf, 2); 923 if (ret < 0) 924 return ret; 925 if (ret != 2) 926 return -EIO; 927 928 st->monitor_on = true; 929 930 return 0; 931 } 932 933 /* 934 * To keep this manageable we always use one of 3 scan modes. 935 * Scan 0...3, 0-1,2-3 and 1-0,3-2 936 */ 937 938 static inline int __max1363_check_event_mask(int thismask, int checkmask) 939 { 940 int ret = 0; 941 /* Is it unipolar */ 942 if (thismask < 4) { 943 if (checkmask & ~0x0F) { 944 ret = -EBUSY; 945 goto error_ret; 946 } 947 } else if (thismask < 6) { 948 if (checkmask & ~0x30) { 949 ret = -EBUSY; 950 goto error_ret; 951 } 952 } else if (checkmask & ~0xC0) 953 ret = -EBUSY; 954 error_ret: 955 return ret; 956 } 957 958 static int __max1363_write_event_config(struct max1363_state *st, 959 const struct iio_chan_spec *chan, 960 enum iio_event_direction dir, bool state) 961 { 962 int number = chan->channel; 963 u16 unifiedmask; 964 int ret; 965 966 guard(mutex)(&st->lock); 967 968 unifiedmask = st->mask_low | st->mask_high; 969 if (dir == IIO_EV_DIR_FALLING) { 970 971 if (state == 0) 972 st->mask_low &= ~(1 << number); 973 else { 974 ret = __max1363_check_event_mask((1 << number), 975 unifiedmask); 976 if (ret) 977 return ret; 978 st->mask_low |= (1 << number); 979 } 980 } else { 981 if (state == 0) 982 st->mask_high &= ~(1 << number); 983 else { 984 ret = __max1363_check_event_mask((1 << number), 985 unifiedmask); 986 if (ret) 987 return ret; 988 st->mask_high |= (1 << number); 989 } 990 } 991 992 return 0; 993 994 } 995 static int max1363_write_event_config(struct iio_dev *indio_dev, 996 const struct iio_chan_spec *chan, enum iio_event_type type, 997 enum iio_event_direction dir, bool state) 998 { 999 struct max1363_state *st = iio_priv(indio_dev); 1000 int ret; 1001 1002 if (!iio_device_claim_direct(indio_dev)) 1003 return -EBUSY; 1004 1005 ret = __max1363_write_event_config(st, chan, dir, state); 1006 iio_device_release_direct(indio_dev); 1007 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); 1008 1009 return ret; 1010 } 1011 1012 /* 1013 * As with scan_elements, only certain sets of these can 1014 * be combined. 1015 */ 1016 static struct attribute *max1363_event_attributes[] = { 1017 &iio_dev_attr_sampling_frequency.dev_attr.attr, 1018 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1019 NULL, 1020 }; 1021 1022 static const struct attribute_group max1363_event_attribute_group = { 1023 .attrs = max1363_event_attributes, 1024 }; 1025 1026 static int max1363_update_scan_mode(struct iio_dev *indio_dev, 1027 const unsigned long *scan_mask) 1028 { 1029 struct max1363_state *st = iio_priv(indio_dev); 1030 1031 /* 1032 * Need to figure out the current mode based upon the requested 1033 * scan mask in iio_dev 1034 */ 1035 st->current_mode = max1363_match_mode(scan_mask, st->chip_info); 1036 if (!st->current_mode) 1037 return -EINVAL; 1038 max1363_set_scan_mode(st); 1039 return 0; 1040 } 1041 1042 static const struct iio_info max1238_info = { 1043 .read_raw = &max1363_read_raw, 1044 .update_scan_mode = &max1363_update_scan_mode, 1045 }; 1046 1047 static const struct iio_info max1363_info = { 1048 .read_event_value = &max1363_read_thresh, 1049 .write_event_value = &max1363_write_thresh, 1050 .read_event_config = &max1363_read_event_config, 1051 .write_event_config = &max1363_write_event_config, 1052 .read_raw = &max1363_read_raw, 1053 .update_scan_mode = &max1363_update_scan_mode, 1054 .event_attrs = &max1363_event_attribute_group, 1055 }; 1056 1057 /* max1363 and max1368 tested - rest from data sheet */ 1058 static const struct max1363_chip_info max1363_chip_info_tbl[] = { 1059 [max1361] = { 1060 .bits = 10, 1061 .int_vref_mv = 2048, 1062 .mode_list = max1363_mode_list, 1063 .num_modes = ARRAY_SIZE(max1363_mode_list), 1064 .default_mode = s0to3, 1065 .channels = max1361_channels, 1066 .num_channels = ARRAY_SIZE(max1361_channels), 1067 .info = &max1363_info, 1068 }, 1069 [max1362] = { 1070 .bits = 10, 1071 .int_vref_mv = 4096, 1072 .mode_list = max1363_mode_list, 1073 .num_modes = ARRAY_SIZE(max1363_mode_list), 1074 .default_mode = s0to3, 1075 .channels = max1361_channels, 1076 .num_channels = ARRAY_SIZE(max1361_channels), 1077 .info = &max1363_info, 1078 }, 1079 [max1363] = { 1080 .bits = 12, 1081 .int_vref_mv = 2048, 1082 .mode_list = max1363_mode_list, 1083 .num_modes = ARRAY_SIZE(max1363_mode_list), 1084 .default_mode = s0to3, 1085 .channels = max1363_channels, 1086 .num_channels = ARRAY_SIZE(max1363_channels), 1087 .info = &max1363_info, 1088 }, 1089 [max1364] = { 1090 .bits = 12, 1091 .int_vref_mv = 4096, 1092 .mode_list = max1363_mode_list, 1093 .num_modes = ARRAY_SIZE(max1363_mode_list), 1094 .default_mode = s0to3, 1095 .channels = max1363_channels, 1096 .num_channels = ARRAY_SIZE(max1363_channels), 1097 .info = &max1363_info, 1098 }, 1099 [max1036] = { 1100 .bits = 8, 1101 .int_vref_mv = 4096, 1102 .mode_list = max1236_mode_list, 1103 .num_modes = ARRAY_SIZE(max1236_mode_list), 1104 .default_mode = s0to3, 1105 .info = &max1238_info, 1106 .channels = max1036_channels, 1107 .num_channels = ARRAY_SIZE(max1036_channels), 1108 }, 1109 [max1037] = { 1110 .bits = 8, 1111 .int_vref_mv = 2048, 1112 .mode_list = max1236_mode_list, 1113 .num_modes = ARRAY_SIZE(max1236_mode_list), 1114 .default_mode = s0to3, 1115 .info = &max1238_info, 1116 .channels = max1036_channels, 1117 .num_channels = ARRAY_SIZE(max1036_channels), 1118 }, 1119 [max1038] = { 1120 .bits = 8, 1121 .int_vref_mv = 4096, 1122 .mode_list = max1238_mode_list, 1123 .num_modes = ARRAY_SIZE(max1238_mode_list), 1124 .default_mode = s0to11, 1125 .info = &max1238_info, 1126 .channels = max1038_channels, 1127 .num_channels = ARRAY_SIZE(max1038_channels), 1128 }, 1129 [max1039] = { 1130 .bits = 8, 1131 .int_vref_mv = 2048, 1132 .mode_list = max1238_mode_list, 1133 .num_modes = ARRAY_SIZE(max1238_mode_list), 1134 .default_mode = s0to11, 1135 .info = &max1238_info, 1136 .channels = max1038_channels, 1137 .num_channels = ARRAY_SIZE(max1038_channels), 1138 }, 1139 [max1136] = { 1140 .bits = 10, 1141 .int_vref_mv = 4096, 1142 .mode_list = max1236_mode_list, 1143 .num_modes = ARRAY_SIZE(max1236_mode_list), 1144 .default_mode = s0to3, 1145 .info = &max1238_info, 1146 .channels = max1136_channels, 1147 .num_channels = ARRAY_SIZE(max1136_channels), 1148 }, 1149 [max1137] = { 1150 .bits = 10, 1151 .int_vref_mv = 2048, 1152 .mode_list = max1236_mode_list, 1153 .num_modes = ARRAY_SIZE(max1236_mode_list), 1154 .default_mode = s0to3, 1155 .info = &max1238_info, 1156 .channels = max1136_channels, 1157 .num_channels = ARRAY_SIZE(max1136_channels), 1158 }, 1159 [max1138] = { 1160 .bits = 10, 1161 .int_vref_mv = 4096, 1162 .mode_list = max1238_mode_list, 1163 .num_modes = ARRAY_SIZE(max1238_mode_list), 1164 .default_mode = s0to11, 1165 .info = &max1238_info, 1166 .channels = max1138_channels, 1167 .num_channels = ARRAY_SIZE(max1138_channels), 1168 }, 1169 [max1139] = { 1170 .bits = 10, 1171 .int_vref_mv = 2048, 1172 .mode_list = max1238_mode_list, 1173 .num_modes = ARRAY_SIZE(max1238_mode_list), 1174 .default_mode = s0to11, 1175 .info = &max1238_info, 1176 .channels = max1138_channels, 1177 .num_channels = ARRAY_SIZE(max1138_channels), 1178 }, 1179 [max1236] = { 1180 .bits = 12, 1181 .int_vref_mv = 4096, 1182 .mode_list = max1236_mode_list, 1183 .num_modes = ARRAY_SIZE(max1236_mode_list), 1184 .default_mode = s0to3, 1185 .info = &max1238_info, 1186 .channels = max1236_channels, 1187 .num_channels = ARRAY_SIZE(max1236_channels), 1188 }, 1189 [max1237] = { 1190 .bits = 12, 1191 .int_vref_mv = 2048, 1192 .mode_list = max1236_mode_list, 1193 .num_modes = ARRAY_SIZE(max1236_mode_list), 1194 .default_mode = s0to3, 1195 .info = &max1238_info, 1196 .channels = max1236_channels, 1197 .num_channels = ARRAY_SIZE(max1236_channels), 1198 }, 1199 [max1238] = { 1200 .bits = 12, 1201 .int_vref_mv = 4096, 1202 .mode_list = max1238_mode_list, 1203 .num_modes = ARRAY_SIZE(max1238_mode_list), 1204 .default_mode = s0to11, 1205 .info = &max1238_info, 1206 .channels = max1238_channels, 1207 .num_channels = ARRAY_SIZE(max1238_channels), 1208 }, 1209 [max1239] = { 1210 .bits = 12, 1211 .int_vref_mv = 2048, 1212 .mode_list = max1238_mode_list, 1213 .num_modes = ARRAY_SIZE(max1238_mode_list), 1214 .default_mode = s0to11, 1215 .info = &max1238_info, 1216 .channels = max1238_channels, 1217 .num_channels = ARRAY_SIZE(max1238_channels), 1218 }, 1219 [max11600] = { 1220 .bits = 8, 1221 .int_vref_mv = 4096, 1222 .mode_list = max11607_mode_list, 1223 .num_modes = ARRAY_SIZE(max11607_mode_list), 1224 .default_mode = s0to3, 1225 .info = &max1238_info, 1226 .channels = max1036_channels, 1227 .num_channels = ARRAY_SIZE(max1036_channels), 1228 }, 1229 [max11601] = { 1230 .bits = 8, 1231 .int_vref_mv = 2048, 1232 .mode_list = max11607_mode_list, 1233 .num_modes = ARRAY_SIZE(max11607_mode_list), 1234 .default_mode = s0to3, 1235 .info = &max1238_info, 1236 .channels = max1036_channels, 1237 .num_channels = ARRAY_SIZE(max1036_channels), 1238 }, 1239 [max11602] = { 1240 .bits = 8, 1241 .int_vref_mv = 4096, 1242 .mode_list = max11608_mode_list, 1243 .num_modes = ARRAY_SIZE(max11608_mode_list), 1244 .default_mode = s0to7, 1245 .info = &max1238_info, 1246 .channels = max11602_channels, 1247 .num_channels = ARRAY_SIZE(max11602_channels), 1248 }, 1249 [max11603] = { 1250 .bits = 8, 1251 .int_vref_mv = 2048, 1252 .mode_list = max11608_mode_list, 1253 .num_modes = ARRAY_SIZE(max11608_mode_list), 1254 .default_mode = s0to7, 1255 .info = &max1238_info, 1256 .channels = max11602_channels, 1257 .num_channels = ARRAY_SIZE(max11602_channels), 1258 }, 1259 [max11604] = { 1260 .bits = 8, 1261 .int_vref_mv = 4096, 1262 .mode_list = max1238_mode_list, 1263 .num_modes = ARRAY_SIZE(max1238_mode_list), 1264 .default_mode = s0to11, 1265 .info = &max1238_info, 1266 .channels = max1038_channels, 1267 .num_channels = ARRAY_SIZE(max1038_channels), 1268 }, 1269 [max11605] = { 1270 .bits = 8, 1271 .int_vref_mv = 2048, 1272 .mode_list = max1238_mode_list, 1273 .num_modes = ARRAY_SIZE(max1238_mode_list), 1274 .default_mode = s0to11, 1275 .info = &max1238_info, 1276 .channels = max1038_channels, 1277 .num_channels = ARRAY_SIZE(max1038_channels), 1278 }, 1279 [max11606] = { 1280 .bits = 10, 1281 .int_vref_mv = 4096, 1282 .mode_list = max11607_mode_list, 1283 .num_modes = ARRAY_SIZE(max11607_mode_list), 1284 .default_mode = s0to3, 1285 .info = &max1238_info, 1286 .channels = max1136_channels, 1287 .num_channels = ARRAY_SIZE(max1136_channels), 1288 }, 1289 [max11607] = { 1290 .bits = 10, 1291 .int_vref_mv = 2048, 1292 .mode_list = max11607_mode_list, 1293 .num_modes = ARRAY_SIZE(max11607_mode_list), 1294 .default_mode = s0to3, 1295 .info = &max1238_info, 1296 .channels = max1136_channels, 1297 .num_channels = ARRAY_SIZE(max1136_channels), 1298 }, 1299 [max11608] = { 1300 .bits = 10, 1301 .int_vref_mv = 4096, 1302 .mode_list = max11608_mode_list, 1303 .num_modes = ARRAY_SIZE(max11608_mode_list), 1304 .default_mode = s0to7, 1305 .info = &max1238_info, 1306 .channels = max11608_channels, 1307 .num_channels = ARRAY_SIZE(max11608_channels), 1308 }, 1309 [max11609] = { 1310 .bits = 10, 1311 .int_vref_mv = 2048, 1312 .mode_list = max11608_mode_list, 1313 .num_modes = ARRAY_SIZE(max11608_mode_list), 1314 .default_mode = s0to7, 1315 .info = &max1238_info, 1316 .channels = max11608_channels, 1317 .num_channels = ARRAY_SIZE(max11608_channels), 1318 }, 1319 [max11610] = { 1320 .bits = 10, 1321 .int_vref_mv = 4096, 1322 .mode_list = max1238_mode_list, 1323 .num_modes = ARRAY_SIZE(max1238_mode_list), 1324 .default_mode = s0to11, 1325 .info = &max1238_info, 1326 .channels = max1138_channels, 1327 .num_channels = ARRAY_SIZE(max1138_channels), 1328 }, 1329 [max11611] = { 1330 .bits = 10, 1331 .int_vref_mv = 2048, 1332 .mode_list = max1238_mode_list, 1333 .num_modes = ARRAY_SIZE(max1238_mode_list), 1334 .default_mode = s0to11, 1335 .info = &max1238_info, 1336 .channels = max1138_channels, 1337 .num_channels = ARRAY_SIZE(max1138_channels), 1338 }, 1339 [max11612] = { 1340 .bits = 12, 1341 .int_vref_mv = 4096, 1342 .mode_list = max11607_mode_list, 1343 .num_modes = ARRAY_SIZE(max11607_mode_list), 1344 .default_mode = s0to3, 1345 .info = &max1238_info, 1346 .channels = max1363_channels, 1347 .num_channels = ARRAY_SIZE(max1363_channels), 1348 }, 1349 [max11613] = { 1350 .bits = 12, 1351 .int_vref_mv = 2048, 1352 .mode_list = max11607_mode_list, 1353 .num_modes = ARRAY_SIZE(max11607_mode_list), 1354 .default_mode = s0to3, 1355 .info = &max1238_info, 1356 .channels = max1363_channels, 1357 .num_channels = ARRAY_SIZE(max1363_channels), 1358 }, 1359 [max11614] = { 1360 .bits = 12, 1361 .int_vref_mv = 4096, 1362 .mode_list = max11608_mode_list, 1363 .num_modes = ARRAY_SIZE(max11608_mode_list), 1364 .default_mode = s0to7, 1365 .info = &max1238_info, 1366 .channels = max11614_channels, 1367 .num_channels = ARRAY_SIZE(max11614_channels), 1368 }, 1369 [max11615] = { 1370 .bits = 12, 1371 .int_vref_mv = 2048, 1372 .mode_list = max11608_mode_list, 1373 .num_modes = ARRAY_SIZE(max11608_mode_list), 1374 .default_mode = s0to7, 1375 .info = &max1238_info, 1376 .channels = max11614_channels, 1377 .num_channels = ARRAY_SIZE(max11614_channels), 1378 }, 1379 [max11616] = { 1380 .bits = 12, 1381 .int_vref_mv = 4096, 1382 .mode_list = max1238_mode_list, 1383 .num_modes = ARRAY_SIZE(max1238_mode_list), 1384 .default_mode = s0to11, 1385 .info = &max1238_info, 1386 .channels = max1238_channels, 1387 .num_channels = ARRAY_SIZE(max1238_channels), 1388 }, 1389 [max11617] = { 1390 .bits = 12, 1391 .int_vref_mv = 2048, 1392 .mode_list = max1238_mode_list, 1393 .num_modes = ARRAY_SIZE(max1238_mode_list), 1394 .default_mode = s0to11, 1395 .info = &max1238_info, 1396 .channels = max1238_channels, 1397 .num_channels = ARRAY_SIZE(max1238_channels), 1398 }, 1399 [max11644] = { 1400 .bits = 12, 1401 .int_vref_mv = 4096, 1402 .mode_list = max11644_mode_list, 1403 .num_modes = ARRAY_SIZE(max11644_mode_list), 1404 .default_mode = s0to1, 1405 .info = &max1238_info, 1406 .channels = max11644_channels, 1407 .num_channels = ARRAY_SIZE(max11644_channels), 1408 }, 1409 [max11645] = { 1410 .bits = 12, 1411 .int_vref_mv = 2048, 1412 .mode_list = max11644_mode_list, 1413 .num_modes = ARRAY_SIZE(max11644_mode_list), 1414 .default_mode = s0to1, 1415 .info = &max1238_info, 1416 .channels = max11644_channels, 1417 .num_channels = ARRAY_SIZE(max11644_channels), 1418 }, 1419 [max11646] = { 1420 .bits = 10, 1421 .int_vref_mv = 4096, 1422 .mode_list = max11644_mode_list, 1423 .num_modes = ARRAY_SIZE(max11644_mode_list), 1424 .default_mode = s0to1, 1425 .info = &max1238_info, 1426 .channels = max11646_channels, 1427 .num_channels = ARRAY_SIZE(max11646_channels), 1428 }, 1429 [max11647] = { 1430 .bits = 10, 1431 .int_vref_mv = 2048, 1432 .mode_list = max11644_mode_list, 1433 .num_modes = ARRAY_SIZE(max11644_mode_list), 1434 .default_mode = s0to1, 1435 .info = &max1238_info, 1436 .channels = max11646_channels, 1437 .num_channels = ARRAY_SIZE(max11646_channels), 1438 }, 1439 }; 1440 1441 static int max1363_initial_setup(struct max1363_state *st) 1442 { 1443 st->setupbyte = MAX1363_SETUP_INT_CLOCK 1444 | MAX1363_SETUP_UNIPOLAR 1445 | MAX1363_SETUP_NORESET; 1446 1447 if (st->vref) 1448 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF; 1449 else 1450 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF 1451 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT; 1452 1453 /* Set scan mode writes the config anyway so wait until then */ 1454 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte); 1455 st->current_mode = &max1363_mode_table[st->chip_info->default_mode]; 1456 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte); 1457 1458 return max1363_set_scan_mode(st); 1459 } 1460 1461 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev) 1462 { 1463 struct max1363_state *st = iio_priv(indio_dev); 1464 unsigned long *masks; 1465 int i; 1466 1467 masks = devm_kzalloc(&indio_dev->dev, 1468 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS), 1469 sizeof(long), 1470 st->chip_info->num_modes + 1), 1471 GFP_KERNEL); 1472 if (!masks) 1473 return -ENOMEM; 1474 1475 for (i = 0; i < st->chip_info->num_modes; i++) 1476 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i, 1477 max1363_mode_table[st->chip_info->mode_list[i]] 1478 .modemask, MAX1363_MAX_CHANNELS); 1479 1480 indio_dev->available_scan_masks = masks; 1481 1482 return 0; 1483 } 1484 1485 static irqreturn_t max1363_trigger_handler(int irq, void *p) 1486 { 1487 struct iio_poll_func *pf = p; 1488 struct iio_dev *indio_dev = pf->indio_dev; 1489 struct max1363_state *st = iio_priv(indio_dev); 1490 int b_sent; 1491 unsigned long numvals = bitmap_weight(st->current_mode->modemask, 1492 MAX1363_MAX_CHANNELS); 1493 1494 /* Monitor mode prevents reading. Whilst not currently implemented 1495 * might as well have this test in here in the meantime as it does 1496 * no harm. 1497 */ 1498 if (numvals == 0) 1499 goto done; 1500 1501 if (st->chip_info->bits != 8) 1502 b_sent = st->recv(st->client, st->data.buf, numvals * 2); 1503 else 1504 b_sent = st->recv(st->client, st->data.buf, numvals); 1505 if (b_sent < 0) 1506 goto done; 1507 1508 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data), 1509 iio_get_time_ns(indio_dev)); 1510 1511 done: 1512 iio_trigger_notify_done(indio_dev->trig); 1513 1514 return IRQ_HANDLED; 1515 } 1516 1517 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \ 1518 .compatible = of_compatible, \ 1519 .data = &max1363_chip_info_tbl[cfg], \ 1520 } 1521 1522 static const struct of_device_id max1363_of_match[] = { 1523 MAX1363_COMPATIBLE("maxim,max1361", max1361), 1524 MAX1363_COMPATIBLE("maxim,max1362", max1362), 1525 MAX1363_COMPATIBLE("maxim,max1363", max1363), 1526 MAX1363_COMPATIBLE("maxim,max1364", max1364), 1527 MAX1363_COMPATIBLE("maxim,max1036", max1036), 1528 MAX1363_COMPATIBLE("maxim,max1037", max1037), 1529 MAX1363_COMPATIBLE("maxim,max1038", max1038), 1530 MAX1363_COMPATIBLE("maxim,max1039", max1039), 1531 MAX1363_COMPATIBLE("maxim,max1136", max1136), 1532 MAX1363_COMPATIBLE("maxim,max1137", max1137), 1533 MAX1363_COMPATIBLE("maxim,max1138", max1138), 1534 MAX1363_COMPATIBLE("maxim,max1139", max1139), 1535 MAX1363_COMPATIBLE("maxim,max1236", max1236), 1536 MAX1363_COMPATIBLE("maxim,max1237", max1237), 1537 MAX1363_COMPATIBLE("maxim,max1238", max1238), 1538 MAX1363_COMPATIBLE("maxim,max1239", max1239), 1539 MAX1363_COMPATIBLE("maxim,max11600", max11600), 1540 MAX1363_COMPATIBLE("maxim,max11601", max11601), 1541 MAX1363_COMPATIBLE("maxim,max11602", max11602), 1542 MAX1363_COMPATIBLE("maxim,max11603", max11603), 1543 MAX1363_COMPATIBLE("maxim,max11604", max11604), 1544 MAX1363_COMPATIBLE("maxim,max11605", max11605), 1545 MAX1363_COMPATIBLE("maxim,max11606", max11606), 1546 MAX1363_COMPATIBLE("maxim,max11607", max11607), 1547 MAX1363_COMPATIBLE("maxim,max11608", max11608), 1548 MAX1363_COMPATIBLE("maxim,max11609", max11609), 1549 MAX1363_COMPATIBLE("maxim,max11610", max11610), 1550 MAX1363_COMPATIBLE("maxim,max11611", max11611), 1551 MAX1363_COMPATIBLE("maxim,max11612", max11612), 1552 MAX1363_COMPATIBLE("maxim,max11613", max11613), 1553 MAX1363_COMPATIBLE("maxim,max11614", max11614), 1554 MAX1363_COMPATIBLE("maxim,max11615", max11615), 1555 MAX1363_COMPATIBLE("maxim,max11616", max11616), 1556 MAX1363_COMPATIBLE("maxim,max11617", max11617), 1557 MAX1363_COMPATIBLE("maxim,max11644", max11644), 1558 MAX1363_COMPATIBLE("maxim,max11645", max11645), 1559 MAX1363_COMPATIBLE("maxim,max11646", max11646), 1560 MAX1363_COMPATIBLE("maxim,max11647", max11647), 1561 { } 1562 }; 1563 MODULE_DEVICE_TABLE(of, max1363_of_match); 1564 1565 static int max1363_probe(struct i2c_client *client) 1566 { 1567 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1568 int ret; 1569 struct max1363_state *st; 1570 struct iio_dev *indio_dev; 1571 1572 indio_dev = devm_iio_device_alloc(&client->dev, 1573 sizeof(struct max1363_state)); 1574 if (!indio_dev) 1575 return -ENOMEM; 1576 1577 st = iio_priv(indio_dev); 1578 1579 mutex_init(&st->lock); 1580 ret = devm_regulator_get_enable(&client->dev, "vcc"); 1581 if (ret) 1582 return ret; 1583 1584 st->chip_info = i2c_get_match_data(client); 1585 st->client = client; 1586 1587 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref"); 1588 if (ret < 0 && ret != -ENODEV) 1589 return ret; 1590 1591 1592 st->vref_uv = ret == -ENODEV ? st->chip_info->int_vref_mv * 1000 : ret; 1593 1594 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1595 st->send = i2c_master_send; 1596 st->recv = i2c_master_recv; 1597 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE) 1598 && st->chip_info->bits == 8) { 1599 st->send = max1363_smbus_send; 1600 st->recv = max1363_smbus_recv; 1601 } else { 1602 return -EOPNOTSUPP; 1603 } 1604 1605 ret = max1363_alloc_scan_masks(indio_dev); 1606 if (ret) 1607 return ret; 1608 1609 indio_dev->name = id->name; 1610 indio_dev->channels = st->chip_info->channels; 1611 indio_dev->num_channels = st->chip_info->num_channels; 1612 indio_dev->info = st->chip_info->info; 1613 indio_dev->modes = INDIO_DIRECT_MODE; 1614 ret = max1363_initial_setup(st); 1615 if (ret < 0) 1616 return ret; 1617 1618 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 1619 &max1363_trigger_handler, NULL); 1620 if (ret) 1621 return ret; 1622 1623 if (client->irq) { 1624 ret = devm_request_threaded_irq(&client->dev, st->client->irq, 1625 NULL, 1626 &max1363_event_handler, 1627 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1628 "max1363_event", 1629 indio_dev); 1630 1631 if (ret) 1632 return ret; 1633 } 1634 1635 return devm_iio_device_register(&client->dev, indio_dev); 1636 } 1637 1638 #define MAX1363_ID_TABLE(_name, cfg) { \ 1639 .name = _name, \ 1640 .driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg], \ 1641 } 1642 1643 static const struct i2c_device_id max1363_id[] = { 1644 MAX1363_ID_TABLE("max1361", max1361), 1645 MAX1363_ID_TABLE("max1362", max1362), 1646 MAX1363_ID_TABLE("max1363", max1363), 1647 MAX1363_ID_TABLE("max1364", max1364), 1648 MAX1363_ID_TABLE("max1036", max1036), 1649 MAX1363_ID_TABLE("max1037", max1037), 1650 MAX1363_ID_TABLE("max1038", max1038), 1651 MAX1363_ID_TABLE("max1039", max1039), 1652 MAX1363_ID_TABLE("max1136", max1136), 1653 MAX1363_ID_TABLE("max1137", max1137), 1654 MAX1363_ID_TABLE("max1138", max1138), 1655 MAX1363_ID_TABLE("max1139", max1139), 1656 MAX1363_ID_TABLE("max1236", max1236), 1657 MAX1363_ID_TABLE("max1237", max1237), 1658 MAX1363_ID_TABLE("max1238", max1238), 1659 MAX1363_ID_TABLE("max1239", max1239), 1660 MAX1363_ID_TABLE("max11600", max11600), 1661 MAX1363_ID_TABLE("max11601", max11601), 1662 MAX1363_ID_TABLE("max11602", max11602), 1663 MAX1363_ID_TABLE("max11603", max11603), 1664 MAX1363_ID_TABLE("max11604", max11604), 1665 MAX1363_ID_TABLE("max11605", max11605), 1666 MAX1363_ID_TABLE("max11606", max11606), 1667 MAX1363_ID_TABLE("max11607", max11607), 1668 MAX1363_ID_TABLE("max11608", max11608), 1669 MAX1363_ID_TABLE("max11609", max11609), 1670 MAX1363_ID_TABLE("max11610", max11610), 1671 MAX1363_ID_TABLE("max11611", max11611), 1672 MAX1363_ID_TABLE("max11612", max11612), 1673 MAX1363_ID_TABLE("max11613", max11613), 1674 MAX1363_ID_TABLE("max11614", max11614), 1675 MAX1363_ID_TABLE("max11615", max11615), 1676 MAX1363_ID_TABLE("max11616", max11616), 1677 MAX1363_ID_TABLE("max11617", max11617), 1678 MAX1363_ID_TABLE("max11644", max11644), 1679 MAX1363_ID_TABLE("max11645", max11645), 1680 MAX1363_ID_TABLE("max11646", max11646), 1681 MAX1363_ID_TABLE("max11647", max11647), 1682 { } 1683 }; 1684 1685 MODULE_DEVICE_TABLE(i2c, max1363_id); 1686 1687 static struct i2c_driver max1363_driver = { 1688 .driver = { 1689 .name = "max1363", 1690 .of_match_table = max1363_of_match, 1691 }, 1692 .probe = max1363_probe, 1693 .id_table = max1363_id, 1694 }; 1695 module_i2c_driver(max1363_driver); 1696 1697 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>"); 1698 MODULE_DESCRIPTION("Maxim 1363 ADC"); 1699 MODULE_LICENSE("GPL v2"); 1700