1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/i2c/busses/i2c-tegra.c
4 *
5 * Copyright (C) 2010 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/irq.h>
22 #include <linux/kernel.h>
23 #include <linux/ktime.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/reset.h>
30
31 #define BYTES_PER_FIFO_WORD 4
32
33 #define I2C_CNFG 0x000
34 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
35 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
36 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
37 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
38 #define I2C_STATUS 0x01c
39 #define I2C_SL_CNFG 0x020
40 #define I2C_SL_CNFG_NACK BIT(1)
41 #define I2C_SL_CNFG_NEWSL BIT(2)
42 #define I2C_SL_ADDR1 0x02c
43 #define I2C_SL_ADDR2 0x030
44 #define I2C_TLOW_SEXT 0x034
45 #define I2C_TX_FIFO 0x050
46 #define I2C_RX_FIFO 0x054
47 #define I2C_PACKET_TRANSFER_STATUS 0x058
48 #define I2C_FIFO_CONTROL 0x05c
49 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
50 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
53 #define I2C_FIFO_STATUS 0x060
54 #define I2C_FIFO_STATUS_TX GENMASK(7, 4)
55 #define I2C_FIFO_STATUS_RX GENMASK(3, 0)
56 #define I2C_INT_MASK 0x064
57 #define I2C_INT_STATUS 0x068
58 #define I2C_INT_BUS_CLR_DONE BIT(11)
59 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
60 #define I2C_INT_NO_ACK BIT(3)
61 #define I2C_INT_ARBITRATION_LOST BIT(2)
62 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
63 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
64 #define I2C_CLK_DIVISOR 0x06c
65 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
66 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
67
68 #define DVC_CTRL_REG1 0x000
69 #define DVC_CTRL_REG1_INTR_EN BIT(10)
70 #define DVC_CTRL_REG3 0x008
71 #define DVC_CTRL_REG3_SW_PROG BIT(26)
72 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
73 #define DVC_STATUS 0x00c
74 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
75
76 #define I2C_ERR_NONE 0x00
77 #define I2C_ERR_NO_ACK BIT(0)
78 #define I2C_ERR_ARBITRATION_LOST BIT(1)
79 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
80 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
81
82 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
83 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
84 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
86 #define PACKET_HEADER0_PROTOCOL_I2C 1
87
88 #define I2C_HEADER_HS_MODE BIT(22)
89 #define I2C_HEADER_CONT_ON_NAK BIT(21)
90 #define I2C_HEADER_READ BIT(19)
91 #define I2C_HEADER_10BIT_ADDR BIT(18)
92 #define I2C_HEADER_IE_ENABLE BIT(17)
93 #define I2C_HEADER_REPEAT_START BIT(16)
94 #define I2C_HEADER_CONTINUE_XFER BIT(15)
95 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
96
97 #define I2C_BUS_CLEAR_CNFG 0x084
98 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
99 #define I2C_BC_STOP_COND BIT(2)
100 #define I2C_BC_TERMINATE BIT(1)
101 #define I2C_BC_ENABLE BIT(0)
102 #define I2C_BUS_CLEAR_STATUS 0x088
103 #define I2C_BC_STATUS BIT(0)
104
105 #define I2C_CONFIG_LOAD 0x08c
106 #define I2C_MSTR_CONFIG_LOAD BIT(0)
107
108 #define I2C_CLKEN_OVERRIDE 0x090
109 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
110
111 #define I2C_INTERFACE_TIMING_0 0x094
112 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
113 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
114 #define I2C_INTERFACE_TIMING_1 0x098
115 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
116 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
117 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
118 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
119
120 #define I2C_HS_INTERFACE_TIMING_0 0x09c
121 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
122 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
123 #define I2C_HS_INTERFACE_TIMING_1 0x0a0
124 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
125 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
126 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
127
128 #define I2C_MST_FIFO_CONTROL 0x0b4
129 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
130 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
131 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
132 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
133
134 #define I2C_MST_FIFO_STATUS 0x0b8
135 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
136 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
137
138 #define I2C_MASTER_RESET_CNTRL 0x0a8
139
140 #define I2C_SW_MUTEX 0x0ec
141 #define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)
142 #define I2C_SW_MUTEX_GRANT GENMASK(7, 4)
143 #define I2C_SW_MUTEX_ID_CCPLEX 9
144
145 /* SW mutex acquire timeout value in microseconds. */
146 #define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC)
147
148 /* configuration load timeout in microseconds */
149 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
150
151 /* packet header size in bytes */
152 #define I2C_PACKET_HEADER_SIZE 12
153
154 /*
155 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
156 * avoid DMA overhead, otherwise external APB DMA controller will be used.
157 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
158 * I2C_PACKET_HEADER_SIZE.
159 */
160 #define I2C_PIO_MODE_PREFERRED_LEN 32
161
162 /*
163 * msg_end_type: The bus control which needs to be sent at end of transfer.
164 * @MSG_END_STOP: Send stop pulse.
165 * @MSG_END_REPEAT_START: Send repeat-start.
166 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
167 */
168 enum msg_end_type {
169 MSG_END_STOP,
170 MSG_END_REPEAT_START,
171 MSG_END_CONTINUE,
172 };
173
174 /**
175 * struct tegra_i2c_hw_feature : per hardware generation features
176 * @has_continue_xfer_support: continue-transfer supported
177 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
178 * completion interrupt on per packet basis.
179 * @has_config_load_reg: Has the config load register to load the new
180 * configuration.
181 * @clk_divisor_hs_mode: Clock divisor in HS mode.
182 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
183 * applicable if there is no fast clock source i.e. single clock
184 * source.
185 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
186 * applicable if there is no fast clock source i.e. single clock
187 * source.
188 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
189 * applicable if there is no fast clock source (i.e. single
190 * clock source).
191 * @has_multi_master_mode: The I2C controller supports running in single-master
192 * or multi-master mode.
193 * @has_slcg_override_reg: The I2C controller supports a register that
194 * overrides the second level clock gating.
195 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
196 * provides additional features and allows for longer messages to
197 * be transferred in one go.
198 * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which
199 * provides an alternative to controller reset when configured as
200 * I2C master
201 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
202 * allowing 0 length transfers.
203 * @supports_bus_clear: Bus Clear support to recover from bus hang during
204 * SDA stuck low from device for some unknown reasons.
205 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
206 * @tlow_std_mode: Low period of the clock in standard mode.
207 * @thigh_std_mode: High period of the clock in standard mode.
208 * @tlow_fast_mode: Low period of the clock in fast mode.
209 * @thigh_fast_mode: High period of the clock in fast mode.
210 * @tlow_fastplus_mode: Low period of the clock in fast-plus mode.
211 * @thigh_fastplus_mode: High period of the clock in fast-plus mode.
212 * @tlow_hs_mode: Low period of the clock in HS mode.
213 * @thigh_hs_mode: High period of the clock in HS mode.
214 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
215 * in standard mode.
216 * @setup_hold_time_fast_mode: Setup and hold time for start and stop
217 * conditions in fast mode.
218 * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop
219 * conditions in fast-plus mode.
220 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
221 * in HS mode.
222 * @has_interface_timing_reg: Has interface timing register to program the tuned
223 * timing settings.
224 * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
225 * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
226 */
227 struct tegra_i2c_hw_feature {
228 bool has_continue_xfer_support;
229 bool has_per_pkt_xfer_complete_irq;
230 bool has_config_load_reg;
231 u32 clk_divisor_hs_mode;
232 u32 clk_divisor_std_mode;
233 u32 clk_divisor_fast_mode;
234 u32 clk_divisor_fast_plus_mode;
235 bool has_multi_master_mode;
236 bool has_slcg_override_reg;
237 bool has_mst_fifo;
238 bool has_mst_reset;
239 const struct i2c_adapter_quirks *quirks;
240 bool supports_bus_clear;
241 bool has_apb_dma;
242 u32 tlow_std_mode;
243 u32 thigh_std_mode;
244 u32 tlow_fast_mode;
245 u32 thigh_fast_mode;
246 u32 tlow_fastplus_mode;
247 u32 thigh_fastplus_mode;
248 u32 tlow_hs_mode;
249 u32 thigh_hs_mode;
250 u32 setup_hold_time_std_mode;
251 u32 setup_hold_time_fast_mode;
252 u32 setup_hold_time_fastplus_mode;
253 u32 setup_hold_time_hs_mode;
254 bool has_interface_timing_reg;
255 bool enable_hs_mode_support;
256 bool has_mutex;
257 };
258
259 /**
260 * struct tegra_i2c_dev - per device I2C context
261 * @dev: device reference for power management
262 * @hw: Tegra I2C HW feature
263 * @adapter: core I2C layer adapter information
264 * @div_clk: clock reference for div clock of I2C controller
265 * @clocks: array of I2C controller clocks
266 * @nclocks: number of clocks in the array
267 * @base: ioremapped registers cookie
268 * @base_phys: physical base address of the I2C controller
269 * @cont_id: I2C controller ID, used for packet header
270 * @irq: IRQ number of transfer complete interrupt
271 * @is_dvc: identifies the DVC I2C controller, has a different register layout
272 * @is_vi: identifies the VI I2C controller, has a different register layout
273 * @msg_complete: transfer completion notifier
274 * @msg_buf_remaining: size of unsent data in the message buffer
275 * @msg_len: length of message in current transfer
276 * @msg_err: error code for completed message
277 * @msg_buf: pointer to current message data
278 * @msg_read: indicates that the transfer is a read access
279 * @timings: i2c timings information like bus frequency
280 * @multimaster_mode: indicates that I2C controller is in multi-master mode
281 * @dma_chan: DMA channel
282 * @dma_phys: handle to DMA resources
283 * @dma_buf: pointer to allocated DMA buffer
284 * @dma_buf_size: DMA buffer size
285 * @dma_dev: DMA device used for transfers
286 * @dma_mode: indicates active DMA transfer
287 * @dma_complete: DMA completion notifier
288 * @atomic_mode: indicates active atomic transfer
289 */
290 struct tegra_i2c_dev {
291 struct device *dev;
292 struct i2c_adapter adapter;
293
294 const struct tegra_i2c_hw_feature *hw;
295 unsigned int cont_id;
296 unsigned int irq;
297
298 phys_addr_t base_phys;
299 void __iomem *base;
300
301 struct clk_bulk_data clocks[2];
302 unsigned int nclocks;
303
304 struct clk *div_clk;
305 struct i2c_timings timings;
306
307 struct completion msg_complete;
308 size_t msg_buf_remaining;
309 unsigned int msg_len;
310 int msg_err;
311 u8 *msg_buf;
312
313 struct completion dma_complete;
314 struct dma_chan *dma_chan;
315 unsigned int dma_buf_size;
316 struct device *dma_dev;
317 dma_addr_t dma_phys;
318 void *dma_buf;
319
320 bool multimaster_mode;
321 bool atomic_mode;
322 bool dma_mode;
323 bool msg_read;
324 bool is_dvc;
325 bool is_vi;
326 };
327
328 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc)
329 #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi)
330
dvc_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned int reg)331 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
332 unsigned int reg)
333 {
334 writel_relaxed(val, i2c_dev->base + reg);
335 }
336
dvc_readl(struct tegra_i2c_dev * i2c_dev,unsigned int reg)337 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
338 {
339 return readl_relaxed(i2c_dev->base + reg);
340 }
341
342 /*
343 * If necessary, i2c_writel() and i2c_readl() will offset the register
344 * in order to talk to the I2C block inside the DVC block.
345 */
tegra_i2c_reg_addr(struct tegra_i2c_dev * i2c_dev,unsigned int reg)346 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
347 {
348 if (IS_DVC(i2c_dev))
349 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
350 else if (IS_VI(i2c_dev))
351 reg = 0xc00 + (reg << 2);
352
353 return reg;
354 }
355
i2c_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned int reg)356 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
357 {
358 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
359
360 /* read back register to make sure that register writes completed */
361 if (reg != I2C_TX_FIFO)
362 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
363 else if (IS_VI(i2c_dev))
364 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
365 }
366
i2c_readl(struct tegra_i2c_dev * i2c_dev,unsigned int reg)367 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
368 {
369 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
370 }
371
i2c_writesl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)372 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
373 unsigned int reg, unsigned int len)
374 {
375 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
376 }
377
i2c_writesl_vi(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)378 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
379 unsigned int reg, unsigned int len)
380 {
381 u32 *data32 = data;
382
383 /*
384 * VI I2C controller has known hardware bug where writes get stuck
385 * when immediate multiple writes happen to TX_FIFO register.
386 * Recommended software work around is to read I2C register after
387 * each write to TX_FIFO register to flush out the data.
388 */
389 while (len--)
390 i2c_writel(i2c_dev, *data32++, reg);
391 }
392
i2c_readsl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)393 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
394 unsigned int reg, unsigned int len)
395 {
396 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
397 }
398
tegra_i2c_mutex_acquired(struct tegra_i2c_dev * i2c_dev)399 static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev)
400 {
401 unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
402 u32 val, id;
403
404 val = readl(i2c_dev->base + reg);
405 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
406
407 return id == I2C_SW_MUTEX_ID_CCPLEX;
408 }
409
tegra_i2c_mutex_trylock(struct tegra_i2c_dev * i2c_dev)410 static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
411 {
412 unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
413 u32 val, id;
414
415 val = readl(i2c_dev->base + reg);
416 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
417 if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX)
418 return false;
419
420 val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX);
421 writel(val, i2c_dev->base + reg);
422
423 return tegra_i2c_mutex_acquired(i2c_dev);
424 }
425
tegra_i2c_mutex_lock(struct tegra_i2c_dev * i2c_dev)426 static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev)
427 {
428 bool locked;
429 int ret;
430
431 if (!i2c_dev->hw->has_mutex)
432 return 0;
433
434 if (i2c_dev->atomic_mode)
435 ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked,
436 USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US,
437 false, i2c_dev);
438 else
439 ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC,
440 I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev);
441
442 if (ret)
443 dev_warn(i2c_dev->dev, "failed to acquire mutex\n");
444
445 return ret;
446 }
447
tegra_i2c_mutex_unlock(struct tegra_i2c_dev * i2c_dev)448 static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
449 {
450 unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
451 u32 val, id;
452
453 if (!i2c_dev->hw->has_mutex)
454 return 0;
455
456 val = readl(i2c_dev->base + reg);
457
458 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
459 if (id && id != I2C_SW_MUTEX_ID_CCPLEX) {
460 dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id);
461 return -EPERM;
462 }
463
464 writel(0, i2c_dev->base + reg);
465
466 return 0;
467 }
468
tegra_i2c_mask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)469 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
470 {
471 u32 int_mask;
472
473 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
474 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
475 }
476
tegra_i2c_unmask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)477 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
478 {
479 u32 int_mask;
480
481 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
482 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
483 }
484
tegra_i2c_dma_complete(void * args)485 static void tegra_i2c_dma_complete(void *args)
486 {
487 struct tegra_i2c_dev *i2c_dev = args;
488
489 complete(&i2c_dev->dma_complete);
490 }
491
tegra_i2c_dma_submit(struct tegra_i2c_dev * i2c_dev,size_t len)492 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
493 {
494 struct dma_async_tx_descriptor *dma_desc;
495 enum dma_transfer_direction dir;
496
497 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
498
499 reinit_completion(&i2c_dev->dma_complete);
500
501 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
502
503 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys,
504 len, dir, DMA_PREP_INTERRUPT |
505 DMA_CTRL_ACK);
506 if (!dma_desc) {
507 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
508 i2c_dev->msg_read ? "RX" : "TX");
509 return -EINVAL;
510 }
511
512 dma_desc->callback = tegra_i2c_dma_complete;
513 dma_desc->callback_param = i2c_dev;
514
515 dmaengine_submit(dma_desc);
516 dma_async_issue_pending(i2c_dev->dma_chan);
517
518 return 0;
519 }
520
tegra_i2c_release_dma(struct tegra_i2c_dev * i2c_dev)521 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
522 {
523 if (i2c_dev->dma_buf) {
524 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
525 i2c_dev->dma_buf, i2c_dev->dma_phys);
526 i2c_dev->dma_buf = NULL;
527 }
528
529 if (i2c_dev->dma_chan) {
530 dma_release_channel(i2c_dev->dma_chan);
531 i2c_dev->dma_chan = NULL;
532 }
533 }
534
tegra_i2c_init_dma(struct tegra_i2c_dev * i2c_dev)535 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
536 {
537 dma_addr_t dma_phys;
538 u32 *dma_buf;
539 int err;
540
541 if (IS_VI(i2c_dev))
542 return 0;
543
544 if (!of_property_present(i2c_dev->dev->of_node, "dmas")) {
545 dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n");
546 return 0;
547 }
548
549 if (i2c_dev->hw->has_apb_dma) {
550 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
551 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");
552 return 0;
553 }
554 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) {
555 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n");
556 return 0;
557 }
558
559 /*
560 * The same channel will be used for both RX and TX.
561 * Keeping the name as "tx" for backward compatibility
562 * with existing devicetrees.
563 */
564 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx");
565 if (IS_ERR(i2c_dev->dma_chan)) {
566 err = PTR_ERR(i2c_dev->dma_chan);
567 i2c_dev->dma_chan = NULL;
568 goto err_out;
569 }
570
571 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;
572 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
573 I2C_PACKET_HEADER_SIZE;
574
575 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
576 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
577 if (!dma_buf) {
578 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
579 err = -ENOMEM;
580 goto err_out;
581 }
582
583 i2c_dev->dma_buf = dma_buf;
584 i2c_dev->dma_phys = dma_phys;
585
586 return 0;
587
588 err_out:
589 tegra_i2c_release_dma(i2c_dev);
590 if (err != -EPROBE_DEFER) {
591 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
592 dev_err(i2c_dev->dev, "falling back to PIO\n");
593 return 0;
594 }
595
596 return err;
597 }
598
599 /*
600 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
601 * block. This block is identical to the rest of the I2C blocks, except that
602 * it only supports master mode, it has registers moved around, and it needs
603 * some extra init to get it into I2C mode. The register moves are handled
604 * by i2c_readl() and i2c_writel().
605 */
tegra_dvc_init(struct tegra_i2c_dev * i2c_dev)606 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
607 {
608 u32 val;
609
610 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
611 val |= DVC_CTRL_REG3_SW_PROG;
612 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
613 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
614
615 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
616 val |= DVC_CTRL_REG1_INTR_EN;
617 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
618 }
619
tegra_i2c_vi_init(struct tegra_i2c_dev * i2c_dev)620 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
621 {
622 u32 value;
623
624 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
625 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
626 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
627
628 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
629 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
630 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
631 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
632 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
633
634 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
635 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
636 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
637
638 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
639 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
640 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
641 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
642
643 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
644 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
645
646 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
647 }
648
tegra_i2c_poll_register(struct tegra_i2c_dev * i2c_dev,u32 reg,u32 mask,u32 delay_us,u32 timeout_us)649 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
650 u32 reg, u32 mask, u32 delay_us,
651 u32 timeout_us)
652 {
653 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
654 u32 val;
655
656 if (!i2c_dev->atomic_mode)
657 return readl_relaxed_poll_timeout(addr, val, !(val & mask),
658 delay_us, timeout_us);
659
660 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
661 delay_us, timeout_us);
662 }
663
tegra_i2c_flush_fifos(struct tegra_i2c_dev * i2c_dev)664 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
665 {
666 u32 mask, val, offset;
667 int err;
668
669 if (i2c_dev->hw->has_mst_fifo) {
670 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
671 I2C_MST_FIFO_CONTROL_RX_FLUSH;
672 offset = I2C_MST_FIFO_CONTROL;
673 } else {
674 mask = I2C_FIFO_CONTROL_TX_FLUSH |
675 I2C_FIFO_CONTROL_RX_FLUSH;
676 offset = I2C_FIFO_CONTROL;
677 }
678
679 val = i2c_readl(i2c_dev, offset);
680 val |= mask;
681 i2c_writel(i2c_dev, val, offset);
682
683 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
684 if (err) {
685 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
686 return err;
687 }
688
689 return 0;
690 }
691
tegra_i2c_wait_for_config_load(struct tegra_i2c_dev * i2c_dev)692 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
693 {
694 int err;
695
696 if (!i2c_dev->hw->has_config_load_reg)
697 return 0;
698
699 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
700
701 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
702 1000, I2C_CONFIG_LOAD_TIMEOUT);
703 if (err) {
704 dev_err(i2c_dev->dev, "failed to load config\n");
705 return err;
706 }
707
708 return 0;
709 }
710
tegra_i2c_master_reset(struct tegra_i2c_dev * i2c_dev)711 static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
712 {
713 if (!i2c_dev->hw->has_mst_reset)
714 return -EOPNOTSUPP;
715
716 /*
717 * Writing 1 to I2C_MASTER_RESET_CNTRL will reset all internal state of
718 * Master logic including FIFOs. Clear this bit to 0 for normal operation.
719 * SW needs to wait for 2us after assertion and de-assertion of this soft
720 * reset.
721 */
722 i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL);
723 fsleep(2);
724
725 i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL);
726 fsleep(2);
727
728 return 0;
729 }
730
tegra_i2c_init(struct tegra_i2c_dev * i2c_dev)731 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
732 {
733 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
734 u32 max_bus_freq_hz;
735 struct i2c_timings *t = &i2c_dev->timings;
736 int err;
737
738 /*
739 * Reset the controller before initializing it.
740 * In case if device_reset() returns -ENOENT, i.e. when the reset is
741 * not available, the internal software reset will be used if it is
742 * supported by the controller.
743 */
744 err = device_reset(i2c_dev->dev);
745 if (err == -ENOENT)
746 err = tegra_i2c_master_reset(i2c_dev);
747
748 /*
749 * The reset shouldn't ever fail in practice. The failure will be a
750 * sign of a severe problem that needs to be resolved. Still we don't
751 * want to fail the initialization completely because this may break
752 * kernel boot up since voltage regulators use I2C. Hence, we will
753 * emit a noisy warning on error, which won't stay unnoticed and
754 * won't hose machine entirely.
755 */
756 WARN_ON_ONCE(err);
757
758 if (IS_DVC(i2c_dev))
759 tegra_dvc_init(i2c_dev);
760
761 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
762 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
763
764 if (i2c_dev->hw->has_multi_master_mode)
765 val |= I2C_CNFG_MULTI_MASTER_MODE;
766
767 i2c_writel(i2c_dev, val, I2C_CNFG);
768 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
769
770 if (IS_VI(i2c_dev))
771 tegra_i2c_vi_init(i2c_dev);
772
773 if (i2c_dev->hw->enable_hs_mode_support)
774 max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ;
775 else
776 max_bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
777
778 if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz))
779 t->bus_freq_hz = max_bus_freq_hz;
780
781 if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
782 tlow = i2c_dev->hw->tlow_std_mode;
783 thigh = i2c_dev->hw->thigh_std_mode;
784 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
785 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
786 } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
787 tlow = i2c_dev->hw->tlow_fast_mode;
788 thigh = i2c_dev->hw->thigh_fast_mode;
789 tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
790 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
791 } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
792 tlow = i2c_dev->hw->tlow_fastplus_mode;
793 thigh = i2c_dev->hw->thigh_fastplus_mode;
794 tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode;
795 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
796 } else {
797 /*
798 * When using HS mode, i.e. when the bus frequency is greater than fast plus mode,
799 * the non-hs timing registers will be used for sending the master code byte for
800 * transition to HS mode. Configure the non-hs timing registers for Fast Mode to
801 * send the master code byte at 400kHz.
802 */
803 tlow = i2c_dev->hw->tlow_fast_mode;
804 thigh = i2c_dev->hw->thigh_fast_mode;
805 tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
806 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
807 }
808
809 /* make sure clock divisor programmed correctly */
810 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
811 i2c_dev->hw->clk_divisor_hs_mode) |
812 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
813 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
814
815 if (i2c_dev->hw->has_interface_timing_reg) {
816 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
817 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
818 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
819 }
820
821 /*
822 * Configure setup and hold times only when tsu_thd is non-zero.
823 * Otherwise, preserve the chip default values.
824 */
825 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
826 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
827
828 /* Write HS mode registers. These will get used only for HS mode*/
829 if (i2c_dev->hw->enable_hs_mode_support) {
830 tlow = i2c_dev->hw->tlow_hs_mode;
831 thigh = i2c_dev->hw->thigh_hs_mode;
832 tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
833
834 val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
835 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
836 i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0);
837 i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1);
838 }
839
840 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
841
842 err = clk_set_rate(i2c_dev->div_clk,
843 t->bus_freq_hz * clk_multiplier);
844 if (err) {
845 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
846 return err;
847 }
848
849 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
850 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
851
852 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
853 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
854 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
855 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
856 }
857
858 err = tegra_i2c_flush_fifos(i2c_dev);
859 if (err)
860 return err;
861
862 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
863 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
864
865 err = tegra_i2c_wait_for_config_load(i2c_dev);
866 if (err)
867 return err;
868
869 return 0;
870 }
871
tegra_i2c_disable_packet_mode(struct tegra_i2c_dev * i2c_dev)872 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
873 {
874 u32 cnfg;
875
876 /*
877 * NACK interrupt is generated before the I2C controller generates
878 * the STOP condition on the bus. So, wait for 2 clock periods
879 * before disabling the controller so that the STOP condition has
880 * been delivered properly.
881 */
882 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
883
884 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
885 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
886 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
887
888 return tegra_i2c_wait_for_config_load(i2c_dev);
889 }
890
tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev * i2c_dev)891 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
892 {
893 size_t buf_remaining = i2c_dev->msg_buf_remaining;
894 unsigned int words_to_transfer, rx_fifo_avail;
895 u8 *buf = i2c_dev->msg_buf;
896 u32 val;
897
898 /*
899 * Catch overflow due to message fully sent before the check for
900 * RX FIFO availability.
901 */
902 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
903 return -EINVAL;
904
905 if (i2c_dev->hw->has_mst_fifo) {
906 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
907 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
908 } else {
909 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
910 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
911 }
912
913 /* round down to exclude partial word at the end of buffer */
914 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
915 if (words_to_transfer > rx_fifo_avail)
916 words_to_transfer = rx_fifo_avail;
917
918 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
919
920 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
921 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
922 rx_fifo_avail -= words_to_transfer;
923
924 /*
925 * If there is a partial word at the end of buffer, handle it
926 * manually to prevent overwriting past the end of buffer.
927 */
928 if (rx_fifo_avail > 0 && buf_remaining > 0) {
929 /*
930 * buf_remaining > 3 check not needed as rx_fifo_avail == 0
931 * when (words_to_transfer was > rx_fifo_avail) earlier
932 * in this function.
933 */
934 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
935 val = cpu_to_le32(val);
936 memcpy(buf, &val, buf_remaining);
937 buf_remaining = 0;
938 rx_fifo_avail--;
939 }
940
941 /* RX FIFO must be drained, otherwise it's an Overflow case. */
942 if (WARN_ON_ONCE(rx_fifo_avail))
943 return -EINVAL;
944
945 i2c_dev->msg_buf_remaining = buf_remaining;
946 i2c_dev->msg_buf = buf;
947
948 return 0;
949 }
950
tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev * i2c_dev)951 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
952 {
953 size_t buf_remaining = i2c_dev->msg_buf_remaining;
954 unsigned int words_to_transfer, tx_fifo_avail;
955 u8 *buf = i2c_dev->msg_buf;
956 u32 val;
957
958 if (i2c_dev->hw->has_mst_fifo) {
959 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
960 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
961 } else {
962 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
963 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
964 }
965
966 /* round down to exclude partial word at the end of buffer */
967 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
968
969 /*
970 * This hunk pushes 4 bytes at a time into the TX FIFO.
971 *
972 * It's very common to have < 4 bytes, hence there is no word
973 * to push if we have less than 4 bytes to transfer.
974 */
975 if (words_to_transfer) {
976 if (words_to_transfer > tx_fifo_avail)
977 words_to_transfer = tx_fifo_avail;
978
979 /*
980 * Update state before writing to FIFO. Note that this may
981 * cause us to finish writing all bytes (AKA buf_remaining
982 * goes to 0), hence we have a potential for an interrupt
983 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
984 * is disabled at this point.
985 */
986 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
987 tx_fifo_avail -= words_to_transfer;
988
989 i2c_dev->msg_buf_remaining = buf_remaining;
990 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
991
992 if (IS_VI(i2c_dev))
993 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
994 else
995 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
996
997 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
998 }
999
1000 /*
1001 * If there is a partial word at the end of buffer, handle it manually
1002 * to prevent reading past the end of buffer, which could cross a page
1003 * boundary and fault.
1004 */
1005 if (tx_fifo_avail > 0 && buf_remaining > 0) {
1006 /*
1007 * buf_remaining > 3 check not needed as tx_fifo_avail == 0
1008 * when (words_to_transfer was > tx_fifo_avail) earlier
1009 * in this function for non-zero words_to_transfer.
1010 */
1011 memcpy(&val, buf, buf_remaining);
1012 val = le32_to_cpu(val);
1013
1014 i2c_dev->msg_buf_remaining = 0;
1015 i2c_dev->msg_buf = NULL;
1016
1017 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
1018 }
1019
1020 return 0;
1021 }
1022
tegra_i2c_isr(int irq,void * dev_id)1023 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
1024 {
1025 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1026 struct tegra_i2c_dev *i2c_dev = dev_id;
1027 u32 status;
1028
1029 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1030
1031 if (status == 0) {
1032 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
1033 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
1034 i2c_readl(i2c_dev, I2C_STATUS),
1035 i2c_readl(i2c_dev, I2C_CNFG));
1036 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1037 goto err;
1038 }
1039
1040 if (status & status_err) {
1041 tegra_i2c_disable_packet_mode(i2c_dev);
1042 if (status & I2C_INT_NO_ACK)
1043 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
1044 if (status & I2C_INT_ARBITRATION_LOST)
1045 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
1046 goto err;
1047 }
1048
1049 /*
1050 * I2C transfer is terminated during the bus clear, so skip
1051 * processing the other interrupts.
1052 */
1053 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
1054 goto err;
1055
1056 if (!i2c_dev->dma_mode) {
1057 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
1058 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
1059 /*
1060 * Overflow error condition: message fully sent,
1061 * with no XFER_COMPLETE interrupt but hardware
1062 * asks to transfer more.
1063 */
1064 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
1065 goto err;
1066 }
1067 }
1068
1069 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
1070 if (i2c_dev->msg_buf_remaining)
1071 tegra_i2c_fill_tx_fifo(i2c_dev);
1072 else
1073 tegra_i2c_mask_irq(i2c_dev,
1074 I2C_INT_TX_FIFO_DATA_REQ);
1075 }
1076 }
1077
1078 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
1079 if (IS_DVC(i2c_dev))
1080 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1081
1082 /*
1083 * During message read XFER_COMPLETE interrupt is triggered prior to
1084 * DMA completion and during message write XFER_COMPLETE interrupt is
1085 * triggered after DMA completion.
1086 *
1087 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
1088 * so forcing msg_buf_remaining to 0 in DMA mode.
1089 */
1090 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
1091 if (i2c_dev->dma_mode)
1092 i2c_dev->msg_buf_remaining = 0;
1093 /*
1094 * Underflow error condition: XFER_COMPLETE before message
1095 * fully sent.
1096 */
1097 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
1098 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1099 goto err;
1100 }
1101 complete(&i2c_dev->msg_complete);
1102 }
1103 goto done;
1104 err:
1105 /* mask all interrupts on error */
1106 tegra_i2c_mask_irq(i2c_dev,
1107 I2C_INT_NO_ACK |
1108 I2C_INT_ARBITRATION_LOST |
1109 I2C_INT_PACKET_XFER_COMPLETE |
1110 I2C_INT_TX_FIFO_DATA_REQ |
1111 I2C_INT_RX_FIFO_DATA_REQ);
1112
1113 if (i2c_dev->hw->supports_bus_clear)
1114 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1115
1116 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
1117
1118 if (IS_DVC(i2c_dev))
1119 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1120
1121 if (i2c_dev->dma_mode) {
1122 dmaengine_terminate_async(i2c_dev->dma_chan);
1123 complete(&i2c_dev->dma_complete);
1124 }
1125
1126 complete(&i2c_dev->msg_complete);
1127 done:
1128 return IRQ_HANDLED;
1129 }
1130
tegra_i2c_config_fifo_trig(struct tegra_i2c_dev * i2c_dev,size_t len)1131 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
1132 size_t len)
1133 {
1134 struct dma_slave_config slv_config = {0};
1135 u32 val, reg, dma_burst, reg_offset;
1136 int err;
1137
1138 if (i2c_dev->hw->has_mst_fifo)
1139 reg = I2C_MST_FIFO_CONTROL;
1140 else
1141 reg = I2C_FIFO_CONTROL;
1142
1143 if (i2c_dev->dma_mode) {
1144 if (len & 0xF)
1145 dma_burst = 1;
1146 else if (len & 0x10)
1147 dma_burst = 4;
1148 else
1149 dma_burst = 8;
1150
1151 if (i2c_dev->msg_read) {
1152 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1153
1154 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1155 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1156 slv_config.src_maxburst = dma_burst;
1157
1158 if (i2c_dev->hw->has_mst_fifo)
1159 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1160 else
1161 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1162 } else {
1163 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1164
1165 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1166 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1167 slv_config.dst_maxburst = dma_burst;
1168
1169 if (i2c_dev->hw->has_mst_fifo)
1170 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1171 else
1172 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1173 }
1174
1175 slv_config.device_fc = true;
1176 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config);
1177 if (err) {
1178 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1179 dev_err(i2c_dev->dev, "falling back to PIO\n");
1180
1181 tegra_i2c_release_dma(i2c_dev);
1182 i2c_dev->dma_mode = false;
1183 } else {
1184 goto out;
1185 }
1186 }
1187
1188 if (i2c_dev->hw->has_mst_fifo)
1189 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1190 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1191 else
1192 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1193 I2C_FIFO_CONTROL_RX_TRIG(1);
1194 out:
1195 i2c_writel(i2c_dev, val, reg);
1196 }
1197
tegra_i2c_poll_completion(struct tegra_i2c_dev * i2c_dev,struct completion * complete,unsigned int timeout_ms)1198 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1199 struct completion *complete,
1200 unsigned int timeout_ms)
1201 {
1202 ktime_t ktime = ktime_get();
1203 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1204
1205 do {
1206 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1207
1208 if (status)
1209 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1210
1211 if (completion_done(complete)) {
1212 s64 delta = ktime_ms_delta(ktimeout, ktime);
1213
1214 return msecs_to_jiffies(delta) ?: 1;
1215 }
1216
1217 ktime = ktime_get();
1218
1219 } while (ktime_before(ktime, ktimeout));
1220
1221 return 0;
1222 }
1223
tegra_i2c_wait_completion(struct tegra_i2c_dev * i2c_dev,struct completion * complete,unsigned int timeout_ms)1224 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1225 struct completion *complete,
1226 unsigned int timeout_ms)
1227 {
1228 unsigned long ret;
1229
1230 if (i2c_dev->atomic_mode) {
1231 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1232 } else {
1233 enable_irq(i2c_dev->irq);
1234 ret = wait_for_completion_timeout(complete,
1235 msecs_to_jiffies(timeout_ms));
1236 disable_irq(i2c_dev->irq);
1237
1238 /*
1239 * Under some rare circumstances (like running KASAN +
1240 * NFS root) CPU, which handles interrupt, may stuck in
1241 * uninterruptible state for a significant time. In this
1242 * case we will get timeout if I2C transfer is running on
1243 * a sibling CPU, despite of IRQ being raised.
1244 *
1245 * In order to handle this rare condition, the IRQ status
1246 * needs to be checked after timeout.
1247 */
1248 if (ret == 0)
1249 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1250 }
1251
1252 return ret;
1253 }
1254
tegra_i2c_issue_bus_clear(struct i2c_adapter * adap)1255 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1256 {
1257 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1258 u32 val, time_left;
1259 int err;
1260
1261 reinit_completion(&i2c_dev->msg_complete);
1262
1263 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1264 I2C_BC_TERMINATE;
1265 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1266
1267 err = tegra_i2c_wait_for_config_load(i2c_dev);
1268 if (err)
1269 return err;
1270
1271 val |= I2C_BC_ENABLE;
1272 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1273 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1274
1275 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1276 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1277
1278 if (time_left == 0) {
1279 dev_err(i2c_dev->dev, "failed to clear bus\n");
1280 return -ETIMEDOUT;
1281 }
1282
1283 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1284 if (!(val & I2C_BC_STATUS)) {
1285 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1286 return -EIO;
1287 }
1288
1289 return -EAGAIN;
1290 }
1291
tegra_i2c_push_packet_header(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)1292 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1293 struct i2c_msg *msg,
1294 enum msg_end_type end_state)
1295 {
1296 u32 *dma_buf = i2c_dev->dma_buf;
1297 u32 packet_header;
1298
1299 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1300 FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1301 PACKET_HEADER0_PROTOCOL_I2C) |
1302 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1303 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1304
1305 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1306 *dma_buf++ = packet_header;
1307 else
1308 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1309
1310 packet_header = i2c_dev->msg_len - 1;
1311
1312 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1313 *dma_buf++ = packet_header;
1314 else
1315 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1316
1317 packet_header = I2C_HEADER_IE_ENABLE;
1318
1319 if (end_state == MSG_END_CONTINUE)
1320 packet_header |= I2C_HEADER_CONTINUE_XFER;
1321 else if (end_state == MSG_END_REPEAT_START)
1322 packet_header |= I2C_HEADER_REPEAT_START;
1323
1324 if (msg->flags & I2C_M_TEN) {
1325 packet_header |= msg->addr;
1326 packet_header |= I2C_HEADER_10BIT_ADDR;
1327 } else {
1328 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1329 }
1330
1331 if (msg->flags & I2C_M_IGNORE_NAK)
1332 packet_header |= I2C_HEADER_CONT_ON_NAK;
1333
1334 if (msg->flags & I2C_M_RD)
1335 packet_header |= I2C_HEADER_READ;
1336
1337 if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1338 packet_header |= I2C_HEADER_HS_MODE;
1339
1340 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1341 *dma_buf++ = packet_header;
1342 else
1343 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1344 }
1345
tegra_i2c_error_recover(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg)1346 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1347 struct i2c_msg *msg)
1348 {
1349 if (i2c_dev->msg_err == I2C_ERR_NONE)
1350 return 0;
1351
1352 tegra_i2c_init(i2c_dev);
1353
1354 /* start recovery upon arbitration loss in single master mode */
1355 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1356 if (!i2c_dev->multimaster_mode)
1357 return i2c_recover_bus(&i2c_dev->adapter);
1358
1359 return -EAGAIN;
1360 }
1361
1362 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1363 if (msg->flags & I2C_M_IGNORE_NAK)
1364 return 0;
1365
1366 return -EREMOTEIO;
1367 }
1368
1369 return -EIO;
1370 }
1371
tegra_i2c_xfer_msg(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)1372 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1373 struct i2c_msg *msg,
1374 enum msg_end_type end_state)
1375 {
1376 unsigned long time_left, xfer_time = 100;
1377 size_t xfer_size;
1378 u32 int_mask;
1379 int err;
1380
1381 err = tegra_i2c_flush_fifos(i2c_dev);
1382 if (err)
1383 return err;
1384
1385 i2c_dev->msg_buf = msg->buf;
1386 i2c_dev->msg_len = msg->len;
1387
1388 i2c_dev->msg_err = I2C_ERR_NONE;
1389 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1390 reinit_completion(&i2c_dev->msg_complete);
1391
1392 /*
1393 * For SMBUS block read command, read only 1 byte in the first transfer.
1394 * Adjust that 1 byte for the next transfer in the msg buffer and msg
1395 * length.
1396 */
1397 if (msg->flags & I2C_M_RECV_LEN) {
1398 if (end_state == MSG_END_CONTINUE) {
1399 i2c_dev->msg_len = 1;
1400 } else {
1401 i2c_dev->msg_buf += 1;
1402 i2c_dev->msg_len -= 1;
1403 }
1404 }
1405
1406 i2c_dev->msg_buf_remaining = i2c_dev->msg_len;
1407
1408 if (i2c_dev->msg_read)
1409 xfer_size = i2c_dev->msg_len;
1410 else
1411 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE;
1412
1413 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1414
1415 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1416 i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1417
1418 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1419
1420 /*
1421 * Transfer time in mSec = Total bits / transfer rate
1422 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1423 */
1424 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1425 i2c_dev->timings.bus_freq_hz);
1426
1427 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1428 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1429
1430 if (i2c_dev->dma_mode) {
1431 if (i2c_dev->msg_read) {
1432 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1433 if (err)
1434 return err;
1435 }
1436 }
1437
1438 tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1439
1440 if (!i2c_dev->msg_read) {
1441 if (i2c_dev->dma_mode) {
1442 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1443 msg->buf, i2c_dev->msg_len);
1444 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1445 if (err)
1446 return err;
1447 } else {
1448 tegra_i2c_fill_tx_fifo(i2c_dev);
1449 }
1450 }
1451
1452 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1453 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1454
1455 if (!i2c_dev->dma_mode) {
1456 if (msg->flags & I2C_M_RD)
1457 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1458 else if (i2c_dev->msg_buf_remaining)
1459 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1460 }
1461
1462 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1463 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1464 i2c_readl(i2c_dev, I2C_INT_MASK));
1465
1466 if (i2c_dev->dma_mode) {
1467 time_left = tegra_i2c_wait_completion(i2c_dev,
1468 &i2c_dev->dma_complete,
1469 xfer_time);
1470
1471 /*
1472 * Synchronize DMA first, since dmaengine_terminate_sync()
1473 * performs synchronization after the transfer's termination
1474 * and we want to get a completion if transfer succeeded.
1475 */
1476 dmaengine_synchronize(i2c_dev->dma_chan);
1477 dmaengine_terminate_sync(i2c_dev->dma_chan);
1478
1479 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1480 tegra_i2c_init(i2c_dev);
1481 return -ETIMEDOUT;
1482 }
1483
1484 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE)
1485 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
1486 }
1487
1488 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1489 xfer_time);
1490
1491 tegra_i2c_mask_irq(i2c_dev, int_mask);
1492
1493 if (time_left == 0) {
1494 tegra_i2c_init(i2c_dev);
1495 return -ETIMEDOUT;
1496 }
1497
1498 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1499 time_left, completion_done(&i2c_dev->msg_complete),
1500 i2c_dev->msg_err);
1501
1502 i2c_dev->dma_mode = false;
1503
1504 err = tegra_i2c_error_recover(i2c_dev, msg);
1505 if (err)
1506 return err;
1507
1508 return 0;
1509 }
1510
tegra_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1511 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1512 int num)
1513 {
1514 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1515 int i, ret;
1516
1517 ret = pm_runtime_get_sync(i2c_dev->dev);
1518 if (ret < 0) {
1519 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1520 pm_runtime_put_noidle(i2c_dev->dev);
1521 return ret;
1522 }
1523
1524 ret = tegra_i2c_mutex_lock(i2c_dev);
1525 if (ret)
1526 return ret;
1527
1528 for (i = 0; i < num; i++) {
1529 enum msg_end_type end_type = MSG_END_STOP;
1530
1531 if (i < (num - 1)) {
1532 /* check whether follow up message is coming */
1533 if (msgs[i + 1].flags & I2C_M_NOSTART)
1534 end_type = MSG_END_CONTINUE;
1535 else
1536 end_type = MSG_END_REPEAT_START;
1537 }
1538 /* If M_RECV_LEN use ContinueXfer to read the first byte */
1539 if (msgs[i].flags & I2C_M_RECV_LEN) {
1540 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE);
1541 if (ret)
1542 break;
1543
1544 /* Validate message length before proceeding */
1545 if (msgs[i].buf[0] == 0 || msgs[i].buf[0] > I2C_SMBUS_BLOCK_MAX)
1546 break;
1547
1548 /* Set the msg length from first byte */
1549 msgs[i].len += msgs[i].buf[0];
1550 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len);
1551 }
1552 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1553 if (ret)
1554 break;
1555 }
1556
1557 ret = tegra_i2c_mutex_unlock(i2c_dev);
1558 pm_runtime_put(i2c_dev->dev);
1559
1560 return ret ?: i;
1561 }
1562
tegra_i2c_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1563 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1564 struct i2c_msg msgs[], int num)
1565 {
1566 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1567 int ret;
1568
1569 i2c_dev->atomic_mode = true;
1570 ret = tegra_i2c_xfer(adap, msgs, num);
1571 i2c_dev->atomic_mode = false;
1572
1573 return ret;
1574 }
1575
tegra_i2c_func(struct i2c_adapter * adap)1576 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1577 {
1578 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1579 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1580 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1581
1582 if (i2c_dev->hw->has_continue_xfer_support)
1583 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1584
1585 return ret;
1586 }
1587
1588 static const struct i2c_algorithm tegra_i2c_algo = {
1589 .xfer = tegra_i2c_xfer,
1590 .xfer_atomic = tegra_i2c_xfer_atomic,
1591 .functionality = tegra_i2c_func,
1592 };
1593
1594 /* payload size is only 12 bit */
1595 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1596 .flags = I2C_AQ_NO_ZERO_LEN,
1597 .max_read_len = SZ_4K,
1598 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1599 };
1600
1601 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1602 .flags = I2C_AQ_NO_ZERO_LEN,
1603 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1604 };
1605
1606 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1607 .recover_bus = tegra_i2c_issue_bus_clear,
1608 };
1609
1610 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1611 .has_continue_xfer_support = false,
1612 .has_per_pkt_xfer_complete_irq = false,
1613 .clk_divisor_hs_mode = 3,
1614 .clk_divisor_std_mode = 0,
1615 .clk_divisor_fast_mode = 0,
1616 .clk_divisor_fast_plus_mode = 0,
1617 .has_config_load_reg = false,
1618 .has_multi_master_mode = false,
1619 .has_slcg_override_reg = false,
1620 .has_mst_fifo = false,
1621 .has_mst_reset = false,
1622 .quirks = &tegra_i2c_quirks,
1623 .supports_bus_clear = false,
1624 .has_apb_dma = true,
1625 .tlow_std_mode = 0x4,
1626 .thigh_std_mode = 0x2,
1627 .tlow_fast_mode = 0x4,
1628 .thigh_fast_mode = 0x2,
1629 .tlow_fastplus_mode = 0x4,
1630 .thigh_fastplus_mode = 0x2,
1631 .setup_hold_time_std_mode = 0x0,
1632 .setup_hold_time_fast_mode = 0x0,
1633 .setup_hold_time_fastplus_mode = 0x0,
1634 .setup_hold_time_hs_mode = 0x0,
1635 .has_interface_timing_reg = false,
1636 .enable_hs_mode_support = false,
1637 .has_mutex = false,
1638 };
1639
1640 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1641 .has_continue_xfer_support = true,
1642 .has_per_pkt_xfer_complete_irq = false,
1643 .clk_divisor_hs_mode = 3,
1644 .clk_divisor_std_mode = 0,
1645 .clk_divisor_fast_mode = 0,
1646 .clk_divisor_fast_plus_mode = 0,
1647 .has_config_load_reg = false,
1648 .has_multi_master_mode = false,
1649 .has_slcg_override_reg = false,
1650 .has_mst_fifo = false,
1651 .has_mst_reset = false,
1652 .quirks = &tegra_i2c_quirks,
1653 .supports_bus_clear = false,
1654 .has_apb_dma = true,
1655 .tlow_std_mode = 0x4,
1656 .thigh_std_mode = 0x2,
1657 .tlow_fast_mode = 0x4,
1658 .thigh_fast_mode = 0x2,
1659 .tlow_fastplus_mode = 0x4,
1660 .thigh_fastplus_mode = 0x2,
1661 .setup_hold_time_std_mode = 0x0,
1662 .setup_hold_time_fast_mode = 0x0,
1663 .setup_hold_time_fastplus_mode = 0x0,
1664 .setup_hold_time_hs_mode = 0x0,
1665 .has_interface_timing_reg = false,
1666 .enable_hs_mode_support = false,
1667 .has_mutex = false,
1668 };
1669
1670 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1671 .has_continue_xfer_support = true,
1672 .has_per_pkt_xfer_complete_irq = true,
1673 .clk_divisor_hs_mode = 1,
1674 .clk_divisor_std_mode = 0x19,
1675 .clk_divisor_fast_mode = 0x19,
1676 .clk_divisor_fast_plus_mode = 0x10,
1677 .has_config_load_reg = false,
1678 .has_multi_master_mode = false,
1679 .has_slcg_override_reg = false,
1680 .has_mst_fifo = false,
1681 .has_mst_reset = false,
1682 .quirks = &tegra_i2c_quirks,
1683 .supports_bus_clear = true,
1684 .has_apb_dma = true,
1685 .tlow_std_mode = 0x4,
1686 .thigh_std_mode = 0x2,
1687 .tlow_fast_mode = 0x4,
1688 .thigh_fast_mode = 0x2,
1689 .tlow_fastplus_mode = 0x4,
1690 .thigh_fastplus_mode = 0x2,
1691 .setup_hold_time_std_mode = 0x0,
1692 .setup_hold_time_fast_mode = 0x0,
1693 .setup_hold_time_fastplus_mode = 0x0,
1694 .setup_hold_time_hs_mode = 0x0,
1695 .has_interface_timing_reg = false,
1696 .enable_hs_mode_support = false,
1697 .has_mutex = false,
1698 };
1699
1700 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1701 .has_continue_xfer_support = true,
1702 .has_per_pkt_xfer_complete_irq = true,
1703 .clk_divisor_hs_mode = 1,
1704 .clk_divisor_std_mode = 0x19,
1705 .clk_divisor_fast_mode = 0x19,
1706 .clk_divisor_fast_plus_mode = 0x10,
1707 .has_config_load_reg = true,
1708 .has_multi_master_mode = false,
1709 .has_slcg_override_reg = true,
1710 .has_mst_fifo = false,
1711 .has_mst_reset = false,
1712 .quirks = &tegra_i2c_quirks,
1713 .supports_bus_clear = true,
1714 .has_apb_dma = true,
1715 .tlow_std_mode = 0x4,
1716 .thigh_std_mode = 0x2,
1717 .tlow_fast_mode = 0x4,
1718 .thigh_fast_mode = 0x2,
1719 .tlow_fastplus_mode = 0x4,
1720 .thigh_fastplus_mode = 0x2,
1721 .setup_hold_time_std_mode = 0x0,
1722 .setup_hold_time_fast_mode = 0x0,
1723 .setup_hold_time_fastplus_mode = 0x0,
1724 .setup_hold_time_hs_mode = 0x0,
1725 .has_interface_timing_reg = true,
1726 .enable_hs_mode_support = false,
1727 .has_mutex = false,
1728 };
1729
1730 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1731 .has_continue_xfer_support = true,
1732 .has_per_pkt_xfer_complete_irq = true,
1733 .clk_divisor_hs_mode = 1,
1734 .clk_divisor_std_mode = 0x19,
1735 .clk_divisor_fast_mode = 0x19,
1736 .clk_divisor_fast_plus_mode = 0x10,
1737 .has_config_load_reg = true,
1738 .has_multi_master_mode = false,
1739 .has_slcg_override_reg = true,
1740 .has_mst_fifo = false,
1741 .has_mst_reset = false,
1742 .quirks = &tegra_i2c_quirks,
1743 .supports_bus_clear = true,
1744 .has_apb_dma = true,
1745 .tlow_std_mode = 0x4,
1746 .thigh_std_mode = 0x2,
1747 .tlow_fast_mode = 0x4,
1748 .thigh_fast_mode = 0x2,
1749 .tlow_fastplus_mode = 0x4,
1750 .thigh_fastplus_mode = 0x2,
1751 .setup_hold_time_std_mode = 0,
1752 .setup_hold_time_fast_mode = 0,
1753 .setup_hold_time_fastplus_mode = 0,
1754 .setup_hold_time_hs_mode = 0,
1755 .has_interface_timing_reg = true,
1756 .enable_hs_mode_support = false,
1757 .has_mutex = false,
1758 };
1759
1760 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1761 .has_continue_xfer_support = true,
1762 .has_per_pkt_xfer_complete_irq = true,
1763 .clk_divisor_hs_mode = 1,
1764 .clk_divisor_std_mode = 0x16,
1765 .clk_divisor_fast_mode = 0x19,
1766 .clk_divisor_fast_plus_mode = 0x10,
1767 .has_config_load_reg = true,
1768 .has_multi_master_mode = false,
1769 .has_slcg_override_reg = true,
1770 .has_mst_fifo = false,
1771 .has_mst_reset = false,
1772 .quirks = &tegra_i2c_quirks,
1773 .supports_bus_clear = true,
1774 .has_apb_dma = false,
1775 .tlow_std_mode = 0x4,
1776 .thigh_std_mode = 0x3,
1777 .tlow_fast_mode = 0x4,
1778 .thigh_fast_mode = 0x2,
1779 .tlow_fastplus_mode = 0x4,
1780 .thigh_fastplus_mode = 0x2,
1781 .setup_hold_time_std_mode = 0,
1782 .setup_hold_time_fast_mode = 0,
1783 .setup_hold_time_fastplus_mode = 0,
1784 .setup_hold_time_hs_mode = 0,
1785 .has_interface_timing_reg = true,
1786 .enable_hs_mode_support = false,
1787 .has_mutex = false,
1788 };
1789
1790 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1791 .has_continue_xfer_support = true,
1792 .has_per_pkt_xfer_complete_irq = true,
1793 .clk_divisor_hs_mode = 1,
1794 .clk_divisor_std_mode = 0x4f,
1795 .clk_divisor_fast_mode = 0x3c,
1796 .clk_divisor_fast_plus_mode = 0x16,
1797 .has_config_load_reg = true,
1798 .has_multi_master_mode = true,
1799 .has_slcg_override_reg = true,
1800 .has_mst_fifo = true,
1801 .has_mst_reset = true,
1802 .quirks = &tegra194_i2c_quirks,
1803 .supports_bus_clear = true,
1804 .has_apb_dma = false,
1805 .tlow_std_mode = 0x8,
1806 .thigh_std_mode = 0x7,
1807 .tlow_fast_mode = 0x2,
1808 .thigh_fast_mode = 0x2,
1809 .tlow_fastplus_mode = 0x2,
1810 .thigh_fastplus_mode = 0x2,
1811 .tlow_hs_mode = 0x8,
1812 .thigh_hs_mode = 0x3,
1813 .setup_hold_time_std_mode = 0x08080808,
1814 .setup_hold_time_fast_mode = 0x02020202,
1815 .setup_hold_time_fastplus_mode = 0x02020202,
1816 .setup_hold_time_hs_mode = 0x090909,
1817 .has_interface_timing_reg = true,
1818 .enable_hs_mode_support = true,
1819 .has_mutex = false,
1820 };
1821
1822 static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
1823 .has_continue_xfer_support = true,
1824 .has_per_pkt_xfer_complete_irq = true,
1825 .clk_divisor_hs_mode = 9,
1826 .clk_divisor_std_mode = 0x7a,
1827 .clk_divisor_fast_mode = 0x40,
1828 .clk_divisor_fast_plus_mode = 0x14,
1829 .has_config_load_reg = true,
1830 .has_multi_master_mode = true,
1831 .has_slcg_override_reg = true,
1832 .has_mst_fifo = true,
1833 .has_mst_reset = true,
1834 .quirks = &tegra194_i2c_quirks,
1835 .supports_bus_clear = true,
1836 .has_apb_dma = false,
1837 .tlow_std_mode = 0x8,
1838 .thigh_std_mode = 0x7,
1839 .tlow_fast_mode = 0x4,
1840 .thigh_fast_mode = 0x2,
1841 .tlow_fastplus_mode = 0x4,
1842 .thigh_fastplus_mode = 0x4,
1843 .tlow_hs_mode = 0x3,
1844 .thigh_hs_mode = 0x2,
1845 .setup_hold_time_std_mode = 0x08080808,
1846 .setup_hold_time_fast_mode = 0x04010101,
1847 .setup_hold_time_fastplus_mode = 0x04020202,
1848 .setup_hold_time_hs_mode = 0x030303,
1849 .has_interface_timing_reg = true,
1850 .enable_hs_mode_support = true,
1851 .has_mutex = true,
1852 };
1853
1854 static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
1855 .has_continue_xfer_support = true,
1856 .has_per_pkt_xfer_complete_irq = true,
1857 .clk_divisor_hs_mode = 1,
1858 .clk_divisor_std_mode = 0x1d,
1859 .clk_divisor_fast_mode = 0x15,
1860 .clk_divisor_fast_plus_mode = 0x8,
1861 .has_config_load_reg = true,
1862 .has_multi_master_mode = true,
1863 .has_slcg_override_reg = true,
1864 .has_mst_fifo = true,
1865 .has_mst_reset = true,
1866 .quirks = &tegra194_i2c_quirks,
1867 .supports_bus_clear = true,
1868 .has_apb_dma = false,
1869 .tlow_std_mode = 0x8,
1870 .thigh_std_mode = 0x7,
1871 .tlow_fast_mode = 0x2,
1872 .thigh_fast_mode = 0x2,
1873 .tlow_fastplus_mode = 0x2,
1874 .thigh_fastplus_mode = 0x2,
1875 .tlow_hs_mode = 0x4,
1876 .thigh_hs_mode = 0x2,
1877 .setup_hold_time_std_mode = 0x08080808,
1878 .setup_hold_time_fast_mode = 0x02020202,
1879 .setup_hold_time_fastplus_mode = 0x02020202,
1880 .setup_hold_time_hs_mode = 0x090909,
1881 .has_interface_timing_reg = true,
1882 .enable_hs_mode_support = true,
1883 .has_mutex = true,
1884 };
1885
1886 static const struct of_device_id tegra_i2c_of_match[] = {
1887 { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, },
1888 { .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
1889 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1890 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1891 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
1892 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1893 #endif
1894 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1895 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1896 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1897 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1898 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1899 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
1900 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1901 #endif
1902 {},
1903 };
1904 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1905
tegra_i2c_parse_dt(struct tegra_i2c_dev * i2c_dev)1906 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1907 {
1908 struct device_node *np = i2c_dev->dev->of_node;
1909 bool multi_mode;
1910
1911 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
1912
1913 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
1914 i2c_dev->multimaster_mode = multi_mode;
1915
1916 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
1917 of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
1918 i2c_dev->is_dvc = true;
1919
1920 if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) &&
1921 of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
1922 i2c_dev->is_vi = true;
1923 }
1924
tegra_i2c_init_clocks(struct tegra_i2c_dev * i2c_dev)1925 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1926 {
1927 int err;
1928
1929 if (ACPI_HANDLE(i2c_dev->dev))
1930 return 0;
1931
1932 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1933
1934 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1935 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1936
1937 if (IS_VI(i2c_dev))
1938 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1939
1940 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1941 i2c_dev->clocks);
1942 if (err)
1943 return err;
1944
1945 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1946 if (err)
1947 return err;
1948
1949 i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1950
1951 if (!i2c_dev->multimaster_mode)
1952 return 0;
1953
1954 err = clk_enable(i2c_dev->div_clk);
1955 if (err) {
1956 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1957 goto unprepare_clocks;
1958 }
1959
1960 return 0;
1961
1962 unprepare_clocks:
1963 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1964
1965 return err;
1966 }
1967
tegra_i2c_release_clocks(struct tegra_i2c_dev * i2c_dev)1968 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1969 {
1970 if (i2c_dev->multimaster_mode)
1971 clk_disable(i2c_dev->div_clk);
1972
1973 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1974 }
1975
tegra_i2c_init_hardware(struct tegra_i2c_dev * i2c_dev)1976 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
1977 {
1978 int ret;
1979
1980 ret = pm_runtime_get_sync(i2c_dev->dev);
1981 if (ret < 0)
1982 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
1983 else
1984 ret = tegra_i2c_init(i2c_dev);
1985
1986 pm_runtime_put_sync(i2c_dev->dev);
1987
1988 return ret;
1989 }
1990
tegra_i2c_probe(struct platform_device * pdev)1991 static int tegra_i2c_probe(struct platform_device *pdev)
1992 {
1993 struct tegra_i2c_dev *i2c_dev;
1994 struct resource *res;
1995 int err;
1996
1997 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1998 if (!i2c_dev)
1999 return -ENOMEM;
2000
2001 platform_set_drvdata(pdev, i2c_dev);
2002
2003 init_completion(&i2c_dev->msg_complete);
2004 init_completion(&i2c_dev->dma_complete);
2005
2006 i2c_dev->hw = device_get_match_data(&pdev->dev);
2007 i2c_dev->cont_id = pdev->id;
2008 i2c_dev->dev = &pdev->dev;
2009
2010 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2011 if (IS_ERR(i2c_dev->base))
2012 return PTR_ERR(i2c_dev->base);
2013
2014 i2c_dev->base_phys = res->start;
2015
2016 err = platform_get_irq(pdev, 0);
2017 if (err < 0)
2018 return err;
2019
2020 i2c_dev->irq = err;
2021
2022 /* interrupt will be enabled during of transfer time */
2023 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
2024
2025 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq,
2026 NULL, tegra_i2c_isr,
2027 IRQF_NO_SUSPEND | IRQF_ONESHOT,
2028 dev_name(i2c_dev->dev), i2c_dev);
2029 if (err)
2030 return err;
2031
2032 tegra_i2c_parse_dt(i2c_dev);
2033
2034 err = tegra_i2c_init_clocks(i2c_dev);
2035 if (err)
2036 return err;
2037
2038 err = tegra_i2c_init_dma(i2c_dev);
2039 if (err)
2040 goto release_clocks;
2041
2042 /*
2043 * VI I2C is in VE power domain which is not always ON and not
2044 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a
2045 * non IRQ-safe domain because this prevents powering off the power
2046 * domain.
2047 *
2048 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
2049 * be used for atomic transfers. ACPI device is not IRQ safe also.
2050 *
2051 * Devices with pinctrl states cannot be marked IRQ-safe as the pinctrl
2052 * state transitions during runtime PM require mutexes.
2053 */
2054 if (!IS_VI(i2c_dev) && !has_acpi_companion(i2c_dev->dev) && !i2c_dev->dev->pins)
2055 pm_runtime_irq_safe(i2c_dev->dev);
2056
2057 pm_runtime_enable(i2c_dev->dev);
2058
2059 err = tegra_i2c_init_hardware(i2c_dev);
2060 if (err)
2061 goto release_rpm;
2062
2063 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
2064 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
2065 i2c_dev->adapter.dev.parent = i2c_dev->dev;
2066 i2c_dev->adapter.retries = 1;
2067 i2c_dev->adapter.timeout = 6 * HZ;
2068 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
2069 i2c_dev->adapter.owner = THIS_MODULE;
2070 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
2071 i2c_dev->adapter.algo = &tegra_i2c_algo;
2072 i2c_dev->adapter.nr = pdev->id;
2073 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev));
2074
2075 if (i2c_dev->hw->supports_bus_clear)
2076 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
2077
2078 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
2079 sizeof(i2c_dev->adapter.name));
2080
2081 err = i2c_add_numbered_adapter(&i2c_dev->adapter);
2082 if (err)
2083 goto release_rpm;
2084
2085 return 0;
2086
2087 release_rpm:
2088 pm_runtime_disable(i2c_dev->dev);
2089
2090 tegra_i2c_release_dma(i2c_dev);
2091 release_clocks:
2092 tegra_i2c_release_clocks(i2c_dev);
2093
2094 return err;
2095 }
2096
tegra_i2c_remove(struct platform_device * pdev)2097 static void tegra_i2c_remove(struct platform_device *pdev)
2098 {
2099 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2100
2101 i2c_del_adapter(&i2c_dev->adapter);
2102 pm_runtime_force_suspend(i2c_dev->dev);
2103
2104 tegra_i2c_release_dma(i2c_dev);
2105 tegra_i2c_release_clocks(i2c_dev);
2106 }
2107
tegra_i2c_runtime_resume(struct device * dev)2108 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
2109 {
2110 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2111 int err;
2112
2113 err = pinctrl_pm_select_default_state(dev);
2114 if (err)
2115 return err;
2116
2117 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
2118 if (err)
2119 return err;
2120
2121 /*
2122 * VI I2C device is attached to VE power domain which goes through
2123 * power ON/OFF during runtime PM resume/suspend, meaning that
2124 * controller needs to be re-initialized after power ON.
2125 */
2126 if (IS_VI(i2c_dev)) {
2127 err = tegra_i2c_init(i2c_dev);
2128 if (err)
2129 goto disable_clocks;
2130 }
2131
2132 return 0;
2133
2134 disable_clocks:
2135 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
2136
2137 return err;
2138 }
2139
tegra_i2c_runtime_suspend(struct device * dev)2140 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
2141 {
2142 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2143
2144 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
2145
2146 return pinctrl_pm_select_idle_state(dev);
2147 }
2148
tegra_i2c_suspend(struct device * dev)2149 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
2150 {
2151 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2152 int err;
2153
2154 i2c_mark_adapter_suspended(&i2c_dev->adapter);
2155
2156 if (!pm_runtime_status_suspended(dev)) {
2157 err = tegra_i2c_runtime_suspend(dev);
2158 if (err)
2159 return err;
2160 }
2161
2162 return 0;
2163 }
2164
tegra_i2c_resume(struct device * dev)2165 static int __maybe_unused tegra_i2c_resume(struct device *dev)
2166 {
2167 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2168 int err;
2169
2170 /*
2171 * We need to ensure that clocks are enabled so that registers can be
2172 * restored in tegra_i2c_init().
2173 */
2174 err = tegra_i2c_runtime_resume(dev);
2175 if (err)
2176 return err;
2177
2178 err = tegra_i2c_init(i2c_dev);
2179 if (err)
2180 return err;
2181
2182 /*
2183 * In case we are runtime suspended, disable clocks again so that we
2184 * don't unbalance the clock reference counts during the next runtime
2185 * resume transition.
2186 */
2187 if (pm_runtime_status_suspended(dev)) {
2188 err = tegra_i2c_runtime_suspend(dev);
2189 if (err)
2190 return err;
2191 }
2192
2193 i2c_mark_adapter_resumed(&i2c_dev->adapter);
2194
2195 return 0;
2196 }
2197
2198 static const struct dev_pm_ops tegra_i2c_pm = {
2199 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
2200 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
2201 NULL)
2202 };
2203
2204 static const struct acpi_device_id tegra_i2c_acpi_match[] = {
2205 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw},
2206 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw},
2207 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw},
2208 { }
2209 };
2210 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);
2211
2212 static struct platform_driver tegra_i2c_driver = {
2213 .probe = tegra_i2c_probe,
2214 .remove = tegra_i2c_remove,
2215 .driver = {
2216 .name = "tegra-i2c",
2217 .of_match_table = tegra_i2c_of_match,
2218 .acpi_match_table = tegra_i2c_acpi_match,
2219 .pm = &tegra_i2c_pm,
2220 },
2221 };
2222 module_platform_driver(tegra_i2c_driver);
2223
2224 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
2225 MODULE_AUTHOR("Colin Cross");
2226 MODULE_LICENSE("GPL v2");
2227