xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h (revision ba23adb6533149df33b9a247f31a87227b3c86d5)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef _DPU_HW_DSPP_H
6 #define _DPU_HW_DSPP_H
7 
8 struct dpu_hw_dspp;
9 
10 /**
11  * struct dpu_hw_pcc_coeff - PCC coefficient structure for each color
12  *                            component.
13  * @r: red coefficient.
14  * @g: green coefficient.
15  * @b: blue coefficient.
16  */
17 
18 struct dpu_hw_pcc_coeff {
19 	__u32 r;
20 	__u32 g;
21 	__u32 b;
22 };
23 
24 /**
25  * struct dpu_hw_pcc_cfg - pcc feature structure
26  * @r: red coefficients.
27  * @g: green coefficients.
28  * @b: blue coefficients.
29  */
30 struct dpu_hw_pcc_cfg {
31 	struct dpu_hw_pcc_coeff r;
32 	struct dpu_hw_pcc_coeff g;
33 	struct dpu_hw_pcc_coeff b;
34 };
35 
36 #define DPU_GAMMA_LUT_SIZE 1024
37 #define PGC_TBL_LEN 512
38 #define PGC_8B_ROUND BIT(0)
39 
40 /**
41  * struct dpu_hw_gc_lut - gc lut feature structure
42  * @flags: flags for the feature values can be:
43  *         - PGC_8B_ROUND
44  * @c0: color0 component lut
45  * @c1: color1 component lut
46  * @c2: color2 component lut
47  */
48 struct dpu_hw_gc_lut {
49 	__u64 flags;
50 	__u32 c0[PGC_TBL_LEN];
51 	__u32 c1[PGC_TBL_LEN];
52 	__u32 c2[PGC_TBL_LEN];
53 };
54 
55 /**
56  * struct dpu_hw_dspp_ops - interface to the dspp hardware driver functions
57  * Caller must call the init function to get the dspp context for each dspp
58  * Assumption is these functions will be called after clocks are enabled
59  */
60 struct dpu_hw_dspp_ops {
61 	/**
62 	 * @setup_pcc: setup_pcc - setup dspp pcc
63 	 * @ctx: Pointer to dspp context
64 	 * @cfg: Pointer to configuration
65 	 */
66 	void (*setup_pcc)(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg);
67 
68 	/**
69 	 * setup_gc - setup dspp gc
70 	 * @ctx: Pointer to dspp context
71 	 * @gc_lut: Pointer to lut content
72 	 */
73 	void (*setup_gc)(struct dpu_hw_dspp *ctx, struct dpu_hw_gc_lut *gc_lut);
74 
75 };
76 
77 /**
78  * struct dpu_hw_dspp - dspp description
79  * @base: Hardware block base structure
80  * @hw: Block hardware details
81  * @idx: DSPP index
82  * @cap: Pointer to layer_cfg
83  * @ops: Pointer to operations possible for this DSPP
84  */
85 struct dpu_hw_dspp {
86 	struct dpu_hw_blk base;
87 	struct dpu_hw_blk_reg_map hw;
88 
89 	/* dspp */
90 	int idx;
91 	const struct dpu_dspp_cfg *cap;
92 
93 	/* Ops */
94 	struct dpu_hw_dspp_ops ops;
95 };
96 
97 /**
98  * to_dpu_hw_dspp - convert base object dpu_hw_base to container
99  * @hw: Pointer to base hardware block
100  * return: Pointer to hardware block container
101  */
to_dpu_hw_dspp(struct dpu_hw_blk * hw)102 static inline struct dpu_hw_dspp *to_dpu_hw_dspp(struct dpu_hw_blk *hw)
103 {
104 	return container_of(hw, struct dpu_hw_dspp, base);
105 }
106 
107 struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,
108 				     const struct dpu_dspp_cfg *cfg,
109 				     void __iomem *addr);
110 
111 #endif /*_DPU_HW_DSPP_H */
112 
113