1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/cacheinfo.h>
15 #include <linux/debugfs.h>
16 #include <linux/kvm_host.h>
17 #include <linux/mm.h>
18 #include <linux/printk.h>
19 #include <linux/uaccess.h>
20 #include <linux/irqchip/arm-gic-v3.h>
21
22 #include <asm/arm_pmuv3.h>
23 #include <asm/cacheflush.h>
24 #include <asm/cputype.h>
25 #include <asm/debug-monitors.h>
26 #include <asm/esr.h>
27 #include <asm/kvm_arm.h>
28 #include <asm/kvm_emulate.h>
29 #include <asm/kvm_hyp.h>
30 #include <asm/kvm_mmu.h>
31 #include <asm/kvm_nested.h>
32 #include <asm/perf_event.h>
33 #include <asm/sysreg.h>
34
35 #include <trace/events/kvm.h>
36
37 #include "sys_regs.h"
38 #include "vgic/vgic.h"
39
40 #include "trace.h"
41
42 /*
43 * For AArch32, we only take care of what is being trapped. Anything
44 * that has to do with init and userspace access has to go via the
45 * 64bit interface.
46 */
47
48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
50 u64 val);
51
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
53 const struct sys_reg_desc *r)
54 {
55 kvm_inject_undefined(vcpu);
56 return false;
57 }
58
bad_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r,const char * msg)59 static bool bad_trap(struct kvm_vcpu *vcpu,
60 struct sys_reg_params *params,
61 const struct sys_reg_desc *r,
62 const char *msg)
63 {
64 WARN_ONCE(1, "Unexpected %s\n", msg);
65 print_sys_reg_instr(params);
66 return undef_access(vcpu, params, r);
67 }
68
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)69 static bool read_from_write_only(struct kvm_vcpu *vcpu,
70 struct sys_reg_params *params,
71 const struct sys_reg_desc *r)
72 {
73 return bad_trap(vcpu, params, r,
74 "sys_reg read to write-only register");
75 }
76
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)77 static bool write_to_read_only(struct kvm_vcpu *vcpu,
78 struct sys_reg_params *params,
79 const struct sys_reg_desc *r)
80 {
81 return bad_trap(vcpu, params, r,
82 "sys_reg write to read-only register");
83 }
84
85 enum sr_loc_attr {
86 SR_LOC_MEMORY = 0, /* Register definitely in memory */
87 SR_LOC_LOADED = BIT(0), /* Register on CPU, unless it cannot */
88 SR_LOC_MAPPED = BIT(1), /* Register in a different CPU register */
89 SR_LOC_XLATED = BIT(2), /* Register translated to fit another reg */
90 SR_LOC_SPECIAL = BIT(3), /* Demanding register, implies loaded */
91 };
92
93 struct sr_loc {
94 enum sr_loc_attr loc;
95 enum vcpu_sysreg map_reg;
96 u64 (*xlate)(u64);
97 };
98
locate_direct_register(const struct kvm_vcpu * vcpu,enum vcpu_sysreg reg)99 static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu,
100 enum vcpu_sysreg reg)
101 {
102 switch (reg) {
103 case SCTLR_EL1:
104 case CPACR_EL1:
105 case TTBR0_EL1:
106 case TTBR1_EL1:
107 case TCR_EL1:
108 case TCR2_EL1:
109 case PIR_EL1:
110 case PIRE0_EL1:
111 case POR_EL1:
112 case ESR_EL1:
113 case AFSR0_EL1:
114 case AFSR1_EL1:
115 case FAR_EL1:
116 case MAIR_EL1:
117 case VBAR_EL1:
118 case CONTEXTIDR_EL1:
119 case AMAIR_EL1:
120 case CNTKCTL_EL1:
121 case ELR_EL1:
122 case SPSR_EL1:
123 case ZCR_EL1:
124 case SCTLR2_EL1:
125 /*
126 * EL1 registers which have an ELx2 mapping are loaded if
127 * we're not in hypervisor context.
128 */
129 return is_hyp_ctxt(vcpu) ? SR_LOC_MEMORY : SR_LOC_LOADED;
130
131 case TPIDR_EL0:
132 case TPIDRRO_EL0:
133 case TPIDR_EL1:
134 case PAR_EL1:
135 case DACR32_EL2:
136 case IFSR32_EL2:
137 case DBGVCR32_EL2:
138 /* These registers are always loaded, no matter what */
139 return SR_LOC_LOADED;
140
141 default:
142 /* Non-mapped EL2 registers are by definition in memory. */
143 return SR_LOC_MEMORY;
144 }
145 }
146
locate_mapped_el2_register(const struct kvm_vcpu * vcpu,enum vcpu_sysreg reg,enum vcpu_sysreg map_reg,u64 (* xlate)(u64),struct sr_loc * loc)147 static void locate_mapped_el2_register(const struct kvm_vcpu *vcpu,
148 enum vcpu_sysreg reg,
149 enum vcpu_sysreg map_reg,
150 u64 (*xlate)(u64),
151 struct sr_loc *loc)
152 {
153 if (!is_hyp_ctxt(vcpu)) {
154 loc->loc = SR_LOC_MEMORY;
155 return;
156 }
157
158 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED;
159 loc->map_reg = map_reg;
160
161 WARN_ON(locate_direct_register(vcpu, map_reg) != SR_LOC_MEMORY);
162
163 if (xlate != NULL && !vcpu_el2_e2h_is_set(vcpu)) {
164 loc->loc |= SR_LOC_XLATED;
165 loc->xlate = xlate;
166 }
167 }
168
169 #define MAPPED_EL2_SYSREG(r, m, t) \
170 case r: { \
171 locate_mapped_el2_register(vcpu, r, m, t, loc); \
172 break; \
173 }
174
locate_register(const struct kvm_vcpu * vcpu,enum vcpu_sysreg reg,struct sr_loc * loc)175 static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg,
176 struct sr_loc *loc)
177 {
178 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) {
179 loc->loc = SR_LOC_MEMORY;
180 return;
181 }
182
183 switch (reg) {
184 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1,
185 translate_sctlr_el2_to_sctlr_el1 );
186 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1,
187 translate_ttbr0_el2_to_ttbr0_el1 );
188 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL );
189 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1,
190 translate_tcr_el2_to_tcr_el1 );
191 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL );
192 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL );
193 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL );
194 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL );
195 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL );
196 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL );
197 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL );
198 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL );
199 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL );
200 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL );
201 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL );
202 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL );
203 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL );
204 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL );
205 MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL );
206 case CNTHCTL_EL2:
207 /* CNTHCTL_EL2 is super special, until we support NV2.1 */
208 loc->loc = ((is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) ?
209 SR_LOC_SPECIAL : SR_LOC_MEMORY);
210 break;
211 case CPTR_EL2:
212 /*
213 * CPTR_EL2 is just as special, and needs a certain amount
214 * of handholding. It always lives in memory, due to being
215 * heavily trapped thanks to CPACR_EL1.TCPAC being RES0.
216 * FEAT_NV2p1 fixes this.
217 */
218 locate_mapped_el2_register(vcpu, CPTR_EL2, CPACR_EL1,
219 translate_cptr_el2_to_cpacr_el1,
220 loc);
221 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
222 loc->loc = SR_LOC_SPECIAL;
223 break;
224 case NVHCR_EL2:
225 /*
226 * Yes, NVHCR_EL2 maps to itself when loaded in nested
227 * context. If you feel like the architecture is double
228 * backing on itself upside down, you're not alone.
229 */
230 WARN_ON_ONCE(!kvm_has_nv3(vcpu->kvm));
231 if (is_hyp_ctxt(vcpu)) {
232 loc->loc = SR_LOC_MEMORY;
233 } else {
234 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED;
235 loc->map_reg = NVHCR_EL2;
236 }
237 break;
238 default:
239 loc->loc = locate_direct_register(vcpu, reg);
240 }
241 }
242
read_sr_from_cpu(enum vcpu_sysreg reg)243 static u64 read_sr_from_cpu(enum vcpu_sysreg reg)
244 {
245 u64 val = 0x8badf00d8badf00d;
246
247 switch (reg) {
248 case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break;
249 case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break;
250 case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break;
251 case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break;
252 case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break;
253 case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break;
254 case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break;
255 case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break;
256 case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break;
257 case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break;
258 case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break;
259 case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break;
260 case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break;
261 case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break;
262 case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break;
263 case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
264 case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break;
265 case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
266 case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break;
267 case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break;
268 case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break;
269 case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break;
270 case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break;
271 case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
272 case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break;
273 case PAR_EL1: val = read_sysreg_par(); break;
274 case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break;
275 case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break;
276 case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
277 case NVHCR_EL2: val = read_sysreg_s(SYS_NVHCR_EL2); break;
278 default: WARN_ON_ONCE(1);
279 }
280
281 return val;
282 }
283
write_sr_to_cpu(enum vcpu_sysreg reg,u64 val)284 static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val)
285 {
286 switch (reg) {
287 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
288 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
289 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
290 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
291 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
292 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
293 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
294 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
295 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
296 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
297 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
298 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
299 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
300 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
301 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
302 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
303 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
304 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
305 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
306 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
307 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
308 case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
309 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
310 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
311 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
312 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
313 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
314 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
315 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
316 case NVHCR_EL2: write_sysreg_s(val, SYS_NVHCR_EL2); break;
317 default: WARN_ON_ONCE(1);
318 }
319 }
320
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,enum vcpu_sysreg reg)321 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
322 {
323 struct sr_loc loc = {};
324
325 locate_register(vcpu, reg, &loc);
326
327 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY);
328
329 if (loc.loc & SR_LOC_SPECIAL) {
330 u64 val;
331
332 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL);
333
334 /*
335 * CNTHCTL_EL2 requires some special treatment to account
336 * for the bits that can be set via CNTKCTL_EL1 when E2H==1.
337 */
338 switch (reg) {
339 case CNTHCTL_EL2:
340 val = read_sysreg_el1(SYS_CNTKCTL);
341 if (!cpus_have_final_cap(ARM64_HAS_NV2P1)) {
342 val &= CNTKCTL_VALID_BITS;
343 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS;
344 }
345 return val;
346 case CPTR_EL2:
347 if (cpus_have_final_cap(ARM64_HAS_NV2P1))
348 return read_sysreg_el1(SYS_CPACR);
349 else
350 return __vcpu_sys_reg(vcpu, reg);
351 default:
352 WARN_ON_ONCE(1);
353 }
354 }
355
356 if (loc.loc & SR_LOC_LOADED) {
357 enum vcpu_sysreg map_reg = reg;
358
359 if (loc.loc & SR_LOC_MAPPED)
360 map_reg = loc.map_reg;
361
362 if (!(loc.loc & SR_LOC_XLATED)) {
363 u64 val = read_sr_from_cpu(map_reg);
364
365 if (reg >= __SANITISED_REG_START__)
366 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
367
368 return val;
369 }
370 }
371
372 return __vcpu_sys_reg(vcpu, reg);
373 }
374
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,enum vcpu_sysreg reg)375 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg)
376 {
377 struct sr_loc loc = {};
378
379 locate_register(vcpu, reg, &loc);
380
381 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY);
382
383 if (loc.loc & SR_LOC_SPECIAL) {
384
385 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL);
386
387 switch (reg) {
388 case CNTHCTL_EL2:
389 /*
390 * If E2H=1, some of the bits are backed by
391 * CNTKCTL_EL1, while the rest is kept in memory.
392 * Yes, this is fun stuff.
393 */
394 write_sysreg_el1(val, SYS_CNTKCTL);
395 break;
396 case CPTR_EL2:
397 write_sysreg_el1(val, SYS_CPACR);
398 break;
399 default:
400 WARN_ON_ONCE(1);
401 }
402 }
403
404 if (loc.loc & SR_LOC_LOADED) {
405 enum vcpu_sysreg map_reg = reg;
406 u64 xlated_val;
407
408 if (reg >= __SANITISED_REG_START__)
409 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
410
411 if (loc.loc & SR_LOC_MAPPED)
412 map_reg = loc.map_reg;
413
414 if (loc.loc & SR_LOC_XLATED)
415 xlated_val = loc.xlate(val);
416 else
417 xlated_val = val;
418
419 write_sr_to_cpu(map_reg, xlated_val);
420
421 /*
422 * Fall through to write the backing store anyway, which
423 * allows translated registers to be directly read without a
424 * reverse translation.
425 */
426 }
427
428 __vcpu_assign_sys_reg(vcpu, reg, val);
429 }
430
431 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
432 #define CSSELR_MAX 14
433
434 /*
435 * Returns the minimum line size for the selected cache, expressed as
436 * Log2(bytes).
437 */
get_min_cache_line_size(bool icache)438 static u8 get_min_cache_line_size(bool icache)
439 {
440 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
441 u8 field;
442
443 if (icache)
444 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
445 else
446 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
447
448 /*
449 * Cache line size is represented as Log2(words) in CTR_EL0.
450 * Log2(bytes) can be derived with the following:
451 *
452 * Log2(words) + 2 = Log2(bytes / 4) + 2
453 * = Log2(bytes) - 2 + 2
454 * = Log2(bytes)
455 */
456 return field + 2;
457 }
458
459 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(struct kvm_vcpu * vcpu,u32 csselr)460 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
461 {
462 u8 line_size;
463
464 if (vcpu->arch.ccsidr)
465 return vcpu->arch.ccsidr[csselr];
466
467 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
468
469 /*
470 * Fabricate a CCSIDR value as the overriding value does not exist.
471 * The real CCSIDR value will not be used as it can vary by the
472 * physical CPU which the vcpu currently resides in.
473 *
474 * The line size is determined with get_min_cache_line_size(), which
475 * should be valid for all CPUs even if they have different cache
476 * configuration.
477 *
478 * The associativity bits are cleared, meaning the geometry of all data
479 * and unified caches (which are guaranteed to be PIPT and thus
480 * non-aliasing) are 1 set and 1 way.
481 * Guests should not be doing cache operations by set/way at all, and
482 * for this reason, we trap them and attempt to infer the intent, so
483 * that we can flush the entire guest's address space at the appropriate
484 * time. The exposed geometry minimizes the number of the traps.
485 * [If guests should attempt to infer aliasing properties from the
486 * geometry (which is not permitted by the architecture), they would
487 * only do so for virtually indexed caches.]
488 *
489 * We don't check if the cache level exists as it is allowed to return
490 * an UNKNOWN value if not.
491 */
492 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
493 }
494
set_ccsidr(struct kvm_vcpu * vcpu,u32 csselr,u32 val)495 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
496 {
497 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
498 u32 *ccsidr = vcpu->arch.ccsidr;
499 u32 i;
500
501 if ((val & CCSIDR_EL1_RES0) ||
502 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
503 return -EINVAL;
504
505 if (!ccsidr) {
506 if (val == get_ccsidr(vcpu, csselr))
507 return 0;
508
509 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
510 if (!ccsidr)
511 return -ENOMEM;
512
513 for (i = 0; i < CSSELR_MAX; i++)
514 ccsidr[i] = get_ccsidr(vcpu, i);
515
516 vcpu->arch.ccsidr = ccsidr;
517 }
518
519 ccsidr[csselr] = val;
520
521 return 0;
522 }
523
access_rw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)524 static bool access_rw(struct kvm_vcpu *vcpu,
525 struct sys_reg_params *p,
526 const struct sys_reg_desc *r)
527 {
528 if (p->is_write)
529 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
530 else
531 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
532
533 return true;
534 }
535
536 /*
537 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
538 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)539 static bool access_dcsw(struct kvm_vcpu *vcpu,
540 struct sys_reg_params *p,
541 const struct sys_reg_desc *r)
542 {
543 if (!p->is_write)
544 return read_from_write_only(vcpu, p, r);
545
546 /*
547 * Only track S/W ops if we don't have FWB. It still indicates
548 * that the guest is a bit broken (S/W operations should only
549 * be done by firmware, knowing that there is only a single
550 * CPU left in the system, and certainly not from non-secure
551 * software).
552 */
553 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
554 kvm_set_way_flush(vcpu);
555
556 return true;
557 }
558
access_dcgsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)559 static bool access_dcgsw(struct kvm_vcpu *vcpu,
560 struct sys_reg_params *p,
561 const struct sys_reg_desc *r)
562 {
563 if (!kvm_has_mte(vcpu->kvm))
564 return undef_access(vcpu, p, r);
565
566 /* Treat MTE S/W ops as we treat the classic ones: with contempt */
567 return access_dcsw(vcpu, p, r);
568 }
569
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)570 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
571 {
572 switch (r->aarch32_map) {
573 case AA32_LO:
574 *mask = GENMASK_ULL(31, 0);
575 *shift = 0;
576 break;
577 case AA32_HI:
578 *mask = GENMASK_ULL(63, 32);
579 *shift = 32;
580 break;
581 default:
582 *mask = GENMASK_ULL(63, 0);
583 *shift = 0;
584 break;
585 }
586 }
587
588 /*
589 * Generic accessor for VM registers. Only called as long as HCR_TVM
590 * is set. If the guest enables the MMU, we stop trapping the VM
591 * sys_regs and leave it in complete control of the caches.
592 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)593 static bool access_vm_reg(struct kvm_vcpu *vcpu,
594 struct sys_reg_params *p,
595 const struct sys_reg_desc *r)
596 {
597 bool was_enabled = vcpu_has_cache_enabled(vcpu);
598 u64 val, mask, shift;
599
600 BUG_ON(!p->is_write);
601
602 get_access_mask(r, &mask, &shift);
603
604 if (~mask) {
605 val = vcpu_read_sys_reg(vcpu, r->reg);
606 val &= ~mask;
607 } else {
608 val = 0;
609 }
610
611 val |= (p->regval & (mask >> shift)) << shift;
612 vcpu_write_sys_reg(vcpu, val, r->reg);
613
614 kvm_toggle_cache(vcpu, was_enabled);
615 return true;
616 }
617
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)618 static bool access_actlr(struct kvm_vcpu *vcpu,
619 struct sys_reg_params *p,
620 const struct sys_reg_desc *r)
621 {
622 u64 mask, shift;
623
624 if (p->is_write)
625 return ignore_write(vcpu, p);
626
627 get_access_mask(r, &mask, &shift);
628 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
629
630 return true;
631 }
632
633 /*
634 * Trap handler for the GICv3 SGI generation system register.
635 * Forward the request to the VGIC emulation.
636 * The cp15_64 code makes sure this automatically works
637 * for both AArch64 and AArch32 accesses.
638 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)639 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
640 struct sys_reg_params *p,
641 const struct sys_reg_desc *r)
642 {
643 bool g1;
644
645 if (!kvm_has_gicv3(vcpu->kvm))
646 return undef_access(vcpu, p, r);
647
648 if (!p->is_write)
649 return read_from_write_only(vcpu, p, r);
650
651 /*
652 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
653 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
654 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
655 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
656 * group.
657 */
658 if (p->Op0 == 0) { /* AArch32 */
659 switch (p->Op1) {
660 default: /* Keep GCC quiet */
661 case 0: /* ICC_SGI1R */
662 g1 = true;
663 break;
664 case 1: /* ICC_ASGI1R */
665 case 2: /* ICC_SGI0R */
666 g1 = false;
667 break;
668 }
669 } else { /* AArch64 */
670 switch (p->Op2) {
671 default: /* Keep GCC quiet */
672 case 5: /* ICC_SGI1R_EL1 */
673 g1 = true;
674 break;
675 case 6: /* ICC_ASGI1R_EL1 */
676 case 7: /* ICC_SGI0R_EL1 */
677 g1 = false;
678 break;
679 }
680 }
681
682 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
683
684 return true;
685 }
686
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)687 static bool access_gic_sre(struct kvm_vcpu *vcpu,
688 struct sys_reg_params *p,
689 const struct sys_reg_desc *r)
690 {
691 if (!kvm_has_gicv3(vcpu->kvm))
692 return undef_access(vcpu, p, r);
693
694 if (p->is_write)
695 return ignore_write(vcpu, p);
696
697 if (p->Op1 == 4) { /* ICC_SRE_EL2 */
698 p->regval = KVM_ICC_SRE_EL2;
699 } else { /* ICC_SRE_EL1 */
700 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
701 }
702
703 return true;
704 }
705
access_gic_dir(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)706 static bool access_gic_dir(struct kvm_vcpu *vcpu,
707 struct sys_reg_params *p,
708 const struct sys_reg_desc *r)
709 {
710 if (!kvm_has_gicv3(vcpu->kvm))
711 return undef_access(vcpu, p, r);
712
713 if (!p->is_write)
714 return undef_access(vcpu, p, r);
715
716 vgic_v3_deactivate(vcpu, p->regval);
717
718 return true;
719 }
720
access_gicv5_idr0(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)721 static bool access_gicv5_idr0(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
722 const struct sys_reg_desc *r)
723 {
724 if (p->is_write)
725 return undef_access(vcpu, p, r);
726
727 /*
728 * Expose KVM's priority- and ID-bits to the guest, but not GCIE_LEGACY.
729 *
730 * Note: for GICv5 the mimic the way that the num_pri_bits and
731 * num_id_bits fields are used with GICv3:
732 * - num_pri_bits stores the actual number of priority bits, whereas the
733 * register field stores num_pri_bits - 1.
734 * - num_id_bits stores the raw field value, which is 0b0000 for 16 bits
735 * and 0b0001 for 24 bits.
736 */
737 p->regval = FIELD_PREP(ICC_IDR0_EL1_PRI_BITS, vcpu->arch.vgic_cpu.num_pri_bits - 1) |
738 FIELD_PREP(ICC_IDR0_EL1_ID_BITS, vcpu->arch.vgic_cpu.num_id_bits);
739
740 return true;
741 }
742
access_gicv5_iaffid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)743 static bool access_gicv5_iaffid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
744 const struct sys_reg_desc *r)
745 {
746 if (p->is_write)
747 return undef_access(vcpu, p, r);
748
749 /*
750 * For GICv5 VMs, the IAFFID value is the same as the VPE ID. The VPE ID
751 * is the same as the VCPU's ID.
752 */
753 p->regval = FIELD_PREP(ICC_IAFFIDR_EL1_IAFFID, vcpu->vcpu_id);
754
755 return true;
756 }
757
access_gicv5_ppi_enabler(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)758 static bool access_gicv5_ppi_enabler(struct kvm_vcpu *vcpu,
759 struct sys_reg_params *p,
760 const struct sys_reg_desc *r)
761 {
762 unsigned long *mask = vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask;
763 struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
764 unsigned long reg = p->regval;
765 int i;
766
767 /* We never expect to get here with a read! */
768 if (WARN_ON_ONCE(!p->is_write))
769 return undef_access(vcpu, p, r);
770
771 /*
772 * As we're only handling architected PPIs, the guest writes to the
773 * enable for the non-architected PPIs just return as there's
774 * nothing to do at all. We don't even allocate the storage for them.
775 */
776 if (p->Op2 % 2)
777 return true;
778
779 /*
780 * Merge the raw guest write into out bitmap, anded with our PPI mask.
781 */
782 bitmap_and(cpu_if->vgic_ppi_enabler, ®, mask, VGIC_V5_NR_PRIVATE_IRQS);
783
784 /*
785 * Sync the change in enable states to the vgic_irqs. We consider all
786 * PPIs as we don't expose many to the guest.
787 */
788 for_each_visible_v5_ppi(i, vcpu->kvm) {
789 u32 intid = vgic_v5_make_ppi(i);
790 struct vgic_irq *irq;
791
792 irq = vgic_get_vcpu_irq(vcpu, intid);
793
794 scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
795 irq->enabled = test_bit(i, cpu_if->vgic_ppi_enabler);
796
797 vgic_put_irq(vcpu->kvm, irq);
798 }
799
800 return true;
801 }
802
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)803 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
804 struct sys_reg_params *p,
805 const struct sys_reg_desc *r)
806 {
807 if (p->is_write)
808 return ignore_write(vcpu, p);
809 else
810 return read_zero(vcpu, p);
811 }
812
813 /*
814 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
815 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
816 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
817 * treat it separately.
818 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)819 static bool trap_loregion(struct kvm_vcpu *vcpu,
820 struct sys_reg_params *p,
821 const struct sys_reg_desc *r)
822 {
823 u32 sr = reg_to_encoding(r);
824
825 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP))
826 return undef_access(vcpu, p, r);
827
828 if (p->is_write && sr == SYS_LORID_EL1)
829 return write_to_read_only(vcpu, p, r);
830
831 return trap_raz_wi(vcpu, p, r);
832 }
833
trap_oslar_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)834 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
835 struct sys_reg_params *p,
836 const struct sys_reg_desc *r)
837 {
838 if (!p->is_write)
839 return read_from_write_only(vcpu, p, r);
840
841 kvm_debug_handle_oslar(vcpu, p->regval);
842 return true;
843 }
844
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)845 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
846 struct sys_reg_params *p,
847 const struct sys_reg_desc *r)
848 {
849 if (p->is_write)
850 return write_to_read_only(vcpu, p, r);
851
852 p->regval = __vcpu_sys_reg(vcpu, r->reg);
853 return true;
854 }
855
set_oslsr_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)856 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
857 u64 val)
858 {
859 /*
860 * The only modifiable bit is the OSLK bit. Refuse the write if
861 * userspace attempts to change any other bit in the register.
862 */
863 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
864 return -EINVAL;
865
866 __vcpu_assign_sys_reg(vcpu, rd->reg, val);
867 return 0;
868 }
869
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)870 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
871 struct sys_reg_params *p,
872 const struct sys_reg_desc *r)
873 {
874 if (p->is_write) {
875 return ignore_write(vcpu, p);
876 } else {
877 p->regval = read_sysreg(dbgauthstatus_el1);
878 return true;
879 }
880 }
881
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)882 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
883 struct sys_reg_params *p,
884 const struct sys_reg_desc *r)
885 {
886 access_rw(vcpu, p, r);
887
888 kvm_debug_set_guest_ownership(vcpu);
889 return true;
890 }
891
892 /*
893 * reg_to_dbg/dbg_to_reg
894 *
895 * A 32 bit write to a debug register leave top bits alone
896 * A 32 bit read from a debug register only returns the bottom bits
897 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)898 static void reg_to_dbg(struct kvm_vcpu *vcpu,
899 struct sys_reg_params *p,
900 const struct sys_reg_desc *rd,
901 u64 *dbg_reg)
902 {
903 u64 mask, shift, val;
904
905 get_access_mask(rd, &mask, &shift);
906
907 val = *dbg_reg;
908 val &= ~mask;
909 val |= (p->regval & (mask >> shift)) << shift;
910 *dbg_reg = val;
911 }
912
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)913 static void dbg_to_reg(struct kvm_vcpu *vcpu,
914 struct sys_reg_params *p,
915 const struct sys_reg_desc *rd,
916 u64 *dbg_reg)
917 {
918 u64 mask, shift;
919
920 get_access_mask(rd, &mask, &shift);
921 p->regval = (*dbg_reg & mask) >> shift;
922 }
923
demux_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)924 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
925 {
926 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state;
927
928 switch (rd->Op2) {
929 case 0b001:
930 case 0b100:
931 return &dbg->dbg_bvr[rd->CRm];
932 case 0b101:
933 return &dbg->dbg_bcr[rd->CRm];
934 case 0b110:
935 return &dbg->dbg_wvr[rd->CRm];
936 case 0b111:
937 return &dbg->dbg_wcr[rd->CRm];
938 default:
939 KVM_BUG_ON(1, vcpu->kvm);
940 return NULL;
941 }
942 }
943
trap_dbg_wb_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)944 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
945 const struct sys_reg_desc *rd)
946 {
947 u64 *reg = demux_wb_reg(vcpu, rd);
948
949 if (!reg)
950 return false;
951
952 if (p->is_write)
953 reg_to_dbg(vcpu, p, rd, reg);
954 else
955 dbg_to_reg(vcpu, p, rd, reg);
956
957 kvm_debug_set_guest_ownership(vcpu);
958 return true;
959 }
960
set_dbg_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)961 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
962 u64 val)
963 {
964 u64 *reg = demux_wb_reg(vcpu, rd);
965
966 if (!reg)
967 return -EINVAL;
968
969 *reg = val;
970 return 0;
971 }
972
get_dbg_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)973 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
974 u64 *val)
975 {
976 u64 *reg = demux_wb_reg(vcpu, rd);
977
978 if (!reg)
979 return -EINVAL;
980
981 *val = *reg;
982 return 0;
983 }
984
reset_dbg_wb_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)985 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)
986 {
987 u64 *reg = demux_wb_reg(vcpu, rd);
988
989 /*
990 * Bail early if we couldn't find storage for the register, the
991 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever
992 * being run.
993 */
994 if (!reg)
995 return 0;
996
997 *reg = rd->val;
998 return rd->val;
999 }
1000
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1001 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1002 {
1003 u64 amair = read_sysreg(amair_el1);
1004 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
1005 return amair;
1006 }
1007
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1008 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1009 {
1010 u64 actlr = read_sysreg(actlr_el1);
1011 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
1012 return actlr;
1013 }
1014
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1015 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1016 {
1017 u64 mpidr = kvm_calculate_mpidr(vcpu);
1018
1019 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
1020 return mpidr;
1021 }
1022
hidden_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1023 static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu,
1024 const struct sys_reg_desc *r)
1025 {
1026 return REG_HIDDEN;
1027 }
1028
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1029 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
1030 const struct sys_reg_desc *r)
1031 {
1032 if (kvm_vcpu_has_pmu(vcpu))
1033 return 0;
1034
1035 return REG_HIDDEN;
1036 }
1037
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1038 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1039 {
1040 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX);
1041 u8 n = vcpu->kvm->arch.nr_pmu_counters;
1042
1043 if (n)
1044 mask |= GENMASK(n - 1, 0);
1045
1046 reset_unknown(vcpu, r);
1047 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, mask);
1048
1049 return __vcpu_sys_reg(vcpu, r->reg);
1050 }
1051
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1052 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1053 {
1054 reset_unknown(vcpu, r);
1055 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0));
1056
1057 return __vcpu_sys_reg(vcpu, r->reg);
1058 }
1059
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1060 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1061 {
1062 /* This thing will UNDEF, who cares about the reset value? */
1063 if (!kvm_vcpu_has_pmu(vcpu))
1064 return 0;
1065
1066 reset_unknown(vcpu, r);
1067 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, kvm_pmu_evtyper_mask(vcpu->kvm));
1068
1069 return __vcpu_sys_reg(vcpu, r->reg);
1070 }
1071
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1072 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1073 {
1074 reset_unknown(vcpu, r);
1075 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, PMSELR_EL0_SEL_MASK);
1076
1077 return __vcpu_sys_reg(vcpu, r->reg);
1078 }
1079
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1080 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1081 {
1082 u64 pmcr = 0;
1083
1084 if (!kvm_supports_32bit_el0())
1085 pmcr |= ARMV8_PMU_PMCR_LC;
1086
1087 /*
1088 * The value of PMCR.N field is included when the
1089 * vCPU register is read via kvm_vcpu_read_pmcr().
1090 */
1091 __vcpu_assign_sys_reg(vcpu, r->reg, pmcr);
1092
1093 return __vcpu_sys_reg(vcpu, r->reg);
1094 }
1095
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)1096 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
1097 {
1098 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
1099 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
1100
1101 if (!enabled)
1102 kvm_inject_undefined(vcpu);
1103
1104 return !enabled;
1105 }
1106
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)1107 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
1108 {
1109 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
1110 }
1111
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)1112 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
1113 {
1114 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
1115 }
1116
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)1117 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
1118 {
1119 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
1120 }
1121
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)1122 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
1123 {
1124 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
1125 }
1126
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1127 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1128 const struct sys_reg_desc *r)
1129 {
1130 u64 val;
1131
1132 if (pmu_access_el0_disabled(vcpu))
1133 return false;
1134
1135 if (p->is_write) {
1136 /*
1137 * Only update writeable bits of PMCR (continuing into
1138 * kvm_pmu_handle_pmcr() as well)
1139 */
1140 val = kvm_vcpu_read_pmcr(vcpu);
1141 val &= ~ARMV8_PMU_PMCR_MASK;
1142 val |= p->regval & ARMV8_PMU_PMCR_MASK;
1143 if (!kvm_supports_32bit_el0())
1144 val |= ARMV8_PMU_PMCR_LC;
1145 kvm_pmu_handle_pmcr(vcpu, val);
1146 } else {
1147 /* PMCR.P & PMCR.C are RAZ */
1148 val = kvm_vcpu_read_pmcr(vcpu)
1149 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
1150 p->regval = val;
1151 }
1152
1153 return true;
1154 }
1155
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1156 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1157 const struct sys_reg_desc *r)
1158 {
1159 if (pmu_access_event_counter_el0_disabled(vcpu))
1160 return false;
1161
1162 if (p->is_write)
1163 __vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval);
1164 else
1165 /* return PMSELR.SEL field */
1166 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
1167 & PMSELR_EL0_SEL_MASK;
1168
1169 return true;
1170 }
1171
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1172 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1173 const struct sys_reg_desc *r)
1174 {
1175 u64 pmceid, mask, shift;
1176
1177 BUG_ON(p->is_write);
1178
1179 if (pmu_access_el0_disabled(vcpu))
1180 return false;
1181
1182 get_access_mask(r, &mask, &shift);
1183
1184 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
1185 pmceid &= mask;
1186 pmceid >>= shift;
1187
1188 p->regval = pmceid;
1189
1190 return true;
1191 }
1192
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)1193 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
1194 {
1195 u64 pmcr, val;
1196
1197 pmcr = kvm_vcpu_read_pmcr(vcpu);
1198 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr);
1199 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
1200 kvm_inject_undefined(vcpu);
1201 return false;
1202 }
1203
1204 return true;
1205 }
1206
get_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1207 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1208 u64 *val)
1209 {
1210 u64 idx;
1211
1212 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
1213 /* PMCCNTR_EL0 */
1214 idx = ARMV8_PMU_CYCLE_IDX;
1215 else
1216 /* PMEVCNTRn_EL0 */
1217 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1218
1219 *val = kvm_pmu_get_counter_value(vcpu, idx);
1220 return 0;
1221 }
1222
set_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1223 static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1224 u64 val)
1225 {
1226 u64 idx;
1227
1228 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
1229 /* PMCCNTR_EL0 */
1230 idx = ARMV8_PMU_CYCLE_IDX;
1231 else
1232 /* PMEVCNTRn_EL0 */
1233 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1234
1235 kvm_pmu_set_counter_value_user(vcpu, idx, val);
1236 return 0;
1237 }
1238
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1239 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
1240 struct sys_reg_params *p,
1241 const struct sys_reg_desc *r)
1242 {
1243 u64 idx = ~0UL;
1244
1245 if (r->CRn == 9 && r->CRm == 13) {
1246 if (r->Op2 == 2) {
1247 /* PMXEVCNTR_EL0 */
1248 if (pmu_access_event_counter_el0_disabled(vcpu))
1249 return false;
1250
1251 idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
1252 __vcpu_sys_reg(vcpu, PMSELR_EL0));
1253 } else if (r->Op2 == 0) {
1254 /* PMCCNTR_EL0 */
1255 if (pmu_access_cycle_counter_el0_disabled(vcpu))
1256 return false;
1257
1258 idx = ARMV8_PMU_CYCLE_IDX;
1259 }
1260 } else if (r->CRn == 0 && r->CRm == 9) {
1261 /* PMCCNTR */
1262 if (pmu_access_event_counter_el0_disabled(vcpu))
1263 return false;
1264
1265 idx = ARMV8_PMU_CYCLE_IDX;
1266 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
1267 /* PMEVCNTRn_EL0 */
1268 if (pmu_access_event_counter_el0_disabled(vcpu))
1269 return false;
1270
1271 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1272 }
1273
1274 /* Catch any decoding mistake */
1275 WARN_ON(idx == ~0UL);
1276
1277 if (!pmu_counter_idx_valid(vcpu, idx))
1278 return false;
1279
1280 if (p->is_write) {
1281 if (pmu_access_el0_disabled(vcpu))
1282 return false;
1283
1284 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
1285 } else {
1286 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
1287 }
1288
1289 return true;
1290 }
1291
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1292 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1293 const struct sys_reg_desc *r)
1294 {
1295 u64 idx, reg;
1296
1297 if (pmu_access_el0_disabled(vcpu))
1298 return false;
1299
1300 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
1301 /* PMXEVTYPER_EL0 */
1302 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
1303 reg = PMEVTYPER0_EL0 + idx;
1304 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
1305 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1306 if (idx == ARMV8_PMU_CYCLE_IDX)
1307 reg = PMCCFILTR_EL0;
1308 else
1309 /* PMEVTYPERn_EL0 */
1310 reg = PMEVTYPER0_EL0 + idx;
1311 } else {
1312 BUG();
1313 }
1314
1315 if (!pmu_counter_idx_valid(vcpu, idx))
1316 return false;
1317
1318 if (p->is_write) {
1319 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
1320 kvm_vcpu_pmu_restore_guest(vcpu);
1321 } else {
1322 p->regval = __vcpu_sys_reg(vcpu, reg);
1323 }
1324
1325 return true;
1326 }
1327
set_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1328 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
1329 {
1330 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1331
1332 __vcpu_assign_sys_reg(vcpu, r->reg, val & mask);
1333 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
1334
1335 return 0;
1336 }
1337
get_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1338 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
1339 {
1340 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1341
1342 *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
1343 return 0;
1344 }
1345
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1346 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1347 const struct sys_reg_desc *r)
1348 {
1349 u64 val, mask;
1350
1351 if (pmu_access_el0_disabled(vcpu))
1352 return false;
1353
1354 mask = kvm_pmu_accessible_counter_mask(vcpu);
1355 if (p->is_write) {
1356 val = p->regval & mask;
1357 if (r->Op2 & 0x1)
1358 /* accessing PMCNTENSET_EL0 */
1359 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, |=, val);
1360 else
1361 /* accessing PMCNTENCLR_EL0 */
1362 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, ~val);
1363
1364 kvm_pmu_reprogram_counter_mask(vcpu, val);
1365 } else {
1366 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
1367 }
1368
1369 return true;
1370 }
1371
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1372 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1373 const struct sys_reg_desc *r)
1374 {
1375 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1376
1377 if (check_pmu_access_disabled(vcpu, 0))
1378 return false;
1379
1380 if (p->is_write) {
1381 u64 val = p->regval & mask;
1382
1383 if (r->Op2 & 0x1)
1384 /* accessing PMINTENSET_EL1 */
1385 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, |=, val);
1386 else
1387 /* accessing PMINTENCLR_EL1 */
1388 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, ~val);
1389 } else {
1390 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
1391 }
1392
1393 return true;
1394 }
1395
access_pmmir(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1396 static bool access_pmmir(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1397 const struct sys_reg_desc *r)
1398 {
1399 if (p->is_write)
1400 return write_to_read_only(vcpu, p, r);
1401
1402 /*
1403 * If KVM_ARM_VCPU_PMU_V3_STRICT is set and PMU was explicitly
1404 * selected, the underlying hardware SLOTS value was read into this
1405 * field. Otherwise, it stays 0. All other PMMIR_EL1 fields are RAZ.
1406 */
1407 p->regval = FIELD_PREP(ARMV8_PMU_SLOTS, vcpu->kvm->arch.pmmir_slots);
1408 return true;
1409 }
1410
get_pmmir(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1411 static int get_pmmir(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1412 u64 *val)
1413 {
1414 *val = FIELD_PREP(ARMV8_PMU_SLOTS, vcpu->kvm->arch.pmmir_slots);
1415 return 0;
1416 }
1417
set_pmmir(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1418 static int set_pmmir(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1419 u64 val)
1420 {
1421 struct kvm *kvm = vcpu->kvm;
1422 u8 slots = FIELD_GET(ARMV8_PMU_SLOTS, val);
1423
1424 /*
1425 * Only the SLOTS field is exposed (get_pmmir returns just that field),
1426 * so reject a write that sets any other bit rather than silently
1427 * masking it.
1428 */
1429 if (val & ~(u64)ARMV8_PMU_SLOTS)
1430 return -EINVAL;
1431
1432 guard(mutex)(&kvm->arch.config_lock);
1433
1434 /*
1435 * Once the VM has started PMMIR_EL1 is immutable. Reject any write
1436 * that does not match the current value.
1437 */
1438 if (kvm_vm_has_ran_once(kvm))
1439 return slots == kvm->arch.pmmir_slots ? 0 : -EBUSY;
1440
1441 /*
1442 * Only SLOTS = 0 is honored for backwards compatibility with the
1443 * old RAZ behavior. Reject any non-zero write that does not match
1444 * the current value.
1445 */
1446 if (!slots)
1447 kvm->arch.pmmir_slots = 0;
1448 else if (slots != kvm->arch.pmmir_slots)
1449 return -EINVAL;
1450
1451 return 0;
1452 }
1453
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1454 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1455 const struct sys_reg_desc *r)
1456 {
1457 u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
1458
1459 if (pmu_access_el0_disabled(vcpu))
1460 return false;
1461
1462 if (p->is_write) {
1463 if (r->CRm & 0x2)
1464 /* accessing PMOVSSET_EL0 */
1465 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask));
1466 else
1467 /* accessing PMOVSCLR_EL0 */
1468 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask));
1469 } else {
1470 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
1471 }
1472
1473 return true;
1474 }
1475
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1476 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1477 const struct sys_reg_desc *r)
1478 {
1479 u64 mask;
1480
1481 if (!p->is_write)
1482 return read_from_write_only(vcpu, p, r);
1483
1484 if (pmu_write_swinc_el0_disabled(vcpu))
1485 return false;
1486
1487 mask = kvm_pmu_accessible_counter_mask(vcpu);
1488 kvm_pmu_software_increment(vcpu, p->regval & mask);
1489 return true;
1490 }
1491
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1492 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1493 const struct sys_reg_desc *r)
1494 {
1495 if (p->is_write) {
1496 if (!vcpu_mode_priv(vcpu))
1497 return undef_access(vcpu, p, r);
1498
1499 __vcpu_assign_sys_reg(vcpu, PMUSERENR_EL0,
1500 (p->regval & ARMV8_PMU_USERENR_MASK));
1501 } else {
1502 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1503 & ARMV8_PMU_USERENR_MASK;
1504 }
1505
1506 return true;
1507 }
1508
get_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1509 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1510 u64 *val)
1511 {
1512 *val = kvm_vcpu_read_pmcr(vcpu);
1513 return 0;
1514 }
1515
set_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1516 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1517 u64 val)
1518 {
1519 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val);
1520 struct kvm *kvm = vcpu->kvm;
1521
1522 mutex_lock(&kvm->arch.config_lock);
1523
1524 /*
1525 * The vCPU can't have more counters than the PMU hardware
1526 * implements. Ignore this error to maintain compatibility
1527 * with the existing KVM behavior.
1528 */
1529 if (!kvm_vm_has_ran_once(kvm) &&
1530 !vcpu_has_nv(vcpu) &&
1531 !kvm_vcpu_has_pmuv3_strict(vcpu) &&
1532 new_n <= kvm_arm_pmu_get_max_counters(kvm))
1533 kvm->arch.nr_pmu_counters = new_n;
1534
1535 mutex_unlock(&kvm->arch.config_lock);
1536
1537 /*
1538 * Ignore writes to RES0 bits, read only bits that are cleared on
1539 * vCPU reset, and writable bits that KVM doesn't support yet.
1540 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace)
1541 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU.
1542 * But, we leave the bit as it is here, as the vCPU's PMUver might
1543 * be changed later (NOTE: the bit will be cleared on first vCPU run
1544 * if necessary).
1545 */
1546 val &= ARMV8_PMU_PMCR_MASK;
1547
1548 /* The LC bit is RES1 when AArch32 is not supported */
1549 if (!kvm_supports_32bit_el0())
1550 val |= ARMV8_PMU_PMCR_LC;
1551
1552 __vcpu_assign_sys_reg(vcpu, r->reg, val);
1553 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
1554
1555 return 0;
1556 }
1557
1558 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1559 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1560 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1561 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1562 get_dbg_wb_reg, set_dbg_wb_reg }, \
1563 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1564 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1565 get_dbg_wb_reg, set_dbg_wb_reg }, \
1566 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1567 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1568 get_dbg_wb_reg, set_dbg_wb_reg }, \
1569 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1570 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \
1571 get_dbg_wb_reg, set_dbg_wb_reg }
1572
1573 #define PMU_SYS_REG(name) \
1574 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
1575 .visibility = pmu_visibility
1576
1577 /* Macro to expand the PMEVCNTRn_EL0 register */
1578 #define PMU_PMEVCNTR_EL0(n) \
1579 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
1580 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
1581 .set_user = set_pmu_evcntr, \
1582 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
1583
1584 /* Macro to expand the PMEVTYPERn_EL0 register */
1585 #define PMU_PMEVTYPER_EL0(n) \
1586 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \
1587 .reset = reset_pmevtyper, \
1588 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
1589
1590 /* Macro to expand the AMU counter and type registers*/
1591 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1592 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1593 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1594 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1595
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1596 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1597 const struct sys_reg_desc *rd)
1598 {
1599 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1600 }
1601
1602 /*
1603 * If we land here on a PtrAuth access, that is because we didn't
1604 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1605 * way this happens is when the guest does not have PtrAuth support
1606 * enabled.
1607 */
1608 #define __PTRAUTH_KEY(k) \
1609 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1610 .visibility = ptrauth_visibility}
1611
1612 #define PTRAUTH_KEY(k) \
1613 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1614 __PTRAUTH_KEY(k ## KEYHI_EL1)
1615
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1616 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1617 struct sys_reg_params *p,
1618 const struct sys_reg_desc *r)
1619 {
1620 enum kvm_arch_timers tmr;
1621 enum kvm_arch_timer_regs treg;
1622 u64 reg = reg_to_encoding(r);
1623
1624 switch (reg) {
1625 case SYS_CNTP_TVAL_EL0:
1626 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1627 tmr = TIMER_HPTIMER;
1628 else
1629 tmr = TIMER_PTIMER;
1630 treg = TIMER_REG_TVAL;
1631 break;
1632
1633 case SYS_CNTV_TVAL_EL0:
1634 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1635 tmr = TIMER_HVTIMER;
1636 else
1637 tmr = TIMER_VTIMER;
1638 treg = TIMER_REG_TVAL;
1639 break;
1640
1641 case SYS_AARCH32_CNTP_TVAL:
1642 case SYS_CNTP_TVAL_EL02:
1643 tmr = TIMER_PTIMER;
1644 treg = TIMER_REG_TVAL;
1645 break;
1646
1647 case SYS_CNTV_TVAL_EL02:
1648 tmr = TIMER_VTIMER;
1649 treg = TIMER_REG_TVAL;
1650 break;
1651
1652 case SYS_CNTHP_TVAL_EL2:
1653 tmr = TIMER_HPTIMER;
1654 treg = TIMER_REG_TVAL;
1655 break;
1656
1657 case SYS_CNTHV_TVAL_EL2:
1658 tmr = TIMER_HVTIMER;
1659 treg = TIMER_REG_TVAL;
1660 break;
1661
1662 case SYS_CNTP_CTL_EL0:
1663 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1664 tmr = TIMER_HPTIMER;
1665 else
1666 tmr = TIMER_PTIMER;
1667 treg = TIMER_REG_CTL;
1668 break;
1669
1670 case SYS_CNTV_CTL_EL0:
1671 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1672 tmr = TIMER_HVTIMER;
1673 else
1674 tmr = TIMER_VTIMER;
1675 treg = TIMER_REG_CTL;
1676 break;
1677
1678 case SYS_AARCH32_CNTP_CTL:
1679 case SYS_CNTP_CTL_EL02:
1680 tmr = TIMER_PTIMER;
1681 treg = TIMER_REG_CTL;
1682 break;
1683
1684 case SYS_CNTV_CTL_EL02:
1685 tmr = TIMER_VTIMER;
1686 treg = TIMER_REG_CTL;
1687 break;
1688
1689 case SYS_CNTHP_CTL_EL2:
1690 tmr = TIMER_HPTIMER;
1691 treg = TIMER_REG_CTL;
1692 break;
1693
1694 case SYS_CNTHV_CTL_EL2:
1695 tmr = TIMER_HVTIMER;
1696 treg = TIMER_REG_CTL;
1697 break;
1698
1699 case SYS_CNTP_CVAL_EL0:
1700 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1701 tmr = TIMER_HPTIMER;
1702 else
1703 tmr = TIMER_PTIMER;
1704 treg = TIMER_REG_CVAL;
1705 break;
1706
1707 case SYS_CNTV_CVAL_EL0:
1708 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu))
1709 tmr = TIMER_HVTIMER;
1710 else
1711 tmr = TIMER_VTIMER;
1712 treg = TIMER_REG_CVAL;
1713 break;
1714
1715 case SYS_AARCH32_CNTP_CVAL:
1716 case SYS_CNTP_CVAL_EL02:
1717 tmr = TIMER_PTIMER;
1718 treg = TIMER_REG_CVAL;
1719 break;
1720
1721 case SYS_CNTV_CVAL_EL02:
1722 tmr = TIMER_VTIMER;
1723 treg = TIMER_REG_CVAL;
1724 break;
1725
1726 case SYS_CNTHP_CVAL_EL2:
1727 tmr = TIMER_HPTIMER;
1728 treg = TIMER_REG_CVAL;
1729 break;
1730
1731 case SYS_CNTHV_CVAL_EL2:
1732 tmr = TIMER_HVTIMER;
1733 treg = TIMER_REG_CVAL;
1734 break;
1735
1736 case SYS_CNTPCT_EL0:
1737 case SYS_CNTPCTSS_EL0:
1738 if (is_hyp_ctxt(vcpu))
1739 tmr = TIMER_HPTIMER;
1740 else
1741 tmr = TIMER_PTIMER;
1742 treg = TIMER_REG_CNT;
1743 break;
1744
1745 case SYS_AARCH32_CNTPCT:
1746 case SYS_AARCH32_CNTPCTSS:
1747 tmr = TIMER_PTIMER;
1748 treg = TIMER_REG_CNT;
1749 break;
1750
1751 case SYS_CNTVCT_EL0:
1752 case SYS_CNTVCTSS_EL0:
1753 if (is_hyp_ctxt(vcpu))
1754 tmr = TIMER_HVTIMER;
1755 else
1756 tmr = TIMER_VTIMER;
1757 treg = TIMER_REG_CNT;
1758 break;
1759
1760 case SYS_AARCH32_CNTVCT:
1761 case SYS_AARCH32_CNTVCTSS:
1762 tmr = TIMER_VTIMER;
1763 treg = TIMER_REG_CNT;
1764 break;
1765
1766 default:
1767 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1768 return undef_access(vcpu, p, r);
1769 }
1770
1771 if (p->is_write)
1772 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1773 else
1774 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1775
1776 return true;
1777 }
1778
arch_timer_set_user(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1779 static int arch_timer_set_user(struct kvm_vcpu *vcpu,
1780 const struct sys_reg_desc *rd,
1781 u64 val)
1782 {
1783 switch (reg_to_encoding(rd)) {
1784 case SYS_CNTV_CTL_EL0:
1785 case SYS_CNTP_CTL_EL0:
1786 case SYS_CNTHV_CTL_EL2:
1787 case SYS_CNTHP_CTL_EL2:
1788 val &= ~ARCH_TIMER_CTRL_IT_STAT;
1789 break;
1790 case SYS_CNTVCT_EL0:
1791 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags))
1792 timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read() - val);
1793 return 0;
1794 case SYS_CNTPCT_EL0:
1795 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags))
1796 timer_set_offset(vcpu_ptimer(vcpu), kvm_phys_timer_read() - val);
1797 return 0;
1798 }
1799
1800 __vcpu_assign_sys_reg(vcpu, rd->reg, val);
1801 return 0;
1802 }
1803
arch_timer_get_user(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1804 static int arch_timer_get_user(struct kvm_vcpu *vcpu,
1805 const struct sys_reg_desc *rd,
1806 u64 *val)
1807 {
1808 switch (reg_to_encoding(rd)) {
1809 case SYS_CNTVCT_EL0:
1810 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_vtimer(vcpu));
1811 break;
1812 case SYS_CNTPCT_EL0:
1813 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_ptimer(vcpu));
1814 break;
1815 default:
1816 *val = __vcpu_sys_reg(vcpu, rd->reg);
1817 }
1818
1819 return 0;
1820 }
1821
kvm_arm64_ftr_safe_value(u32 id,const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)1822 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1823 s64 new, s64 cur)
1824 {
1825 struct arm64_ftr_bits kvm_ftr = *ftrp;
1826
1827 /* Some features have different safe value type in KVM than host features */
1828 switch (id) {
1829 case SYS_ID_AA64DFR0_EL1:
1830 switch (kvm_ftr.shift) {
1831 case ID_AA64DFR0_EL1_PMUVer_SHIFT:
1832 kvm_ftr.type = FTR_LOWER_SAFE;
1833 break;
1834 case ID_AA64DFR0_EL1_DebugVer_SHIFT:
1835 kvm_ftr.type = FTR_LOWER_SAFE;
1836 break;
1837 }
1838 break;
1839 case SYS_ID_DFR0_EL1:
1840 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1841 kvm_ftr.type = FTR_LOWER_SAFE;
1842 break;
1843 }
1844
1845 return arm64_ftr_safe_value(&kvm_ftr, new, cur);
1846 }
1847
1848 /*
1849 * arm64_check_features() - Check if a feature register value constitutes
1850 * a subset of features indicated by the idreg's KVM sanitised limit.
1851 *
1852 * This function will check if each feature field of @val is the "safe" value
1853 * against idreg's KVM sanitised limit return from reset() callback.
1854 * If a field value in @val is the same as the one in limit, it is always
1855 * considered the safe value regardless For register fields that are not in
1856 * writable, only the value in limit is considered the safe value.
1857 *
1858 * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1859 */
arm64_check_features(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1860 static int arm64_check_features(struct kvm_vcpu *vcpu,
1861 const struct sys_reg_desc *rd,
1862 u64 val)
1863 {
1864 const struct arm64_ftr_reg *ftr_reg;
1865 const struct arm64_ftr_bits *ftrp = NULL;
1866 u32 id = reg_to_encoding(rd);
1867 u64 writable_mask = rd->val;
1868 u64 limit = rd->reset(vcpu, rd);
1869 u64 mask = 0;
1870
1871 /*
1872 * Hidden and unallocated ID registers may not have a corresponding
1873 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1874 * only safe value is 0.
1875 */
1876 if (sysreg_visible_as_raz(vcpu, rd))
1877 return val ? -E2BIG : 0;
1878
1879 ftr_reg = get_arm64_ftr_reg(id);
1880 if (!ftr_reg)
1881 return -EINVAL;
1882
1883 ftrp = ftr_reg->ftr_bits;
1884
1885 for (; ftrp && ftrp->width; ftrp++) {
1886 s64 f_val, f_lim, safe_val;
1887 u64 ftr_mask;
1888
1889 ftr_mask = arm64_ftr_mask(ftrp);
1890 if ((ftr_mask & writable_mask) != ftr_mask)
1891 continue;
1892
1893 f_val = arm64_ftr_value(ftrp, val);
1894 f_lim = arm64_ftr_value(ftrp, limit);
1895 mask |= ftr_mask;
1896
1897 if (f_val == f_lim)
1898 safe_val = f_val;
1899 else
1900 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1901
1902 if (safe_val != f_val)
1903 return -E2BIG;
1904 }
1905
1906 /* For fields that are not writable, values in limit are the safe values. */
1907 if ((val & ~mask) != (limit & ~mask))
1908 return -E2BIG;
1909
1910 return 0;
1911 }
1912
pmuver_to_perfmon(u8 pmuver)1913 static u8 pmuver_to_perfmon(u8 pmuver)
1914 {
1915 switch (pmuver) {
1916 case ID_AA64DFR0_EL1_PMUVer_IMP:
1917 return ID_DFR0_EL1_PerfMon_PMUv3;
1918 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
1919 return ID_DFR0_EL1_PerfMon_IMPDEF;
1920 default:
1921 /* Anything ARMv8.1+ and NI have the same value. For now. */
1922 return pmuver;
1923 }
1924 }
1925
1926 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1927 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val);
1928 static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val);
1929 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1930
1931 /* Read a sanitised cpufeature ID register by sys_reg_desc */
__kvm_read_sanitised_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1932 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1933 const struct sys_reg_desc *r)
1934 {
1935 u32 id = reg_to_encoding(r);
1936 u64 val;
1937
1938 if (sysreg_visible_as_raz(vcpu, r))
1939 return 0;
1940
1941 val = read_sanitised_ftr_reg(id);
1942
1943 switch (id) {
1944 case SYS_ID_AA64DFR0_EL1:
1945 val = sanitise_id_aa64dfr0_el1(vcpu, val);
1946 break;
1947 case SYS_ID_AA64PFR0_EL1:
1948 val = sanitise_id_aa64pfr0_el1(vcpu, val);
1949 break;
1950 case SYS_ID_AA64PFR1_EL1:
1951 val = sanitise_id_aa64pfr1_el1(vcpu, val);
1952 break;
1953 case SYS_ID_AA64PFR2_EL1:
1954 val = sanitise_id_aa64pfr2_el1(vcpu, val);
1955 break;
1956 case SYS_ID_AA64ISAR1_EL1:
1957 if (!vcpu_has_ptrauth(vcpu))
1958 val &= ~(ID_AA64ISAR1_EL1_APA |
1959 ID_AA64ISAR1_EL1_API |
1960 ID_AA64ISAR1_EL1_GPA |
1961 ID_AA64ISAR1_EL1_GPI);
1962 break;
1963 case SYS_ID_AA64ISAR2_EL1:
1964 if (!vcpu_has_ptrauth(vcpu))
1965 val &= ~(ID_AA64ISAR2_EL1_APA3 |
1966 ID_AA64ISAR2_EL1_GPA3);
1967 if (!cpus_have_final_cap(ARM64_HAS_WFXT) ||
1968 has_broken_cntvoff())
1969 val &= ~ID_AA64ISAR2_EL1_WFxT;
1970 break;
1971 case SYS_ID_AA64ISAR3_EL1:
1972 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_LSFE |
1973 ID_AA64ISAR3_EL1_FAMINMAX | ID_AA64ISAR3_EL1_LSUI;
1974 break;
1975 case SYS_ID_AA64MMFR2_EL1:
1976 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1977 val &= ~ID_AA64MMFR2_EL1_NV;
1978 break;
1979 case SYS_ID_AA64MMFR3_EL1:
1980 val &= ID_AA64MMFR3_EL1_TCRX |
1981 ID_AA64MMFR3_EL1_SCTLRX |
1982 ID_AA64MMFR3_EL1_S1POE |
1983 ID_AA64MMFR3_EL1_S1PIE;
1984
1985 if (!system_supports_poe())
1986 val &= ~ID_AA64MMFR3_EL1_S1POE;
1987 break;
1988 case SYS_ID_MMFR4_EL1:
1989 val &= ~ID_MMFR4_EL1_CCIDX;
1990 break;
1991 }
1992
1993 if (vcpu_has_nv(vcpu))
1994 val = limit_nv_id_reg(vcpu->kvm, id, val);
1995
1996 return val;
1997 }
1998
kvm_read_sanitised_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1999 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
2000 const struct sys_reg_desc *r)
2001 {
2002 return __kvm_read_sanitised_id_reg(vcpu, r);
2003 }
2004
read_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2005 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2006 {
2007 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r));
2008 }
2009
is_feature_id_reg(u32 encoding)2010 static bool is_feature_id_reg(u32 encoding)
2011 {
2012 return (sys_reg_Op0(encoding) == 3 &&
2013 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) &&
2014 sys_reg_CRn(encoding) == 0 &&
2015 sys_reg_CRm(encoding) <= 7);
2016 }
2017
2018 /*
2019 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
2020 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID
2021 * registers KVM maintains on a per-VM basis.
2022 *
2023 * Additionally, the implementation ID registers and CTR_EL0 are handled as
2024 * per-VM registers.
2025 */
is_vm_ftr_id_reg(u32 id)2026 static inline bool is_vm_ftr_id_reg(u32 id)
2027 {
2028 switch (id) {
2029 case SYS_CTR_EL0:
2030 case SYS_MIDR_EL1:
2031 case SYS_REVIDR_EL1:
2032 case SYS_AIDR_EL1:
2033 return true;
2034 default:
2035 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
2036 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
2037 sys_reg_CRm(id) < 8);
2038
2039 }
2040 }
2041
is_vcpu_ftr_id_reg(u32 id)2042 static inline bool is_vcpu_ftr_id_reg(u32 id)
2043 {
2044 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id);
2045 }
2046
is_aa32_id_reg(u32 id)2047 static inline bool is_aa32_id_reg(u32 id)
2048 {
2049 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
2050 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
2051 sys_reg_CRm(id) <= 3);
2052 }
2053
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2054 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
2055 const struct sys_reg_desc *r)
2056 {
2057 u32 id = reg_to_encoding(r);
2058
2059 switch (id) {
2060 case SYS_ID_AA64ZFR0_EL1:
2061 if (!vcpu_has_sve(vcpu))
2062 return REG_RAZ;
2063 break;
2064 }
2065
2066 return 0;
2067 }
2068
aa32_id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2069 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
2070 const struct sys_reg_desc *r)
2071 {
2072 /*
2073 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
2074 * EL. Promote to RAZ/WI in order to guarantee consistency between
2075 * systems.
2076 */
2077 if (!kvm_supports_32bit_el0())
2078 return REG_RAZ | REG_USER_WI;
2079
2080 return id_visibility(vcpu, r);
2081 }
2082
raz_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2083 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
2084 const struct sys_reg_desc *r)
2085 {
2086 return REG_RAZ;
2087 }
2088
2089 /* cpufeature ID register access trap handlers */
2090
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2091 static bool access_id_reg(struct kvm_vcpu *vcpu,
2092 struct sys_reg_params *p,
2093 const struct sys_reg_desc *r)
2094 {
2095 if (p->is_write)
2096 return write_to_read_only(vcpu, p, r);
2097
2098 p->regval = read_id_reg(vcpu, r);
2099
2100 return true;
2101 }
2102
2103 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2104 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
2105 const struct sys_reg_desc *rd)
2106 {
2107 if (vcpu_has_sve(vcpu))
2108 return 0;
2109
2110 return REG_HIDDEN;
2111 }
2112
sme_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2113 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu,
2114 const struct sys_reg_desc *rd)
2115 {
2116 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP))
2117 return 0;
2118
2119 return REG_HIDDEN;
2120 }
2121
fp8_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2122 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu,
2123 const struct sys_reg_desc *rd)
2124 {
2125 if (kvm_has_fpmr(vcpu->kvm))
2126 return 0;
2127
2128 return REG_HIDDEN;
2129 }
2130
sanitise_id_aa64pfr0_el1(const struct kvm_vcpu * vcpu,u64 val)2131 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
2132 {
2133 if (!vcpu_has_sve(vcpu))
2134 val &= ~ID_AA64PFR0_EL1_SVE_MASK;
2135
2136 /*
2137 * The default is to expose CSV2 == 1 if the HW isn't affected.
2138 * Although this is a per-CPU feature, we make it global because
2139 * asymmetric systems are just a nuisance.
2140 *
2141 * Userspace can override this as long as it doesn't promise
2142 * the impossible.
2143 */
2144 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
2145 val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
2146 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
2147 }
2148 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
2149 val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
2150 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
2151 }
2152
2153 if (vgic_host_has_gicv3()) {
2154 val &= ~ID_AA64PFR0_EL1_GIC_MASK;
2155 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
2156 }
2157
2158 val &= ~ID_AA64PFR0_EL1_AMU_MASK;
2159
2160 /*
2161 * MPAM is disabled by default as KVM also needs a set of PARTID to
2162 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some
2163 * older kernels let the guest see the ID bit.
2164 */
2165 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
2166
2167 val &= ~ID_AA64PFR0_EL1_RME_MASK;
2168
2169 return val;
2170 }
2171
sanitise_id_aa64pfr1_el1(const struct kvm_vcpu * vcpu,u64 val)2172 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val)
2173 {
2174 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
2175
2176 if (!kvm_has_mte(vcpu->kvm)) {
2177 val &= ~ID_AA64PFR1_EL1_MTE;
2178 val &= ~ID_AA64PFR1_EL1_MTE_frac;
2179 }
2180
2181 if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) &&
2182 SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP))
2183 val &= ~ID_AA64PFR1_EL1_RAS_frac;
2184
2185 val &= ~ID_AA64PFR1_EL1_SME;
2186 val &= ~ID_AA64PFR1_EL1_RNDR_trap;
2187 val &= ~ID_AA64PFR1_EL1_NMI;
2188 val &= ~ID_AA64PFR1_EL1_GCS;
2189 val &= ~ID_AA64PFR1_EL1_THE;
2190 val &= ~ID_AA64PFR1_EL1_MTEX;
2191 val &= ~ID_AA64PFR1_EL1_PFAR;
2192 val &= ~ID_AA64PFR1_EL1_MPAM_frac;
2193
2194 return val;
2195 }
2196
sanitise_id_aa64pfr2_el1(const struct kvm_vcpu * vcpu,u64 val)2197 static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val)
2198 {
2199 val &= ID_AA64PFR2_EL1_FPMR |
2200 ID_AA64PFR2_EL1_MTEFAR |
2201 ID_AA64PFR2_EL1_MTESTOREONLY;
2202
2203 if (!kvm_has_mte(vcpu->kvm)) {
2204 val &= ~ID_AA64PFR2_EL1_MTEFAR;
2205 val &= ~ID_AA64PFR2_EL1_MTESTOREONLY;
2206 }
2207
2208 if (vgic_host_has_gicv5())
2209 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, IMP);
2210
2211 return val;
2212 }
2213
sanitise_id_aa64dfr0_el1(const struct kvm_vcpu * vcpu,u64 val)2214 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
2215 {
2216 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8);
2217
2218 /*
2219 * Only initialize the PMU version if the vCPU was configured with one.
2220 */
2221 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
2222 if (kvm_vcpu_has_pmu(vcpu))
2223 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
2224 kvm_arm_pmu_get_pmuver_limit());
2225
2226 /* Hide SPE from guests */
2227 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
2228
2229 /* Hide BRBE from guests */
2230 val &= ~ID_AA64DFR0_EL1_BRBE_MASK;
2231
2232 return val;
2233 }
2234
2235 /*
2236 * Older versions of KVM erroneously claim support for FEAT_DoubleLock with
2237 * NV-enabled VMs on unsupporting hardware. Silently ignore the incorrect
2238 * value if it is consistent with the bug.
2239 */
ignore_feat_doublelock(struct kvm_vcpu * vcpu,u64 val)2240 static bool ignore_feat_doublelock(struct kvm_vcpu *vcpu, u64 val)
2241 {
2242 u8 host, user;
2243
2244 if (!vcpu_has_nv(vcpu))
2245 return false;
2246
2247 host = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock,
2248 read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1));
2249 user = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, val);
2250
2251 return host == ID_AA64DFR0_EL1_DoubleLock_NI &&
2252 user == ID_AA64DFR0_EL1_DoubleLock_IMP;
2253 }
2254
set_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2255 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
2256 const struct sys_reg_desc *rd,
2257 u64 val)
2258 {
2259 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val);
2260 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
2261
2262 /*
2263 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
2264 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
2265 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
2266 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
2267 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
2268 *
2269 * At minimum, we're on the hook to allow values that were given to
2270 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
2271 * with a more sensible NI. The value of an ID register changing under
2272 * the nose of the guest is unfortunate, but is certainly no more
2273 * surprising than an ill-guided PMU driver poking at impdef system
2274 * registers that end in an UNDEF...
2275 */
2276 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
2277 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
2278
2279 /*
2280 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a
2281 * nonzero minimum safe value.
2282 */
2283 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP)
2284 return -EINVAL;
2285
2286 if (ignore_feat_doublelock(vcpu, val)) {
2287 val &= ~ID_AA64DFR0_EL1_DoubleLock;
2288 val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI);
2289 }
2290
2291 return set_id_reg(vcpu, rd, val);
2292 }
2293
read_sanitised_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2294 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
2295 const struct sys_reg_desc *rd)
2296 {
2297 u8 perfmon;
2298 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
2299
2300 val &= ~ID_DFR0_EL1_PerfMon_MASK;
2301 if (kvm_vcpu_has_pmu(vcpu)) {
2302 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
2303 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
2304 }
2305
2306 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8);
2307
2308 return val;
2309 }
2310
set_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2311 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
2312 const struct sys_reg_desc *rd,
2313 u64 val)
2314 {
2315 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
2316 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val);
2317
2318 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
2319 val &= ~ID_DFR0_EL1_PerfMon_MASK;
2320 perfmon = 0;
2321 }
2322
2323 /*
2324 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
2325 * it doesn't promise more than what the HW gives us on the
2326 * AArch64 side (as everything is emulated with that), and
2327 * that this is a PMUv3.
2328 */
2329 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
2330 return -EINVAL;
2331
2332 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8)
2333 return -EINVAL;
2334
2335 return set_id_reg(vcpu, rd, val);
2336 }
2337
set_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)2338 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
2339 const struct sys_reg_desc *rd, u64 user_val)
2340 {
2341 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
2342 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK;
2343
2344 /*
2345 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits
2346 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to
2347 * guests, but didn't add trap handling. KVM doesn't support MPAM and
2348 * always returns an UNDEF for these registers. The guest must see 0
2349 * for this field.
2350 *
2351 * But KVM must also accept values from user-space that were provided
2352 * by KVM. On CPUs that support MPAM, permit user-space to write
2353 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field.
2354 */
2355 if ((hw_val & mpam_mask) == (user_val & mpam_mask))
2356 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
2357
2358 /* Fail the guest's request to disable the AA64 ISA at EL{0,1,2} */
2359 if (!FIELD_GET(ID_AA64PFR0_EL1_EL0, user_val) ||
2360 !FIELD_GET(ID_AA64PFR0_EL1_EL1, user_val) ||
2361 (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val)))
2362 return -EINVAL;
2363
2364 return set_id_reg(vcpu, rd, user_val);
2365 }
2366
set_id_aa64pfr1_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)2367 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
2368 const struct sys_reg_desc *rd, u64 user_val)
2369 {
2370 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
2371 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK;
2372 u8 mte = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, hw_val);
2373 u8 user_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, user_val);
2374 u8 hw_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, hw_val);
2375
2376 /* See set_id_aa64pfr0_el1 for comment about MPAM */
2377 if ((hw_val & mpam_mask) == (user_val & mpam_mask))
2378 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
2379
2380 /*
2381 * Previously MTE_frac was hidden from guest. However, if the
2382 * hardware supports MTE2 but not MTE_ASYM_FAULT then a value
2383 * of 0 for this field indicates that the hardware supports
2384 * MTE_ASYNC. Whereas, 0xf indicates MTE_ASYNC is not supported.
2385 *
2386 * As KVM must accept values from KVM provided by user-space,
2387 * when ID_AA64PFR1_EL1.MTE is 2 allow user-space to set
2388 * ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid
2389 * incorrectly claiming hardware support for MTE_ASYNC in the
2390 * guest.
2391 */
2392
2393 if (mte == ID_AA64PFR1_EL1_MTE_MTE2 &&
2394 hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI &&
2395 user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) {
2396 user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK;
2397 user_val |= hw_val & ID_AA64PFR1_EL1_MTE_frac_MASK;
2398 }
2399
2400 return set_id_reg(vcpu, rd, user_val);
2401 }
2402
set_id_aa64pfr2_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)2403 static int set_id_aa64pfr2_el1(struct kvm_vcpu *vcpu,
2404 const struct sys_reg_desc *rd, u64 user_val)
2405 {
2406 return set_id_reg(vcpu, rd, user_val);
2407 }
2408
2409 /*
2410 * Allow userspace to de-feature a stage-2 translation granule but prevent it
2411 * from claiming the impossible.
2412 */
2413 #define tgran2_val_allowed(tg, safe, user) \
2414 ({ \
2415 u8 __s = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, safe); \
2416 u8 __u = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, user); \
2417 \
2418 __s == __u || __u == ID_AA64MMFR0_EL1_##tg##_NI; \
2419 })
2420
set_id_aa64mmfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)2421 static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu,
2422 const struct sys_reg_desc *rd, u64 user_val)
2423 {
2424 u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd);
2425
2426 if (!vcpu_has_nv(vcpu))
2427 return set_id_reg(vcpu, rd, user_val);
2428
2429 if (!tgran2_val_allowed(TGRAN4_2, sanitized_val, user_val) ||
2430 !tgran2_val_allowed(TGRAN16_2, sanitized_val, user_val) ||
2431 !tgran2_val_allowed(TGRAN64_2, sanitized_val, user_val))
2432 return -EINVAL;
2433
2434 return set_id_reg(vcpu, rd, user_val);
2435 }
2436
set_id_aa64mmfr2_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)2437 static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu,
2438 const struct sys_reg_desc *rd, u64 user_val)
2439 {
2440 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1);
2441 u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK;
2442
2443 /*
2444 * We made the mistake to expose the now deprecated NV field,
2445 * so allow userspace to write it, but silently ignore it.
2446 */
2447 if ((hw_val & nv_mask) == (user_val & nv_mask))
2448 user_val &= ~nv_mask;
2449
2450 return set_id_reg(vcpu, rd, user_val);
2451 }
2452
set_ctr_el0(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)2453 static int set_ctr_el0(struct kvm_vcpu *vcpu,
2454 const struct sys_reg_desc *rd, u64 user_val)
2455 {
2456 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val);
2457
2458 /*
2459 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved.
2460 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based
2461 * on what hardware reports.
2462 *
2463 * Using a VIPT software model on PIPT will lead to over invalidation,
2464 * but still correct. Hence, we can allow downgrading PIPT to VIPT,
2465 * but not the other way around. This is handled via arm64_ftr_safe_value()
2466 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value
2467 * set as VIPT.
2468 */
2469 switch (user_L1Ip) {
2470 case CTR_EL0_L1Ip_RESERVED_VPIPT:
2471 case CTR_EL0_L1Ip_RESERVED_AIVIVT:
2472 return -EINVAL;
2473 case CTR_EL0_L1Ip_VIPT:
2474 case CTR_EL0_L1Ip_PIPT:
2475 return set_id_reg(vcpu, rd, user_val);
2476 default:
2477 return -ENOENT;
2478 }
2479 }
2480
2481 /*
2482 * cpufeature ID register user accessors
2483 *
2484 * For now, these registers are immutable for userspace, so no values
2485 * are stored, and for set_id_reg() we don't allow the effective value
2486 * to be changed.
2487 */
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)2488 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2489 u64 *val)
2490 {
2491 /*
2492 * Avoid locking if the VM has already started, as the ID registers are
2493 * guaranteed to be invariant at that point.
2494 */
2495 if (kvm_vm_has_ran_once(vcpu->kvm)) {
2496 *val = read_id_reg(vcpu, rd);
2497 return 0;
2498 }
2499
2500 mutex_lock(&vcpu->kvm->arch.config_lock);
2501 *val = read_id_reg(vcpu, rd);
2502 mutex_unlock(&vcpu->kvm->arch.config_lock);
2503
2504 return 0;
2505 }
2506
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2507 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2508 u64 val)
2509 {
2510 u32 id = reg_to_encoding(rd);
2511 int ret;
2512
2513 mutex_lock(&vcpu->kvm->arch.config_lock);
2514
2515 /*
2516 * Once the VM has started the ID registers are immutable. Reject any
2517 * write that does not match the final register value.
2518 */
2519 if (kvm_vm_has_ran_once(vcpu->kvm)) {
2520 if (val != read_id_reg(vcpu, rd))
2521 ret = -EBUSY;
2522 else
2523 ret = 0;
2524
2525 mutex_unlock(&vcpu->kvm->arch.config_lock);
2526 return ret;
2527 }
2528
2529 ret = arm64_check_features(vcpu, rd, val);
2530 if (!ret)
2531 kvm_set_vm_id_reg(vcpu->kvm, id, val);
2532
2533 mutex_unlock(&vcpu->kvm->arch.config_lock);
2534
2535 /*
2536 * arm64_check_features() returns -E2BIG to indicate the register's
2537 * feature set is a superset of the maximally-allowed register value.
2538 * While it would be nice to precisely describe this to userspace, the
2539 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
2540 * writes return -EINVAL.
2541 */
2542 if (ret == -E2BIG)
2543 ret = -EINVAL;
2544 return ret;
2545 }
2546
kvm_set_vm_id_reg(struct kvm * kvm,u32 reg,u64 val)2547 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val)
2548 {
2549 u64 *p = __vm_id_reg(&kvm->arch, reg);
2550
2551 lockdep_assert_held(&kvm->arch.config_lock);
2552
2553 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm))
2554 return;
2555
2556 *p = val;
2557 }
2558
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)2559 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2560 u64 *val)
2561 {
2562 *val = 0;
2563 return 0;
2564 }
2565
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2566 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2567 u64 val)
2568 {
2569 return 0;
2570 }
2571
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2572 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2573 const struct sys_reg_desc *r)
2574 {
2575 if (p->is_write)
2576 return write_to_read_only(vcpu, p, r);
2577
2578 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0);
2579 return true;
2580 }
2581
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2582 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2583 const struct sys_reg_desc *r)
2584 {
2585 if (p->is_write)
2586 return write_to_read_only(vcpu, p, r);
2587
2588 p->regval = __vcpu_sys_reg(vcpu, r->reg);
2589 return true;
2590 }
2591
2592 /*
2593 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
2594 * by the physical CPU which the vcpu currently resides in.
2595 */
reset_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2596 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2597 {
2598 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
2599 u64 clidr;
2600 u8 loc;
2601
2602 if ((ctr_el0 & CTR_EL0_IDC)) {
2603 /*
2604 * Data cache clean to the PoU is not required so LoUU and LoUIS
2605 * will not be set and a unified cache, which will be marked as
2606 * LoC, will be added.
2607 *
2608 * If not DIC, let the unified cache L2 so that an instruction
2609 * cache can be added as L1 later.
2610 */
2611 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
2612 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
2613 } else {
2614 /*
2615 * Data cache clean to the PoU is required so let L1 have a data
2616 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
2617 * it can be marked as LoC too.
2618 */
2619 loc = 1;
2620 clidr = 1 << CLIDR_LOUU_SHIFT;
2621 clidr |= 1 << CLIDR_LOUIS_SHIFT;
2622 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
2623 }
2624
2625 /*
2626 * Instruction cache invalidation to the PoU is required so let L1 have
2627 * an instruction cache. If L1 already has a data cache, it will be
2628 * CACHE_TYPE_SEPARATE.
2629 */
2630 if (!(ctr_el0 & CTR_EL0_DIC))
2631 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
2632
2633 clidr |= loc << CLIDR_LOC_SHIFT;
2634
2635 /*
2636 * Add tag cache unified to data cache. Allocation tags and data are
2637 * unified in a cache line so that it looks valid even if there is only
2638 * one cache line.
2639 */
2640 if (kvm_has_mte(vcpu->kvm))
2641 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc);
2642
2643 __vcpu_assign_sys_reg(vcpu, r->reg, clidr);
2644
2645 return __vcpu_sys_reg(vcpu, r->reg);
2646 }
2647
set_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2648 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2649 u64 val)
2650 {
2651 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
2652 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
2653
2654 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
2655 return -EINVAL;
2656
2657 __vcpu_assign_sys_reg(vcpu, rd->reg, val);
2658
2659 return 0;
2660 }
2661
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2662 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2663 const struct sys_reg_desc *r)
2664 {
2665 int reg = r->reg;
2666
2667 if (p->is_write)
2668 vcpu_write_sys_reg(vcpu, p->regval, reg);
2669 else
2670 p->regval = vcpu_read_sys_reg(vcpu, reg);
2671 return true;
2672 }
2673
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2674 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2675 const struct sys_reg_desc *r)
2676 {
2677 u32 csselr;
2678
2679 if (p->is_write)
2680 return write_to_read_only(vcpu, p, r);
2681
2682 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
2683 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
2684 if (csselr < CSSELR_MAX)
2685 p->regval = get_ccsidr(vcpu, csselr);
2686
2687 return true;
2688 }
2689
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2690 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
2691 const struct sys_reg_desc *rd)
2692 {
2693 if (kvm_has_mte(vcpu->kvm))
2694 return 0;
2695
2696 return REG_HIDDEN;
2697 }
2698
2699 #define MTE_REG(name) { \
2700 SYS_DESC(SYS_##name), \
2701 .access = undef_access, \
2702 .reset = reset_unknown, \
2703 .reg = name, \
2704 .visibility = mte_visibility, \
2705 }
2706
el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2707 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
2708 const struct sys_reg_desc *rd)
2709 {
2710 if (vcpu_has_nv(vcpu))
2711 return 0;
2712
2713 return REG_HIDDEN;
2714 }
2715
bad_vncr_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2716 static bool bad_vncr_trap(struct kvm_vcpu *vcpu,
2717 struct sys_reg_params *p,
2718 const struct sys_reg_desc *r)
2719 {
2720 /*
2721 * We really shouldn't be here, and this is likely the result
2722 * of a misconfigured trap, as this register should target the
2723 * VNCR page, and nothing else.
2724 */
2725 return bad_trap(vcpu, p, r,
2726 "trap of VNCR-backed register");
2727 }
2728
bad_redir_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2729 static bool bad_redir_trap(struct kvm_vcpu *vcpu,
2730 struct sys_reg_params *p,
2731 const struct sys_reg_desc *r)
2732 {
2733 /*
2734 * We really shouldn't be here, and this is likely the result
2735 * of a misconfigured trap, as this register should target the
2736 * corresponding EL1, and nothing else.
2737 */
2738 return bad_trap(vcpu, p, r,
2739 "trap of EL2 register redirected to EL1");
2740 }
2741
2742 #define SYS_REG_USER_FILTER(name, acc, rst, v, gu, su, filter) { \
2743 SYS_DESC(SYS_##name), \
2744 .access = acc, \
2745 .reset = rst, \
2746 .reg = name, \
2747 .get_user = gu, \
2748 .set_user = su, \
2749 .visibility = filter, \
2750 .val = v, \
2751 }
2752
2753 #define EL2_REG_FILTERED(name, acc, rst, v, filter) \
2754 SYS_REG_USER_FILTER(name, acc, rst, v, NULL, NULL, filter)
2755
2756 #define EL2_REG(name, acc, rst, v) \
2757 EL2_REG_FILTERED(name, acc, rst, v, el2_visibility)
2758
2759 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v)
2760 #define EL2_REG_VNCR_FILT(name, vis) \
2761 EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis)
2762 #define EL2_REG_VNCR_GICv3(name) \
2763 EL2_REG_VNCR_FILT(name, hidden_visibility)
2764 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v)
2765
2766 #define TIMER_REG(name, vis) \
2767 SYS_REG_USER_FILTER(name, access_arch_timer, reset_val, 0, \
2768 arch_timer_get_user, arch_timer_set_user, vis)
2769
2770 /*
2771 * Since reset() callback and field val are not used for idregs, they will be
2772 * used for specific purposes for idregs.
2773 * The reset() would return KVM sanitised register value. The value would be the
2774 * same as the host kernel sanitised value if there is no KVM sanitisation.
2775 * The val would be used as a mask indicating writable fields for the idreg.
2776 * Only bits with 1 are writable from userspace. This mask might not be
2777 * necessary in the future whenever all ID registers are enabled as writable
2778 * from userspace.
2779 */
2780
2781 #define ID_DESC_DEFAULT_CALLBACKS \
2782 .access = access_id_reg, \
2783 .get_user = get_id_reg, \
2784 .set_user = set_id_reg, \
2785 .visibility = id_visibility, \
2786 .reset = kvm_read_sanitised_id_reg
2787
2788 #define ID_DESC(name) \
2789 SYS_DESC(SYS_##name), \
2790 ID_DESC_DEFAULT_CALLBACKS
2791
2792 /* sys_reg_desc initialiser for known cpufeature ID registers */
2793 #define ID_SANITISED(name) { \
2794 ID_DESC(name), \
2795 .val = 0, \
2796 }
2797
2798 /* sys_reg_desc initialiser for writable ID registers */
2799 #define ID_WRITABLE(name, mask) { \
2800 ID_DESC(name), \
2801 .val = mask, \
2802 }
2803
2804 /*
2805 * 32bit ID regs are fully writable when the guest is 32bit
2806 * capable. Nothing in the KVM code should rely on 32bit features
2807 * anyway, only 64bit, so let the VMM do its worse.
2808 */
2809 #define AA32_ID_WRITABLE(name) { \
2810 ID_DESC(name), \
2811 .visibility = aa32_id_visibility, \
2812 .val = GENMASK(31, 0), \
2813 }
2814
2815 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */
2816 #define ID_FILTERED(sysreg, name, mask) { \
2817 ID_DESC(sysreg), \
2818 .set_user = set_##name, \
2819 .val = (mask), \
2820 }
2821
2822 /*
2823 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
2824 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
2825 * (1 <= crm < 8, 0 <= Op2 < 8).
2826 */
2827 #define ID_UNALLOCATED(crm, op2) { \
2828 .name = "S3_0_0_" #crm "_" #op2, \
2829 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2830 ID_DESC_DEFAULT_CALLBACKS, \
2831 .visibility = raz_visibility, \
2832 .val = 0, \
2833 }
2834
2835 /*
2836 * sys_reg_desc initialiser for known ID registers that we hide from guests.
2837 * For now, these are exposed just like unallocated ID regs: they appear
2838 * RAZ for the guest.
2839 */
2840 #define ID_HIDDEN(name) { \
2841 ID_DESC(name), \
2842 .visibility = raz_visibility, \
2843 .val = 0, \
2844 }
2845
access_sp_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2846 static bool access_sp_el1(struct kvm_vcpu *vcpu,
2847 struct sys_reg_params *p,
2848 const struct sys_reg_desc *r)
2849 {
2850 if (p->is_write)
2851 __vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval);
2852 else
2853 p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
2854
2855 return true;
2856 }
2857
access_elr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2858 static bool access_elr(struct kvm_vcpu *vcpu,
2859 struct sys_reg_params *p,
2860 const struct sys_reg_desc *r)
2861 {
2862 if (p->is_write)
2863 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
2864 else
2865 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
2866
2867 return true;
2868 }
2869
access_spsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2870 static bool access_spsr(struct kvm_vcpu *vcpu,
2871 struct sys_reg_params *p,
2872 const struct sys_reg_desc *r)
2873 {
2874 if (p->is_write)
2875 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval);
2876 else
2877 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
2878
2879 return true;
2880 }
2881
access_cntkctl_el12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2882 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu,
2883 struct sys_reg_params *p,
2884 const struct sys_reg_desc *r)
2885 {
2886 if (p->is_write)
2887 __vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval);
2888 else
2889 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1);
2890
2891 return true;
2892 }
2893
reset_hcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2894 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2895 {
2896 u64 val = r->val;
2897
2898 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1))
2899 val |= HCR_E2H;
2900
2901 __vcpu_assign_sys_reg(vcpu, r->reg, val);
2902
2903 return __vcpu_sys_reg(vcpu, r->reg);
2904 }
2905
__el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,unsigned int (* fn)(const struct kvm_vcpu *,const struct sys_reg_desc *))2906 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu,
2907 const struct sys_reg_desc *rd,
2908 unsigned int (*fn)(const struct kvm_vcpu *,
2909 const struct sys_reg_desc *))
2910 {
2911 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd);
2912 }
2913
sve_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2914 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu,
2915 const struct sys_reg_desc *rd)
2916 {
2917 return __el2_visibility(vcpu, rd, sve_visibility);
2918 }
2919
vncr_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2920 static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu,
2921 const struct sys_reg_desc *rd)
2922 {
2923 if (el2_visibility(vcpu, rd) == 0 &&
2924 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY))
2925 return 0;
2926
2927 return REG_HIDDEN;
2928 }
2929
nvhcr_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2930 static unsigned int nvhcr_el2_visibility(const struct kvm_vcpu *vcpu,
2931 const struct sys_reg_desc *rd)
2932 {
2933 if (el2_visibility(vcpu, rd) == 0 &&
2934 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV3))
2935 return 0;
2936
2937 return REG_HIDDEN;
2938 }
2939
sctlr2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2940 static unsigned int sctlr2_visibility(const struct kvm_vcpu *vcpu,
2941 const struct sys_reg_desc *rd)
2942 {
2943 if (kvm_has_sctlr2(vcpu->kvm))
2944 return 0;
2945
2946 return REG_HIDDEN;
2947 }
2948
sctlr2_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2949 static unsigned int sctlr2_el2_visibility(const struct kvm_vcpu *vcpu,
2950 const struct sys_reg_desc *rd)
2951 {
2952 return __el2_visibility(vcpu, rd, sctlr2_visibility);
2953 }
2954
access_zcr_el2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2955 static bool access_zcr_el2(struct kvm_vcpu *vcpu,
2956 struct sys_reg_params *p,
2957 const struct sys_reg_desc *r)
2958 {
2959 if (guest_hyp_sve_traps_enabled(vcpu)) {
2960 kvm_inject_nested_sve_trap(vcpu);
2961 return false;
2962 }
2963
2964 if (!p->is_write)
2965 p->regval = __vcpu_sys_reg(vcpu, ZCR_EL2);
2966 else
2967 __vcpu_assign_sys_reg(vcpu, ZCR_EL2, p->regval);
2968
2969 return true;
2970 }
2971
access_gic_vtr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2972 static bool access_gic_vtr(struct kvm_vcpu *vcpu,
2973 struct sys_reg_params *p,
2974 const struct sys_reg_desc *r)
2975 {
2976 if (p->is_write)
2977 return write_to_read_only(vcpu, p, r);
2978
2979 p->regval = kvm_get_guest_vtr_el2();
2980
2981 return true;
2982 }
2983
access_gic_misr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2984 static bool access_gic_misr(struct kvm_vcpu *vcpu,
2985 struct sys_reg_params *p,
2986 const struct sys_reg_desc *r)
2987 {
2988 if (p->is_write)
2989 return write_to_read_only(vcpu, p, r);
2990
2991 p->regval = vgic_v3_get_misr(vcpu);
2992
2993 return true;
2994 }
2995
access_gic_eisr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2996 static bool access_gic_eisr(struct kvm_vcpu *vcpu,
2997 struct sys_reg_params *p,
2998 const struct sys_reg_desc *r)
2999 {
3000 if (p->is_write)
3001 return write_to_read_only(vcpu, p, r);
3002
3003 p->regval = vgic_v3_get_eisr(vcpu);
3004
3005 return true;
3006 }
3007
access_gic_elrsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3008 static bool access_gic_elrsr(struct kvm_vcpu *vcpu,
3009 struct sys_reg_params *p,
3010 const struct sys_reg_desc *r)
3011 {
3012 if (p->is_write)
3013 return write_to_read_only(vcpu, p, r);
3014
3015 p->regval = vgic_v3_get_elrsr(vcpu);
3016
3017 return true;
3018 }
3019
s1poe_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3020 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu,
3021 const struct sys_reg_desc *rd)
3022 {
3023 if (kvm_has_s1poe(vcpu->kvm))
3024 return 0;
3025
3026 return REG_HIDDEN;
3027 }
3028
s1poe_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3029 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu,
3030 const struct sys_reg_desc *rd)
3031 {
3032 return __el2_visibility(vcpu, rd, s1poe_visibility);
3033 }
3034
tcr2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3035 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu,
3036 const struct sys_reg_desc *rd)
3037 {
3038 if (kvm_has_tcr2(vcpu->kvm))
3039 return 0;
3040
3041 return REG_HIDDEN;
3042 }
3043
tcr2_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3044 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu,
3045 const struct sys_reg_desc *rd)
3046 {
3047 return __el2_visibility(vcpu, rd, tcr2_visibility);
3048 }
3049
fgt2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3050 static unsigned int fgt2_visibility(const struct kvm_vcpu *vcpu,
3051 const struct sys_reg_desc *rd)
3052 {
3053 if (el2_visibility(vcpu, rd) == 0 &&
3054 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, FGT2))
3055 return 0;
3056
3057 return REG_HIDDEN;
3058 }
3059
fgt_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3060 static unsigned int fgt_visibility(const struct kvm_vcpu *vcpu,
3061 const struct sys_reg_desc *rd)
3062 {
3063 if (el2_visibility(vcpu, rd) == 0 &&
3064 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, IMP))
3065 return 0;
3066
3067 return REG_HIDDEN;
3068 }
3069
s1pie_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3070 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu,
3071 const struct sys_reg_desc *rd)
3072 {
3073 if (kvm_has_s1pie(vcpu->kvm))
3074 return 0;
3075
3076 return REG_HIDDEN;
3077 }
3078
s1pie_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3079 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu,
3080 const struct sys_reg_desc *rd)
3081 {
3082 return __el2_visibility(vcpu, rd, s1pie_visibility);
3083 }
3084
cnthv_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)3085 static unsigned int cnthv_visibility(const struct kvm_vcpu *vcpu,
3086 const struct sys_reg_desc *rd)
3087 {
3088 if (vcpu_has_nv(vcpu) &&
3089 !vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2_E2H0))
3090 return 0;
3091
3092 return REG_HIDDEN;
3093 }
3094
access_mdcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3095 static bool access_mdcr(struct kvm_vcpu *vcpu,
3096 struct sys_reg_params *p,
3097 const struct sys_reg_desc *r)
3098 {
3099 u64 hpmn, val, old = __vcpu_sys_reg(vcpu, MDCR_EL2);
3100
3101 if (!p->is_write) {
3102 p->regval = old;
3103 return true;
3104 }
3105
3106 val = p->regval;
3107 hpmn = FIELD_GET(MDCR_EL2_HPMN, val);
3108
3109 /*
3110 * If HPMN is out of bounds, limit it to what we actually
3111 * support. This matches the UNKNOWN definition of the field
3112 * in that case, and keeps the emulation simple. Sort of.
3113 */
3114 if (hpmn > vcpu->kvm->arch.nr_pmu_counters) {
3115 hpmn = vcpu->kvm->arch.nr_pmu_counters;
3116 u64p_replace_bits(&val, hpmn, MDCR_EL2_HPMN);
3117 }
3118
3119 __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val);
3120
3121 /*
3122 * Request a reload of the PMU to enable/disable the counters
3123 * affected by HPME.
3124 */
3125 if ((old ^ val) & MDCR_EL2_HPME)
3126 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
3127
3128 return true;
3129 }
3130
access_ras(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3131 static bool access_ras(struct kvm_vcpu *vcpu,
3132 struct sys_reg_params *p,
3133 const struct sys_reg_desc *r)
3134 {
3135 struct kvm *kvm = vcpu->kvm;
3136
3137 switch(reg_to_encoding(r)) {
3138 case SYS_ERXPFGCDN_EL1:
3139 case SYS_ERXPFGCTL_EL1:
3140 case SYS_ERXPFGF_EL1:
3141 case SYS_ERXMISC2_EL1:
3142 case SYS_ERXMISC3_EL1:
3143 if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) ||
3144 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) &&
3145 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) {
3146 kvm_inject_undefined(vcpu);
3147 return false;
3148 }
3149 break;
3150 default:
3151 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) {
3152 kvm_inject_undefined(vcpu);
3153 return false;
3154 }
3155 }
3156
3157 return trap_raz_wi(vcpu, p, r);
3158 }
3159
3160 /*
3161 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and
3162 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them.
3163 * The values made visible to userspace were the register values of the boot
3164 * CPU.
3165 *
3166 * At the same time, reads from these registers at EL1 previously were not
3167 * trapped, allowing the guest to read the actual hardware value. On big-little
3168 * machines, this means the VM can see different values depending on where a
3169 * given vCPU got scheduled.
3170 *
3171 * These registers are now trapped as collateral damage from SME, and what
3172 * follows attempts to give a user / guest view consistent with the existing
3173 * ABI.
3174 */
access_imp_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3175 static bool access_imp_id_reg(struct kvm_vcpu *vcpu,
3176 struct sys_reg_params *p,
3177 const struct sys_reg_desc *r)
3178 {
3179 if (p->is_write)
3180 return write_to_read_only(vcpu, p, r);
3181
3182 /*
3183 * Return the VM-scoped implementation ID register values if userspace
3184 * has made them writable.
3185 */
3186 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags))
3187 return access_id_reg(vcpu, p, r);
3188
3189 /*
3190 * Otherwise, fall back to the old behavior of returning the value of
3191 * the current CPU.
3192 */
3193 switch (reg_to_encoding(r)) {
3194 case SYS_REVIDR_EL1:
3195 p->regval = read_sysreg(revidr_el1);
3196 break;
3197 case SYS_AIDR_EL1:
3198 p->regval = read_sysreg(aidr_el1);
3199 break;
3200 default:
3201 WARN_ON_ONCE(1);
3202 }
3203
3204 return true;
3205 }
3206
3207 static u64 __ro_after_init boot_cpu_midr_val;
3208 static u64 __ro_after_init boot_cpu_revidr_val;
3209 static u64 __ro_after_init boot_cpu_aidr_val;
3210
init_imp_id_regs(void)3211 static void init_imp_id_regs(void)
3212 {
3213 boot_cpu_midr_val = read_sysreg(midr_el1);
3214 boot_cpu_revidr_val = read_sysreg(revidr_el1);
3215 boot_cpu_aidr_val = read_sysreg(aidr_el1);
3216 }
3217
reset_imp_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)3218 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
3219 {
3220 switch (reg_to_encoding(r)) {
3221 case SYS_MIDR_EL1:
3222 return boot_cpu_midr_val;
3223 case SYS_REVIDR_EL1:
3224 return boot_cpu_revidr_val;
3225 case SYS_AIDR_EL1:
3226 return boot_cpu_aidr_val;
3227 default:
3228 KVM_BUG_ON(1, vcpu->kvm);
3229 return 0;
3230 }
3231 }
3232
set_imp_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)3233 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
3234 u64 val)
3235 {
3236 struct kvm *kvm = vcpu->kvm;
3237 u64 expected;
3238
3239 guard(mutex)(&kvm->arch.config_lock);
3240
3241 expected = read_id_reg(vcpu, r);
3242 if (expected == val)
3243 return 0;
3244
3245 if (!test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags))
3246 return -EINVAL;
3247
3248 /*
3249 * Once the VM has started the ID registers are immutable. Reject the
3250 * write if userspace tries to change it.
3251 */
3252 if (kvm_vm_has_ran_once(kvm))
3253 return -EBUSY;
3254
3255 /*
3256 * Any value is allowed for the implementation ID registers so long as
3257 * it is within the writable mask.
3258 */
3259 if ((val & r->val) != val)
3260 return -EINVAL;
3261
3262 kvm_set_vm_id_reg(kvm, reg_to_encoding(r), val);
3263 return 0;
3264 }
3265
3266 #define IMPLEMENTATION_ID(reg, mask) { \
3267 SYS_DESC(SYS_##reg), \
3268 .access = access_imp_id_reg, \
3269 .get_user = get_id_reg, \
3270 .set_user = set_imp_id_reg, \
3271 .reset = reset_imp_id_reg, \
3272 .val = mask, \
3273 }
3274
reset_mdcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)3275 static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
3276 {
3277 __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters);
3278 return vcpu->kvm->arch.nr_pmu_counters;
3279 }
3280
3281 /*
3282 * Architected system registers.
3283 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
3284 *
3285 * Debug handling: We do trap most, if not all debug related system
3286 * registers. The implementation is good enough to ensure that a guest
3287 * can use these with minimal performance degradation. The drawback is
3288 * that we don't implement any of the external debug architecture.
3289 * This should be revisited if we ever encounter a more demanding
3290 * guest...
3291 */
3292 static const struct sys_reg_desc sys_reg_descs[] = {
3293 DBG_BCR_BVR_WCR_WVR_EL1(0),
3294 DBG_BCR_BVR_WCR_WVR_EL1(1),
3295 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
3296 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
3297 DBG_BCR_BVR_WCR_WVR_EL1(2),
3298 DBG_BCR_BVR_WCR_WVR_EL1(3),
3299 DBG_BCR_BVR_WCR_WVR_EL1(4),
3300 DBG_BCR_BVR_WCR_WVR_EL1(5),
3301 DBG_BCR_BVR_WCR_WVR_EL1(6),
3302 DBG_BCR_BVR_WCR_WVR_EL1(7),
3303 DBG_BCR_BVR_WCR_WVR_EL1(8),
3304 DBG_BCR_BVR_WCR_WVR_EL1(9),
3305 DBG_BCR_BVR_WCR_WVR_EL1(10),
3306 DBG_BCR_BVR_WCR_WVR_EL1(11),
3307 DBG_BCR_BVR_WCR_WVR_EL1(12),
3308 DBG_BCR_BVR_WCR_WVR_EL1(13),
3309 DBG_BCR_BVR_WCR_WVR_EL1(14),
3310 DBG_BCR_BVR_WCR_WVR_EL1(15),
3311
3312 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
3313 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
3314 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
3315 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
3316 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
3317 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
3318 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
3319 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
3320 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
3321
3322 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
3323 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
3324 // DBGDTR[TR]X_EL0 share the same encoding
3325 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
3326
3327 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
3328
3329 IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)),
3330 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
3331 IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)),
3332
3333 /*
3334 * ID regs: all ID_SANITISED() entries here must have corresponding
3335 * entries in arm64_ftr_regs[].
3336 */
3337
3338 /* AArch64 mappings of the AArch32 ID registers */
3339 /* CRm=1 */
3340 AA32_ID_WRITABLE(ID_PFR0_EL1),
3341 AA32_ID_WRITABLE(ID_PFR1_EL1),
3342 { SYS_DESC(SYS_ID_DFR0_EL1),
3343 .access = access_id_reg,
3344 .get_user = get_id_reg,
3345 .set_user = set_id_dfr0_el1,
3346 .visibility = aa32_id_visibility,
3347 .reset = read_sanitised_id_dfr0_el1,
3348 .val = GENMASK(31, 0) },
3349 ID_HIDDEN(ID_AFR0_EL1),
3350 AA32_ID_WRITABLE(ID_MMFR0_EL1),
3351 AA32_ID_WRITABLE(ID_MMFR1_EL1),
3352 AA32_ID_WRITABLE(ID_MMFR2_EL1),
3353 AA32_ID_WRITABLE(ID_MMFR3_EL1),
3354
3355 /* CRm=2 */
3356 AA32_ID_WRITABLE(ID_ISAR0_EL1),
3357 AA32_ID_WRITABLE(ID_ISAR1_EL1),
3358 AA32_ID_WRITABLE(ID_ISAR2_EL1),
3359 AA32_ID_WRITABLE(ID_ISAR3_EL1),
3360 AA32_ID_WRITABLE(ID_ISAR4_EL1),
3361 AA32_ID_WRITABLE(ID_ISAR5_EL1),
3362 AA32_ID_WRITABLE(ID_MMFR4_EL1),
3363 AA32_ID_WRITABLE(ID_ISAR6_EL1),
3364
3365 /* CRm=3 */
3366 AA32_ID_WRITABLE(MVFR0_EL1),
3367 AA32_ID_WRITABLE(MVFR1_EL1),
3368 AA32_ID_WRITABLE(MVFR2_EL1),
3369 ID_UNALLOCATED(3,3),
3370 AA32_ID_WRITABLE(ID_PFR2_EL1),
3371 ID_HIDDEN(ID_DFR1_EL1),
3372 AA32_ID_WRITABLE(ID_MMFR5_EL1),
3373 ID_UNALLOCATED(3,7),
3374
3375 /* AArch64 ID registers */
3376 /* CRm=4 */
3377 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1,
3378 ~(ID_AA64PFR0_EL1_AMU |
3379 ID_AA64PFR0_EL1_MPAM |
3380 ID_AA64PFR0_EL1_SVE |
3381 ID_AA64PFR0_EL1_AdvSIMD |
3382 ID_AA64PFR0_EL1_FP)),
3383 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1,
3384 ~(ID_AA64PFR1_EL1_PFAR |
3385 ID_AA64PFR1_EL1_MTEX |
3386 ID_AA64PFR1_EL1_THE |
3387 ID_AA64PFR1_EL1_GCS |
3388 ID_AA64PFR1_EL1_MTE_frac |
3389 ID_AA64PFR1_EL1_NMI |
3390 ID_AA64PFR1_EL1_RNDR_trap |
3391 ID_AA64PFR1_EL1_SME |
3392 ID_AA64PFR1_EL1_RES0 |
3393 ID_AA64PFR1_EL1_MPAM_frac |
3394 ID_AA64PFR1_EL1_MTE)),
3395 ID_FILTERED(ID_AA64PFR2_EL1, id_aa64pfr2_el1,
3396 (ID_AA64PFR2_EL1_FPMR |
3397 ID_AA64PFR2_EL1_MTEFAR |
3398 ID_AA64PFR2_EL1_MTESTOREONLY |
3399 ID_AA64PFR2_EL1_GCIE)),
3400 ID_UNALLOCATED(4,3),
3401 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
3402 ID_HIDDEN(ID_AA64SMFR0_EL1),
3403 ID_UNALLOCATED(4,6),
3404 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0),
3405
3406 /* CRm=5 */
3407 /*
3408 * Prior to FEAT_Debugv8.9, the architecture defines context-aware
3409 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs).
3410 * KVM does not trap + emulate the breakpoint registers, and as such
3411 * cannot support a layout that misaligns with the underlying hardware.
3412 * While it may be possible to describe a subset that aligns with
3413 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for
3414 * simplicity.
3415 *
3416 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking
3417 * of breakpoints for more details.
3418 */
3419 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1,
3420 ID_AA64DFR0_EL1_DoubleLock_MASK |
3421 ID_AA64DFR0_EL1_WRPs_MASK |
3422 ID_AA64DFR0_EL1_PMUVer_MASK |
3423 ID_AA64DFR0_EL1_DebugVer_MASK),
3424 ID_SANITISED(ID_AA64DFR1_EL1),
3425 ID_UNALLOCATED(5,2),
3426 ID_UNALLOCATED(5,3),
3427 ID_HIDDEN(ID_AA64AFR0_EL1),
3428 ID_HIDDEN(ID_AA64AFR1_EL1),
3429 ID_UNALLOCATED(5,6),
3430 ID_UNALLOCATED(5,7),
3431
3432 /* CRm=6 */
3433 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0),
3434 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI |
3435 ID_AA64ISAR1_EL1_GPA |
3436 ID_AA64ISAR1_EL1_API |
3437 ID_AA64ISAR1_EL1_APA)),
3438 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
3439 ID_AA64ISAR2_EL1_APA3 |
3440 ID_AA64ISAR2_EL1_GPA3)),
3441 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT |
3442 ID_AA64ISAR3_EL1_LSFE |
3443 ID_AA64ISAR3_EL1_LSUI |
3444 ID_AA64ISAR3_EL1_FAMINMAX)),
3445 ID_UNALLOCATED(6,4),
3446 ID_UNALLOCATED(6,5),
3447 ID_UNALLOCATED(6,6),
3448 ID_UNALLOCATED(6,7),
3449
3450 /* CRm=7 */
3451 ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1,
3452 ~(ID_AA64MMFR0_EL1_RES0 |
3453 ID_AA64MMFR0_EL1_ASIDBITS)),
3454 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |
3455 ID_AA64MMFR1_EL1_XNX |
3456 ID_AA64MMFR1_EL1_VH |
3457 ID_AA64MMFR1_EL1_VMIDBits)),
3458 ID_FILTERED(ID_AA64MMFR2_EL1,
3459 id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 |
3460 ID_AA64MMFR2_EL1_EVT |
3461 ID_AA64MMFR2_EL1_FWB |
3462 ID_AA64MMFR2_EL1_IDS |
3463 ID_AA64MMFR2_EL1_NV |
3464 ID_AA64MMFR2_EL1_CCIDX)),
3465 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX |
3466 ID_AA64MMFR3_EL1_SCTLRX |
3467 ID_AA64MMFR3_EL1_S1PIE |
3468 ID_AA64MMFR3_EL1_S1POE)),
3469 ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac),
3470 ID_UNALLOCATED(7,5),
3471 ID_UNALLOCATED(7,6),
3472 ID_UNALLOCATED(7,7),
3473
3474 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
3475 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
3476 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
3477 { SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0,
3478 .visibility = sctlr2_visibility },
3479
3480 MTE_REG(RGSR_EL1),
3481 MTE_REG(GCR_EL1),
3482
3483 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
3484 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
3485 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
3486 { SYS_DESC(SYS_SMCR_EL1), undef_access },
3487 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
3488 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
3489 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
3490 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0,
3491 .visibility = tcr2_visibility },
3492
3493 PTRAUTH_KEY(APIA),
3494 PTRAUTH_KEY(APIB),
3495 PTRAUTH_KEY(APDA),
3496 PTRAUTH_KEY(APDB),
3497 PTRAUTH_KEY(APGA),
3498
3499 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
3500 { SYS_DESC(SYS_ELR_EL1), access_elr},
3501
3502 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
3503
3504 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
3505 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
3506 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
3507
3508 { SYS_DESC(SYS_ERRIDR_EL1), access_ras },
3509 { SYS_DESC(SYS_ERRSELR_EL1), access_ras },
3510 { SYS_DESC(SYS_ERXFR_EL1), access_ras },
3511 { SYS_DESC(SYS_ERXCTLR_EL1), access_ras },
3512 { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras },
3513 { SYS_DESC(SYS_ERXADDR_EL1), access_ras },
3514 { SYS_DESC(SYS_ERXPFGF_EL1), access_ras },
3515 { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras },
3516 { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras },
3517 { SYS_DESC(SYS_ERXMISC0_EL1), access_ras },
3518 { SYS_DESC(SYS_ERXMISC1_EL1), access_ras },
3519 { SYS_DESC(SYS_ERXMISC2_EL1), access_ras },
3520 { SYS_DESC(SYS_ERXMISC3_EL1), access_ras },
3521
3522 MTE_REG(TFSR_EL1),
3523 MTE_REG(TFSRE0_EL1),
3524
3525 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
3526 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
3527
3528 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
3529 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
3530 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
3531 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
3532 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
3533 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
3534 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
3535 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
3536 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
3537 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
3538 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
3539 { SYS_DESC(SYS_PMSDSFR_EL1), undef_access },
3540 /* PMBIDR_EL1 is not trapped */
3541
3542 { PMU_SYS_REG(PMINTENSET_EL1),
3543 .access = access_pminten, .reg = PMINTENSET_EL1,
3544 .get_user = get_pmreg, .set_user = set_pmreg },
3545 { PMU_SYS_REG(PMINTENCLR_EL1),
3546 .access = access_pminten, .reg = PMINTENSET_EL1,
3547 .get_user = get_pmreg, .set_user = set_pmreg },
3548 { PMU_SYS_REG(PMMIR_EL1), .access = access_pmmir, .reset = NULL,
3549 .get_user = get_pmmir, .set_user = set_pmmir },
3550
3551 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
3552 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1,
3553 .visibility = s1pie_visibility },
3554 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1,
3555 .visibility = s1pie_visibility },
3556 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1,
3557 .visibility = s1poe_visibility },
3558 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
3559
3560 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
3561 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
3562 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
3563 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
3564 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access },
3565 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
3566
3567 { SYS_DESC(SYS_MPAM1_EL1), undef_access },
3568 { SYS_DESC(SYS_MPAM0_EL1), undef_access },
3569 { SYS_DESC(SYS_MPAMSM_EL1), undef_access },
3570
3571 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
3572 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
3573
3574 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
3575 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
3576 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
3577 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
3578 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
3579 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
3580 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
3581 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
3582 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
3583 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
3584 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
3585 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
3586 { SYS_DESC(SYS_ICC_IDR0_EL1), access_gicv5_idr0 },
3587 { SYS_DESC(SYS_ICC_IAFFIDR_EL1), access_gicv5_iaffid },
3588 { SYS_DESC(SYS_ICC_PPI_ENABLER0_EL1), access_gicv5_ppi_enabler },
3589 { SYS_DESC(SYS_ICC_PPI_ENABLER1_EL1), access_gicv5_ppi_enabler },
3590 { SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir },
3591 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
3592 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
3593 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
3594 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
3595 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
3596 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
3597 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
3598 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
3599 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
3600 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
3601 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
3602 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
3603
3604 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
3605 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
3606
3607 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
3608
3609 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
3610
3611 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
3612
3613 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
3614 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
3615 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 },
3616 IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)),
3617 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
3618 ID_FILTERED(CTR_EL0, ctr_el0,
3619 CTR_EL0_DIC_MASK |
3620 CTR_EL0_IDC_MASK |
3621 CTR_EL0_DminLine_MASK |
3622 CTR_EL0_L1Ip_MASK |
3623 CTR_EL0_IminLine_MASK),
3624 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
3625 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
3626
3627 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr,
3628 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
3629 { PMU_SYS_REG(PMCNTENSET_EL0),
3630 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
3631 .get_user = get_pmreg, .set_user = set_pmreg },
3632 { PMU_SYS_REG(PMCNTENCLR_EL0),
3633 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
3634 .get_user = get_pmreg, .set_user = set_pmreg },
3635 { PMU_SYS_REG(PMOVSCLR_EL0),
3636 .access = access_pmovs, .reg = PMOVSSET_EL0,
3637 .get_user = get_pmreg, .set_user = set_pmreg },
3638 /*
3639 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
3640 * previously (and pointlessly) advertised in the past...
3641 */
3642 { PMU_SYS_REG(PMSWINC_EL0),
3643 .get_user = get_raz_reg, .set_user = set_wi_reg,
3644 .access = access_pmswinc, .reset = NULL },
3645 { PMU_SYS_REG(PMSELR_EL0),
3646 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
3647 { PMU_SYS_REG(PMCEID0_EL0),
3648 .access = access_pmceid, .reset = NULL },
3649 { PMU_SYS_REG(PMCEID1_EL0),
3650 .access = access_pmceid, .reset = NULL },
3651 { PMU_SYS_REG(PMCCNTR_EL0),
3652 .access = access_pmu_evcntr, .reset = reset_unknown,
3653 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr,
3654 .set_user = set_pmu_evcntr },
3655 { PMU_SYS_REG(PMXEVTYPER_EL0),
3656 .access = access_pmu_evtyper, .reset = NULL },
3657 { PMU_SYS_REG(PMXEVCNTR_EL0),
3658 .access = access_pmu_evcntr, .reset = NULL },
3659 /*
3660 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
3661 * in 32bit mode. Here we choose to reset it as zero for consistency.
3662 */
3663 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
3664 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
3665 { PMU_SYS_REG(PMOVSSET_EL0),
3666 .access = access_pmovs, .reg = PMOVSSET_EL0,
3667 .get_user = get_pmreg, .set_user = set_pmreg },
3668
3669 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0,
3670 .visibility = s1poe_visibility },
3671 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
3672 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
3673 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
3674
3675 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
3676
3677 { SYS_DESC(SYS_AMCR_EL0), undef_access },
3678 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
3679 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
3680 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
3681 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
3682 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
3683 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
3684 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
3685 AMU_AMEVCNTR0_EL0(0),
3686 AMU_AMEVCNTR0_EL0(1),
3687 AMU_AMEVCNTR0_EL0(2),
3688 AMU_AMEVCNTR0_EL0(3),
3689 AMU_AMEVCNTR0_EL0(4),
3690 AMU_AMEVCNTR0_EL0(5),
3691 AMU_AMEVCNTR0_EL0(6),
3692 AMU_AMEVCNTR0_EL0(7),
3693 AMU_AMEVCNTR0_EL0(8),
3694 AMU_AMEVCNTR0_EL0(9),
3695 AMU_AMEVCNTR0_EL0(10),
3696 AMU_AMEVCNTR0_EL0(11),
3697 AMU_AMEVCNTR0_EL0(12),
3698 AMU_AMEVCNTR0_EL0(13),
3699 AMU_AMEVCNTR0_EL0(14),
3700 AMU_AMEVCNTR0_EL0(15),
3701 AMU_AMEVTYPER0_EL0(0),
3702 AMU_AMEVTYPER0_EL0(1),
3703 AMU_AMEVTYPER0_EL0(2),
3704 AMU_AMEVTYPER0_EL0(3),
3705 AMU_AMEVTYPER0_EL0(4),
3706 AMU_AMEVTYPER0_EL0(5),
3707 AMU_AMEVTYPER0_EL0(6),
3708 AMU_AMEVTYPER0_EL0(7),
3709 AMU_AMEVTYPER0_EL0(8),
3710 AMU_AMEVTYPER0_EL0(9),
3711 AMU_AMEVTYPER0_EL0(10),
3712 AMU_AMEVTYPER0_EL0(11),
3713 AMU_AMEVTYPER0_EL0(12),
3714 AMU_AMEVTYPER0_EL0(13),
3715 AMU_AMEVTYPER0_EL0(14),
3716 AMU_AMEVTYPER0_EL0(15),
3717 AMU_AMEVCNTR1_EL0(0),
3718 AMU_AMEVCNTR1_EL0(1),
3719 AMU_AMEVCNTR1_EL0(2),
3720 AMU_AMEVCNTR1_EL0(3),
3721 AMU_AMEVCNTR1_EL0(4),
3722 AMU_AMEVCNTR1_EL0(5),
3723 AMU_AMEVCNTR1_EL0(6),
3724 AMU_AMEVCNTR1_EL0(7),
3725 AMU_AMEVCNTR1_EL0(8),
3726 AMU_AMEVCNTR1_EL0(9),
3727 AMU_AMEVCNTR1_EL0(10),
3728 AMU_AMEVCNTR1_EL0(11),
3729 AMU_AMEVCNTR1_EL0(12),
3730 AMU_AMEVCNTR1_EL0(13),
3731 AMU_AMEVCNTR1_EL0(14),
3732 AMU_AMEVCNTR1_EL0(15),
3733 AMU_AMEVTYPER1_EL0(0),
3734 AMU_AMEVTYPER1_EL0(1),
3735 AMU_AMEVTYPER1_EL0(2),
3736 AMU_AMEVTYPER1_EL0(3),
3737 AMU_AMEVTYPER1_EL0(4),
3738 AMU_AMEVTYPER1_EL0(5),
3739 AMU_AMEVTYPER1_EL0(6),
3740 AMU_AMEVTYPER1_EL0(7),
3741 AMU_AMEVTYPER1_EL0(8),
3742 AMU_AMEVTYPER1_EL0(9),
3743 AMU_AMEVTYPER1_EL0(10),
3744 AMU_AMEVTYPER1_EL0(11),
3745 AMU_AMEVTYPER1_EL0(12),
3746 AMU_AMEVTYPER1_EL0(13),
3747 AMU_AMEVTYPER1_EL0(14),
3748 AMU_AMEVTYPER1_EL0(15),
3749
3750 { SYS_DESC(SYS_CNTPCT_EL0), .access = access_arch_timer,
3751 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user },
3752 { SYS_DESC(SYS_CNTVCT_EL0), .access = access_arch_timer,
3753 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user },
3754 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
3755 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer },
3756 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
3757 TIMER_REG(CNTP_CTL_EL0, NULL),
3758 TIMER_REG(CNTP_CVAL_EL0, NULL),
3759
3760 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer },
3761 TIMER_REG(CNTV_CTL_EL0, NULL),
3762 TIMER_REG(CNTV_CVAL_EL0, NULL),
3763
3764 /* PMEVCNTRn_EL0 */
3765 PMU_PMEVCNTR_EL0(0),
3766 PMU_PMEVCNTR_EL0(1),
3767 PMU_PMEVCNTR_EL0(2),
3768 PMU_PMEVCNTR_EL0(3),
3769 PMU_PMEVCNTR_EL0(4),
3770 PMU_PMEVCNTR_EL0(5),
3771 PMU_PMEVCNTR_EL0(6),
3772 PMU_PMEVCNTR_EL0(7),
3773 PMU_PMEVCNTR_EL0(8),
3774 PMU_PMEVCNTR_EL0(9),
3775 PMU_PMEVCNTR_EL0(10),
3776 PMU_PMEVCNTR_EL0(11),
3777 PMU_PMEVCNTR_EL0(12),
3778 PMU_PMEVCNTR_EL0(13),
3779 PMU_PMEVCNTR_EL0(14),
3780 PMU_PMEVCNTR_EL0(15),
3781 PMU_PMEVCNTR_EL0(16),
3782 PMU_PMEVCNTR_EL0(17),
3783 PMU_PMEVCNTR_EL0(18),
3784 PMU_PMEVCNTR_EL0(19),
3785 PMU_PMEVCNTR_EL0(20),
3786 PMU_PMEVCNTR_EL0(21),
3787 PMU_PMEVCNTR_EL0(22),
3788 PMU_PMEVCNTR_EL0(23),
3789 PMU_PMEVCNTR_EL0(24),
3790 PMU_PMEVCNTR_EL0(25),
3791 PMU_PMEVCNTR_EL0(26),
3792 PMU_PMEVCNTR_EL0(27),
3793 PMU_PMEVCNTR_EL0(28),
3794 PMU_PMEVCNTR_EL0(29),
3795 PMU_PMEVCNTR_EL0(30),
3796 /* PMEVTYPERn_EL0 */
3797 PMU_PMEVTYPER_EL0(0),
3798 PMU_PMEVTYPER_EL0(1),
3799 PMU_PMEVTYPER_EL0(2),
3800 PMU_PMEVTYPER_EL0(3),
3801 PMU_PMEVTYPER_EL0(4),
3802 PMU_PMEVTYPER_EL0(5),
3803 PMU_PMEVTYPER_EL0(6),
3804 PMU_PMEVTYPER_EL0(7),
3805 PMU_PMEVTYPER_EL0(8),
3806 PMU_PMEVTYPER_EL0(9),
3807 PMU_PMEVTYPER_EL0(10),
3808 PMU_PMEVTYPER_EL0(11),
3809 PMU_PMEVTYPER_EL0(12),
3810 PMU_PMEVTYPER_EL0(13),
3811 PMU_PMEVTYPER_EL0(14),
3812 PMU_PMEVTYPER_EL0(15),
3813 PMU_PMEVTYPER_EL0(16),
3814 PMU_PMEVTYPER_EL0(17),
3815 PMU_PMEVTYPER_EL0(18),
3816 PMU_PMEVTYPER_EL0(19),
3817 PMU_PMEVTYPER_EL0(20),
3818 PMU_PMEVTYPER_EL0(21),
3819 PMU_PMEVTYPER_EL0(22),
3820 PMU_PMEVTYPER_EL0(23),
3821 PMU_PMEVTYPER_EL0(24),
3822 PMU_PMEVTYPER_EL0(25),
3823 PMU_PMEVTYPER_EL0(26),
3824 PMU_PMEVTYPER_EL0(27),
3825 PMU_PMEVTYPER_EL0(28),
3826 PMU_PMEVTYPER_EL0(29),
3827 PMU_PMEVTYPER_EL0(30),
3828 /*
3829 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
3830 * in 32bit mode. Here we choose to reset it as zero for consistency.
3831 */
3832 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
3833 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
3834
3835 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0),
3836 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0),
3837 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
3838 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
3839 EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0,
3840 sctlr2_el2_visibility),
3841 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0),
3842 EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0),
3843 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
3844 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
3845 EL2_REG_VNCR_FILT(HFGRTR_EL2, fgt_visibility),
3846 EL2_REG_VNCR_FILT(HFGWTR_EL2, fgt_visibility),
3847 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
3848 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
3849
3850 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0,
3851 sve_el2_visibility),
3852
3853 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
3854 EL2_REG_FILTERED(NVHCR_EL2, undef_access, reset_val, 0,
3855 nvhcr_el2_visibility),
3856
3857 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
3858 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
3859 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
3860 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1,
3861 tcr2_el2_visibility),
3862 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
3863 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
3864 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0,
3865 vncr_el2_visibility),
3866
3867 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },
3868 EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility),
3869 EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility),
3870 EL2_REG_VNCR_FILT(HFGRTR2_EL2, fgt2_visibility),
3871 EL2_REG_VNCR_FILT(HFGWTR2_EL2, fgt2_visibility),
3872 EL2_REG_VNCR_FILT(HDFGRTR_EL2, fgt_visibility),
3873 EL2_REG_VNCR_FILT(HDFGWTR_EL2, fgt_visibility),
3874 EL2_REG_VNCR_FILT(HAFGRTR_EL2, fgt_visibility),
3875 EL2_REG_VNCR_FILT(HFGITR2_EL2, fgt2_visibility),
3876 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
3877 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
3878 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
3879
3880 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
3881 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi },
3882 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi },
3883 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi },
3884 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi },
3885
3886 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },
3887 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
3888 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
3889 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
3890 EL2_REG_VNCR(VSESR_EL2, reset_unknown, 0),
3891 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
3892
3893 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
3894 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
3895
3896 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
3897 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0,
3898 s1pie_el2_visibility),
3899 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,
3900 s1pie_el2_visibility),
3901 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0,
3902 s1poe_el2_visibility),
3903 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
3904 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access },
3905 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access },
3906 { SYS_DESC(SYS_MPAM2_EL2), undef_access },
3907 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access },
3908 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access },
3909 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access },
3910 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access },
3911 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access },
3912 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access },
3913 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access },
3914 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },
3915
3916 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
3917 { SYS_DESC(SYS_RVBAR_EL2), undef_access },
3918 { SYS_DESC(SYS_RMR_EL2), undef_access },
3919 EL2_REG_VNCR(VDISR_EL2, reset_unknown, 0),
3920
3921 EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2),
3922 EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2),
3923 EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2),
3924 EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2),
3925 EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2),
3926 EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2),
3927 EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2),
3928 EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2),
3929
3930 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre },
3931
3932 EL2_REG_VNCR_GICv3(ICH_HCR_EL2),
3933 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr },
3934 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr },
3935 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr },
3936 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr },
3937 EL2_REG_VNCR_GICv3(ICH_VMCR_EL2),
3938
3939 EL2_REG_VNCR_GICv3(ICH_LR0_EL2),
3940 EL2_REG_VNCR_GICv3(ICH_LR1_EL2),
3941 EL2_REG_VNCR_GICv3(ICH_LR2_EL2),
3942 EL2_REG_VNCR_GICv3(ICH_LR3_EL2),
3943 EL2_REG_VNCR_GICv3(ICH_LR4_EL2),
3944 EL2_REG_VNCR_GICv3(ICH_LR5_EL2),
3945 EL2_REG_VNCR_GICv3(ICH_LR6_EL2),
3946 EL2_REG_VNCR_GICv3(ICH_LR7_EL2),
3947 EL2_REG_VNCR_GICv3(ICH_LR8_EL2),
3948 EL2_REG_VNCR_GICv3(ICH_LR9_EL2),
3949 EL2_REG_VNCR_GICv3(ICH_LR10_EL2),
3950 EL2_REG_VNCR_GICv3(ICH_LR11_EL2),
3951 EL2_REG_VNCR_GICv3(ICH_LR12_EL2),
3952 EL2_REG_VNCR_GICv3(ICH_LR13_EL2),
3953 EL2_REG_VNCR_GICv3(ICH_LR14_EL2),
3954 EL2_REG_VNCR_GICv3(ICH_LR15_EL2),
3955
3956 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
3957 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
3958
3959 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
3960 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
3961 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer },
3962 TIMER_REG(CNTHP_CTL_EL2, el2_visibility),
3963 TIMER_REG(CNTHP_CVAL_EL2, el2_visibility),
3964
3965 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_arch_timer, .visibility = cnthv_visibility },
3966 TIMER_REG(CNTHV_CTL_EL2, cnthv_visibility),
3967 TIMER_REG(CNTHV_CVAL_EL2, cnthv_visibility),
3968
3969 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 },
3970
3971 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer },
3972 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer },
3973 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer },
3974
3975 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer },
3976 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer },
3977 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer },
3978
3979 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
3980 };
3981
handle_at_s1e01(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3982 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3983 const struct sys_reg_desc *r)
3984 {
3985 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3986
3987 if (__kvm_at_s1e01(vcpu, op, p->regval))
3988 return false;
3989
3990 return true;
3991 }
3992
handle_at_s1e2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3993 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3994 const struct sys_reg_desc *r)
3995 {
3996 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3997
3998 /* There is no FGT associated with AT S1E2A :-( */
3999 if (op == OP_AT_S1E2A &&
4000 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) {
4001 kvm_inject_undefined(vcpu);
4002 return false;
4003 }
4004
4005 if (__kvm_at_s1e2(vcpu, op, p->regval))
4006 return false;
4007
4008 return true;
4009 }
4010
handle_at_s12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4011 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4012 const struct sys_reg_desc *r)
4013 {
4014 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4015
4016 if (__kvm_at_s12(vcpu, op, p->regval))
4017 return false;
4018
4019 return true;
4020 }
4021
kvm_supported_tlbi_s12_op(struct kvm_vcpu * vpcu,u32 instr)4022 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr)
4023 {
4024 struct kvm *kvm = vpcu->kvm;
4025 u8 CRm = sys_reg_CRm(instr);
4026
4027 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
4028 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
4029 return false;
4030
4031 if (CRm == TLBI_CRm_nROS &&
4032 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4033 return false;
4034
4035 return true;
4036 }
4037
handle_alle1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4038 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4039 const struct sys_reg_desc *r)
4040 {
4041 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4042
4043 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
4044 return undef_access(vcpu, p, r);
4045
4046 write_lock(&vcpu->kvm->mmu_lock);
4047
4048 /*
4049 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the
4050 * corresponding VMIDs.
4051 */
4052 kvm_nested_s2_unmap(vcpu->kvm, true);
4053
4054 write_unlock(&vcpu->kvm->mmu_lock);
4055
4056 return true;
4057 }
4058
kvm_supported_tlbi_ipas2_op(struct kvm_vcpu * vpcu,u32 instr)4059 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr)
4060 {
4061 struct kvm *kvm = vpcu->kvm;
4062 u8 CRm = sys_reg_CRm(instr);
4063 u8 Op2 = sys_reg_Op2(instr);
4064
4065 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
4066 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
4067 return false;
4068
4069 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) &&
4070 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
4071 return false;
4072
4073 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) &&
4074 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4075 return false;
4076
4077 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) &&
4078 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
4079 return false;
4080
4081 return true;
4082 }
4083
4084 /* Only defined here as this is an internal "abstraction" */
4085 union tlbi_info {
4086 struct {
4087 u64 start;
4088 u64 size;
4089 } range;
4090
4091 struct {
4092 u64 addr;
4093 } ipa;
4094
4095 struct {
4096 u64 addr;
4097 u32 encoding;
4098 } va;
4099 };
4100
s2_mmu_unmap_range(struct kvm_s2_mmu * mmu,const union tlbi_info * info)4101 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu,
4102 const union tlbi_info *info)
4103 {
4104 /*
4105 * The unmap operation is allowed to drop the MMU lock and block, which
4106 * means that @mmu could be used for a different context than the one
4107 * currently being invalidated.
4108 *
4109 * This behavior is still safe, as:
4110 *
4111 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating
4112 * the entire MMU before reusing it, which still honors the intent
4113 * of a TLBI.
4114 *
4115 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC
4116 * and ERET to the guest), other vCPUs are allowed to use stale
4117 * translations.
4118 *
4119 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and
4120 * at worst may cause more aborts for shadow stage-2 fills.
4121 *
4122 * Dropping the MMU lock also implies that shadow stage-2 fills could
4123 * happen behind the back of the TLBI. This is still safe, though, as
4124 * the L1 needs to put its stage-2 in a consistent state before doing
4125 * the TLBI.
4126 */
4127 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true);
4128 }
4129
handle_vmalls12e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4130 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4131 const struct sys_reg_desc *r)
4132 {
4133 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4134 u64 limit, vttbr;
4135
4136 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
4137 return undef_access(vcpu, p, r);
4138
4139 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
4140 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm));
4141
4142 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
4143 &(union tlbi_info) {
4144 .range = {
4145 .start = 0,
4146 .size = limit,
4147 },
4148 },
4149 s2_mmu_unmap_range);
4150
4151 return true;
4152 }
4153
handle_ripas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4154 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4155 const struct sys_reg_desc *r)
4156 {
4157 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4158 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
4159 u64 base, range;
4160 int pa_bits;
4161
4162 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
4163 return undef_access(vcpu, p, r);
4164
4165 /*
4166 * Because the shadow S2 structure doesn't necessarily reflect that
4167 * of the guest's S2 (different base granule size, for example), we
4168 * decide to ignore TTL and only use the described range.
4169 */
4170 base = decode_range_tlbi(p->regval, &range, NULL);
4171
4172 /*
4173 * Ignore TLBIs that start out of PA_bits range, and cap the
4174 * invalidation to the [base:bit(PA_bits)] interval.
4175 */
4176 pa_bits = kvm_get_pa_bits(vcpu->kvm);
4177 if (fls64(base) > pa_bits)
4178 return true;
4179
4180 range = min(range, BIT_ULL(pa_bits) - base);
4181
4182 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
4183 &(union tlbi_info) {
4184 .range = {
4185 .start = base,
4186 .size = range,
4187 },
4188 },
4189 s2_mmu_unmap_range);
4190
4191 return true;
4192 }
4193
s2_mmu_unmap_ipa(struct kvm_s2_mmu * mmu,const union tlbi_info * info)4194 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu,
4195 const union tlbi_info *info)
4196 {
4197 unsigned long max_size;
4198 u64 base_addr;
4199
4200 /*
4201 * We drop a number of things from the supplied value:
4202 *
4203 * - NS bit: we're non-secure only.
4204 *
4205 * - IPA[51:48]: We don't support 52bit IPA just yet...
4206 *
4207 * And of course, adjust the IPA to be on an actual address.
4208 */
4209 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12;
4210 max_size = compute_tlb_inval_range(mmu, info->ipa.addr);
4211 base_addr &= ~(max_size - 1);
4212
4213 /*
4214 * See comment in s2_mmu_unmap_range() for why this is allowed to
4215 * reschedule.
4216 */
4217 kvm_stage2_unmap_range(mmu, base_addr, max_size, true);
4218 }
4219
handle_ipas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4220 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4221 const struct sys_reg_desc *r)
4222 {
4223 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4224 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
4225
4226 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
4227 return undef_access(vcpu, p, r);
4228
4229 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
4230 &(union tlbi_info) {
4231 .ipa = {
4232 .addr = p->regval,
4233 },
4234 },
4235 s2_mmu_unmap_ipa);
4236
4237 return true;
4238 }
4239
s2_mmu_tlbi_s1e1(struct kvm_s2_mmu * mmu,const union tlbi_info * info)4240 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu,
4241 const union tlbi_info *info)
4242 {
4243 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding));
4244 }
4245
handle_tlbi_el2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4246 static bool handle_tlbi_el2(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4247 const struct sys_reg_desc *r)
4248 {
4249 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4250
4251 if (!kvm_supported_tlbi_s1e2_op(vcpu, sys_encoding))
4252 return undef_access(vcpu, p, r);
4253
4254 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval);
4255 return true;
4256 }
4257
handle_tlbi_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4258 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
4259 const struct sys_reg_desc *r)
4260 {
4261 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
4262
4263 /*
4264 * If we're here, this is because we've trapped on a EL1 TLBI
4265 * instruction that affects the EL1 translation regime while
4266 * we're running in a context that doesn't allow us to let the
4267 * HW do its thing (aka vEL2):
4268 *
4269 * - HCR_EL2.E2H == 0 : a non-VHE guest
4270 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode
4271 *
4272 * Another possibility is that we are invalidating the EL2 context
4273 * using EL1 instructions, but that we landed here because we need
4274 * additional invalidation for structures that are not held in the
4275 * CPU TLBs (such as the VNCR pseudo-TLB and its EL2 mapping). In
4276 * that case, we are guaranteed that HCR_EL2.{E2H,TGE} == { 1, 1 }
4277 * as we don't allow an NV-capable L1 in a nVHE configuration.
4278 *
4279 * We don't expect these helpers to ever be called when running
4280 * in a vEL1 context.
4281 */
4282
4283 WARN_ON(!vcpu_is_el2(vcpu));
4284
4285 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding))
4286 return undef_access(vcpu, p, r);
4287
4288 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) {
4289 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval);
4290 return true;
4291 }
4292
4293 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm,
4294 get_vmid(__vcpu_sys_reg(vcpu, VTTBR_EL2)),
4295 &(union tlbi_info) {
4296 .va = {
4297 .addr = p->regval,
4298 .encoding = sys_encoding,
4299 },
4300 },
4301 s2_mmu_tlbi_s1e1);
4302
4303 return true;
4304 }
4305
4306 #define SYS_INSN(insn, access_fn) \
4307 { \
4308 SYS_DESC(OP_##insn), \
4309 .access = (access_fn), \
4310 }
4311
4312 static struct sys_reg_desc sys_insn_descs[] = {
4313 { SYS_DESC(SYS_DC_ISW), access_dcsw },
4314 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
4315 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
4316
4317 SYS_INSN(AT_S1E1R, handle_at_s1e01),
4318 SYS_INSN(AT_S1E1W, handle_at_s1e01),
4319 SYS_INSN(AT_S1E0R, handle_at_s1e01),
4320 SYS_INSN(AT_S1E0W, handle_at_s1e01),
4321 SYS_INSN(AT_S1E1RP, handle_at_s1e01),
4322 SYS_INSN(AT_S1E1WP, handle_at_s1e01),
4323 SYS_INSN(AT_S1E1A, handle_at_s1e01),
4324
4325 { SYS_DESC(SYS_DC_CSW), access_dcsw },
4326 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
4327 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
4328 { SYS_DESC(SYS_DC_CISW), access_dcsw },
4329 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
4330 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
4331
4332 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1),
4333 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1),
4334 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1),
4335 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1),
4336 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1),
4337 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1),
4338
4339 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1),
4340 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1),
4341 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1),
4342 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1),
4343
4344 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1),
4345 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1),
4346 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1),
4347 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1),
4348 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1),
4349 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1),
4350
4351 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1),
4352 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1),
4353 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1),
4354 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1),
4355
4356 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1),
4357 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1),
4358 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1),
4359 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1),
4360
4361 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1),
4362 SYS_INSN(TLBI_VAE1, handle_tlbi_el1),
4363 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1),
4364 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1),
4365 SYS_INSN(TLBI_VALE1, handle_tlbi_el1),
4366 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1),
4367
4368 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1),
4369 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1),
4370 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1),
4371 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1),
4372 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1),
4373 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1),
4374
4375 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1),
4376 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1),
4377 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1),
4378 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1),
4379
4380 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1),
4381 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1),
4382 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1),
4383 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1),
4384 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1),
4385 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1),
4386
4387 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1),
4388 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1),
4389 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1),
4390 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1),
4391
4392 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1),
4393 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1),
4394 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1),
4395 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1),
4396
4397 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1),
4398 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1),
4399 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1),
4400 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1),
4401 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1),
4402 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1),
4403
4404 SYS_INSN(AT_S1E2R, handle_at_s1e2),
4405 SYS_INSN(AT_S1E2W, handle_at_s1e2),
4406 SYS_INSN(AT_S12E1R, handle_at_s12),
4407 SYS_INSN(AT_S12E1W, handle_at_s12),
4408 SYS_INSN(AT_S12E0R, handle_at_s12),
4409 SYS_INSN(AT_S12E0W, handle_at_s12),
4410 SYS_INSN(AT_S1E2A, handle_at_s1e2),
4411
4412 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is),
4413 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is),
4414 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is),
4415 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is),
4416
4417 SYS_INSN(TLBI_ALLE2OS, handle_tlbi_el2),
4418 SYS_INSN(TLBI_VAE2OS, handle_tlbi_el2),
4419 SYS_INSN(TLBI_ALLE1OS, handle_alle1is),
4420 SYS_INSN(TLBI_VALE2OS, handle_tlbi_el2),
4421 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is),
4422
4423 SYS_INSN(TLBI_RVAE2IS, handle_tlbi_el2),
4424 SYS_INSN(TLBI_RVALE2IS, handle_tlbi_el2),
4425 SYS_INSN(TLBI_ALLE2IS, handle_tlbi_el2),
4426 SYS_INSN(TLBI_VAE2IS, handle_tlbi_el2),
4427
4428 SYS_INSN(TLBI_ALLE1IS, handle_alle1is),
4429
4430 SYS_INSN(TLBI_VALE2IS, handle_tlbi_el2),
4431
4432 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is),
4433 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is),
4434 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is),
4435 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is),
4436 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is),
4437 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is),
4438 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is),
4439 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is),
4440 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is),
4441 SYS_INSN(TLBI_RVAE2OS, handle_tlbi_el2),
4442 SYS_INSN(TLBI_RVALE2OS, handle_tlbi_el2),
4443 SYS_INSN(TLBI_RVAE2, handle_tlbi_el2),
4444 SYS_INSN(TLBI_RVALE2, handle_tlbi_el2),
4445 SYS_INSN(TLBI_ALLE2, handle_tlbi_el2),
4446 SYS_INSN(TLBI_VAE2, handle_tlbi_el2),
4447
4448 SYS_INSN(TLBI_ALLE1, handle_alle1is),
4449
4450 SYS_INSN(TLBI_VALE2, handle_tlbi_el2),
4451
4452 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is),
4453
4454 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is),
4455 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is),
4456 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is),
4457 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is),
4458
4459 SYS_INSN(TLBI_ALLE2OSNXS, handle_tlbi_el2),
4460 SYS_INSN(TLBI_VAE2OSNXS, handle_tlbi_el2),
4461 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is),
4462 SYS_INSN(TLBI_VALE2OSNXS, handle_tlbi_el2),
4463 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is),
4464
4465 SYS_INSN(TLBI_RVAE2ISNXS, handle_tlbi_el2),
4466 SYS_INSN(TLBI_RVALE2ISNXS, handle_tlbi_el2),
4467 SYS_INSN(TLBI_ALLE2ISNXS, handle_tlbi_el2),
4468 SYS_INSN(TLBI_VAE2ISNXS, handle_tlbi_el2),
4469
4470 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is),
4471 SYS_INSN(TLBI_VALE2ISNXS, handle_tlbi_el2),
4472 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is),
4473 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is),
4474 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is),
4475 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is),
4476 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is),
4477 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is),
4478 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is),
4479 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is),
4480 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is),
4481 SYS_INSN(TLBI_RVAE2OSNXS, handle_tlbi_el2),
4482 SYS_INSN(TLBI_RVALE2OSNXS, handle_tlbi_el2),
4483 SYS_INSN(TLBI_RVAE2NXS, handle_tlbi_el2),
4484 SYS_INSN(TLBI_RVALE2NXS, handle_tlbi_el2),
4485 SYS_INSN(TLBI_ALLE2NXS, handle_tlbi_el2),
4486 SYS_INSN(TLBI_VAE2NXS, handle_tlbi_el2),
4487 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is),
4488 SYS_INSN(TLBI_VALE2NXS, handle_tlbi_el2),
4489 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is),
4490 };
4491
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)4492 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
4493 struct sys_reg_params *p,
4494 const struct sys_reg_desc *r)
4495 {
4496 if (p->is_write) {
4497 return ignore_write(vcpu, p);
4498 } else {
4499 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1);
4500 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP);
4501
4502 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) |
4503 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) |
4504 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) |
4505 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) |
4506 (1 << 15) | (el3 << 14) | (el3 << 12));
4507 return true;
4508 }
4509 }
4510
4511 /*
4512 * AArch32 debug register mappings
4513 *
4514 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
4515 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
4516 *
4517 * None of the other registers share their location, so treat them as
4518 * if they were 64bit.
4519 */
4520 #define DBG_BCR_BVR_WCR_WVR(n) \
4521 /* DBGBVRn */ \
4522 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \
4523 trap_dbg_wb_reg, NULL, n }, \
4524 /* DBGBCRn */ \
4525 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \
4526 /* DBGWVRn */ \
4527 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \
4528 /* DBGWCRn */ \
4529 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n }
4530
4531 #define DBGBXVR(n) \
4532 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \
4533 trap_dbg_wb_reg, NULL, n }
4534
4535 /*
4536 * Trapped cp14 registers. We generally ignore most of the external
4537 * debug, on the principle that they don't really make sense to a
4538 * guest. Revisit this one day, would this principle change.
4539 */
4540 static const struct sys_reg_desc cp14_regs[] = {
4541 /* DBGDIDR */
4542 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
4543 /* DBGDTRRXext */
4544 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
4545
4546 DBG_BCR_BVR_WCR_WVR(0),
4547 /* DBGDSCRint */
4548 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
4549 DBG_BCR_BVR_WCR_WVR(1),
4550 /* DBGDCCINT */
4551 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
4552 /* DBGDSCRext */
4553 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
4554 DBG_BCR_BVR_WCR_WVR(2),
4555 /* DBGDTR[RT]Xint */
4556 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
4557 /* DBGDTR[RT]Xext */
4558 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
4559 DBG_BCR_BVR_WCR_WVR(3),
4560 DBG_BCR_BVR_WCR_WVR(4),
4561 DBG_BCR_BVR_WCR_WVR(5),
4562 /* DBGWFAR */
4563 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
4564 /* DBGOSECCR */
4565 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
4566 DBG_BCR_BVR_WCR_WVR(6),
4567 /* DBGVCR */
4568 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
4569 DBG_BCR_BVR_WCR_WVR(7),
4570 DBG_BCR_BVR_WCR_WVR(8),
4571 DBG_BCR_BVR_WCR_WVR(9),
4572 DBG_BCR_BVR_WCR_WVR(10),
4573 DBG_BCR_BVR_WCR_WVR(11),
4574 DBG_BCR_BVR_WCR_WVR(12),
4575 DBG_BCR_BVR_WCR_WVR(13),
4576 DBG_BCR_BVR_WCR_WVR(14),
4577 DBG_BCR_BVR_WCR_WVR(15),
4578
4579 /* DBGDRAR (32bit) */
4580 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
4581
4582 DBGBXVR(0),
4583 /* DBGOSLAR */
4584 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
4585 DBGBXVR(1),
4586 /* DBGOSLSR */
4587 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
4588 DBGBXVR(2),
4589 DBGBXVR(3),
4590 /* DBGOSDLR */
4591 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
4592 DBGBXVR(4),
4593 /* DBGPRCR */
4594 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
4595 DBGBXVR(5),
4596 DBGBXVR(6),
4597 DBGBXVR(7),
4598 DBGBXVR(8),
4599 DBGBXVR(9),
4600 DBGBXVR(10),
4601 DBGBXVR(11),
4602 DBGBXVR(12),
4603 DBGBXVR(13),
4604 DBGBXVR(14),
4605 DBGBXVR(15),
4606
4607 /* DBGDSAR (32bit) */
4608 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
4609
4610 /* DBGDEVID2 */
4611 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
4612 /* DBGDEVID1 */
4613 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
4614 /* DBGDEVID */
4615 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
4616 /* DBGCLAIMSET */
4617 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
4618 /* DBGCLAIMCLR */
4619 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
4620 /* DBGAUTHSTATUS */
4621 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
4622 };
4623
4624 /* Trapped cp14 64bit registers */
4625 static const struct sys_reg_desc cp14_64_regs[] = {
4626 /* DBGDRAR (64bit) */
4627 { Op1( 0), CRm( 1), .access = trap_raz_wi },
4628
4629 /* DBGDSAR (64bit) */
4630 { Op1( 0), CRm( 2), .access = trap_raz_wi },
4631 };
4632
4633 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
4634 AA32(_map), \
4635 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
4636 .visibility = pmu_visibility
4637
4638 /* Macro to expand the PMEVCNTRn register */
4639 #define PMU_PMEVCNTR(n) \
4640 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
4641 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
4642 .access = access_pmu_evcntr }
4643
4644 /* Macro to expand the PMEVTYPERn register */
4645 #define PMU_PMEVTYPER(n) \
4646 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
4647 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
4648 .access = access_pmu_evtyper }
4649 /*
4650 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
4651 * depending on the way they are accessed (as a 32bit or a 64bit
4652 * register).
4653 */
4654 static const struct sys_reg_desc cp15_regs[] = {
4655 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
4656 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
4657 /* ACTLR */
4658 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
4659 /* ACTLR2 */
4660 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
4661 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
4662 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
4663 /* TTBCR */
4664 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
4665 /* TTBCR2 */
4666 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
4667 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
4668 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
4669 /* DFSR */
4670 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
4671 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
4672 /* ADFSR */
4673 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
4674 /* AIFSR */
4675 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
4676 /* DFAR */
4677 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
4678 /* IFAR */
4679 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
4680
4681 /*
4682 * DC{C,I,CI}SW operations:
4683 */
4684 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
4685 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
4686 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4687
4688 /* PMU */
4689 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
4690 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
4691 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
4692 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
4693 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
4694 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
4695 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
4696 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
4697 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
4698 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
4699 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
4700 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
4701 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
4702 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
4703 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
4704 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
4705 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
4706 /* PMMIR */
4707 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = access_pmmir },
4708
4709 /* PRRR/MAIR0 */
4710 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
4711 /* NMRR/MAIR1 */
4712 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
4713 /* AMAIR0 */
4714 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
4715 /* AMAIR1 */
4716 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
4717
4718 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
4719 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
4720 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
4721 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
4722 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
4723 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
4724 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
4725 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
4726 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
4727 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
4728 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
4729 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
4730 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir },
4731 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
4732 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
4733 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
4734 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
4735 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
4736 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
4737 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
4738 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
4739 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
4740
4741 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
4742
4743 /* Arch Tmers */
4744 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
4745 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
4746
4747 /* PMEVCNTRn */
4748 PMU_PMEVCNTR(0),
4749 PMU_PMEVCNTR(1),
4750 PMU_PMEVCNTR(2),
4751 PMU_PMEVCNTR(3),
4752 PMU_PMEVCNTR(4),
4753 PMU_PMEVCNTR(5),
4754 PMU_PMEVCNTR(6),
4755 PMU_PMEVCNTR(7),
4756 PMU_PMEVCNTR(8),
4757 PMU_PMEVCNTR(9),
4758 PMU_PMEVCNTR(10),
4759 PMU_PMEVCNTR(11),
4760 PMU_PMEVCNTR(12),
4761 PMU_PMEVCNTR(13),
4762 PMU_PMEVCNTR(14),
4763 PMU_PMEVCNTR(15),
4764 PMU_PMEVCNTR(16),
4765 PMU_PMEVCNTR(17),
4766 PMU_PMEVCNTR(18),
4767 PMU_PMEVCNTR(19),
4768 PMU_PMEVCNTR(20),
4769 PMU_PMEVCNTR(21),
4770 PMU_PMEVCNTR(22),
4771 PMU_PMEVCNTR(23),
4772 PMU_PMEVCNTR(24),
4773 PMU_PMEVCNTR(25),
4774 PMU_PMEVCNTR(26),
4775 PMU_PMEVCNTR(27),
4776 PMU_PMEVCNTR(28),
4777 PMU_PMEVCNTR(29),
4778 PMU_PMEVCNTR(30),
4779 /* PMEVTYPERn */
4780 PMU_PMEVTYPER(0),
4781 PMU_PMEVTYPER(1),
4782 PMU_PMEVTYPER(2),
4783 PMU_PMEVTYPER(3),
4784 PMU_PMEVTYPER(4),
4785 PMU_PMEVTYPER(5),
4786 PMU_PMEVTYPER(6),
4787 PMU_PMEVTYPER(7),
4788 PMU_PMEVTYPER(8),
4789 PMU_PMEVTYPER(9),
4790 PMU_PMEVTYPER(10),
4791 PMU_PMEVTYPER(11),
4792 PMU_PMEVTYPER(12),
4793 PMU_PMEVTYPER(13),
4794 PMU_PMEVTYPER(14),
4795 PMU_PMEVTYPER(15),
4796 PMU_PMEVTYPER(16),
4797 PMU_PMEVTYPER(17),
4798 PMU_PMEVTYPER(18),
4799 PMU_PMEVTYPER(19),
4800 PMU_PMEVTYPER(20),
4801 PMU_PMEVTYPER(21),
4802 PMU_PMEVTYPER(22),
4803 PMU_PMEVTYPER(23),
4804 PMU_PMEVTYPER(24),
4805 PMU_PMEVTYPER(25),
4806 PMU_PMEVTYPER(26),
4807 PMU_PMEVTYPER(27),
4808 PMU_PMEVTYPER(28),
4809 PMU_PMEVTYPER(29),
4810 PMU_PMEVTYPER(30),
4811 /* PMCCFILTR */
4812 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
4813
4814 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
4815 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
4816
4817 /* CCSIDR2 */
4818 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
4819
4820 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
4821 };
4822
4823 static const struct sys_reg_desc cp15_64_regs[] = {
4824 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
4825 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
4826 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
4827 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
4828 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
4829 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
4830 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer },
4831 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
4832 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
4833 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
4834 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer },
4835 };
4836
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool reset_check)4837 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
4838 bool reset_check)
4839 {
4840 unsigned int i;
4841
4842 for (i = 0; i < n; i++) {
4843 if (reset_check && table[i].reg && !table[i].reset) {
4844 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n",
4845 &table[i], i, table[i].name);
4846 return false;
4847 }
4848
4849 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
4850 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n",
4851 &table[i], i, table[i - 1].name, table[i].name);
4852 return false;
4853 }
4854 }
4855
4856 return true;
4857 }
4858
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)4859 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
4860 {
4861 kvm_inject_undefined(vcpu);
4862 return 1;
4863 }
4864
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)4865 static void perform_access(struct kvm_vcpu *vcpu,
4866 struct sys_reg_params *params,
4867 const struct sys_reg_desc *r)
4868 {
4869 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
4870
4871 /* Check for regs disabled by runtime config */
4872 if (sysreg_hidden(vcpu, r)) {
4873 kvm_inject_undefined(vcpu);
4874 return;
4875 }
4876
4877 /*
4878 * Not having an accessor means that we have configured a trap
4879 * that we don't know how to handle. This certainly qualifies
4880 * as a gross bug that should be fixed right away.
4881 */
4882 if (!r->access) {
4883 bad_trap(vcpu, params, r, "register access");
4884 return;
4885 }
4886
4887 /* Skip instruction if instructed so */
4888 if (likely(r->access(vcpu, params, r)))
4889 kvm_incr_pc(vcpu);
4890 }
4891
4892 /*
4893 * emulate_cp -- tries to match a sys_reg access in a handling table, and
4894 * call the corresponding trap handler.
4895 *
4896 * @params: pointer to the descriptor of the access
4897 * @table: array of trap descriptors
4898 * @num: size of the trap descriptor array
4899 *
4900 * Return true if the access has been handled, false if not.
4901 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)4902 static bool emulate_cp(struct kvm_vcpu *vcpu,
4903 struct sys_reg_params *params,
4904 const struct sys_reg_desc *table,
4905 size_t num)
4906 {
4907 const struct sys_reg_desc *r;
4908
4909 if (!table)
4910 return false; /* Not handled */
4911
4912 r = find_reg(params, table, num);
4913
4914 if (r) {
4915 perform_access(vcpu, params, r);
4916 return true;
4917 }
4918
4919 /* Not handled */
4920 return false;
4921 }
4922
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)4923 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
4924 struct sys_reg_params *params)
4925 {
4926 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
4927 int cp = -1;
4928
4929 switch (esr_ec) {
4930 case ESR_ELx_EC_CP15_32:
4931 case ESR_ELx_EC_CP15_64:
4932 cp = 15;
4933 break;
4934 case ESR_ELx_EC_CP14_MR:
4935 case ESR_ELx_EC_CP14_64:
4936 cp = 14;
4937 break;
4938 default:
4939 WARN_ON(1);
4940 }
4941
4942 print_sys_reg_msg(params,
4943 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
4944 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
4945 kvm_inject_undefined(vcpu);
4946 }
4947
4948 /**
4949 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
4950 * @vcpu: The VCPU pointer
4951 * @global: &struct sys_reg_desc
4952 * @nr_global: size of the @global array
4953 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)4954 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
4955 const struct sys_reg_desc *global,
4956 size_t nr_global)
4957 {
4958 struct sys_reg_params params;
4959 u64 esr = kvm_vcpu_get_esr(vcpu);
4960 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4961 int Rt2 = (esr >> 10) & 0x1f;
4962
4963 params.CRm = (esr >> 1) & 0xf;
4964 params.is_write = ((esr & 1) == 0);
4965
4966 params.Op0 = 0;
4967 params.Op1 = (esr >> 16) & 0xf;
4968 params.Op2 = 0;
4969 params.CRn = 0;
4970
4971 /*
4972 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
4973 * backends between AArch32 and AArch64, we get away with it.
4974 */
4975 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
4976 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
4977
4978 /*
4979 * If the table contains a handler, handle the
4980 * potential register operation in the case of a read and return
4981 * with success.
4982 */
4983 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
4984 /* Split up the value between registers for the read side */
4985 if (!params.is_write) {
4986 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
4987 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
4988 }
4989
4990 return 1;
4991 }
4992
4993 unhandled_cp_access(vcpu, ¶ms);
4994 return 1;
4995 }
4996
4997 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
4998
4999 /*
5000 * The CP10 ID registers are architecturally mapped to AArch64 feature
5001 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
5002 * from AArch32.
5003 */
kvm_esr_cp10_id_to_sys64(u64 esr,struct sys_reg_params * params)5004 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
5005 {
5006 u8 reg_id = (esr >> 10) & 0xf;
5007 bool valid;
5008
5009 params->is_write = ((esr & 1) == 0);
5010 params->Op0 = 3;
5011 params->Op1 = 0;
5012 params->CRn = 0;
5013 params->CRm = 3;
5014
5015 /* CP10 ID registers are read-only */
5016 valid = !params->is_write;
5017
5018 switch (reg_id) {
5019 /* MVFR0 */
5020 case 0b0111:
5021 params->Op2 = 0;
5022 break;
5023 /* MVFR1 */
5024 case 0b0110:
5025 params->Op2 = 1;
5026 break;
5027 /* MVFR2 */
5028 case 0b0101:
5029 params->Op2 = 2;
5030 break;
5031 default:
5032 valid = false;
5033 }
5034
5035 if (valid)
5036 return true;
5037
5038 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
5039 str_write_read(params->is_write), reg_id);
5040 return false;
5041 }
5042
5043 /**
5044 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
5045 * VFP Register' from AArch32.
5046 * @vcpu: The vCPU pointer
5047 *
5048 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
5049 * Work out the correct AArch64 system register encoding and reroute to the
5050 * AArch64 system register emulation.
5051 */
kvm_handle_cp10_id(struct kvm_vcpu * vcpu)5052 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
5053 {
5054 int Rt = kvm_vcpu_sys_get_rt(vcpu);
5055 u64 esr = kvm_vcpu_get_esr(vcpu);
5056 struct sys_reg_params params;
5057
5058 /* UNDEF on any unhandled register access */
5059 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
5060 kvm_inject_undefined(vcpu);
5061 return 1;
5062 }
5063
5064 if (emulate_sys_reg(vcpu, ¶ms))
5065 vcpu_set_reg(vcpu, Rt, params.regval);
5066
5067 return 1;
5068 }
5069
5070 /**
5071 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
5072 * CRn=0, which corresponds to the AArch32 feature
5073 * registers.
5074 * @vcpu: the vCPU pointer
5075 * @params: the system register access parameters.
5076 *
5077 * Our cp15 system register tables do not enumerate the AArch32 feature
5078 * registers. Conveniently, our AArch64 table does, and the AArch32 system
5079 * register encoding can be trivially remapped into the AArch64 for the feature
5080 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
5081 *
5082 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
5083 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
5084 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
5085 * treat undefined registers in this range as RAZ.
5086 */
kvm_emulate_cp15_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)5087 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
5088 struct sys_reg_params *params)
5089 {
5090 int Rt = kvm_vcpu_sys_get_rt(vcpu);
5091
5092 /* Treat impossible writes to RO registers as UNDEFINED */
5093 if (params->is_write) {
5094 unhandled_cp_access(vcpu, params);
5095 return 1;
5096 }
5097
5098 params->Op0 = 3;
5099
5100 /*
5101 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
5102 * Avoid conflicting with future expansion of AArch64 feature registers
5103 * and simply treat them as RAZ here.
5104 */
5105 if (params->CRm > 3)
5106 params->regval = 0;
5107 else if (!emulate_sys_reg(vcpu, params))
5108 return 1;
5109
5110 vcpu_set_reg(vcpu, Rt, params->regval);
5111 return 1;
5112 }
5113
5114 /**
5115 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
5116 * @vcpu: The VCPU pointer
5117 * @params: &struct sys_reg_params
5118 * @global: &struct sys_reg_desc
5119 * @nr_global: size of the @global array
5120 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * global,size_t nr_global)5121 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
5122 struct sys_reg_params *params,
5123 const struct sys_reg_desc *global,
5124 size_t nr_global)
5125 {
5126 int Rt = kvm_vcpu_sys_get_rt(vcpu);
5127
5128 params->regval = vcpu_get_reg(vcpu, Rt);
5129
5130 if (emulate_cp(vcpu, params, global, nr_global)) {
5131 if (!params->is_write)
5132 vcpu_set_reg(vcpu, Rt, params->regval);
5133 return 1;
5134 }
5135
5136 unhandled_cp_access(vcpu, params);
5137 return 1;
5138 }
5139
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)5140 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
5141 {
5142 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
5143 }
5144
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)5145 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
5146 {
5147 struct sys_reg_params params;
5148
5149 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
5150
5151 /*
5152 * Certain AArch32 ID registers are handled by rerouting to the AArch64
5153 * system register table. Registers in the ID range where CRm=0 are
5154 * excluded from this scheme as they do not trivially map into AArch64
5155 * system register encodings, except for AIDR/REVIDR.
5156 */
5157 if (params.Op1 == 0 && params.CRn == 0 &&
5158 (params.CRm || params.Op2 == 6 /* REVIDR */))
5159 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
5160 if (params.Op1 == 1 && params.CRn == 0 &&
5161 params.CRm == 0 && params.Op2 == 7 /* AIDR */)
5162 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
5163
5164 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
5165 }
5166
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)5167 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
5168 {
5169 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
5170 }
5171
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)5172 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
5173 {
5174 struct sys_reg_params params;
5175
5176 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
5177
5178 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
5179 }
5180
5181 /**
5182 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
5183 * @vcpu: The VCPU pointer
5184 * @params: Decoded system register parameters
5185 *
5186 * Return: true if the system register access was successful, false otherwise.
5187 */
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)5188 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
5189 struct sys_reg_params *params)
5190 {
5191 const struct sys_reg_desc *r;
5192
5193 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
5194 if (likely(r)) {
5195 perform_access(vcpu, params, r);
5196 return true;
5197 }
5198
5199 print_sys_reg_msg(params,
5200 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
5201 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
5202 kvm_inject_undefined(vcpu);
5203
5204 return false;
5205 }
5206
idregs_debug_find(struct kvm * kvm,loff_t pos)5207 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, loff_t pos)
5208 {
5209 unsigned long i, idreg_idx = 0;
5210
5211 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
5212 const struct sys_reg_desc *r = &sys_reg_descs[i];
5213
5214 if (!is_vm_ftr_id_reg(reg_to_encoding(r)))
5215 continue;
5216
5217 if (idreg_idx++ == pos)
5218 return r;
5219 }
5220
5221 return NULL;
5222 }
5223
idregs_debug_start(struct seq_file * s,loff_t * pos)5224 static void *idregs_debug_start(struct seq_file *s, loff_t *pos)
5225 {
5226 struct kvm *kvm = s->private;
5227
5228 if (!test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
5229 return NULL;
5230
5231 return (void *)idregs_debug_find(kvm, *pos);
5232 }
5233
idregs_debug_next(struct seq_file * s,void * v,loff_t * pos)5234 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos)
5235 {
5236 struct kvm *kvm = s->private;
5237
5238 (*pos)++;
5239
5240 return (void *)idregs_debug_find(kvm, *pos);
5241 }
5242
idregs_debug_stop(struct seq_file * s,void * v)5243 static void idregs_debug_stop(struct seq_file *s, void *v)
5244 {
5245 }
5246
idregs_debug_show(struct seq_file * s,void * v)5247 static int idregs_debug_show(struct seq_file *s, void *v)
5248 {
5249 const struct sys_reg_desc *desc = v;
5250 struct kvm *kvm = s->private;
5251
5252 if (!desc)
5253 return 0;
5254
5255 seq_printf(s, "%20s:\t%016llx\n",
5256 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc)));
5257
5258 return 0;
5259 }
5260
5261 static const struct seq_operations idregs_debug_sops = {
5262 .start = idregs_debug_start,
5263 .next = idregs_debug_next,
5264 .stop = idregs_debug_stop,
5265 .show = idregs_debug_show,
5266 };
5267
5268 DEFINE_SEQ_ATTRIBUTE(idregs_debug);
5269
sr_resx_find(struct kvm * kvm,loff_t pos)5270 static const struct sys_reg_desc *sr_resx_find(struct kvm *kvm, loff_t pos)
5271 {
5272 unsigned long i, sr_idx = 0;
5273
5274 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
5275 const struct sys_reg_desc *r = &sys_reg_descs[i];
5276
5277 if (r->reg < __SANITISED_REG_START__)
5278 continue;
5279
5280 if (sr_idx++ == pos)
5281 return r;
5282 }
5283
5284 return NULL;
5285 }
5286
sr_resx_start(struct seq_file * s,loff_t * pos)5287 static void *sr_resx_start(struct seq_file *s, loff_t *pos)
5288 {
5289 struct kvm *kvm = s->private;
5290
5291 if (!kvm->arch.sysreg_masks)
5292 return NULL;
5293
5294 return (void *)sr_resx_find(kvm, *pos);
5295 }
5296
sr_resx_next(struct seq_file * s,void * v,loff_t * pos)5297 static void *sr_resx_next(struct seq_file *s, void *v, loff_t *pos)
5298 {
5299 struct kvm *kvm = s->private;
5300
5301 (*pos)++;
5302
5303 return (void *)sr_resx_find(kvm, *pos);
5304 }
5305
sr_resx_stop(struct seq_file * s,void * v)5306 static void sr_resx_stop(struct seq_file *s, void *v)
5307 {
5308 }
5309
sr_resx_show(struct seq_file * s,void * v)5310 static int sr_resx_show(struct seq_file *s, void *v)
5311 {
5312 const struct sys_reg_desc *desc = v;
5313 struct kvm *kvm = s->private;
5314 struct resx resx;
5315
5316 if (!desc)
5317 return 0;
5318
5319 resx = kvm_get_sysreg_resx(kvm, desc->reg);
5320
5321 seq_printf(s, "%20s:\tRES0:%016llx\tRES1:%016llx\n",
5322 desc->name, resx.res0, resx.res1);
5323
5324 return 0;
5325 }
5326
5327 static const struct seq_operations sr_resx_sops = {
5328 .start = sr_resx_start,
5329 .next = sr_resx_next,
5330 .stop = sr_resx_stop,
5331 .show = sr_resx_show,
5332 };
5333
5334 DEFINE_SEQ_ATTRIBUTE(sr_resx);
5335
kvm_sys_regs_create_debugfs(struct kvm * kvm)5336 void kvm_sys_regs_create_debugfs(struct kvm *kvm)
5337 {
5338 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm,
5339 &idregs_debug_fops);
5340 debugfs_create_file("resx", 0444, kvm->debugfs_dentry, kvm,
5341 &sr_resx_fops);
5342 }
5343
reset_vm_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)5344 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg)
5345 {
5346 u32 id = reg_to_encoding(reg);
5347 struct kvm *kvm = vcpu->kvm;
5348
5349 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
5350 return;
5351
5352 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg));
5353 }
5354
reset_vcpu_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)5355 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu,
5356 const struct sys_reg_desc *reg)
5357 {
5358 if (kvm_vcpu_initialized(vcpu))
5359 return;
5360
5361 reg->reset(vcpu, reg);
5362 }
5363
5364 /**
5365 * kvm_reset_sys_regs - sets system registers to reset value
5366 * @vcpu: The VCPU pointer
5367 *
5368 * This function finds the right table above and sets the registers on the
5369 * virtual CPU struct to their architecturally defined reset values.
5370 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)5371 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
5372 {
5373 struct kvm *kvm = vcpu->kvm;
5374 unsigned long i;
5375
5376 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
5377 const struct sys_reg_desc *r = &sys_reg_descs[i];
5378
5379 if (!r->reset)
5380 continue;
5381
5382 if (is_vm_ftr_id_reg(reg_to_encoding(r)))
5383 reset_vm_ftr_id_reg(vcpu, r);
5384 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r)))
5385 reset_vcpu_ftr_id_reg(vcpu, r);
5386 else
5387 r->reset(vcpu, r);
5388
5389 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS)
5390 __vcpu_rmw_sys_reg(vcpu, r->reg, |=, 0);
5391 }
5392
5393 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
5394
5395 if (kvm_vcpu_has_pmu(vcpu))
5396 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
5397 }
5398
5399 /**
5400 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction
5401 * trap on a guest execution
5402 * @vcpu: The VCPU pointer
5403 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)5404 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
5405 {
5406 const struct sys_reg_desc *desc = NULL;
5407 struct sys_reg_params params;
5408 unsigned long esr = kvm_vcpu_get_esr(vcpu);
5409 int Rt = kvm_vcpu_sys_get_rt(vcpu);
5410 int sr_idx;
5411
5412 trace_kvm_handle_sys_reg(esr);
5413
5414 if (triage_sysreg_trap(vcpu, &sr_idx))
5415 return 1;
5416
5417 params = esr_sys64_to_params(esr);
5418 params.regval = vcpu_get_reg(vcpu, Rt);
5419
5420 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */
5421 if (params.Op0 == 2 || params.Op0 == 3)
5422 desc = &sys_reg_descs[sr_idx];
5423 else
5424 desc = &sys_insn_descs[sr_idx];
5425
5426 perform_access(vcpu, ¶ms, desc);
5427
5428 /* Read from system register? */
5429 if (!params.is_write &&
5430 (params.Op0 == 2 || params.Op0 == 3))
5431 vcpu_set_reg(vcpu, Rt, params.regval);
5432
5433 return 1;
5434 }
5435
5436 /******************************************************************************
5437 * Userspace API
5438 *****************************************************************************/
5439
index_to_params(u64 id,struct sys_reg_params * params)5440 static bool index_to_params(u64 id, struct sys_reg_params *params)
5441 {
5442 switch (id & KVM_REG_SIZE_MASK) {
5443 case KVM_REG_SIZE_U64:
5444 /* Any unused index bits means it's not valid. */
5445 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
5446 | KVM_REG_ARM_COPROC_MASK
5447 | KVM_REG_ARM64_SYSREG_OP0_MASK
5448 | KVM_REG_ARM64_SYSREG_OP1_MASK
5449 | KVM_REG_ARM64_SYSREG_CRN_MASK
5450 | KVM_REG_ARM64_SYSREG_CRM_MASK
5451 | KVM_REG_ARM64_SYSREG_OP2_MASK))
5452 return false;
5453 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
5454 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
5455 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
5456 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
5457 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
5458 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
5459 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
5460 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
5461 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
5462 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
5463 return true;
5464 default:
5465 return false;
5466 }
5467 }
5468
get_reg_by_id(u64 id,const struct sys_reg_desc table[],unsigned int num)5469 const struct sys_reg_desc *get_reg_by_id(u64 id,
5470 const struct sys_reg_desc table[],
5471 unsigned int num)
5472 {
5473 struct sys_reg_params params;
5474
5475 if (!index_to_params(id, ¶ms))
5476 return NULL;
5477
5478 return find_reg(¶ms, table, num);
5479 }
5480
5481 /* Decode an index value, and find the sys_reg_desc entry. */
5482 static const struct sys_reg_desc *
id_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id,const struct sys_reg_desc table[],unsigned int num)5483 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
5484 const struct sys_reg_desc table[], unsigned int num)
5485
5486 {
5487 const struct sys_reg_desc *r;
5488
5489 /* We only do sys_reg for now. */
5490 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
5491 return NULL;
5492
5493 r = get_reg_by_id(id, table, num);
5494
5495 /* Not saved in the sys_reg array and not otherwise accessible? */
5496 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
5497 r = NULL;
5498
5499 return r;
5500 }
5501
demux_c15_get(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)5502 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
5503 {
5504 u32 val;
5505 u32 __user *uval = uaddr;
5506
5507 /* Fail if we have unknown bits set. */
5508 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
5509 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
5510 return -ENOENT;
5511
5512 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
5513 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
5514 if (KVM_REG_SIZE(id) != 4)
5515 return -ENOENT;
5516 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
5517 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
5518 if (val >= CSSELR_MAX)
5519 return -ENOENT;
5520
5521 return put_user(get_ccsidr(vcpu, val), uval);
5522 default:
5523 return -ENOENT;
5524 }
5525 }
5526
demux_c15_set(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)5527 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
5528 {
5529 u32 val, newval;
5530 u32 __user *uval = uaddr;
5531
5532 /* Fail if we have unknown bits set. */
5533 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
5534 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
5535 return -ENOENT;
5536
5537 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
5538 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
5539 if (KVM_REG_SIZE(id) != 4)
5540 return -ENOENT;
5541 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
5542 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
5543 if (val >= CSSELR_MAX)
5544 return -ENOENT;
5545
5546 if (get_user(newval, uval))
5547 return -EFAULT;
5548
5549 return set_ccsidr(vcpu, val, newval);
5550 default:
5551 return -ENOENT;
5552 }
5553 }
5554
kvm_one_reg_to_id(const struct kvm_one_reg * reg)5555 static u64 kvm_one_reg_to_id(const struct kvm_one_reg *reg)
5556 {
5557 switch(reg->id) {
5558 case KVM_REG_ARM_TIMER_CVAL:
5559 return TO_ARM64_SYS_REG(CNTV_CVAL_EL0);
5560 case KVM_REG_ARM_TIMER_CNT:
5561 return TO_ARM64_SYS_REG(CNTVCT_EL0);
5562 default:
5563 return reg->id;
5564 }
5565 }
5566
kvm_sys_reg_get_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)5567 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
5568 const struct sys_reg_desc table[], unsigned int num)
5569 {
5570 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
5571 const struct sys_reg_desc *r;
5572 u64 id = kvm_one_reg_to_id(reg);
5573 u64 val;
5574 int ret;
5575
5576 r = id_to_sys_reg_desc(vcpu, id, table, num);
5577 if (!r || sysreg_hidden(vcpu, r))
5578 return -ENOENT;
5579
5580 if (r->get_user) {
5581 ret = (r->get_user)(vcpu, r, &val);
5582 } else {
5583 val = __vcpu_sys_reg(vcpu, r->reg);
5584 ret = 0;
5585 }
5586
5587 if (!ret)
5588 ret = put_user(val, uaddr);
5589
5590 return ret;
5591 }
5592
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)5593 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
5594 {
5595 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
5596
5597 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
5598 return demux_c15_get(vcpu, reg->id, uaddr);
5599
5600 return kvm_sys_reg_get_user(vcpu, reg,
5601 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
5602 }
5603
kvm_sys_reg_set_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)5604 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
5605 const struct sys_reg_desc table[], unsigned int num)
5606 {
5607 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
5608 const struct sys_reg_desc *r;
5609 u64 id = kvm_one_reg_to_id(reg);
5610 u64 val;
5611 int ret;
5612
5613 if (get_user(val, uaddr))
5614 return -EFAULT;
5615
5616 r = id_to_sys_reg_desc(vcpu, id, table, num);
5617 if (!r || sysreg_hidden(vcpu, r))
5618 return -ENOENT;
5619
5620 if (sysreg_user_write_ignore(vcpu, r))
5621 return 0;
5622
5623 if (r->set_user) {
5624 ret = (r->set_user)(vcpu, r, val);
5625 } else {
5626 __vcpu_assign_sys_reg(vcpu, r->reg, val);
5627 ret = 0;
5628 }
5629
5630 return ret;
5631 }
5632
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)5633 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
5634 {
5635 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
5636
5637 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
5638 return demux_c15_set(vcpu, reg->id, uaddr);
5639
5640 return kvm_sys_reg_set_user(vcpu, reg,
5641 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
5642 }
5643
num_demux_regs(void)5644 static unsigned int num_demux_regs(void)
5645 {
5646 return CSSELR_MAX;
5647 }
5648
write_demux_regids(u64 __user * uindices)5649 static int write_demux_regids(u64 __user *uindices)
5650 {
5651 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
5652 unsigned int i;
5653
5654 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
5655 for (i = 0; i < CSSELR_MAX; i++) {
5656 if (put_user(val | i, uindices))
5657 return -EFAULT;
5658 uindices++;
5659 }
5660 return 0;
5661 }
5662
sys_reg_to_index(const struct sys_reg_desc * reg)5663 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
5664 {
5665 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
5666 KVM_REG_ARM64_SYSREG |
5667 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
5668 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
5669 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
5670 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
5671 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
5672 }
5673
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)5674 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
5675 {
5676 u64 idx;
5677
5678 if (!*uind)
5679 return true;
5680
5681 switch (reg_to_encoding(reg)) {
5682 case SYS_CNTV_CVAL_EL0:
5683 idx = KVM_REG_ARM_TIMER_CVAL;
5684 break;
5685 case SYS_CNTVCT_EL0:
5686 idx = KVM_REG_ARM_TIMER_CNT;
5687 break;
5688 default:
5689 idx = sys_reg_to_index(reg);
5690 }
5691
5692 if (put_user(idx, *uind))
5693 return false;
5694
5695 (*uind)++;
5696 return true;
5697 }
5698
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)5699 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
5700 const struct sys_reg_desc *rd,
5701 u64 __user **uind,
5702 unsigned int *total)
5703 {
5704 /*
5705 * Ignore registers we trap but don't save,
5706 * and for which no custom user accessor is provided.
5707 */
5708 if (!(rd->reg || rd->get_user))
5709 return 0;
5710
5711 if (sysreg_hidden(vcpu, rd))
5712 return 0;
5713
5714 if (!copy_reg_to_user(rd, uind))
5715 return -EFAULT;
5716
5717 (*total)++;
5718 return 0;
5719 }
5720
5721 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)5722 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
5723 {
5724 const struct sys_reg_desc *i2, *end2;
5725 unsigned int total = 0;
5726 int err;
5727
5728 i2 = sys_reg_descs;
5729 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
5730
5731 while (i2 != end2) {
5732 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
5733 if (err)
5734 return err;
5735 }
5736 return total;
5737 }
5738
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)5739 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
5740 {
5741 return num_demux_regs()
5742 + walk_sys_regs(vcpu, (u64 __user *)NULL);
5743 }
5744
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)5745 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
5746 {
5747 int err;
5748
5749 err = walk_sys_regs(vcpu, uindices);
5750 if (err < 0)
5751 return err;
5752 uindices += err;
5753
5754 return write_demux_regids(uindices);
5755 }
5756
5757 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \
5758 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \
5759 sys_reg_Op1(r), \
5760 sys_reg_CRn(r), \
5761 sys_reg_CRm(r), \
5762 sys_reg_Op2(r))
5763
kvm_vm_ioctl_get_reg_writable_masks(struct kvm * kvm,struct reg_mask_range * range)5764 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range)
5765 {
5766 const void *zero_page = page_to_virt(ZERO_PAGE(0));
5767 u64 __user *masks = (u64 __user *)range->addr;
5768
5769 /* Only feature id range is supported, reserved[13] must be zero. */
5770 if (range->range ||
5771 memcmp(range->reserved, zero_page, sizeof(range->reserved)))
5772 return -EINVAL;
5773
5774 /* Wipe the whole thing first */
5775 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64)))
5776 return -EFAULT;
5777
5778 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
5779 const struct sys_reg_desc *reg = &sys_reg_descs[i];
5780 u32 encoding = reg_to_encoding(reg);
5781 u64 val;
5782
5783 if (!is_feature_id_reg(encoding) || !reg->set_user)
5784 continue;
5785
5786 if (!reg->val ||
5787 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) {
5788 continue;
5789 }
5790 val = reg->val;
5791
5792 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding))))
5793 return -EFAULT;
5794 }
5795
5796 return 0;
5797 }
5798
vcpu_set_hcr(struct kvm_vcpu * vcpu)5799 static void vcpu_set_hcr(struct kvm_vcpu *vcpu)
5800 {
5801 struct kvm *kvm = vcpu->kvm;
5802
5803 if (has_vhe() || has_hvhe())
5804 vcpu->arch.hcr_el2 |= HCR_E2H;
5805 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
5806 /* route synchronous external abort exceptions to EL2 */
5807 vcpu->arch.hcr_el2 |= HCR_TEA;
5808 /* trap error record accesses */
5809 vcpu->arch.hcr_el2 |= HCR_TERR;
5810 }
5811
5812 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
5813 vcpu->arch.hcr_el2 |= HCR_FWB;
5814
5815 if (cpus_have_final_cap(ARM64_HAS_EVT) &&
5816 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) &&
5817 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0))
5818 vcpu->arch.hcr_el2 |= HCR_TID4;
5819 else
5820 vcpu->arch.hcr_el2 |= HCR_TID2;
5821
5822 if (vcpu_el1_is_32bit(vcpu))
5823 vcpu->arch.hcr_el2 &= ~HCR_RW;
5824
5825 if (kvm_has_mte(vcpu->kvm))
5826 vcpu->arch.hcr_el2 |= HCR_ATA;
5827 else
5828 vcpu->arch.hcr_el2 |= HCR_TID5;
5829
5830 /*
5831 * In the absence of FGT, we cannot independently trap TLBI
5832 * Range instructions. This isn't great, but trapping all
5833 * TLBIs would be far worse. Live with it...
5834 */
5835 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
5836 vcpu->arch.hcr_el2 |= HCR_TTLBOS;
5837 }
5838
kvm_calculate_traps(struct kvm_vcpu * vcpu)5839 void kvm_calculate_traps(struct kvm_vcpu *vcpu)
5840 {
5841 struct kvm *kvm = vcpu->kvm;
5842
5843 mutex_lock(&kvm->arch.config_lock);
5844 vcpu_set_hcr(vcpu);
5845 vcpu_set_ich_hcr(vcpu);
5846 vcpu_set_hcrx(vcpu);
5847
5848 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags))
5849 goto out;
5850
5851 compute_fgu(kvm, HFGRTR_GROUP);
5852 compute_fgu(kvm, HFGITR_GROUP);
5853 compute_fgu(kvm, HDFGRTR_GROUP);
5854 compute_fgu(kvm, HAFGRTR_GROUP);
5855 compute_fgu(kvm, HFGRTR2_GROUP);
5856 compute_fgu(kvm, HFGITR2_GROUP);
5857 compute_fgu(kvm, HDFGRTR2_GROUP);
5858 compute_fgu(kvm, ICH_HFGRTR_GROUP);
5859 compute_fgu(kvm, ICH_HFGITR_GROUP);
5860
5861 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
5862 out:
5863 mutex_unlock(&kvm->arch.config_lock);
5864 }
5865
5866 /*
5867 * Perform last adjustments to the ID registers that are implied by the
5868 * configuration outside of the ID regs themselves, as well as any
5869 * initialisation that directly depend on these ID registers (such as
5870 * RES0/RES1 behaviours). This is not the place to configure traps though.
5871 *
5872 * Because this can be called once per CPU, changes must be idempotent.
5873 */
kvm_finalize_sys_regs(struct kvm_vcpu * vcpu)5874 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu)
5875 {
5876 struct kvm *kvm = vcpu->kvm;
5877
5878 guard(mutex)(&kvm->arch.config_lock);
5879
5880 if (vcpu_has_nv(vcpu)) {
5881 int ret = kvm_init_nv_sysregs(vcpu);
5882 if (ret)
5883 return ret;
5884 }
5885
5886 if (kvm_vm_has_ran_once(kvm))
5887 return 0;
5888
5889 /*
5890 * This hacks into the ID registers, so only perform it when the
5891 * first vcpu runs, or the kvm_set_vm_id_reg() helper will scream.
5892 */
5893 if (!irqchip_in_kernel(kvm)) {
5894 u64 val;
5895
5896 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1) & ~ID_AA64PFR0_EL1_GIC;
5897 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, val);
5898 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1) & ~ID_AA64PFR2_EL1_GCIE;
5899 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1, val);
5900 val = kvm_read_vm_id_reg(kvm, SYS_ID_PFR1_EL1) & ~ID_PFR1_EL1_GIC;
5901 kvm_set_vm_id_reg(kvm, SYS_ID_PFR1_EL1, val);
5902 } else {
5903 /*
5904 * Certain userspace software - QEMU - samples the system
5905 * register state without creating an irqchip, then blindly
5906 * restores the state prior to running the final guest. This
5907 * means that it restores the virtualization & emulation
5908 * capabilities of the host system, rather than something that
5909 * reflects the final guest state. Moreover, it checks that the
5910 * state was "correctly" restored (i.e., verbatim), bailing if
5911 * it isn't, so masking off invalid state isn't an option.
5912 *
5913 * On GICv5 hardware that supports FEAT_GCIE_LEGACY we can run
5914 * both GICv3- and GICv5-based guests. Therefore, we initially
5915 * present both ID_AA64PFR0.GIC and ID_AA64PFR2.GCIE as IMP to
5916 * reflect that userspace can create EITHER a vGICv3 or a
5917 * vGICv5. This is an architecturally invalid combination, of
5918 * course. Once an in-kernel GIC is created, the sysreg state is
5919 * updated to reflect the actual, valid configuration.
5920 *
5921 * Setting both the GIC and GCIE features to IMP unsurprisingly
5922 * results in guests falling over, and hence we need to fix up
5923 * this mess in KVM. Before running for the first time we yet
5924 * again ensure that the GIC and GCIE fields accurately reflect
5925 * the actual hardware the guest should see.
5926 *
5927 * This hack allows legacy QEMU-based GICv3 guests to run
5928 * unmodified on compatible GICv5 hosts, and avoids the inverse
5929 * problem for GICv5-based guests in the future.
5930 */
5931 kvm_vgic_finalize_idregs(kvm);
5932 }
5933
5934 return 0;
5935 }
5936
kvm_sys_reg_table_init(void)5937 int __init kvm_sys_reg_table_init(void)
5938 {
5939 const struct sys_reg_desc *gicv3_regs;
5940 bool valid = true;
5941 unsigned int i, sz;
5942 int ret = 0;
5943
5944 /* Make sure tables are unique and in order. */
5945 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), true);
5946 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), false);
5947 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), false);
5948 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), false);
5949 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), false);
5950 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false);
5951
5952 gicv3_regs = vgic_v3_get_sysreg_table(&sz);
5953 valid &= check_sysreg_table(gicv3_regs, sz, false);
5954
5955 if (!valid)
5956 return -EINVAL;
5957
5958 init_imp_id_regs();
5959
5960 ret = populate_nv_trap_config();
5961
5962 check_feature_map();
5963
5964 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++)
5965 ret = populate_sysreg_config(sys_reg_descs + i, i);
5966
5967 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++)
5968 ret = populate_sysreg_config(sys_insn_descs + i, i);
5969
5970 return ret;
5971 }
5972