1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern bool host_cpu_is_hygon; 25 extern bool host_cpu_is_amd_compatible; 26 extern uint64_t guest_tsc_khz; 27 28 #ifndef MAX_NR_CPUID_ENTRIES 29 #define MAX_NR_CPUID_ENTRIES 100 30 #endif 31 32 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 33 34 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 35 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 36 37 #define NMI_VECTOR 0x02 38 39 const char *ex_str(int vector); 40 41 #define X86_EFLAGS_FIXED (1u << 1) 42 43 #define X86_CR4_VME (1ul << 0) 44 #define X86_CR4_PVI (1ul << 1) 45 #define X86_CR4_TSD (1ul << 2) 46 #define X86_CR4_DE (1ul << 3) 47 #define X86_CR4_PSE (1ul << 4) 48 #define X86_CR4_PAE (1ul << 5) 49 #define X86_CR4_MCE (1ul << 6) 50 #define X86_CR4_PGE (1ul << 7) 51 #define X86_CR4_PCE (1ul << 8) 52 #define X86_CR4_OSFXSR (1ul << 9) 53 #define X86_CR4_OSXMMEXCPT (1ul << 10) 54 #define X86_CR4_UMIP (1ul << 11) 55 #define X86_CR4_LA57 (1ul << 12) 56 #define X86_CR4_VMXE (1ul << 13) 57 #define X86_CR4_SMXE (1ul << 14) 58 #define X86_CR4_FSGSBASE (1ul << 16) 59 #define X86_CR4_PCIDE (1ul << 17) 60 #define X86_CR4_OSXSAVE (1ul << 18) 61 #define X86_CR4_SMEP (1ul << 20) 62 #define X86_CR4_SMAP (1ul << 21) 63 #define X86_CR4_PKE (1ul << 22) 64 65 struct xstate_header { 66 u64 xstate_bv; 67 u64 xcomp_bv; 68 u64 reserved[6]; 69 } __attribute__((packed)); 70 71 struct xstate { 72 u8 i387[512]; 73 struct xstate_header header; 74 u8 extended_state_area[0]; 75 } __attribute__ ((packed, aligned (64))); 76 77 #define XFEATURE_MASK_FP BIT_ULL(0) 78 #define XFEATURE_MASK_SSE BIT_ULL(1) 79 #define XFEATURE_MASK_YMM BIT_ULL(2) 80 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 81 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 82 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 83 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 84 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 85 #define XFEATURE_MASK_PT BIT_ULL(8) 86 #define XFEATURE_MASK_PKRU BIT_ULL(9) 87 #define XFEATURE_MASK_PASID BIT_ULL(10) 88 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 89 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 90 #define XFEATURE_MASK_LBR BIT_ULL(15) 91 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 92 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 93 94 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 95 XFEATURE_MASK_ZMM_Hi256 | \ 96 XFEATURE_MASK_Hi16_ZMM) 97 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 98 XFEATURE_MASK_XTILE_CFG) 99 100 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 101 enum cpuid_output_regs { 102 KVM_CPUID_EAX, 103 KVM_CPUID_EBX, 104 KVM_CPUID_ECX, 105 KVM_CPUID_EDX 106 }; 107 108 /* 109 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 110 * passed by value with no overhead. 111 */ 112 struct kvm_x86_cpu_feature { 113 u32 function; 114 u16 index; 115 u8 reg; 116 u8 bit; 117 }; 118 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 119 ({ \ 120 struct kvm_x86_cpu_feature feature = { \ 121 .function = fn, \ 122 .index = idx, \ 123 .reg = KVM_CPUID_##gpr, \ 124 .bit = __bit, \ 125 }; \ 126 \ 127 kvm_static_assert((fn & 0xc0000000) == 0 || \ 128 (fn & 0xc0000000) == 0x40000000 || \ 129 (fn & 0xc0000000) == 0x80000000 || \ 130 (fn & 0xc0000000) == 0xc0000000); \ 131 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 132 feature; \ 133 }) 134 135 /* 136 * Basic Leafs, a.k.a. Intel defined 137 */ 138 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 139 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 140 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 141 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 142 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 143 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 144 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 145 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 146 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 147 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 148 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 149 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 150 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 151 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 152 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 153 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 154 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 155 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 156 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 157 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 158 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 159 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 160 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 161 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 162 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 163 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 164 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 165 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 166 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 167 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 168 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 169 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 170 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 171 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 172 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 173 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 174 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 175 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 176 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 177 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 178 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 179 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 180 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 181 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 182 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 183 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 184 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 185 186 /* 187 * Extended Leafs, a.k.a. AMD defined 188 */ 189 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 190 #define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) 191 #define X86_FEATURE_PERFCTR_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) 192 #define X86_FEATURE_PERFCTR_LLC KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) 193 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 194 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 195 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 196 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 197 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 198 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 199 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 200 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 201 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 202 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 203 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 204 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 205 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 206 #define X86_FEATURE_V_VMSAVE_VMLOAD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 15) 207 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 208 #define X86_FEATURE_IDLE_HLT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 30) 209 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 210 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 211 #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) 212 #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) 213 #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) 214 215 /* 216 * KVM defined paravirt features. 217 */ 218 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 219 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 220 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 221 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 222 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 223 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 224 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 225 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 226 /* Bit 8 apparently isn't used?!?! */ 227 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 228 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 229 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 230 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 231 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 232 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 233 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 234 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 235 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 236 237 /* 238 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 239 * value/property as opposed to a single-bit feature. Again, pack the info 240 * into a 64-bit value to pass by value with no overhead. 241 */ 242 struct kvm_x86_cpu_property { 243 u32 function; 244 u8 index; 245 u8 reg; 246 u8 lo_bit; 247 u8 hi_bit; 248 }; 249 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 250 ({ \ 251 struct kvm_x86_cpu_property property = { \ 252 .function = fn, \ 253 .index = idx, \ 254 .reg = KVM_CPUID_##gpr, \ 255 .lo_bit = low_bit, \ 256 .hi_bit = high_bit, \ 257 }; \ 258 \ 259 kvm_static_assert(low_bit < high_bit); \ 260 kvm_static_assert((fn & 0xc0000000) == 0 || \ 261 (fn & 0xc0000000) == 0x40000000 || \ 262 (fn & 0xc0000000) == 0x80000000 || \ 263 (fn & 0xc0000000) == 0xc0000000); \ 264 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 265 property; \ 266 }) 267 268 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 269 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 270 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 271 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 272 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 273 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 12) 274 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 275 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 276 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 277 278 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 279 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 280 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 281 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 282 283 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 284 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 285 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 286 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 287 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 288 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 289 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 290 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 291 292 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 293 294 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 295 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 296 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 297 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 298 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 299 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 300 #define X86_PROPERTY_NR_PERFCTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) 301 #define X86_PROPERTY_NR_PERFCTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) 302 303 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 304 305 /* 306 * Intel's architectural PMU events are bizarre. They have a "feature" bit 307 * that indicates the feature is _not_ supported, and a property that states 308 * the length of the bit mask of unsupported features. A feature is supported 309 * if the size of the bit mask is larger than the "unavailable" bit, and said 310 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 311 * arch events for general purpose counters. Fixed counters are supported if a 312 * feature flag is set **OR** the total number of fixed counters is greater 313 * than index of the counter. 314 * 315 * Wrap the events for general purpose and fixed counters to simplify checking 316 * whether or not a given architectural event is supported. 317 */ 318 struct kvm_x86_pmu_feature { 319 struct kvm_x86_cpu_feature f; 320 }; 321 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 322 ({ \ 323 struct kvm_x86_pmu_feature feature = { \ 324 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 325 }; \ 326 \ 327 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 328 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 329 feature; \ 330 }) 331 332 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 333 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 334 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 335 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 336 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 337 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 338 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 339 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 340 #define X86_PMU_FEATURE_TOPDOWN_BE_BOUND KVM_X86_PMU_FEATURE(EBX, 8) 341 #define X86_PMU_FEATURE_TOPDOWN_BAD_SPEC KVM_X86_PMU_FEATURE(EBX, 9) 342 #define X86_PMU_FEATURE_TOPDOWN_FE_BOUND KVM_X86_PMU_FEATURE(EBX, 10) 343 #define X86_PMU_FEATURE_TOPDOWN_RETIRING KVM_X86_PMU_FEATURE(EBX, 11) 344 #define X86_PMU_FEATURE_LBR_INSERTS KVM_X86_PMU_FEATURE(EBX, 12) 345 346 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 347 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 348 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 349 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 350 351 static inline unsigned int x86_family(unsigned int eax) 352 { 353 unsigned int x86; 354 355 x86 = (eax >> 8) & 0xf; 356 357 if (x86 == 0xf) 358 x86 += (eax >> 20) & 0xff; 359 360 return x86; 361 } 362 363 static inline unsigned int x86_model(unsigned int eax) 364 { 365 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 366 } 367 368 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 369 370 #define PAGE_SHIFT 12 371 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 372 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 373 374 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 375 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 376 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 377 378 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 379 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 380 381 /* General Registers in 64-Bit Mode */ 382 struct gpr64_regs { 383 u64 rax; 384 u64 rcx; 385 u64 rdx; 386 u64 rbx; 387 u64 rsp; 388 u64 rbp; 389 u64 rsi; 390 u64 rdi; 391 u64 r8; 392 u64 r9; 393 u64 r10; 394 u64 r11; 395 u64 r12; 396 u64 r13; 397 u64 r14; 398 u64 r15; 399 }; 400 401 struct desc64 { 402 uint16_t limit0; 403 uint16_t base0; 404 unsigned base1:8, type:4, s:1, dpl:2, p:1; 405 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 406 uint32_t base3; 407 uint32_t zero1; 408 } __attribute__((packed)); 409 410 struct desc_ptr { 411 uint16_t size; 412 uint64_t address; 413 } __attribute__((packed)); 414 415 struct kvm_x86_state { 416 struct kvm_xsave *xsave; 417 struct kvm_vcpu_events events; 418 struct kvm_mp_state mp_state; 419 struct kvm_regs regs; 420 struct kvm_xcrs xcrs; 421 struct kvm_sregs sregs; 422 struct kvm_debugregs debugregs; 423 union { 424 struct kvm_nested_state nested; 425 char nested_[16384]; 426 }; 427 struct kvm_msrs msrs; 428 }; 429 430 static inline uint64_t get_desc64_base(const struct desc64 *desc) 431 { 432 return (uint64_t)desc->base3 << 32 | 433 (uint64_t)desc->base2 << 24 | 434 (uint64_t)desc->base1 << 16 | 435 (uint64_t)desc->base0; 436 } 437 438 static inline uint64_t rdtsc(void) 439 { 440 uint32_t eax, edx; 441 uint64_t tsc_val; 442 /* 443 * The lfence is to wait (on Intel CPUs) until all previous 444 * instructions have been executed. If software requires RDTSC to be 445 * executed prior to execution of any subsequent instruction, it can 446 * execute LFENCE immediately after RDTSC 447 */ 448 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 449 tsc_val = ((uint64_t)edx) << 32 | eax; 450 return tsc_val; 451 } 452 453 static inline uint64_t rdtscp(uint32_t *aux) 454 { 455 uint32_t eax, edx; 456 457 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 458 return ((uint64_t)edx) << 32 | eax; 459 } 460 461 static inline uint64_t rdmsr(uint32_t msr) 462 { 463 uint32_t a, d; 464 465 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 466 467 return a | ((uint64_t) d << 32); 468 } 469 470 static inline void wrmsr(uint32_t msr, uint64_t value) 471 { 472 uint32_t a = value; 473 uint32_t d = value >> 32; 474 475 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 476 } 477 478 479 static inline uint16_t inw(uint16_t port) 480 { 481 uint16_t tmp; 482 483 __asm__ __volatile__("in %%dx, %%ax" 484 : /* output */ "=a" (tmp) 485 : /* input */ "d" (port)); 486 487 return tmp; 488 } 489 490 static inline uint16_t get_es(void) 491 { 492 uint16_t es; 493 494 __asm__ __volatile__("mov %%es, %[es]" 495 : /* output */ [es]"=rm"(es)); 496 return es; 497 } 498 499 static inline uint16_t get_cs(void) 500 { 501 uint16_t cs; 502 503 __asm__ __volatile__("mov %%cs, %[cs]" 504 : /* output */ [cs]"=rm"(cs)); 505 return cs; 506 } 507 508 static inline uint16_t get_ss(void) 509 { 510 uint16_t ss; 511 512 __asm__ __volatile__("mov %%ss, %[ss]" 513 : /* output */ [ss]"=rm"(ss)); 514 return ss; 515 } 516 517 static inline uint16_t get_ds(void) 518 { 519 uint16_t ds; 520 521 __asm__ __volatile__("mov %%ds, %[ds]" 522 : /* output */ [ds]"=rm"(ds)); 523 return ds; 524 } 525 526 static inline uint16_t get_fs(void) 527 { 528 uint16_t fs; 529 530 __asm__ __volatile__("mov %%fs, %[fs]" 531 : /* output */ [fs]"=rm"(fs)); 532 return fs; 533 } 534 535 static inline uint16_t get_gs(void) 536 { 537 uint16_t gs; 538 539 __asm__ __volatile__("mov %%gs, %[gs]" 540 : /* output */ [gs]"=rm"(gs)); 541 return gs; 542 } 543 544 static inline uint16_t get_tr(void) 545 { 546 uint16_t tr; 547 548 __asm__ __volatile__("str %[tr]" 549 : /* output */ [tr]"=rm"(tr)); 550 return tr; 551 } 552 553 static inline uint64_t get_cr0(void) 554 { 555 uint64_t cr0; 556 557 __asm__ __volatile__("mov %%cr0, %[cr0]" 558 : /* output */ [cr0]"=r"(cr0)); 559 return cr0; 560 } 561 562 static inline void set_cr0(uint64_t val) 563 { 564 __asm__ __volatile__("mov %0, %%cr0" : : "r" (val) : "memory"); 565 } 566 567 static inline uint64_t get_cr3(void) 568 { 569 uint64_t cr3; 570 571 __asm__ __volatile__("mov %%cr3, %[cr3]" 572 : /* output */ [cr3]"=r"(cr3)); 573 return cr3; 574 } 575 576 static inline void set_cr3(uint64_t val) 577 { 578 __asm__ __volatile__("mov %0, %%cr3" : : "r" (val) : "memory"); 579 } 580 581 static inline uint64_t get_cr4(void) 582 { 583 uint64_t cr4; 584 585 __asm__ __volatile__("mov %%cr4, %[cr4]" 586 : /* output */ [cr4]"=r"(cr4)); 587 return cr4; 588 } 589 590 static inline void set_cr4(uint64_t val) 591 { 592 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 593 } 594 595 static inline uint64_t get_cr8(void) 596 { 597 uint64_t cr8; 598 599 __asm__ __volatile__("mov %%cr8, %[cr8]" : [cr8]"=r"(cr8)); 600 return cr8; 601 } 602 603 static inline void set_cr8(uint64_t val) 604 { 605 __asm__ __volatile__("mov %0, %%cr8" : : "r" (val) : "memory"); 606 } 607 608 static inline void set_idt(const struct desc_ptr *idt_desc) 609 { 610 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 611 } 612 613 static inline u64 xgetbv(u32 index) 614 { 615 u32 eax, edx; 616 617 __asm__ __volatile__("xgetbv;" 618 : "=a" (eax), "=d" (edx) 619 : "c" (index)); 620 return eax | ((u64)edx << 32); 621 } 622 623 static inline void xsetbv(u32 index, u64 value) 624 { 625 u32 eax = value; 626 u32 edx = value >> 32; 627 628 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 629 } 630 631 static inline void wrpkru(u32 pkru) 632 { 633 /* Note, ECX and EDX are architecturally required to be '0'. */ 634 asm volatile(".byte 0x0f,0x01,0xef\n\t" 635 : : "a" (pkru), "c"(0), "d"(0)); 636 } 637 638 static inline struct desc_ptr get_gdt(void) 639 { 640 struct desc_ptr gdt; 641 __asm__ __volatile__("sgdt %[gdt]" 642 : /* output */ [gdt]"=m"(gdt)); 643 return gdt; 644 } 645 646 static inline struct desc_ptr get_idt(void) 647 { 648 struct desc_ptr idt; 649 __asm__ __volatile__("sidt %[idt]" 650 : /* output */ [idt]"=m"(idt)); 651 return idt; 652 } 653 654 static inline void outl(uint16_t port, uint32_t value) 655 { 656 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 657 } 658 659 static inline void __cpuid(uint32_t function, uint32_t index, 660 uint32_t *eax, uint32_t *ebx, 661 uint32_t *ecx, uint32_t *edx) 662 { 663 *eax = function; 664 *ecx = index; 665 666 asm volatile("cpuid" 667 : "=a" (*eax), 668 "=b" (*ebx), 669 "=c" (*ecx), 670 "=d" (*edx) 671 : "0" (*eax), "2" (*ecx) 672 : "memory"); 673 } 674 675 static inline void cpuid(uint32_t function, 676 uint32_t *eax, uint32_t *ebx, 677 uint32_t *ecx, uint32_t *edx) 678 { 679 return __cpuid(function, 0, eax, ebx, ecx, edx); 680 } 681 682 static inline uint32_t this_cpu_fms(void) 683 { 684 uint32_t eax, ebx, ecx, edx; 685 686 cpuid(1, &eax, &ebx, &ecx, &edx); 687 return eax; 688 } 689 690 static inline uint32_t this_cpu_family(void) 691 { 692 return x86_family(this_cpu_fms()); 693 } 694 695 static inline uint32_t this_cpu_model(void) 696 { 697 return x86_model(this_cpu_fms()); 698 } 699 700 static inline bool this_cpu_vendor_string_is(const char *vendor) 701 { 702 const uint32_t *chunk = (const uint32_t *)vendor; 703 uint32_t eax, ebx, ecx, edx; 704 705 cpuid(0, &eax, &ebx, &ecx, &edx); 706 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 707 } 708 709 static inline bool this_cpu_is_intel(void) 710 { 711 return this_cpu_vendor_string_is("GenuineIntel"); 712 } 713 714 /* 715 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 716 */ 717 static inline bool this_cpu_is_amd(void) 718 { 719 return this_cpu_vendor_string_is("AuthenticAMD"); 720 } 721 722 static inline bool this_cpu_is_hygon(void) 723 { 724 return this_cpu_vendor_string_is("HygonGenuine"); 725 } 726 727 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index, 728 uint8_t reg, uint8_t lo, uint8_t hi) 729 { 730 uint32_t gprs[4]; 731 732 __cpuid(function, index, 733 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 734 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 735 736 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 737 } 738 739 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 740 { 741 return __this_cpu_has(feature.function, feature.index, 742 feature.reg, feature.bit, feature.bit); 743 } 744 745 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property) 746 { 747 return __this_cpu_has(property.function, property.index, 748 property.reg, property.lo_bit, property.hi_bit); 749 } 750 751 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 752 { 753 uint32_t max_leaf; 754 755 switch (property.function & 0xc0000000) { 756 case 0: 757 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 758 break; 759 case 0x40000000: 760 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 761 break; 762 case 0x80000000: 763 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 764 break; 765 case 0xc0000000: 766 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 767 } 768 return max_leaf >= property.function; 769 } 770 771 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 772 { 773 uint32_t nr_bits; 774 775 if (feature.f.reg == KVM_CPUID_EBX) { 776 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 777 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 778 } 779 780 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 781 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 782 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 783 } 784 785 static __always_inline uint64_t this_cpu_supported_xcr0(void) 786 { 787 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 788 return 0; 789 790 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 791 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 792 } 793 794 typedef u32 __attribute__((vector_size(16))) sse128_t; 795 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 796 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 797 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 798 799 static inline void read_sse_reg(int reg, sse128_t *data) 800 { 801 switch (reg) { 802 case 0: 803 asm("movdqa %%xmm0, %0" : "=m"(*data)); 804 break; 805 case 1: 806 asm("movdqa %%xmm1, %0" : "=m"(*data)); 807 break; 808 case 2: 809 asm("movdqa %%xmm2, %0" : "=m"(*data)); 810 break; 811 case 3: 812 asm("movdqa %%xmm3, %0" : "=m"(*data)); 813 break; 814 case 4: 815 asm("movdqa %%xmm4, %0" : "=m"(*data)); 816 break; 817 case 5: 818 asm("movdqa %%xmm5, %0" : "=m"(*data)); 819 break; 820 case 6: 821 asm("movdqa %%xmm6, %0" : "=m"(*data)); 822 break; 823 case 7: 824 asm("movdqa %%xmm7, %0" : "=m"(*data)); 825 break; 826 default: 827 BUG(); 828 } 829 } 830 831 static inline void write_sse_reg(int reg, const sse128_t *data) 832 { 833 switch (reg) { 834 case 0: 835 asm("movdqa %0, %%xmm0" : : "m"(*data)); 836 break; 837 case 1: 838 asm("movdqa %0, %%xmm1" : : "m"(*data)); 839 break; 840 case 2: 841 asm("movdqa %0, %%xmm2" : : "m"(*data)); 842 break; 843 case 3: 844 asm("movdqa %0, %%xmm3" : : "m"(*data)); 845 break; 846 case 4: 847 asm("movdqa %0, %%xmm4" : : "m"(*data)); 848 break; 849 case 5: 850 asm("movdqa %0, %%xmm5" : : "m"(*data)); 851 break; 852 case 6: 853 asm("movdqa %0, %%xmm6" : : "m"(*data)); 854 break; 855 case 7: 856 asm("movdqa %0, %%xmm7" : : "m"(*data)); 857 break; 858 default: 859 BUG(); 860 } 861 } 862 863 static inline void cpu_relax(void) 864 { 865 asm volatile("rep; nop" ::: "memory"); 866 } 867 868 static inline void udelay(unsigned long usec) 869 { 870 uint64_t start, now, cycles; 871 872 GUEST_ASSERT(guest_tsc_khz); 873 cycles = guest_tsc_khz / 1000 * usec; 874 875 /* 876 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 877 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 878 */ 879 start = rdtsc(); 880 do { 881 now = rdtsc(); 882 } while (now - start < cycles); 883 } 884 885 #define ud2() \ 886 __asm__ __volatile__( \ 887 "ud2\n" \ 888 ) 889 890 #define hlt() \ 891 __asm__ __volatile__( \ 892 "hlt\n" \ 893 ) 894 895 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 896 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 897 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 898 899 const struct kvm_msr_list *kvm_get_msr_index_list(void); 900 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 901 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index); 902 uint64_t kvm_get_feature_msr(uint64_t msr_index); 903 904 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 905 struct kvm_msrs *msrs) 906 { 907 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 908 909 TEST_ASSERT(r == msrs->nmsrs, 910 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 911 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 912 } 913 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 914 { 915 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 916 917 TEST_ASSERT(r == msrs->nmsrs, 918 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 919 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 920 } 921 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 922 struct kvm_debugregs *debugregs) 923 { 924 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 925 } 926 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 927 struct kvm_debugregs *debugregs) 928 { 929 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 930 } 931 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 932 struct kvm_xsave *xsave) 933 { 934 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 935 } 936 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 937 struct kvm_xsave *xsave) 938 { 939 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 940 } 941 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 942 struct kvm_xsave *xsave) 943 { 944 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 945 } 946 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 947 struct kvm_xcrs *xcrs) 948 { 949 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 950 } 951 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 952 { 953 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 954 } 955 956 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 957 uint32_t function, uint32_t index); 958 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 959 960 static inline uint32_t kvm_cpu_fms(void) 961 { 962 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 963 } 964 965 static inline uint32_t kvm_cpu_family(void) 966 { 967 return x86_family(kvm_cpu_fms()); 968 } 969 970 static inline uint32_t kvm_cpu_model(void) 971 { 972 return x86_model(kvm_cpu_fms()); 973 } 974 975 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 976 struct kvm_x86_cpu_feature feature); 977 978 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 979 { 980 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 981 } 982 983 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 984 struct kvm_x86_cpu_property property); 985 986 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property) 987 { 988 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 989 } 990 991 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 992 { 993 uint32_t max_leaf; 994 995 switch (property.function & 0xc0000000) { 996 case 0: 997 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 998 break; 999 case 0x40000000: 1000 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 1001 break; 1002 case 0x80000000: 1003 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 1004 break; 1005 case 0xc0000000: 1006 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 1007 } 1008 return max_leaf >= property.function; 1009 } 1010 1011 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 1012 { 1013 uint32_t nr_bits; 1014 1015 if (feature.f.reg == KVM_CPUID_EBX) { 1016 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 1017 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 1018 } 1019 1020 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 1021 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 1022 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 1023 } 1024 1025 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) 1026 { 1027 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 1028 return 0; 1029 1030 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 1031 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 1032 } 1033 1034 static inline size_t kvm_cpuid2_size(int nr_entries) 1035 { 1036 return sizeof(struct kvm_cpuid2) + 1037 sizeof(struct kvm_cpuid_entry2) * nr_entries; 1038 } 1039 1040 /* 1041 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1042 * entries sized to hold @nr_entries. The caller is responsible for freeing 1043 * the struct. 1044 */ 1045 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1046 { 1047 struct kvm_cpuid2 *cpuid; 1048 1049 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1050 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1051 1052 cpuid->nent = nr_entries; 1053 1054 return cpuid; 1055 } 1056 1057 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1058 1059 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1060 { 1061 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1062 } 1063 1064 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1065 uint32_t function, 1066 uint32_t index) 1067 { 1068 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1069 1070 vcpu_get_cpuid(vcpu); 1071 1072 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1073 function, index); 1074 } 1075 1076 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1077 uint32_t function) 1078 { 1079 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1080 } 1081 1082 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1083 { 1084 int r; 1085 1086 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1087 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1088 if (r) 1089 return r; 1090 1091 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1092 vcpu_get_cpuid(vcpu); 1093 return 0; 1094 } 1095 1096 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1097 { 1098 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1099 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1100 1101 /* Refresh the cache to pick up adjustments made by KVM. */ 1102 vcpu_get_cpuid(vcpu); 1103 } 1104 1105 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1106 struct kvm_x86_cpu_property property, 1107 uint32_t value); 1108 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); 1109 1110 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); 1111 1112 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1113 struct kvm_x86_cpu_feature feature) 1114 { 1115 struct kvm_cpuid_entry2 *entry; 1116 1117 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1118 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1119 } 1120 1121 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1122 struct kvm_x86_cpu_feature feature, 1123 bool set); 1124 1125 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1126 struct kvm_x86_cpu_feature feature) 1127 { 1128 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1129 1130 } 1131 1132 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1133 struct kvm_x86_cpu_feature feature) 1134 { 1135 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1136 } 1137 1138 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index); 1139 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value); 1140 1141 /* 1142 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1143 * Note, the caller provides the stringified name so that the name of macro is 1144 * printed, not the value the macro resolves to (due to macro expansion). 1145 */ 1146 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1147 do { \ 1148 if (__builtin_constant_p(msr)) { \ 1149 TEST_ASSERT(cond, fmt, str, args); \ 1150 } else if (!(cond)) { \ 1151 char buf[16]; \ 1152 \ 1153 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1154 TEST_ASSERT(cond, fmt, buf, args); \ 1155 } \ 1156 } while (0) 1157 1158 /* 1159 * Returns true if KVM should return the last written value when reading an MSR 1160 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1161 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1162 * out MSRs that are not durable _and_ that a selftest wants to write. 1163 */ 1164 static inline bool is_durable_msr(uint32_t msr) 1165 { 1166 return msr != MSR_IA32_TSC; 1167 } 1168 1169 #define vcpu_set_msr(vcpu, msr, val) \ 1170 do { \ 1171 uint64_t r, v = val; \ 1172 \ 1173 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1174 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1175 if (!is_durable_msr(msr)) \ 1176 break; \ 1177 r = vcpu_get_msr(vcpu, msr); \ 1178 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1179 } while (0) 1180 1181 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1182 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1183 1184 struct ex_regs { 1185 uint64_t rax, rcx, rdx, rbx; 1186 uint64_t rbp, rsi, rdi; 1187 uint64_t r8, r9, r10, r11; 1188 uint64_t r12, r13, r14, r15; 1189 uint64_t vector; 1190 uint64_t error_code; 1191 uint64_t rip; 1192 uint64_t cs; 1193 uint64_t rflags; 1194 }; 1195 1196 struct idt_entry { 1197 uint16_t offset0; 1198 uint16_t selector; 1199 uint16_t ist : 3; 1200 uint16_t : 5; 1201 uint16_t type : 4; 1202 uint16_t : 1; 1203 uint16_t dpl : 2; 1204 uint16_t p : 1; 1205 uint16_t offset1; 1206 uint32_t offset2; uint32_t reserved; 1207 }; 1208 1209 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1210 void (*handler)(struct ex_regs *)); 1211 1212 /* 1213 * Exception fixup morphs #DE to an arbitrary magic vector so that '0' can be 1214 * used to signal "no expcetion". 1215 */ 1216 #define KVM_MAGIC_DE_VECTOR 0xff 1217 1218 /* If a toddler were to say "abracadabra". */ 1219 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1220 1221 /* 1222 * KVM selftest exception fixup uses registers to coordinate with the exception 1223 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1224 * per-CPU data. Using only registers avoids having to map memory into the 1225 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1226 * for recursive faults when accessing memory in the handler. The downside to 1227 * using registers is that it restricts what registers can be used by the actual 1228 * instruction. But, selftests are 64-bit only, making register* pressure a 1229 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1230 * by the callee, and except for r11 are not implicit parameters to any 1231 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1232 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1233 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1234 * 1235 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1236 * is guaranteed to be non-zero on fault. 1237 * 1238 * REGISTER INPUTS: 1239 * r9 = MAGIC 1240 * r10 = RIP 1241 * r11 = new RIP on fault 1242 * 1243 * REGISTER OUTPUTS: 1244 * r9 = exception vector (non-zero) 1245 * r10 = error code 1246 */ 1247 #define __KVM_ASM_SAFE(insn, fep) \ 1248 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1249 "lea 1f(%%rip), %%r10\n\t" \ 1250 "lea 2f(%%rip), %%r11\n\t" \ 1251 fep "1: " insn "\n\t" \ 1252 "xor %%r9, %%r9\n\t" \ 1253 "2:\n\t" \ 1254 "mov %%r9b, %[vector]\n\t" \ 1255 "mov %%r10, %[error_code]\n\t" 1256 1257 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1258 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1259 1260 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1261 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1262 1263 #define kvm_asm_safe(insn, inputs...) \ 1264 ({ \ 1265 uint64_t ign_error_code; \ 1266 uint8_t vector; \ 1267 \ 1268 asm volatile(KVM_ASM_SAFE(insn) \ 1269 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1270 : inputs \ 1271 : KVM_ASM_SAFE_CLOBBERS); \ 1272 vector; \ 1273 }) 1274 1275 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1276 ({ \ 1277 uint8_t vector; \ 1278 \ 1279 asm volatile(KVM_ASM_SAFE(insn) \ 1280 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1281 : inputs \ 1282 : KVM_ASM_SAFE_CLOBBERS); \ 1283 vector; \ 1284 }) 1285 1286 #define kvm_asm_safe_fep(insn, inputs...) \ 1287 ({ \ 1288 uint64_t ign_error_code; \ 1289 uint8_t vector; \ 1290 \ 1291 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1292 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1293 : inputs \ 1294 : KVM_ASM_SAFE_CLOBBERS); \ 1295 vector; \ 1296 }) 1297 1298 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1299 ({ \ 1300 uint8_t vector; \ 1301 \ 1302 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1303 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1304 : inputs \ 1305 : KVM_ASM_SAFE_CLOBBERS); \ 1306 vector; \ 1307 }) 1308 1309 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1310 static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \ 1311 { \ 1312 uint64_t error_code; \ 1313 uint8_t vector; \ 1314 uint32_t a, d; \ 1315 \ 1316 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1317 : "=a"(a), "=d"(d), \ 1318 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1319 : "c"(idx) \ 1320 : KVM_ASM_SAFE_CLOBBERS); \ 1321 \ 1322 *val = (uint64_t)a | ((uint64_t)d << 32); \ 1323 return vector; \ 1324 } 1325 1326 /* 1327 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1328 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1329 */ 1330 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1331 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1332 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1333 1334 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1335 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1336 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1337 1338 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val) 1339 { 1340 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1341 } 1342 1343 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value) 1344 { 1345 u32 eax = value; 1346 u32 edx = value >> 32; 1347 1348 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1349 } 1350 1351 bool kvm_is_tdp_enabled(void); 1352 1353 static inline bool get_kvm_intel_param_bool(const char *param) 1354 { 1355 return kvm_get_module_param_bool("kvm_intel", param); 1356 } 1357 1358 static inline bool get_kvm_amd_param_bool(const char *param) 1359 { 1360 return kvm_get_module_param_bool("kvm_amd", param); 1361 } 1362 1363 static inline int get_kvm_intel_param_integer(const char *param) 1364 { 1365 return kvm_get_module_param_integer("kvm_intel", param); 1366 } 1367 1368 static inline int get_kvm_amd_param_integer(const char *param) 1369 { 1370 return kvm_get_module_param_integer("kvm_amd", param); 1371 } 1372 1373 static inline bool kvm_is_pmu_enabled(void) 1374 { 1375 return get_kvm_param_bool("enable_pmu"); 1376 } 1377 1378 static inline bool kvm_is_forced_emulation_enabled(void) 1379 { 1380 return !!get_kvm_param_integer("force_emulation_prefix"); 1381 } 1382 1383 static inline bool kvm_is_unrestricted_guest_enabled(void) 1384 { 1385 return get_kvm_intel_param_bool("unrestricted_guest"); 1386 } 1387 1388 static inline bool kvm_is_ignore_msrs(void) 1389 { 1390 return get_kvm_param_bool("ignore_msrs"); 1391 } 1392 1393 static inline bool kvm_is_lbrv_enabled(void) 1394 { 1395 return !!get_kvm_amd_param_integer("lbrv"); 1396 } 1397 1398 uint64_t *vm_get_pte(struct kvm_vm *vm, uint64_t vaddr); 1399 1400 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2, 1401 uint64_t a3); 1402 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1403 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1); 1404 1405 static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa, 1406 uint64_t size, uint64_t flags) 1407 { 1408 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1409 } 1410 1411 static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, 1412 uint64_t flags) 1413 { 1414 uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1415 1416 GUEST_ASSERT(!ret); 1417 } 1418 1419 /* 1420 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 1421 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 1422 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 1423 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 1424 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 1425 */ 1426 static inline void safe_halt(void) 1427 { 1428 asm volatile("sti; hlt"); 1429 } 1430 1431 /* 1432 * Enable interrupts and ensure that interrupts are evaluated upon return from 1433 * this function, i.e. execute a nop to consume the STi interrupt shadow. 1434 */ 1435 static inline void sti_nop(void) 1436 { 1437 asm volatile ("sti; nop"); 1438 } 1439 1440 /* 1441 * Enable interrupts for one instruction (nop), to allow the CPU to process all 1442 * interrupts that are already pending. 1443 */ 1444 static inline void sti_nop_cli(void) 1445 { 1446 asm volatile ("sti; nop; cli"); 1447 } 1448 1449 static inline void sti(void) 1450 { 1451 asm volatile("sti"); 1452 } 1453 1454 static inline void cli(void) 1455 { 1456 asm volatile ("cli"); 1457 } 1458 1459 void __vm_xsave_require_permission(uint64_t xfeature, const char *name); 1460 1461 #define vm_xsave_require_permission(xfeature) \ 1462 __vm_xsave_require_permission(xfeature, #xfeature) 1463 1464 enum pg_level { 1465 PG_LEVEL_NONE, 1466 PG_LEVEL_4K, 1467 PG_LEVEL_2M, 1468 PG_LEVEL_1G, 1469 PG_LEVEL_512G, 1470 PG_LEVEL_256T 1471 }; 1472 1473 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1474 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1475 1476 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1477 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1478 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1479 1480 #define PTE_PRESENT_MASK(mmu) ((mmu)->arch.pte_masks.present) 1481 #define PTE_WRITABLE_MASK(mmu) ((mmu)->arch.pte_masks.writable) 1482 #define PTE_USER_MASK(mmu) ((mmu)->arch.pte_masks.user) 1483 #define PTE_READABLE_MASK(mmu) ((mmu)->arch.pte_masks.readable) 1484 #define PTE_EXECUTABLE_MASK(mmu) ((mmu)->arch.pte_masks.executable) 1485 #define PTE_ACCESSED_MASK(mmu) ((mmu)->arch.pte_masks.accessed) 1486 #define PTE_DIRTY_MASK(mmu) ((mmu)->arch.pte_masks.dirty) 1487 #define PTE_HUGE_MASK(mmu) ((mmu)->arch.pte_masks.huge) 1488 #define PTE_NX_MASK(mmu) ((mmu)->arch.pte_masks.nx) 1489 #define PTE_C_BIT_MASK(mmu) ((mmu)->arch.pte_masks.c) 1490 #define PTE_S_BIT_MASK(mmu) ((mmu)->arch.pte_masks.s) 1491 #define PTE_ALWAYS_SET_MASK(mmu) ((mmu)->arch.pte_masks.always_set) 1492 1493 /* 1494 * For PTEs without a PRESENT bit (i.e. EPT entries), treat the PTE as present 1495 * if it's executable or readable, as EPT supports execute-only PTEs, but not 1496 * write-only PTEs. 1497 */ 1498 #define is_present_pte(mmu, pte) \ 1499 (PTE_PRESENT_MASK(mmu) ? \ 1500 !!(*(pte) & PTE_PRESENT_MASK(mmu)) : \ 1501 !!(*(pte) & (PTE_READABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu)))) 1502 #define is_executable_pte(mmu, pte) \ 1503 ((*(pte) & (PTE_EXECUTABLE_MASK(mmu) | PTE_NX_MASK(mmu))) == PTE_EXECUTABLE_MASK(mmu)) 1504 #define is_writable_pte(mmu, pte) (!!(*(pte) & PTE_WRITABLE_MASK(mmu))) 1505 #define is_user_pte(mmu, pte) (!!(*(pte) & PTE_USER_MASK(mmu))) 1506 #define is_accessed_pte(mmu, pte) (!!(*(pte) & PTE_ACCESSED_MASK(mmu))) 1507 #define is_dirty_pte(mmu, pte) (!!(*(pte) & PTE_DIRTY_MASK(mmu))) 1508 #define is_huge_pte(mmu, pte) (!!(*(pte) & PTE_HUGE_MASK(mmu))) 1509 #define is_nx_pte(mmu, pte) (!is_executable_pte(mmu, pte)) 1510 1511 void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels, 1512 struct pte_masks *pte_masks); 1513 1514 void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr, 1515 uint64_t paddr, int level); 1516 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, 1517 uint64_t nr_bytes, int level); 1518 1519 void vm_enable_tdp(struct kvm_vm *vm); 1520 bool kvm_cpu_has_tdp(void); 1521 void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr, uint64_t size); 1522 void tdp_identity_map_default_memslots(struct kvm_vm *vm); 1523 void tdp_identity_map_1g(struct kvm_vm *vm, uint64_t addr, uint64_t size); 1524 uint64_t *tdp_get_pte(struct kvm_vm *vm, uint64_t l2_gpa); 1525 1526 /* 1527 * Basic CPU control in CR0 1528 */ 1529 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1530 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1531 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1532 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1533 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1534 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1535 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1536 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1537 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1538 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1539 #define X86_CR0_PG (1UL<<31) /* Paging */ 1540 1541 #define PFERR_PRESENT_BIT 0 1542 #define PFERR_WRITE_BIT 1 1543 #define PFERR_USER_BIT 2 1544 #define PFERR_RSVD_BIT 3 1545 #define PFERR_FETCH_BIT 4 1546 #define PFERR_PK_BIT 5 1547 #define PFERR_SGX_BIT 15 1548 #define PFERR_GUEST_FINAL_BIT 32 1549 #define PFERR_GUEST_PAGE_BIT 33 1550 #define PFERR_IMPLICIT_ACCESS_BIT 48 1551 1552 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1553 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1554 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1555 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1556 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1557 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1558 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1559 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1560 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1561 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1562 1563 bool sys_clocksource_is_based_on_tsc(void); 1564 1565 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1566