1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAuto v9 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov9.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,boot-mode.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "samsung,exynosautov9"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_aud; 24 pinctrl2 = &pinctrl_fsys0; 25 pinctrl3 = &pinctrl_fsys1; 26 pinctrl4 = &pinctrl_fsys2; 27 pinctrl5 = &pinctrl_peric0; 28 pinctrl6 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; 33 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 42 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a76"; 84 reg = <0x0>; 85 enable-method = "psci"; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a76"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a76"; 98 reg = <0x200>; 99 enable-method = "psci"; 100 }; 101 102 cpu3: cpu@300 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x300>; 106 enable-method = "psci"; 107 }; 108 109 cpu4: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x10000>; 113 enable-method = "psci"; 114 }; 115 116 cpu5: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a76"; 119 reg = <0x10100>; 120 enable-method = "psci"; 121 }; 122 123 cpu6: cpu@10200 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x10200>; 127 enable-method = "psci"; 128 }; 129 130 cpu7: cpu@10300 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a76"; 133 reg = <0x10300>; 134 enable-method = "psci"; 135 }; 136 }; 137 138 psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 cpu_suspend = <0xc4000001>; 142 cpu_off = <0x84000002>; 143 cpu_on = <0xc4000003>; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 153 }; 154 155 fixed-rate-clocks { 156 xtcxo: clock { 157 compatible = "fixed-clock"; 158 #clock-cells = <0>; 159 clock-output-names = "oscclk"; 160 }; 161 }; 162 163 soc: soc@0 { 164 compatible = "simple-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0x0 0x0 0x0 0x20000000>; 168 169 chipid@10000000 { 170 compatible = "samsung,exynosautov9-chipid", 171 "samsung,exynos850-chipid"; 172 reg = <0x10000000 0x24>; 173 }; 174 175 cmu_peris: clock-controller@10020000 { 176 compatible = "samsung,exynosautov9-cmu-peris"; 177 reg = <0x10020000 0x8000>; 178 #clock-cells = <1>; 179 180 clocks = <&xtcxo>, 181 <&cmu_top DOUT_CLKCMU_PERIS_BUS>; 182 clock-names = "oscclk", 183 "dout_clkcmu_peris_bus"; 184 }; 185 186 cmu_peric0: clock-controller@10200000 { 187 compatible = "samsung,exynosautov9-cmu-peric0"; 188 reg = <0x10200000 0x8000>; 189 #clock-cells = <1>; 190 191 clocks = <&xtcxo>, 192 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, 193 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 194 clock-names = "oscclk", 195 "dout_clkcmu_peric0_bus", 196 "dout_clkcmu_peric0_ip"; 197 }; 198 199 cmu_peric1: clock-controller@10800000 { 200 compatible = "samsung,exynosautov9-cmu-peric1"; 201 reg = <0x10800000 0x8000>; 202 #clock-cells = <1>; 203 204 clocks = <&xtcxo>, 205 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, 206 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 207 clock-names = "oscclk", 208 "dout_clkcmu_peric1_bus", 209 "dout_clkcmu_peric1_ip"; 210 }; 211 212 cmu_fsys1: clock-controller@17040000 { 213 compatible = "samsung,exynosautov9-cmu-fsys1"; 214 reg = <0x17040000 0x8000>; 215 #clock-cells = <1>; 216 217 clocks = <&xtcxo>, 218 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, 219 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, 220 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; 221 clock-names = "oscclk", 222 "dout_clkcmu_fsys1_bus", 223 "gout_clkcmu_fsys1_mmc_card", 224 "dout_clkcmu_fsys1_usbdrd"; 225 }; 226 227 cmu_fsys0: clock-controller@17700000 { 228 compatible = "samsung,exynosautov9-cmu-fsys0"; 229 reg = <0x17700000 0x8000>; 230 #clock-cells = <1>; 231 232 clocks = <&xtcxo>, 233 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, 234 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; 235 clock-names = "oscclk", 236 "dout_clkcmu_fsys0_bus", 237 "dout_clkcmu_fsys0_pcie"; 238 }; 239 240 cmu_fsys2: clock-controller@17c00000 { 241 compatible = "samsung,exynosautov9-cmu-fsys2"; 242 reg = <0x17c00000 0x8000>; 243 #clock-cells = <1>; 244 245 clocks = <&xtcxo>, 246 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, 247 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, 248 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; 249 clock-names = "oscclk", 250 "dout_clkcmu_fsys2_bus", 251 "dout_fsys2_clkcmu_ufs_embd", 252 "dout_fsys2_clkcmu_ethernet"; 253 }; 254 255 cmu_dpum: clock-controller@18c00000 { 256 compatible = "samsung,exynosautov9-cmu-dpum"; 257 reg = <0x18c00000 0x8000>; 258 #clock-cells = <1>; 259 260 clocks = <&xtcxo>, 261 <&cmu_top DOUT_CLKCMU_DPUM_BUS>; 262 clock-names = "oscclk", "bus"; 263 }; 264 265 sysmmu_dpum_0: sysmmu@18c80000 { 266 compatible = "samsung,exynos-sysmmu"; 267 reg = <0x18c80000 0x10000>; 268 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D0_CLK>; 270 clock-names = "sysmmu"; 271 #iommu-cells = <0>; 272 }; 273 274 sysmmu_dpum_1: sysmmu@18c90000 { 275 compatible = "samsung,exynos-sysmmu"; 276 reg = <0x18c90000 0x10000>; 277 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D1_CLK>; 279 clock-names = "sysmmu"; 280 #iommu-cells = <0>; 281 }; 282 283 sysmmu_dpum_2: sysmmu@18ca0000 { 284 compatible = "samsung,exynos-sysmmu"; 285 reg = <0x18ca0000 0x10000>; 286 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D2_CLK>; 288 clock-names = "sysmmu"; 289 #iommu-cells = <0>; 290 }; 291 292 sysmmu_dpum_3: sysmmu@18cb0000 { 293 compatible = "samsung,exynos-sysmmu"; 294 reg = <0x18cb0000 0x10000>; 295 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D3_CLK>; 297 clock-names = "sysmmu"; 298 #iommu-cells = <0>; 299 }; 300 301 cmu_core: clock-controller@1b030000 { 302 compatible = "samsung,exynosautov9-cmu-core"; 303 reg = <0x1b030000 0x8000>; 304 #clock-cells = <1>; 305 306 clocks = <&xtcxo>, 307 <&cmu_top DOUT_CLKCMU_CORE_BUS>; 308 clock-names = "oscclk", 309 "dout_clkcmu_core_bus"; 310 }; 311 312 cmu_busmc: clock-controller@1b200000 { 313 compatible = "samsung,exynosautov9-cmu-busmc"; 314 reg = <0x1b200000 0x8000>; 315 #clock-cells = <1>; 316 317 clocks = <&xtcxo>, 318 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; 319 clock-names = "oscclk", 320 "dout_clkcmu_busmc_bus"; 321 }; 322 323 cmu_top: clock-controller@1b240000 { 324 compatible = "samsung,exynosautov9-cmu-top"; 325 reg = <0x1b240000 0x8000>; 326 #clock-cells = <1>; 327 328 clocks = <&xtcxo>; 329 clock-names = "oscclk"; 330 }; 331 332 gic: interrupt-controller@10101000 { 333 compatible = "arm,gic-400"; 334 #interrupt-cells = <3>; 335 #address-cells = <0>; 336 interrupt-controller; 337 reg = <0x10101000 0x1000>, 338 <0x10102000 0x2000>, 339 <0x10104000 0x2000>, 340 <0x10106000 0x2000>; 341 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 342 IRQ_TYPE_LEVEL_HIGH)>; 343 }; 344 345 pdma0: dma-controller@1b2e0000 { 346 compatible = "arm,pl330", "arm,primecell"; 347 reg = <0x1b2e0000 0x1000>; 348 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>; 350 clock-names = "apb_pclk"; 351 arm,pl330-broken-no-flushp; 352 #dma-cells = <1>; 353 }; 354 355 pinctrl_alive: pinctrl@10450000 { 356 compatible = "samsung,exynosautov9-pinctrl"; 357 reg = <0x10450000 0x1000>; 358 359 wakeup-interrupt-controller { 360 compatible = "samsung,exynosautov9-wakeup-eint", 361 "samsung,exynos850-wakeup-eint", 362 "samsung,exynos7-wakeup-eint"; 363 }; 364 }; 365 366 pinctrl_aud: pinctrl@19c60000 { 367 compatible = "samsung,exynosautov9-pinctrl"; 368 reg = <0x19c60000 0x1000>; 369 }; 370 371 pinctrl_fsys0: pinctrl@17740000 { 372 compatible = "samsung,exynosautov9-pinctrl"; 373 reg = <0x17740000 0x1000>; 374 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 375 }; 376 377 pinctrl_fsys1: pinctrl@17060000 { 378 compatible = "samsung,exynosautov9-pinctrl"; 379 reg = <0x17060000 0x1000>; 380 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 383 pinctrl_fsys2: pinctrl@17c30000 { 384 compatible = "samsung,exynosautov9-pinctrl"; 385 reg = <0x17c30000 0x1000>; 386 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 387 }; 388 389 pinctrl_peric0: pinctrl@10230000 { 390 compatible = "samsung,exynosautov9-pinctrl"; 391 reg = <0x10230000 0x1000>; 392 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 395 pinctrl_peric1: pinctrl@10830000 { 396 compatible = "samsung,exynosautov9-pinctrl"; 397 reg = <0x10830000 0x1000>; 398 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 399 }; 400 401 pmu_system_controller: system-controller@10460000 { 402 compatible = "samsung,exynosautov9-pmu", 403 "samsung,exynos7-pmu", "syscon"; 404 reg = <0x10460000 0x10000>; 405 406 reboot: syscon-reboot { 407 compatible = "syscon-reboot"; 408 regmap = <&pmu_system_controller>; 409 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 410 value = <0x2>; 411 mask = <0x2>; 412 }; 413 414 reboot-mode { 415 compatible = "syscon-reboot-mode"; 416 offset = <0x810>; /* SYSIP_DAT0 */ 417 mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; 418 mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; 419 mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; 420 }; 421 }; 422 423 syscon_fsys2: syscon@17c20000 { 424 compatible = "samsung,exynosautov9-fsys2-sysreg", 425 "samsung,exynosautov9-sysreg", "syscon"; 426 reg = <0x17c20000 0x1000>; 427 }; 428 429 syscon_peric0: syscon@10220000 { 430 compatible = "samsung,exynosautov9-peric0-sysreg", 431 "samsung,exynosautov9-sysreg", "syscon"; 432 reg = <0x10220000 0x2000>; 433 }; 434 435 syscon_peric1: syscon@10820000 { 436 compatible = "samsung,exynosautov9-peric1-sysreg", 437 "samsung,exynosautov9-sysreg", "syscon"; 438 reg = <0x10820000 0x2000>; 439 }; 440 441 usi_0: usi@103000c0 { 442 compatible = "samsung,exynosautov9-usi", 443 "samsung,exynos850-usi"; 444 reg = <0x103000c0 0x20>; 445 samsung,sysreg = <&syscon_peric0 0x1000>; 446 samsung,mode = <USI_MODE_UART>; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 ranges; 450 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 451 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 452 clock-names = "pclk", "ipclk"; 453 status = "disabled"; 454 455 serial_0: serial@10300000 { 456 compatible = "samsung,exynosautov9-uart", 457 "samsung,exynos850-uart"; 458 reg = <0x10300000 0xc0>; 459 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&uart0_bus>; 462 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 463 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 464 clock-names = "uart", "clk_uart_baud0"; 465 samsung,uart-fifosize = <256>; 466 status = "disabled"; 467 }; 468 469 spi_0: spi@10300000 { 470 compatible = "samsung,exynosautov9-spi"; 471 reg = <0x10300000 0x30>; 472 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&spi0_bus &spi0_cs_func>; 475 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 476 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>, 477 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 478 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 479 samsung,spi-src-clk = <0>; 480 dmas = <&pdma0 1>, <&pdma0 0>; 481 dma-names = "tx", "rx"; 482 num-cs = <1>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 fifo-depth = <256>; 486 status = "disabled"; 487 }; 488 489 hsi2c_0: i2c@10300000 { 490 compatible = "samsung,exynosautov9-hsi2c"; 491 reg = <0x10300000 0xc0>; 492 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&hsi2c0_bus>; 495 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 496 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 497 clock-names = "hsi2c", "hsi2c_pclk"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 status = "disabled"; 501 }; 502 }; 503 504 usi_i2c_0: usi@103100c0 { 505 compatible = "samsung,exynosautov9-usi", 506 "samsung,exynos850-usi"; 507 reg = <0x103100c0 0x20>; 508 samsung,sysreg = <&syscon_peric0 0x1004>; 509 samsung,mode = <USI_MODE_I2C>; 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges; 513 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, 514 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; 515 clock-names = "pclk", "ipclk"; 516 status = "disabled"; 517 518 hsi2c_1: i2c@10310000 { 519 compatible = "samsung,exynosautov9-hsi2c"; 520 reg = <0x10310000 0xc0>; 521 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&hsi2c1_bus>; 524 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>, 525 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>; 526 clock-names = "hsi2c", "hsi2c_pclk"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 status = "disabled"; 530 }; 531 }; 532 533 usi_1: usi@103200c0 { 534 compatible = "samsung,exynosautov9-usi", 535 "samsung,exynos850-usi"; 536 reg = <0x103200c0 0x20>; 537 samsung,sysreg = <&syscon_peric0 0x1008>; 538 samsung,mode = <USI_MODE_UART>; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 ranges; 542 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 543 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 544 clock-names = "pclk", "ipclk"; 545 status = "disabled"; 546 547 serial_1: serial@10320000 { 548 compatible = "samsung,exynosautov9-uart", 549 "samsung,exynos850-uart"; 550 reg = <0x10320000 0xc0>; 551 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&uart1_bus>; 554 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 555 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 556 clock-names = "uart", "clk_uart_baud0"; 557 samsung,uart-fifosize = <256>; 558 status = "disabled"; 559 }; 560 561 spi_1: spi@10320000 { 562 compatible = "samsung,exynosautov9-spi"; 563 reg = <0x10320000 0x30>; 564 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&spi1_bus &spi1_cs_func>; 567 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 568 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>, 569 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 570 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 571 samsung,spi-src-clk = <0>; 572 dmas = <&pdma0 3>, <&pdma0 2>; 573 dma-names = "tx", "rx"; 574 num-cs = <1>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 fifo-depth = <256>; 578 status = "disabled"; 579 }; 580 581 hsi2c_2: i2c@10320000 { 582 compatible = "samsung,exynosautov9-hsi2c"; 583 reg = <0x10320000 0xc0>; 584 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&hsi2c2_bus>; 587 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 588 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 589 clock-names = "hsi2c", "hsi2c_pclk"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 }; 595 596 usi_i2c_1: usi@103300c0 { 597 compatible = "samsung,exynosautov9-usi", 598 "samsung,exynos850-usi"; 599 reg = <0x103300c0 0x20>; 600 samsung,sysreg = <&syscon_peric0 0x100c>; 601 samsung,mode = <USI_MODE_I2C>; 602 #address-cells = <1>; 603 #size-cells = <1>; 604 ranges; 605 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, 606 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; 607 clock-names = "pclk", "ipclk"; 608 status = "disabled"; 609 610 hsi2c_3: i2c@10330000 { 611 compatible = "samsung,exynosautov9-hsi2c"; 612 reg = <0x10330000 0xc0>; 613 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&hsi2c3_bus>; 616 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>, 617 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>; 618 clock-names = "hsi2c", "hsi2c_pclk"; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 }; 624 625 usi_2: usi@103400c0 { 626 compatible = "samsung,exynosautov9-usi", 627 "samsung,exynos850-usi"; 628 reg = <0x103400c0 0x20>; 629 samsung,sysreg = <&syscon_peric0 0x1010>; 630 samsung,mode = <USI_MODE_UART>; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 ranges; 634 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 635 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 636 clock-names = "pclk", "ipclk"; 637 status = "disabled"; 638 639 serial_2: serial@10340000 { 640 compatible = "samsung,exynosautov9-uart", 641 "samsung,exynos850-uart"; 642 reg = <0x10340000 0xc0>; 643 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&uart2_bus>; 646 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 647 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 648 clock-names = "uart", "clk_uart_baud0"; 649 samsung,uart-fifosize = <64>; 650 status = "disabled"; 651 }; 652 653 spi_2: spi@10340000 { 654 compatible = "samsung,exynosautov9-spi"; 655 reg = <0x10340000 0x30>; 656 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&spi2_bus &spi2_cs_func>; 659 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 660 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>, 661 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 662 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 663 samsung,spi-src-clk = <0>; 664 dmas = <&pdma0 5>, <&pdma0 4>; 665 dma-names = "tx", "rx"; 666 num-cs = <1>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 fifo-depth = <64>; 670 status = "disabled"; 671 }; 672 673 hsi2c_4: i2c@10340000 { 674 compatible = "samsung,exynosautov9-hsi2c"; 675 reg = <0x10340000 0xc0>; 676 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&hsi2c4_bus>; 679 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 680 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 681 clock-names = "hsi2c", "hsi2c_pclk"; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 status = "disabled"; 685 }; 686 }; 687 688 usi_i2c_2: usi@103500c0 { 689 compatible = "samsung,exynosautov9-usi", 690 "samsung,exynos850-usi"; 691 reg = <0x103500c0 0x20>; 692 samsung,sysreg = <&syscon_peric0 0x1014>; 693 samsung,mode = <USI_MODE_I2C>; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges; 697 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, 698 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; 699 clock-names = "pclk", "ipclk"; 700 status = "disabled"; 701 702 hsi2c_5: i2c@10350000 { 703 compatible = "samsung,exynosautov9-hsi2c"; 704 reg = <0x10350000 0xc0>; 705 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&hsi2c5_bus>; 708 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>, 709 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>; 710 clock-names = "hsi2c", "hsi2c_pclk"; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 status = "disabled"; 714 }; 715 }; 716 717 usi_3: usi@103600c0 { 718 compatible = "samsung,exynosautov9-usi", 719 "samsung,exynos850-usi"; 720 reg = <0x103600c0 0x20>; 721 samsung,sysreg = <&syscon_peric0 0x1018>; 722 samsung,mode = <USI_MODE_UART>; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 ranges; 726 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 727 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 728 clock-names = "pclk", "ipclk"; 729 status = "disabled"; 730 731 serial_3: serial@10360000 { 732 compatible = "samsung,exynosautov9-uart", 733 "samsung,exynos850-uart"; 734 reg = <0x10360000 0xc0>; 735 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&uart3_bus>; 738 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 739 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 740 clock-names = "uart", "clk_uart_baud0"; 741 samsung,uart-fifosize = <64>; 742 status = "disabled"; 743 }; 744 745 spi_3: spi@10360000 { 746 compatible = "samsung,exynosautov9-spi"; 747 reg = <0x10360000 0x30>; 748 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&spi3_bus &spi3_cs_func>; 751 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 752 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>, 753 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 754 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 755 samsung,spi-src-clk = <0>; 756 dmas = <&pdma0 7>, <&pdma0 6>; 757 dma-names = "tx", "rx"; 758 num-cs = <1>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 fifo-depth = <64>; 762 status = "disabled"; 763 }; 764 765 hsi2c_6: i2c@10360000 { 766 compatible = "samsung,exynosautov9-hsi2c"; 767 reg = <0x10360000 0xc0>; 768 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&hsi2c6_bus>; 771 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 772 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 773 clock-names = "hsi2c", "hsi2c_pclk"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 }; 779 780 usi_i2c_3: usi@103700c0 { 781 compatible = "samsung,exynosautov9-usi", 782 "samsung,exynos850-usi"; 783 reg = <0x103700c0 0x20>; 784 samsung,sysreg = <&syscon_peric0 0x101c>; 785 samsung,mode = <USI_MODE_I2C>; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 ranges; 789 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, 790 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; 791 clock-names = "pclk", "ipclk"; 792 status = "disabled"; 793 794 hsi2c_7: i2c@10370000 { 795 compatible = "samsung,exynosautov9-hsi2c"; 796 reg = <0x10370000 0xc0>; 797 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&hsi2c7_bus>; 800 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>, 801 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>; 802 clock-names = "hsi2c", "hsi2c_pclk"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 }; 808 809 usi_4: usi@103800c0 { 810 compatible = "samsung,exynosautov9-usi", 811 "samsung,exynos850-usi"; 812 reg = <0x103800c0 0x20>; 813 samsung,sysreg = <&syscon_peric0 0x1020>; 814 samsung,mode = <USI_MODE_UART>; 815 #address-cells = <1>; 816 #size-cells = <1>; 817 ranges; 818 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 819 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 820 clock-names = "pclk", "ipclk"; 821 status = "disabled"; 822 823 serial_4: serial@10380000 { 824 compatible = "samsung,exynosautov9-uart", 825 "samsung,exynos850-uart"; 826 reg = <0x10380000 0xc0>; 827 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&uart4_bus>; 830 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 831 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 832 clock-names = "uart", "clk_uart_baud0"; 833 samsung,uart-fifosize = <64>; 834 status = "disabled"; 835 }; 836 837 spi_4: spi@10380000 { 838 compatible = "samsung,exynosautov9-spi"; 839 reg = <0x10380000 0x30>; 840 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&spi4_bus &spi4_cs_func>; 843 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 844 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>, 845 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 846 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 847 samsung,spi-src-clk = <0>; 848 dmas = <&pdma0 9>, <&pdma0 8>; 849 dma-names = "tx", "rx"; 850 num-cs = <1>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 fifo-depth = <64>; 854 status = "disabled"; 855 }; 856 857 hsi2c_8: i2c@10380000 { 858 compatible = "samsung,exynosautov9-hsi2c"; 859 reg = <0x10380000 0xc0>; 860 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&hsi2c8_bus>; 863 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 864 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 865 clock-names = "hsi2c", "hsi2c_pclk"; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 status = "disabled"; 869 }; 870 }; 871 872 usi_i2c_4: usi@103900c0 { 873 compatible = "samsung,exynosautov9-usi", 874 "samsung,exynos850-usi"; 875 reg = <0x103900c0 0x20>; 876 samsung,sysreg = <&syscon_peric0 0x1024>; 877 samsung,mode = <USI_MODE_I2C>; 878 #address-cells = <1>; 879 #size-cells = <1>; 880 ranges; 881 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, 882 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; 883 clock-names = "pclk", "ipclk"; 884 status = "disabled"; 885 886 hsi2c_9: i2c@10390000 { 887 compatible = "samsung,exynosautov9-hsi2c"; 888 reg = <0x10390000 0xc0>; 889 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&hsi2c9_bus>; 892 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>, 893 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>; 894 clock-names = "hsi2c", "hsi2c_pclk"; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 status = "disabled"; 898 }; 899 }; 900 901 usi_5: usi@103a00c0 { 902 compatible = "samsung,exynosautov9-usi", 903 "samsung,exynos850-usi"; 904 reg = <0x103a00c0 0x20>; 905 samsung,sysreg = <&syscon_peric0 0x1028>; 906 samsung,mode = <USI_MODE_UART>; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 ranges; 910 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 911 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 912 clock-names = "pclk", "ipclk"; 913 status = "disabled"; 914 915 serial_5: serial@103a0000 { 916 compatible = "samsung,exynosautov9-uart", 917 "samsung,exynos850-uart"; 918 reg = <0x103a0000 0xc0>; 919 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&uart5_bus>; 922 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 923 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 924 clock-names = "uart", "clk_uart_baud0"; 925 samsung,uart-fifosize = <64>; 926 status = "disabled"; 927 }; 928 929 spi_5: spi@103a0000 { 930 compatible = "samsung,exynosautov9-spi"; 931 reg = <0x103a0000 0x30>; 932 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&spi5_bus &spi5_cs_func>; 935 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 936 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>, 937 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 938 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 939 samsung,spi-src-clk = <0>; 940 dmas = <&pdma0 11>, <&pdma0 10>; 941 dma-names = "tx", "rx"; 942 num-cs = <1>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 fifo-depth = <64>; 946 status = "disabled"; 947 }; 948 949 hsi2c_10: i2c@103a0000 { 950 compatible = "samsung,exynosautov9-hsi2c"; 951 reg = <0x103a0000 0xc0>; 952 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&hsi2c10_bus>; 955 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 956 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 957 clock-names = "hsi2c", "hsi2c_pclk"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 status = "disabled"; 961 }; 962 }; 963 964 usi_i2c_5: usi@103b00c0 { 965 compatible = "samsung,exynosautov9-usi", 966 "samsung,exynos850-usi"; 967 reg = <0x103b00c0 0x20>; 968 samsung,sysreg = <&syscon_peric0 0x102c>; 969 samsung,mode = <USI_MODE_I2C>; 970 #address-cells = <1>; 971 #size-cells = <1>; 972 ranges; 973 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, 974 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; 975 clock-names = "pclk", "ipclk"; 976 status = "disabled"; 977 978 hsi2c_11: i2c@103b0000 { 979 compatible = "samsung,exynosautov9-hsi2c"; 980 reg = <0x103b0000 0xc0>; 981 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&hsi2c11_bus>; 984 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>, 985 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>; 986 clock-names = "hsi2c", "hsi2c_pclk"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 }; 992 993 usi_6: usi@109000c0 { 994 compatible = "samsung,exynosautov9-usi", 995 "samsung,exynos850-usi"; 996 reg = <0x109000c0 0x20>; 997 samsung,sysreg = <&syscon_peric1 0x1000>; 998 samsung,mode = <USI_MODE_UART>; 999 #address-cells = <1>; 1000 #size-cells = <1>; 1001 ranges; 1002 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 1003 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 1004 clock-names = "pclk", "ipclk"; 1005 status = "disabled"; 1006 1007 serial_6: serial@10900000 { 1008 compatible = "samsung,exynosautov9-uart", 1009 "samsung,exynos850-uart"; 1010 reg = <0x10900000 0xc0>; 1011 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&uart6_bus>; 1014 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 1015 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 1016 clock-names = "uart", "clk_uart_baud0"; 1017 samsung,uart-fifosize = <256>; 1018 status = "disabled"; 1019 }; 1020 1021 spi_6: spi@10900000 { 1022 compatible = "samsung,exynosautov9-spi"; 1023 reg = <0x10900000 0x30>; 1024 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&spi6_bus &spi6_cs_func>; 1027 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 1028 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>, 1029 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 1030 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1031 samsung,spi-src-clk = <0>; 1032 dmas = <&pdma0 13>, <&pdma0 12>; 1033 dma-names = "tx", "rx"; 1034 num-cs = <1>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 fifo-depth = <256>; 1038 status = "disabled"; 1039 }; 1040 1041 hsi2c_12: i2c@10900000 { 1042 compatible = "samsung,exynosautov9-hsi2c"; 1043 reg = <0x10900000 0xc0>; 1044 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&hsi2c12_bus>; 1047 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 1048 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 1049 clock-names = "hsi2c", "hsi2c_pclk"; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 }; 1055 1056 usi_i2c_6: usi@109100c0 { 1057 compatible = "samsung,exynosautov9-usi", 1058 "samsung,exynos850-usi"; 1059 reg = <0x109100c0 0x20>; 1060 samsung,sysreg = <&syscon_peric1 0x1004>; 1061 samsung,mode = <USI_MODE_I2C>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges; 1065 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, 1066 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; 1067 clock-names = "pclk", "ipclk"; 1068 status = "disabled"; 1069 1070 hsi2c_13: i2c@10910000 { 1071 compatible = "samsung,exynosautov9-hsi2c"; 1072 reg = <0x10910000 0xc0>; 1073 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&hsi2c13_bus>; 1076 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>, 1077 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>; 1078 clock-names = "hsi2c", "hsi2c_pclk"; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 }; 1084 1085 usi_7: usi@109200c0 { 1086 compatible = "samsung,exynosautov9-usi", 1087 "samsung,exynos850-usi"; 1088 reg = <0x109200c0 0x20>; 1089 samsung,sysreg = <&syscon_peric1 0x1008>; 1090 samsung,mode = <USI_MODE_UART>; 1091 #address-cells = <1>; 1092 #size-cells = <1>; 1093 ranges; 1094 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1095 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1096 clock-names = "pclk", "ipclk"; 1097 status = "disabled"; 1098 1099 serial_7: serial@10920000 { 1100 compatible = "samsung,exynosautov9-uart", 1101 "samsung,exynos850-uart"; 1102 reg = <0x10920000 0xc0>; 1103 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&uart7_bus>; 1106 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1107 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1108 clock-names = "uart", "clk_uart_baud0"; 1109 samsung,uart-fifosize = <64>; 1110 status = "disabled"; 1111 }; 1112 1113 spi_7: spi@10920000 { 1114 compatible = "samsung,exynosautov9-spi"; 1115 reg = <0x10920000 0x30>; 1116 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&spi7_bus &spi7_cs_func>; 1119 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1120 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>, 1121 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1122 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1123 samsung,spi-src-clk = <0>; 1124 dmas = <&pdma0 15>, <&pdma0 14>; 1125 dma-names = "tx", "rx"; 1126 num-cs = <1>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 fifo-depth = <64>; 1130 status = "disabled"; 1131 }; 1132 1133 hsi2c_14: i2c@10920000 { 1134 compatible = "samsung,exynosautov9-hsi2c"; 1135 reg = <0x10920000 0xc0>; 1136 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&hsi2c14_bus>; 1139 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1140 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1141 clock-names = "hsi2c", "hsi2c_pclk"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 }; 1147 1148 usi_i2c_7: usi@109300c0 { 1149 compatible = "samsung,exynosautov9-usi", 1150 "samsung,exynos850-usi"; 1151 reg = <0x109300c0 0x20>; 1152 samsung,sysreg = <&syscon_peric1 0x100c>; 1153 samsung,mode = <USI_MODE_I2C>; 1154 #address-cells = <1>; 1155 #size-cells = <1>; 1156 ranges; 1157 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, 1158 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; 1159 clock-names = "pclk", "ipclk"; 1160 status = "disabled"; 1161 1162 hsi2c_15: i2c@10930000 { 1163 compatible = "samsung,exynosautov9-hsi2c"; 1164 reg = <0x10930000 0xc0>; 1165 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&hsi2c15_bus>; 1168 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>, 1169 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>; 1170 clock-names = "hsi2c", "hsi2c_pclk"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 }; 1176 1177 usi_8: usi@109400c0 { 1178 compatible = "samsung,exynosautov9-usi", 1179 "samsung,exynos850-usi"; 1180 reg = <0x109400c0 0x20>; 1181 samsung,sysreg = <&syscon_peric1 0x1010>; 1182 samsung,mode = <USI_MODE_UART>; 1183 #address-cells = <1>; 1184 #size-cells = <1>; 1185 ranges; 1186 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1187 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1188 clock-names = "pclk", "ipclk"; 1189 status = "disabled"; 1190 1191 serial_8: serial@10940000 { 1192 compatible = "samsung,exynosautov9-uart", 1193 "samsung,exynos850-uart"; 1194 reg = <0x10940000 0xc0>; 1195 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&uart8_bus>; 1198 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1199 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1200 clock-names = "uart", "clk_uart_baud0"; 1201 samsung,uart-fifosize = <64>; 1202 status = "disabled"; 1203 }; 1204 1205 spi_8: spi@10940000 { 1206 compatible = "samsung,exynosautov9-spi"; 1207 reg = <0x10940000 0x30>; 1208 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&spi8_bus &spi8_cs_func>; 1211 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1212 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>, 1213 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1214 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1215 samsung,spi-src-clk = <0>; 1216 dmas = <&pdma0 17>, <&pdma0 16>; 1217 dma-names = "tx", "rx"; 1218 num-cs = <1>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 fifo-depth = <64>; 1222 status = "disabled"; 1223 }; 1224 1225 hsi2c_16: i2c@10940000 { 1226 compatible = "samsung,exynosautov9-hsi2c"; 1227 reg = <0x10940000 0xc0>; 1228 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&hsi2c16_bus>; 1231 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1232 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1233 clock-names = "hsi2c", "hsi2c_pclk"; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 status = "disabled"; 1237 }; 1238 }; 1239 1240 usi_i2c_8: usi@109500c0 { 1241 compatible = "samsung,exynosautov9-usi", 1242 "samsung,exynos850-usi"; 1243 reg = <0x109500c0 0x20>; 1244 samsung,sysreg = <&syscon_peric1 0x1014>; 1245 samsung,mode = <USI_MODE_I2C>; 1246 #address-cells = <1>; 1247 #size-cells = <1>; 1248 ranges; 1249 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, 1250 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; 1251 clock-names = "pclk", "ipclk"; 1252 status = "disabled"; 1253 1254 hsi2c_17: i2c@10950000 { 1255 compatible = "samsung,exynosautov9-hsi2c"; 1256 reg = <0x10950000 0xc0>; 1257 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&hsi2c17_bus>; 1260 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>, 1261 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>; 1262 clock-names = "hsi2c", "hsi2c_pclk"; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 status = "disabled"; 1266 }; 1267 }; 1268 1269 usi_9: usi@109600c0 { 1270 compatible = "samsung,exynosautov9-usi", 1271 "samsung,exynos850-usi"; 1272 reg = <0x109600c0 0x20>; 1273 samsung,sysreg = <&syscon_peric1 0x1018>; 1274 samsung,mode = <USI_MODE_UART>; 1275 #address-cells = <1>; 1276 #size-cells = <1>; 1277 ranges; 1278 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1279 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1280 clock-names = "pclk", "ipclk"; 1281 status = "disabled"; 1282 1283 serial_9: serial@10960000 { 1284 compatible = "samsung,exynosautov9-uart", 1285 "samsung,exynos850-uart"; 1286 reg = <0x10960000 0xc0>; 1287 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&uart9_bus>; 1290 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1291 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1292 clock-names = "uart", "clk_uart_baud0"; 1293 samsung,uart-fifosize = <64>; 1294 status = "disabled"; 1295 }; 1296 1297 spi_9: spi@10960000 { 1298 compatible = "samsung,exynosautov9-spi"; 1299 reg = <0x10960000 0x30>; 1300 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&spi9_bus &spi9_cs_func>; 1303 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1304 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>, 1305 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1306 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1307 samsung,spi-src-clk = <0>; 1308 dmas = <&pdma0 19>, <&pdma0 18>; 1309 dma-names = "tx", "rx"; 1310 num-cs = <1>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 fifo-depth = <64>; 1314 status = "disabled"; 1315 }; 1316 1317 hsi2c_18: i2c@10960000 { 1318 compatible = "samsung,exynosautov9-hsi2c"; 1319 reg = <0x10960000 0xc0>; 1320 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&hsi2c18_bus>; 1323 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1324 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1325 clock-names = "hsi2c", "hsi2c_pclk"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 }; 1331 1332 usi_i2c_9: usi@109700c0 { 1333 compatible = "samsung,exynosautov9-usi", 1334 "samsung,exynos850-usi"; 1335 reg = <0x109700c0 0x20>; 1336 samsung,sysreg = <&syscon_peric1 0x101c>; 1337 samsung,mode = <USI_MODE_I2C>; 1338 #address-cells = <1>; 1339 #size-cells = <1>; 1340 ranges; 1341 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, 1342 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; 1343 clock-names = "pclk", "ipclk"; 1344 status = "disabled"; 1345 1346 hsi2c_19: i2c@10970000 { 1347 compatible = "samsung,exynosautov9-hsi2c"; 1348 reg = <0x10970000 0xc0>; 1349 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&hsi2c19_bus>; 1352 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>, 1353 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>; 1354 clock-names = "hsi2c", "hsi2c_pclk"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 }; 1360 1361 usi_10: usi@109800c0 { 1362 compatible = "samsung,exynosautov9-usi", 1363 "samsung,exynos850-usi"; 1364 reg = <0x109800c0 0x20>; 1365 samsung,sysreg = <&syscon_peric1 0x1020>; 1366 samsung,mode = <USI_MODE_UART>; 1367 #address-cells = <1>; 1368 #size-cells = <1>; 1369 ranges; 1370 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1371 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1372 clock-names = "pclk", "ipclk"; 1373 status = "disabled"; 1374 1375 serial_10: serial@10980000 { 1376 compatible = "samsung,exynosautov9-uart", 1377 "samsung,exynos850-uart"; 1378 reg = <0x10980000 0xc0>; 1379 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&uart10_bus>; 1382 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1383 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1384 clock-names = "uart", "clk_uart_baud0"; 1385 samsung,uart-fifosize = <64>; 1386 status = "disabled"; 1387 }; 1388 1389 spi_10: spi@10980000 { 1390 compatible = "samsung,exynosautov9-spi"; 1391 reg = <0x10980000 0x30>; 1392 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&spi10_bus &spi10_cs_func>; 1395 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1396 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>, 1397 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1398 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1399 samsung,spi-src-clk = <0>; 1400 dmas = <&pdma0 21>, <&pdma0 20>; 1401 dma-names = "tx", "rx"; 1402 num-cs = <1>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 fifo-depth = <64>; 1406 status = "disabled"; 1407 }; 1408 1409 hsi2c_20: i2c@10980000 { 1410 compatible = "samsung,exynosautov9-hsi2c"; 1411 reg = <0x10980000 0xc0>; 1412 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&hsi2c20_bus>; 1415 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1416 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1417 clock-names = "hsi2c", "hsi2c_pclk"; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 }; 1423 1424 usi_i2c_10: usi@109900c0 { 1425 compatible = "samsung,exynosautov9-usi", 1426 "samsung,exynos850-usi"; 1427 reg = <0x109900c0 0x20>; 1428 samsung,sysreg = <&syscon_peric1 0x1024>; 1429 samsung,mode = <USI_MODE_I2C>; 1430 #address-cells = <1>; 1431 #size-cells = <1>; 1432 ranges; 1433 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, 1434 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; 1435 clock-names = "pclk", "ipclk"; 1436 status = "disabled"; 1437 1438 hsi2c_21: i2c@10990000 { 1439 compatible = "samsung,exynosautov9-hsi2c"; 1440 reg = <0x10990000 0xc0>; 1441 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&hsi2c21_bus>; 1444 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>, 1445 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>; 1446 clock-names = "hsi2c", "hsi2c_pclk"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 }; 1452 1453 usi_11: usi@109a00c0 { 1454 compatible = "samsung,exynosautov9-usi", 1455 "samsung,exynos850-usi"; 1456 reg = <0x109a00c0 0x20>; 1457 samsung,sysreg = <&syscon_peric1 0x1028>; 1458 samsung,mode = <USI_MODE_UART>; 1459 #address-cells = <1>; 1460 #size-cells = <1>; 1461 ranges; 1462 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1463 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1464 clock-names = "pclk", "ipclk"; 1465 status = "disabled"; 1466 1467 serial_11: serial@109a0000 { 1468 compatible = "samsung,exynosautov9-uart", 1469 "samsung,exynos850-uart"; 1470 reg = <0x109a0000 0xc0>; 1471 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&uart11_bus>; 1474 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1475 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1476 clock-names = "uart", "clk_uart_baud0"; 1477 samsung,uart-fifosize = <64>; 1478 status = "disabled"; 1479 }; 1480 1481 spi_11: spi@109a0000 { 1482 compatible = "samsung,exynosautov9-spi"; 1483 reg = <0x109a0000 0x30>; 1484 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1485 pinctrl-names = "default"; 1486 pinctrl-0 = <&spi11_bus &spi11_cs_func>; 1487 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1488 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>, 1489 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1490 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1491 samsung,spi-src-clk = <0>; 1492 num-cs = <1>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 fifo-depth = <64>; 1496 status = "disabled"; 1497 }; 1498 1499 hsi2c_22: i2c@109a0000 { 1500 compatible = "samsung,exynosautov9-hsi2c"; 1501 reg = <0x109a0000 0xc0>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&hsi2c22_bus>; 1504 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1505 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1506 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1507 clock-names = "hsi2c", "hsi2c_pclk"; 1508 #address-cells = <1>; 1509 #size-cells = <0>; 1510 status = "disabled"; 1511 }; 1512 }; 1513 1514 usi_i2c_11: usi@109b00c0 { 1515 compatible = "samsung,exynosautov9-usi", 1516 "samsung,exynos850-usi"; 1517 reg = <0x109b00c0 0x20>; 1518 samsung,sysreg = <&syscon_peric1 0x102c>; 1519 samsung,mode = <USI_MODE_I2C>; 1520 #address-cells = <1>; 1521 #size-cells = <1>; 1522 ranges; 1523 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, 1524 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; 1525 clock-names = "pclk", "ipclk"; 1526 status = "disabled"; 1527 1528 hsi2c_23: i2c@109b0000 { 1529 compatible = "samsung,exynosautov9-hsi2c"; 1530 reg = <0x109b0000 0xc0>; 1531 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&hsi2c23_bus>; 1534 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>, 1535 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>; 1536 clock-names = "hsi2c", "hsi2c_pclk"; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 status = "disabled"; 1540 }; 1541 }; 1542 1543 ufs_0_phy: phy@17e04000 { 1544 compatible = "samsung,exynosautov9-ufs-phy"; 1545 reg = <0x17e04000 0xc00>; 1546 reg-names = "phy-pma"; 1547 samsung,pmu-syscon = <&pmu_system_controller>; 1548 #phy-cells = <0>; 1549 clocks = <&xtcxo>; 1550 clock-names = "ref_clk"; 1551 status = "disabled"; 1552 }; 1553 1554 ufs_0: ufs@17e00000 { 1555 compatible = "samsung,exynosautov9-ufs"; 1556 1557 reg = <0x17e00000 0x100>, 1558 <0x17e01100 0x410>, 1559 <0x17e80000 0x8000>, 1560 <0x17dc0000 0x2200>; 1561 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1562 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1563 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, 1564 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; 1565 clock-names = "core_clk", "sclk_unipro_main"; 1566 freq-table-hz = <0 0>, <0 0>; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1569 phys = <&ufs_0_phy>; 1570 phy-names = "ufs-phy"; 1571 samsung,sysreg = <&syscon_fsys2 0x710>; 1572 status = "disabled"; 1573 }; 1574 1575 ufs_1_phy: phy@17f04000 { 1576 compatible = "samsung,exynosautov9-ufs-phy"; 1577 reg = <0x17f04000 0xc00>; 1578 reg-names = "phy-pma"; 1579 samsung,pmu-syscon = <&pmu_system_controller 0x72c>; 1580 #phy-cells = <0>; 1581 clocks = <&xtcxo>; 1582 clock-names = "ref_clk"; 1583 status = "disabled"; 1584 }; 1585 1586 ufs_1: ufs@17f00000 { 1587 compatible = "samsung,exynosautov9-ufs"; 1588 1589 reg = <0x17f00000 0x100>, 1590 <0x17f01100 0x410>, 1591 <0x17f80000 0x8000>, 1592 <0x17de0000 0x2200>; 1593 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1594 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, 1596 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; 1597 clock-names = "core_clk", "sclk_unipro_main"; 1598 freq-table-hz = <0 0>, <0 0>; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; 1601 phys = <&ufs_1_phy>; 1602 phy-names = "ufs-phy"; 1603 samsung,sysreg = <&syscon_fsys2 0x714>; 1604 status = "disabled"; 1605 }; 1606 1607 watchdog_cl0: watchdog@10050000 { 1608 compatible = "samsung,exynosautov9-wdt"; 1609 reg = <0x10050000 0x100>; 1610 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; 1612 clock-names = "watchdog", "watchdog_src"; 1613 samsung,syscon-phandle = <&pmu_system_controller>; 1614 samsung,cluster-index = <0>; 1615 }; 1616 1617 watchdog_cl1: watchdog@10060000 { 1618 compatible = "samsung,exynosautov9-wdt"; 1619 reg = <0x10060000 0x100>; 1620 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 1621 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; 1622 clock-names = "watchdog", "watchdog_src"; 1623 samsung,syscon-phandle = <&pmu_system_controller>; 1624 samsung,cluster-index = <1>; 1625 }; 1626 1627 pwm: pwm@103f0000 { 1628 compatible = "samsung,exynosautov9-pwm", 1629 "samsung,exynos4210-pwm"; 1630 reg = <0x103f0000 0x100>; 1631 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1632 #pwm-cells = <3>; 1633 clocks = <&xtcxo>; 1634 clock-names = "timers"; 1635 status = "disabled"; 1636 }; 1637 }; 1638}; 1639 1640#include "exynosautov9-pinctrl.dtsi" 1641