1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2026 Realtek Corporation
3 */
4
5 #include "chan.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "efuse.h"
9 #include "mac.h"
10 #include "phy.h"
11 #include "reg.h"
12 #include "rtw8922d.h"
13 #include "rtw8922d_rfk.h"
14 #include "sar.h"
15 #include "util.h"
16
17 #define RTW8922D_FW_FORMAT_MAX 0
18 #define RTW8922D_FW_BASENAME "rtw89/rtw8922d_fw"
19 #define RTW8922D_MODULE_FIRMWARE \
20 RTW89_GEN_MODULE_FWNAME(RTW8922D_FW_BASENAME, RTW8922D_FW_FORMAT_MAX)
21
22 #define RTW8922DS_FW_FORMAT_MAX 0
23 #define RTW8922DS_FW_BASENAME "rtw89/rtw8922ds_fw"
24 #define RTW8922DS_MODULE_FIRMWARE \
25 RTW89_GEN_MODULE_FWNAME(RTW8922DS_FW_BASENAME, RTW8922DS_FW_FORMAT_MAX)
26
27 static const struct rtw89_hfc_ch_cfg rtw8922d_hfc_chcfg_pcie[] = {
28 {2, 732, 0}, /* ACH 0 */
29 {0, 730, 0}, /* ACH 1 */
30 {2, 732, 0}, /* ACH 2 */
31 {0, 730, 0}, /* ACH 3 */
32 {2, 732, 0}, /* ACH 4 */
33 {0, 730, 0}, /* ACH 5 */
34 {2, 732, 0}, /* ACH 6 */
35 {0, 730, 0}, /* ACH 7 */
36 {2, 732, 0}, /* B0MGQ */
37 {0, 730, 0}, /* B0HIQ */
38 {2, 732, 0}, /* B1MGQ */
39 {0, 730, 0}, /* B1HIQ */
40 {0, 0, 0}, /* GCQ */
41 };
42
43 static const struct rtw89_hfc_pub_cfg rtw8922d_hfc_pubcfg_pcie = {
44 742, /* Group 0 */
45 0, /* Group 1 */
46 742, /* Public Max */
47 0, /* WP threshold */
48 };
49
50 static const struct rtw89_hfc_param_ini rtw8922d_hfc_param_ini_pcie[] = {
51 [RTW89_QTA_SCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
52 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
53 [RTW89_QTA_DBCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
54 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
55 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
56 RTW89_HCIFC_POH},
57 [RTW89_QTA_INVALID] = {NULL},
58 };
59
60 static const struct rtw89_dle_mem rtw8922d_dle_mem_pcie[] = {
61 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size22_v1,
62 &rtw89_mac_size.ple_size29_v1, &rtw89_mac_size.wde_qt23_v1,
63 &rtw89_mac_size.wde_qt23_v1, &rtw89_mac_size.ple_qt64_v2,
64 &rtw89_mac_size.ple_qt65_v2, &rtw89_mac_size.ple_rsvd_qt9,
65 &rtw89_mac_size.rsvd0_size17, &rtw89_mac_size.rsvd1_size3,
66 &rtw89_mac_size.dle_input28},
67 [RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size22_v1,
68 &rtw89_mac_size.ple_size29_v1, &rtw89_mac_size.wde_qt23_v1,
69 &rtw89_mac_size.wde_qt23_v1, &rtw89_mac_size.ple_qt64_v2,
70 &rtw89_mac_size.ple_qt65_v2, &rtw89_mac_size.ple_rsvd_qt9,
71 &rtw89_mac_size.rsvd0_size17, &rtw89_mac_size.rsvd1_size3,
72 &rtw89_mac_size.dle_input28},
73 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18_v1,
74 &rtw89_mac_size.ple_size22_v1, &rtw89_mac_size.wde_qt3,
75 &rtw89_mac_size.wde_qt3, &rtw89_mac_size.ple_qt5_v2,
76 &rtw89_mac_size.ple_qt47_v2, &rtw89_mac_size.ple_rsvd_qt1,
77 &rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
78 &rtw89_mac_size.dle_input3},
79 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
80 NULL},
81 };
82
83 static const struct rtw89_hfc_ch_cfg rtw8922ds_hfc_chcfg_pcie[] = {
84 {2, 603, 0}, /* ACH 0 */
85 {0, 601, 0}, /* ACH 1 */
86 {2, 603, 0}, /* ACH 2 */
87 {0, 601, 0}, /* ACH 3 */
88 {2, 603, 0}, /* ACH 4 */
89 {0, 601, 0}, /* ACH 5 */
90 {2, 603, 0}, /* ACH 6 */
91 {0, 601, 0}, /* ACH 7 */
92 {2, 603, 0}, /* B0MGQ */
93 {0, 601, 0}, /* B0HIQ */
94 {2, 603, 0}, /* B1MGQ */
95 {0, 601, 0}, /* B1HIQ */
96 {0, 0, 0}, /* GCQ */
97 };
98
99 static const struct rtw89_hfc_pub_cfg rtw8922ds_hfc_pubcfg_pcie = {
100 613, /* Group 0 */
101 0, /* Group 1 */
102 613, /* Public Max */
103 0, /* WP threshold */
104 };
105
106 static const struct rtw89_hfc_param_ini rtw8922ds_hfc_param_ini_pcie[] = {
107 [RTW89_QTA_SCC] = {rtw8922ds_hfc_chcfg_pcie, &rtw8922ds_hfc_pubcfg_pcie,
108 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
109 [RTW89_QTA_DBCC] = {rtw8922ds_hfc_chcfg_pcie, &rtw8922ds_hfc_pubcfg_pcie,
110 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
111 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
112 RTW89_HCIFC_POH},
113 [RTW89_QTA_INVALID] = {NULL},
114 };
115
116 static const struct rtw89_dle_mem rtw8922ds_dle_mem_pcie[] = {
117 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size16_v1,
118 &rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
119 &rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt44_v2,
120 &rtw89_mac_size.ple_qt45_v2, &rtw89_mac_size.ple_rsvd_qt9,
121 &rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
122 &rtw89_mac_size.dle_input20},
123 [RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size16_v1,
124 &rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
125 &rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt44_v2,
126 &rtw89_mac_size.ple_qt45_v2, &rtw89_mac_size.ple_rsvd_qt9,
127 &rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
128 &rtw89_mac_size.dle_input20},
129 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18_v1,
130 &rtw89_mac_size.ple_size22_v1, &rtw89_mac_size.wde_qt3,
131 &rtw89_mac_size.wde_qt3, &rtw89_mac_size.ple_qt5_v2,
132 &rtw89_mac_size.ple_qt47_v2, &rtw89_mac_size.ple_rsvd_qt1,
133 &rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
134 &rtw89_mac_size.dle_input3},
135 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
136 NULL},
137 };
138
139 static const u32 rtw8922d_h2c_regs[RTW89_H2CREG_MAX] = {
140 R_BE_H2CREG_DATA0, R_BE_H2CREG_DATA1, R_BE_H2CREG_DATA2,
141 R_BE_H2CREG_DATA3
142 };
143
144 static const u32 rtw8922d_c2h_regs[RTW89_H2CREG_MAX] = {
145 R_BE_C2HREG_DATA0, R_BE_C2HREG_DATA1, R_BE_C2HREG_DATA2,
146 R_BE_C2HREG_DATA3
147 };
148
149 static const u32 rtw8922d_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
150 R_BE_DBG_WOW, R_BE_DBG_WOW,
151 };
152
153 static const struct rtw89_page_regs rtw8922d_page_regs = {
154 .hci_fc_ctrl = R_BE_HCI_FC_CTRL,
155 .ch_page_ctrl = R_BE_CH_PAGE_CTRL,
156 .ach_page_ctrl = R_BE_CH0_PAGE_CTRL,
157 .ach_page_info = R_BE_CH0_PAGE_INFO,
158 .pub_page_info3 = R_BE_PUB_PAGE_INFO3,
159 .pub_page_ctrl1 = R_BE_PUB_PAGE_CTRL1,
160 .pub_page_ctrl2 = R_BE_PUB_PAGE_CTRL2,
161 .pub_page_info1 = R_BE_PUB_PAGE_INFO1,
162 .pub_page_info2 = R_BE_PUB_PAGE_INFO2,
163 .wp_page_ctrl1 = R_BE_WP_PAGE_CTRL1,
164 .wp_page_ctrl2 = R_BE_WP_PAGE_CTRL2,
165 .wp_page_info1 = R_BE_WP_PAGE_INFO1,
166 };
167
168 static const struct rtw89_reg_imr rtw8922d_imr_dmac_regs[] = {
169 {R_BE_HCI_BUF_IMR, B_BE_HCI_BUF_IMR_CLR, B_BE_HCI_BUF_IMR_SET},
170 {R_BE_DISP_HOST_IMR, B_BE_DISP_HOST_IMR_CLR_V1, B_BE_DISP_HOST_IMR_SET_V1},
171 {R_BE_DISP_CPU_IMR, B_BE_DISP_CPU_IMR_CLR_V1, B_BE_DISP_CPU_IMR_SET_V1},
172 {R_BE_DISP_OTHER_IMR, B_BE_DISP_OTHER_IMR_CLR_V1, B_BE_DISP_OTHER_IMR_SET_V1},
173 {R_BE_PKTIN_ERR_IMR, B_BE_PKTIN_ERR_IMR_CLR, B_BE_PKTIN_ERR_IMR_SET},
174 {R_BE_MLO_ERR_IDCT_IMR, B_BE_MLO_ERR_IDCT_IMR_CLR, B_BE_MLO_ERR_IDCT_IMR_SET},
175 {R_BE_MPDU_TX_ERR_IMR, B_BE_MPDU_TX_ERR_IMR_CLR, B_BE_MPDU_TX_ERR_IMR_SET},
176 {R_BE_MPDU_RX_ERR_IMR, B_BE_MPDU_RX_ERR_IMR_CLR, B_BE_MPDU_RX_ERR_IMR_SET},
177 {R_BE_SEC_ERROR_IMR, B_BE_SEC_ERROR_IMR_CLR, B_BE_SEC_ERROR_IMR_SET},
178 {R_BE_CPUIO_ERR_IMR, B_BE_CPUIO_ERR_IMR_CLR, B_BE_CPUIO_ERR_IMR_SET},
179 {R_BE_WDE_ERR_IMR, B_BE_WDE_ERR_IMR_CLR, B_BE_WDE_ERR_IMR_SET},
180 {R_BE_PLE_ERR_IMR, B_BE_PLE_ERR_IMR_CLR, B_BE_PLE_ERR_IMR_SET},
181 {R_BE_WDRLS_ERR_IMR, B_BE_WDRLS_ERR_IMR_CLR, B_BE_WDRLS_ERR_IMR_SET},
182 {R_BE_TXPKTCTL_B0_ERRFLAG_IMR, B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR,
183 B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET},
184 {R_BE_TXPKTCTL_B1_ERRFLAG_IMR, B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR,
185 B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET},
186 {R_BE_BBRPT_COM_ERR_IMR, B_BE_BBRPT_COM_ERR_IMR_CLR, B_BE_BBRPT_COM_ERR_IMR_SET},
187 {R_BE_BBRPT_CHINFO_ERR_IMR, B_BE_BBRPT_CHINFO_ERR_IMR_CLR,
188 B_BE_BBRPT_CHINFO_ERR_IMR_SET},
189 {R_BE_BBRPT_DFS_ERR_IMR, B_BE_BBRPT_DFS_ERR_IMR_CLR, B_BE_BBRPT_DFS_ERR_IMR_SET},
190 {R_BE_LA_ERRFLAG_IMR, B_BE_LA_ERRFLAG_IMR_CLR, B_BE_LA_ERRFLAG_IMR_SET},
191 {R_BE_CH_INFO_DBGFLAG_IMR, B_BE_CH_INFO_DBGFLAG_IMR_CLR, B_BE_CH_INFO_DBGFLAG_IMR_SET},
192 {R_BE_PLRLS_ERR_IMR_V1, B_BE_PLRLS_ERR_IMR_V1_CLR, B_BE_PLRLS_ERR_IMR_V1_SET},
193 {R_BE_HAXI_IDCT_MSK, B_BE_HAXI_IDCT_MSK_CLR, B_BE_HAXI_IDCT_MSK_SET},
194 };
195
196 static const struct rtw89_imr_table rtw8922d_imr_dmac_table = {
197 .regs = rtw8922d_imr_dmac_regs,
198 .n_regs = ARRAY_SIZE(rtw8922d_imr_dmac_regs),
199 };
200
201 static const struct rtw89_reg_imr rtw8922d_imr_cmac_regs[] = {
202 {R_BE_RESP_IMR, B_BE_RESP_IMR_CLR_V1, B_BE_RESP_IMR_SET_V1},
203 {R_BE_RESP_IMR1, B_BE_RESP_IMR1_CLR, B_BE_RESP_IMR1_SET},
204 {R_BE_RX_ERROR_FLAG_IMR, B_BE_RX_ERROR_FLAG_IMR_CLR_V1, B_BE_RX_ERROR_FLAG_IMR_SET_V1},
205 {R_BE_TX_ERROR_FLAG_IMR, B_BE_TX_ERROR_FLAG_IMR_CLR, B_BE_TX_ERROR_FLAG_IMR_SET},
206 {R_BE_RX_ERROR_FLAG_IMR_1, B_BE_TX_ERROR_FLAG_IMR_1_CLR, B_BE_TX_ERROR_FLAG_IMR_1_SET},
207 {R_BE_PTCL_IMR1, B_BE_PTCL_IMR1_CLR, B_BE_PTCL_IMR1_SET},
208 {R_BE_PTCL_IMR0, B_BE_PTCL_IMR0_CLR, B_BE_PTCL_IMR0_SET},
209 {R_BE_PTCL_IMR_2, B_BE_PTCL_IMR_2_CLR, B_BE_PTCL_IMR_2_SET},
210 {R_BE_SCHEDULE_ERR_IMR, B_BE_SCHEDULE_ERR_IMR_CLR, B_BE_SCHEDULE_ERR_IMR_SET},
211 {R_BE_C0_TXPWR_IMR, B_BE_C0_TXPWR_IMR_CLR, B_BE_C0_TXPWR_IMR_SET},
212 {R_BE_TRXPTCL_ERROR_INDICA_MASK, B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR,
213 B_BE_TRXPTCL_ERROR_INDICA_MASK_SET},
214 {R_BE_RX_ERR_IMR, B_BE_RX_ERR_IMR_CLR, B_BE_RX_ERR_IMR_SET},
215 {R_BE_PHYINFO_ERR_IMR_V1, B_BE_PHYINFO_ERR_IMR_V1_CLR, B_BE_PHYINFO_ERR_IMR_V1_SET},
216 };
217
218 static const struct rtw89_imr_table rtw8922d_imr_cmac_table = {
219 .regs = rtw8922d_imr_cmac_regs,
220 .n_regs = ARRAY_SIZE(rtw8922d_imr_cmac_regs),
221 };
222
223 static const struct rtw89_rrsr_cfgs rtw8922d_rrsr_cfgs = {
224 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
225 .rsc = {R_BE_PTCL_RRSR1, B_BE_RSC_MASK, 2},
226 };
227
228 static const struct rtw89_rfkill_regs rtw8922d_rfkill_regs = {
229 .pinmux = {R_BE_GPIO8_15_FUNC_SEL,
230 B_BE_PINMUX_GPIO9_FUNC_SEL_MASK,
231 0xf},
232 .mode = {R_BE_GPIO_EXT_CTRL + 2,
233 (B_BE_GPIO_MOD_9 | B_BE_GPIO_IO_SEL_9) >> 16,
234 0x0},
235 };
236
237 static const struct rtw89_dig_regs rtw8922d_dig_regs = {
238 .seg0_pd_reg = R_SEG0R_PD_BE4,
239 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
240 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
241 .bmode_pd_reg = R_BMODE_PDTH_EN_BE4,
242 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
243 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_BE4,
244 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
245 .p0_lna_init = {R_PATH0_LNA_INIT_BE4, B_PATH0_LNA_INIT_IDX_BE4},
246 .p1_lna_init = {R_PATH1_LNA_INIT_BE4, B_PATH1_LNA_INIT_IDX_BE4},
247 .p0_tia_init = {R_PATH0_TIA_INIT_BE4, B_PATH0_TIA_INIT_IDX_BE4},
248 .p1_tia_init = {R_PATH1_TIA_INIT_BE4, B_PATH1_TIA_INIT_IDX_BE4},
249 .p0_rxb_init = {R_PATH0_RXIDX_INIT_BE4, B_PATH0_RXIDX_INIT_BE4},
250 .p1_rxb_init = {R_PATH1_RXIDX_INIT_BE4, B_PATH1_RXIDX_INIT_BE4},
251 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_BE4,
252 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
253 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_BE4,
254 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
255 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_BE4,
256 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
257 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_BE4,
258 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
259 };
260
261 static const struct rtw89_edcca_regs rtw8922d_edcca_regs = {
262 .edcca_level = R_SEG0R_EDCCA_LVL_BE4,
263 .edcca_mask = B_EDCCA_LVL_MSK0,
264 .edcca_p_mask = B_EDCCA_LVL_MSK1,
265 .ppdu_level = R_SEG0R_PPDU_LVL_BE4,
266 .ppdu_mask = B_EDCCA_LVL_MSK1,
267 .p = {{
268 .rpt_a = R_EDCCA_RPT_A_BE4,
269 .rpt_b = R_EDCCA_RPT_B_BE4,
270 .rpt_sel = R_EDCCA_RPT_SEL_BE4,
271 .rpt_sel_mask = B_EDCCA_RPT_SEL_BE4_MSK,
272 }, {
273 .rpt_a = R_EDCCA_RPT_A_BE4_C1,
274 .rpt_b = R_EDCCA_RPT_A_BE4_C1,
275 .rpt_sel = R_EDCCA_RPT_SEL_BE4_C1,
276 .rpt_sel_mask = B_EDCCA_RPT_SEL_BE4_MSK,
277 }},
278 .rpt_sel_be = R_EDCCA_RPTREG_SEL_BE4,
279 .rpt_sel_be_mask = B_EDCCA_RPTREG_SEL_BE_MSK,
280 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST_BE4,
281 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
282 };
283
284 static const struct rtw89_pmac_regs rtw8922d_pmac_regs = {
285 .cck_txon = {R_CNT_CCKTXON_BE4, B_CNT_CCKTXON},
286 .cck_txen = {R_CNT_CCKTXEN_BE4, B_CNT_CCKTXEN},
287 .cck_cca = {R_CNT_CCK_CCA_BE4, B_CNT_CCK_CCA_BE4},
288 .cck_sfd_gg = {R_SFD_GG_CNT_BE4, B_SFD_GG_CNT},
289 .cck_sig_gg = {R_SIG_GG_CNT_BE4, B_SIG_GG_CNT_V1},
290 .cck_spoofing = {R_SPOOF_CNT_BE4, B_SPOOF_CNT_V1},
291 .cck_brk = {R_BRK_CNT_BE4, B_BRK_CNT},
292 .brk = {R_CNT_BRK_BE4, B_CNT_BRK},
293 .brk_option = {},
294 .search_fail = {R_CNT_SEARCH_FAIL_BE4, B_CNT_SEARCH_FAIL},
295 .lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH_BE4, B_CNT_LSIG_BRK_S_TH},
296 .lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH_BE4, B_CNT_LSIG_BRK_L_TH},
297 .rxl_err_parity = {R_CNT_RXL_ERR_PARITY_BE4, B_CNT_RXL_ERR_PARITY},
298 .rxl_err_rate = {R_CNT_RXL_ERR_RATE_BE4, B_CNT_RXL_ERR_RATE},
299 .ofdm_cca = {R_CNT_OFDM_CCA_BE4, B_CNT_OFDM_CCA},
300 .cca_spoofing = {R_CNT_CCA_SPOOFING_BE4, B_CNT_CCA_SPOOFING},
301 .ampdu_miss = {R_CNT_AMPDU_MISS_BE4, B_CNT_AMPDU_MISS},
302 .r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_BE4, B_R1B_RX_RPT_RST_V1},
303 .r1b_rr_sel = {},
304 .enable_all_cnt = {R_ENABLE_ALL_CNT_BE4, B_ENABLE_ALL_CNT},
305 .rst_all_cnt = {R_RST_ALL_CNT_BE4, B_RST_ALL_CNT},
306 .cck_crc32 = R_CNT_CCK_CRC32_BE4,
307 .cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_BE4,
308 .cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_BE4,
309 .ofdm_txon = R_CNT_OFDMTXON_BE4,
310 .ofdm_txon_mask = B_CNT_OFDMTXON,
311 .ofdm_txen_mask = B_CNT_OFDMTXEN,
312 .l_crc = R_CNT_L_CRC_BE4,
313 .l_crc_ok_mask = B_CNT_L_CRC_OK,
314 .l_crc_err_mask = B_CNT_L_CRC_ERR,
315 .ht_crc = R_CNT_HT_CRC_BE4,
316 .ht_crc_ok_mask = B_CNT_HT_CRC_OK,
317 .ht_crc_err_mask = B_CNT_HT_CRC_ERR,
318 .vht_crc = R_CNT_VHT_CRC_BE4,
319 .vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
320 .vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
321 .he_crc = R_CNT_HE_CRC_BE4,
322 .he_crc_ok_mask = B_CNT_HE_CRC_OK,
323 .he_crc_err_mask = B_CNT_HE_CRC_ERR,
324 .eht_crc = R_CNT_EHT_CRC_BE4,
325 .eht_crc_ok_mask = B_CNT_EHT_CRC_OK,
326 .eht_crc_err_mask = B_CNT_EHT_CRC_ERR,
327 .ampdu_crc = R_CNT_AMPDU_RX_CRC32_BE4,
328 .ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
329 .ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
330 };
331
332 static const struct rtw89_efuse_block_cfg rtw8922d_efuse_blocks[] = {
333 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
334 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
335 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
336 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
337 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x400},
338 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
339 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x50},
340 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
341 };
342
343 static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7025 = {
344 .bands = {
345 [RFSI_CTRL_BAND_5_6GHZ] = {
346 .cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_ENABLE, CIM3K_ENABLE},
347 .rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
348 _8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
349 .pb_tb = 3,
350 },
351 [RFSI_CTRL_BAND_2GHZ] = {
352 .cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_ENABLE, CIM3K_ENABLE},
353 .rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
354 _8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
355 .pb_tb = 0,
356 }},
357 .qam_th = {RFSI_BPSK, RFSI_QPSK, RFSI_256QAM, RFSI_MAX, RFSI_MAX, RFSI_MAX},
358 };
359
360 static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7090 = {
361 .bands = {
362 [RFSI_CTRL_BAND_5_6GHZ] = {
363 .cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_DISABLE, CIM3K_ENABLE},
364 .rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
365 _8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
366 .pb_tb = 3,
367 },
368 [RFSI_CTRL_BAND_2GHZ] = {
369 .cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_DISABLE, CIM3K_ENABLE},
370 .rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
371 _8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
372 .pb_tb = 0,
373 }},
374 .qam_th = {RFSI_BPSK, RFSI_QPSK, RFSI_256QAM, RFSI_MAX, RFSI_MAX, RFSI_MAX},
375 };
376
377 static const
378 struct rtw89_bb_wrap_common_data_gen3 rtw8922d_bb_wrap_common_data_gen3_7090 = {
379 .bands = {
380 [RFSI_CTRL_BAND_5_6GHZ] = {
381 .qam_th = {RFSI_QPSK, RFSI_BPSK, RFSI_256QAM, RFSI_MAX,
382 RFSI_MAX, RFSI_MAX},
383 },
384 [RFSI_CTRL_BAND_2GHZ] = {
385 .qam_th = {RFSI_MAX, RFSI_MAX, RFSI_256QAM, RFSI_MAX,
386 RFSI_MAX, RFSI_MAX},
387 }},
388 .cck_val = {CFIR_OFF, FILTER_A_OFF},
389 };
390
391 static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7025_default = {
392 .common = &rtw8922d_bb_wrap_common_data_7025,
393 .common_gen3 = NULL,
394 .bands = {
395 [RFSI_CTRL_BAND_5_6GHZ] = {
396 .qam_comp_th0 = {0x4000, 0x6400, 0x6500, 0x6000, 0, 0, 0, 0, 0, 0},
397 .qam_comp_th1 = {_10qam_comp_code(0x4000, 0x6400, 0x6500, 0x6000,
398 0, 0, 0, 0, 0, 0)},
399 .qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0x4000,
400 0, 0, 0, 0, 0, 0)},
401 .qam_comp_ow = {0x4000, 0x4400, 0x4400, 0x4000, 0, 0, 0, 0, 0, 0},
402 .oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
403 OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
404 },
405 [RFSI_CTRL_BAND_2GHZ] = {
406 .qam_comp_th0 = {0x4000, 0x4400, 0x4500, 0, 0, 0, 0, 0, 0, 0},
407 .qam_comp_th1 = {_10qam_comp_code(0x4000, 0x4400, 0x4500, 0,
408 0, 0, 0, 0, 0, 0)},
409 .qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0,
410 0, 0, 0, 0, 0, 0)},
411 .qam_comp_ow = {0x4000, 0x4400, 0x4400, 0, 0, 0, 0, 0, 0, 0},
412 .oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
413 OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
414 }},
415 .mdpd_by_dbw = {MDPD_ON, MDPD_ON, MDPD_ON, MDPD_ON},
416 };
417
418 static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_default = {
419 .common = &rtw8922d_bb_wrap_common_data_7090,
420 .common_gen3 = &rtw8922d_bb_wrap_common_data_gen3_7090,
421 .bands = {
422 [RFSI_CTRL_BAND_5_6GHZ] = {
423 .qam_comp_th0 = {0x4000, 0x6420, 0x6520, 0x6000, 0, 0, 0, 0, 0, 0},
424 .qam_comp_th1 = {_10qam_comp_code(0x4000, 0x6400, 0x6500, 0x6000,
425 0, 0, 0, 0, 0, 0)},
426 .qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0x4000,
427 0, 0, 0, 0, 0, 0)},
428 .qam_comp_ow = {0x4000, 0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0},
429 .oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
430 OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
431 },
432 [RFSI_CTRL_BAND_2GHZ] = {
433 .qam_comp_th0 = {0x4000, 0x4400, 0x4500, 0, 0, 0, 0, 0, 0, 0},
434 .qam_comp_th1 = {_10qam_comp_code(0x4000, 0x4400, 0x4500, 0, 0,
435 0, 0, 0, 0, 0)},
436 .qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0, 0,
437 0, 0, 0, 0, 0)},
438 .qam_comp_ow = {0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0, 0},
439 .oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
440 OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
441 }},
442 .mdpd_by_dbw = {MDPD_OFF, MDPD_OFF, MDPD_ON, MDPD_ON},
443 };
444
445 static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_rfe35_41_44 = {
446 .common = &rtw8922d_bb_wrap_common_data_7090,
447 .common_gen3 = &rtw8922d_bb_wrap_common_data_gen3_7090,
448 .bands = {
449 [RFSI_CTRL_BAND_5_6GHZ] = {
450 .qam_comp_th0 = {0x4000, 0x6420, 0x6520, 0x6000, 0, 0, 0, 0, 0, 0},
451 .qam_comp_th1 = {_10qam_comp_code(0x4000, 0x6400, 0x6500, 0x6000,
452 0, 0, 0, 0, 0, 0)},
453 .qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0x4000,
454 0, 0, 0, 0, 0, 0)},
455 .qam_comp_ow = {0x4000, 0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0},
456 .oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
457 OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
458 },
459 [RFSI_CTRL_BAND_2GHZ] = {
460 .qam_comp_th0 = {0x4000, 0x4400, 0x4500, 0, 0, 0, 0, 0, 0, 0},
461 .qam_comp_th1 = {_10qam_comp_code(0x4000, 0x4400, 0x4500, 0, 0,
462 0, 0, 0, 0, 0)},
463 .qam_comp_th2 = {_10qam_comp_code(0x4000, 0x4400, 0x4400, 0, 0,
464 0, 0, 0, 0, 0)},
465 .qam_comp_ow = {0x4000, 0x4000, 0x4000, 0, 0, 0, 0, 0, 0, 0},
466 .oob_dpd_by_cbw = {OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF,
467 OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF, OOB_DPD_OFF},
468 }},
469 .mdpd_by_dbw = {MDPD_OFF, MDPD_OFF, MDPD_ON, MDPD_ON},
470 };
471
rtw8922d_sel_bt_rx_path(struct rtw89_dev * rtwdev,u8 val,enum rtw89_rf_path rx_path)472 static void rtw8922d_sel_bt_rx_path(struct rtw89_dev *rtwdev, u8 val,
473 enum rtw89_rf_path rx_path)
474 {
475 if (rx_path == RF_PATH_A)
476 rtw89_phy_write32_mask(rtwdev, R_SEL_GNT_BT_RX_BE4,
477 B_SEL_GNT_BT_RX_PATH0_BE4, val);
478 else if (rx_path == RF_PATH_B)
479 rtw89_phy_write32_mask(rtwdev, R_SEL_GNT_BT_RX_BE4,
480 B_SEL_GNT_BT_RX_PATH1_BE4, val);
481 else
482 rtw89_warn(rtwdev, "[%s] Not support path = %d\n", __func__, rx_path);
483 }
484
rtw8922d_sel_bt_rx_phy(struct rtw89_dev * rtwdev,u8 val,enum rtw89_phy_idx phy_idx)485 static void rtw8922d_sel_bt_rx_phy(struct rtw89_dev *rtwdev, u8 val,
486 enum rtw89_phy_idx phy_idx)
487 {
488 rtw89_phy_write32_idx(rtwdev, R_SEL_GNT_BT_RXPHY_BE4,
489 B_SEL_GNT_BT_RXPHY_BE4, val, phy_idx);
490 }
491
rtw8922d_set_gbt_bt_rx_sel(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)492 static void rtw8922d_set_gbt_bt_rx_sel(struct rtw89_dev *rtwdev, bool en,
493 enum rtw89_phy_idx phy_idx)
494 {
495 rtw8922d_sel_bt_rx_path(rtwdev, 0x3, RF_PATH_A);
496 rtw8922d_sel_bt_rx_phy(rtwdev, 0x0, RTW89_PHY_0);
497 rtw8922d_sel_bt_rx_path(rtwdev, 0x3, RF_PATH_B);
498 rtw8922d_sel_bt_rx_phy(rtwdev, 0x0, RTW89_PHY_1);
499 }
500
rtw8922d_pwr_on_func(struct rtw89_dev * rtwdev)501 static int rtw8922d_pwr_on_func(struct rtw89_dev *rtwdev)
502 {
503 struct rtw89_hal *hal = &rtwdev->hal;
504 u32 val32;
505 int ret;
506
507 if (hal->cid != RTL8922D_CID7025)
508 goto begin;
509
510 switch (hal->cv) {
511 case CHIP_CAV:
512 case CHIP_CBV:
513 rtw89_write32_set(rtwdev, R_BE_SPS_DIG_ON_CTRL1, B_BE_PWM_FORCE);
514 rtw89_write32_set(rtwdev, R_BE_SPS_ANA_ON_CTRL1, B_BE_PWM_FORCE_ANA);
515 break;
516 default:
517 break;
518 }
519
520 begin:
521 val32 = rtw89_read32(rtwdev, R_BE_SYS_PW_CTRL);
522 val32 &= ~(B_BE_AFSM_WLSUS_EN | B_BE_AFSM_PCIE_SUS_EN | B_BE_APFM_SWLPS);
523 val32 |= B_BE_DIS_WLBT_PDNSUSEN_SOPC;
524 if (hal->cid != RTL8922D_CID7090)
525 val32 &= ~B_BE_APDM_HPDN;
526 rtw89_write32(rtwdev, R_BE_SYS_PW_CTRL, val32);
527
528 rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_DIS_WLBT_LPSEN_LOPC);
529 rtw89_write32_clr(rtwdev, R_BE_FWS1ISR, B_BE_FS_WL_HW_RADIO_OFF_INT);
530
531 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_RDY_SYSPWR,
532 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
533 if (ret)
534 return ret;
535
536 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
537 rtw89_write32_set(rtwdev, R_BE_WLRESUME_CTRL, B_BE_LPSROP_CMAC0 |
538 B_BE_LPSROP_CMAC1);
539
540 if (hal->aid == RTL8922D_AID7102) {
541 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_AONLDO_CTRL, 0, 0x20);
542 if (ret)
543 return ret;
544
545 udelay(1);
546
547 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_AONLDO_CTRL, 0, 0x40);
548 if (ret)
549 return ret;
550 }
551
552 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFN_ONMAC);
553
554 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFN_ONMAC),
555 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
556 if (ret)
557 return ret;
558
559 rtw89_write8_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_PLATFORM_EN);
560 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
561
562 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HAXIDMA_IO_ST,
563 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
564 if (ret)
565 return ret;
566
567 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
568 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
569 if (ret)
570 return ret;
571
572 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
573
574 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HCI_WLAN_IO_ST,
575 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
576 if (ret)
577 return ret;
578
579 rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN);
580
581 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_NORMAL_WRITE, 0x10, 0x10);
582 if (ret)
583 return ret;
584
585 rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL,
586 B_BE_SYM_PADPDN_WL_RFC1_1P3 | B_BE_SYM_PADPDN_WL_RFC0_1P3);
587
588 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
589 if (ret)
590 return ret;
591
592 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
593 if (ret)
594 return ret;
595 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
596 if (ret)
597 return ret;
598 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
599 if (ret)
600 return ret;
601 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10);
602 if (ret)
603 return ret;
604 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF);
605 if (ret)
606 return ret;
607 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF);
608 if (ret)
609 return ret;
610 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
611 if (ret)
612 return ret;
613 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
614 if (ret)
615 return ret;
616 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80);
617 if (ret)
618 return ret;
619 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, 0x70);
620 if (ret)
621 return ret;
622 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, 0x02);
623 if (ret)
624 return ret;
625
626 rtw89_write32_set(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
627 rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
628 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
629
630 mdelay(1);
631
632 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
633 rtw89_write32_clr(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
634
635 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
636 B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN |
637 B_BE_MPDU_PROC_EN | B_BE_WD_RLS_EN |
638 B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
639 B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN |
640 B_BE_PKT_BUF_EN | B_BE_DMAC_TBL_EN |
641 B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
642 B_BE_DISPATCHER_EN | B_BE_BBRPT_EN |
643 B_BE_MAC_SEC_EN | B_BE_H_AXIDMA_EN |
644 B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
645 B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN |
646 B_BE_LTR_CTL_EN);
647
648 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
649
650 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
651 B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN |
652 B_BE_ADDRSRCH_EN | B_BE_BTCOEX_EN);
653
654 rtw89_write32_set(rtwdev, R_BE_CMAC_FUNC_EN,
655 B_BE_CMAC_EN | B_BE_CMAC_TXEN |
656 B_BE_CMAC_RXEN | B_BE_SIGB_EN |
657 B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN |
658 B_BE_PTCLTOP_EN | B_BE_SCHEDULER_EN |
659 B_BE_TMAC_EN | B_BE_RMAC_EN |
660 B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN);
661
662 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
663
664 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
665 B_BE_FEN_BB_IP_RSTN | B_BE_FEN_BBPLAT_RSTB);
666
667 return 0;
668 }
669
rtw8922d_pwr_off_func(struct rtw89_dev * rtwdev)670 static int rtw8922d_pwr_off_func(struct rtw89_dev *rtwdev)
671 {
672 u32 val32;
673 int ret;
674
675 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
676 if (ret)
677 return ret;
678 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08);
679 if (ret)
680 return ret;
681 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04);
682 if (ret)
683 return ret;
684 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, 0x01);
685 if (ret)
686 return ret;
687 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, 0x01);
688 if (ret)
689 return ret;
690 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
691 if (ret)
692 return ret;
693 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02);
694 if (ret)
695 return ret;
696 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01);
697 if (ret)
698 return ret;
699
700 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
701 rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
702 B_BE_FEN_BBPLAT_RSTB);
703 rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL,
704 B_BE_SYM_PADPDN_WL_RFC0_1P3);
705
706 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20);
707 if (ret)
708 return ret;
709
710 rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL,
711 B_BE_SYM_PADPDN_WL_RFC1_1P3);
712
713 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40);
714 if (ret)
715 return ret;
716
717 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
718
719 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_IO_ST),
720 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
721 if (ret)
722 return ret;
723 ret = read_poll_timeout(rtw89_read32, val32,
724 !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
725 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
726 if (ret)
727 return ret;
728
729 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
730
731 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HCI_WLAN_IO_ST),
732 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
733 if (ret)
734 return ret;
735
736 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
737
738 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFM_OFFMAC),
739 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
740 if (ret)
741 return ret;
742
743 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x00015002);
744 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
745 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
746 rtw89_write32(rtwdev, R_BE_UDM1, 0);
747
748 return 0;
749 }
750
rtw8922d_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8922d_efuse * map)751 static void rtw8922d_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
752 struct rtw8922d_efuse *map)
753 {
754 const struct rtw8922d_tssi_offset_6g * const ofst_6g[] = {
755 &map->path_a_tssi_6g,
756 &map->path_b_tssi_6g,
757 };
758 const struct rtw8922d_tssi_offset * const ofst[] = {
759 &map->path_a_tssi,
760 &map->path_b_tssi,
761 };
762 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
763 u8 i, j;
764
765 tssi->thermal[RF_PATH_A] = map->path_a_therm;
766 tssi->thermal[RF_PATH_B] = map->path_b_therm;
767
768 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
769 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, TSSI_CCK_CH_GROUP_NUM);
770
771 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
772 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
773 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
774 i, j, tssi->tssi_cck[i][j]);
775
776 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
777 TSSI_MCS_2G_CH_GROUP_NUM);
778 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
779 ofst[i]->bw40_1s_tssi_5g, TSSI_MCS_5G_CH_GROUP_NUM);
780 memcpy(tssi->tssi_6g_mcs[i], ofst_6g[i]->bw40_1s_tssi_6g,
781 TSSI_MCS_6G_CH_GROUP_NUM);
782
783 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
784 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
785 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
786 i, j, tssi->tssi_mcs[i][j]);
787
788 for (j = 0; j < TSSI_MCS_6G_CH_GROUP_NUM; j++)
789 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
790 "[TSSI][EFUSE] path=%d mcs_6g[%d]=0x%x\n",
791 i, j, tssi->tssi_6g_mcs[i][j]);
792 }
793 }
794
795 static void
__rtw8922d_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,s8 offset[RTW89_GAIN_OFFSET_NR],const s8 * offset_default,const struct rtw8922d_rx_gain * rx_gain,const struct rtw8922d_rx_gain_6g * rx_gain_6g)796 __rtw8922d_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
797 s8 offset[RTW89_GAIN_OFFSET_NR],
798 const s8 *offset_default,
799 const struct rtw8922d_rx_gain *rx_gain,
800 const struct rtw8922d_rx_gain_6g *rx_gain_6g)
801 {
802 int i;
803 u8 t;
804
805 offset[RTW89_GAIN_OFFSET_2G_CCK] = rx_gain->_2g_cck;
806 offset[RTW89_GAIN_OFFSET_2G_OFDM] = rx_gain->_2g_ofdm;
807 offset[RTW89_GAIN_OFFSET_5G_LOW] = rx_gain->_5g_low;
808 offset[RTW89_GAIN_OFFSET_5G_MID] = rx_gain->_5g_mid;
809 offset[RTW89_GAIN_OFFSET_5G_HIGH] = rx_gain->_5g_high;
810 offset[RTW89_GAIN_OFFSET_6G_L0] = rx_gain_6g->_6g_l0;
811 offset[RTW89_GAIN_OFFSET_6G_L1] = rx_gain_6g->_6g_l1;
812 offset[RTW89_GAIN_OFFSET_6G_M0] = rx_gain_6g->_6g_m0;
813 offset[RTW89_GAIN_OFFSET_6G_M1] = rx_gain_6g->_6g_m1;
814 offset[RTW89_GAIN_OFFSET_6G_H0] = rx_gain_6g->_6g_h0;
815 offset[RTW89_GAIN_OFFSET_6G_H1] = rx_gain_6g->_6g_h1;
816 offset[RTW89_GAIN_OFFSET_6G_UH0] = rx_gain_6g->_6g_uh0;
817 offset[RTW89_GAIN_OFFSET_6G_UH1] = rx_gain_6g->_6g_uh1;
818
819 for (i = 0; i < RTW89_GAIN_OFFSET_NR; i++) {
820 t = offset[i];
821 if (t == 0xff) {
822 if (offset_default) {
823 offset[i] = offset_default[i];
824 continue;
825 }
826 t = 0;
827 }
828
829 /* transform: sign-bit + U(7,2) to S(8,2) */
830 if (t & 0x80)
831 offset[i] = (t ^ 0x7f) + 1;
832 else
833 offset[i] = t;
834 }
835 }
836
rtw8922d_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8922d_efuse * map)837 static void rtw8922d_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
838 struct rtw8922d_efuse *map)
839 {
840 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
841
842 __rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset[RF_PATH_A],
843 NULL,
844 &map->rx_gain_a, &map->rx_gain_6g_a);
845 __rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset[RF_PATH_B],
846 NULL,
847 &map->rx_gain_b, &map->rx_gain_6g_b);
848
849 __rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset2[RF_PATH_A],
850 gain->offset[RF_PATH_A],
851 &map->rx_gain_a_2, &map->rx_gain_6g_a_2);
852 __rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset2[RF_PATH_B],
853 gain->offset[RF_PATH_B],
854 &map->rx_gain_b_2, &map->rx_gain_6g_b_2);
855
856 gain->offset_valid = true;
857 }
858
rtw8922d_read_efuse_pci_sdio(struct rtw89_dev * rtwdev,u8 * log_map)859 static int rtw8922d_read_efuse_pci_sdio(struct rtw89_dev *rtwdev, u8 *log_map)
860 {
861 struct rtw89_efuse *efuse = &rtwdev->efuse;
862
863 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
864 ether_addr_copy(efuse->addr, log_map + 0x4104);
865 else
866 ether_addr_copy(efuse->addr, log_map + 0x001A);
867
868 return 0;
869 }
870
rtw8922d_read_efuse_usb(struct rtw89_dev * rtwdev,u8 * log_map)871 static int rtw8922d_read_efuse_usb(struct rtw89_dev *rtwdev, u8 *log_map)
872 {
873 struct rtw89_efuse *efuse = &rtwdev->efuse;
874
875 ether_addr_copy(efuse->addr, log_map + 0x0078);
876
877 return 0;
878 }
879
rtw8922d_read_efuse_rf(struct rtw89_dev * rtwdev,u8 * log_map)880 static int rtw8922d_read_efuse_rf(struct rtw89_dev *rtwdev, u8 *log_map)
881 {
882 struct rtw8922d_efuse *map = (struct rtw8922d_efuse *)log_map;
883 struct rtw89_efuse *efuse = &rtwdev->efuse;
884
885 efuse->rfe_type = map->rfe_type;
886 efuse->xtal_cap = map->xtal_k;
887 efuse->country_code[0] = map->country_code[0];
888 efuse->country_code[1] = map->country_code[1];
889 efuse->bt_setting_2 = map->bt_setting_2;
890 efuse->bt_setting_3 = map->bt_setting_3;
891 rtw8922d_efuse_parsing_tssi(rtwdev, map);
892 rtw8922d_efuse_parsing_gain_offset(rtwdev, map);
893
894 return 0;
895 }
896
rtw8922d_read_sys(struct rtw89_dev * rtwdev,u8 * log_map)897 static int rtw8922d_read_sys(struct rtw89_dev *rtwdev, u8 *log_map)
898 {
899 struct rtw89_efuse *efuse = &rtwdev->efuse;
900 struct rtw89_hal *hal = &rtwdev->hal;
901 u16 digk;
902 u8 vmin;
903
904 digk = log_map[0x200] | log_map[0x201] << 8;
905 hal->thermal_prot_vmax = u16_get_bits(digk, B_BE_PWMTUNE_MASK);
906
907 if (efuse->dswr_valid)
908 vmin = efuse->dswr_vmin;
909 else if (efuse->vcore_valid)
910 vmin = hal->thermal_prot_vmax - efuse->vcore_vmax_reduce;
911 else
912 vmin = hal->thermal_prot_vmax - 3;
913
914 hal->thermal_prot_vmin = vmin;
915
916 return 0;
917 }
918
rtw8922d_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)919 static int rtw8922d_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
920 enum rtw89_efuse_block block)
921 {
922 switch (block) {
923 case RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO:
924 return rtw8922d_read_efuse_pci_sdio(rtwdev, log_map);
925 case RTW89_EFUSE_BLOCK_HCI_DIG_USB:
926 return rtw8922d_read_efuse_usb(rtwdev, log_map);
927 case RTW89_EFUSE_BLOCK_RF:
928 return rtw8922d_read_efuse_rf(rtwdev, log_map);
929 case RTW89_EFUSE_BLOCK_SYS:
930 return rtw8922d_read_sys(rtwdev, log_map);
931 default:
932 return 0;
933 }
934 }
935
rtw8922d_phycap_parsing_vco_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)936 static void rtw8922d_phycap_parsing_vco_trim(struct rtw89_dev *rtwdev,
937 u8 *phycap_map)
938 {
939 static const u32 vco_trim_addr[RF_PATH_NUM_8922D] = {0x175E, 0x175F};
940 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
941 u32 addr = rtwdev->chip->phycap_addr;
942 const u32 vco_check_addr = 0x1700;
943 u8 val;
944
945 val = phycap_map[vco_check_addr - addr];
946 if (val & BIT(1))
947 return;
948
949 info->pg_vco_trim = true;
950
951 info->vco_trim[0] = u8_get_bits(phycap_map[vco_trim_addr[0] - addr], GENMASK(4, 0));
952 info->vco_trim[1] = u8_get_bits(phycap_map[vco_trim_addr[1] - addr], GENMASK(4, 0));
953 }
954
rtw8922d_vco_trim(struct rtw89_dev * rtwdev)955 static void rtw8922d_vco_trim(struct rtw89_dev *rtwdev)
956 {
957 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
958
959 if (!info->pg_vco_trim)
960 return;
961
962 rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCO, RR_VCO_VAL, info->vco_trim[0]);
963 rtw89_write_rf(rtwdev, RF_PATH_B, RR_VCO, RR_VCO_VAL, info->vco_trim[1]);
964 }
965
966 #define THM_TRIM_POSITIVE_MASK BIT(6)
967 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
968 #define THM_TRIM_MAX (15)
969 #define THM_TRIM_MIN (-15)
970
rtw8922d_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)971 static void rtw8922d_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
972 u8 *phycap_map)
973 {
974 static const u32 thm_trim_addr[RF_PATH_NUM_8922D] = {0x1706, 0x1732};
975 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
976 u32 addr = rtwdev->chip->phycap_addr;
977 bool pg = true;
978 u8 pg_th;
979 s8 val;
980 u8 i;
981
982 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
983 pg_th = phycap_map[thm_trim_addr[i] - addr];
984 if (pg_th == 0xff) {
985 memset(info->thermal_trim, 0, sizeof(info->thermal_trim));
986 pg = false;
987 goto out;
988 }
989
990 val = u8_get_bits(pg_th, THM_TRIM_MAGNITUDE_MASK);
991
992 if (!(pg_th & THM_TRIM_POSITIVE_MASK))
993 val *= -1;
994
995 if (val <= THM_TRIM_MIN || val >= THM_TRIM_MAX) {
996 val = 0;
997 info->thermal_trim[i] = 0;
998 } else {
999 info->thermal_trim[i] = pg_th;
1000 }
1001
1002 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1003 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n",
1004 i, pg_th, val);
1005 }
1006
1007 out:
1008 info->pg_thermal_trim = pg;
1009 }
1010
rtw8922d_thermal_trim(struct rtw89_dev * rtwdev)1011 static void rtw8922d_thermal_trim(struct rtw89_dev *rtwdev)
1012 {
1013 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
1014 u8 thermal;
1015 int i;
1016
1017 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
1018 thermal = info->pg_thermal_trim ? info->thermal_trim[i] : 0;
1019 rtw89_write_rf(rtwdev, i, RR_TM, RR_TM_TRM, thermal & 0x7f);
1020 }
1021 }
1022
rtw8922d_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)1023 static void rtw8922d_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
1024 u8 *phycap_map)
1025 {
1026 static const u32 pabias_trim_addr[RF_PATH_NUM_8922D] = {0x1707, 0x1733};
1027 static const u32 check_pa_pad_trim_addr = 0x1700;
1028 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
1029 u32 addr = rtwdev->chip->phycap_addr;
1030 bool pg = true;
1031 u8 val;
1032 u8 i;
1033
1034 val = phycap_map[check_pa_pad_trim_addr - addr];
1035 if (val == 0xff) {
1036 pg = false;
1037 goto out;
1038 }
1039
1040 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
1041 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
1042
1043 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1044 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
1045 i, info->pa_bias_trim[i]);
1046 }
1047
1048 out:
1049 info->pg_pa_bias_trim = pg;
1050 }
1051
rtw8922d_pa_bias_trim(struct rtw89_dev * rtwdev)1052 static void rtw8922d_pa_bias_trim(struct rtw89_dev *rtwdev)
1053 {
1054 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
1055 u8 pabias_2g, pabias_5g;
1056 u8 i;
1057
1058 if (!info->pg_pa_bias_trim) {
1059 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1060 "[PA_BIAS][TRIM] no PG, do nothing\n");
1061
1062 return;
1063 }
1064
1065 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
1066 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
1067 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
1068
1069 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1070 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
1071 i, pabias_2g, pabias_5g);
1072
1073 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG_V1, pabias_2g);
1074 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA_V1, pabias_5g);
1075 }
1076 }
1077
rtw8922d_phycap_parsing_pad_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)1078 static void rtw8922d_phycap_parsing_pad_bias_trim(struct rtw89_dev *rtwdev,
1079 u8 *phycap_map)
1080 {
1081 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922D] = {0x1708, 0x1734};
1082 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
1083 u32 addr = rtwdev->chip->phycap_addr;
1084 u8 i;
1085
1086 if (!info->pg_pa_bias_trim)
1087 return;
1088
1089 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
1090 info->pad_bias_trim[i] = phycap_map[pad_bias_trim_addr[i] - addr];
1091
1092 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1093 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n",
1094 i, info->pad_bias_trim[i]);
1095 }
1096 }
1097
rtw8922d_pad_bias_trim(struct rtw89_dev * rtwdev)1098 static void rtw8922d_pad_bias_trim(struct rtw89_dev *rtwdev)
1099 {
1100 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
1101 u8 pad_bias_2g, pad_bias_5g;
1102 u8 i;
1103
1104 if (!info->pg_pa_bias_trim) {
1105 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1106 "[PAD_BIAS][TRIM] no PG, do nothing\n");
1107 return;
1108 }
1109
1110 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
1111 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0));
1112 pad_bias_5g = u8_get_bits(info->pad_bias_trim[i], GENMASK(7, 4));
1113
1114 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1115 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
1116 i, pad_bias_2g, pad_bias_5g);
1117
1118 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXG_V1, pad_bias_2g);
1119 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXA_V1, pad_bias_5g);
1120 }
1121 }
1122
rtw8922d_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)1123 static int rtw8922d_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
1124 {
1125 rtw8922d_phycap_parsing_vco_trim(rtwdev, phycap_map);
1126 rtw8922d_phycap_parsing_thermal_trim(rtwdev, phycap_map);
1127 rtw8922d_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
1128 rtw8922d_phycap_parsing_pad_bias_trim(rtwdev, phycap_map);
1129
1130 return 0;
1131 }
1132
rtw8922d_power_trim(struct rtw89_dev * rtwdev)1133 static void rtw8922d_power_trim(struct rtw89_dev *rtwdev)
1134 {
1135 rtw8922d_vco_trim(rtwdev);
1136 rtw8922d_thermal_trim(rtwdev);
1137 rtw8922d_pa_bias_trim(rtwdev);
1138 rtw8922d_pad_bias_trim(rtwdev);
1139 }
1140
rtw8922d_data_setup(struct rtw89_dev * rtwdev)1141 static int rtw8922d_data_setup(struct rtw89_dev *rtwdev)
1142 {
1143 const struct rtw89_bb_wrap_data *data;
1144 struct rtw89_hal *hal = &rtwdev->hal;
1145 bool rfe35_41_44 = false;
1146
1147 switch (rtwdev->efuse.rfe_type) {
1148 case 35:
1149 case 41:
1150 case 44:
1151 rfe35_41_44 = true;
1152 break;
1153 }
1154
1155 if (hal->cid == RTL8922D_CID7025) {
1156 data = &rtw8922d_bb_wrap_data_7025_default;
1157 } else {
1158 if (rfe35_41_44)
1159 data = &rtw8922d_bb_wrap_data_7090_rfe35_41_44;
1160 else
1161 data = &rtw8922d_bb_wrap_data_7090_default;
1162 }
1163
1164 rtwdev->phy_info.bb_wrap_data = data;
1165
1166 return 0;
1167 }
1168
rtw8922d_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)1169 static void rtw8922d_set_channel_mac(struct rtw89_dev *rtwdev,
1170 const struct rtw89_chan *chan,
1171 u8 mac_idx)
1172 {
1173 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_BE_TX_SUB_BAND_VALUE, mac_idx);
1174 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_BE_TXRATE_CHK, mac_idx);
1175 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_RFMOD, mac_idx);
1176 const struct rtw89_chip_info *chip = rtwdev->chip;
1177 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0;
1178 u8 rf_mod_val, chk_rate_mask, sifs;
1179 u16 tx_time = AMPDU_MAX_TIME_V1;
1180 u32 txsb;
1181 u32 reg;
1182
1183 switch (chan->band_width) {
1184 case RTW89_CHANNEL_WIDTH_160:
1185 txsb80 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_80);
1186 fallthrough;
1187 case RTW89_CHANNEL_WIDTH_80:
1188 txsb40 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
1189 fallthrough;
1190 case RTW89_CHANNEL_WIDTH_40:
1191 txsb20 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
1192 break;
1193 default:
1194 break;
1195 }
1196
1197 switch (chan->band_width) {
1198 case RTW89_CHANNEL_WIDTH_160:
1199 rf_mod_val = BE_WMAC_RFMOD_160M;
1200 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
1201 u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK) |
1202 u32_encode_bits(txsb80, B_BE_TXSB_80M_MASK);
1203 break;
1204 case RTW89_CHANNEL_WIDTH_80:
1205 rf_mod_val = BE_WMAC_RFMOD_80M;
1206 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
1207 u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK);
1208 break;
1209 case RTW89_CHANNEL_WIDTH_40:
1210 rf_mod_val = BE_WMAC_RFMOD_40M;
1211 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK);
1212 break;
1213 case RTW89_CHANNEL_WIDTH_20:
1214 default:
1215 rf_mod_val = BE_WMAC_RFMOD_20M;
1216 txsb = 0;
1217 break;
1218 }
1219
1220 if (txsb20 <= BE_PRI20_BITMAP_MAX)
1221 txsb |= u32_encode_bits(BIT(txsb20), B_BE_PRI20_BITMAP_MASK);
1222
1223 rtw89_write8_mask(rtwdev, rf_mod, B_BE_WMAC_RFMOD_MASK, rf_mod_val);
1224 rtw89_write32(rtwdev, sub_carr, txsb);
1225
1226 switch (chan->band_type) {
1227 case RTW89_BAND_2G:
1228 chk_rate_mask = B_BE_BAND_MODE;
1229 break;
1230 case RTW89_BAND_5G:
1231 case RTW89_BAND_6G:
1232 chk_rate_mask = B_BE_CHECK_CCK_EN | B_BE_RTS_LIMIT_IN_OFDM6;
1233 break;
1234 default:
1235 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
1236 return;
1237 }
1238
1239 rtw89_write8_clr(rtwdev, chk_rate, B_BE_BAND_MODE | B_BE_CHECK_CCK_EN |
1240 B_BE_RTS_LIMIT_IN_OFDM6);
1241 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
1242
1243 switch (chan->band_width) {
1244 case RTW89_CHANNEL_WIDTH_160:
1245 sifs = 0x8C;
1246 break;
1247 case RTW89_CHANNEL_WIDTH_80:
1248 sifs = 0x8A;
1249 break;
1250 case RTW89_CHANNEL_WIDTH_40:
1251 sifs = 0x84;
1252 break;
1253 case RTW89_CHANNEL_WIDTH_20:
1254 default:
1255 sifs = 0x82;
1256 }
1257
1258 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MUEDCA_EN, mac_idx);
1259 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_DOT05US_MASK, sifs);
1260
1261 if (chan->band_type == RTW89_BAND_2G && chip->txtime_limit_2ghz)
1262 tx_time = min_t(u32, tx_time, chip->txtime_limit_2ghz * 1000 >> 15);
1263
1264 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1265 rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, tx_time);
1266 }
1267
1268 static const u32 rtw8922d_sco_barker_threshold[14] = {
1269 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
1270 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
1271 };
1272
1273 static const u32 rtw8922d_sco_cck_threshold[14] = {
1274 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
1275 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
1276 };
1277
rtw8922d_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch,enum rtw89_bandwidth bw,enum rtw89_phy_idx phy_idx)1278 static int rtw8922d_ctrl_sco_cck(struct rtw89_dev *rtwdev,
1279 u8 primary_ch, enum rtw89_bandwidth bw,
1280 enum rtw89_phy_idx phy_idx)
1281 {
1282 u8 ch_element;
1283
1284 if (primary_ch >= 14)
1285 return -EINVAL;
1286
1287 ch_element = primary_ch - 1;
1288
1289 rtw89_phy_write32_idx(rtwdev, R_BK_FC0_INV_BE4, B_BK_FC0_INV_BE4,
1290 rtw8922d_sco_barker_threshold[ch_element],
1291 phy_idx);
1292 rtw89_phy_write32_idx(rtwdev, R_CCK_FC0_INV_BE4, B_CCK_FC0_INV_BE4,
1293 rtw8922d_sco_cck_threshold[ch_element],
1294 phy_idx);
1295
1296 return 0;
1297 }
1298
rtw8922d_ctrl_ch_core(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1299 static void rtw8922d_ctrl_ch_core(struct rtw89_dev *rtwdev,
1300 const struct rtw89_chan *chan,
1301 enum rtw89_phy_idx phy_idx)
1302 {
1303 u16 central_freq = chan->freq;
1304 u16 sco;
1305
1306 if (chan->band_type == RTW89_BAND_2G) {
1307 rtw89_phy_write32_idx(rtwdev, R_BAND_SEL0_BE4, B_BAND_SEL0_BE4,
1308 1, phy_idx);
1309 rtw89_phy_write32_idx(rtwdev, R_BAND_SEL1_BE4, B_BAND_SEL1_BE4,
1310 1, phy_idx);
1311 rtw89_phy_write32_idx(rtwdev, R_ENABLE_CCK0_BE4, B_ENABLE_CCK0_BE4,
1312 1, phy_idx);
1313 } else {
1314 rtw89_phy_write32_idx(rtwdev, R_BAND_SEL0_BE4, B_BAND_SEL0_BE4,
1315 0, phy_idx);
1316 rtw89_phy_write32_idx(rtwdev, R_BAND_SEL1_BE4, B_BAND_SEL1_BE4,
1317 0, phy_idx);
1318 rtw89_phy_write32_idx(rtwdev, R_ENABLE_CCK0_BE4, B_ENABLE_CCK0_BE4,
1319 0, phy_idx);
1320 }
1321
1322 rtw89_phy_write32_idx(rtwdev, R_FC0_BE4, B_FC0_BE4, central_freq, phy_idx);
1323
1324 sco = phy_div((BIT(0) << 27) + (central_freq / 2), central_freq);
1325 rtw89_phy_write32_idx(rtwdev, R_FC0_INV_BE4, B_FC0_INV_BE4, sco, phy_idx);
1326 }
1327
1328 struct rtw8922d_bb_gain {
1329 u32 gain_g[BB_PATH_NUM_8922D];
1330 u32 gain_a[BB_PATH_NUM_8922D];
1331 u32 gain_g_mask;
1332 u32 gain_a_mask;
1333 };
1334
1335 static const struct rtw89_reg_def rpl_comp_bw160[RTW89_BW20_SC_160M] = {
1336 { .addr = 0x241E8, .mask = 0xFF00},
1337 { .addr = 0x241E8, .mask = 0xFF0000},
1338 { .addr = 0x241E8, .mask = 0xFF000000},
1339 { .addr = 0x241EC, .mask = 0xFF},
1340 { .addr = 0x241EC, .mask = 0xFF00},
1341 { .addr = 0x241EC, .mask = 0xFF0000},
1342 { .addr = 0x241EC, .mask = 0xFF000000},
1343 { .addr = 0x241F0, .mask = 0xFF}
1344 };
1345
1346 static const struct rtw89_reg_def rpl_comp_bw80[RTW89_BW20_SC_80M] = {
1347 { .addr = 0x241F4, .mask = 0xFF},
1348 { .addr = 0x241F4, .mask = 0xFF00},
1349 { .addr = 0x241F4, .mask = 0xFF0000},
1350 { .addr = 0x241F4, .mask = 0xFF000000}
1351 };
1352
1353 static const struct rtw89_reg_def rpl_comp_bw40[RTW89_BW20_SC_40M] = {
1354 { .addr = 0x241F0, .mask = 0xFF0000},
1355 { .addr = 0x241F0, .mask = 0xFF000000}
1356 };
1357
1358 static const struct rtw89_reg_def rpl_comp_bw20[RTW89_BW20_SC_20M] = {
1359 { .addr = 0x241F0, .mask = 0xFF00}
1360 };
1361
1362 static const struct rtw8922d_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
1363 { .gain_g = {0x2409C, 0x2449C}, .gain_a = {0x2406C, 0x2446C},
1364 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1365 { .gain_g = {0x2409C, 0x2449C}, .gain_a = {0x2406C, 0x2446C},
1366 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1367 { .gain_g = {0x240A0, 0x244A0}, .gain_a = {0x24070, 0x24470},
1368 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1369 { .gain_g = {0x240A0, 0x244A0}, .gain_a = {0x24070, 0x24470},
1370 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1371 { .gain_g = {0x240A4, 0x244A4}, .gain_a = {0x24074, 0x24474},
1372 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1373 { .gain_g = {0x240A4, 0x244A4}, .gain_a = {0x24074, 0x24474},
1374 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1375 { .gain_g = {0x240A8, 0x244A8}, .gain_a = {0x24078, 0x24478},
1376 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1377 };
1378
1379 static const struct rtw8922d_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
1380 { .gain_g = {0x24054, 0x24454}, .gain_a = {0x24054, 0x24454},
1381 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
1382 { .gain_g = {0x24058, 0x24458}, .gain_a = {0x24054, 0x24454},
1383 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
1384 };
1385
1386 static const struct rtw8922d_bb_gain bb_op1db_lna[LNA_GAIN_NUM] = {
1387 { .gain_g = {0x240AC, 0x244AC}, .gain_a = {0x24078, 0x24478},
1388 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
1389 { .gain_g = {0x240AC, 0x244AC}, .gain_a = {0x2407C, 0x2447C},
1390 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
1391 { .gain_g = {0x240AC, 0x244AC}, .gain_a = {0x2407C, 0x2447C},
1392 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1393 { .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x2407C, 0x2447C},
1394 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
1395 { .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x2407C, 0x2447C},
1396 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
1397 { .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x24080, 0x24480},
1398 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
1399 { .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x24080, 0x24480},
1400 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1401 };
1402
1403 static const struct rtw8922d_bb_gain bb_op1db_tia_lna[TIA_LNA_OP1DB_NUM] = {
1404 { .gain_g = {0x240B4, 0x244B4}, .gain_a = {0x24080, 0x24480},
1405 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1406 { .gain_g = {0x240B4, 0x244B4}, .gain_a = {0x24084, 0x24484},
1407 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1408 { .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24084, 0x24484},
1409 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1410 { .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24084, 0x24484},
1411 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1412 { .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24084, 0x24484},
1413 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1414 { .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24088, 0x24488},
1415 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1416 { .gain_g = {0x240BC, 0x244BC}, .gain_a = {0x24088, 0x24488},
1417 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1418 { .gain_g = {0x240BC, 0x244BC}, .gain_a = {0x24088, 0x24488},
1419 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1420 };
1421
rtw8922d_set_rpl_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1422 static void rtw8922d_set_rpl_gain(struct rtw89_dev *rtwdev,
1423 const struct rtw89_chan *chan,
1424 enum rtw89_rf_path path,
1425 enum rtw89_phy_idx phy_idx)
1426 {
1427 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1428 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1429 u32 reg_path_ofst = 0;
1430 u32 mask;
1431 s32 val;
1432 u32 reg;
1433 int i;
1434
1435 if (path == RF_PATH_B)
1436 reg_path_ofst = 0x400;
1437
1438 for (i = 0; i < RTW89_BW20_SC_160M; i++) {
1439 reg = rpl_comp_bw160[i].addr | reg_path_ofst;
1440 mask = rpl_comp_bw160[i].mask;
1441 val = gain->rpl_ofst_160[gain_band][path][i];
1442 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1443 }
1444
1445 for (i = 0; i < RTW89_BW20_SC_80M; i++) {
1446 reg = rpl_comp_bw80[i].addr | reg_path_ofst;
1447 mask = rpl_comp_bw80[i].mask;
1448 val = gain->rpl_ofst_80[gain_band][path][i];
1449 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1450 }
1451
1452 for (i = 0; i < RTW89_BW20_SC_40M; i++) {
1453 reg = rpl_comp_bw40[i].addr | reg_path_ofst;
1454 mask = rpl_comp_bw40[i].mask;
1455 val = gain->rpl_ofst_40[gain_band][path][i];
1456 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1457 }
1458
1459 for (i = 0; i < RTW89_BW20_SC_20M; i++) {
1460 reg = rpl_comp_bw20[i].addr | reg_path_ofst;
1461 mask = rpl_comp_bw20[i].mask;
1462 val = gain->rpl_ofst_20[gain_band][path][i];
1463 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1464 }
1465 }
1466
rtw8922d_set_lna_tia_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1467 static void rtw8922d_set_lna_tia_gain(struct rtw89_dev *rtwdev,
1468 const struct rtw89_chan *chan,
1469 enum rtw89_rf_path path,
1470 enum rtw89_phy_idx phy_idx)
1471 {
1472 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1473 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1474 enum rtw89_phy_bb_bw_be bw_type;
1475 u32 mask;
1476 s32 val;
1477 u32 reg;
1478 int i;
1479
1480 bw_type = chan->band_width <= RTW89_CHANNEL_WIDTH_40 ?
1481 RTW89_BB_BW_20_40 : RTW89_BB_BW_80_160_320;
1482
1483 for (i = 0; i < LNA_GAIN_NUM; i++) {
1484 if (chan->band_type == RTW89_BAND_2G) {
1485 reg = bb_gain_lna[i].gain_g[path];
1486 mask = bb_gain_lna[i].gain_g_mask;
1487 } else {
1488 reg = bb_gain_lna[i].gain_a[path];
1489 mask = bb_gain_lna[i].gain_a_mask;
1490 }
1491 val = gain->lna_gain[gain_band][bw_type][path][i];
1492 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1493 }
1494
1495 for (i = 0; i < TIA_GAIN_NUM; i++) {
1496 if (chan->band_type == RTW89_BAND_2G) {
1497 reg = bb_gain_tia[i].gain_g[path];
1498 mask = bb_gain_tia[i].gain_g_mask;
1499 } else {
1500 reg = bb_gain_tia[i].gain_a[path];
1501 mask = bb_gain_tia[i].gain_a_mask;
1502 }
1503 val = gain->tia_gain[gain_band][bw_type][path][i];
1504 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1505 }
1506 }
1507
rtw8922d_set_op1db(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1508 static void rtw8922d_set_op1db(struct rtw89_dev *rtwdev,
1509 const struct rtw89_chan *chan,
1510 enum rtw89_rf_path path,
1511 enum rtw89_phy_idx phy_idx)
1512 {
1513 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1514 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1515 enum rtw89_phy_bb_bw_be bw_type;
1516 u32 mask;
1517 s32 val;
1518 u32 reg;
1519 int i;
1520
1521 bw_type = chan->band_width <= RTW89_CHANNEL_WIDTH_40 ?
1522 RTW89_BB_BW_20_40 : RTW89_BB_BW_80_160_320;
1523
1524 for (i = 0; i < LNA_GAIN_NUM; i++) {
1525 if (chan->band_type == RTW89_BAND_2G) {
1526 reg = bb_op1db_lna[i].gain_g[path];
1527 mask = bb_op1db_lna[i].gain_g_mask;
1528 } else {
1529 reg = bb_op1db_lna[i].gain_a[path];
1530 mask = bb_op1db_lna[i].gain_a_mask;
1531 }
1532 val = gain->lna_op1db[gain_band][bw_type][path][i];
1533 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1534 }
1535
1536 for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) {
1537 if (chan->band_type == RTW89_BAND_2G) {
1538 reg = bb_op1db_tia_lna[i].gain_g[path];
1539 mask = bb_op1db_tia_lna[i].gain_g_mask;
1540 } else {
1541 reg = bb_op1db_tia_lna[i].gain_a[path];
1542 mask = bb_op1db_tia_lna[i].gain_a_mask;
1543 }
1544 val = gain->tia_lna_op1db[gain_band][bw_type][path][i];
1545 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1546 }
1547 }
1548
rtw8922d_set_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1549 static void rtw8922d_set_gain(struct rtw89_dev *rtwdev,
1550 const struct rtw89_chan *chan,
1551 enum rtw89_rf_path path,
1552 enum rtw89_phy_idx phy_idx)
1553 {
1554 rtw8922d_set_rpl_gain(rtwdev, chan, path, phy_idx);
1555 rtw8922d_set_lna_tia_gain(rtwdev, chan, path, phy_idx);
1556 rtw8922d_set_op1db(rtwdev, chan, path, phy_idx);
1557 }
1558
rtw8922d_get_rx_gain_by_chan(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,bool is_cck)1559 static s8 rtw8922d_get_rx_gain_by_chan(struct rtw89_dev *rtwdev,
1560 const struct rtw89_chan *chan,
1561 enum rtw89_rf_path path, bool is_cck)
1562 {
1563 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1564 enum rtw89_gain_offset band;
1565 u8 fc_ch = chan->channel;
1566 s8 normal_efuse = 0;
1567
1568 if (path > RF_PATH_B)
1569 return 0;
1570
1571 if (is_cck) {
1572 if (fc_ch >= 1 && fc_ch <= 7)
1573 return gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
1574 else if (fc_ch >= 8 && fc_ch <= 14)
1575 return gain->offset2[path][RTW89_GAIN_OFFSET_2G_CCK];
1576
1577 return 0;
1578 }
1579
1580 band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
1581
1582 if (band == RTW89_GAIN_OFFSET_2G_OFDM) {
1583 if (fc_ch >= 1 && fc_ch <= 7)
1584 normal_efuse = gain->offset[path][band];
1585 else if (fc_ch >= 8 && fc_ch <= 14)
1586 normal_efuse = gain->offset2[path][band];
1587 } else if (band == RTW89_GAIN_OFFSET_5G_LOW) {
1588 if (fc_ch == 50)
1589 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1590 else if (fc_ch >= 36 && fc_ch <= 48)
1591 normal_efuse = gain->offset[path][band];
1592 else if (fc_ch >= 52 && fc_ch <= 64)
1593 normal_efuse = gain->offset2[path][band];
1594
1595 } else if (band == RTW89_GAIN_OFFSET_5G_MID) {
1596 if (fc_ch == 122)
1597 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1598 else if (fc_ch >= 100 && fc_ch <= 120)
1599 normal_efuse = gain->offset[path][band];
1600 else if (fc_ch >= 124 && fc_ch <= 144)
1601 normal_efuse = gain->offset2[path][band];
1602 } else if (band == RTW89_GAIN_OFFSET_5G_HIGH) {
1603 if (fc_ch == 163)
1604 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1605 else if (fc_ch >= 149 && fc_ch <= 161)
1606 normal_efuse = gain->offset[path][band];
1607 else if (fc_ch >= 165 && fc_ch <= 177)
1608 normal_efuse = gain->offset2[path][band];
1609 } else if (band == RTW89_GAIN_OFFSET_6G_L0) {
1610 if (fc_ch == 15)
1611 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1612 else if (fc_ch >= 1 && fc_ch <= 13)
1613 normal_efuse = gain->offset[path][band];
1614 else if (fc_ch >= 17 && fc_ch <= 29)
1615 normal_efuse = gain->offset2[path][band];
1616 } else if (band == RTW89_GAIN_OFFSET_6G_L1) {
1617 if (fc_ch == 47)
1618 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1619 else if (fc_ch >= 33 && fc_ch <= 45)
1620 normal_efuse = gain->offset[path][band];
1621 else if (fc_ch >= 49 && fc_ch <= 61)
1622 normal_efuse = gain->offset2[path][band];
1623 } else if (band == RTW89_GAIN_OFFSET_6G_M0) {
1624 if (fc_ch == 79)
1625 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1626 else if (fc_ch >= 65 && fc_ch <= 77)
1627 normal_efuse = gain->offset[path][band];
1628 else if (fc_ch >= 81 && fc_ch <= 93)
1629 normal_efuse = gain->offset2[path][band];
1630 } else if (band == RTW89_GAIN_OFFSET_6G_M1) {
1631 if (fc_ch == 111)
1632 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1633 else if (fc_ch >= 97 && fc_ch <= 109)
1634 normal_efuse = gain->offset[path][band];
1635 else if (fc_ch >= 113 && fc_ch <= 125)
1636 normal_efuse = gain->offset2[path][band];
1637 } else if (band == RTW89_GAIN_OFFSET_6G_H0) {
1638 if (fc_ch == 143)
1639 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1640 else if (fc_ch >= 129 && fc_ch <= 141)
1641 normal_efuse = gain->offset[path][band];
1642 else if (fc_ch >= 145 && fc_ch <= 157)
1643 normal_efuse = gain->offset2[path][band];
1644 } else if (band == RTW89_GAIN_OFFSET_6G_H1) {
1645 if (fc_ch == 175)
1646 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1647 else if (fc_ch >= 161 && fc_ch <= 173)
1648 normal_efuse = gain->offset[path][band];
1649 else if (fc_ch >= 177 && fc_ch <= 189)
1650 normal_efuse = gain->offset2[path][band];
1651 } else if (band == RTW89_GAIN_OFFSET_6G_UH0) {
1652 if (fc_ch == 207)
1653 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1654 else if (fc_ch >= 193 && fc_ch <= 205)
1655 normal_efuse = gain->offset[path][band];
1656 else if (fc_ch >= 209 && fc_ch <= 221)
1657 normal_efuse = gain->offset2[path][band];
1658 } else if (band == RTW89_GAIN_OFFSET_6G_UH1) {
1659 if (fc_ch == 239)
1660 normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1661 else if (fc_ch >= 225 && fc_ch <= 237)
1662 normal_efuse = gain->offset[path][band];
1663 else if (fc_ch >= 241 && fc_ch <= 253)
1664 normal_efuse = gain->offset2[path][band];
1665 } else {
1666 normal_efuse = gain->offset[path][band];
1667 }
1668
1669 return normal_efuse;
1670 }
1671
rtw8922d_calc_rx_gain_normal_cck(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx,struct rtw89_phy_calc_efuse_gain * calc)1672 static void rtw8922d_calc_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
1673 const struct rtw89_chan *chan,
1674 enum rtw89_rf_path path,
1675 enum rtw89_phy_idx phy_idx,
1676 struct rtw89_phy_calc_efuse_gain *calc)
1677 {
1678 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1679 s8 rx_gain_offset;
1680
1681 rx_gain_offset = -rtw8922d_get_rx_gain_by_chan(rtwdev, chan, path, true);
1682 calc->cck_mean_gain_bias = (rx_gain_offset & 0x3) << 1;
1683 calc->cck_rpl_ofst = (rx_gain_offset >> 2) + gain->cck_rpl_base[phy_idx];
1684 }
1685
rtw8922d_set_rx_gain_normal_cck(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1686 static void rtw8922d_set_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
1687 const struct rtw89_chan *chan,
1688 enum rtw89_rf_path path,
1689 enum rtw89_phy_idx phy_idx)
1690 {
1691 struct rtw89_phy_calc_efuse_gain calc = {};
1692
1693 rtw8922d_calc_rx_gain_normal_cck(rtwdev, chan, path, phy_idx, &calc);
1694
1695 rtw89_phy_write32_idx(rtwdev, R_GAIN_BIAS_BE4, B_GAIN_BIAS_BW20_BE4,
1696 calc.cck_mean_gain_bias, phy_idx);
1697 rtw89_phy_write32_idx(rtwdev, R_GAIN_BIAS_BE4, B_GAIN_BIAS_BW40_BE4,
1698 calc.cck_mean_gain_bias, phy_idx);
1699 rtw89_phy_write32_idx(rtwdev, R_CCK_RPL_OFST_BE4, B_CCK_RPL_OFST_BE4,
1700 calc.cck_rpl_ofst, phy_idx);
1701 }
1702
rtw8922d_calc_rx_gain_normal_ofdm(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx,struct rtw89_phy_calc_efuse_gain * calc)1703 static void rtw8922d_calc_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
1704 const struct rtw89_chan *chan,
1705 enum rtw89_rf_path path,
1706 enum rtw89_phy_idx phy_idx,
1707 struct rtw89_phy_calc_efuse_gain *calc)
1708 {
1709 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1710 s8 rx_gain_offset;
1711
1712 rx_gain_offset = rtw8922d_get_rx_gain_by_chan(rtwdev, chan, path, false);
1713 calc->rssi_ofst = (rx_gain_offset + gain->ref_gain_base[phy_idx]) & 0xff;
1714 }
1715
rtw8922d_set_rx_gain_normal_ofdm(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1716 static void rtw8922d_set_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
1717 const struct rtw89_chan *chan,
1718 enum rtw89_rf_path path,
1719 enum rtw89_phy_idx phy_idx)
1720 {
1721 static const u32 rssi_ofst_addr[2] = {R_OFDM_OFST_P0_BE4, R_OFDM_OFST_P1_BE4};
1722 static const u32 rssi_ofst_addr_m[2] = {B_OFDM_OFST_P0_BE4, B_OFDM_OFST_P1_BE4};
1723 static const u32 rpl_bias_comp[2] = {R_OFDM_RPL_BIAS_P0_BE4, R_OFDM_RPL_BIAS_P1_BE4};
1724 static const u32 rpl_bias_comp_m[2] = {B_OFDM_RPL_BIAS_P0_BE4, B_OFDM_RPL_BIAS_P1_BE4};
1725 struct rtw89_phy_calc_efuse_gain calc = {};
1726
1727 rtw8922d_calc_rx_gain_normal_ofdm(rtwdev, chan, path, phy_idx, &calc);
1728
1729 rtw89_phy_write32_idx(rtwdev, rssi_ofst_addr[path], rssi_ofst_addr_m[path],
1730 calc.rssi_ofst, phy_idx);
1731 rtw89_phy_write32_idx(rtwdev, rpl_bias_comp[path], rpl_bias_comp_m[path], 0, phy_idx);
1732 }
1733
rtw8922d_set_rx_gain_normal(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1734 static void rtw8922d_set_rx_gain_normal(struct rtw89_dev *rtwdev,
1735 const struct rtw89_chan *chan,
1736 enum rtw89_rf_path path,
1737 enum rtw89_phy_idx phy_idx)
1738 {
1739 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1740
1741 if (!gain->offset_valid)
1742 return;
1743
1744 if (chan->band_type == RTW89_BAND_2G)
1745 rtw8922d_set_rx_gain_normal_cck(rtwdev, chan, path, phy_idx);
1746
1747 rtw8922d_set_rx_gain_normal_ofdm(rtwdev, chan, path, phy_idx);
1748 }
1749
rtw8922d_calc_rx_gain_normal(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx,struct rtw89_phy_calc_efuse_gain * calc)1750 static void rtw8922d_calc_rx_gain_normal(struct rtw89_dev *rtwdev,
1751 const struct rtw89_chan *chan,
1752 enum rtw89_rf_path path,
1753 enum rtw89_phy_idx phy_idx,
1754 struct rtw89_phy_calc_efuse_gain *calc)
1755 {
1756 rtw8922d_calc_rx_gain_normal_ofdm(rtwdev, chan, path, phy_idx, calc);
1757
1758 if (chan->band_type != RTW89_BAND_2G)
1759 return;
1760
1761 rtw8922d_calc_rx_gain_normal_cck(rtwdev, chan, path, phy_idx, calc);
1762 }
1763
rtw8922d_path_diff_update(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)1764 static void rtw8922d_path_diff_update(struct rtw89_dev *rtwdev,
1765 struct rtw89_bb_ctx *bb)
1766 {
1767 #define BF_SMOOTH_TH 80
1768 static const u32 path_diff_cnt_mask[] = {0xff0000, 0xff};
1769 static const u32 ndp_cnt_mask[] = {0xff000000, 0xff00};
1770 static const u16 he_eht_sel_tone[4] = {27, 54, 56, 56};
1771 static const u16 vht_sel_tone[4] = {11, 25, 25, 25};
1772 struct rtw89_hal *hal = &rtwdev->hal;
1773 struct rtw89_entity_conf conf;
1774 const struct rtw89_chan *chan;
1775 u8 phy_idx = bb->phy_idx;
1776 u32 path_diff_cnt;
1777 u16 sel_tone = 0;
1778 bool bf_smo_lmt;
1779 u32 ndp_cnt;
1780
1781 if (hal->cid != RTL8922D_CID7090)
1782 return;
1783
1784 ndp_cnt = rtw89_phy_read32_mask(rtwdev, R_CL_MODE_CNT_BE4, ndp_cnt_mask[phy_idx]);
1785 path_diff_cnt = rtw89_phy_read32_mask(rtwdev, R_CL_MODE_CNT_BE4,
1786 path_diff_cnt_mask[phy_idx]);
1787
1788 bb->path_diff.raw = clamp(phy_div(path_diff_cnt * 100, ndp_cnt), 0, 255);
1789
1790 if (ndp_cnt == 0)
1791 ewma_path_diff_init(&bb->path_diff.avg);
1792 else
1793 ewma_path_diff_add(&bb->path_diff.avg, bb->path_diff.raw);
1794
1795 rtw89_phy_write32_mask(rtwdev, R_CL_MODE_TRIG_BE4, B_CL_MODE_TRIG_BE4, 1);
1796 rtw89_phy_write32_mask(rtwdev, R_CL_MODE_TRIG_BE4, B_CL_MODE_TRIG_BE4, 0);
1797
1798 bf_smo_lmt = ewma_path_diff_read(&bb->path_diff.avg) < BF_SMOOTH_TH;
1799 bb->path_diff.bf_smo_en = !bf_smo_lmt;
1800
1801 rtw89_phy_write32_mask(rtwdev, R_BF_SMO_PDP_LMT_EHT_BE4,
1802 B_BF_SMO_PDP_LMT_EHT_BE4, bf_smo_lmt);
1803 rtw89_phy_write32_mask(rtwdev, R_BF_SMO_PDP_LMT_HE_BE4,
1804 B_BF_SMO_PDP_LMT_HE_BE4, bf_smo_lmt);
1805 rtw89_phy_write32_mask(rtwdev, R_BF_SMO_PDP_LMT_VHT_BE4,
1806 B_BF_SMO_PDP_LMT_VHT_BE4, bf_smo_lmt);
1807
1808 rtw89_phy_write32_mask(rtwdev, R_OS_TRIG_BY_SW_BE4,
1809 B_OS_TRIG_BY_SW_BE4, !bf_smo_lmt);
1810 rtw89_phy_write32_mask(rtwdev, R_OS_TRIG_SOURCE_BE4,
1811 B_OS_TRIG_SOURCE_BE4, !bf_smo_lmt);
1812
1813 rtw89_entity_get_conf(rtwdev, &conf);
1814 chan = conf.chans[phy_idx];
1815 if (chan->band_width <= RTW89_CHANNEL_WIDTH_160) {
1816 if (bb->path_diff.link_mode >= 2)
1817 sel_tone = he_eht_sel_tone[chan->band_width];
1818 else if (bb->path_diff.link_mode == 1)
1819 sel_tone = vht_sel_tone[chan->band_width];
1820 rtw89_phy_write32_mask(rtwdev, R_SELECTED_TONE_IDX_BE4,
1821 B_SELECTED_TONE_IDX_BE4, sel_tone);
1822 }
1823
1824 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
1825 "[PATH_DIFF] raw=%d%%, ma=%ld%%, bf_smo_en=%d, tone=%d\n",
1826 bb->path_diff.raw,
1827 ewma_path_diff_read(&bb->path_diff.avg),
1828 bb->path_diff.bf_smo_en, sel_tone);
1829 }
1830
rtw8922d_set_cck_parameters(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1831 static void rtw8922d_set_cck_parameters(struct rtw89_dev *rtwdev,
1832 const struct rtw89_chan *chan,
1833 enum rtw89_phy_idx phy_idx)
1834 {
1835 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
1836 u8 central_ch = chan->channel;
1837
1838 if (central_ch == 14) {
1839 rtw89_phy_write32_idx(rtwdev, R_PCOEFF0_BE4, B_PCOEFF01_BE4, 0x3b13ff, phy_idx);
1840 rtw89_phy_write32_idx(rtwdev, R_PCOEFF2_BE4, B_PCOEFF23_BE4, 0x1c42de, phy_idx);
1841 rtw89_phy_write32_idx(rtwdev, R_PCOEFF4_BE4, B_PCOEFF45_BE4, 0xfdb0ad, phy_idx);
1842 rtw89_phy_write32_idx(rtwdev, R_PCOEFF6_BE4, B_PCOEFF67_BE4, 0xf60f6e, phy_idx);
1843 rtw89_phy_write32_idx(rtwdev, R_PCOEFF8_BE4, B_PCOEFF89_BE4, 0xfd8f92, phy_idx);
1844 rtw89_phy_write32_idx(rtwdev, R_PCOEFF10_BE4, B_PCOEFF10_BE4, 0x2d011, phy_idx);
1845 rtw89_phy_write32_idx(rtwdev, R_PCOEFF12_BE4, B_PCOEFF12_BE4, 0x1c02c, phy_idx);
1846 rtw89_phy_write32_idx(rtwdev, R_PCOEFF14_BE4, B_PCOEFF14_BE4, 0xfff00a, phy_idx);
1847
1848 return;
1849 }
1850
1851 if (regd == RTW89_FCC) {
1852 rtw89_phy_write32_idx(rtwdev, R_PCOEFF0_BE4, B_PCOEFF01_BE4, 0x39A3BC, phy_idx);
1853 rtw89_phy_write32_idx(rtwdev, R_PCOEFF2_BE4, B_PCOEFF23_BE4, 0x2AA339, phy_idx);
1854 rtw89_phy_write32_idx(rtwdev, R_PCOEFF4_BE4, B_PCOEFF45_BE4, 0x15B202, phy_idx);
1855 rtw89_phy_write32_idx(rtwdev, R_PCOEFF6_BE4, B_PCOEFF67_BE4, 0x0550C7, phy_idx);
1856 rtw89_phy_write32_idx(rtwdev, R_PCOEFF8_BE4, B_PCOEFF89_BE4, 0xfe0009, phy_idx);
1857 rtw89_phy_write32_idx(rtwdev, R_PCOEFF10_BE4, B_PCOEFF10_BE4, 0xfd7fd3, phy_idx);
1858 rtw89_phy_write32_idx(rtwdev, R_PCOEFF12_BE4, B_PCOEFF12_BE4, 0xfeffe2, phy_idx);
1859 rtw89_phy_write32_idx(rtwdev, R_PCOEFF14_BE4, B_PCOEFF14_BE4, 0xffeff8, phy_idx);
1860 } else {
1861 rtw89_phy_write32_idx(rtwdev, R_PCOEFF0_BE4, B_PCOEFF01_BE4, 0x3d23ff, phy_idx);
1862 rtw89_phy_write32_idx(rtwdev, R_PCOEFF2_BE4, B_PCOEFF23_BE4, 0x29b354, phy_idx);
1863 rtw89_phy_write32_idx(rtwdev, R_PCOEFF4_BE4, B_PCOEFF45_BE4, 0xfc1c8, phy_idx);
1864 rtw89_phy_write32_idx(rtwdev, R_PCOEFF6_BE4, B_PCOEFF67_BE4, 0xfdb053, phy_idx);
1865 rtw89_phy_write32_idx(rtwdev, R_PCOEFF8_BE4, B_PCOEFF89_BE4, 0xf86f9a, phy_idx);
1866 rtw89_phy_write32_idx(rtwdev, R_PCOEFF10_BE4, B_PCOEFF10_BE4, 0xfaef92, phy_idx);
1867 rtw89_phy_write32_idx(rtwdev, R_PCOEFF12_BE4, B_PCOEFF12_BE4, 0xfe5fcc, phy_idx);
1868 rtw89_phy_write32_idx(rtwdev, R_PCOEFF14_BE4, B_PCOEFF14_BE4, 0xffdff5, phy_idx);
1869 }
1870 }
1871
rtw8922d_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1872 static void rtw8922d_ctrl_ch(struct rtw89_dev *rtwdev,
1873 const struct rtw89_chan *chan,
1874 enum rtw89_phy_idx phy_idx)
1875 {
1876 u16 central_freq = chan->freq;
1877 u8 band = chan->band_type;
1878 u8 chan_idx;
1879
1880 if (!central_freq) {
1881 rtw89_warn(rtwdev, "Invalid central_freq\n");
1882 return;
1883 }
1884
1885 rtw8922d_ctrl_ch_core(rtwdev, chan, phy_idx);
1886
1887 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1888 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL_BE4, B_CH_IDX_SEG0, chan_idx, phy_idx);
1889
1890 rtw8922d_set_gain(rtwdev, chan, RF_PATH_A, phy_idx);
1891 rtw8922d_set_gain(rtwdev, chan, RF_PATH_B, phy_idx);
1892
1893 rtw8922d_set_rx_gain_normal(rtwdev, chan, RF_PATH_A, phy_idx);
1894 rtw8922d_set_rx_gain_normal(rtwdev, chan, RF_PATH_B, phy_idx);
1895
1896 if (band == RTW89_BAND_2G)
1897 rtw8922d_set_cck_parameters(rtwdev, chan, phy_idx);
1898 }
1899
rtw8922d_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_sb,u8 bw,enum rtw89_phy_idx phy_idx)1900 static void rtw8922d_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_sb, u8 bw,
1901 enum rtw89_phy_idx phy_idx)
1902 {
1903 switch (bw) {
1904 default:
1905 case RTW89_CHANNEL_WIDTH_20:
1906 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x0, phy_idx);
1907 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, 0x0, phy_idx);
1908 rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x2, phy_idx);
1909 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x2, phy_idx);
1910 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x2, phy_idx);
1911 break;
1912 case RTW89_CHANNEL_WIDTH_40:
1913 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x1, phy_idx);
1914 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, pri_sb, phy_idx);
1915 rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x3, phy_idx);
1916 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x3, phy_idx);
1917 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x3, phy_idx);
1918 break;
1919 case RTW89_CHANNEL_WIDTH_80:
1920 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x2, phy_idx);
1921 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, pri_sb, phy_idx);
1922 rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x4, phy_idx);
1923 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x4, phy_idx);
1924 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x4, phy_idx);
1925 break;
1926 case RTW89_CHANNEL_WIDTH_160:
1927 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x3, phy_idx);
1928 rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, pri_sb, phy_idx);
1929 rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x5, phy_idx);
1930 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x5, phy_idx);
1931 rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x5, phy_idx);
1932 break;
1933 }
1934 }
1935
1936 static const u16 spur_nbi_a[] = {6400};
1937 static const u16 spur_csi[] = {6400};
1938
rtw8922d_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,bool nbi_or_csi,enum rtw89_rf_path path)1939 static u32 rtw8922d_spur_freq(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1940 bool nbi_or_csi, enum rtw89_rf_path path)
1941 {
1942 static const u16 cbw[RTW89_CHANNEL_WIDTH_ORDINARY_NUM] = {
1943 20, 40, 80, 160, 320,
1944 };
1945 u16 freq_lower, freq_upper, freq;
1946 const u16 *spur_freq;
1947 int spur_freq_nr, i;
1948
1949 if (rtwdev->hal.aid != RTL8922D_AID7060)
1950 return 0;
1951
1952 if (nbi_or_csi && path == RF_PATH_A) {
1953 spur_freq = spur_nbi_a;
1954 spur_freq_nr = ARRAY_SIZE(spur_nbi_a);
1955 } else if (!nbi_or_csi) {
1956 spur_freq = spur_csi;
1957 spur_freq_nr = ARRAY_SIZE(spur_csi);
1958 } else {
1959 return 0;
1960 }
1961
1962 if (chan->band_width >= RTW89_CHANNEL_WIDTH_ORDINARY_NUM)
1963 return 0;
1964
1965 freq_lower = chan->freq - cbw[chan->band_width] / 2;
1966 freq_upper = chan->freq + cbw[chan->band_width] / 2;
1967
1968 for (i = 0; i < spur_freq_nr; i++) {
1969 freq = spur_freq[i];
1970
1971 if (freq >= freq_lower && freq <= freq_upper)
1972 return freq;
1973 }
1974
1975 return 0;
1976 }
1977
1978 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1979 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1980 #define MAX_TONE_NUM 2048
1981
rtw8922d_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1982 static void rtw8922d_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1983 const struct rtw89_chan *chan,
1984 enum rtw89_phy_idx phy_idx)
1985 {
1986 s32 freq_diff, csi_idx, csi_tone_idx;
1987 u32 spur_freq;
1988
1989 spur_freq = rtw8922d_spur_freq(rtwdev, chan, false, RF_PATH_AB);
1990 if (spur_freq == 0) {
1991 rtw89_phy_write32_idx(rtwdev, R_CSI_WGT_BE4, B_CSI_WGT_EN_BE4,
1992 0, phy_idx);
1993 return;
1994 }
1995
1996 freq_diff = (spur_freq - chan->freq) * 1000000;
1997 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1998 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1999
2000 rtw89_phy_write32_idx(rtwdev, R_CSI_WGT_BE4, B_CSI_WGT_IDX_BE4,
2001 csi_tone_idx, phy_idx);
2002 rtw89_phy_write32_idx(rtwdev, R_CSI_WGT_BE4, B_CSI_WGT_EN_BE4, 1, phy_idx);
2003 }
2004
2005 static const struct rtw89_nbi_reg_def rtw8922d_nbi_reg_def[] = {
2006 [RF_PATH_A] = {
2007 .notch1_idx = {0x241A0, 0xFF},
2008 .notch1_frac_idx = {0x241A0, 0xC00},
2009 .notch1_en = {0x241A0, 0x1000},
2010 .notch2_idx = {0x241AC, 0xFF},
2011 .notch2_frac_idx = {0x241AC, 0xC00},
2012 .notch2_en = {0x241AC, 0x1000},
2013 },
2014 [RF_PATH_B] = {
2015 .notch1_idx = {0x245A0, 0xFF},
2016 .notch1_frac_idx = {0x245A0, 0xC00},
2017 .notch1_en = {0x245A0, 0x1000},
2018 .notch2_idx = {0x245AC, 0xFF},
2019 .notch2_frac_idx = {0x245AC, 0xC00},
2020 .notch2_en = {0x245AC, 0x1000},
2021 },
2022 };
2023
rtw8922d_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)2024 static void rtw8922d_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
2025 const struct rtw89_chan *chan,
2026 enum rtw89_rf_path path,
2027 enum rtw89_phy_idx phy_idx)
2028 {
2029 const struct rtw89_nbi_reg_def *nbi = &rtw8922d_nbi_reg_def[path];
2030 s32 nbi_frac_idx, nbi_frac_tone_idx;
2031 s32 nbi_idx, nbi_tone_idx;
2032 bool notch2_chk = false;
2033 u32 spur_freq, fc;
2034 s32 freq_diff;
2035
2036 spur_freq = rtw8922d_spur_freq(rtwdev, chan, true, path);
2037 if (spur_freq == 0) {
2038 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
2039 nbi->notch1_en.mask, 0, phy_idx);
2040 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
2041 nbi->notch2_en.mask, 0, phy_idx);
2042 return;
2043 }
2044
2045 fc = chan->freq;
2046 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
2047 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
2048 if ((fc > spur_freq &&
2049 chan->channel < chan->primary_channel) ||
2050 (fc < spur_freq &&
2051 chan->channel > chan->primary_channel))
2052 notch2_chk = true;
2053 }
2054
2055 freq_diff = (spur_freq - fc) * 1000000;
2056 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
2057 &nbi_frac_idx);
2058
2059 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
2060 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
2061 } else {
2062 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
2063 128 : 256;
2064
2065 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
2066 }
2067 nbi_frac_tone_idx =
2068 s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
2069
2070 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
2071 rtw89_phy_write32_idx(rtwdev, nbi->notch2_idx.addr,
2072 nbi->notch2_idx.mask, nbi_tone_idx, phy_idx);
2073 rtw89_phy_write32_idx(rtwdev, nbi->notch2_frac_idx.addr,
2074 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx,
2075 phy_idx);
2076 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
2077 nbi->notch2_en.mask, 0, phy_idx);
2078 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
2079 nbi->notch2_en.mask, 1, phy_idx);
2080 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
2081 nbi->notch1_en.mask, 0, phy_idx);
2082 } else {
2083 rtw89_phy_write32_idx(rtwdev, nbi->notch1_idx.addr,
2084 nbi->notch1_idx.mask, nbi_tone_idx, phy_idx);
2085 rtw89_phy_write32_idx(rtwdev, nbi->notch1_frac_idx.addr,
2086 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx,
2087 phy_idx);
2088 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
2089 nbi->notch1_en.mask, 0, phy_idx);
2090 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
2091 nbi->notch1_en.mask, 1, phy_idx);
2092 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
2093 nbi->notch2_en.mask, 0, phy_idx);
2094 }
2095 }
2096
rtw8922d_spur_elimination(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2097 static void rtw8922d_spur_elimination(struct rtw89_dev *rtwdev,
2098 const struct rtw89_chan *chan,
2099 enum rtw89_phy_idx phy_idx)
2100 {
2101 rtw8922d_set_csi_tone_idx(rtwdev, chan, phy_idx);
2102 rtw8922d_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A, phy_idx);
2103 rtw8922d_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B, phy_idx);
2104 }
2105
2106 static const u32 bbrst_mask[2] = {B_BE_FEN_BBPLAT_RSTB, B_BE_FEN_BB1PLAT_RSTB};
2107 static const u32 glbrst_mask[2] = {B_BE_FEN_BB_IP_RSTN, B_BE_FEN_BB1_IP_RSTN};
2108 static const u32 chip_top_bitmask[2] = {0xffff, 0xffff0000};
2109
rtw8922d_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2110 static void rtw8922d_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2111 {
2112 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0);
2113 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0);
2114 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, chip_top_bitmask[phy_idx], 0x74F9);
2115 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1);
2116 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC_BE4, B_RSTB_ASYNC_BE4, 0, phy_idx);
2117 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x1);
2118 }
2119
rtw8922d_bb_postinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2120 static void rtw8922d_bb_postinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2121 {
2122 rtw89_phy_write32_idx_clr(rtwdev, R_SHAPER_COEFF_BE4, B_SHAPER_COEFF_BE4, phy_idx);
2123 rtw89_phy_write32_idx_set(rtwdev, R_SHAPER_COEFF_BE4, B_SHAPER_COEFF_BE4, phy_idx);
2124 }
2125
rtw8922d_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,bool en,enum rtw89_phy_idx phy_idx)2126 static void rtw8922d_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
2127 bool en, enum rtw89_phy_idx phy_idx)
2128 {
2129 if (en)
2130 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC_BE4, B_RSTB_ASYNC_BE4, 1, phy_idx);
2131 else
2132 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC_BE4, B_RSTB_ASYNC_BE4, 0, phy_idx);
2133 }
2134
rtw8922d_ctrl_tx_path_tmac(struct rtw89_dev * rtwdev,enum rtw89_rf_path tx_path,enum rtw89_phy_idx phy_idx)2135 static int rtw8922d_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev,
2136 enum rtw89_rf_path tx_path,
2137 enum rtw89_phy_idx phy_idx)
2138 {
2139 struct rtw89_reg2_def path_com_cr[] = {
2140 {0x11A00, 0x21C86900},
2141 {0x11A04, 0x00E4E433},
2142 {0x11A08, 0x39390CC9},
2143 {0x11A10, 0x10CC0000},
2144 {0x11A14, 0x00240393},
2145 {0x11A18, 0x201C8600},
2146 {0x11B38, 0x39393FDB},
2147 {0x11B3C, 0x00E4E4FF},
2148 };
2149 int ret = 0;
2150 u32 reg;
2151 int i;
2152
2153 rtw89_phy_write32_idx(rtwdev, R_TXINFO_PATH_BE4, B_TXINFO_PATH_EN_BE4, 0x0, phy_idx);
2154 rtw89_phy_write32_idx(rtwdev, R_TXINFO_PATH_BE4, B_TXINFO_PATH_MA_BE4, 0x0, phy_idx);
2155 rtw89_phy_write32_idx(rtwdev, R_TXINFO_PATH_BE4, B_TXINFO_PATH_MB_BE4, 0x0, phy_idx);
2156
2157 if (phy_idx == RTW89_PHY_1 && !rtwdev->dbcc_en)
2158 return 0;
2159
2160 if (tx_path == RF_PATH_A) {
2161 path_com_cr[1].data = 0x40031;
2162 path_com_cr[2].data = 0x1000C48;
2163 path_com_cr[5].data = 0x200;
2164 path_com_cr[6].data = 0x1000C48;
2165 path_com_cr[7].data = 0x40031;
2166 } else if (tx_path == RF_PATH_B) {
2167 path_com_cr[1].data = 0x40032;
2168 path_com_cr[2].data = 0x1000C88;
2169 path_com_cr[5].data = 0x400;
2170 path_com_cr[6].data = 0x1000C88;
2171 path_com_cr[7].data = 0x40032;
2172 } else if (tx_path == RF_PATH_AB) {
2173 path_com_cr[1].data = 0x00E4E433;
2174 path_com_cr[2].data = 0x39390CC9;
2175 path_com_cr[5].data = 0x201C8600;
2176 path_com_cr[6].data = 0x1010CC9;
2177 path_com_cr[7].data = 0x40433;
2178 } else {
2179 ret = -EINVAL;
2180 }
2181
2182 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) {
2183 reg = rtw89_mac_reg_by_idx(rtwdev, path_com_cr[i].addr, phy_idx);
2184 rtw89_write32(rtwdev, reg, path_com_cr[i].data);
2185 }
2186
2187 return ret;
2188 }
2189
rtw8922d_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2190 static void rtw8922d_bb_reset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2191 {
2192 }
2193
rtw8922d_tssi_reset(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)2194 static void rtw8922d_tssi_reset(struct rtw89_dev *rtwdev,
2195 enum rtw89_rf_path path,
2196 enum rtw89_phy_idx phy_idx)
2197 {
2198 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
2199 if (phy_idx == RTW89_PHY_0) {
2200 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4,
2201 B_TXPWR_RSTB0_BE4, 0x0);
2202 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4,
2203 B_TXPWR_RSTB0_BE4, 0x1);
2204 } else {
2205 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4,
2206 B_TXPWR_RSTB1_BE4, 0x0);
2207 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4,
2208 B_TXPWR_RSTB1_BE4, 0x1);
2209 }
2210 } else {
2211 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4, B_TXPWR_RSTB0_BE4, 0x0);
2212 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4, B_TXPWR_RSTB0_BE4, 0x1);
2213 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4, B_TXPWR_RSTB1_BE4, 0x0);
2214 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4, B_TXPWR_RSTB1_BE4, 0x1);
2215 }
2216 }
2217
rtw8922d_ctrl_rx_path_tmac(struct rtw89_dev * rtwdev,enum rtw89_rf_path rx_path,enum rtw89_phy_idx phy_idx)2218 static int rtw8922d_ctrl_rx_path_tmac(struct rtw89_dev *rtwdev,
2219 enum rtw89_rf_path rx_path,
2220 enum rtw89_phy_idx phy_idx)
2221 {
2222 enum rtw89_rf_path_bit path;
2223
2224 if (rx_path == RF_PATH_A)
2225 path = RF_A;
2226 else if (rx_path == RF_PATH_B)
2227 path = RF_B;
2228 else
2229 path = RF_AB;
2230
2231 rtw89_phy_write32_idx(rtwdev, R_ANT_RX_BE4, B_ANT_RX_BE4, path, phy_idx);
2232 rtw89_phy_write32_idx(rtwdev, R_ANT_RX_1RCCA_BE4, B_ANT_RX_1RCCA_BE4,
2233 path, phy_idx);
2234
2235 if (rx_path == RF_PATH_AB) {
2236 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC0_BE4, B_RXCH_MCS4_BE4, 8, phy_idx);
2237 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS5_BE4, 4, phy_idx);
2238 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS6_BE4, 3, phy_idx);
2239 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS7_BE4, 7, phy_idx);
2240 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS8_BE4, 2, phy_idx);
2241 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN04_BE4, 4, phy_idx);
2242 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN07_BE4, 2, phy_idx);
2243 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN01_BE4, B_RX_AWGN09_BE4, 0, phy_idx);
2244 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN02_BE4, B_RX_AWGN11_BE4, 1, phy_idx);
2245 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC03_BE4, B_RX_LDPC02_BE4, 0x6, phy_idx);
2246 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC03_BE4, B_RX_LDPC03_BE4, 0xf, phy_idx);
2247 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC04_BE4, 0x10, phy_idx);
2248 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC05_BE4, 0xa, phy_idx);
2249 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC06_BE4, 0x8, phy_idx);
2250 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC07_BE4, 0x14, phy_idx);
2251 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC01_BE4, B_RX_LDPC09_BE4, 0x14, phy_idx);
2252 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC10_BE4, 0xc, phy_idx);
2253 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC11_BE4, 0xb, phy_idx);
2254 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC12_BE4, 0x14, phy_idx);
2255 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC03_BE4, B_RX_LDPC13_BE4, 0x2d, phy_idx);
2256 } else {
2257 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC0_BE4, B_RXCH_MCS4_BE4, 13, phy_idx);
2258 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS5_BE4, 15, phy_idx);
2259 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS6_BE4, 6, phy_idx);
2260 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS7_BE4, 15, phy_idx);
2261 rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS8_BE4, 4, phy_idx);
2262 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN04_BE4, 9, phy_idx);
2263 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN07_BE4, 3, phy_idx);
2264 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN01_BE4, B_RX_AWGN09_BE4, 1, phy_idx);
2265 rtw89_phy_write32_idx(rtwdev, R_RX_AWGN02_BE4, B_RX_AWGN11_BE4, 0, phy_idx);
2266 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC03_BE4, B_RX_LDPC02_BE4, 0x3, phy_idx);
2267 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC03_BE4, B_RX_LDPC03_BE4, 0x9, phy_idx);
2268 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC04_BE4, 9, phy_idx);
2269 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC05_BE4, 8, phy_idx);
2270 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC06_BE4, 6, phy_idx);
2271 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC07_BE4, 16, phy_idx);
2272 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC01_BE4, B_RX_LDPC09_BE4, 9, phy_idx);
2273 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC10_BE4, 9, phy_idx);
2274 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC11_BE4, 7, phy_idx);
2275 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC12_BE4, 0x17, phy_idx);
2276 rtw89_phy_write32_idx(rtwdev, R_RX_LDPC03_BE4, B_RX_LDPC13_BE4, 0x1a, phy_idx);
2277 }
2278
2279 return 0;
2280 }
2281
rtw8922d_set_digital_pwr_comp(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 nss,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)2282 static void rtw8922d_set_digital_pwr_comp(struct rtw89_dev *rtwdev,
2283 const struct rtw89_chan *chan, u8 nss,
2284 enum rtw89_rf_path path,
2285 enum rtw89_phy_idx phy_idx)
2286 {
2287 #define DIGITAL_PWR_COMP_BASE_NUM 7
2288 #define DIGITAL_PWR_COMP_VALS_NUM 15
2289 static const u32 pw_comp_cr[2] = {R_RX_PATH0_TBL0_BE4, R_RX_PATH1_TBL0_BE4};
2290 const struct {
2291 struct {
2292 __le32 base[DIGITAL_PWR_COMP_BASE_NUM];
2293 __le32 vals[DIGITAL_PWR_COMP_VALS_NUM];
2294 } sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D];
2295 } *pwr_comp_v0;
2296 const struct {
2297 __le32 base[DIGITAL_PWR_COMP_BASE_NUM];
2298 struct {
2299 __le32 vals[DIGITAL_PWR_COMP_VALS_NUM];
2300 } sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D];
2301 } *pwr_comp_v1;
2302 const struct {
2303 __le32 base[2][DIGITAL_PWR_COMP_BASE_NUM];
2304 struct {
2305 __le32 vals[DIGITAL_PWR_COMP_VALS_NUM];
2306 } sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D];
2307 } *pwr_comp;
2308 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
2309 const struct rtw89_fw_element_hdr *txcomp_elm = elm_info->tx_comp;
2310 const __le32 (*comp_base)[DIGITAL_PWR_COMP_BASE_NUM];
2311 const __le32 (*comp_vals)[DIGITAL_PWR_COMP_VALS_NUM];
2312 u32 addr, val;
2313 u32 i;
2314
2315 if (sizeof(*pwr_comp) == le32_to_cpu(txcomp_elm->size)) {
2316 pwr_comp = (const void *)txcomp_elm->u.common.contents;
2317 comp_base = &pwr_comp->base[nss];
2318 comp_vals = &pwr_comp->sets[nss][chan->tx_comp_band][path].vals;
2319 } else if (sizeof(*pwr_comp_v1) == le32_to_cpu(txcomp_elm->size)) {
2320 pwr_comp_v1 = (const void *)txcomp_elm->u.common.contents;
2321 comp_base = &pwr_comp_v1->base;
2322 comp_vals = &pwr_comp_v1->sets[nss][chan->tx_comp_band][path].vals;
2323 } else if (sizeof(*pwr_comp_v0) == le32_to_cpu(txcomp_elm->size)) {
2324 pwr_comp_v0 = (const void *)txcomp_elm->u.common.contents;
2325 comp_base = &pwr_comp_v0->sets[nss][chan->tx_comp_band][path].base;
2326 comp_vals = &pwr_comp_v0->sets[nss][chan->tx_comp_band][path].vals;
2327 } else {
2328 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
2329 "incorrect power comp size %d\n",
2330 le32_to_cpu(txcomp_elm->size));
2331 return;
2332 }
2333
2334 addr = pw_comp_cr[path];
2335
2336 for (i = 0; i < ARRAY_SIZE(*comp_base); i++, addr += 4) {
2337 val = le32_to_cpu((*comp_base)[i]);
2338 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
2339 }
2340
2341 for (i = 0; i < ARRAY_SIZE(*comp_vals); i++, addr += 4) {
2342 val = le32_to_cpu((*comp_vals)[i]);
2343 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
2344 }
2345 }
2346
rtw8922d_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2347 static void rtw8922d_digital_pwr_comp(struct rtw89_dev *rtwdev,
2348 enum rtw89_phy_idx phy_idx)
2349 {
2350 const struct rtw89_chan *chan0, *chan1;
2351 struct rtw89_entity_conf conf;
2352
2353 rtw89_entity_get_conf(rtwdev, &conf);
2354 chan0 = conf.chans[0];
2355 chan1 = conf.chans[1];
2356
2357 if (conf.en_emlsr) {
2358 rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_A, RTW89_PHY_0);
2359 rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_B, RTW89_PHY_0);
2360 rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 1, RF_PATH_A, RTW89_PHY_1);
2361 rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 1, RF_PATH_B, RTW89_PHY_1);
2362 } else if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
2363 rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 0, RF_PATH_A, RTW89_PHY_0);
2364 rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 0, RF_PATH_B, RTW89_PHY_1);
2365 } else {
2366 rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_A, phy_idx);
2367 rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_B, phy_idx);
2368 }
2369 }
2370
rtw8922d_ctrl_mlo_mode_core(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode)2371 static void rtw8922d_ctrl_mlo_mode_core(struct rtw89_dev *rtwdev,
2372 enum rtw89_mlo_dbcc_mode mode)
2373 {
2374 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_CLR_FORCE_BE4, 0x3);
2375
2376 if (mode == MLO_2_PLUS_0_1RF) {
2377 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
2378 udelay(1);
2379 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
2380 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x3BAB);
2381 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEBAD);
2382 udelay(1);
2383
2384 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
2385 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEAAD);
2386 } else if (mode == MLO_0_PLUS_2_1RF) {
2387 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
2388 udelay(1);
2389 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
2390 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x3BAB);
2391 udelay(1);
2392 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEFFF);
2393
2394 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
2395 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEEFF);
2396 } else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
2397 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
2398 udelay(1);
2399 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
2400 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x3BAB);
2401 udelay(1);
2402 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
2403 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x3AAB);
2404 } else {
2405 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x6180);
2406 udelay(1);
2407 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
2408 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x180);
2409 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
2410 rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x0);
2411 }
2412 }
2413
rtw8922d_ctrl_mlo(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode,bool pwr_comp)2414 static int rtw8922d_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode mode,
2415 bool pwr_comp)
2416 {
2417 u32 reg0, reg1;
2418 u8 cck_phy_idx;
2419
2420 rtw8922d_ctrl_mlo_mode_core(rtwdev, mode);
2421
2422 if (pwr_comp)
2423 rtw8922d_digital_pwr_comp(rtwdev, RTW89_PHY_0);
2424
2425 reg0 = R_BBWRAP_ELMSR_BE4;
2426 reg1 = rtw89_mac_reg_by_idx(rtwdev, reg0, 1);
2427
2428 if (mode == MLO_2_PLUS_0_1RF) {
2429 rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2430 B_SYS_DBCC_24G_BAND_SEL_BE4, RTW89_PHY_0);
2431 rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
2432 rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
2433 } else if (mode == MLO_0_PLUS_2_1RF) {
2434 rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2435 B_SYS_DBCC_24G_BAND_SEL_BE4, RTW89_PHY_0);
2436 rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
2437 rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
2438 } else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
2439 struct rtw89_entity_conf conf;
2440
2441 rtw89_entity_get_conf(rtwdev, &conf);
2442 cck_phy_idx = conf.chans[1]->band_type == RTW89_BAND_2G ?
2443 RTW89_PHY_1 : RTW89_PHY_0;
2444
2445 rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2446 B_SYS_DBCC_24G_BAND_SEL_BE4, cck_phy_idx);
2447 rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0x3);
2448 rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0x3);
2449 } else {
2450 rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2451 B_SYS_DBCC_24G_BAND_SEL_BE4, RTW89_PHY_0);
2452 rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
2453 rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
2454 }
2455
2456 udelay(1);
2457
2458 return 0;
2459 }
2460
rtw8922d_bb_sethw(struct rtw89_dev * rtwdev)2461 static void rtw8922d_bb_sethw(struct rtw89_dev *rtwdev)
2462 {
2463 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
2464 struct rtw89_hal *hal = &rtwdev->hal;
2465 enum rtw89_phy_idx phy_idx;
2466 u32 reg;
2467
2468 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, RTW89_PHY_0);
2469 rtw89_write32_clr(rtwdev, reg, B_BE_PWR_CTRL_SEL);
2470 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, RTW89_PHY_1);
2471 rtw89_write32_clr(rtwdev, reg, B_BE_PWR_CTRL_SEL);
2472
2473 if (hal->cid == RTL8922D_CID7090) {
2474 reg = rtw89_mac_reg_by_idx(rtwdev, R_PWR_BOOST_BE4, RTW89_PHY_0);
2475 rtw89_write32_set(rtwdev, reg, B_PWR_BOOST_BE4);
2476 reg = rtw89_mac_reg_by_idx(rtwdev, R_PWR_BOOST_BE4, RTW89_PHY_1);
2477 rtw89_write32_set(rtwdev, reg, B_PWR_BOOST_BE4);
2478 }
2479
2480 rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_PSDU_BE4, 0);
2481 rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_NSYM_BE4, 1);
2482 rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_LSIG_BE4, 1);
2483 rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_TXINFO_BE4, 1);
2484 rtw89_phy_write32_mask(rtwdev, R_TXERRCT_EN_BE4, B_TXERRCT_EN_BE4, 0);
2485 rtw89_phy_write32_mask(rtwdev, R_TXERRCT1_EN_BE4, B_TXERRCT1_EN_BE4, 0);
2486 rtw89_phy_write32_idx(rtwdev, R_IMR_TX_ERROR_BE4, B_IMR_TX_ERROR_BE4, 1, RTW89_PHY_0);
2487 rtw89_phy_write32_idx(rtwdev, R_IMR_TX_ERROR_BE4, B_IMR_TX_ERROR_BE4, 1, RTW89_PHY_1);
2488
2489 rtw8922d_ctrl_mlo(rtwdev, rtwdev->mlo_dbcc_mode, false);
2490
2491 /* read these registers after loading BB parameters */
2492 for (phy_idx = RTW89_PHY_0; phy_idx < RTW89_PHY_NUM; phy_idx++) {
2493 gain->ref_gain_base[phy_idx] =
2494 rtw89_phy_read32_idx(rtwdev, R_OFDM_OFST_P0_BE4,
2495 B_OFDM_OFST_P0_BE4, phy_idx);
2496 gain->cck_rpl_base[phy_idx] =
2497 rtw89_phy_read32_idx(rtwdev, R_CCK_RPL_OFST_BE4,
2498 B_CCK_RPL_OFST_BE4, phy_idx);
2499 }
2500 }
2501
rtw8922d_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2502 static void rtw8922d_set_channel_bb(struct rtw89_dev *rtwdev,
2503 const struct rtw89_chan *chan,
2504 enum rtw89_phy_idx phy_idx)
2505 {
2506 struct rtw89_hal *hal = &rtwdev->hal;
2507 bool cck_en = chan->band_type == RTW89_BAND_2G;
2508 u8 pri_sb = chan->pri_sb_idx;
2509 u32 val;
2510
2511 rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, chan->rfsi_band, phy_idx);
2512 rtw8922d_ctrl_ch(rtwdev, chan, phy_idx);
2513 rtw8922d_ctrl_bw(rtwdev, pri_sb, chan->band_width, phy_idx);
2514 rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
2515
2516 if (cck_en)
2517 rtw8922d_ctrl_sco_cck(rtwdev, chan->primary_channel,
2518 chan->band_width, phy_idx);
2519
2520 rtw8922d_spur_elimination(rtwdev, chan, phy_idx);
2521
2522 if (hal->cid == RTL8922D_CID7025) {
2523 if (chan->band_width == RTW89_CHANNEL_WIDTH_160)
2524 val = 0x1f9;
2525 else if (chan->band_width == RTW89_CHANNEL_WIDTH_80)
2526 val = 0x1f5;
2527 else
2528 val = 0x1e2;
2529
2530 rtw89_phy_write32_idx(rtwdev, R_AWGN_DET_BE4, B_AWGN_DET_BE4, val, phy_idx);
2531 }
2532
2533 rtw8922d_tssi_reset(rtwdev, RF_PATH_AB, phy_idx);
2534 }
2535
rtw8922d_pre_set_channel_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2536 static void rtw8922d_pre_set_channel_bb(struct rtw89_dev *rtwdev,
2537 enum rtw89_phy_idx phy_idx)
2538 {
2539 if (!rtwdev->dbcc_en)
2540 return;
2541
2542 rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4, B_SYS_DBCC_BE4, 0x0);
2543
2544 if (phy_idx == RTW89_PHY_0)
2545 rtw8922d_ctrl_mlo_mode_core(rtwdev, MLO_2_PLUS_0_1RF);
2546 else
2547 rtw8922d_ctrl_mlo_mode_core(rtwdev, MLO_0_PLUS_2_1RF);
2548
2549 fsleep(1);
2550 }
2551
rtw8922d_post_set_channel_bb(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode,enum rtw89_phy_idx phy_idx)2552 static void rtw8922d_post_set_channel_bb(struct rtw89_dev *rtwdev,
2553 enum rtw89_mlo_dbcc_mode mode,
2554 enum rtw89_phy_idx phy_idx)
2555 {
2556 if (!rtwdev->dbcc_en)
2557 return;
2558
2559 rtw8922d_ctrl_mlo(rtwdev, mode, true);
2560 }
2561
rtw8922d_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)2562 static void rtw8922d_set_channel(struct rtw89_dev *rtwdev,
2563 const struct rtw89_chan *chan,
2564 enum rtw89_mac_idx mac_idx,
2565 enum rtw89_phy_idx phy_idx)
2566 {
2567 rtw8922d_set_channel_mac(rtwdev, chan, mac_idx);
2568 rtw8922d_set_channel_bb(rtwdev, chan, phy_idx);
2569 rtw8922d_set_channel_rf(rtwdev, chan, phy_idx);
2570 }
2571
__rtw8922d_dack_reset(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)2572 static void __rtw8922d_dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2573 {
2574 rtw89_phy_write32_mask(rtwdev, 0x3c000 + (path << 8), BIT(17), 0x0);
2575 rtw89_phy_write32_mask(rtwdev, 0x3c000 + (path << 8), BIT(17), 0x1);
2576 }
2577
rtw8922d_dack_reset(struct rtw89_dev * rtwdev)2578 static void rtw8922d_dack_reset(struct rtw89_dev *rtwdev)
2579 {
2580 __rtw8922d_dack_reset(rtwdev, RF_PATH_A);
2581 __rtw8922d_dack_reset(rtwdev, RF_PATH_B);
2582 }
2583
2584 static
rtw8922d_hal_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_mac_idx mac_idx,enum rtw89_band band,u32 * tx_en,bool enter)2585 void rtw8922d_hal_reset(struct rtw89_dev *rtwdev,
2586 enum rtw89_phy_idx phy_idx, enum rtw89_mac_idx mac_idx,
2587 enum rtw89_band band, u32 *tx_en, bool enter)
2588 {
2589 if (enter) {
2590 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, tx_en, RTW89_SCH_TX_SEL_ALL);
2591 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
2592 rtw8922d_dack_reset(rtwdev);
2593 rtw8922d_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
2594 fsleep(40);
2595 rtw8922d_bb_reset_en(rtwdev, band, false, phy_idx);
2596 } else {
2597 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
2598 rtw8922d_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
2599 rtw8922d_bb_reset_en(rtwdev, band, true, phy_idx);
2600 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, *tx_en);
2601 }
2602 }
2603
rtw8922d_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)2604 static void rtw8922d_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
2605 struct rtw89_channel_help_params *p,
2606 const struct rtw89_chan *chan,
2607 enum rtw89_mac_idx mac_idx,
2608 enum rtw89_phy_idx phy_idx)
2609 {
2610 if (enter) {
2611 rtw8922d_pre_set_channel_bb(rtwdev, phy_idx);
2612 rtw8922d_pre_set_channel_rf(rtwdev, phy_idx);
2613 }
2614
2615 rtw8922d_hal_reset(rtwdev, phy_idx, mac_idx, chan->band_type, &p->tx_en, enter);
2616
2617 if (!enter) {
2618 rtw8922d_post_set_channel_bb(rtwdev, rtwdev->mlo_dbcc_mode, phy_idx);
2619 rtw8922d_post_set_channel_rf(rtwdev, phy_idx);
2620 }
2621 }
2622
rtw8922d_rfk_init(struct rtw89_dev * rtwdev)2623 static void rtw8922d_rfk_init(struct rtw89_dev *rtwdev)
2624 {
2625 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
2626 struct rtw89_lck_info *lck = &rtwdev->lck;
2627
2628 rtwdev->is_tssi_mode[RF_PATH_A] = false;
2629 rtwdev->is_tssi_mode[RF_PATH_B] = false;
2630 memset(rfk_mcc, 0, sizeof(*rfk_mcc));
2631 memset(lck, 0, sizeof(*lck));
2632 }
2633
__rtw8922d_rfk_init_late(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2634 static void __rtw8922d_rfk_init_late(struct rtw89_dev *rtwdev,
2635 enum rtw89_phy_idx phy_idx,
2636 const struct rtw89_chan *chan)
2637 {
2638 rtw8922d_rfk_mlo_ctrl(rtwdev);
2639
2640 rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2641 if (!test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2642 rtw89_phy_rfk_rxdck_and_wait(rtwdev, phy_idx, chan, false, 128);
2643 if (phy_idx == RTW89_PHY_0)
2644 rtw89_phy_rfk_dack_and_wait(rtwdev, phy_idx, chan, 58);
2645 }
2646
rtw8922d_rfk_init_late(struct rtw89_dev * rtwdev)2647 static void rtw8922d_rfk_init_late(struct rtw89_dev *rtwdev)
2648 {
2649 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2650
2651 __rtw8922d_rfk_init_late(rtwdev, RTW89_PHY_0, chan);
2652 if (rtwdev->dbcc_en)
2653 __rtw8922d_rfk_init_late(rtwdev, RTW89_PHY_1, chan);
2654 }
2655
_wait_rx_mode(struct rtw89_dev * rtwdev,u8 kpath)2656 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
2657 {
2658 u32 rf_mode;
2659 u8 path;
2660 int ret;
2661
2662 for (path = 0; path < RF_PATH_NUM_8922D; path++) {
2663 if (!(kpath & BIT(path)))
2664 continue;
2665
2666 ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
2667 2, 5000, false, rtwdev, path, 0x00,
2668 RR_MOD_MASK);
2669 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2670 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
2671 path, ret);
2672 }
2673 }
2674
__rtw8922d_tssi_enable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2675 static void __rtw8922d_tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2676 {
2677 u8 path;
2678
2679 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
2680 u32 addr_ofst = (phy_idx << 12) + (path << 8);
2681
2682 rtw89_phy_write32_mask(rtwdev, R_TSSI_DCK_MOV_AVG_LEN_P0_BE4 + addr_ofst,
2683 B_TSSI_DCK_MOV_AVG_LEN_P0_BE4, 0x4);
2684 rtw89_phy_write32_clr(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,
2685 B_USED_TSSI_TRK_ON_P0_BE4);
2686 rtw89_phy_write32_set(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,
2687 B_USED_TSSI_TRK_ON_P0_BE4);
2688 rtw89_phy_write32_clr(rtwdev, R_TSSI_EN_P0_BE4 + addr_ofst,
2689 B_TSSI_EN_P0_BE4);
2690 rtw89_phy_write32_mask(rtwdev, R_TSSI_EN_P0_BE4 + addr_ofst,
2691 B_TSSI_EN_P0_BE4, 0x3);
2692 }
2693 }
2694
__rtw8922d_tssi_disable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2695 static void __rtw8922d_tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2696 {
2697 u8 path;
2698
2699 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
2700 u32 addr_ofst = (phy_idx << 12) + (path << 8);
2701
2702 rtw89_phy_write32_clr(rtwdev, R_TSSI_DCK_MOV_AVG_LEN_P0_BE4 + addr_ofst,
2703 B_TSSI_DCK_MOV_AVG_LEN_P0_BE4);
2704 rtw89_phy_write32_clr(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,
2705 B_USED_TSSI_TRK_ON_P0_BE4);
2706 rtw89_phy_write32_clr(rtwdev, R_TSSI_EN_P0_BE4 + addr_ofst,
2707 B_TSSI_EN_P0_BE4);
2708 }
2709 }
2710
rtw8922d_rfk_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)2711 static void rtw8922d_rfk_tssi(struct rtw89_dev *rtwdev,
2712 enum rtw89_phy_idx phy_idx,
2713 const struct rtw89_chan *chan,
2714 enum rtw89_tssi_mode tssi_mode,
2715 unsigned int ms)
2716 {
2717 int ret;
2718
2719 ret = rtw89_phy_rfk_tssi_and_wait(rtwdev, phy_idx, chan, tssi_mode, ms);
2720 if (ret) {
2721 rtwdev->is_tssi_mode[RF_PATH_A] = false;
2722 rtwdev->is_tssi_mode[RF_PATH_B] = false;
2723 } else {
2724 rtwdev->is_tssi_mode[RF_PATH_A] = true;
2725 rtwdev->is_tssi_mode[RF_PATH_B] = true;
2726 }
2727 }
2728
rtw8922d_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2729 static void rtw8922d_rfk_channel(struct rtw89_dev *rtwdev,
2730 struct rtw89_vif_link *rtwvif_link)
2731 {
2732 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif_link->rtwvif);
2733 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
2734 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2735 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
2736 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
2737 u32 tx_en;
2738
2739 if (ieee80211_vif_is_mld(vif))
2740 rtw8922d_chlk_ktbl_ctl_mld(rtwdev, phy_idx, true);
2741
2742 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_START);
2743 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
2744 _wait_rx_mode(rtwdev, RF_AB);
2745
2746 rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2747 rtw89_phy_rfk_txgapk_and_wait(rtwdev, phy_idx, chan, 54);
2748 rtw89_phy_rfk_txiqk_and_wait(rtwdev, phy_idx, chan, 45);
2749 rtw89_phy_rfk_iqk_and_wait(rtwdev, phy_idx, chan, 84);
2750 rtw8922d_rfk_tssi(rtwdev, phy_idx, chan, RTW89_TSSI_NORMAL, 20);
2751 rtw89_phy_rfk_cim3k_and_wait(rtwdev, phy_idx, chan, 44);
2752 rtw89_phy_rfk_dpk_and_wait(rtwdev, phy_idx, chan, 68);
2753 rtw89_phy_rfk_rxdck_and_wait(rtwdev, RTW89_PHY_0, chan, true, 32);
2754
2755 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
2756 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_STOP);
2757
2758 if (ieee80211_vif_is_mld(vif))
2759 rtw8922d_chlk_ktbl_ctl_mld(rtwdev, phy_idx, false);
2760 }
2761
rtw8922d_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2762 static void rtw8922d_rfk_band_changed(struct rtw89_dev *rtwdev,
2763 enum rtw89_phy_idx phy_idx,
2764 const struct rtw89_chan *chan)
2765 {
2766 }
2767
__rtw8922d_txiqk_disable(struct rtw89_dev * rtwdev)2768 static void __rtw8922d_txiqk_disable(struct rtw89_dev *rtwdev)
2769 {
2770 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
2771 u8 path, kidx;
2772
2773 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
2774 kidx = rtw89_phy_read32_mask(rtwdev, R_KTBL0A_BE4 + (path << 8),
2775 B_KTBL0_IDX0);
2776 if (kidx == 0) {
2777 rtw89_phy_write32_clr(rtwdev, R_CFIR_CTRL_A_BE4 + (path << 8),
2778 B_CFIR_CTRL_KIDX0_EN);
2779 } else if (kidx == 1) {
2780 rtw89_phy_write32_clr(rtwdev, R_CFIR_CTRL_A_BE4 + (path << 8),
2781 B_CFIR_CTRL_KIDX1_EN);
2782 } else {
2783 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG_BE4,
2784 B_NCTL_CFG_BE4_SPAGE, 0x1);
2785 rtw89_phy_write32_clr(rtwdev, R_CFIR_CTRL_A_BE4 + (path << 8),
2786 B_CFIR_CTRL_KIDX0_EN);
2787 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG_BE4,
2788 B_NCTL_CFG_BE4_SPAGE, 0x0);
2789 }
2790
2791 iqk_info->iqc_bak[path] =
2792 rtw89_phy_read32(rtwdev, R_TX_IQC_A_BE4 + (path << 8));
2793 rtw89_phy_write32(rtwdev, R_TX_IQC_A_BE4 + (path << 8), 0x40000002);
2794 }
2795 }
2796
__rtw8922d_txiqk_enable(struct rtw89_dev * rtwdev)2797 static void __rtw8922d_txiqk_enable(struct rtw89_dev *rtwdev)
2798 {
2799 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
2800 u8 path, kidx;
2801
2802 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
2803 kidx = rtw89_phy_read32_mask(rtwdev, R_KTBL0A_BE4 + (path << 8),
2804 B_KTBL0_IDX0);
2805 if (kidx == 0) {
2806 rtw89_phy_write32_set(rtwdev, R_CFIR_CTRL_A_BE4 + (path << 8),
2807 B_CFIR_CTRL_KIDX0_EN);
2808 } else if (kidx == 1) {
2809 rtw89_phy_write32_set(rtwdev, R_CFIR_CTRL_A_BE4 + (path << 8),
2810 B_CFIR_CTRL_KIDX1_EN);
2811 } else {
2812 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG_BE4,
2813 B_NCTL_CFG_BE4_SPAGE, 0x1);
2814 rtw89_phy_write32_set(rtwdev, R_CFIR_CTRL_A_BE4 + (path << 8),
2815 B_CFIR_CTRL_KIDX0_EN);
2816 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG_BE4,
2817 B_NCTL_CFG_BE4_SPAGE, 0x0);
2818 }
2819
2820 rtw89_phy_write32(rtwdev, R_TX_IQC_A_BE4 + (path << 8),
2821 iqk_info->iqc_bak[path]);
2822 }
2823 }
2824
rtw8922d_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)2825 static void rtw8922d_rfk_scan(struct rtw89_dev *rtwdev,
2826 struct rtw89_vif_link *rtwvif_link,
2827 bool start)
2828 {
2829 if (start) {
2830 __rtw8922d_tssi_disable(rtwdev, rtwvif_link->phy_idx);
2831 __rtw8922d_txiqk_disable(rtwdev);
2832 } else {
2833 __rtw8922d_tssi_enable(rtwdev, rtwvif_link->phy_idx);
2834 __rtw8922d_txiqk_enable(rtwdev);
2835 }
2836 }
2837
rtw8922d_rfk_track(struct rtw89_dev * rtwdev)2838 static void rtw8922d_rfk_track(struct rtw89_dev *rtwdev)
2839 {
2840 rtw8922d_lck_track(rtwdev);
2841 }
2842
2843 static const struct rtw89_reg_def rtw8922d_txpwr_ref[][3] = {
2844 {{ .addr = R_TXAGC_REF_DBM_PATH0_TBL0_BE4,
2845 .mask = B_TXAGC_OFDM_REF_DBM_PATH0_TBL0_BE4 },
2846 { .addr = R_TXAGC_REF_DBM_PATH0_TBL0_BE4,
2847 .mask = B_TXAGC_CCK_REF_DBM_PATH0_TBL0_BE4 },
2848 { .addr = R_TSSI_K_OFDM_PATH0_TBL0_BE4,
2849 .mask = B_TSSI_K_OFDM_PATH0_TBL0_BE4 }
2850 },
2851 {{ .addr = R_TXAGC_REF_DBM_PATH0_TBL1_BE4,
2852 .mask = B_TXAGC_OFDM_REF_DBM_PATH0_TBL1_BE4 },
2853 { .addr = R_TXAGC_REF_DBM_PATH0_TBL1_BE4,
2854 .mask = B_TXAGC_CCK_REF_DBM_PATH0_TBL1_BE4 },
2855 { .addr = R_TSSI_K_OFDM_PATH0_TBL1_BE4,
2856 .mask = B_TSSI_K_OFDM_PATH0_TBL1_BE4 }
2857 },
2858 };
2859
rtw8922d_set_txpwr_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2860 static void rtw8922d_set_txpwr_diff(struct rtw89_dev *rtwdev,
2861 const struct rtw89_chan *chan,
2862 enum rtw89_phy_idx phy_idx)
2863 {
2864 s16 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan);
2865 const struct rtw89_chip_info *chip = rtwdev->chip;
2866 static const u32 path_ofst[] = {0x0, 0x100};
2867 const struct rtw89_reg_def *txpwr_ref;
2868 s16 tssi_k_ofst = abs(pwr_ofst);
2869 s16 ofst_dec[RF_PATH_NUM_8922D];
2870 s16 tssi_k[RF_PATH_NUM_8922D];
2871 s16 pwr_ref_ofst;
2872 s16 pwr_ref = 16;
2873 u8 i;
2874
2875 pwr_ref <<= chip->txpwr_factor_rf;
2876 pwr_ref_ofst = pwr_ref - rtw89_phy_txpwr_bb_to_rf(rtwdev, abs(pwr_ofst));
2877
2878 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? pwr_ref : pwr_ref_ofst;
2879 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ref_ofst : pwr_ref;
2880 tssi_k[RF_PATH_A] = pwr_ofst > 0 ? 0 : tssi_k_ofst;
2881 tssi_k[RF_PATH_B] = pwr_ofst > 0 ? tssi_k_ofst : 0;
2882
2883 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
2884 txpwr_ref = rtw8922d_txpwr_ref[phy_idx];
2885
2886 rtw89_phy_write32_mask(rtwdev, txpwr_ref[0].addr + path_ofst[i],
2887 txpwr_ref[0].mask, ofst_dec[i]);
2888 rtw89_phy_write32_mask(rtwdev, txpwr_ref[1].addr + path_ofst[i],
2889 txpwr_ref[1].mask, ofst_dec[i]);
2890 rtw89_phy_write32_mask(rtwdev, txpwr_ref[2].addr + path_ofst[i],
2891 txpwr_ref[2].mask, tssi_k[i]);
2892 }
2893 }
2894
rtw8922d_set_txpwr_ref(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2895 static void rtw8922d_set_txpwr_ref(struct rtw89_dev *rtwdev,
2896 const struct rtw89_chan *chan,
2897 enum rtw89_phy_idx phy_idx)
2898 {
2899 s16 ref_ofdm = 0;
2900 s16 ref_cck = 0;
2901
2902 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
2903
2904 rtw8922d_set_txpwr_diff(rtwdev, chan, phy_idx);
2905
2906 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2907 B_BE_PWR_REF_CTRL_OFDM, ref_ofdm);
2908 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2909 B_BE_PWR_REF_CTRL_CCK, ref_cck);
2910 }
2911
rtw8922d_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2912 static void rtw8922d_set_tx_shape(struct rtw89_dev *rtwdev,
2913 const struct rtw89_chan *chan,
2914 enum rtw89_phy_idx phy_idx)
2915 {
2916 const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
2917 u8 band = chan->band_type;
2918 u8 tx_shape_idx;
2919 const u16 *th;
2920
2921 tx_shape_idx = rtw89_get_tx_shape_idx(rtwdev, band, RTW89_RS_OFDM);
2922 if (tx_shape_idx == 0)
2923 goto disable;
2924
2925 th = d->bands[chan->rfsi_band].qam_comp_th0;
2926 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, th[0], phy_idx);
2927 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, th[1], phy_idx);
2928 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, th[2], phy_idx);
2929 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, th[3], phy_idx);
2930 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, th[4], phy_idx);
2931 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, th[5], phy_idx);
2932 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, th[6], phy_idx);
2933 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, th[7], phy_idx);
2934
2935 th = d->bands[chan->rfsi_band].qam_comp_ow;
2936 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, th[0], phy_idx);
2937 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, th[1], phy_idx);
2938 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, th[2], phy_idx);
2939 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, th[3], phy_idx);
2940 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, th[4], phy_idx);
2941 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, th[5], phy_idx);
2942 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, th[6], phy_idx);
2943 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, th[7], phy_idx);
2944
2945 return;
2946
2947 disable:
2948 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
2949 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
2950 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
2951 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
2952 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
2953 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
2954 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, B_QAM_COMP_TH_TRIANGULAR_L, 0, phy_idx);
2955 rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, B_QAM_COMP_TH_TRIANGULAR_H, 0, phy_idx);
2956
2957 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
2958 rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
2959 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
2960 rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
2961 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
2962 rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
2963 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, B_OW_VAL_TRIANGULAR_L, 0, phy_idx);
2964 rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, B_OW_VAL_TRIANGULAR_H, 0, phy_idx);
2965 }
2966
rtw8922d_set_txpwr_sar_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2967 static void rtw8922d_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
2968 const struct rtw89_chan *chan,
2969 enum rtw89_phy_idx phy_idx)
2970 {
2971 struct rtw89_sar_parm sar_parm = {
2972 .center_freq = chan->freq,
2973 .force_path = true,
2974 };
2975 s16 sar_rf;
2976 s8 sar_mac;
2977
2978 if (phy_idx != RTW89_PHY_0)
2979 return;
2980
2981 sar_parm.path = RF_PATH_A;
2982 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2983 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2984 rtw89_phy_write32_mask(rtwdev, R_P0_TXPWRB_BE4, B_TXPWRB_MAX_BE, sar_rf);
2985
2986 sar_parm.path = RF_PATH_B;
2987 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2988 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2989 rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB_BE4, B_TXPWRB_MAX_BE, sar_rf);
2990 }
2991
rtw8922d_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2992 static void rtw8922d_set_txpwr(struct rtw89_dev *rtwdev,
2993 const struct rtw89_chan *chan,
2994 enum rtw89_phy_idx phy_idx)
2995 {
2996 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2997 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2998 rtw8922d_set_tx_shape(rtwdev, chan, phy_idx);
2999 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
3000 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
3001 rtw8922d_set_txpwr_ref(rtwdev, chan, phy_idx);
3002 rtw8922d_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
3003 }
3004
rtw8922d_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)3005 static void rtw8922d_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
3006 enum rtw89_phy_idx phy_idx)
3007 {
3008 struct rtw89_entity_conf conf;
3009
3010 rtw89_entity_get_conf(rtwdev, &conf);
3011
3012 rtw8922d_set_txpwr_ref(rtwdev, conf.chans[phy_idx], phy_idx);
3013 }
3014
rtw8922d_ctrl_trx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path tx_path,u8 tx_nss,enum rtw89_rf_path rx_path,u8 rx_nss)3015 static void rtw8922d_ctrl_trx_path(struct rtw89_dev *rtwdev,
3016 enum rtw89_rf_path tx_path, u8 tx_nss,
3017 enum rtw89_rf_path rx_path, u8 rx_nss)
3018 {
3019 enum rtw89_phy_idx phy_idx;
3020
3021 for (phy_idx = RTW89_PHY_0; phy_idx <= RTW89_PHY_1; phy_idx++) {
3022 rtw8922d_ctrl_tx_path_tmac(rtwdev, tx_path, phy_idx);
3023 rtw8922d_ctrl_rx_path_tmac(rtwdev, rx_path, phy_idx);
3024
3025 rtw8922d_tssi_reset(rtwdev, rx_path, phy_idx);
3026 }
3027 }
3028
rtw8922d_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)3029 static void rtw8922d_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
3030 enum rtw89_phy_idx phy_idx)
3031 {
3032 if (en) {
3033 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx);
3034 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
3035 0xf, phy_idx);
3036 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
3037 0x0, phy_idx);
3038 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx);
3039 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx);
3040 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx);
3041 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx);
3042 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx);
3043 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx);
3044 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
3045 0xf, phy_idx);
3046 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
3047 0x0, phy_idx);
3048 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx);
3049 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA1_B, 0x80, phy_idx);
3050 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx);
3051 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx);
3052 } else {
3053 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx);
3054 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
3055 0x0, phy_idx);
3056 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
3057 0x1, phy_idx);
3058 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx);
3059 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx);
3060 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx);
3061 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx);
3062 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx);
3063 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx);
3064 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
3065 0x0, phy_idx);
3066 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
3067 0x1, phy_idx);
3068 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx);
3069 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA1_B, 0x2a, phy_idx);
3070 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx);
3071 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx);
3072 }
3073 }
3074
rtw8922d_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)3075 static void rtw8922d_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
3076 {
3077 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
3078 enum rtw89_band band = chan->band_type;
3079 struct rtw89_hal *hal = &rtwdev->hal;
3080 u8 ntx_path = RF_PATH_AB;
3081 u8 nrx_path = RF_PATH_AB;
3082 u32 tx_en0, tx_en1;
3083 u8 rx_nss = 2;
3084
3085 if (hal->antenna_tx == RF_A)
3086 ntx_path = RF_PATH_A;
3087 else if (hal->antenna_tx == RF_B)
3088 ntx_path = RF_PATH_B;
3089
3090 if (hal->antenna_rx == RF_A)
3091 nrx_path = RF_PATH_A;
3092 else if (hal->antenna_rx == RF_B)
3093 nrx_path = RF_PATH_B;
3094
3095 if (nrx_path != RF_PATH_AB)
3096 rx_nss = 1;
3097
3098 rtw8922d_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, true);
3099 if (rtwdev->dbcc_en)
3100 rtw8922d_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
3101 &tx_en1, true);
3102
3103 rtw8922d_ctrl_trx_path(rtwdev, ntx_path, 2, nrx_path, rx_nss);
3104
3105 rtw8922d_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, false);
3106 if (rtwdev->dbcc_en)
3107 rtw8922d_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
3108 &tx_en1, false);
3109 }
3110
rtw8922d_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)3111 static u8 rtw8922d_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
3112 {
3113 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
3114 u8 val;
3115
3116 rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_EN_BE4, 0x1);
3117 rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_TRIG_BE4, 0x0);
3118 rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_TRIG_BE4, 0x1);
3119
3120 fsleep(100);
3121
3122 val = rtw89_phy_read32_mask(rtwdev, R_TC_VAL_BE4, B_TC_VAL_BE4);
3123 val = clamp_t(int, val + info->thermal_k, 0, 255);
3124
3125 return val;
3126 }
3127
rtw8922d_chan_to_rf18_val(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)3128 static u32 rtw8922d_chan_to_rf18_val(struct rtw89_dev *rtwdev,
3129 const struct rtw89_chan *chan)
3130 {
3131 u32 val = u32_encode_bits(chan->channel, RR_CFGCH_CH);
3132
3133 switch (chan->band_type) {
3134 case RTW89_BAND_2G:
3135 default:
3136 break;
3137 case RTW89_BAND_5G:
3138 val |= u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
3139 u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
3140 break;
3141 case RTW89_BAND_6G:
3142 val |= u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
3143 u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
3144 break;
3145 }
3146
3147 switch (chan->band_width) {
3148 case RTW89_CHANNEL_WIDTH_5:
3149 case RTW89_CHANNEL_WIDTH_10:
3150 case RTW89_CHANNEL_WIDTH_20:
3151 default:
3152 break;
3153 case RTW89_CHANNEL_WIDTH_40:
3154 val |= u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
3155 break;
3156 case RTW89_CHANNEL_WIDTH_80:
3157 val |= u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
3158 break;
3159 case RTW89_CHANNEL_WIDTH_160:
3160 val |= u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
3161 break;
3162 case RTW89_CHANNEL_WIDTH_320:
3163 val |= u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
3164 break;
3165 }
3166
3167 return val;
3168 }
3169
rtw8922d_btc_set_rfe(struct rtw89_dev * rtwdev)3170 static void rtw8922d_btc_set_rfe(struct rtw89_dev *rtwdev)
3171 {
3172 struct rtw89_btc *btc = &rtwdev->btc;
3173 struct rtw89_btc_module *md = &btc->mdinfo;
3174 struct rtw89_btc_dm *dm = &btc->dm;
3175 struct rtw89_btc_cx *cx = &btc->cx;
3176 u8 efuse_bt_func, efuse_ant_info, bt_sw_gpio_pos;
3177 u8 is_combo, is_bt_share, is_spdt;
3178 u8 tx_path_pos, rx_path_pos;
3179 u8 i, j;
3180
3181 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s !!\n", __func__);
3182
3183 /* get from final capability of device */
3184 md->rfe_type = rtwdev->efuse.rfe_type;
3185 md->kt_ver = rtwdev->hal.cv;
3186 md->kt_ver_adie = rtwdev->hal.acv;
3187 md->wa_type = 0;
3188 dm->wl_trx_nss_en = 0;
3189
3190 md->ant.num = 2;
3191 md->ant.single_pos = BTC_RF_S0; /* WL 1ss+1Ant 0:s0(A)/ 1:s1(B) */
3192
3193 /* set default antenna isolation */
3194 cx->bt0.ant_iso_to_wl = md->ant.isolation;
3195 cx->bt1.ant_iso_to_wl = md->ant.isolation;
3196
3197 md->ant.stream_cnt = (rtwdev->hal.tx_nss << BTC_ANT_SHIFT) +
3198 rtwdev->hal.rx_nss;
3199 md->ant.btg_pos = BTC_RF_S1; /* BTG0 at WL-S1 */
3200 md->ant.btg1_pos = BTC_RF_S0; /* BTG1 at WL-S0 if Dual-BTGA */
3201
3202 cx->bt0.band_56G_support = 1;
3203 cx->bt1.band_56G_support = 1;
3204 cx->bt0.func_type = BTC_BTF_BT;
3205 cx->bt1.func_type = BTC_BTF_BT;
3206
3207 efuse_bt_func = rtwdev->efuse.bt_setting_2;
3208
3209 is_spdt = !!(efuse_bt_func & BIT(5));
3210
3211 switch ((efuse_bt_func & 0xc0) >> 6) { /* 0xcd[7:6] */
3212 default:
3213 case 0:
3214 bt_sw_gpio_pos = 5;
3215 break;
3216 case 1:
3217 bt_sw_gpio_pos = 11;
3218 break;
3219 case 2:
3220 bt_sw_gpio_pos = 15;
3221 break;
3222 case 3:
3223 bt_sw_gpio_pos = 20;
3224 break;
3225 }
3226
3227 efuse_bt_func &= 0x1f; /* 0xcd[4:0] */
3228 efuse_ant_info = rtwdev->efuse.bt_setting_3;
3229 md->ant.num = (efuse_ant_info & 0xe0) >> 5; /* 0xCE[7:5] */
3230 is_combo = (efuse_ant_info & 0xe) >> 1; /* 0xCE[3:1] */
3231 is_bt_share = efuse_ant_info & BIT(0); /* 0xCE[0] */
3232
3233 memset(dm->ant_xmap, 0, sizeof(dm->ant_xmap));
3234
3235 /* To-Do: "RFE_TYpe" to "ant.num" translation */
3236 switch (md->ant.num) {
3237 case 1: /* 1-Ant WL-S0 only & BT0 only */
3238 md->ant.type = BTC_ANT_SHARED;
3239 md->bt0_pos = BTC_BT_BTG;
3240 md->bt0_sw_type = BTC_SWITCH_V1_INTERNAL;
3241 md->ant.btg_pos = BTC_RF_S0; /* BTG0 at WL-S0 */
3242 md->ant.func[0] = BTC_EFMAP_BT0;
3243 dm->ant_xmap[BTC_RF_S0][BTC_BT_1ST] = 1; /* BT0 shared with S0*/
3244 dm->ant_xmap[BTC_RF_S1][BTC_BT_1ST] = 0; /* WL 1T1R no RF-S1 */
3245 break;
3246 case 2: /* 2-Ant */
3247 default:
3248 if (is_combo) {
3249 if (efuse_bt_func == (BTC_EFMAP_BT0 | BTC_EFMAP_BT1))
3250 md->ant.func[0] = BTC_EFMAP_BT1;
3251
3252 md->ant.func[1] = BTC_EFMAP_BT0;
3253 } else {
3254 md->ant.func[0] = BTC_EFMAP_NONE;
3255 md->ant.func[1] = BTC_EFMAP_NONE;
3256 }
3257
3258 if (is_bt_share) { /* WL-S0 + (WL-S1 & BT0-S1) */
3259 md->ant.type = BTC_ANT_SHARED;
3260 md->bt0_pos = BTC_BT_BTG;
3261 md->bt0_sw_type = BTC_SWITCH_INTERNAL;
3262 dm->ant_xmap[BTC_RF_S1][BTC_BT_1ST] = 1;
3263 } else { /* WL-S0 + BT0-S1 */
3264 md->ant.type = BTC_ANT_DEDICATED;
3265 md->bt0_pos = BTC_BT_ALONE;
3266 md->bt0_sw_type = BTC_SWITCH_V1_NONE;
3267 }
3268
3269 if (md->ant.func[0] == BTC_EFMAP_BT1) { /* if 2nd BT exist */
3270 dm->ant_xmap[BTC_RF_S0][BTC_BT_2ND] = 1;
3271 if (is_spdt) { /* WL-S0 & BT1 by SPDT */
3272 md->bt1_pos = BTC_BT_ALONE;
3273 /* Todo: set SPDT GPIO-ctrl */
3274 md->bt1_sw_type = bt_sw_gpio_pos;
3275 } else { /* WL-S0 & BT1-S1 by BTGA */
3276 md->bt1_pos = BTC_BT_BTG;
3277 md->bt1_sw_type = BTC_SWITCH_V1_INTERNAL;
3278 }
3279 }
3280
3281 dm->wl_trx_nss_en = 1; /* 1ss MIMO-PS capability if 1-BT */
3282 break;
3283 case 3: /* 3-Ant, 3 different BT-configuration */
3284 if (is_bt_share) {
3285 md->ant.func[0] = BTC_EFMAP_NONE;
3286 md->ant.func[1] = BTC_EFMAP_BT0;
3287 md->ant.func[2] = efuse_bt_func & (~BTC_EFMAP_BT0);
3288 md->ant.type = BTC_ANT_SHARED;
3289 md->bt0_pos = BTC_BT_BTG;
3290 md->bt0_sw_type = BTC_SWITCH_V1_INTERNAL;
3291 dm->ant_xmap[BTC_RF_S1][BTC_BT_1ST] = 1;
3292 dm->wl_trx_nss_en = 1; /* 1ss MIMO-PS capability */
3293 } else {
3294 md->ant.func[0] = BTC_EFMAP_NONE;
3295 md->ant.func[1] = BTC_EFMAP_NONE;
3296 md->ant.func[2] = efuse_bt_func;
3297 md->ant.type = BTC_ANT_DEDICATED;
3298 md->bt0_pos = BTC_BT_ALONE;
3299 md->bt0_sw_type = BTC_SWITCH_V1_NONE;
3300 }
3301
3302 md->bt1_pos = BTC_BT_ALONE; /* BT1 may exist or not */
3303 md->bt1_sw_type = BTC_SWITCH_V1_NONE;
3304 break;
3305 case 4: /* 4-Ant, WL-S0 + WL-S1 + BT0 + BT1 */
3306 md->ant.func[0] = BTC_EFMAP_NONE;
3307 md->ant.func[1] = BTC_EFMAP_NONE;
3308 md->ant.func[2] = BTC_EFMAP_BT0;
3309 md->ant.func[3] = efuse_bt_func & (~BTC_EFMAP_BT0);
3310 md->ant.type = BTC_ANT_DEDICATED;
3311 md->bt0_pos = BTC_BT_ALONE;
3312 md->bt0_sw_type = BTC_SWITCH_V1_NONE;
3313 md->bt1_pos = BTC_BT_ALONE;
3314 md->bt1_sw_type = BTC_SWITCH_V1_NONE;
3315 break;
3316 case 5:
3317 md->ant.func[0] = BTC_EFMAP_NONE;
3318 md->ant.func[1] = BTC_EFMAP_NONE;
3319 md->ant.func[2] = BTC_EFMAP_BT0;
3320 md->ant.func[3] = BTC_EFMAP_BT1;
3321 md->ant.func[4] = BTC_EFMAP_ZB;
3322 md->ant.type = BTC_ANT_DEDICATED;
3323 md->bt0_pos = BTC_BT_ALONE;
3324 md->bt0_sw_type = BTC_SWITCH_V1_NONE;
3325 md->bt1_pos = BTC_BT_ALONE;
3326 md->bt1_sw_type = BTC_SWITCH_V1_NONE;
3327 break;
3328 }
3329
3330 tx_path_pos = _btc_get_rf_path_from_ant_num(btc, rtwdev->hal.tx_nss);
3331 rx_path_pos = _btc_get_rf_path_from_ant_num(btc, rtwdev->hal.rx_nss);
3332 /* Combine TX[7:4] and RX[3:0] into path_pos byte */
3333 md->ant.path_pos = ((tx_path_pos << BTC_ANT_SHIFT) & BTC_ANT_TX_MASK) |
3334 (rx_path_pos & BTC_ANT_RX_MASK);
3335
3336 /*
3337 * if only BT0 at BTGA: 2-Ant, 3-Ant(BT1 used dedicated-ant)
3338 * can setup dm->wl_trx_nss_en = 1, WL MIMO-PS to 1T1R
3339 * (WL at WL-S0 only, BT0 at WL-S1)
3340 * tx_limit/rx_limit is decided by _set_trx_nss()
3341 */
3342 if (dm->wl_trx_nss_en &&
3343 (dm->wl_trx_nss.tx_limit && dm->wl_trx_nss.rx_limit)) {
3344 md->ant.type = BTC_ANT_DEDICATED;
3345 md->ant.stream_cnt = 1;
3346 dm->ant_xmap[BTC_RF_S0][BTC_BT_1ST] = 0; /* wl 1ss-> RF-S0 */
3347 dm->ant_xmap[BTC_RF_S1][BTC_BT_1ST] = 0; /* BT0-> RF-S1 */
3348 dm->ant_xmap[BTC_RF_S0][BTC_BT_2ND] = 0;
3349 dm->ant_xmap[BTC_RF_S1][BTC_BT_2ND] = 0; /* BT1 -> 3rd Ant */
3350 }
3351
3352 /*
3353 * Todo: call HALBB API to set BT0/1 at WL_S0 or WL_S1
3354 * r_sel_gnt_bt_rx_path0[1:0], r_sel_gnt_bt_rx_path1[1:0]
3355 * WL_S0 with BT1 -> r_sel_gnt_bt_rx_path0[1:0]= 2b'10
3356 * WL_S1 with BT0 -> r_sel_gnt_bt_rx_path1[1:0]= 2b'01
3357 */
3358
3359 /* To Do: setup ext-SOC coex if exist */
3360 switch (cx->bt_ext.chip_id) {
3361 default:
3362 case BTC_ESOC_NONE:
3363 memset(&cx->bt_ext, 0, sizeof(struct rtw89_btc_extsoc_info));
3364 cx->bt_ext.max_tx_pwr = RTW89_BTC_BT_DEF_LE_TX_PWR;
3365 cx->bt_ext.ant_iso_to_wl = RTW89_BTC_DEFAULT_ANISO;
3366 break;
3367 case BTC_ESOC_8771:
3368 cx->bt_ext.func_type = BTC_BTF_THREAD;
3369 cx->bt_ext.hw_coex = BTC_EXTSOC_INTF_PTA;
3370 cx->bt_ext.rf_band_map = 0x1; /* 2.4GHz only */
3371 cx->bt_ext.link_weight[BTC_BT_B2G] = 10;
3372 cx->bt_ext.profile_map[BTC_BT_B2G] |= BTC_BT_THREAD;
3373 /* use GPIO 12~15 for Ext-4-wire-PTA */
3374 cx->bt_ext.hpta_cfg = BIT(12) | BIT(13) | BIT(14) | BIT(15);
3375 /* for Ext-SOC locate at Ant-2 */
3376 if (md->ant.num >= 5)
3377 md->ant.func[4] = BTC_EFMAP_ZB;
3378 else
3379 md->ant.func[md->ant.num - 1] = BTC_EFMAP_ZB;
3380 break;
3381 }
3382
3383 dm->ant_xmap[BTC_RF_S0][BTC_BT_EXT] = 0;
3384 dm->ant_xmap[BTC_RF_S1][BTC_BT_EXT] = 0;
3385
3386 for (i = BTC_RF_S0; i <= BTC_RF_S1; i++)
3387 for (j = BTC_BT_1ST; j <= BTC_BT_EXT; j++)
3388 md->ant.ant_xmap[i][j] = dm->ant_xmap[i][j];
3389
3390 rtwdev->btc.btg_pos = md->ant.btg_pos;
3391 rtwdev->btc.ant_type = md->ant.type;
3392 }
3393
rtw8922d_btc_init_cfg(struct rtw89_dev * rtwdev)3394 static void rtw8922d_btc_init_cfg(struct rtw89_dev *rtwdev)
3395 {
3396 /* offload to firmware */
3397 }
3398
3399 static void
rtw8922d_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)3400 rtw8922d_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
3401 {
3402 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
3403 u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));
3404
3405 switch (ctrl_all_time) {
3406 case 0xffff:
3407 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
3408 B_BE_FORCE_PWR_BY_RATE_EN, 0x0);
3409 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
3410 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0);
3411 break;
3412 default:
3413 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
3414 B_BE_FORCE_PWR_BY_RATE_VAL, ctrl_all_time);
3415 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
3416 B_BE_FORCE_PWR_BY_RATE_EN, 0x1);
3417 break;
3418 }
3419
3420 switch (ctrl_gnt_bt) {
3421 case 0xffff:
3422 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
3423 B_BE_PWR_BT_EN, 0x0);
3424 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
3425 B_BE_PWR_BT_VAL, 0x0);
3426 break;
3427 default:
3428 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
3429 B_BE_PWR_BT_VAL, ctrl_gnt_bt);
3430 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
3431 B_BE_PWR_BT_EN, 0x1);
3432 break;
3433 }
3434 }
3435
3436 static
rtw8922d_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)3437 s8 rtw8922d_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
3438 {
3439 return clamp_t(s8, val, -100, 0) + 100;
3440 }
3441
3442 static const struct rtw89_btc_rf_trx_para_v9 rtw89_btc_8922d_rf_ul_v9[] = {
3443 /*
3444 * 0 -> original
3445 * 1 -> for BT-connected ACI issue && BTG co-rx
3446 * 2 ~ 4 ->reserved for shared-antenna
3447 * 5 ~ 8 ->for non-shared-antenna free-run
3448 */
3449 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3450 {{15, 15}, {2, 2}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3451 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3452 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3453 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3454 {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3455 {{ 6, 6}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3456 {{13, 13}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3457 {{13, 13}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3458 };
3459
3460 static const struct rtw89_btc_rf_trx_para_v9 rtw89_btc_8922d_rf_dl_v9[] = {
3461 /*
3462 * 0 -> original
3463 * 1 -> for BT-connected ACI issue && BTG co-rx
3464 * 2 ~ 4 ->reserved for shared-antenna
3465 * 5 ~ 8 ->for non-shared-antenna free-run
3466 */
3467 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3468 {{15, 15}, {2, 2}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3469 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3470 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3471 {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3472 {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3473 {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3474 {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3475 {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
3476 };
3477
3478 static const u8 rtw89_btc_8922d_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
3479 static const u8 rtw89_btc_8922d_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
3480
3481 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8922d_mon_reg[] = {
3482 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
3483 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
3484 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
3485 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
3486 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
3487 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
3488 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
3489 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
3490 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe354),
3491 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe35c),
3492 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe370),
3493 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe380),
3494 };
3495
3496 static
rtw8922d_btc_update_bt_cnt(struct rtw89_dev * rtwdev)3497 void rtw8922d_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
3498 {
3499 /* Feature move to firmware */
3500 }
3501
3502 static
rtw8922d_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)3503 void rtw8922d_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
3504 {
3505 /* Feature move to firmware */
3506 }
3507
rtw8922d_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)3508 static void rtw8922d_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
3509 {
3510 /* Feature move to firmware */
3511 }
3512
rtw8922d_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)3513 static void rtw8922d_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
3514 struct rtw89_rx_phy_ppdu *phy_ppdu,
3515 struct ieee80211_rx_status *status)
3516 {
3517 u8 chan_idx = phy_ppdu->chan_idx;
3518 enum nl80211_band band;
3519 u8 ch;
3520
3521 if (chan_idx == 0)
3522 return;
3523
3524 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
3525 status->freq = ieee80211_channel_to_frequency(ch, band);
3526 status->band = band;
3527 }
3528
rtw8922d_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)3529 static void rtw8922d_query_ppdu(struct rtw89_dev *rtwdev,
3530 struct rtw89_rx_phy_ppdu *phy_ppdu,
3531 struct ieee80211_rx_status *status)
3532 {
3533 u8 path;
3534 u8 *rx_power = phy_ppdu->rssi;
3535
3536 if (!status->signal)
3537 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
3538 rx_power[RF_PATH_B]));
3539
3540 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
3541 status->chains |= BIT(path);
3542 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
3543 }
3544 if (phy_ppdu->valid)
3545 rtw8922d_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
3546 }
3547
rtw8922d_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)3548 static void rtw8922d_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
3549 struct rtw89_rx_phy_ppdu *phy_ppdu)
3550 {
3551 /* Mapping to BW: 5, 10, 20, 40, 80, 160, 80_80 */
3552 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0};
3553 u8 *rssi = phy_ppdu->rssi;
3554 u8 compensate = 0;
3555 u8 i;
3556
3557 if (phy_ppdu->bw_idx < ARRAY_SIZE(bw_compensate))
3558 compensate = bw_compensate[phy_ppdu->bw_idx];
3559
3560 for (i = 0; i < RF_PATH_NUM_8922D; i++) {
3561 if (!(phy_ppdu->rx_path_en & BIT(i))) {
3562 rssi[i] = 0;
3563 phy_ppdu->rpl_path[i] = 0;
3564 phy_ppdu->rpl_fd[i] = 0;
3565 }
3566
3567 if (phy_ppdu->ie != RTW89_CCK_PKT && rssi[i])
3568 rssi[i] += compensate;
3569
3570 phy_ppdu->rpl_path[i] = rssi[i];
3571 }
3572 }
3573
rtw8922d_phy_rpt_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)3574 static void rtw8922d_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
3575 struct rtw89_rx_desc_info *desc_info,
3576 struct ieee80211_rx_status *rx_status)
3577 {
3578 if (desc_info->rssi <= 0x1 || (desc_info->rssi >> 2) > MAX_RSSI)
3579 return;
3580
3581 rx_status->signal = (desc_info->rssi >> 2) - MAX_RSSI;
3582 }
3583
rtw8922d_mac_enable_bb_rf(struct rtw89_dev * rtwdev)3584 static int rtw8922d_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3585 {
3586 return 0;
3587 }
3588
rtw8922d_mac_disable_bb_rf(struct rtw89_dev * rtwdev)3589 static int rtw8922d_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3590 {
3591 return 0;
3592 }
3593
3594 static const struct rtw89_chanctx_listener rtw8922d_chanctx_listener = {
3595 .callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb,
3596 };
3597
3598 #ifdef CONFIG_PM
3599 static const struct wiphy_wowlan_support rtw_wowlan_stub_8922d = {
3600 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT |
3601 WIPHY_WOWLAN_NET_DETECT,
3602 .n_patterns = RTW89_MAX_PATTERN_NUM,
3603 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
3604 .pattern_min_len = 1,
3605 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID,
3606 };
3607 #endif
3608
3609 static const struct rtw89_chip_ops rtw8922d_chip_ops = {
3610 .enable_bb_rf = rtw8922d_mac_enable_bb_rf,
3611 .disable_bb_rf = rtw8922d_mac_disable_bb_rf,
3612 .bb_preinit = rtw8922d_bb_preinit,
3613 .bb_postinit = rtw8922d_bb_postinit,
3614 .bb_reset = rtw8922d_bb_reset,
3615 .bb_sethw = rtw8922d_bb_sethw,
3616 .read_rf = rtw89_phy_read_rf_v3,
3617 .write_rf = rtw89_phy_write_rf_v3,
3618 .set_channel = rtw8922d_set_channel,
3619 .set_channel_help = rtw8922d_set_channel_help,
3620 .read_efuse = rtw8922d_read_efuse,
3621 .read_phycap = rtw8922d_read_phycap,
3622 .fem_setup = NULL,
3623 .data_setup = rtw8922d_data_setup,
3624 .rfe_gpio = NULL,
3625 .rfk_hw_init = rtw8922d_rfk_hw_init,
3626 .rfk_init = rtw8922d_rfk_init,
3627 .rfk_init_late = rtw8922d_rfk_init_late,
3628 .rfk_channel = rtw8922d_rfk_channel,
3629 .rfk_band_changed = rtw8922d_rfk_band_changed,
3630 .rfk_scan = rtw8922d_rfk_scan,
3631 .rfk_track = rtw8922d_rfk_track,
3632 .power_trim = rtw8922d_power_trim,
3633 .set_txpwr = rtw8922d_set_txpwr,
3634 .set_txpwr_ctrl = rtw8922d_set_txpwr_ctrl,
3635 .init_txpwr_unit = NULL,
3636 .get_thermal = rtw8922d_get_thermal,
3637 .chan_to_rf18_val = rtw8922d_chan_to_rf18_val,
3638 .ctrl_btg_bt_rx = rtw8922d_set_gbt_bt_rx_sel,
3639 .query_ppdu = rtw8922d_query_ppdu,
3640 .convert_rpl_to_rssi = rtw8922d_convert_rpl_to_rssi,
3641 .phy_rpt_to_rssi = rtw8922d_phy_rpt_to_rssi,
3642 .ctrl_nbtg_bt_tx = rtw8922d_ctrl_nbtg_bt_tx,
3643 .cfg_txrx_path = rtw8922d_bb_cfg_txrx_path,
3644 .set_txpwr_ul_tb_offset = NULL,
3645 .digital_pwr_comp = rtw8922d_digital_pwr_comp,
3646 .calc_rx_gain_normal = rtw8922d_calc_rx_gain_normal,
3647 .path_diff_update = rtw8922d_path_diff_update,
3648 .pwr_on_func = rtw8922d_pwr_on_func,
3649 .pwr_off_func = rtw8922d_pwr_off_func,
3650 .query_rxdesc = rtw89_core_query_rxdesc_v3,
3651 .fill_txdesc = rtw89_core_fill_txdesc_v3,
3652 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2,
3653 .get_ch_dma = {rtw89_core_get_ch_dma_v1,
3654 NULL,
3655 NULL,},
3656 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2,
3657 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v3,
3658 .stop_sch_tx = rtw89_mac_stop_sch_tx_v2,
3659 .resume_sch_tx = rtw89_mac_resume_sch_tx_v2,
3660 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v3,
3661 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl_be,
3662 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl_be,
3663 .h2c_ampdu_cmac_tbl = rtw89_fw_h2c_ampdu_cmac_tbl_be,
3664 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl_be,
3665 .h2c_punctured_cmac_tbl = rtw89_fw_h2c_punctured_cmac_tbl_be,
3666 .h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v3,
3667 .h2c_update_beacon = rtw89_fw_h2c_update_beacon_be,
3668 .h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1,
3669 .h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update_v1,
3670
3671 .btc_set_rfe = rtw8922d_btc_set_rfe,
3672 .btc_init_cfg = rtw8922d_btc_init_cfg,
3673 .btc_set_wl_pri = NULL,
3674 .btc_set_wl_txpwr_ctrl = rtw8922d_btc_set_wl_txpwr_ctrl,
3675 .btc_get_bt_rssi = rtw8922d_btc_get_bt_rssi,
3676 .btc_update_bt_cnt = rtw8922d_btc_update_bt_cnt,
3677 .btc_wl_s1_standby = rtw8922d_btc_wl_s1_standby,
3678 .btc_set_wl_rx_gain = rtw8922d_btc_set_wl_rx_gain,
3679 .btc_set_policy = rtw89_btc_set_policy_v1,
3680 };
3681
3682 const struct rtw89_chip_info rtw8922d_chip_info = {
3683 .chip_id = RTL8922D,
3684 .chip_gen = RTW89_CHIP_BE,
3685 .ops = &rtw8922d_chip_ops,
3686 .mac_def = &rtw89_mac_gen_be,
3687 .phy_def = &rtw89_phy_gen_be_v1,
3688 .fw_def = {
3689 .fw_basename = RTW8922D_FW_BASENAME,
3690 .fw_format_max = RTW8922D_FW_FORMAT_MAX,
3691 .fw_b_aid = RTL8922D_AID7102,
3692 },
3693 .try_ce_fw = false,
3694 .bbmcu_nr = 0,
3695 .needed_fw_elms = RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_V1,
3696 .fw_blacklist = &rtw89_fw_blacklist_default,
3697 .fifo_size = 393216,
3698 .small_fifo_size = false,
3699 .dle_scc_rsvd_size = 0,
3700 .max_amsdu_limit = 11000,
3701 .max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991,
3702 .max_eht_mpdu_cap = IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
3703 .max_tx_agg_num = 128,
3704 .max_rx_agg_num = 256,
3705 .dis_2g_40m_ul_ofdma = false,
3706 .rsvd_ple_ofst = 0x5f800,
3707 .qta_def = {
3708 .hfc_param_ini = {rtw8922d_hfc_param_ini_pcie, NULL, NULL, NULL},
3709 .dle_mem = {rtw8922d_dle_mem_pcie, NULL, NULL, NULL},
3710 },
3711 .wde_qempty_acq_grpnum = 8,
3712 .wde_qempty_mgq_grpsel = 8,
3713 .rf_base_addr = {0x3e000, 0x3f000},
3714 .thermal_th = {0xac, 0xb4},
3715 .pwr_on_seq = NULL,
3716 .pwr_off_seq = NULL,
3717 .bb_table = NULL,
3718 .bb_gain_table = NULL,
3719 .rf_table = {},
3720 .nctl_table = NULL,
3721 .nctl_post_table = &rtw8922d_nctl_post_defs_tbl,
3722 .dflt_parms = NULL, /* load parm from fw */
3723 .rfe_parms_conf = NULL, /* load parm from fw */
3724 .chanctx_listener = &rtw8922d_chanctx_listener,
3725 .txpwr_factor_bb = 3,
3726 .txpwr_factor_rf = 2,
3727 .txpwr_factor_mac = 1,
3728 .dig_table = NULL,
3729 .dig_regs = &rtw8922d_dig_regs,
3730 .tssi_dbw_table = NULL,
3731 .support_macid_num = 64,
3732 .support_link_num = 2,
3733 .support_chanctx_num = 2,
3734 .support_rnr = true,
3735 .support_bands = BIT(NL80211_BAND_2GHZ) |
3736 BIT(NL80211_BAND_5GHZ) |
3737 BIT(NL80211_BAND_6GHZ),
3738 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
3739 BIT(NL80211_CHAN_WIDTH_40) |
3740 BIT(NL80211_CHAN_WIDTH_80) |
3741 BIT(NL80211_CHAN_WIDTH_160),
3742 .support_unii4 = true,
3743 .support_ant_gain = false,
3744 .support_tas = false,
3745 .support_sar_by_ant = true,
3746 .support_noise = false,
3747 .support_fw_cmd_ofld = false,
3748 .ul_tb_waveform_ctrl = false,
3749 .ul_tb_pwr_diff = false,
3750 .rx_freq_from_ie = false,
3751 .hw_sec_hdr = true,
3752 .hw_mgmt_tx_encrypt = true,
3753 .hw_tkip_crypto = true,
3754 .hw_mlo_bmc_crypto = true,
3755 .rf_path_num = 2,
3756 .tx_nss = 2,
3757 .rx_nss = 2,
3758 .acam_num = 128,
3759 .bcam_num = 16,
3760 .scam_num = 32,
3761 .bacam_num = 24,
3762 .bacam_dynamic_num = 8,
3763 .bacam_ver = RTW89_BACAM_V1,
3764 .addrcam_ver = 1,
3765 .ppdu_max_usr = 16,
3766 .sec_ctrl_efuse_size = 4,
3767 .physical_efuse_size = 0x1300,
3768 .logical_efuse_size = 0x70000,
3769 .limit_efuse_size = 0x40000,
3770 .dav_phy_efuse_size = 0,
3771 .dav_log_efuse_size = 0,
3772 .efuse_blocks = rtw8922d_efuse_blocks,
3773 .phycap_addr = 0x1700,
3774 .phycap_size = 0x60,
3775 .para_ver = 0x3ff,
3776 .wlcx_desired = 0x09150000,
3777 .scbd = 0x1,
3778 .mailbox = 0x1,
3779
3780 .afh_guard_ch = 6,
3781 .fdd_iso_freq = 1000,
3782 .wl_rssi_thres = rtw89_btc_8922d_wl_rssi_thres,
3783 .bt_rssi_thres = rtw89_btc_8922d_bt_rssi_thres,
3784 .rssi_tol = 2,
3785 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8922d_mon_reg),
3786 .mon_reg = rtw89_btc_8922d_mon_reg,
3787 .rf_para_ulink_v0 = NULL,
3788 .rf_para_dlink_v0 = NULL,
3789 .rf_para_ulink_num_v0 = 0,
3790 .rf_para_dlink_num_v0 = 0,
3791 .rf_para_ulink_v9 = rtw89_btc_8922d_rf_ul_v9,
3792 .rf_para_dlink_v9 = rtw89_btc_8922d_rf_dl_v9,
3793 .rf_para_ulink_num_v9 = ARRAY_SIZE(rtw89_btc_8922d_rf_ul_v9),
3794 .rf_para_dlink_num_v9 = ARRAY_SIZE(rtw89_btc_8922d_rf_dl_v9),
3795 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3796 BIT(RTW89_PS_MODE_CLK_GATED) |
3797 BIT(RTW89_PS_MODE_PWR_GATED),
3798 .low_power_hci_modes = 0,
3799 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_G7,
3800 .hci_func_en_addr = R_BE_HCI_FUNC_EN,
3801 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short_v3),
3802 .txwd_body_size = sizeof(struct rtw89_txwd_body_v2),
3803 .txwd_info_size = sizeof(struct rtw89_txwd_info_v2),
3804 .h2c_ctrl_reg = R_BE_H2CREG_CTRL,
3805 .h2c_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
3806 .h2c_regs = rtw8922d_h2c_regs,
3807 .c2h_ctrl_reg = R_BE_C2HREG_CTRL,
3808 .c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
3809 .c2h_regs = rtw8922d_c2h_regs,
3810 .page_regs = &rtw8922d_page_regs,
3811 .wow_reason_reg = rtw8922d_wow_wakeup_regs,
3812 .cfo_src_fd = true,
3813 .cfo_hw_comp = true,
3814 .dcfo_comp = NULL,
3815 .dcfo_comp_sft = 0,
3816 .nhm_report = NULL,
3817 .nhm_th = NULL,
3818 .imr_info = NULL,
3819 .imr_dmac_table = &rtw8922d_imr_dmac_table,
3820 .imr_cmac_table = &rtw8922d_imr_cmac_table,
3821 .rrsr_cfgs = &rtw8922d_rrsr_cfgs,
3822 .bss_clr_vld = {R_BSS_CLR_VLD_BE4, B_BSS_CLR_VLD_BE4},
3823 .bss_clr_map_reg = R_BSS_CLR_MAP_BE4,
3824 .rfkill_init = &rtw8922d_rfkill_regs,
3825 .rfkill_get = {R_BE_GPIO_EXT_CTRL, B_BE_GPIO_IN_9},
3826 .btc_sb = {{{R_BE_SCOREBOARD_0, R_BE_SCOREBOARD_0_BT_DATA},
3827 {R_BE_SCOREBOARD_1, R_BE_SCOREBOARD_1_BT_DATA}}},
3828 .dma_ch_mask = BIT(RTW89_DMA_ACH1) | BIT(RTW89_DMA_ACH3) |
3829 BIT(RTW89_DMA_ACH5) | BIT(RTW89_DMA_ACH7) |
3830 BIT(RTW89_DMA_B0HI) | BIT(RTW89_DMA_B1HI),
3831 .edcca_regs = &rtw8922d_edcca_regs,
3832 .pmac_regs = &rtw8922d_pmac_regs,
3833 #ifdef CONFIG_PM
3834 .wowlan_stub = &rtw_wowlan_stub_8922d,
3835 #endif
3836 .xtal_info = NULL,
3837 .default_quirks = BIT(RTW89_QUIRK_THERMAL_PROT_120C),
3838 .txtime_limit_2ghz = 4608,
3839 };
3840 EXPORT_SYMBOL(rtw8922d_chip_info);
3841
3842 static const struct rtw89_fw_def rtw8922de_vs_fw_def = {
3843 .fw_basename = RTW8922DS_FW_BASENAME,
3844 .fw_format_max = RTW8922DS_FW_FORMAT_MAX,
3845 .fw_b_aid = RTL8922D_AID7060,
3846 };
3847
3848 static const struct rtw89_qta_def rtw8922ds_qta_def = {
3849 .hfc_param_ini = {rtw8922ds_hfc_param_ini_pcie, NULL, NULL},
3850 .dle_mem = {rtw8922ds_dle_mem_pcie, NULL, NULL, NULL},
3851 };
3852
3853 const struct rtw89_chip_variant rtw8922de_vs_variant = {
3854 .no_mcs_12_13 = true,
3855 .fw_min_ver_code = RTW89_FW_VER_CODE(0, 0, 0, 0),
3856 .fw_def_override = &rtw8922de_vs_fw_def,
3857 .qta_def_override = &rtw8922ds_qta_def,
3858 };
3859 EXPORT_SYMBOL(rtw8922de_vs_variant);
3860
3861 MODULE_FIRMWARE(RTW8922D_MODULE_FIRMWARE);
3862 MODULE_FIRMWARE(RTW8922DS_MODULE_FIRMWARE);
3863 MODULE_AUTHOR("Realtek Corporation");
3864 MODULE_DESCRIPTION("Realtek 802.11be wireless 8922D driver");
3865 MODULE_LICENSE("Dual BSD/GPL");
3866