1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2024 NanjingTianyihexin Electronics Ltd.
4 * http://www.tianyihexin.com
5 *
6 * Driver for NanjingTianyihexin HX9023S Cap Sensor.
7 * Datasheet available at:
8 * http://www.tianyihexin.com/ueditor/php/upload/file/20240614/1718336303992081.pdf
9 */
10
11 #include <linux/array_size.h>
12 #include <linux/bitfield.h>
13 #include <linux/bitops.h>
14 #include <linux/cleanup.h>
15 #include <linux/device.h>
16 #include <linux/errno.h>
17 #include <linux/firmware.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqreturn.h>
21 #include <linux/math64.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
24 #include <linux/pm.h>
25 #include <linux/property.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/types.h>
29 #include <linux/units.h>
30
31 #include <asm/byteorder.h>
32 #include <linux/unaligned.h>
33
34 #include <linux/iio/buffer.h>
35 #include <linux/iio/events.h>
36 #include <linux/iio/iio.h>
37 #include <linux/iio/trigger.h>
38 #include <linux/iio/triggered_buffer.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/types.h>
41
42 #define HX9023S_CHIP_ID 0x1D
43 #define HX9023S_CH_NUM 5
44 #define HX9023S_POS 0x03
45 #define HX9023S_NEG 0x02
46 #define HX9023S_NOT_CONNECTED 16
47
48 #define HX9023S_GLOBAL_CTRL0 0x00
49 #define HX9023S_PRF_CFG 0x02
50 #define HX9023S_CH0_CFG_7_0 0x03
51 #define HX9023S_CH4_CFG_9_8 0x0C
52 #define HX9023S_RANGE_7_0 0x0D
53 #define HX9023S_RANGE_9_8 0x0E
54 #define HX9023S_RANGE_18_16 0x0F
55 #define HX9023S_AVG0_NOSR0_CFG 0x10
56 #define HX9023S_NOSR12_CFG 0x11
57 #define HX9023S_NOSR34_CFG 0x12
58 #define HX9023S_AVG12_CFG 0x13
59 #define HX9023S_AVG34_CFG 0x14
60 #define HX9023S_OFFSET_DAC0_7_0 0x15
61 #define HX9023S_OFFSET_DAC4_9_8 0x1E
62 #define HX9023S_SAMPLE_NUM_7_0 0x1F
63 #define HX9023S_INTEGRATION_NUM_7_0 0x21
64 #define HX9023S_CH_NUM_CFG 0x24
65 #define HX9023S_LP_ALP_4_CFG 0x29
66 #define HX9023S_LP_ALP_1_0_CFG 0x2A
67 #define HX9023S_LP_ALP_3_2_CFG 0x2B
68 #define HX9023S_UP_ALP_1_0_CFG 0x2C
69 #define HX9023S_UP_ALP_3_2_CFG 0x2D
70 #define HX9023S_DN_UP_ALP_0_4_CFG 0x2E
71 #define HX9023S_DN_ALP_2_1_CFG 0x2F
72 #define HX9023S_DN_ALP_4_3_CFG 0x30
73 #define HX9023S_RAW_BL_RD_CFG 0x38
74 #define HX9023S_INTERRUPT_CFG 0x39
75 #define HX9023S_INTERRUPT_CFG1 0x3A
76 #define HX9023S_CALI_DIFF_CFG 0x3B
77 #define HX9023S_DITHER_CFG 0x3C
78 #define HX9023S_DEVICE_ID 0x60
79 #define HX9023S_PROX_STATUS 0x6B
80 #define HX9023S_PROX_INT_HIGH_CFG 0x6C
81 #define HX9023S_PROX_INT_LOW_CFG 0x6D
82 #define HX9023S_PROX_HIGH_DIFF_CFG_CH0_0 0x80
83 #define HX9023S_PROX_LOW_DIFF_CFG_CH0_0 0x88
84 #define HX9023S_PROX_LOW_DIFF_CFG_CH3_1 0x8F
85 #define HX9023S_PROX_HIGH_DIFF_CFG_CH4_0 0x9E
86 #define HX9023S_PROX_HIGH_DIFF_CFG_CH4_1 0x9F
87 #define HX9023S_PROX_LOW_DIFF_CFG_CH4_0 0xA2
88 #define HX9023S_PROX_LOW_DIFF_CFG_CH4_1 0xA3
89 #define HX9023S_CAP_INI_CH4_0 0xB3
90 #define HX9023S_LP_DIFF_CH4_2 0xBA
91 #define HX9023S_RAW_BL_CH4_0 0xB5
92 #define HX9023S_LP_DIFF_CH4_0 0xB8
93 #define HX9023S_DSP_CONFIG_CTRL1 0xC8
94 #define HX9023S_CAP_INI_CH0_0 0xE0
95 #define HX9023S_RAW_BL_CH0_0 0xE8
96 #define HX9023S_LP_DIFF_CH0_0 0xF4
97 #define HX9023S_LP_DIFF_CH3_2 0xFF
98
99 #define HX9023S_DATA_LOCK_MASK BIT(4)
100 #define HX9023S_INTERRUPT_MASK GENMASK(9, 0)
101 #define HX9023S_PROX_DEBOUNCE_MASK GENMASK(3, 0)
102
103 #define FW_VER_OFFSET 2
104 #define FW_REG_CNT_OFFSET 3
105 #define FW_DATA_OFFSET 16
106
107 struct hx9023s_bin {
108 u16 reg_count;
109 u16 fw_size;
110 u8 fw_ver;
111 u8 data[] __counted_by(fw_size);
112 };
113
114 struct hx9023s_ch_data {
115 s16 raw; /* Raw Data*/
116 s16 lp; /* Low Pass Filter Data*/
117 s16 bl; /* Base Line Data */
118 s16 diff; /* Difference of Low Pass Data and Base Line Data */
119
120 struct {
121 unsigned int near;
122 unsigned int far;
123 } thres;
124
125 u16 dac;
126 u8 channel_positive;
127 u8 channel_negative;
128 bool sel_bl;
129 bool sel_raw;
130 bool sel_diff;
131 bool sel_lp;
132 bool enable;
133 };
134
135 struct hx9023s_data {
136 struct iio_trigger *trig;
137 struct regmap *regmap;
138 unsigned long chan_prox_stat;
139 unsigned long chan_read;
140 unsigned long chan_event;
141 unsigned long ch_en_stat;
142 unsigned long chan_in_use;
143 unsigned int prox_state_reg;
144 bool trigger_enabled;
145
146 struct {
147 __le16 channels[HX9023S_CH_NUM];
148 aligned_s64 ts;
149 } buffer;
150
151 /*
152 * Serialize access to registers below:
153 * HX9023S_PROX_INT_LOW_CFG,
154 * HX9023S_PROX_INT_HIGH_CFG,
155 * HX9023S_INTERRUPT_CFG,
156 * HX9023S_CH_NUM_CFG
157 * Serialize access to channel configuration in
158 * hx9023s_push_events and hx9023s_trigger_handler.
159 */
160 struct mutex mutex;
161 struct hx9023s_ch_data ch_data[HX9023S_CH_NUM];
162 };
163
164 static const struct reg_sequence hx9023s_reg_init_list[] = {
165 /* scan period */
166 REG_SEQ0(HX9023S_PRF_CFG, 0x17),
167
168 /* full scale of conversion phase of each channel */
169 REG_SEQ0(HX9023S_RANGE_7_0, 0x11),
170 REG_SEQ0(HX9023S_RANGE_9_8, 0x02),
171 REG_SEQ0(HX9023S_RANGE_18_16, 0x00),
172
173 /* ADC average number and OSR number of each channel */
174 REG_SEQ0(HX9023S_AVG0_NOSR0_CFG, 0x71),
175 REG_SEQ0(HX9023S_NOSR12_CFG, 0x44),
176 REG_SEQ0(HX9023S_NOSR34_CFG, 0x00),
177 REG_SEQ0(HX9023S_AVG12_CFG, 0x33),
178 REG_SEQ0(HX9023S_AVG34_CFG, 0x00),
179
180 /* sample & integration frequency of the ADC */
181 REG_SEQ0(HX9023S_SAMPLE_NUM_7_0, 0x65),
182 REG_SEQ0(HX9023S_INTEGRATION_NUM_7_0, 0x65),
183
184 /* coefficient of the first order low pass filter during each channel */
185 REG_SEQ0(HX9023S_LP_ALP_1_0_CFG, 0x22),
186 REG_SEQ0(HX9023S_LP_ALP_3_2_CFG, 0x22),
187 REG_SEQ0(HX9023S_LP_ALP_4_CFG, 0x02),
188
189 /* up coefficient of the first order low pass filter during each channel */
190 REG_SEQ0(HX9023S_UP_ALP_1_0_CFG, 0x88),
191 REG_SEQ0(HX9023S_UP_ALP_3_2_CFG, 0x88),
192 REG_SEQ0(HX9023S_DN_UP_ALP_0_4_CFG, 0x18),
193
194 /* down coefficient of the first order low pass filter during each channel */
195 REG_SEQ0(HX9023S_DN_ALP_2_1_CFG, 0x11),
196 REG_SEQ0(HX9023S_DN_ALP_4_3_CFG, 0x11),
197
198 /* selection of data for the Data Mux Register to output data */
199 REG_SEQ0(HX9023S_RAW_BL_RD_CFG, 0xF0),
200
201 /* enable the interrupt function */
202 REG_SEQ0(HX9023S_INTERRUPT_CFG, 0xFF),
203 REG_SEQ0(HX9023S_INTERRUPT_CFG1, 0x3B),
204 REG_SEQ0(HX9023S_DITHER_CFG, 0x21),
205
206 /* threshold of the offset compensation */
207 REG_SEQ0(HX9023S_CALI_DIFF_CFG, 0x07),
208
209 /* proximity persistency number(near & far) */
210 REG_SEQ0(HX9023S_PROX_INT_HIGH_CFG, 0x01),
211 REG_SEQ0(HX9023S_PROX_INT_LOW_CFG, 0x01),
212
213 /* disable the data lock */
214 REG_SEQ0(HX9023S_DSP_CONFIG_CTRL1, 0x00),
215 };
216
217 static const struct iio_event_spec hx9023s_events[] = {
218 {
219 .type = IIO_EV_TYPE_THRESH,
220 .dir = IIO_EV_DIR_RISING,
221 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
222 .mask_separate = BIT(IIO_EV_INFO_VALUE),
223 },
224 {
225 .type = IIO_EV_TYPE_THRESH,
226 .dir = IIO_EV_DIR_FALLING,
227 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
228 .mask_separate = BIT(IIO_EV_INFO_VALUE),
229
230 },
231 {
232 .type = IIO_EV_TYPE_THRESH,
233 .dir = IIO_EV_DIR_EITHER,
234 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
235 },
236 };
237
238 #define HX9023S_CHANNEL(idx) \
239 { \
240 .type = IIO_PROXIMITY, \
241 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
242 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
243 .indexed = 1, \
244 .channel = idx, \
245 .address = 0, \
246 .event_spec = hx9023s_events, \
247 .num_event_specs = ARRAY_SIZE(hx9023s_events), \
248 .scan_index = idx, \
249 .scan_type = { \
250 .sign = 's', \
251 .realbits = 16, \
252 .storagebits = 16, \
253 .endianness = IIO_BE, \
254 }, \
255 }
256
257 static const struct iio_chan_spec hx9023s_channels[] = {
258 HX9023S_CHANNEL(0),
259 HX9023S_CHANNEL(1),
260 HX9023S_CHANNEL(2),
261 HX9023S_CHANNEL(3),
262 HX9023S_CHANNEL(4),
263 IIO_CHAN_SOFT_TIMESTAMP(5),
264 };
265
266 static const unsigned int hx9023s_samp_freq_table[] = {
267 2, 2, 4, 6, 8, 10, 14, 18, 22, 26,
268 30, 34, 38, 42, 46, 50, 56, 62, 68, 74,
269 80, 90, 100, 200, 300, 400, 600, 800, 1000, 2000,
270 3000, 4000,
271 };
272
273 static const struct regmap_range hx9023s_rd_reg_ranges[] = {
274 regmap_reg_range(HX9023S_GLOBAL_CTRL0, HX9023S_LP_DIFF_CH3_2),
275 };
276
277 static const struct regmap_range hx9023s_wr_reg_ranges[] = {
278 regmap_reg_range(HX9023S_GLOBAL_CTRL0, HX9023S_LP_DIFF_CH3_2),
279 };
280
281 static const struct regmap_range hx9023s_volatile_reg_ranges[] = {
282 regmap_reg_range(HX9023S_CAP_INI_CH4_0, HX9023S_LP_DIFF_CH4_2),
283 regmap_reg_range(HX9023S_CAP_INI_CH0_0, HX9023S_LP_DIFF_CH3_2),
284 regmap_reg_range(HX9023S_PROX_STATUS, HX9023S_PROX_STATUS),
285 };
286
287 static const struct regmap_access_table hx9023s_rd_regs = {
288 .yes_ranges = hx9023s_rd_reg_ranges,
289 .n_yes_ranges = ARRAY_SIZE(hx9023s_rd_reg_ranges),
290 };
291
292 static const struct regmap_access_table hx9023s_wr_regs = {
293 .yes_ranges = hx9023s_wr_reg_ranges,
294 .n_yes_ranges = ARRAY_SIZE(hx9023s_wr_reg_ranges),
295 };
296
297 static const struct regmap_access_table hx9023s_volatile_regs = {
298 .yes_ranges = hx9023s_volatile_reg_ranges,
299 .n_yes_ranges = ARRAY_SIZE(hx9023s_volatile_reg_ranges),
300 };
301
302 static const struct regmap_config hx9023s_regmap_config = {
303 .reg_bits = 8,
304 .val_bits = 8,
305 .cache_type = REGCACHE_MAPLE,
306 .rd_table = &hx9023s_rd_regs,
307 .wr_table = &hx9023s_wr_regs,
308 .volatile_table = &hx9023s_volatile_regs,
309 };
310
hx9023s_interrupt_enable(struct hx9023s_data * data)311 static int hx9023s_interrupt_enable(struct hx9023s_data *data)
312 {
313 return regmap_update_bits(data->regmap, HX9023S_INTERRUPT_CFG,
314 HX9023S_INTERRUPT_MASK, HX9023S_INTERRUPT_MASK);
315 }
316
hx9023s_interrupt_disable(struct hx9023s_data * data)317 static int hx9023s_interrupt_disable(struct hx9023s_data *data)
318 {
319 return regmap_update_bits(data->regmap, HX9023S_INTERRUPT_CFG,
320 HX9023S_INTERRUPT_MASK, 0x00);
321 }
322
hx9023s_data_lock(struct hx9023s_data * data,bool locked)323 static int hx9023s_data_lock(struct hx9023s_data *data, bool locked)
324 {
325 if (locked)
326 return regmap_update_bits(data->regmap,
327 HX9023S_DSP_CONFIG_CTRL1,
328 HX9023S_DATA_LOCK_MASK,
329 HX9023S_DATA_LOCK_MASK);
330 else
331 return regmap_update_bits(data->regmap,
332 HX9023S_DSP_CONFIG_CTRL1,
333 HX9023S_DATA_LOCK_MASK, 0);
334 }
335
hx9023s_ch_cfg(struct hx9023s_data * data)336 static int hx9023s_ch_cfg(struct hx9023s_data *data)
337 {
338 __le16 reg_list[HX9023S_CH_NUM];
339 u8 ch_pos[HX9023S_CH_NUM];
340 u8 ch_neg[HX9023S_CH_NUM];
341 /* Bit positions corresponding to input pin connections */
342 u8 conn_cs[HX9023S_CH_NUM] = { 0, 2, 4, 6, 8 };
343 unsigned int i;
344 u16 reg;
345
346 for (i = 0; i < HX9023S_CH_NUM; i++) {
347 ch_pos[i] = data->ch_data[i].channel_positive == HX9023S_NOT_CONNECTED ?
348 HX9023S_NOT_CONNECTED : conn_cs[data->ch_data[i].channel_positive];
349 ch_neg[i] = data->ch_data[i].channel_negative == HX9023S_NOT_CONNECTED ?
350 HX9023S_NOT_CONNECTED : conn_cs[data->ch_data[i].channel_negative];
351
352 reg = (HX9023S_POS << ch_pos[i]) | (HX9023S_NEG << ch_neg[i]);
353 reg_list[i] = cpu_to_le16(reg);
354 }
355
356 return regmap_bulk_write(data->regmap, HX9023S_CH0_CFG_7_0, reg_list,
357 sizeof(reg_list));
358 }
359
hx9023s_write_far_debounce(struct hx9023s_data * data,int val)360 static int hx9023s_write_far_debounce(struct hx9023s_data *data, int val)
361 {
362 guard(mutex)(&data->mutex);
363 return regmap_update_bits(data->regmap, HX9023S_PROX_INT_LOW_CFG,
364 HX9023S_PROX_DEBOUNCE_MASK,
365 FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, val));
366 }
367
hx9023s_write_near_debounce(struct hx9023s_data * data,int val)368 static int hx9023s_write_near_debounce(struct hx9023s_data *data, int val)
369 {
370 guard(mutex)(&data->mutex);
371 return regmap_update_bits(data->regmap, HX9023S_PROX_INT_HIGH_CFG,
372 HX9023S_PROX_DEBOUNCE_MASK,
373 FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, val));
374 }
375
hx9023s_read_far_debounce(struct hx9023s_data * data,int * val)376 static int hx9023s_read_far_debounce(struct hx9023s_data *data, int *val)
377 {
378 int ret;
379
380 ret = regmap_read(data->regmap, HX9023S_PROX_INT_LOW_CFG, val);
381 if (ret)
382 return ret;
383
384 *val = FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, *val);
385
386 return IIO_VAL_INT;
387 }
388
hx9023s_read_near_debounce(struct hx9023s_data * data,int * val)389 static int hx9023s_read_near_debounce(struct hx9023s_data *data, int *val)
390 {
391 int ret;
392
393 ret = regmap_read(data->regmap, HX9023S_PROX_INT_HIGH_CFG, val);
394 if (ret)
395 return ret;
396
397 *val = FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, *val);
398
399 return IIO_VAL_INT;
400 }
401
hx9023s_get_thres_near(struct hx9023s_data * data,u8 ch,int * val)402 static int hx9023s_get_thres_near(struct hx9023s_data *data, u8 ch, int *val)
403 {
404 int ret;
405 __le16 buf;
406 unsigned int reg, tmp;
407
408 reg = (ch == 4) ? HX9023S_PROX_HIGH_DIFF_CFG_CH4_0 :
409 HX9023S_PROX_HIGH_DIFF_CFG_CH0_0 + (ch * 2);
410
411 ret = regmap_bulk_read(data->regmap, reg, &buf, sizeof(buf));
412 if (ret)
413 return ret;
414
415 tmp = (le16_to_cpu(buf) & GENMASK(9, 0)) * 32;
416 data->ch_data[ch].thres.near = tmp;
417 *val = tmp;
418
419 return IIO_VAL_INT;
420 }
421
hx9023s_get_thres_far(struct hx9023s_data * data,u8 ch,int * val)422 static int hx9023s_get_thres_far(struct hx9023s_data *data, u8 ch, int *val)
423 {
424 int ret;
425 __le16 buf;
426 unsigned int reg, tmp;
427
428 reg = (ch == 4) ? HX9023S_PROX_LOW_DIFF_CFG_CH4_0 :
429 HX9023S_PROX_LOW_DIFF_CFG_CH0_0 + (ch * 2);
430
431 ret = regmap_bulk_read(data->regmap, reg, &buf, sizeof(buf));
432 if (ret)
433 return ret;
434
435 tmp = (le16_to_cpu(buf) & GENMASK(9, 0)) * 32;
436 data->ch_data[ch].thres.far = tmp;
437 *val = tmp;
438
439 return IIO_VAL_INT;
440 }
441
hx9023s_set_thres_near(struct hx9023s_data * data,u8 ch,int val)442 static int hx9023s_set_thres_near(struct hx9023s_data *data, u8 ch, int val)
443 {
444 __le16 val_le16 = cpu_to_le16((val / 32) & GENMASK(9, 0));
445 unsigned int reg;
446
447 data->ch_data[ch].thres.near = ((val / 32) & GENMASK(9, 0)) * 32;
448 reg = (ch == 4) ? HX9023S_PROX_HIGH_DIFF_CFG_CH4_0 :
449 HX9023S_PROX_HIGH_DIFF_CFG_CH0_0 + (ch * 2);
450
451 return regmap_bulk_write(data->regmap, reg, &val_le16, sizeof(val_le16));
452 }
453
hx9023s_set_thres_far(struct hx9023s_data * data,u8 ch,int val)454 static int hx9023s_set_thres_far(struct hx9023s_data *data, u8 ch, int val)
455 {
456 __le16 val_le16 = cpu_to_le16((val / 32) & GENMASK(9, 0));
457 unsigned int reg;
458
459 data->ch_data[ch].thres.far = ((val / 32) & GENMASK(9, 0)) * 32;
460 reg = (ch == 4) ? HX9023S_PROX_LOW_DIFF_CFG_CH4_0 :
461 HX9023S_PROX_LOW_DIFF_CFG_CH0_0 + (ch * 2);
462
463 return regmap_bulk_write(data->regmap, reg, &val_le16, sizeof(val_le16));
464 }
465
hx9023s_get_prox_state(struct hx9023s_data * data)466 static int hx9023s_get_prox_state(struct hx9023s_data *data)
467 {
468 return regmap_read(data->regmap, HX9023S_PROX_STATUS, &data->prox_state_reg);
469 }
470
hx9023s_data_select(struct hx9023s_data * data)471 static int hx9023s_data_select(struct hx9023s_data *data)
472 {
473 int ret;
474 unsigned int i, buf;
475 unsigned long tmp;
476
477 ret = regmap_read(data->regmap, HX9023S_RAW_BL_RD_CFG, &buf);
478 if (ret)
479 return ret;
480
481 tmp = buf;
482 for (i = 0; i < 4; i++) {
483 data->ch_data[i].sel_diff = test_bit(i, &tmp);
484 data->ch_data[i].sel_lp = !data->ch_data[i].sel_diff;
485 data->ch_data[i].sel_bl = test_bit(i + 4, &tmp);
486 data->ch_data[i].sel_raw = !data->ch_data[i].sel_bl;
487 }
488
489 ret = regmap_read(data->regmap, HX9023S_INTERRUPT_CFG1, &buf);
490 if (ret)
491 return ret;
492
493 tmp = buf;
494 data->ch_data[4].sel_diff = test_bit(2, &tmp);
495 data->ch_data[4].sel_lp = !data->ch_data[4].sel_diff;
496 data->ch_data[4].sel_bl = test_bit(3, &tmp);
497 data->ch_data[4].sel_raw = !data->ch_data[4].sel_bl;
498
499 return 0;
500 }
501
hx9023s_sample(struct hx9023s_data * data)502 static int hx9023s_sample(struct hx9023s_data *data)
503 {
504 int ret;
505 unsigned int i;
506 u8 buf[HX9023S_CH_NUM * 3];
507 u16 value;
508
509 ret = hx9023s_data_lock(data, true);
510 if (ret)
511 return ret;
512
513 ret = hx9023s_data_select(data);
514 if (ret)
515 goto err;
516
517 /* 3 bytes for each of channels 0 to 3 which have contiguous registers */
518 ret = regmap_bulk_read(data->regmap, HX9023S_RAW_BL_CH0_0, buf, 12);
519 if (ret)
520 goto err;
521
522 /* 3 bytes for channel 4 */
523 ret = regmap_bulk_read(data->regmap, HX9023S_RAW_BL_CH4_0, buf + 12, 3);
524 if (ret)
525 goto err;
526
527 for (i = 0; i < HX9023S_CH_NUM; i++) {
528 value = get_unaligned_le16(&buf[i * 3 + 1]);
529 data->ch_data[i].raw = 0;
530 data->ch_data[i].bl = 0;
531 if (data->ch_data[i].sel_raw)
532 data->ch_data[i].raw = value;
533 if (data->ch_data[i].sel_bl)
534 data->ch_data[i].bl = value;
535 }
536
537 /* 3 bytes for each of channels 0 to 3 which have contiguous registers */
538 ret = regmap_bulk_read(data->regmap, HX9023S_LP_DIFF_CH0_0, buf, 12);
539 if (ret)
540 goto err;
541
542 /* 3 bytes for channel 4 */
543 ret = regmap_bulk_read(data->regmap, HX9023S_LP_DIFF_CH4_0, buf + 12, 3);
544 if (ret)
545 goto err;
546
547 for (i = 0; i < HX9023S_CH_NUM; i++) {
548 value = get_unaligned_le16(&buf[i * 3 + 1]);
549 data->ch_data[i].lp = 0;
550 data->ch_data[i].diff = 0;
551 if (data->ch_data[i].sel_lp)
552 data->ch_data[i].lp = value;
553 if (data->ch_data[i].sel_diff)
554 data->ch_data[i].diff = value;
555 }
556
557 for (i = 0; i < HX9023S_CH_NUM; i++) {
558 if (data->ch_data[i].sel_lp && data->ch_data[i].sel_bl)
559 data->ch_data[i].diff = data->ch_data[i].lp - data->ch_data[i].bl;
560 }
561
562 /* 2 bytes for each of channels 0 to 4 which have contiguous registers */
563 ret = regmap_bulk_read(data->regmap, HX9023S_OFFSET_DAC0_7_0, buf, 10);
564 if (ret)
565 goto err;
566
567 for (i = 0; i < HX9023S_CH_NUM; i++) {
568 value = get_unaligned_le16(&buf[i * 2]);
569 value = FIELD_GET(GENMASK(11, 0), value);
570 data->ch_data[i].dac = value;
571 }
572
573 err:
574 return hx9023s_data_lock(data, false);
575 }
576
hx9023s_ch_en(struct hx9023s_data * data,u8 ch_id,bool en)577 static int hx9023s_ch_en(struct hx9023s_data *data, u8 ch_id, bool en)
578 {
579 int ret;
580 unsigned int buf;
581
582 ret = regmap_read(data->regmap, HX9023S_CH_NUM_CFG, &buf);
583 if (ret)
584 return ret;
585
586 data->ch_en_stat = buf;
587 if (en && data->ch_en_stat == 0)
588 data->prox_state_reg = 0;
589
590 data->ch_data[ch_id].enable = en;
591 __assign_bit(ch_id, &data->ch_en_stat, en);
592
593 return regmap_write(data->regmap, HX9023S_CH_NUM_CFG, data->ch_en_stat);
594 }
595
hx9023s_property_get(struct hx9023s_data * data)596 static int hx9023s_property_get(struct hx9023s_data *data)
597 {
598 struct device *dev = regmap_get_device(data->regmap);
599 u32 array[2];
600 u32 i, reg, temp;
601 int ret;
602
603 data->chan_in_use = 0;
604 for (i = 0; i < HX9023S_CH_NUM; i++) {
605 data->ch_data[i].channel_positive = HX9023S_NOT_CONNECTED;
606 data->ch_data[i].channel_negative = HX9023S_NOT_CONNECTED;
607 }
608
609 device_for_each_child_node_scoped(dev, child) {
610 ret = fwnode_property_read_u32(child, "reg", ®);
611 if (ret || reg >= HX9023S_CH_NUM)
612 return dev_err_probe(dev, ret < 0 ? ret : -EINVAL,
613 "Failed to read reg\n");
614 __set_bit(reg, &data->chan_in_use);
615
616 ret = fwnode_property_read_u32(child, "single-channel", &temp);
617 if (ret == 0) {
618 data->ch_data[reg].channel_positive = temp;
619 data->ch_data[reg].channel_negative = HX9023S_NOT_CONNECTED;
620 } else {
621 ret = fwnode_property_read_u32_array(child, "diff-channels",
622 array, ARRAY_SIZE(array));
623 if (ret == 0) {
624 data->ch_data[reg].channel_positive = array[0];
625 data->ch_data[reg].channel_negative = array[1];
626 } else {
627 return dev_err_probe(dev, ret,
628 "Property read failed: %d\n",
629 reg);
630 }
631 }
632 }
633
634 return 0;
635 }
636
hx9023s_update_chan_en(struct hx9023s_data * data,unsigned long chan_read,unsigned long chan_event)637 static int hx9023s_update_chan_en(struct hx9023s_data *data,
638 unsigned long chan_read,
639 unsigned long chan_event)
640 {
641 unsigned int i;
642 unsigned long channels = chan_read | chan_event;
643
644 if ((data->chan_read | data->chan_event) != channels) {
645 for_each_set_bit(i, &channels, HX9023S_CH_NUM)
646 hx9023s_ch_en(data, i, test_bit(i, &data->chan_in_use));
647 for_each_clear_bit(i, &channels, HX9023S_CH_NUM)
648 hx9023s_ch_en(data, i, false);
649 }
650
651 data->chan_read = chan_read;
652 data->chan_event = chan_event;
653
654 return 0;
655 }
656
hx9023s_get_proximity(struct hx9023s_data * data,const struct iio_chan_spec * chan,int * val)657 static int hx9023s_get_proximity(struct hx9023s_data *data,
658 const struct iio_chan_spec *chan,
659 int *val)
660 {
661 int ret;
662
663 ret = hx9023s_sample(data);
664 if (ret)
665 return ret;
666
667 ret = hx9023s_get_prox_state(data);
668 if (ret)
669 return ret;
670
671 *val = data->ch_data[chan->channel].diff;
672 return IIO_VAL_INT;
673 }
674
hx9023s_get_samp_freq(struct hx9023s_data * data,int * val,int * val2)675 static int hx9023s_get_samp_freq(struct hx9023s_data *data, int *val, int *val2)
676 {
677 int ret;
678 unsigned int odr, index;
679
680 ret = regmap_read(data->regmap, HX9023S_PRF_CFG, &index);
681 if (ret)
682 return ret;
683
684 odr = hx9023s_samp_freq_table[index];
685 *val = KILO / odr;
686 *val2 = div_u64((KILO % odr) * MICRO, odr);
687
688 return IIO_VAL_INT_PLUS_MICRO;
689 }
690
hx9023s_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)691 static int hx9023s_read_raw(struct iio_dev *indio_dev,
692 const struct iio_chan_spec *chan,
693 int *val, int *val2, long mask)
694 {
695 struct hx9023s_data *data = iio_priv(indio_dev);
696 int ret;
697
698 if (chan->type != IIO_PROXIMITY)
699 return -EINVAL;
700
701 switch (mask) {
702 case IIO_CHAN_INFO_RAW:
703 if (!iio_device_claim_direct(indio_dev))
704 return -EBUSY;
705
706 ret = hx9023s_get_proximity(data, chan, val);
707 iio_device_release_direct(indio_dev);
708 return ret;
709 case IIO_CHAN_INFO_SAMP_FREQ:
710 return hx9023s_get_samp_freq(data, val, val2);
711 default:
712 return -EINVAL;
713 }
714 }
715
hx9023s_set_samp_freq(struct hx9023s_data * data,int val,int val2)716 static int hx9023s_set_samp_freq(struct hx9023s_data *data, int val, int val2)
717 {
718 struct device *dev = regmap_get_device(data->regmap);
719 unsigned int i, period_ms;
720
721 if (!val && !val2)
722 return -EINVAL;
723
724 period_ms = div_u64(NANO, (val * MEGA + val2));
725
726 for (i = 0; i < ARRAY_SIZE(hx9023s_samp_freq_table); i++) {
727 if (period_ms == hx9023s_samp_freq_table[i])
728 break;
729 }
730 if (i == ARRAY_SIZE(hx9023s_samp_freq_table)) {
731 dev_err(dev, "Period:%dms NOT found!\n", period_ms);
732 return -EINVAL;
733 }
734
735 return regmap_write(data->regmap, HX9023S_PRF_CFG, i);
736 }
737
hx9023s_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)738 static int hx9023s_write_raw(struct iio_dev *indio_dev,
739 const struct iio_chan_spec *chan,
740 int val, int val2, long mask)
741 {
742 struct hx9023s_data *data = iio_priv(indio_dev);
743
744 if (chan->type != IIO_PROXIMITY)
745 return -EINVAL;
746
747 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
748 return -EINVAL;
749
750 return hx9023s_set_samp_freq(data, val, val2);
751 }
752
hx9023s_irq_handler(int irq,void * private)753 static irqreturn_t hx9023s_irq_handler(int irq, void *private)
754 {
755 struct iio_dev *indio_dev = private;
756 struct hx9023s_data *data = iio_priv(indio_dev);
757
758 if (data->trigger_enabled)
759 iio_trigger_poll(data->trig);
760
761 return IRQ_WAKE_THREAD;
762 }
763
hx9023s_push_events(struct iio_dev * indio_dev)764 static void hx9023s_push_events(struct iio_dev *indio_dev)
765 {
766 struct hx9023s_data *data = iio_priv(indio_dev);
767 s64 timestamp = iio_get_time_ns(indio_dev);
768 unsigned long prox_changed;
769 unsigned int chan;
770 int ret;
771
772 ret = hx9023s_sample(data);
773 if (ret)
774 return;
775
776 ret = hx9023s_get_prox_state(data);
777 if (ret)
778 return;
779
780 prox_changed = (data->chan_prox_stat ^ data->prox_state_reg) & data->chan_event;
781 for_each_set_bit(chan, &prox_changed, HX9023S_CH_NUM) {
782 unsigned int dir;
783
784 dir = (data->prox_state_reg & BIT(chan)) ?
785 IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
786
787 iio_push_event(indio_dev,
788 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
789 IIO_EV_TYPE_THRESH, dir),
790 timestamp);
791 }
792 data->chan_prox_stat = data->prox_state_reg;
793 }
794
hx9023s_irq_thread_handler(int irq,void * private)795 static irqreturn_t hx9023s_irq_thread_handler(int irq, void *private)
796 {
797 struct iio_dev *indio_dev = private;
798 struct hx9023s_data *data = iio_priv(indio_dev);
799
800 guard(mutex)(&data->mutex);
801 hx9023s_push_events(indio_dev);
802
803 return IRQ_HANDLED;
804 }
805
hx9023s_read_event_val(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)806 static int hx9023s_read_event_val(struct iio_dev *indio_dev,
807 const struct iio_chan_spec *chan,
808 enum iio_event_type type,
809 enum iio_event_direction dir,
810 enum iio_event_info info, int *val, int *val2)
811 {
812 struct hx9023s_data *data = iio_priv(indio_dev);
813
814 if (chan->type != IIO_PROXIMITY)
815 return -EINVAL;
816
817 switch (info) {
818 case IIO_EV_INFO_VALUE:
819 switch (dir) {
820 case IIO_EV_DIR_RISING:
821 return hx9023s_get_thres_far(data, chan->channel, val);
822 case IIO_EV_DIR_FALLING:
823 return hx9023s_get_thres_near(data, chan->channel, val);
824 default:
825 return -EINVAL;
826 }
827 case IIO_EV_INFO_PERIOD:
828 switch (dir) {
829 case IIO_EV_DIR_RISING:
830 return hx9023s_read_far_debounce(data, val);
831 case IIO_EV_DIR_FALLING:
832 return hx9023s_read_near_debounce(data, val);
833 default:
834 return -EINVAL;
835 }
836 default:
837 return -EINVAL;
838 }
839 }
840
hx9023s_write_event_val(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)841 static int hx9023s_write_event_val(struct iio_dev *indio_dev,
842 const struct iio_chan_spec *chan,
843 enum iio_event_type type,
844 enum iio_event_direction dir,
845 enum iio_event_info info, int val, int val2)
846 {
847 struct hx9023s_data *data = iio_priv(indio_dev);
848
849 if (chan->type != IIO_PROXIMITY)
850 return -EINVAL;
851
852 switch (info) {
853 case IIO_EV_INFO_VALUE:
854 switch (dir) {
855 case IIO_EV_DIR_RISING:
856 return hx9023s_set_thres_far(data, chan->channel, val);
857 case IIO_EV_DIR_FALLING:
858 return hx9023s_set_thres_near(data, chan->channel, val);
859 default:
860 return -EINVAL;
861 }
862 case IIO_EV_INFO_PERIOD:
863 switch (dir) {
864 case IIO_EV_DIR_RISING:
865 return hx9023s_write_far_debounce(data, val);
866 case IIO_EV_DIR_FALLING:
867 return hx9023s_write_near_debounce(data, val);
868 default:
869 return -EINVAL;
870 }
871 default:
872 return -EINVAL;
873 }
874 }
875
hx9023s_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)876 static int hx9023s_read_event_config(struct iio_dev *indio_dev,
877 const struct iio_chan_spec *chan,
878 enum iio_event_type type,
879 enum iio_event_direction dir)
880 {
881 struct hx9023s_data *data = iio_priv(indio_dev);
882
883 return test_bit(chan->channel, &data->chan_event);
884 }
885
hx9023s_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)886 static int hx9023s_write_event_config(struct iio_dev *indio_dev,
887 const struct iio_chan_spec *chan,
888 enum iio_event_type type,
889 enum iio_event_direction dir,
890 bool state)
891 {
892 struct hx9023s_data *data = iio_priv(indio_dev);
893
894 if (test_bit(chan->channel, &data->chan_in_use)) {
895 hx9023s_ch_en(data, chan->channel, state);
896 __assign_bit(chan->channel, &data->chan_event,
897 data->ch_data[chan->channel].enable);
898 }
899
900 return 0;
901 }
902
903 static const struct iio_info hx9023s_info = {
904 .read_raw = hx9023s_read_raw,
905 .write_raw = hx9023s_write_raw,
906 .read_event_value = hx9023s_read_event_val,
907 .write_event_value = hx9023s_write_event_val,
908 .read_event_config = hx9023s_read_event_config,
909 .write_event_config = hx9023s_write_event_config,
910 };
911
hx9023s_set_trigger_state(struct iio_trigger * trig,bool state)912 static int hx9023s_set_trigger_state(struct iio_trigger *trig, bool state)
913 {
914 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
915 struct hx9023s_data *data = iio_priv(indio_dev);
916
917 guard(mutex)(&data->mutex);
918 if (state)
919 hx9023s_interrupt_enable(data);
920 else if (!data->chan_read)
921 hx9023s_interrupt_disable(data);
922 data->trigger_enabled = state;
923
924 return 0;
925 }
926
927 static const struct iio_trigger_ops hx9023s_trigger_ops = {
928 .set_trigger_state = hx9023s_set_trigger_state,
929 };
930
hx9023s_trigger_handler(int irq,void * private)931 static irqreturn_t hx9023s_trigger_handler(int irq, void *private)
932 {
933 struct iio_poll_func *pf = private;
934 struct iio_dev *indio_dev = pf->indio_dev;
935 struct hx9023s_data *data = iio_priv(indio_dev);
936 struct device *dev = regmap_get_device(data->regmap);
937 unsigned int bit, index, i = 0;
938 int ret;
939
940 guard(mutex)(&data->mutex);
941 ret = hx9023s_sample(data);
942 if (ret) {
943 dev_warn(dev, "sampling failed\n");
944 goto out;
945 }
946
947 ret = hx9023s_get_prox_state(data);
948 if (ret) {
949 dev_warn(dev, "get prox failed\n");
950 goto out;
951 }
952
953 iio_for_each_active_channel(indio_dev, bit) {
954 index = indio_dev->channels[bit].channel;
955 data->buffer.channels[i++] = cpu_to_le16(data->ch_data[index].diff);
956 }
957
958 iio_push_to_buffers_with_ts(indio_dev, &data->buffer,
959 sizeof(data->buffer), pf->timestamp);
960
961 out:
962 iio_trigger_notify_done(indio_dev->trig);
963
964 return IRQ_HANDLED;
965 }
966
hx9023s_buffer_preenable(struct iio_dev * indio_dev)967 static int hx9023s_buffer_preenable(struct iio_dev *indio_dev)
968 {
969 struct hx9023s_data *data = iio_priv(indio_dev);
970 unsigned long channels = 0;
971 unsigned int bit;
972
973 guard(mutex)(&data->mutex);
974 iio_for_each_active_channel(indio_dev, bit)
975 __set_bit(indio_dev->channels[bit].channel, &channels);
976
977 hx9023s_update_chan_en(data, channels, data->chan_event);
978
979 return 0;
980 }
981
hx9023s_buffer_postdisable(struct iio_dev * indio_dev)982 static int hx9023s_buffer_postdisable(struct iio_dev *indio_dev)
983 {
984 struct hx9023s_data *data = iio_priv(indio_dev);
985
986 guard(mutex)(&data->mutex);
987 hx9023s_update_chan_en(data, 0, data->chan_event);
988
989 return 0;
990 }
991
992 static const struct iio_buffer_setup_ops hx9023s_buffer_setup_ops = {
993 .preenable = hx9023s_buffer_preenable,
994 .postdisable = hx9023s_buffer_postdisable,
995 };
996
hx9023s_id_check(struct iio_dev * indio_dev)997 static int hx9023s_id_check(struct iio_dev *indio_dev)
998 {
999 struct hx9023s_data *data = iio_priv(indio_dev);
1000 struct device *dev = regmap_get_device(data->regmap);
1001 unsigned int id;
1002 int ret;
1003
1004 ret = regmap_read(data->regmap, HX9023S_DEVICE_ID, &id);
1005 if (ret)
1006 return ret;
1007
1008 if (id != HX9023S_CHIP_ID)
1009 dev_warn(dev, "Unexpected chip ID, assuming compatible\n");
1010
1011 return 0;
1012 }
1013
hx9023s_bin_load(struct hx9023s_data * data,struct hx9023s_bin * bin)1014 static int hx9023s_bin_load(struct hx9023s_data *data, struct hx9023s_bin *bin)
1015 {
1016 u8 *cfg_start = bin->data + FW_DATA_OFFSET;
1017 u8 addr, val;
1018 u16 i;
1019 int ret;
1020
1021 for (i = 0; i < bin->reg_count; i++) {
1022 addr = cfg_start[i * 2];
1023 val = cfg_start[i * 2 + 1];
1024 ret = regmap_write(data->regmap, addr, val);
1025 if (ret < 0)
1026 return ret;
1027 }
1028
1029 return 0;
1030 }
1031
hx9023s_send_cfg(const struct firmware * fw,struct hx9023s_data * data)1032 static int hx9023s_send_cfg(const struct firmware *fw, struct hx9023s_data *data)
1033 {
1034 struct hx9023s_bin *bin __free(kfree) =
1035 kzalloc(fw->size + sizeof(*bin), GFP_KERNEL);
1036 if (!bin)
1037 return -ENOMEM;
1038
1039 bin->fw_size = fw->size;
1040 memcpy(bin->data, fw->data, bin->fw_size);
1041 bin->fw_ver = bin->data[FW_VER_OFFSET];
1042 bin->reg_count = get_unaligned_le16(bin->data + FW_REG_CNT_OFFSET);
1043
1044 release_firmware(fw);
1045
1046 return hx9023s_bin_load(data, bin);
1047 }
1048
hx9023s_cfg_update(const struct firmware * fw,void * context)1049 static void hx9023s_cfg_update(const struct firmware *fw, void *context)
1050 {
1051 struct hx9023s_data *data = context;
1052 struct device *dev = regmap_get_device(data->regmap);
1053 int ret;
1054
1055 if (!fw || !fw->data) {
1056 dev_warn(dev, "No firmware\n");
1057 goto no_fw;
1058 }
1059
1060 ret = hx9023s_send_cfg(fw, data);
1061 if (ret) {
1062 dev_warn(dev, "Firmware update failed: %d\n", ret);
1063 goto no_fw;
1064 }
1065
1066 ret = regcache_sync(data->regmap);
1067 if (ret)
1068 dev_err(dev, "regcache sync failed\n");
1069
1070 return;
1071
1072 no_fw:
1073 ret = regmap_multi_reg_write(data->regmap, hx9023s_reg_init_list,
1074 ARRAY_SIZE(hx9023s_reg_init_list));
1075 if (ret) {
1076 dev_err(dev, "Error loading default configuration\n");
1077 return;
1078 }
1079
1080 ret = regcache_sync(data->regmap);
1081 if (ret)
1082 dev_err(dev, "regcache sync failed\n");
1083 }
1084
hx9023s_probe(struct i2c_client * client)1085 static int hx9023s_probe(struct i2c_client *client)
1086 {
1087 struct device *dev = &client->dev;
1088 struct iio_dev *indio_dev;
1089 struct hx9023s_data *data;
1090 const char *fw_name;
1091 int ret;
1092
1093 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1094 if (!indio_dev)
1095 return -ENOMEM;
1096
1097 data = iio_priv(indio_dev);
1098 mutex_init(&data->mutex);
1099
1100 data->regmap = devm_regmap_init_i2c(client, &hx9023s_regmap_config);
1101 if (IS_ERR(data->regmap))
1102 return dev_err_probe(dev, PTR_ERR(data->regmap),
1103 "regmap init failed\n");
1104
1105 ret = hx9023s_property_get(data);
1106 if (ret)
1107 return dev_err_probe(dev, ret, "dts phase failed\n");
1108
1109 ret = devm_regulator_get_enable(dev, "vdd");
1110 if (ret)
1111 return dev_err_probe(dev, ret, "regulator get failed\n");
1112
1113 ret = hx9023s_id_check(indio_dev);
1114 if (ret)
1115 return dev_err_probe(dev, ret, "id check failed\n");
1116
1117 indio_dev->name = "hx9023s";
1118 indio_dev->channels = hx9023s_channels;
1119 indio_dev->num_channels = ARRAY_SIZE(hx9023s_channels);
1120 indio_dev->info = &hx9023s_info;
1121 indio_dev->modes = INDIO_DIRECT_MODE;
1122 i2c_set_clientdata(client, indio_dev);
1123
1124 ret = hx9023s_ch_cfg(data);
1125 if (ret)
1126 return dev_err_probe(dev, ret, "channel config failed\n");
1127
1128 fw_name = "hx9023s.bin";
1129 device_property_read_string(dev, "firmware-name", &fw_name);
1130 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, dev,
1131 GFP_KERNEL, data, hx9023s_cfg_update);
1132 if (ret)
1133 return dev_err_probe(dev, ret, "reg config failed\n");
1134
1135 if (client->irq) {
1136 ret = devm_request_threaded_irq(dev, client->irq,
1137 hx9023s_irq_handler,
1138 hx9023s_irq_thread_handler,
1139 IRQF_ONESHOT,
1140 "hx9023s_event", indio_dev);
1141 if (ret)
1142 return ret;
1143
1144 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1145 indio_dev->name,
1146 iio_device_id(indio_dev));
1147 if (!data->trig)
1148 return -ENOMEM;
1149
1150 data->trig->ops = &hx9023s_trigger_ops;
1151 iio_trigger_set_drvdata(data->trig, indio_dev);
1152
1153 ret = devm_iio_trigger_register(dev, data->trig);
1154 if (ret)
1155 return dev_err_probe(dev, ret,
1156 "iio trigger register failed\n");
1157 }
1158
1159 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1160 iio_pollfunc_store_time,
1161 hx9023s_trigger_handler,
1162 &hx9023s_buffer_setup_ops);
1163 if (ret)
1164 return dev_err_probe(dev, ret,
1165 "iio triggered buffer setup failed\n");
1166
1167 return devm_iio_device_register(dev, indio_dev);
1168 }
1169
hx9023s_suspend(struct device * dev)1170 static int hx9023s_suspend(struct device *dev)
1171 {
1172 struct hx9023s_data *data = iio_priv(dev_get_drvdata(dev));
1173
1174 guard(mutex)(&data->mutex);
1175 hx9023s_interrupt_disable(data);
1176
1177 return 0;
1178 }
1179
hx9023s_resume(struct device * dev)1180 static int hx9023s_resume(struct device *dev)
1181 {
1182 struct hx9023s_data *data = iio_priv(dev_get_drvdata(dev));
1183
1184 guard(mutex)(&data->mutex);
1185 if (data->trigger_enabled)
1186 hx9023s_interrupt_enable(data);
1187
1188 return 0;
1189 }
1190
1191 static DEFINE_SIMPLE_DEV_PM_OPS(hx9023s_pm_ops, hx9023s_suspend,
1192 hx9023s_resume);
1193
1194 static const struct of_device_id hx9023s_of_match[] = {
1195 { .compatible = "tyhx,hx9023s" },
1196 { }
1197 };
1198 MODULE_DEVICE_TABLE(of, hx9023s_of_match);
1199
1200 static const struct i2c_device_id hx9023s_id[] = {
1201 { .name = "hx9023s" },
1202 { }
1203 };
1204 MODULE_DEVICE_TABLE(i2c, hx9023s_id);
1205
1206 static struct i2c_driver hx9023s_driver = {
1207 .driver = {
1208 .name = "hx9023s",
1209 .of_match_table = hx9023s_of_match,
1210 .pm = &hx9023s_pm_ops,
1211
1212 /*
1213 * The I2C operations in hx9023s_reg_init() and hx9023s_ch_cfg()
1214 * are time-consuming. Prefer async so we don't delay boot
1215 * if we're builtin to the kernel.
1216 */
1217 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1218 },
1219 .probe = hx9023s_probe,
1220 .id_table = hx9023s_id,
1221 };
1222 module_i2c_driver(hx9023s_driver);
1223
1224 MODULE_AUTHOR("Yasin Lee <yasin.lee.x@gmail.com>");
1225 MODULE_DESCRIPTION("Driver for TYHX HX9023S SAR sensor");
1226 MODULE_LICENSE("GPL");
1227