1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * LiteX LiteSDCard driver
4 *
5 * Copyright (C) 2019-2020 Antmicro <contact@antmicro.com>
6 * Copyright (C) 2019-2020 Kamil Rakoczy <krakoczy@antmicro.com>
7 * Copyright (C) 2019-2020 Maciej Dudek <mdudek@internships.antmicro.com>
8 * Copyright (C) 2020 Paul Mackerras <paulus@ozlabs.org>
9 * Copyright (C) 2020-2022 Gabriel Somlo <gsomlo@gmail.com>
10 */
11
12 #include <linux/bits.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/litex.h>
19 #include <linux/math.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
26 #include <linux/mmc/sd.h>
27
28 #define LITEX_PHY_CARDDETECT 0x00
29 #define LITEX_PHY_CLOCKERDIV 0x04
30 #define LITEX_PHY_INITIALIZE 0x08
31 #define LITEX_PHY_WRITESTATUS 0x0C
32 #define LITEX_CORE_CMDARG 0x00
33 #define LITEX_CORE_CMDCMD 0x04
34 #define LITEX_CORE_CMDSND 0x08
35 #define LITEX_CORE_CMDRSP 0x0C
36 #define LITEX_CORE_CMDEVT 0x1C
37 #define LITEX_CORE_DATEVT 0x20
38 #define LITEX_CORE_BLKLEN 0x24
39 #define LITEX_CORE_BLKCNT 0x28
40 #define LITEX_BLK2MEM_BASE 0x00
41 #define LITEX_BLK2MEM_LEN 0x08
42 #define LITEX_BLK2MEM_ENA 0x0C
43 #define LITEX_BLK2MEM_DONE 0x10
44 #define LITEX_BLK2MEM_LOOP 0x14
45 #define LITEX_MEM2BLK_BASE 0x00
46 #define LITEX_MEM2BLK_LEN 0x08
47 #define LITEX_MEM2BLK_ENA 0x0C
48 #define LITEX_MEM2BLK_DONE 0x10
49 #define LITEX_MEM2BLK_LOOP 0x14
50 #define LITEX_MEM2BLK 0x18
51 #define LITEX_IRQ_STATUS 0x00
52 #define LITEX_IRQ_PENDING 0x04
53 #define LITEX_IRQ_ENABLE 0x08
54
55 #define SD_CTL_DATA_XFER_NONE 0
56 #define SD_CTL_DATA_XFER_READ 1
57 #define SD_CTL_DATA_XFER_WRITE 2
58
59 #define SD_CTL_RESP_NONE 0
60 #define SD_CTL_RESP_SHORT 1
61 #define SD_CTL_RESP_LONG 2
62 #define SD_CTL_RESP_SHORT_BUSY 3
63
64 #define SD_BIT_DONE BIT(0)
65 #define SD_BIT_WR_ERR BIT(1)
66 #define SD_BIT_TIMEOUT BIT(2)
67 #define SD_BIT_CRC_ERR BIT(3)
68
69 #define SD_SLEEP_US 5
70 #define SD_TIMEOUT_US 20000
71
72 #define SD_INIT_DELAY_US 1000
73 #define SD_INIT_CLK_HZ 400000
74
75 #define SDIRQ_CARD_DETECT 1
76 #define SDIRQ_SD_TO_MEM_DONE 2
77 #define SDIRQ_MEM_TO_SD_DONE 4
78 #define SDIRQ_CMD_DONE 8
79
80 struct litex_mmc_host {
81 struct mmc_host *mmc;
82
83 void __iomem *sdphy;
84 void __iomem *sdcore;
85 void __iomem *sdreader;
86 void __iomem *sdwriter;
87 void __iomem *sdirq;
88
89 void *buffer;
90 size_t buf_size;
91 dma_addr_t dma;
92
93 struct completion cmd_done;
94 int irq;
95
96 unsigned int ref_clk;
97 unsigned int sd_clk;
98
99 u32 resp[4];
100 u16 rca;
101
102 bool is_bus_width_set;
103 bool app_cmd;
104 };
105
litex_mmc_sdcard_wait_done(void __iomem * reg,struct device * dev)106 static int litex_mmc_sdcard_wait_done(void __iomem *reg, struct device *dev)
107 {
108 u8 evt;
109 int ret;
110
111 ret = readx_poll_timeout(litex_read8, reg, evt, evt & SD_BIT_DONE,
112 SD_SLEEP_US, SD_TIMEOUT_US);
113 if (ret)
114 return ret;
115 if (evt == SD_BIT_DONE)
116 return 0;
117 if (evt & SD_BIT_WR_ERR)
118 return -EIO;
119 if (evt & SD_BIT_TIMEOUT)
120 return -ETIMEDOUT;
121 if (evt & SD_BIT_CRC_ERR)
122 return -EILSEQ;
123 dev_err(dev, "%s: unknown error (evt=%x)\n", __func__, evt);
124 return -EINVAL;
125 }
126
litex_mmc_send_cmd(struct litex_mmc_host * host,u8 cmd,u32 arg,u8 response_len,u8 transfer)127 static int litex_mmc_send_cmd(struct litex_mmc_host *host,
128 u8 cmd, u32 arg, u8 response_len, u8 transfer)
129 {
130 struct device *dev = mmc_dev(host->mmc);
131 void __iomem *reg;
132 int ret;
133 u8 evt;
134
135 litex_write32(host->sdcore + LITEX_CORE_CMDARG, arg);
136 litex_write32(host->sdcore + LITEX_CORE_CMDCMD,
137 cmd << 8 | transfer << 5 | response_len);
138 litex_write8(host->sdcore + LITEX_CORE_CMDSND, 1);
139
140 /*
141 * Wait for an interrupt if we have an interrupt and either there is
142 * data to be transferred, or if the card can report busy via DAT0.
143 */
144 if (host->irq > 0 &&
145 (transfer != SD_CTL_DATA_XFER_NONE ||
146 response_len == SD_CTL_RESP_SHORT_BUSY)) {
147 reinit_completion(&host->cmd_done);
148 litex_write32(host->sdirq + LITEX_IRQ_ENABLE,
149 SDIRQ_CMD_DONE | SDIRQ_CARD_DETECT);
150 wait_for_completion(&host->cmd_done);
151 }
152
153 ret = litex_mmc_sdcard_wait_done(host->sdcore + LITEX_CORE_CMDEVT, dev);
154 if (ret) {
155 dev_err(dev, "Command (cmd %d) error, status %d\n", cmd, ret);
156 return ret;
157 }
158
159 if (response_len != SD_CTL_RESP_NONE) {
160 /*
161 * NOTE: this matches the semantics of litex_read32()
162 * regardless of underlying arch endianness!
163 */
164 memcpy_fromio(host->resp,
165 host->sdcore + LITEX_CORE_CMDRSP, 0x10);
166 }
167
168 if (!host->app_cmd && cmd == SD_SEND_RELATIVE_ADDR)
169 host->rca = (host->resp[3] >> 16);
170
171 host->app_cmd = (cmd == MMC_APP_CMD);
172
173 if (transfer == SD_CTL_DATA_XFER_NONE)
174 return ret; /* OK from prior litex_mmc_sdcard_wait_done() */
175
176 ret = litex_mmc_sdcard_wait_done(host->sdcore + LITEX_CORE_DATEVT, dev);
177 if (ret) {
178 dev_err(dev, "Data xfer (cmd %d) error, status %d\n", cmd, ret);
179 return ret;
180 }
181
182 /* Wait for completion of (read or write) DMA transfer */
183 reg = (transfer == SD_CTL_DATA_XFER_READ) ?
184 host->sdreader + LITEX_BLK2MEM_DONE :
185 host->sdwriter + LITEX_MEM2BLK_DONE;
186 ret = readx_poll_timeout(litex_read8, reg, evt, evt & SD_BIT_DONE,
187 SD_SLEEP_US, SD_TIMEOUT_US);
188 if (ret)
189 dev_err(dev, "DMA timeout (cmd %d)\n", cmd);
190
191 return ret;
192 }
193
litex_mmc_send_app_cmd(struct litex_mmc_host * host)194 static int litex_mmc_send_app_cmd(struct litex_mmc_host *host)
195 {
196 return litex_mmc_send_cmd(host, MMC_APP_CMD, host->rca << 16,
197 SD_CTL_RESP_SHORT, SD_CTL_DATA_XFER_NONE);
198 }
199
litex_mmc_send_set_bus_w_cmd(struct litex_mmc_host * host,u32 width)200 static int litex_mmc_send_set_bus_w_cmd(struct litex_mmc_host *host, u32 width)
201 {
202 return litex_mmc_send_cmd(host, SD_APP_SET_BUS_WIDTH, width,
203 SD_CTL_RESP_SHORT, SD_CTL_DATA_XFER_NONE);
204 }
205
litex_mmc_set_bus_width(struct litex_mmc_host * host)206 static int litex_mmc_set_bus_width(struct litex_mmc_host *host)
207 {
208 bool app_cmd_sent;
209 int ret;
210
211 if (host->is_bus_width_set)
212 return 0;
213
214 /* Ensure 'app_cmd' precedes 'app_set_bus_width_cmd' */
215 app_cmd_sent = host->app_cmd; /* was preceding command app_cmd? */
216 if (!app_cmd_sent) {
217 ret = litex_mmc_send_app_cmd(host);
218 if (ret)
219 return ret;
220 }
221
222 /* LiteSDCard only supports 4-bit bus width */
223 ret = litex_mmc_send_set_bus_w_cmd(host, MMC_BUS_WIDTH_4);
224 if (ret)
225 return ret;
226
227 /* Re-send 'app_cmd' if necessary */
228 if (app_cmd_sent) {
229 ret = litex_mmc_send_app_cmd(host);
230 if (ret)
231 return ret;
232 }
233
234 host->is_bus_width_set = true;
235
236 return 0;
237 }
238
litex_mmc_get_cd(struct mmc_host * mmc)239 static int litex_mmc_get_cd(struct mmc_host *mmc)
240 {
241 struct litex_mmc_host *host = mmc_priv(mmc);
242 int ret;
243
244 if (!mmc_card_is_removable(mmc))
245 return 1;
246
247 ret = !litex_read8(host->sdphy + LITEX_PHY_CARDDETECT);
248 if (ret)
249 return ret;
250
251 /* Ensure bus width will be set (again) upon card (re)insertion */
252 host->is_bus_width_set = false;
253
254 return 0;
255 }
256
litex_mmc_interrupt(int irq,void * arg)257 static irqreturn_t litex_mmc_interrupt(int irq, void *arg)
258 {
259 struct mmc_host *mmc = arg;
260 struct litex_mmc_host *host = mmc_priv(mmc);
261 u32 pending = litex_read32(host->sdirq + LITEX_IRQ_PENDING);
262 irqreturn_t ret = IRQ_NONE;
263
264 /* Check for card change interrupt */
265 if (pending & SDIRQ_CARD_DETECT) {
266 litex_write32(host->sdirq + LITEX_IRQ_PENDING,
267 SDIRQ_CARD_DETECT);
268 mmc_detect_change(mmc, msecs_to_jiffies(10));
269 ret = IRQ_HANDLED;
270 }
271
272 /* Check for command completed */
273 if (pending & SDIRQ_CMD_DONE) {
274 /* Disable it so it doesn't keep interrupting */
275 litex_write32(host->sdirq + LITEX_IRQ_ENABLE,
276 SDIRQ_CARD_DETECT);
277 complete(&host->cmd_done);
278 ret = IRQ_HANDLED;
279 }
280
281 return ret;
282 }
283
litex_mmc_response_len(struct mmc_command * cmd)284 static u32 litex_mmc_response_len(struct mmc_command *cmd)
285 {
286 if (cmd->flags & MMC_RSP_136)
287 return SD_CTL_RESP_LONG;
288 if (!(cmd->flags & MMC_RSP_PRESENT))
289 return SD_CTL_RESP_NONE;
290 if (cmd->flags & MMC_RSP_BUSY)
291 return SD_CTL_RESP_SHORT_BUSY;
292 return SD_CTL_RESP_SHORT;
293 }
294
litex_mmc_do_dma(struct litex_mmc_host * host,struct mmc_data * data,unsigned int * len,bool * direct,u8 * transfer)295 static void litex_mmc_do_dma(struct litex_mmc_host *host, struct mmc_data *data,
296 unsigned int *len, bool *direct, u8 *transfer)
297 {
298 struct device *dev = mmc_dev(host->mmc);
299 dma_addr_t dma;
300 int sg_count;
301
302 /*
303 * Try to DMA directly to/from the data buffer.
304 * We can do that if the buffer can be mapped for DMA
305 * in one contiguous chunk.
306 */
307 dma = host->dma;
308 *len = data->blksz * data->blocks;
309 sg_count = dma_map_sg(dev, data->sg, data->sg_len,
310 mmc_get_dma_dir(data));
311 if (sg_count == 1) {
312 dma = sg_dma_address(data->sg);
313 *len = sg_dma_len(data->sg);
314 *direct = true;
315 } else if (*len > host->buf_size)
316 *len = host->buf_size;
317
318 if (data->flags & MMC_DATA_READ) {
319 litex_write8(host->sdreader + LITEX_BLK2MEM_ENA, 0);
320 litex_write64(host->sdreader + LITEX_BLK2MEM_BASE, dma);
321 litex_write32(host->sdreader + LITEX_BLK2MEM_LEN, *len);
322 litex_write8(host->sdreader + LITEX_BLK2MEM_ENA, 1);
323 *transfer = SD_CTL_DATA_XFER_READ;
324 } else if (data->flags & MMC_DATA_WRITE) {
325 if (!*direct)
326 sg_copy_to_buffer(data->sg, data->sg_len,
327 host->buffer, *len);
328 litex_write8(host->sdwriter + LITEX_MEM2BLK_ENA, 0);
329 litex_write64(host->sdwriter + LITEX_MEM2BLK_BASE, dma);
330 litex_write32(host->sdwriter + LITEX_MEM2BLK_LEN, *len);
331 litex_write8(host->sdwriter + LITEX_MEM2BLK_ENA, 1);
332 *transfer = SD_CTL_DATA_XFER_WRITE;
333 } else {
334 dev_warn(dev, "Data present w/o read or write flag.\n");
335 /* Continue: set cmd status, mark req done */
336 }
337
338 litex_write16(host->sdcore + LITEX_CORE_BLKLEN, data->blksz);
339 litex_write32(host->sdcore + LITEX_CORE_BLKCNT, data->blocks);
340 }
341
litex_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)342 static void litex_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
343 {
344 struct litex_mmc_host *host = mmc_priv(mmc);
345 struct device *dev = mmc_dev(mmc);
346 struct mmc_command *cmd = mrq->cmd;
347 struct mmc_command *sbc = mrq->sbc;
348 struct mmc_data *data = mrq->data;
349 struct mmc_command *stop = mrq->stop;
350 unsigned int retries = cmd->retries;
351 unsigned int len = 0;
352 bool direct = false;
353 u32 response_len = litex_mmc_response_len(cmd);
354 u8 transfer = SD_CTL_DATA_XFER_NONE;
355
356 /* First check that the card is still there */
357 if (!litex_mmc_get_cd(mmc)) {
358 cmd->error = -ENOMEDIUM;
359 mmc_request_done(mmc, mrq);
360 return;
361 }
362
363 /* Send set-block-count command if needed */
364 if (sbc) {
365 sbc->error = litex_mmc_send_cmd(host, sbc->opcode, sbc->arg,
366 litex_mmc_response_len(sbc),
367 SD_CTL_DATA_XFER_NONE);
368 if (sbc->error) {
369 host->is_bus_width_set = false;
370 mmc_request_done(mmc, mrq);
371 return;
372 }
373 }
374
375 if (data) {
376 /*
377 * LiteSDCard only supports 4-bit bus width; therefore, we MUST
378 * inject a SET_BUS_WIDTH (acmd6) before the very first data
379 * transfer, earlier than when the mmc subsystem would normally
380 * get around to it!
381 */
382 cmd->error = litex_mmc_set_bus_width(host);
383 if (cmd->error) {
384 dev_err(dev, "Can't set bus width!\n");
385 mmc_request_done(mmc, mrq);
386 return;
387 }
388
389 litex_mmc_do_dma(host, data, &len, &direct, &transfer);
390 }
391
392 do {
393 cmd->error = litex_mmc_send_cmd(host, cmd->opcode, cmd->arg,
394 response_len, transfer);
395 } while (cmd->error && retries-- > 0);
396
397 if (cmd->error) {
398 /* Card may be gone; don't assume bus width is still set */
399 host->is_bus_width_set = false;
400 }
401
402 if (response_len == SD_CTL_RESP_SHORT) {
403 /* Pull short response fields from appropriate host registers */
404 cmd->resp[0] = host->resp[3];
405 cmd->resp[1] = host->resp[2] & 0xFF;
406 } else if (response_len == SD_CTL_RESP_LONG) {
407 cmd->resp[0] = host->resp[0];
408 cmd->resp[1] = host->resp[1];
409 cmd->resp[2] = host->resp[2];
410 cmd->resp[3] = host->resp[3];
411 }
412
413 /* Send stop-transmission command if required */
414 if (stop && (cmd->error || !sbc)) {
415 stop->error = litex_mmc_send_cmd(host, stop->opcode, stop->arg,
416 litex_mmc_response_len(stop),
417 SD_CTL_DATA_XFER_NONE);
418 if (stop->error)
419 host->is_bus_width_set = false;
420 }
421
422 if (data) {
423 dma_unmap_sg(dev, data->sg, data->sg_len,
424 mmc_get_dma_dir(data));
425 }
426
427 if (!cmd->error && transfer != SD_CTL_DATA_XFER_NONE) {
428 data->bytes_xfered = min(len, mmc->max_req_size);
429 if (transfer == SD_CTL_DATA_XFER_READ && !direct) {
430 sg_copy_from_buffer(data->sg, sg_nents(data->sg),
431 host->buffer, data->bytes_xfered);
432 }
433 }
434
435 mmc_request_done(mmc, mrq);
436 }
437
litex_mmc_setclk(struct litex_mmc_host * host,unsigned int freq)438 static void litex_mmc_setclk(struct litex_mmc_host *host, unsigned int freq)
439 {
440 struct device *dev = mmc_dev(host->mmc);
441 u32 div;
442
443 div = freq ? DIV_ROUND_UP(host->ref_clk, freq) : 256U;
444 div = clamp(div, 2U, 256U);
445 dev_dbg(dev, "sd_clk_freq=%d: set to %d via div=%d\n",
446 freq, host->ref_clk / ((div + 1) & ~1U), div);
447 litex_write16(host->sdphy + LITEX_PHY_CLOCKERDIV, div);
448 host->sd_clk = freq;
449 }
450
litex_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)451 static void litex_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
452 {
453 struct litex_mmc_host *host = mmc_priv(mmc);
454
455 /*
456 * The SD specification requires at least 74 idle clocks before CMD0.
457 * These dummy cycles is generated by writing LITEX_PHY_INITIALIZE.
458 */
459 if (ios->chip_select == MMC_CS_HIGH) {
460 litex_mmc_setclk(host, SD_INIT_CLK_HZ);
461 litex_write8(host->sdphy + LITEX_PHY_INITIALIZE, 1);
462 fsleep(SD_INIT_DELAY_US);
463 return;
464 }
465
466 /*
467 * NOTE: Ignore any ios->bus_width updates; they occur right after
468 * the mmc core sends its own acmd6 bus-width change notification,
469 * which is redundant since we snoop on the command flow and inject
470 * an early acmd6 before the first data transfer command is sent!
471 */
472
473 /* Update sd_clk */
474 if (ios->clock != host->sd_clk)
475 litex_mmc_setclk(host, ios->clock);
476 }
477
478 static const struct mmc_host_ops litex_mmc_ops = {
479 .get_cd = litex_mmc_get_cd,
480 .request = litex_mmc_request,
481 .set_ios = litex_mmc_set_ios,
482 };
483
litex_mmc_irq_init(struct platform_device * pdev,struct litex_mmc_host * host)484 static int litex_mmc_irq_init(struct platform_device *pdev,
485 struct litex_mmc_host *host)
486 {
487 struct device *dev = mmc_dev(host->mmc);
488 int ret;
489
490 ret = platform_get_irq_optional(pdev, 0);
491 if (ret < 0 && ret != -ENXIO)
492 return ret;
493 if (ret > 0)
494 host->irq = ret;
495 else {
496 dev_warn(dev, "Failed to get IRQ, using polling\n");
497 goto use_polling;
498 }
499
500 host->sdirq = devm_platform_ioremap_resource_byname(pdev, "irq");
501 if (IS_ERR(host->sdirq))
502 return PTR_ERR(host->sdirq);
503
504 ret = devm_request_irq(dev, host->irq, litex_mmc_interrupt, 0,
505 "litex-mmc", host->mmc);
506 if (ret < 0) {
507 dev_warn(dev, "IRQ request error %d, using polling\n", ret);
508 goto use_polling;
509 }
510
511 /* Clear & enable card-change interrupts */
512 litex_write32(host->sdirq + LITEX_IRQ_PENDING, SDIRQ_CARD_DETECT);
513 litex_write32(host->sdirq + LITEX_IRQ_ENABLE, SDIRQ_CARD_DETECT);
514
515 return 0;
516
517 use_polling:
518 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
519 host->irq = 0;
520 return 0;
521 }
522
litex_mmc_probe(struct platform_device * pdev)523 static int litex_mmc_probe(struct platform_device *pdev)
524 {
525 struct device *dev = &pdev->dev;
526 struct litex_mmc_host *host;
527 struct mmc_host *mmc;
528 struct clk *clk;
529 int ret;
530
531 /*
532 * NOTE: defaults to max_[req,seg]_size=PAGE_SIZE, max_blk_size=512,
533 * and max_blk_count accordingly set to 8;
534 * If for some reason we need to modify max_blk_count, we must also
535 * re-calculate `max_[req,seg]_size = max_blk_size * max_blk_count;`
536 */
537 mmc = devm_mmc_alloc_host(dev, sizeof(*host));
538 if (!mmc)
539 return -ENOMEM;
540
541 host = mmc_priv(mmc);
542 host->mmc = mmc;
543
544 /* Initialize clock source */
545 clk = devm_clk_get(dev, NULL);
546 if (IS_ERR(clk))
547 return dev_err_probe(dev, PTR_ERR(clk), "can't get clock\n");
548 host->ref_clk = clk_get_rate(clk);
549 host->sd_clk = 0;
550
551 /*
552 * LiteSDCard only supports 4-bit bus width; therefore, we MUST inject
553 * a SET_BUS_WIDTH (acmd6) before the very first data transfer, earlier
554 * than when the mmc subsystem would normally get around to it!
555 */
556 host->is_bus_width_set = false;
557 host->app_cmd = false;
558
559 /* LiteSDCard can support 64-bit DMA addressing */
560 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
561 if (ret)
562 return ret;
563
564 host->buf_size = mmc->max_req_size * 2;
565 host->buffer = dmam_alloc_coherent(dev, host->buf_size,
566 &host->dma, GFP_KERNEL);
567 if (host->buffer == NULL)
568 return -ENOMEM;
569
570 host->sdphy = devm_platform_ioremap_resource_byname(pdev, "phy");
571 if (IS_ERR(host->sdphy))
572 return PTR_ERR(host->sdphy);
573
574 host->sdcore = devm_platform_ioremap_resource_byname(pdev, "core");
575 if (IS_ERR(host->sdcore))
576 return PTR_ERR(host->sdcore);
577
578 host->sdreader = devm_platform_ioremap_resource_byname(pdev, "reader");
579 if (IS_ERR(host->sdreader))
580 return PTR_ERR(host->sdreader);
581
582 host->sdwriter = devm_platform_ioremap_resource_byname(pdev, "writer");
583 if (IS_ERR(host->sdwriter))
584 return PTR_ERR(host->sdwriter);
585
586 /* Ensure DMA bus masters are disabled */
587 litex_write8(host->sdreader + LITEX_BLK2MEM_ENA, 0);
588 litex_write8(host->sdwriter + LITEX_MEM2BLK_ENA, 0);
589
590 init_completion(&host->cmd_done);
591 ret = litex_mmc_irq_init(pdev, host);
592 if (ret)
593 return ret;
594
595 mmc->ops = &litex_mmc_ops;
596
597 ret = mmc_regulator_get_supply(mmc);
598 if (ret || mmc->ocr_avail == 0) {
599 dev_warn(dev, "can't get voltage, defaulting to 3.3V\n");
600 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
601 }
602
603 /*
604 * Set default sd_clk frequency range based on empirical observations
605 * of LiteSDCard gateware behavior on typical SDCard media
606 */
607 mmc->f_min = 12.5e6;
608 mmc->f_max = 50e6;
609
610 ret = mmc_of_parse(mmc);
611 if (ret)
612 return ret;
613
614 /* Force 4-bit bus_width (only width supported by hardware) */
615 mmc->caps &= ~MMC_CAP_8_BIT_DATA;
616 mmc->caps |= MMC_CAP_4_BIT_DATA;
617
618 /* Set default capabilities */
619 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
620 MMC_CAP_DRIVER_TYPE_D |
621 MMC_CAP_CMD23;
622 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT |
623 MMC_CAP2_NO_SDIO |
624 MMC_CAP2_NO_MMC;
625
626 platform_set_drvdata(pdev, host);
627
628 ret = mmc_add_host(mmc);
629 if (ret)
630 return ret;
631
632 dev_info(dev, "LiteX MMC controller initialized.\n");
633 return 0;
634 }
635
litex_mmc_remove(struct platform_device * pdev)636 static void litex_mmc_remove(struct platform_device *pdev)
637 {
638 struct litex_mmc_host *host = platform_get_drvdata(pdev);
639
640 mmc_remove_host(host->mmc);
641 }
642
643 static const struct of_device_id litex_match[] = {
644 { .compatible = "litex,mmc" },
645 { }
646 };
647 MODULE_DEVICE_TABLE(of, litex_match);
648
649 static struct platform_driver litex_mmc_driver = {
650 .probe = litex_mmc_probe,
651 .remove = litex_mmc_remove,
652 .driver = {
653 .name = "litex-mmc",
654 .of_match_table = litex_match,
655 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
656 },
657 };
658 module_platform_driver(litex_mmc_driver);
659
660 MODULE_DESCRIPTION("LiteX SDCard driver");
661 MODULE_AUTHOR("Antmicro <contact@antmicro.com>");
662 MODULE_AUTHOR("Kamil Rakoczy <krakoczy@antmicro.com>");
663 MODULE_AUTHOR("Maciej Dudek <mdudek@internships.antmicro.com>");
664 MODULE_AUTHOR("Paul Mackerras <paulus@ozlabs.org>");
665 MODULE_AUTHOR("Gabriel Somlo <gsomlo@gmail.com>");
666 MODULE_LICENSE("GPL v2");
667