1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 // Copyright 2018 NXP
3
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/interrupt.h>
8 #include <linux/kobject.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19 #include <linux/dma/imx-dma.h>
20 #include <linux/log2.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26 #include <sound/core.h>
27
28 #include "fsl_micfil.h"
29 #include "fsl_utils.h"
30
31 #define MICFIL_OSR_DEFAULT 16
32
33 #define MICFIL_NUM_RATES 7
34 #define MICFIL_CLK_SRC_NUM 3
35 /* clock source ids */
36 #define MICFIL_AUDIO_PLL1 0
37 #define MICFIL_AUDIO_PLL2 1
38 #define MICFIL_CLK_EXT3 2
39
40 static const unsigned int fsl_micfil_rates[] = {
41 8000, 11025, 16000, 22050, 32000, 44100, 48000,
42 };
43
44 static const struct snd_pcm_hw_constraint_list fsl_micfil_rate_constraints = {
45 .count = ARRAY_SIZE(fsl_micfil_rates),
46 .list = fsl_micfil_rates,
47 };
48
49 enum quality {
50 QUALITY_HIGH,
51 QUALITY_MEDIUM,
52 QUALITY_LOW,
53 QUALITY_VLOW0,
54 QUALITY_VLOW1,
55 QUALITY_VLOW2,
56 };
57
58 struct fsl_micfil {
59 struct platform_device *pdev;
60 struct regmap *regmap;
61 const struct fsl_micfil_soc_data *soc;
62 struct clk *busclk;
63 struct clk *mclk;
64 struct clk *pll8k_clk;
65 struct clk *pll11k_clk;
66 struct clk *clk_src[MICFIL_CLK_SRC_NUM];
67 struct snd_dmaengine_dai_dma_data dma_params_rx;
68 struct sdma_peripheral_config sdmacfg;
69 struct snd_soc_card *card;
70 struct snd_pcm_hw_constraint_list constraint_rates;
71 unsigned int constraint_rates_list[MICFIL_NUM_RATES];
72 unsigned int dataline;
73 char name[32];
74 int irq[MICFIL_IRQ_LINES];
75 enum quality quality;
76 int dc_remover;
77 int dc_out_remover;
78 int vad_init_mode;
79 int vad_enabled;
80 int vad_detected;
81 struct fsl_micfil_verid verid;
82 struct fsl_micfil_param param;
83 bool mclk_flag; /* mclk enable flag */
84 bool dec_bypass;
85 };
86
87 struct fsl_micfil_soc_data {
88 unsigned int fifos;
89 unsigned int fifo_depth;
90 unsigned int dataline;
91 bool imx;
92 bool use_edma;
93 bool use_verid;
94 bool volume_sx;
95 u64 formats;
96 int fifo_offset;
97 enum quality default_quality;
98 /* stores const value in formula to calculate range */
99 int rangeadj_const[3][2];
100 };
101
102 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
103 .imx = true,
104 .fifos = 8,
105 .fifo_depth = 8,
106 .dataline = 0xf,
107 .formats = SNDRV_PCM_FMTBIT_S16_LE,
108 .volume_sx = true,
109 .fifo_offset = 0,
110 .default_quality = QUALITY_VLOW0,
111 };
112
113 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
114 .imx = true,
115 .fifos = 8,
116 .fifo_depth = 32,
117 .dataline = 0xf,
118 .formats = SNDRV_PCM_FMTBIT_S32_LE,
119 .volume_sx = false,
120 .fifo_offset = 0,
121 .default_quality = QUALITY_MEDIUM,
122 .rangeadj_const = {{27, 7}, {27, 7}, {26, 7}},
123 };
124
125 static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
126 .imx = true,
127 .fifos = 8,
128 .fifo_depth = 32,
129 .dataline = 0xf,
130 .formats = SNDRV_PCM_FMTBIT_S32_LE,
131 .use_edma = true,
132 .use_verid = true,
133 .volume_sx = false,
134 .fifo_offset = 0,
135 .default_quality = QUALITY_MEDIUM,
136 .rangeadj_const = {{30, 6}, {30, 6}, {29, 6}},
137 };
138
139 static struct fsl_micfil_soc_data fsl_micfil_imx943 = {
140 .imx = true,
141 .fifos = 8,
142 .fifo_depth = 32,
143 .dataline = 0xf,
144 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_DSD_U32_LE,
145 .use_edma = true,
146 .use_verid = true,
147 .volume_sx = false,
148 .fifo_offset = -4,
149 .default_quality = QUALITY_MEDIUM,
150 .rangeadj_const = {{34, 6}, {34, 6}, {33, 6}},
151 };
152
153 static const struct of_device_id fsl_micfil_dt_ids[] = {
154 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
155 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
156 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
157 { .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 },
158 {}
159 };
160 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
161
162 static const char * const micfil_quality_select_texts[] = {
163 [QUALITY_HIGH] = "High",
164 [QUALITY_MEDIUM] = "Medium",
165 [QUALITY_LOW] = "Low",
166 [QUALITY_VLOW0] = "VLow0",
167 [QUALITY_VLOW1] = "Vlow1",
168 [QUALITY_VLOW2] = "Vlow2",
169 };
170
171 static const struct soc_enum fsl_micfil_quality_enum =
172 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
173 micfil_quality_select_texts);
174
175 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
176
micfil_get_max_range(struct fsl_micfil * micfil)177 static int micfil_get_max_range(struct fsl_micfil *micfil)
178 {
179 int max_range;
180
181 switch (micfil->quality) {
182 case QUALITY_HIGH:
183 case QUALITY_VLOW0:
184 max_range = micfil->soc->rangeadj_const[0][0] - micfil->soc->rangeadj_const[0][1] *
185 ilog2(2 * MICFIL_OSR_DEFAULT);
186 break;
187 case QUALITY_MEDIUM:
188 case QUALITY_VLOW1:
189 max_range = micfil->soc->rangeadj_const[1][0] - micfil->soc->rangeadj_const[1][1] *
190 ilog2(MICFIL_OSR_DEFAULT);
191 break;
192 case QUALITY_LOW:
193 case QUALITY_VLOW2:
194 max_range = micfil->soc->rangeadj_const[2][0] - micfil->soc->rangeadj_const[2][1] *
195 ilog2(MICFIL_OSR_DEFAULT);
196 break;
197 default:
198 return 0;
199 }
200 max_range = max_range < 0 ? 0 : max_range;
201
202 return max_range;
203 }
204
micfil_range_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)205 static int micfil_range_set(struct snd_kcontrol *kcontrol,
206 struct snd_ctl_elem_value *ucontrol)
207 {
208 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
209 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
210 struct soc_mixer_control *mc =
211 (struct soc_mixer_control *)kcontrol->private_value;
212 unsigned int shift = mc->shift;
213 int max_range, new_range;
214 int ret;
215
216 new_range = ucontrol->value.integer.value[0];
217 max_range = micfil_get_max_range(micfil);
218 if (new_range > max_range)
219 dev_warn(&micfil->pdev->dev, "range makes channel %d data unreliable\n", shift / 4);
220
221 ret = pm_runtime_resume_and_get(cmpnt->dev);
222 if (ret)
223 return ret;
224
225 ret = snd_soc_component_update_bits(cmpnt, REG_MICFIL_OUT_CTRL, 0xF << shift,
226 new_range << shift);
227
228 pm_runtime_put_autosuspend(cmpnt->dev);
229
230 return ret;
231 }
232
micfil_set_quality(struct fsl_micfil * micfil)233 static int micfil_set_quality(struct fsl_micfil *micfil)
234 {
235 int range, max_range;
236 u32 qsel, val;
237 int i;
238
239 if (!micfil->soc->volume_sx) {
240 regmap_read(micfil->regmap, REG_MICFIL_OUT_CTRL, &val);
241 max_range = micfil_get_max_range(micfil);
242 for (i = 0; i < micfil->soc->fifos; i++) {
243 range = (val >> MICFIL_OUTGAIN_CHX_SHIFT(i)) & 0xF;
244 if (range > max_range)
245 dev_warn(&micfil->pdev->dev, "please reset channel %d range\n", i);
246 }
247 }
248
249 switch (micfil->quality) {
250 case QUALITY_HIGH:
251 qsel = MICFIL_QSEL_HIGH_QUALITY;
252 break;
253 case QUALITY_MEDIUM:
254 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
255 break;
256 case QUALITY_LOW:
257 qsel = MICFIL_QSEL_LOW_QUALITY;
258 break;
259 case QUALITY_VLOW0:
260 qsel = MICFIL_QSEL_VLOW0_QUALITY;
261 break;
262 case QUALITY_VLOW1:
263 qsel = MICFIL_QSEL_VLOW1_QUALITY;
264 break;
265 case QUALITY_VLOW2:
266 qsel = MICFIL_QSEL_VLOW2_QUALITY;
267 break;
268 default:
269 return -EINVAL;
270 }
271
272 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
273 MICFIL_CTRL2_QSEL,
274 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
275 }
276
micfil_quality_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)277 static int micfil_quality_get(struct snd_kcontrol *kcontrol,
278 struct snd_ctl_elem_value *ucontrol)
279 {
280 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
281 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
282
283 ucontrol->value.integer.value[0] = micfil->quality;
284
285 return 0;
286 }
287
micfil_quality_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)288 static int micfil_quality_set(struct snd_kcontrol *kcontrol,
289 struct snd_ctl_elem_value *ucontrol)
290 {
291 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
292 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
293 int val = ucontrol->value.integer.value[0];
294 bool change = false;
295 int old_val;
296 int ret;
297
298 if (val < QUALITY_HIGH || val > QUALITY_VLOW2)
299 return -EINVAL;
300
301 if (micfil->quality != val) {
302 ret = pm_runtime_resume_and_get(cmpnt->dev);
303 if (ret)
304 return ret;
305
306 old_val = micfil->quality;
307 micfil->quality = val;
308 ret = micfil_set_quality(micfil);
309
310 pm_runtime_put_autosuspend(cmpnt->dev);
311
312 if (ret) {
313 micfil->quality = old_val;
314 return ret;
315 }
316
317 change = true;
318 }
319
320 return change;
321 }
322
323 static const char * const micfil_hwvad_enable[] = {
324 "Disable (Record only)",
325 "Enable (Record with Vad)",
326 };
327
328 static const char * const micfil_hwvad_init_mode[] = {
329 "Envelope mode", "Energy mode",
330 };
331
332 static const char * const micfil_hwvad_hpf_texts[] = {
333 "Filter bypass",
334 "Cut-off @1750Hz",
335 "Cut-off @215Hz",
336 "Cut-off @102Hz",
337 };
338
339 /*
340 * DC Remover Control
341 * Filter Bypassed 1 1
342 * Cut-off @21Hz 0 0
343 * Cut-off @83Hz 0 1
344 * Cut-off @152HZ 1 0
345 */
346 static const char * const micfil_dc_remover_texts[] = {
347 "Cut-off @21Hz", "Cut-off @83Hz",
348 "Cut-off @152Hz", "Bypass",
349 };
350
351 static const char * const micfil_dc_out_remover_texts[] = {
352 "Cut-off @20Hz", "Cut-off @13.3Hz",
353 "Cut-off @40Hz", "Bypass",
354 };
355
356 static const struct soc_enum hwvad_enable_enum =
357 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
358 micfil_hwvad_enable);
359 static const struct soc_enum hwvad_init_mode_enum =
360 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
361 micfil_hwvad_init_mode);
362 static const struct soc_enum hwvad_hpf_enum =
363 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
364 ARRAY_SIZE(micfil_hwvad_hpf_texts),
365 micfil_hwvad_hpf_texts);
366 static const struct soc_enum fsl_micfil_dc_remover_enum =
367 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
368 micfil_dc_remover_texts);
369 static const struct soc_enum fsl_micfil_dc_out_remover_enum =
370 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_out_remover_texts),
371 micfil_dc_out_remover_texts);
372
micfil_put_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)373 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
374 struct snd_ctl_elem_value *ucontrol)
375 {
376 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
377 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
378 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
379 unsigned int *item = ucontrol->value.enumerated.item;
380 int val = snd_soc_enum_item_to_val(e, item[0]);
381 int i = 0, ret = 0;
382 u32 reg_val = 0;
383
384 if (val < 0 || val > 3)
385 return -EINVAL;
386
387 ret = pm_runtime_resume_and_get(comp->dev);
388 if (ret)
389 return ret;
390
391 micfil->dc_remover = val;
392
393 /* Calculate total value for all channels */
394 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
395 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
396
397 /* Update DC Remover mode for all channels */
398 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
399 MICFIL_DC_CTRL_CONFIG, reg_val);
400
401 pm_runtime_put_autosuspend(comp->dev);
402
403 return ret;
404 }
405
micfil_get_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)406 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
408 {
409 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
410 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
411
412 ucontrol->value.enumerated.item[0] = micfil->dc_remover;
413
414 return 0;
415 }
416
micfil_put_dc_out_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)417 static int micfil_put_dc_out_remover_state(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol)
419 {
420 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
421 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
422 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
423 unsigned int *item = ucontrol->value.enumerated.item;
424 int val = snd_soc_enum_item_to_val(e, item[0]);
425 int i = 0, ret = 0;
426 u32 reg_val = 0;
427
428 if (val < 0 || val > 3)
429 return -EINVAL;
430
431 ret = pm_runtime_resume_and_get(comp->dev);
432 if (ret)
433 return ret;
434
435 micfil->dc_out_remover = val;
436
437 /* Calculate total value for all channels */
438 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
439 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
440
441 /* Update DC Remover mode for all channels */
442 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_OUT_CTRL,
443 MICFIL_DC_CTRL_CONFIG, reg_val);
444
445 pm_runtime_put_autosuspend(comp->dev);
446
447 return ret;
448 }
449
micfil_get_dc_out_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)450 static int micfil_get_dc_out_remover_state(struct snd_kcontrol *kcontrol,
451 struct snd_ctl_elem_value *ucontrol)
452 {
453 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
454 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
455
456 ucontrol->value.enumerated.item[0] = micfil->dc_out_remover;
457
458 return 0;
459 }
460
hwvad_put_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)461 static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463 {
464 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
465 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
466 unsigned int *item = ucontrol->value.enumerated.item;
467 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
468 int val = snd_soc_enum_item_to_val(e, item[0]);
469 bool change = false;
470
471 if (val < 0 || val > 1)
472 return -EINVAL;
473
474 change = (micfil->vad_enabled != val);
475 micfil->vad_enabled = val;
476
477 return change;
478 }
479
hwvad_get_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)480 static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
481 struct snd_ctl_elem_value *ucontrol)
482 {
483 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
484 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
485
486 ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
487
488 return 0;
489 }
490
hwvad_put_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)491 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
492 struct snd_ctl_elem_value *ucontrol)
493 {
494 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
495 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
496 unsigned int *item = ucontrol->value.enumerated.item;
497 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
498 int val = snd_soc_enum_item_to_val(e, item[0]);
499 bool change = false;
500
501 if (val < MICFIL_HWVAD_ENVELOPE_MODE || val > MICFIL_HWVAD_ENERGY_MODE)
502 return -EINVAL;
503
504 /* 0 - Envelope-based Mode
505 * 1 - Energy-based Mode
506 */
507 change = (micfil->vad_init_mode != val);
508 micfil->vad_init_mode = val;
509
510 return change;
511 }
512
hwvad_get_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)513 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
514 struct snd_ctl_elem_value *ucontrol)
515 {
516 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
517 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
518
519 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
520
521 return 0;
522 }
523
hwvad_detected(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)524 static int hwvad_detected(struct snd_kcontrol *kcontrol,
525 struct snd_ctl_elem_value *ucontrol)
526 {
527 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
528 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
529
530 ucontrol->value.enumerated.item[0] = micfil->vad_detected;
531
532 return 0;
533 }
534
535 static const struct snd_kcontrol_new fsl_micfil_range_controls[] = {
536 SOC_SINGLE_EXT("CH0 Range", REG_MICFIL_OUT_CTRL,
537 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0,
538 snd_soc_get_volsw, micfil_range_set),
539 SOC_SINGLE_EXT("CH1 Range", REG_MICFIL_OUT_CTRL,
540 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0,
541 snd_soc_get_volsw, micfil_range_set),
542 SOC_SINGLE_EXT("CH2 Range", REG_MICFIL_OUT_CTRL,
543 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0,
544 snd_soc_get_volsw, micfil_range_set),
545 SOC_SINGLE_EXT("CH3 Range", REG_MICFIL_OUT_CTRL,
546 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0,
547 snd_soc_get_volsw, micfil_range_set),
548 SOC_SINGLE_EXT("CH4 Range", REG_MICFIL_OUT_CTRL,
549 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0,
550 snd_soc_get_volsw, micfil_range_set),
551 SOC_SINGLE_EXT("CH5 Range", REG_MICFIL_OUT_CTRL,
552 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0,
553 snd_soc_get_volsw, micfil_range_set),
554 SOC_SINGLE_EXT("CH6 Range", REG_MICFIL_OUT_CTRL,
555 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0,
556 snd_soc_get_volsw, micfil_range_set),
557 SOC_SINGLE_EXT("CH7 Range", REG_MICFIL_OUT_CTRL,
558 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0,
559 snd_soc_get_volsw, micfil_range_set),
560 };
561
562 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
563 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
564 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
565 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
566 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
567 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
568 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
569 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
570 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
571 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
572 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
573 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
574 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
575 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
576 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
577 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
578 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
579 };
580
581 static const struct snd_kcontrol_new fsl_micfil_dc_out_controls[] = {
582 SOC_ENUM_EXT("MICFIL DC Out Remover Control", fsl_micfil_dc_out_remover_enum,
583 micfil_get_dc_out_remover_state, micfil_put_dc_out_remover_state),
584 };
585
586 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
587 SOC_ENUM_EXT("MICFIL Quality Select",
588 fsl_micfil_quality_enum,
589 micfil_quality_get, micfil_quality_set),
590 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
591 hwvad_get_enable, hwvad_put_enable),
592 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
593 hwvad_get_init_mode, hwvad_put_init_mode),
594 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
595 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
596 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
597 REG_MICFIL_VAD0_ZCD, 2, 1, 0),
598 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
599 micfil_get_dc_remover_state, micfil_put_dc_remover_state),
600 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
601 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
602 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
603 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
604 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
605 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
606 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
607 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
608 SOC_SINGLE("HWVAD ZCD And Behavior Switch",
609 REG_MICFIL_VAD0_ZCD, 4, 1, 0),
610 {
611 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
612 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
613 .name = "VAD Detected",
614 .info = snd_soc_info_bool_ext,
615 .get = hwvad_detected,
616 },
617 };
618
fsl_micfil_use_verid(struct device * dev)619 static int fsl_micfil_use_verid(struct device *dev)
620 {
621 struct fsl_micfil *micfil = dev_get_drvdata(dev);
622 unsigned int val;
623 int ret;
624
625 if (!micfil->soc->use_verid)
626 return 0;
627
628 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
629 if (ret < 0)
630 return ret;
631
632 dev_dbg(dev, "VERID: 0x%016X\n", val);
633
634 micfil->verid.version = val &
635 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
636 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
637 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
638
639 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
640 if (ret < 0)
641 return ret;
642
643 dev_dbg(dev, "PARAM: 0x%016X\n", val);
644
645 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
646 MICFIL_PARAM_NUM_HWVAD_SHIFT;
647 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
648 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
649 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
650 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
651 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
652 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
653 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
654 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
655 MICFIL_PARAM_FIFO_PTRWID_SHIFT;
656 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
657 MICFIL_PARAM_NPAIR_SHIFT;
658
659 return 0;
660 }
661
662 /* The SRES is a self-negated bit which provides the CPU with the
663 * capability to initialize the PDM Interface module through the
664 * slave-bus interface. This bit always reads as zero, and this
665 * bit is only effective when MDIS is cleared
666 */
fsl_micfil_reset(struct device * dev)667 static int fsl_micfil_reset(struct device *dev)
668 {
669 struct fsl_micfil *micfil = dev_get_drvdata(dev);
670 int ret;
671
672 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
673 MICFIL_CTRL1_MDIS);
674 if (ret)
675 return ret;
676
677 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
678 MICFIL_CTRL1_SRES);
679 if (ret)
680 return ret;
681
682 /*
683 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
684 * as non-volatile register, so SRES still remain in regmap
685 * cache after set, that every update of REG_MICFIL_CTRL1,
686 * software reset happens. so clear it explicitly.
687 */
688 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
689 MICFIL_CTRL1_SRES);
690 if (ret)
691 return ret;
692
693 /*
694 * Set SRES should clear CHnF flags, But even add delay here
695 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
696 */
697 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
698 if (ret)
699 return ret;
700
701 return 0;
702 }
703
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)704 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
705 struct snd_soc_dai *dai)
706 {
707 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
708
709 if (!micfil) {
710 dev_err(dai->dev, "micfil dai priv_data not set\n");
711 return -EINVAL;
712 }
713
714 if (micfil->constraint_rates.count > 0)
715 snd_pcm_hw_constraint_list(substream->runtime, 0,
716 SNDRV_PCM_HW_PARAM_RATE,
717 &micfil->constraint_rates);
718
719 return 0;
720 }
721
722 /* Enable/disable hwvad interrupts */
fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil * micfil,int enable)723 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
724 {
725 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
726 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
727
728 /* Voice Activity Detector Error Interruption */
729 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
730 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
731
732 /* Voice Activity Detector Interruption */
733 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
734 MICFIL_VAD0_CTRL1_IE, vadie_reg);
735
736 return 0;
737 }
738
739 /* Configuration done only in energy-based initialization mode */
fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil * micfil)740 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
741 {
742 /* Keep the VADFRENDIS bitfield cleared. */
743 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
744 MICFIL_VAD0_CTRL2_FRENDIS);
745
746 /* Keep the VADPREFEN bitfield cleared. */
747 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
748 MICFIL_VAD0_CTRL2_PREFEN);
749
750 /* Keep the VADSFILEN bitfield cleared. */
751 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
752 MICFIL_VAD0_SCONFIG_SFILEN);
753
754 /* Keep the VADSMAXEN bitfield cleared. */
755 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
756 MICFIL_VAD0_SCONFIG_SMAXEN);
757
758 /* Keep the VADNFILAUTO bitfield asserted. */
759 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
760 MICFIL_VAD0_NCONFIG_NFILAUT);
761
762 /* Keep the VADNMINEN bitfield cleared. */
763 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
764 MICFIL_VAD0_NCONFIG_NMINEN);
765
766 /* Keep the VADNDECEN bitfield cleared. */
767 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
768 MICFIL_VAD0_NCONFIG_NDECEN);
769
770 /* Keep the VADNOREN bitfield cleared. */
771 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
772 MICFIL_VAD0_NCONFIG_NOREN);
773
774 return 0;
775 }
776
777 /* Configuration done only in envelope-based initialization mode */
fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil * micfil)778 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
779 {
780 /* Assert the VADFRENDIS bitfield */
781 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
782 MICFIL_VAD0_CTRL2_FRENDIS);
783
784 /* Assert the VADPREFEN bitfield. */
785 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
786 MICFIL_VAD0_CTRL2_PREFEN);
787
788 /* Assert the VADSFILEN bitfield. */
789 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
790 MICFIL_VAD0_SCONFIG_SFILEN);
791
792 /* Assert the VADSMAXEN bitfield. */
793 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
794 MICFIL_VAD0_SCONFIG_SMAXEN);
795
796 /* Clear the VADNFILAUTO bitfield */
797 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
798 MICFIL_VAD0_NCONFIG_NFILAUT);
799
800 /* Assert the VADNMINEN bitfield. */
801 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
802 MICFIL_VAD0_NCONFIG_NMINEN);
803
804 /* Assert the VADNDECEN bitfield. */
805 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
806 MICFIL_VAD0_NCONFIG_NDECEN);
807
808 /* Assert VADNOREN bitfield. */
809 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
810 MICFIL_VAD0_NCONFIG_NOREN);
811
812 return 0;
813 }
814
815 /*
816 * Hardware Voice Active Detection: The HWVAD takes data from the input
817 * of a selected PDM microphone to detect if there is any
818 * voice activity. When a voice activity is detected, an interrupt could
819 * be delivered to the system. Initialization in section 8.4:
820 * Can work in two modes:
821 * -> Eneveope-based mode (section 8.4.1)
822 * -> Energy-based mode (section 8.4.2)
823 *
824 * It is important to remark that the HWVAD detector could be enabled
825 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
826 * bit in STAT register is cleared
827 */
fsl_micfil_hwvad_enable(struct fsl_micfil * micfil)828 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
829 {
830 int ret;
831
832 micfil->vad_detected = 0;
833
834 /* envelope-based specific initialization */
835 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
836 ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
837 else
838 ret = fsl_micfil_init_hwvad_energy_mode(micfil);
839 if (ret)
840 return ret;
841
842 /* Voice Activity Detector Internal Filters Initialization*/
843 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
844 MICFIL_VAD0_CTRL1_ST10);
845
846 /* Voice Activity Detector Internal Filter */
847 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
848 MICFIL_VAD0_CTRL1_ST10);
849
850 /* Enable Interrupts */
851 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
852 if (ret)
853 return ret;
854
855 /* Voice Activity Detector Reset */
856 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
857 MICFIL_VAD0_CTRL1_RST);
858
859 /* Voice Activity Detector Enabled */
860 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
861 MICFIL_VAD0_CTRL1_EN);
862
863 return 0;
864 }
865
fsl_micfil_hwvad_disable(struct fsl_micfil * micfil)866 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
867 {
868 struct device *dev = &micfil->pdev->dev;
869 int ret = 0;
870
871 /* Disable HWVAD */
872 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
873 MICFIL_VAD0_CTRL1_EN);
874
875 /* Disable hwvad interrupts */
876 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
877 if (ret)
878 dev_err(dev, "Failed to disable interrupts\n");
879
880 return ret;
881 }
882
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)883 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
884 struct snd_soc_dai *dai)
885 {
886 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
887 struct device *dev = &micfil->pdev->dev;
888 int ret;
889
890 switch (cmd) {
891 case SNDRV_PCM_TRIGGER_START:
892 case SNDRV_PCM_TRIGGER_RESUME:
893 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
894 ret = fsl_micfil_reset(dev);
895 if (ret) {
896 dev_err(dev, "failed to soft reset\n");
897 return ret;
898 }
899
900 /* DMA Interrupt Selection - DISEL bits
901 * 00 - DMA and IRQ disabled
902 * 01 - DMA req enabled
903 * 10 - IRQ enabled
904 * 11 - reserved
905 */
906 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
907 MICFIL_CTRL1_DISEL,
908 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
909 if (ret)
910 return ret;
911
912 /* Enable the module */
913 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
914 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
915 if (ret)
916 return ret;
917
918 if (micfil->vad_enabled && !micfil->dec_bypass)
919 fsl_micfil_hwvad_enable(micfil);
920
921 break;
922 case SNDRV_PCM_TRIGGER_STOP:
923 case SNDRV_PCM_TRIGGER_SUSPEND:
924 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
925 if (micfil->vad_enabled && !micfil->dec_bypass)
926 fsl_micfil_hwvad_disable(micfil);
927
928 /* Disable the module */
929 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
930 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
931 if (ret)
932 return ret;
933
934 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
935 MICFIL_CTRL1_DISEL,
936 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
937 if (ret)
938 return ret;
939 break;
940 default:
941 return -EINVAL;
942 }
943 return 0;
944 }
945
fsl_micfil_reparent_rootclk(struct fsl_micfil * micfil,unsigned int sample_rate)946 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
947 {
948 struct device *dev = &micfil->pdev->dev;
949 u64 ratio = sample_rate;
950 struct clk *clk;
951 int ret;
952
953 /* Get root clock */
954 clk = micfil->mclk;
955
956 /* Reparent root clock to the PLL matching this sample rate */
957 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
958 micfil->pll11k_clk, ratio);
959
960 /* Enable only once; hw_params can be called multiple times */
961 if (!micfil->mclk_flag) {
962 ret = clk_prepare_enable(clk);
963 if (ret)
964 return ret;
965 micfil->mclk_flag = true;
966 }
967
968 return 0;
969 }
970
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)971 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
972 struct snd_pcm_hw_params *params,
973 struct snd_soc_dai *dai)
974 {
975 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
976 unsigned int channels = params_channels(params);
977 snd_pcm_format_t format = params_format(params);
978 unsigned int rate = params_rate(params);
979 int clk_div = 8, mclk_rate, div_multiply_k;
980 int osr = MICFIL_OSR_DEFAULT;
981 int ret;
982
983 /* 1. Disable the module */
984 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
985 MICFIL_CTRL1_PDMIEN);
986 if (ret)
987 return ret;
988
989 /* enable channels */
990 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
991 0xFF, ((1 << channels) - 1));
992 if (ret)
993 return ret;
994
995 ret = fsl_micfil_reparent_rootclk(micfil, rate);
996 if (ret)
997 return ret;
998
999 /* floor(K * CLKDIV) */
1000 switch (micfil->quality) {
1001 case QUALITY_HIGH:
1002 div_multiply_k = clk_div >> 1;
1003 break;
1004 case QUALITY_LOW:
1005 case QUALITY_VLOW1:
1006 div_multiply_k = clk_div << 1;
1007 break;
1008 case QUALITY_VLOW2:
1009 div_multiply_k = clk_div << 2;
1010 break;
1011 case QUALITY_MEDIUM:
1012 case QUALITY_VLOW0:
1013 default:
1014 div_multiply_k = clk_div;
1015 break;
1016 }
1017
1018 if (format == SNDRV_PCM_FORMAT_DSD_U32_LE) {
1019 micfil->dec_bypass = true;
1020 /*
1021 * According to equation 29 in RM:
1022 * MCLK_CLK_ROOT = PDM CLK rate * 2 * floor(K * CLKDIV)
1023 * PDM CLK rate = rate * physical bit width (32)
1024 */
1025 mclk_rate = rate * div_multiply_k * 32 * 2;
1026 } else {
1027 micfil->dec_bypass = false;
1028 mclk_rate = rate * clk_div * osr * 8;
1029 }
1030
1031 ret = clk_set_rate(micfil->mclk, mclk_rate);
1032 if (ret)
1033 return ret;
1034
1035 ret = micfil_set_quality(micfil);
1036 if (ret)
1037 return ret;
1038
1039 regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
1040 MICFIL_CTRL2_DEC_BYPASS,
1041 micfil->dec_bypass ? MICFIL_CTRL2_DEC_BYPASS : 0);
1042
1043 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
1044 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
1045 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
1046 FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr));
1047
1048 /* Configure CIC OSR in VADCICOSR */
1049 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
1050 MICFIL_VAD0_CTRL1_CICOSR,
1051 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
1052
1053 /* Configure source channel in VADCHSEL */
1054 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
1055 MICFIL_VAD0_CTRL1_CHSEL,
1056 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
1057
1058 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
1059 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
1060 micfil->sdmacfg.n_fifos_src = channels;
1061 micfil->sdmacfg.sw_done = true;
1062 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
1063 if (micfil->soc->use_edma)
1064 micfil->dma_params_rx.maxburst = channels;
1065
1066 return 0;
1067 }
1068
fsl_micfil_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1069 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream,
1070 struct snd_soc_dai *dai)
1071 {
1072 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
1073
1074 if (micfil->mclk_flag) {
1075 clk_disable_unprepare(micfil->mclk);
1076 micfil->mclk_flag = false;
1077 }
1078
1079 return 0;
1080 }
1081
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)1082 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
1083 {
1084 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
1085 struct device *dev = cpu_dai->dev;
1086 unsigned int val = 0;
1087 int ret, i, max_range;
1088
1089 micfil->quality = micfil->soc->default_quality;
1090 micfil->card = cpu_dai->component->card;
1091
1092 /* set default gain to 2 */
1093 if (micfil->soc->volume_sx) {
1094 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
1095 } else {
1096 max_range = micfil_get_max_range(micfil);
1097 for (i = 1; i < micfil->soc->fifos; i++)
1098 max_range |= max_range << 4;
1099 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, max_range);
1100 }
1101
1102 /* set DC Remover in bypass mode*/
1103 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
1104 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
1105 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
1106 MICFIL_DC_CTRL_CONFIG, val);
1107 if (ret) {
1108 dev_err(dev, "failed to set DC Remover mode bits\n");
1109 return ret;
1110 }
1111 micfil->dc_remover = MICFIL_DC_BYPASS;
1112
1113 if (micfil->soc->use_verid) {
1114 val = 0;
1115 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
1116 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
1117 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_OUT_CTRL,
1118 MICFIL_DC_CTRL_CONFIG, val);
1119 if (ret) {
1120 dev_err(dev, "failed to set DC OUT Remover mode bits\n");
1121 return ret;
1122 }
1123 micfil->dc_out_remover = MICFIL_DC_BYPASS;
1124 }
1125
1126 snd_soc_dai_init_dma_data(cpu_dai, NULL,
1127 &micfil->dma_params_rx);
1128
1129 /* FIFO Watermark Control - FIFOWMK*/
1130 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
1131 MICFIL_FIFO_CTRL_FIFOWMK,
1132 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
1133 if (ret)
1134 return ret;
1135
1136 return 0;
1137 }
1138
fsl_micfil_component_probe(struct snd_soc_component * component)1139 static int fsl_micfil_component_probe(struct snd_soc_component *component)
1140 {
1141 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);
1142
1143 if (micfil->soc->volume_sx)
1144 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,
1145 ARRAY_SIZE(fsl_micfil_volume_sx_controls));
1146 else
1147 snd_soc_add_component_controls(component, fsl_micfil_range_controls,
1148 ARRAY_SIZE(fsl_micfil_range_controls));
1149
1150 if (micfil->soc->use_verid)
1151 snd_soc_add_component_controls(component, fsl_micfil_dc_out_controls,
1152 ARRAY_SIZE(fsl_micfil_dc_out_controls));
1153
1154 return 0;
1155 }
1156
1157 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
1158 .probe = fsl_micfil_dai_probe,
1159 .startup = fsl_micfil_startup,
1160 .trigger = fsl_micfil_trigger,
1161 .hw_params = fsl_micfil_hw_params,
1162 .hw_free = fsl_micfil_hw_free,
1163 };
1164
1165 static struct snd_soc_dai_driver fsl_micfil_dai = {
1166 .capture = {
1167 .stream_name = "CPU-Capture",
1168 .channels_min = 1,
1169 .channels_max = 8,
1170 .rates = SNDRV_PCM_RATE_8000_48000,
1171 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1172 },
1173 .ops = &fsl_micfil_dai_ops,
1174 };
1175
1176 static const struct snd_soc_component_driver fsl_micfil_component = {
1177 .name = "fsl-micfil-dai",
1178 .probe = fsl_micfil_component_probe,
1179 .controls = fsl_micfil_snd_controls,
1180 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
1181 .legacy_dai_naming = 1,
1182 };
1183
1184 /* REGMAP */
1185 static const struct reg_default fsl_micfil_reg_defaults[] = {
1186 {REG_MICFIL_CTRL1, 0x00000000},
1187 {REG_MICFIL_CTRL2, 0x00000000},
1188 {REG_MICFIL_STAT, 0x00000000},
1189 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
1190 {REG_MICFIL_FIFO_STAT, 0x00000000},
1191 {REG_MICFIL_DATACH0, 0x00000000},
1192 {REG_MICFIL_DATACH1, 0x00000000},
1193 {REG_MICFIL_DATACH2, 0x00000000},
1194 {REG_MICFIL_DATACH3, 0x00000000},
1195 {REG_MICFIL_DATACH4, 0x00000000},
1196 {REG_MICFIL_DATACH5, 0x00000000},
1197 {REG_MICFIL_DATACH6, 0x00000000},
1198 {REG_MICFIL_DATACH7, 0x00000000},
1199 {REG_MICFIL_DC_CTRL, 0x00000000},
1200 {REG_MICFIL_DC_OUT_CTRL, 0x00000000},
1201 {REG_MICFIL_OUT_CTRL, 0x00000000},
1202 {REG_MICFIL_OUT_STAT, 0x00000000},
1203 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
1204 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
1205 {REG_MICFIL_VAD0_STAT, 0x00000000},
1206 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
1207 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
1208 {REG_MICFIL_VAD0_NDATA, 0x00000000},
1209 {REG_MICFIL_VAD0_ZCD, 0x00000004},
1210 };
1211
1212 static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
1213 {REG_MICFIL_CTRL1, 0x00000000},
1214 {REG_MICFIL_CTRL2, 0x00000000},
1215 {REG_MICFIL_STAT, 0x00000000},
1216 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
1217 {REG_MICFIL_FIFO_STAT, 0x00000000},
1218 {REG_MICFIL_DATACH0 - 0x4, 0x00000000},
1219 {REG_MICFIL_DATACH1 - 0x4, 0x00000000},
1220 {REG_MICFIL_DATACH2 - 0x4, 0x00000000},
1221 {REG_MICFIL_DATACH3 - 0x4, 0x00000000},
1222 {REG_MICFIL_DATACH4 - 0x4, 0x00000000},
1223 {REG_MICFIL_DATACH5 - 0x4, 0x00000000},
1224 {REG_MICFIL_DATACH6 - 0x4, 0x00000000},
1225 {REG_MICFIL_DATACH7 - 0x4, 0x00000000},
1226 {REG_MICFIL_DC_CTRL, 0x00000000},
1227 {REG_MICFIL_DC_OUT_CTRL, 0x00000000},
1228 {REG_MICFIL_OUT_CTRL, 0x00000000},
1229 {REG_MICFIL_OUT_STAT, 0x00000000},
1230 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
1231 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
1232 {REG_MICFIL_VAD0_STAT, 0x00000000},
1233 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
1234 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
1235 {REG_MICFIL_VAD0_NDATA, 0x00000000},
1236 {REG_MICFIL_VAD0_ZCD, 0x00000004},
1237 };
1238
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)1239 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
1240 {
1241 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1242 int ofs = micfil->soc->fifo_offset;
1243
1244 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1245 return true;
1246
1247 switch (reg) {
1248 case REG_MICFIL_CTRL1:
1249 case REG_MICFIL_CTRL2:
1250 case REG_MICFIL_STAT:
1251 case REG_MICFIL_FIFO_CTRL:
1252 case REG_MICFIL_FIFO_STAT:
1253 case REG_MICFIL_DC_CTRL:
1254 case REG_MICFIL_OUT_CTRL:
1255 case REG_MICFIL_OUT_STAT:
1256 case REG_MICFIL_VAD0_CTRL1:
1257 case REG_MICFIL_VAD0_CTRL2:
1258 case REG_MICFIL_VAD0_STAT:
1259 case REG_MICFIL_VAD0_SCONFIG:
1260 case REG_MICFIL_VAD0_NCONFIG:
1261 case REG_MICFIL_VAD0_NDATA:
1262 case REG_MICFIL_VAD0_ZCD:
1263 return true;
1264 case REG_MICFIL_DC_OUT_CTRL:
1265 case REG_MICFIL_FSYNC_CTRL:
1266 case REG_MICFIL_VERID:
1267 case REG_MICFIL_PARAM:
1268 if (micfil->soc->use_verid)
1269 return true;
1270 fallthrough;
1271 default:
1272 return false;
1273 }
1274 }
1275
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)1276 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
1277 {
1278 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1279
1280 switch (reg) {
1281 case REG_MICFIL_CTRL1:
1282 case REG_MICFIL_CTRL2:
1283 case REG_MICFIL_STAT: /* Write 1 to Clear */
1284 case REG_MICFIL_FIFO_CTRL:
1285 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
1286 case REG_MICFIL_DC_CTRL:
1287 case REG_MICFIL_OUT_CTRL:
1288 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
1289 case REG_MICFIL_VAD0_CTRL1:
1290 case REG_MICFIL_VAD0_CTRL2:
1291 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
1292 case REG_MICFIL_VAD0_SCONFIG:
1293 case REG_MICFIL_VAD0_NCONFIG:
1294 case REG_MICFIL_VAD0_ZCD:
1295 return true;
1296 case REG_MICFIL_DC_OUT_CTRL:
1297 case REG_MICFIL_FSYNC_CTRL:
1298 if (micfil->soc->use_verid)
1299 return true;
1300 fallthrough;
1301 default:
1302 return false;
1303 }
1304 }
1305
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)1306 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
1307 {
1308 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1309 int ofs = micfil->soc->fifo_offset;
1310
1311 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1312 return true;
1313
1314 switch (reg) {
1315 case REG_MICFIL_STAT:
1316 case REG_MICFIL_FIFO_STAT:
1317 case REG_MICFIL_OUT_STAT:
1318 case REG_MICFIL_VERID:
1319 case REG_MICFIL_PARAM:
1320 case REG_MICFIL_VAD0_STAT:
1321 case REG_MICFIL_VAD0_NDATA:
1322 return true;
1323 default:
1324 return false;
1325 }
1326 }
1327
1328 static const struct regmap_config fsl_micfil_regmap_config = {
1329 .reg_bits = 32,
1330 .reg_stride = 4,
1331 .val_bits = 32,
1332
1333 .max_register = REG_MICFIL_VAD0_ZCD,
1334 .reg_defaults = fsl_micfil_reg_defaults,
1335 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1336 .readable_reg = fsl_micfil_readable_reg,
1337 .volatile_reg = fsl_micfil_volatile_reg,
1338 .writeable_reg = fsl_micfil_writeable_reg,
1339 .cache_type = REGCACHE_MAPLE,
1340 };
1341
1342 static const struct regmap_config fsl_micfil_regmap_config_v2 = {
1343 .reg_bits = 32,
1344 .reg_stride = 4,
1345 .val_bits = 32,
1346
1347 .max_register = REG_MICFIL_VAD0_ZCD,
1348 .reg_defaults = fsl_micfil_reg_defaults_v2,
1349 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2),
1350 .readable_reg = fsl_micfil_readable_reg,
1351 .volatile_reg = fsl_micfil_volatile_reg,
1352 .writeable_reg = fsl_micfil_writeable_reg,
1353 .cache_type = REGCACHE_MAPLE,
1354 };
1355
1356 /* END OF REGMAP */
1357
micfil_isr(int irq,void * devid)1358 static irqreturn_t micfil_isr(int irq, void *devid)
1359 {
1360 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1361 struct platform_device *pdev = micfil->pdev;
1362 u32 stat_reg;
1363 u32 fifo_stat_reg;
1364 u32 ctrl1_reg;
1365 bool dma_enabled;
1366 int i;
1367
1368 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1369 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
1370 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1371
1372 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
1373
1374 /* Channel 0-7 Output Data Flags */
1375 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
1376 if (stat_reg & MICFIL_STAT_CHXF(i))
1377 dev_dbg(&pdev->dev,
1378 "Data available in Data Channel %d\n", i);
1379 /* if DMA is not enabled, field must be written with 1
1380 * to clear
1381 */
1382 if (!dma_enabled)
1383 regmap_write_bits(micfil->regmap,
1384 REG_MICFIL_STAT,
1385 MICFIL_STAT_CHXF(i),
1386 MICFIL_STAT_CHXF(i));
1387 }
1388
1389 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
1390 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
1391 dev_dbg(&pdev->dev,
1392 "FIFO Overflow Exception flag for channel %d\n",
1393 i);
1394
1395 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
1396 dev_dbg(&pdev->dev,
1397 "FIFO Underflow Exception flag for channel %d\n",
1398 i);
1399 }
1400
1401 return IRQ_HANDLED;
1402 }
1403
micfil_err_isr(int irq,void * devid)1404 static irqreturn_t micfil_err_isr(int irq, void *devid)
1405 {
1406 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1407 struct platform_device *pdev = micfil->pdev;
1408 u32 fifo_stat_reg;
1409 u32 out_stat_reg;
1410 u32 stat_reg;
1411
1412 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1413
1414 if (stat_reg & MICFIL_STAT_BSY_FIL)
1415 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1416
1417 if (stat_reg & MICFIL_STAT_FIR_RDY)
1418 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1419
1420 if (stat_reg & MICFIL_STAT_LOWFREQF) {
1421 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1422 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1423 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
1424 }
1425
1426 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1427 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT,
1428 fifo_stat_reg, fifo_stat_reg);
1429
1430 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg);
1431 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT,
1432 out_stat_reg, out_stat_reg);
1433
1434 return IRQ_HANDLED;
1435 }
1436
voice_detected_fn(int irq,void * devid)1437 static irqreturn_t voice_detected_fn(int irq, void *devid)
1438 {
1439 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1440 struct snd_kcontrol *kctl;
1441
1442 if (!micfil->card)
1443 return IRQ_HANDLED;
1444
1445 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1446 if (!kctl)
1447 return IRQ_HANDLED;
1448
1449 if (micfil->vad_detected)
1450 snd_ctl_notify(micfil->card->snd_card,
1451 SNDRV_CTL_EVENT_MASK_VALUE,
1452 &kctl->id);
1453
1454 return IRQ_HANDLED;
1455 }
1456
hwvad_isr(int irq,void * devid)1457 static irqreturn_t hwvad_isr(int irq, void *devid)
1458 {
1459 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1460 struct device *dev = &micfil->pdev->dev;
1461 u32 vad0_reg;
1462 int ret;
1463
1464 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1465
1466 /*
1467 * The only difference between MICFIL_VAD0_STAT_EF and
1468 * MICFIL_VAD0_STAT_IF is that the former requires Write
1469 * 1 to Clear. Since both flags are set, it is enough
1470 * to only read one of them
1471 */
1472 if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1473 /* Write 1 to clear */
1474 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1475 MICFIL_VAD0_STAT_IF,
1476 MICFIL_VAD0_STAT_IF);
1477
1478 micfil->vad_detected = 1;
1479 }
1480
1481 ret = fsl_micfil_hwvad_disable(micfil);
1482 if (ret)
1483 dev_err(dev, "Failed to disable hwvad\n");
1484
1485 return IRQ_WAKE_THREAD;
1486 }
1487
hwvad_err_isr(int irq,void * devid)1488 static irqreturn_t hwvad_err_isr(int irq, void *devid)
1489 {
1490 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1491 struct device *dev = &micfil->pdev->dev;
1492 u32 vad0_reg;
1493
1494 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1495
1496 if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1497 dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1498
1499 return IRQ_HANDLED;
1500 }
1501
1502 static int fsl_micfil_runtime_suspend(struct device *dev);
1503 static int fsl_micfil_runtime_resume(struct device *dev);
1504
fsl_micfil_probe(struct platform_device * pdev)1505 static int fsl_micfil_probe(struct platform_device *pdev)
1506 {
1507 struct device_node *np = pdev->dev.of_node;
1508 struct fsl_micfil *micfil;
1509 struct resource *res;
1510 void __iomem *regs;
1511 int ret, i;
1512
1513 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1514 if (!micfil)
1515 return -ENOMEM;
1516
1517 micfil->pdev = pdev;
1518 strscpy(micfil->name, np->name, sizeof(micfil->name));
1519
1520 micfil->soc = of_device_get_match_data(&pdev->dev);
1521
1522 /* ipg_clk is used to control the registers
1523 * ipg_clk_app is used to operate the filter
1524 */
1525 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1526 if (IS_ERR(micfil->mclk)) {
1527 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1528 PTR_ERR(micfil->mclk));
1529 return PTR_ERR(micfil->mclk);
1530 }
1531
1532 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1533 if (IS_ERR(micfil->busclk)) {
1534 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1535 PTR_ERR(micfil->busclk));
1536 return PTR_ERR(micfil->busclk);
1537 }
1538
1539 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1540 &micfil->pll11k_clk);
1541
1542 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;
1543 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;
1544 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");
1545 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))
1546 micfil->clk_src[MICFIL_CLK_EXT3] = NULL;
1547
1548 fsl_asoc_constrain_rates(&micfil->constraint_rates,
1549 &fsl_micfil_rate_constraints,
1550 micfil->clk_src[MICFIL_AUDIO_PLL1],
1551 micfil->clk_src[MICFIL_AUDIO_PLL2],
1552 micfil->clk_src[MICFIL_CLK_EXT3],
1553 micfil->constraint_rates_list);
1554
1555 /* init regmap */
1556 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1557 if (IS_ERR(regs))
1558 return PTR_ERR(regs);
1559
1560 if (of_device_is_compatible(np, "fsl,imx943-micfil"))
1561 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1562 regs,
1563 &fsl_micfil_regmap_config_v2);
1564 else
1565 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1566 regs,
1567 &fsl_micfil_regmap_config);
1568 if (IS_ERR(micfil->regmap)) {
1569 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1570 PTR_ERR(micfil->regmap));
1571 return PTR_ERR(micfil->regmap);
1572 }
1573
1574 /* dataline mask for RX */
1575 ret = of_property_read_u32_index(np,
1576 "fsl,dataline",
1577 0,
1578 &micfil->dataline);
1579 if (ret)
1580 micfil->dataline = 1;
1581
1582 if (micfil->dataline & ~micfil->soc->dataline) {
1583 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1584 micfil->soc->dataline);
1585 return -EINVAL;
1586 }
1587
1588 /* get IRQs */
1589 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1590 micfil->irq[i] = platform_get_irq(pdev, i);
1591 if (micfil->irq[i] < 0)
1592 return micfil->irq[i];
1593 }
1594
1595 /* Digital Microphone interface interrupt */
1596 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1597 micfil_isr, IRQF_SHARED,
1598 micfil->name, micfil);
1599 if (ret) {
1600 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1601 micfil->irq[0]);
1602 return ret;
1603 }
1604
1605 /* Digital Microphone interface error interrupt */
1606 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1607 micfil_err_isr, IRQF_SHARED,
1608 micfil->name, micfil);
1609 if (ret) {
1610 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1611 micfil->irq[1]);
1612 return ret;
1613 }
1614
1615 /* Digital Microphone interface voice activity detector event */
1616 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1617 hwvad_isr, voice_detected_fn,
1618 IRQF_SHARED, micfil->name, micfil);
1619 if (ret) {
1620 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1621 micfil->irq[0]);
1622 return ret;
1623 }
1624
1625 /* Digital Microphone interface voice activity detector error */
1626 ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1627 hwvad_err_isr, IRQF_SHARED,
1628 micfil->name, micfil);
1629 if (ret) {
1630 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1631 micfil->irq[1]);
1632 return ret;
1633 }
1634
1635 micfil->dma_params_rx.chan_name = "rx";
1636 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset;
1637 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1638
1639 platform_set_drvdata(pdev, micfil);
1640
1641 pm_runtime_enable(&pdev->dev);
1642 if (!pm_runtime_enabled(&pdev->dev)) {
1643 ret = fsl_micfil_runtime_resume(&pdev->dev);
1644 if (ret)
1645 goto err_pm_disable;
1646 }
1647
1648 ret = pm_runtime_resume_and_get(&pdev->dev);
1649 if (ret < 0)
1650 goto err_pm_get_sync;
1651
1652 /* Get micfil version */
1653 ret = fsl_micfil_use_verid(&pdev->dev);
1654 if (ret < 0)
1655 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1656
1657 ret = pm_runtime_put_sync(&pdev->dev);
1658 if (ret < 0 && ret != -ENOSYS)
1659 goto err_pm_get_sync;
1660
1661 regcache_cache_only(micfil->regmap, true);
1662
1663 /*
1664 * Register platform component before registering cpu dai for there
1665 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1666 */
1667 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1668 if (ret) {
1669 dev_err(&pdev->dev, "failed to pcm register\n");
1670 goto err_pm_disable;
1671 }
1672
1673 fsl_micfil_dai.capture.formats = micfil->soc->formats;
1674
1675 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1676 &fsl_micfil_dai, 1);
1677 if (ret) {
1678 dev_err(&pdev->dev, "failed to register component %s\n",
1679 fsl_micfil_component.name);
1680 goto err_pm_disable;
1681 }
1682
1683 return ret;
1684
1685 err_pm_get_sync:
1686 if (!pm_runtime_status_suspended(&pdev->dev))
1687 fsl_micfil_runtime_suspend(&pdev->dev);
1688 err_pm_disable:
1689 pm_runtime_disable(&pdev->dev);
1690
1691 return ret;
1692 }
1693
fsl_micfil_remove(struct platform_device * pdev)1694 static void fsl_micfil_remove(struct platform_device *pdev)
1695 {
1696 pm_runtime_disable(&pdev->dev);
1697 }
1698
fsl_micfil_runtime_suspend(struct device * dev)1699 static int fsl_micfil_runtime_suspend(struct device *dev)
1700 {
1701 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1702
1703 regcache_cache_only(micfil->regmap, true);
1704
1705 if (micfil->mclk_flag)
1706 clk_disable_unprepare(micfil->mclk);
1707 clk_disable_unprepare(micfil->busclk);
1708
1709 return 0;
1710 }
1711
fsl_micfil_runtime_resume(struct device * dev)1712 static int fsl_micfil_runtime_resume(struct device *dev)
1713 {
1714 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1715 int ret;
1716
1717 ret = clk_prepare_enable(micfil->busclk);
1718 if (ret < 0)
1719 return ret;
1720
1721 if (micfil->mclk_flag) {
1722 ret = clk_prepare_enable(micfil->mclk);
1723 if (ret < 0) {
1724 clk_disable_unprepare(micfil->busclk);
1725 return ret;
1726 }
1727 }
1728
1729 regcache_cache_only(micfil->regmap, false);
1730 regcache_mark_dirty(micfil->regmap);
1731 regcache_sync(micfil->regmap);
1732
1733 return 0;
1734 }
1735
1736 static const struct dev_pm_ops fsl_micfil_pm_ops = {
1737 RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, fsl_micfil_runtime_resume, NULL)
1738 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1739 };
1740
1741 static struct platform_driver fsl_micfil_driver = {
1742 .probe = fsl_micfil_probe,
1743 .remove = fsl_micfil_remove,
1744 .driver = {
1745 .name = "fsl-micfil-dai",
1746 .pm = pm_ptr(&fsl_micfil_pm_ops),
1747 .of_match_table = fsl_micfil_dt_ids,
1748 },
1749 };
1750 module_platform_driver(fsl_micfil_driver);
1751
1752 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1753 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1754 MODULE_LICENSE("Dual BSD/GPL");
1755