1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51
52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
56
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA3_REG_OFFSET 0x400
59 #define SDMA0_HYP_DEC_REG_START 0x5880
60 #define SDMA0_HYP_DEC_REG_END 0x5893
61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
62
63 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = {
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
109 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
110 };
111
112 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
113 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
114 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
115 static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring);
116 static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring);
117
sdma_v5_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)118 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
119 {
120 u32 base;
121
122 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
123 internal_offset <= SDMA0_HYP_DEC_REG_END) {
124 base = adev->reg_offset[GC_HWIP][0][1];
125 if (instance != 0)
126 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
127 } else {
128 if (instance < 2) {
129 base = adev->reg_offset[GC_HWIP][0][0];
130 if (instance == 1)
131 internal_offset += SDMA1_REG_OFFSET;
132 } else {
133 base = adev->reg_offset[GC_HWIP][0][2];
134 if (instance == 3)
135 internal_offset += SDMA3_REG_OFFSET;
136 }
137 }
138
139 return base + internal_offset;
140 }
141
sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)142 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring,
143 uint64_t addr)
144 {
145 unsigned ret;
146
147 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
148 amdgpu_ring_write(ring, lower_32_bits(addr));
149 amdgpu_ring_write(ring, upper_32_bits(addr));
150 amdgpu_ring_write(ring, 1);
151 /* this is the offset we need patch later */
152 ret = ring->wptr & ring->buf_mask;
153 /* insert dummy here and patch it later */
154 amdgpu_ring_write(ring, 0);
155
156 return ret;
157 }
158
159 /**
160 * sdma_v5_2_ring_get_rptr - get the current read pointer
161 *
162 * @ring: amdgpu ring pointer
163 *
164 * Get the current rptr from the hardware (NAVI10+).
165 */
sdma_v5_2_ring_get_rptr(struct amdgpu_ring * ring)166 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
167 {
168 u64 *rptr;
169
170 /* XXX check if swapping is necessary on BE */
171 rptr = (u64 *)ring->rptr_cpu_addr;
172
173 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
174 return ((*rptr) >> 2);
175 }
176
177 /**
178 * sdma_v5_2_ring_get_wptr - get the current write pointer
179 *
180 * @ring: amdgpu ring pointer
181 *
182 * Get the current wptr from the hardware (NAVI10+).
183 */
sdma_v5_2_ring_get_wptr(struct amdgpu_ring * ring)184 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
185 {
186 struct amdgpu_device *adev = ring->adev;
187 u64 wptr;
188
189 if (ring->use_doorbell) {
190 /* XXX check if swapping is necessary on BE */
191 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
192 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
193 } else {
194 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
195 wptr = wptr << 32;
196 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
197 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
198 }
199
200 return wptr >> 2;
201 }
202
203 /**
204 * sdma_v5_2_ring_set_wptr - commit the write pointer
205 *
206 * @ring: amdgpu ring pointer
207 *
208 * Write the wptr back to the hardware (NAVI10+).
209 */
sdma_v5_2_ring_set_wptr(struct amdgpu_ring * ring)210 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
211 {
212 struct amdgpu_device *adev = ring->adev;
213
214 DRM_DEBUG("Setting write pointer\n");
215 if (ring->use_doorbell) {
216 DRM_DEBUG("Using doorbell -- "
217 "wptr_offs == 0x%08x "
218 "lower_32_bits(ring->wptr << 2) == 0x%08x "
219 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
220 ring->wptr_offs,
221 lower_32_bits(ring->wptr << 2),
222 upper_32_bits(ring->wptr << 2));
223 /* XXX check if swapping is necessary on BE */
224 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
225 ring->wptr << 2);
226 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
227 ring->doorbell_index, ring->wptr << 2);
228 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
229 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) {
230 /* SDMA seems to miss doorbells sometimes when powergating kicks in.
231 * Updating the wptr directly will wake it. This is only safe because
232 * we disallow gfxoff in begin_use() and then allow it again in end_use().
233 */
234 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
235 lower_32_bits(ring->wptr << 2));
236 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
237 upper_32_bits(ring->wptr << 2));
238 }
239 } else {
240 DRM_DEBUG("Not using doorbell -- "
241 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
242 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
243 ring->me,
244 lower_32_bits(ring->wptr << 2),
245 ring->me,
246 upper_32_bits(ring->wptr << 2));
247 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
248 lower_32_bits(ring->wptr << 2));
249 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
250 upper_32_bits(ring->wptr << 2));
251 }
252 }
253
sdma_v5_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)254 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
255 {
256 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
257 int i;
258
259 for (i = 0; i < count; i++)
260 if (sdma && sdma->burst_nop && (i == 0))
261 amdgpu_ring_write(ring, ring->funcs->nop |
262 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
263 else
264 amdgpu_ring_write(ring, ring->funcs->nop);
265 }
266
267 /**
268 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
269 *
270 * @ring: amdgpu ring pointer
271 * @job: job to retrieve vmid from
272 * @ib: IB object to schedule
273 * @flags: unused
274 *
275 * Schedule an IB in the DMA ring.
276 */
sdma_v5_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)277 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
278 struct amdgpu_job *job,
279 struct amdgpu_ib *ib,
280 uint32_t flags)
281 {
282 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
283 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
284
285 /* An IB packet must end on a 8 DW boundary--the next dword
286 * must be on a 8-dword boundary. Our IB packet below is 6
287 * dwords long, thus add x number of NOPs, such that, in
288 * modular arithmetic,
289 * wptr + 6 + x = 8k, k >= 0, which in C is,
290 * (wptr + 6 + x) % 8 = 0.
291 * The expression below, is a solution of x.
292 */
293 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
294
295 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
296 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
297 /* base must be 32 byte aligned */
298 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
299 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
300 amdgpu_ring_write(ring, ib->length_dw);
301 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
302 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
303 }
304
305 /**
306 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
307 *
308 * @ring: amdgpu ring pointer
309 *
310 * flush the IB by graphics cache rinse.
311 */
sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring * ring)312 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
313 {
314 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
315 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
316 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
317 SDMA_GCR_GLI_INV(1);
318
319 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
320 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
321 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
322 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
323 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
324 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
325 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
326 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
327 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
328 }
329
330 /**
331 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
332 *
333 * @ring: amdgpu ring pointer
334 *
335 * Emit an hdp flush packet on the requested DMA ring.
336 */
sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)337 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
338 {
339 struct amdgpu_device *adev = ring->adev;
340 u32 ref_and_mask = 0;
341 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
342
343 if (ring->me > 1) {
344 amdgpu_hdp_flush(adev, ring);
345 } else {
346 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
347
348 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
349 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
350 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
351 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
352 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
353 amdgpu_ring_write(ring, ref_and_mask); /* reference */
354 amdgpu_ring_write(ring, ref_and_mask); /* mask */
355 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
356 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
357 }
358 }
359
360 /**
361 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
362 *
363 * @ring: amdgpu ring pointer
364 * @addr: address
365 * @seq: sequence number
366 * @flags: fence related flags
367 *
368 * Add a DMA fence packet to the ring to write
369 * the fence seq number and DMA trap packet to generate
370 * an interrupt if needed.
371 */
sdma_v5_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)372 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
373 unsigned flags)
374 {
375 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
376 /* write the fence */
377 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
378 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
379 /* zero in first two bits */
380 WARN_ON(addr & 0x3);
381 amdgpu_ring_write(ring, lower_32_bits(addr));
382 amdgpu_ring_write(ring, upper_32_bits(addr));
383 amdgpu_ring_write(ring, lower_32_bits(seq));
384
385 /* optionally write high bits as well */
386 if (write64bit) {
387 addr += 4;
388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
389 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
390 /* zero in first two bits */
391 WARN_ON(addr & 0x3);
392 amdgpu_ring_write(ring, lower_32_bits(addr));
393 amdgpu_ring_write(ring, upper_32_bits(addr));
394 amdgpu_ring_write(ring, upper_32_bits(seq));
395 }
396
397 if ((flags & AMDGPU_FENCE_FLAG_INT)) {
398 /* generate an interrupt */
399 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
400 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
401 }
402 }
403
404
405 /**
406 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
407 *
408 * @adev: amdgpu_device pointer
409 * @inst_mask: mask of dma engine instances to be disabled
410 * Stop the gfx async dma ring buffers.
411 */
sdma_v5_2_gfx_stop(struct amdgpu_device * adev,uint32_t inst_mask)412 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask)
413 {
414 u32 rb_cntl, ib_cntl;
415 int i;
416
417 for_each_inst(i, inst_mask) {
418 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
419 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
420 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
421 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
422 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
423 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
424 }
425 }
426
427 /**
428 * sdma_v5_2_rlc_stop - stop the compute async dma engines
429 *
430 * @adev: amdgpu_device pointer
431 *
432 * Stop the compute async dma queues.
433 */
sdma_v5_2_rlc_stop(struct amdgpu_device * adev)434 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
435 {
436 /* XXX todo */
437 }
438
439 /**
440 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
441 *
442 * @adev: amdgpu_device pointer
443 * @enable: enable/disable the DMA MEs context switch.
444 *
445 * Halt or unhalt the async dma engines context switch.
446 */
sdma_v5_2_ctx_switch_enable(struct amdgpu_device * adev,bool enable)447 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
448 {
449 u32 f32_cntl, phase_quantum = 0;
450 int i;
451
452 if (amdgpu_sdma_phase_quantum) {
453 unsigned value = amdgpu_sdma_phase_quantum;
454 unsigned unit = 0;
455
456 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
457 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
458 value = (value + 1) >> 1;
459 unit++;
460 }
461 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
462 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
463 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
464 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
465 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
466 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
467 WARN_ONCE(1,
468 "clamping sdma_phase_quantum to %uK clock cycles\n",
469 value << unit);
470 }
471 phase_quantum =
472 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
473 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
474 }
475
476 for (i = 0; i < adev->sdma.num_instances; i++) {
477 if (enable && amdgpu_sdma_phase_quantum) {
478 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
479 phase_quantum);
480 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
481 phase_quantum);
482 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
483 phase_quantum);
484 }
485
486 if (!amdgpu_sriov_vf(adev)) {
487 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
488 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
489 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
490 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
491 }
492 }
493
494 }
495
496 /**
497 * sdma_v5_2_enable - stop the async dma engines
498 *
499 * @adev: amdgpu_device pointer
500 * @enable: enable/disable the DMA MEs.
501 *
502 * Halt or unhalt the async dma engines.
503 */
sdma_v5_2_enable(struct amdgpu_device * adev,bool enable)504 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
505 {
506 u32 f32_cntl;
507 int i;
508 uint32_t inst_mask;
509
510 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
511 if (!enable) {
512 sdma_v5_2_gfx_stop(adev, inst_mask);
513 sdma_v5_2_rlc_stop(adev);
514 }
515
516 if (!amdgpu_sriov_vf(adev)) {
517 for (i = 0; i < adev->sdma.num_instances; i++) {
518 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
519 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
520 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
521 }
522 }
523 }
524
525 /**
526 * sdma_v5_2_gfx_resume_instance - start/restart a certain sdma engine
527 *
528 * @adev: amdgpu_device pointer
529 * @i: instance
530 * @restore: used to restore wptr when restart
531 *
532 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
533 * Return 0 for success.
534 */
535
sdma_v5_2_gfx_resume_instance(struct amdgpu_device * adev,int i,bool restore)536 static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
537 {
538 struct amdgpu_ring *ring;
539 u32 rb_cntl, ib_cntl;
540 u32 rb_bufsz;
541 u32 doorbell;
542 u32 doorbell_offset;
543 u32 temp;
544 u32 wptr_poll_cntl;
545 u64 wptr_gpu_addr;
546
547 ring = &adev->sdma.instance[i].ring;
548
549 if (!amdgpu_sriov_vf(adev))
550 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
551
552 /* Set ring buffer size in dwords */
553 rb_bufsz = order_base_2(ring->ring_size / 4);
554 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
555 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
556 #ifdef __BIG_ENDIAN
557 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
558 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
559 RPTR_WRITEBACK_SWAP_ENABLE, 1);
560 #endif
561 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
562
563 /* Initialize the ring buffer's read and write pointers */
564 if (restore) {
565 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
566 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
567 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
568 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
569 } else {
570 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
571 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
572 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
574 }
575
576 /* setup the wptr shadow polling */
577 wptr_gpu_addr = ring->wptr_gpu_addr;
578 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
579 lower_32_bits(wptr_gpu_addr));
580 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
581 upper_32_bits(wptr_gpu_addr));
582 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
583 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
584 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
585 SDMA0_GFX_RB_WPTR_POLL_CNTL,
586 F32_POLL_ENABLE, 1);
587 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
588 wptr_poll_cntl);
589
590 /* set the wb address whether it's enabled or not */
591 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
592 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
593 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
594 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
595
596 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
597
598 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
599 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
600
601 if (!restore)
602 ring->wptr = 0;
603
604 /* before programing wptr to a less value, need set minor_ptr_update first */
605 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
606
607 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
608 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
609 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
610 }
611
612 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
613 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
614
615 if (ring->use_doorbell) {
616 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
617 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
618 OFFSET, ring->doorbell_index);
619 } else {
620 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
621 }
622 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
623 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
624
625 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
626 ring->doorbell_index,
627 adev->doorbell_index.sdma_doorbell_range);
628
629 if (amdgpu_sriov_vf(adev))
630 sdma_v5_2_ring_set_wptr(ring);
631
632 /* set minor_ptr_update to 0 after wptr programed */
633
634 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
635
636 /* SRIOV VF has no control of any of registers below */
637 if (!amdgpu_sriov_vf(adev)) {
638 /* set utc l1 enable flag always to 1 */
639 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
640 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
641
642 /* enable MCBP */
643 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
644 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
645
646 /* Set up RESP_MODE to non-copy addresses */
647 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
648 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
649 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
650 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
651
652 /* program default cache read and write policy */
653 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
654 /* clean read policy and write policy bits */
655 temp &= 0xFF0FFF;
656 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
657 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
658 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
659 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
660
661 /* unhalt engine */
662 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
663 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
664 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
665 }
666
667 /* enable DMA RB */
668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
669 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
670
671 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
672 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
673 #ifdef __BIG_ENDIAN
674 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
675 #endif
676 /* enable DMA IBs */
677 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
678
679 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
680 sdma_v5_2_ctx_switch_enable(adev, true);
681 sdma_v5_2_enable(adev, true);
682 }
683
684 return amdgpu_ring_test_helper(ring);
685 }
686
687 /**
688 * sdma_v5_2_gfx_resume - setup and start the async dma engines
689 *
690 * @adev: amdgpu_device pointer
691 *
692 * Set up the gfx DMA ring buffers and enable them.
693 * Returns 0 for success, error for failure.
694 */
sdma_v5_2_gfx_resume(struct amdgpu_device * adev)695 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
696 {
697 int i, r;
698
699 for (i = 0; i < adev->sdma.num_instances; i++) {
700 r = sdma_v5_2_gfx_resume_instance(adev, i, false);
701 if (r)
702 return r;
703 }
704
705 return 0;
706 }
707
708 /**
709 * sdma_v5_2_rlc_resume - setup and start the async dma engines
710 *
711 * @adev: amdgpu_device pointer
712 *
713 * Set up the compute DMA queues and enable them.
714 * Returns 0 for success, error for failure.
715 */
sdma_v5_2_rlc_resume(struct amdgpu_device * adev)716 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
717 {
718 return 0;
719 }
720
721 /**
722 * sdma_v5_2_load_microcode - load the sDMA ME ucode
723 *
724 * @adev: amdgpu_device pointer
725 *
726 * Loads the sDMA0/1/2/3 ucode.
727 * Returns 0 for success, -EINVAL if the ucode is not available.
728 */
sdma_v5_2_load_microcode(struct amdgpu_device * adev)729 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
730 {
731 const struct sdma_firmware_header_v1_0 *hdr;
732 const __le32 *fw_data;
733 u32 fw_size;
734 int i, j;
735
736 /* halt the MEs */
737 sdma_v5_2_enable(adev, false);
738
739 for (i = 0; i < adev->sdma.num_instances; i++) {
740 if (!adev->sdma.instance[i].fw)
741 return -EINVAL;
742
743 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
744 amdgpu_ucode_print_sdma_hdr(&hdr->header);
745 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
746
747 fw_data = (const __le32 *)
748 (adev->sdma.instance[i].fw->data +
749 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
750
751 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
752
753 for (j = 0; j < fw_size; j++) {
754 if (amdgpu_emu_mode == 1 && j % 500 == 0)
755 msleep(1);
756 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
757 }
758
759 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
760 }
761
762 return 0;
763 }
764
sdma_v5_2_soft_reset_engine(struct amdgpu_device * adev,u32 instance_id)765 static int sdma_v5_2_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)
766 {
767 u32 grbm_soft_reset;
768 u32 tmp;
769
770 grbm_soft_reset = REG_SET_FIELD(0,
771 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
772 1);
773 grbm_soft_reset <<= instance_id;
774
775 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
776 tmp |= grbm_soft_reset;
777 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
778 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
779 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
780
781 udelay(50);
782
783 tmp &= ~grbm_soft_reset;
784 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
785 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
786 return 0;
787 }
788
sdma_v5_2_soft_reset(struct amdgpu_ip_block * ip_block)789 static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block)
790 {
791 struct amdgpu_device *adev = ip_block->adev;
792 int i;
793
794 for (i = 0; i < adev->sdma.num_instances; i++) {
795 sdma_v5_2_soft_reset_engine(adev, i);
796 udelay(50);
797 }
798
799 return 0;
800 }
801
802 static const struct amdgpu_sdma_funcs sdma_v5_2_sdma_funcs = {
803 .stop_kernel_queue = &sdma_v5_2_stop_queue,
804 .start_kernel_queue = &sdma_v5_2_restore_queue,
805 .soft_reset_kernel_queue = &sdma_v5_2_soft_reset_engine,
806 };
807
808 /**
809 * sdma_v5_2_start - setup and start the async dma engines
810 *
811 * @adev: amdgpu_device pointer
812 *
813 * Set up the DMA engines and enable them.
814 * Returns 0 for success, error for failure.
815 */
sdma_v5_2_start(struct amdgpu_device * adev)816 static int sdma_v5_2_start(struct amdgpu_device *adev)
817 {
818 int r = 0;
819 struct amdgpu_ip_block *ip_block;
820
821 if (amdgpu_sriov_vf(adev)) {
822 sdma_v5_2_ctx_switch_enable(adev, false);
823 sdma_v5_2_enable(adev, false);
824
825 /* set RB registers */
826 r = sdma_v5_2_gfx_resume(adev);
827 return r;
828 }
829
830 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
831 r = sdma_v5_2_load_microcode(adev);
832 if (r)
833 return r;
834
835 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
836 if (amdgpu_emu_mode == 1)
837 msleep(1000);
838 }
839
840 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA);
841 if (!ip_block)
842 return -EINVAL;
843
844 sdma_v5_2_soft_reset(ip_block);
845 /* unhalt the MEs */
846 sdma_v5_2_enable(adev, true);
847 /* enable sdma ring preemption */
848 sdma_v5_2_ctx_switch_enable(adev, true);
849
850 /* start the gfx rings and rlc compute queues */
851 r = sdma_v5_2_gfx_resume(adev);
852 if (r)
853 return r;
854 r = sdma_v5_2_rlc_resume(adev);
855
856 return r;
857 }
858
sdma_v5_2_mqd_init(struct amdgpu_device * adev,void * mqd,struct amdgpu_mqd_prop * prop)859 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
860 struct amdgpu_mqd_prop *prop)
861 {
862 struct v10_sdma_mqd *m = mqd;
863 uint64_t wb_gpu_addr;
864
865 m->sdmax_rlcx_rb_cntl =
866 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
867 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
868 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
869 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
870
871 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
872 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
873
874 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
875 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
876
877 wb_gpu_addr = prop->wptr_gpu_addr;
878 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
879 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
880
881 wb_gpu_addr = prop->rptr_gpu_addr;
882 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
883 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
884
885 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
886 mmSDMA0_GFX_IB_CNTL));
887
888 m->sdmax_rlcx_doorbell_offset =
889 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
890
891 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
892
893 return 0;
894 }
895
sdma_v5_2_set_mqd_funcs(struct amdgpu_device * adev)896 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
897 {
898 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
899 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
900 }
901
902 /**
903 * sdma_v5_2_ring_test_ring - simple async dma engine test
904 *
905 * @ring: amdgpu_ring structure holding ring information
906 *
907 * Test the DMA engine by writing using it to write an
908 * value to memory.
909 * Returns 0 for success, error for failure.
910 */
sdma_v5_2_ring_test_ring(struct amdgpu_ring * ring)911 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
912 {
913 struct amdgpu_device *adev = ring->adev;
914 unsigned i;
915 unsigned index;
916 int r;
917 u32 tmp;
918 u64 gpu_addr;
919
920 tmp = 0xCAFEDEAD;
921
922 r = amdgpu_wb_get(adev, &index);
923 if (r) {
924 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
925 return r;
926 }
927
928 gpu_addr = adev->wb.gpu_addr + (index * 4);
929 adev->wb.wb[index] = cpu_to_le32(tmp);
930
931 r = amdgpu_ring_alloc(ring, 20);
932 if (r) {
933 drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r);
934 amdgpu_wb_free(adev, index);
935 return r;
936 }
937
938 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
939 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
940 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
941 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
942 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
943 amdgpu_ring_write(ring, 0xDEADBEEF);
944 amdgpu_ring_commit(ring);
945
946 for (i = 0; i < adev->usec_timeout; i++) {
947 tmp = le32_to_cpu(adev->wb.wb[index]);
948 if (tmp == 0xDEADBEEF)
949 break;
950 if (amdgpu_emu_mode == 1)
951 msleep(1);
952 else
953 udelay(1);
954 }
955
956 if (i >= adev->usec_timeout)
957 r = -ETIMEDOUT;
958
959 amdgpu_wb_free(adev, index);
960
961 return r;
962 }
963
964 /**
965 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
966 *
967 * @ring: amdgpu_ring structure holding ring information
968 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
969 *
970 * Test a simple IB in the DMA ring.
971 * Returns 0 on success, error on failure.
972 */
sdma_v5_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)973 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
974 {
975 struct amdgpu_device *adev = ring->adev;
976 struct amdgpu_ib ib;
977 struct dma_fence *f = NULL;
978 unsigned index;
979 long r;
980 u32 tmp = 0;
981 u64 gpu_addr;
982
983 tmp = 0xCAFEDEAD;
984 memset(&ib, 0, sizeof(ib));
985
986 r = amdgpu_wb_get(adev, &index);
987 if (r) {
988 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
989 return r;
990 }
991
992 gpu_addr = adev->wb.gpu_addr + (index * 4);
993 adev->wb.wb[index] = cpu_to_le32(tmp);
994
995 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
996 if (r) {
997 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
998 goto err0;
999 }
1000
1001 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1002 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1003 ib.ptr[1] = lower_32_bits(gpu_addr);
1004 ib.ptr[2] = upper_32_bits(gpu_addr);
1005 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1006 ib.ptr[4] = 0xDEADBEEF;
1007 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1008 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1009 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1010 ib.length_dw = 8;
1011
1012 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1013 if (r)
1014 goto err1;
1015
1016 r = dma_fence_wait_timeout(f, false, timeout);
1017 if (r == 0) {
1018 drm_err(adev_to_drm(adev), "IB test timed out\n");
1019 r = -ETIMEDOUT;
1020 goto err1;
1021 } else if (r < 0) {
1022 drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r);
1023 goto err1;
1024 }
1025
1026 tmp = le32_to_cpu(adev->wb.wb[index]);
1027
1028 if (tmp == 0xDEADBEEF)
1029 r = 0;
1030 else
1031 r = -EINVAL;
1032
1033 err1:
1034 amdgpu_ib_free(&ib, NULL);
1035 dma_fence_put(f);
1036 err0:
1037 amdgpu_wb_free(adev, index);
1038 return r;
1039 }
1040
1041
1042 /**
1043 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1044 *
1045 * @ib: indirect buffer to fill with commands
1046 * @pe: addr of the page entry
1047 * @src: src addr to copy from
1048 * @count: number of page entries to update
1049 *
1050 * Update PTEs by copying them from the GART using sDMA.
1051 */
sdma_v5_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1052 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1053 uint64_t pe, uint64_t src,
1054 unsigned count)
1055 {
1056 unsigned bytes = count * 8;
1057
1058 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1059 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1060 ib->ptr[ib->length_dw++] = bytes - 1;
1061 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1062 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1063 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1064 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1065 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1066
1067 }
1068
1069 /**
1070 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1071 *
1072 * @ib: indirect buffer to fill with commands
1073 * @pe: addr of the page entry
1074 * @value: dst addr to write into pe
1075 * @count: number of page entries to update
1076 * @incr: increase next addr by incr bytes
1077 *
1078 * Update PTEs by writing them manually using sDMA.
1079 */
sdma_v5_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1080 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1081 uint64_t value, unsigned count,
1082 uint32_t incr)
1083 {
1084 unsigned ndw = count * 2;
1085
1086 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1087 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1088 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1089 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1090 ib->ptr[ib->length_dw++] = ndw - 1;
1091 for (; ndw > 0; ndw -= 2) {
1092 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1093 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1094 value += incr;
1095 }
1096 }
1097
1098 /**
1099 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1100 *
1101 * @ib: indirect buffer to fill with commands
1102 * @pe: addr of the page entry
1103 * @addr: dst addr to write into pe
1104 * @count: number of page entries to update
1105 * @incr: increase next addr by incr bytes
1106 * @flags: access flags
1107 *
1108 * Update the page tables using sDMA.
1109 */
sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1110 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1111 uint64_t pe,
1112 uint64_t addr, unsigned count,
1113 uint32_t incr, uint64_t flags)
1114 {
1115 /* for physically contiguous pages (vram) */
1116 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1117 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1118 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1119 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1120 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1121 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1122 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1123 ib->ptr[ib->length_dw++] = incr; /* increment size */
1124 ib->ptr[ib->length_dw++] = 0;
1125 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1126 }
1127
1128 /**
1129 * sdma_v5_2_ring_pad_ib - pad the IB
1130 *
1131 * @ib: indirect buffer to fill with padding
1132 * @ring: amdgpu_ring structure holding ring information
1133 *
1134 * Pad the IB with NOPs to a boundary multiple of 8.
1135 */
sdma_v5_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1136 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1137 {
1138 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1139 u32 pad_count;
1140 int i;
1141
1142 pad_count = (-ib->length_dw) & 0x7;
1143 for (i = 0; i < pad_count; i++)
1144 if (sdma && sdma->burst_nop && (i == 0))
1145 ib->ptr[ib->length_dw++] =
1146 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1147 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1148 else
1149 ib->ptr[ib->length_dw++] =
1150 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1151 }
1152
1153
1154 /**
1155 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1156 *
1157 * @ring: amdgpu_ring pointer
1158 *
1159 * Make sure all previous operations are completed (CIK).
1160 */
sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1161 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1162 {
1163 uint32_t seq = ring->fence_drv.sync_seq;
1164 uint64_t addr = ring->fence_drv.gpu_addr;
1165
1166 /* wait for idle */
1167 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1168 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1169 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1170 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1171 amdgpu_ring_write(ring, addr & 0xfffffffc);
1172 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1173 amdgpu_ring_write(ring, seq); /* reference */
1174 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1175 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1176 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1177 }
1178
1179
1180 /**
1181 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1182 *
1183 * @ring: amdgpu_ring pointer
1184 * @vmid: vmid number to use
1185 * @pd_addr: address
1186 *
1187 * Update the page table base and flush the VM TLB
1188 * using sDMA.
1189 */
sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1190 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1191 unsigned vmid, uint64_t pd_addr)
1192 {
1193 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1194 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1195
1196 /* Update the PD address for this VMID. */
1197 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1198 (hub->ctx_addr_distance * vmid),
1199 lower_32_bits(pd_addr));
1200 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1201 (hub->ctx_addr_distance * vmid),
1202 upper_32_bits(pd_addr));
1203
1204 /* Trigger invalidation. */
1205 amdgpu_ring_write(ring,
1206 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1207 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1208 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1209 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1210 amdgpu_ring_write(ring, req);
1211 amdgpu_ring_write(ring, 0xFFFFFFFF);
1212 amdgpu_ring_write(ring,
1213 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1214 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1215 }
1216
sdma_v5_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1217 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1218 uint32_t reg, uint32_t val)
1219 {
1220 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1221 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1222 amdgpu_ring_write(ring, reg);
1223 amdgpu_ring_write(ring, val);
1224 }
1225
sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1226 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1227 uint32_t val, uint32_t mask)
1228 {
1229 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1230 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1231 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1232 amdgpu_ring_write(ring, reg << 2);
1233 amdgpu_ring_write(ring, 0);
1234 amdgpu_ring_write(ring, val); /* reference */
1235 amdgpu_ring_write(ring, mask); /* mask */
1236 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1237 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1238 }
1239
sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1240 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1241 uint32_t reg0, uint32_t reg1,
1242 uint32_t ref, uint32_t mask)
1243 {
1244 amdgpu_ring_emit_wreg(ring, reg0, ref);
1245 /* wait for a cycle to reset vm_inv_eng*_ack */
1246 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1247 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1248 }
1249
1250 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1251 .copy_pte_num_dw = 7,
1252 .copy_pte = sdma_v5_2_vm_copy_pte,
1253 .write_pte = sdma_v5_2_vm_write_pte,
1254 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1255 };
1256
sdma_v5_2_early_init(struct amdgpu_ip_block * ip_block)1257 static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block)
1258 {
1259 struct amdgpu_device *adev = ip_block->adev;
1260 int r;
1261
1262 r = amdgpu_sdma_init_microcode(adev, 0, true);
1263 if (r)
1264 return r;
1265
1266 sdma_v5_2_set_ring_funcs(adev);
1267 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs);
1268 sdma_v5_2_set_irq_funcs(adev);
1269 sdma_v5_2_set_mqd_funcs(adev);
1270
1271 return 0;
1272 }
1273
sdma_v5_2_seq_to_irq_id(int seq_num)1274 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1275 {
1276 switch (seq_num) {
1277 case 0:
1278 return SOC15_IH_CLIENTID_SDMA0;
1279 case 1:
1280 return SOC15_IH_CLIENTID_SDMA1;
1281 case 2:
1282 return SOC15_IH_CLIENTID_SDMA2;
1283 case 3:
1284 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1285 default:
1286 break;
1287 }
1288 return -EINVAL;
1289 }
1290
sdma_v5_2_seq_to_trap_id(int seq_num)1291 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1292 {
1293 switch (seq_num) {
1294 case 0:
1295 return SDMA0_5_0__SRCID__SDMA_TRAP;
1296 case 1:
1297 return SDMA1_5_0__SRCID__SDMA_TRAP;
1298 case 2:
1299 return SDMA2_5_0__SRCID__SDMA_TRAP;
1300 case 3:
1301 return SDMA3_5_0__SRCID__SDMA_TRAP;
1302 default:
1303 break;
1304 }
1305 return -EINVAL;
1306 }
1307
sdma_v5_2_sw_init(struct amdgpu_ip_block * ip_block)1308 static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block)
1309 {
1310 struct amdgpu_ring *ring;
1311 int r, i;
1312 struct amdgpu_device *adev = ip_block->adev;
1313 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
1314 uint32_t *ptr;
1315
1316 /* SDMA trap event */
1317 for (i = 0; i < adev->sdma.num_instances; i++) {
1318 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1319 sdma_v5_2_seq_to_trap_id(i),
1320 &adev->sdma.trap_irq);
1321 if (r)
1322 return r;
1323 }
1324
1325 for (i = 0; i < adev->sdma.num_instances; i++) {
1326 mutex_init(&adev->sdma.instance[i].engine_reset_mutex);
1327 adev->sdma.instance[i].funcs = &sdma_v5_2_sdma_funcs;
1328 ring = &adev->sdma.instance[i].ring;
1329 ring->ring_obj = NULL;
1330 ring->use_doorbell = true;
1331 ring->me = i;
1332
1333 drm_info(adev_to_drm(adev), "use_doorbell being set to: [%s]\n",
1334 ring->use_doorbell?"true":"false");
1335
1336 ring->doorbell_index =
1337 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1338
1339 ring->vm_hub = AMDGPU_GFXHUB(0);
1340 sprintf(ring->name, "sdma%d", i);
1341 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1342 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1343 AMDGPU_RING_PRIO_DEFAULT, NULL);
1344 if (r)
1345 return r;
1346 }
1347
1348 adev->sdma.supported_reset =
1349 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
1350 if (!amdgpu_sriov_vf(adev) &&
1351 !adev->debug_disable_gpu_ring_reset)
1352 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1353
1354 /* Allocate memory for SDMA IP Dump buffer */
1355 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1356 if (ptr)
1357 adev->sdma.ip_dump = ptr;
1358 else
1359 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1360
1361 r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1362 if (r)
1363 return r;
1364
1365 return r;
1366 }
1367
sdma_v5_2_sw_fini(struct amdgpu_ip_block * ip_block)1368 static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block)
1369 {
1370 struct amdgpu_device *adev = ip_block->adev;
1371 int i;
1372
1373 for (i = 0; i < adev->sdma.num_instances; i++)
1374 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1375
1376 amdgpu_sdma_sysfs_reset_mask_fini(adev);
1377 amdgpu_sdma_destroy_inst_ctx(adev, true);
1378
1379 kfree(adev->sdma.ip_dump);
1380
1381 return 0;
1382 }
1383
sdma_v5_2_hw_init(struct amdgpu_ip_block * ip_block)1384 static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block)
1385 {
1386 struct amdgpu_device *adev = ip_block->adev;
1387 int r;
1388
1389 r = sdma_v5_2_start(adev);
1390 if (r)
1391 return r;
1392 sdma_v5_2_set_buffer_funcs(adev);
1393
1394 return 0;
1395 }
1396
sdma_v5_2_hw_fini(struct amdgpu_ip_block * ip_block)1397 static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block)
1398 {
1399 struct amdgpu_device *adev = ip_block->adev;
1400
1401 if (amdgpu_sriov_vf(adev))
1402 return 0;
1403
1404 sdma_v5_2_ctx_switch_enable(adev, false);
1405 sdma_v5_2_enable(adev, false);
1406
1407 return 0;
1408 }
1409
sdma_v5_2_suspend(struct amdgpu_ip_block * ip_block)1410 static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block)
1411 {
1412 return sdma_v5_2_hw_fini(ip_block);
1413 }
1414
sdma_v5_2_resume(struct amdgpu_ip_block * ip_block)1415 static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block)
1416 {
1417 return sdma_v5_2_hw_init(ip_block);
1418 }
1419
sdma_v5_2_is_idle(struct amdgpu_ip_block * ip_block)1420 static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)
1421 {
1422 struct amdgpu_device *adev = ip_block->adev;
1423 u32 i;
1424
1425 for (i = 0; i < adev->sdma.num_instances; i++) {
1426 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1427
1428 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1429 return false;
1430 }
1431
1432 return true;
1433 }
1434
sdma_v5_2_wait_for_idle(struct amdgpu_ip_block * ip_block)1435 static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
1436 {
1437 unsigned i;
1438 u32 sdma0, sdma1, sdma2, sdma3;
1439 struct amdgpu_device *adev = ip_block->adev;
1440
1441 for (i = 0; i < adev->usec_timeout; i++) {
1442 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1443 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1444 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1445 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1446
1447 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1448 return 0;
1449 udelay(1);
1450 }
1451 return -ETIMEDOUT;
1452 }
1453
sdma_v5_2_reset_queue(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)1454 static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring,
1455 unsigned int vmid,
1456 struct amdgpu_fence *timedout_fence)
1457 {
1458 struct amdgpu_device *adev = ring->adev;
1459 int r;
1460
1461 if (ring->me >= adev->sdma.num_instances) {
1462 dev_err(adev->dev, "sdma instance not found\n");
1463 return -EINVAL;
1464 }
1465
1466 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
1467
1468 amdgpu_amdkfd_suspend(adev, true);
1469 r = amdgpu_sdma_reset_engine(adev, ring->me, true);
1470 amdgpu_amdkfd_resume(adev, true);
1471 if (r)
1472 return r;
1473
1474 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
1475 }
1476
sdma_v5_2_stop_queue(struct amdgpu_ring * ring)1477 static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring)
1478 {
1479 u32 f32_cntl, freeze, cntl, stat1_reg;
1480 struct amdgpu_device *adev = ring->adev;
1481 int i, j, r = 0;
1482
1483 if (amdgpu_sriov_vf(adev))
1484 return -EINVAL;
1485
1486 i = ring->me;
1487 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1488
1489 /* stop queue */
1490 sdma_v5_2_gfx_stop(adev, 1 << i);
1491
1492 /*engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */
1493 freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));
1494 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);
1495 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);
1496
1497 for (j = 0; j < adev->usec_timeout; j++) {
1498 freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));
1499
1500 if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)
1501 break;
1502 udelay(1);
1503 }
1504
1505
1506 if (j == adev->usec_timeout) {
1507 stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));
1508 if ((stat1_reg & 0x3FF) != 0x3FF) {
1509 DRM_ERROR("cannot soft reset as sdma not idle\n");
1510 r = -ETIMEDOUT;
1511 goto err0;
1512 }
1513 }
1514
1515 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
1516 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
1517 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
1518
1519 cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
1520 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);
1521 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);
1522
1523 err0:
1524 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1525 return r;
1526 }
1527
sdma_v5_2_restore_queue(struct amdgpu_ring * ring)1528 static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)
1529 {
1530 struct amdgpu_device *adev = ring->adev;
1531 u32 inst_id = ring->me;
1532 u32 freeze;
1533 int r;
1534
1535 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1536 /* unfreeze and unhalt */
1537 freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));
1538 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
1539 WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
1540
1541 r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);
1542
1543 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1544
1545 return r;
1546 }
1547
sdma_v5_2_ring_preempt_ib(struct amdgpu_ring * ring)1548 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1549 {
1550 int i, r = 0;
1551 struct amdgpu_device *adev = ring->adev;
1552 u32 index = 0;
1553 u64 sdma_gfx_preempt;
1554
1555 amdgpu_sdma_get_index_from_ring(ring, &index);
1556 sdma_gfx_preempt =
1557 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1558
1559 /* assert preemption condition */
1560 amdgpu_ring_set_preempt_cond_exec(ring, false);
1561
1562 /* emit the trailing fence */
1563 ring->trail_seq += 1;
1564 amdgpu_ring_alloc(ring, 10);
1565 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1566 ring->trail_seq, 0);
1567 amdgpu_ring_commit(ring);
1568
1569 /* assert IB preemption */
1570 WREG32(sdma_gfx_preempt, 1);
1571
1572 /* poll the trailing fence */
1573 for (i = 0; i < adev->usec_timeout; i++) {
1574 if (ring->trail_seq ==
1575 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1576 break;
1577 udelay(1);
1578 }
1579
1580 if (i >= adev->usec_timeout) {
1581 r = -EINVAL;
1582 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1583 }
1584
1585 /* deassert IB preemption */
1586 WREG32(sdma_gfx_preempt, 0);
1587
1588 /* deassert the preemption condition */
1589 amdgpu_ring_set_preempt_cond_exec(ring, true);
1590 return r;
1591 }
1592
sdma_v5_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1593 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1594 struct amdgpu_irq_src *source,
1595 unsigned type,
1596 enum amdgpu_interrupt_state state)
1597 {
1598 u32 sdma_cntl;
1599 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1600
1601 if (!amdgpu_sriov_vf(adev)) {
1602 sdma_cntl = RREG32(reg_offset);
1603 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1604 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1605 WREG32(reg_offset, sdma_cntl);
1606 }
1607
1608 return 0;
1609 }
1610
sdma_v5_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1611 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1612 struct amdgpu_irq_src *source,
1613 struct amdgpu_iv_entry *entry)
1614 {
1615 DRM_DEBUG("IH: SDMA trap\n");
1616
1617 if (drm_WARN_ON_ONCE(&adev->ddev,
1618 adev->enable_mes &&
1619 (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
1620 return 0;
1621
1622 switch (entry->client_id) {
1623 case SOC15_IH_CLIENTID_SDMA0:
1624 switch (entry->ring_id) {
1625 case 0:
1626 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1627 break;
1628 case 1:
1629 /* XXX compute */
1630 break;
1631 case 2:
1632 /* XXX compute */
1633 break;
1634 case 3:
1635 /* XXX page queue*/
1636 break;
1637 }
1638 break;
1639 case SOC15_IH_CLIENTID_SDMA1:
1640 switch (entry->ring_id) {
1641 case 0:
1642 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1643 break;
1644 case 1:
1645 /* XXX compute */
1646 break;
1647 case 2:
1648 /* XXX compute */
1649 break;
1650 case 3:
1651 /* XXX page queue*/
1652 break;
1653 }
1654 break;
1655 case SOC15_IH_CLIENTID_SDMA2:
1656 switch (entry->ring_id) {
1657 case 0:
1658 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1659 break;
1660 case 1:
1661 /* XXX compute */
1662 break;
1663 case 2:
1664 /* XXX compute */
1665 break;
1666 case 3:
1667 /* XXX page queue*/
1668 break;
1669 }
1670 break;
1671 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1672 switch (entry->ring_id) {
1673 case 0:
1674 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1675 break;
1676 case 1:
1677 /* XXX compute */
1678 break;
1679 case 2:
1680 /* XXX compute */
1681 break;
1682 case 3:
1683 /* XXX page queue*/
1684 break;
1685 }
1686 break;
1687 }
1688 return 0;
1689 }
1690
sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1691 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1692 struct amdgpu_irq_src *source,
1693 struct amdgpu_iv_entry *entry)
1694 {
1695 return 0;
1696 }
1697
sdma_v5_2_firmware_mgcg_support(struct amdgpu_device * adev,int i)1698 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev,
1699 int i)
1700 {
1701 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1702 case IP_VERSION(5, 2, 1):
1703 if (adev->sdma.instance[i].fw_version < 70)
1704 return false;
1705 break;
1706 case IP_VERSION(5, 2, 3):
1707 if (adev->sdma.instance[i].fw_version < 47)
1708 return false;
1709 break;
1710 case IP_VERSION(5, 2, 7):
1711 if (adev->sdma.instance[i].fw_version < 9)
1712 return false;
1713 break;
1714 default:
1715 return true;
1716 }
1717
1718 return true;
1719
1720 }
1721
sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1722 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1723 bool enable)
1724 {
1725 uint32_t data, def;
1726 int i;
1727
1728 for (i = 0; i < adev->sdma.num_instances; i++) {
1729
1730 if (!sdma_v5_2_firmware_mgcg_support(adev, i))
1731 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1732
1733 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1734 /* Enable sdma clock gating */
1735 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1736 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1737 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1738 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1739 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1740 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1741 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1742 if (def != data)
1743 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1744 } else {
1745 /* Disable sdma clock gating */
1746 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1747 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1748 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1749 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1750 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1751 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1752 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1753 if (def != data)
1754 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1755 }
1756 }
1757 }
1758
sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1759 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1760 bool enable)
1761 {
1762 uint32_t data, def;
1763 int i;
1764
1765 for (i = 0; i < adev->sdma.num_instances; i++) {
1766 if (adev->sdma.instance[i].fw_version < 70 &&
1767 amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
1768 IP_VERSION(5, 2, 1))
1769 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1770
1771 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1772 /* Enable sdma mem light sleep */
1773 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1774 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1775 if (def != data)
1776 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1777
1778 } else {
1779 /* Disable sdma mem light sleep */
1780 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1781 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1782 if (def != data)
1783 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1784
1785 }
1786 }
1787 }
1788
sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1789 static int sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1790 enum amd_clockgating_state state)
1791 {
1792 struct amdgpu_device *adev = ip_block->adev;
1793
1794 if (amdgpu_sriov_vf(adev))
1795 return 0;
1796
1797 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1798 case IP_VERSION(5, 2, 0):
1799 case IP_VERSION(5, 2, 2):
1800 case IP_VERSION(5, 2, 1):
1801 case IP_VERSION(5, 2, 4):
1802 case IP_VERSION(5, 2, 5):
1803 case IP_VERSION(5, 2, 6):
1804 case IP_VERSION(5, 2, 3):
1805 case IP_VERSION(5, 2, 7):
1806 sdma_v5_2_update_medium_grain_clock_gating(adev,
1807 state == AMD_CG_STATE_GATE);
1808 sdma_v5_2_update_medium_grain_light_sleep(adev,
1809 state == AMD_CG_STATE_GATE);
1810 break;
1811 default:
1812 break;
1813 }
1814
1815 return 0;
1816 }
1817
sdma_v5_2_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)1818 static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
1819 enum amd_powergating_state state)
1820 {
1821 return 0;
1822 }
1823
sdma_v5_2_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)1824 static void sdma_v5_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1825 {
1826 struct amdgpu_device *adev = ip_block->adev;
1827 int data;
1828
1829 if (amdgpu_sriov_vf(adev))
1830 *flags = 0;
1831
1832 /* AMD_CG_SUPPORT_SDMA_MGCG */
1833 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1834 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1835 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1836
1837 /* AMD_CG_SUPPORT_SDMA_LS */
1838 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1839 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1840 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1841 }
1842
sdma_v5_2_ring_begin_use(struct amdgpu_ring * ring)1843 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)
1844 {
1845 struct amdgpu_device *adev = ring->adev;
1846
1847 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1848 * disallow GFXOFF in some cases leading to
1849 * hangs in SDMA. Disallow GFXOFF while SDMA is active.
1850 * We can probably just limit this to 5.2.3,
1851 * but it shouldn't hurt for other parts since
1852 * this GFXOFF will be disallowed anyway when SDMA is
1853 * active, this just makes it explicit.
1854 * sdma_v5_2_ring_set_wptr() takes advantage of this
1855 * to update the wptr because sometimes SDMA seems to miss
1856 * doorbells when entering PG. If you remove this, update
1857 * sdma_v5_2_ring_set_wptr() as well!
1858 */
1859 amdgpu_gfx_off_ctrl(adev, false);
1860 }
1861
sdma_v5_2_ring_end_use(struct amdgpu_ring * ring)1862 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)
1863 {
1864 struct amdgpu_device *adev = ring->adev;
1865
1866 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1867 * disallow GFXOFF in some cases leading to
1868 * hangs in SDMA. Allow GFXOFF when SDMA is complete.
1869 */
1870 amdgpu_gfx_off_ctrl(adev, true);
1871 }
1872
sdma_v5_2_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)1873 static void sdma_v5_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1874 {
1875 struct amdgpu_device *adev = ip_block->adev;
1876 int i, j;
1877 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
1878 uint32_t instance_offset;
1879
1880 if (!adev->sdma.ip_dump)
1881 return;
1882
1883 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1884 for (i = 0; i < adev->sdma.num_instances; i++) {
1885 instance_offset = i * reg_count;
1886 drm_printf(p, "\nInstance:%d\n", i);
1887
1888 for (j = 0; j < reg_count; j++)
1889 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name,
1890 adev->sdma.ip_dump[instance_offset + j]);
1891 }
1892 }
1893
sdma_v5_2_dump_ip_state(struct amdgpu_ip_block * ip_block)1894 static void sdma_v5_2_dump_ip_state(struct amdgpu_ip_block *ip_block)
1895 {
1896 struct amdgpu_device *adev = ip_block->adev;
1897 int i, j;
1898 uint32_t instance_offset;
1899 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
1900
1901 if (!adev->sdma.ip_dump)
1902 return;
1903
1904 amdgpu_gfx_off_ctrl(adev, false);
1905 for (i = 0; i < adev->sdma.num_instances; i++) {
1906 instance_offset = i * reg_count;
1907 for (j = 0; j < reg_count; j++)
1908 adev->sdma.ip_dump[instance_offset + j] =
1909 RREG32(sdma_v5_2_get_reg_offset(adev, i,
1910 sdma_reg_list_5_2[j].reg_offset));
1911 }
1912 amdgpu_gfx_off_ctrl(adev, true);
1913 }
1914
1915 static const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1916 .name = "sdma_v5_2",
1917 .early_init = sdma_v5_2_early_init,
1918 .sw_init = sdma_v5_2_sw_init,
1919 .sw_fini = sdma_v5_2_sw_fini,
1920 .hw_init = sdma_v5_2_hw_init,
1921 .hw_fini = sdma_v5_2_hw_fini,
1922 .suspend = sdma_v5_2_suspend,
1923 .resume = sdma_v5_2_resume,
1924 .is_idle = sdma_v5_2_is_idle,
1925 .wait_for_idle = sdma_v5_2_wait_for_idle,
1926 .soft_reset = sdma_v5_2_soft_reset,
1927 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1928 .set_powergating_state = sdma_v5_2_set_powergating_state,
1929 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1930 .dump_ip_state = sdma_v5_2_dump_ip_state,
1931 .print_ip_state = sdma_v5_2_print_ip_state,
1932 };
1933
1934 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1935 .type = AMDGPU_RING_TYPE_SDMA,
1936 .align_mask = 0xf,
1937 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1938 .support_64bit_ptrs = true,
1939 .secure_submission_supported = true,
1940 .get_rptr = sdma_v5_2_ring_get_rptr,
1941 .get_wptr = sdma_v5_2_ring_get_wptr,
1942 .set_wptr = sdma_v5_2_ring_set_wptr,
1943 .emit_frame_size =
1944 5 + /* sdma_v5_2_ring_init_cond_exec */
1945 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1946 3 + /* hdp_invalidate */
1947 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1948 /* sdma_v5_2_ring_emit_vm_flush */
1949 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1950 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1951 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1952 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1953 .emit_ib = sdma_v5_2_ring_emit_ib,
1954 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1955 .emit_fence = sdma_v5_2_ring_emit_fence,
1956 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1957 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1958 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1959 .test_ring = sdma_v5_2_ring_test_ring,
1960 .test_ib = sdma_v5_2_ring_test_ib,
1961 .insert_nop = sdma_v5_2_ring_insert_nop,
1962 .pad_ib = sdma_v5_2_ring_pad_ib,
1963 .begin_use = sdma_v5_2_ring_begin_use,
1964 .end_use = sdma_v5_2_ring_end_use,
1965 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1966 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1967 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1968 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1969 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1970 .reset = sdma_v5_2_reset_queue,
1971 };
1972
sdma_v5_2_set_ring_funcs(struct amdgpu_device * adev)1973 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1974 {
1975 int i;
1976
1977 for (i = 0; i < adev->sdma.num_instances; i++) {
1978 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1979 adev->sdma.instance[i].ring.me = i;
1980 }
1981 }
1982
1983 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1984 .set = sdma_v5_2_set_trap_irq_state,
1985 .process = sdma_v5_2_process_trap_irq,
1986 };
1987
1988 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1989 .process = sdma_v5_2_process_illegal_inst_irq,
1990 };
1991
sdma_v5_2_set_irq_funcs(struct amdgpu_device * adev)1992 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1993 {
1994 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1995 adev->sdma.num_instances;
1996 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1997 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1998 }
1999
2000 /**
2001 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
2002 *
2003 * @ib: indirect buffer to copy to
2004 * @src_offset: src GPU address
2005 * @dst_offset: dst GPU address
2006 * @byte_count: number of bytes to xfer
2007 * @copy_flags: copy flags for the buffers
2008 *
2009 * Copy GPU buffers using the DMA engine.
2010 * Used by the amdgpu ttm implementation to move pages if
2011 * registered as the asic copy callback.
2012 */
sdma_v5_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)2013 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
2014 uint64_t src_offset,
2015 uint64_t dst_offset,
2016 uint32_t byte_count,
2017 uint32_t copy_flags)
2018 {
2019 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2020 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2021 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
2022 ib->ptr[ib->length_dw++] = byte_count - 1;
2023 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2024 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2025 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2026 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2027 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2028 }
2029
2030 /**
2031 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
2032 *
2033 * @ib: indirect buffer to fill
2034 * @src_data: value to write to buffer
2035 * @dst_offset: dst GPU address
2036 * @byte_count: number of bytes to xfer
2037 *
2038 * Fill GPU buffers using the DMA engine.
2039 */
sdma_v5_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)2040 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
2041 uint32_t src_data,
2042 uint64_t dst_offset,
2043 uint32_t byte_count)
2044 {
2045 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2046 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2047 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2048 ib->ptr[ib->length_dw++] = src_data;
2049 ib->ptr[ib->length_dw++] = byte_count - 1;
2050 }
2051
2052 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
2053 .copy_max_bytes = 1 << 30,
2054 .copy_num_dw = 7,
2055 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
2056
2057 .fill_max_bytes = 1 << 30, /* HW supports 1 << 30, but PAL uses 1 << 22 */
2058 .fill_num_dw = 5,
2059 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
2060 };
2061
sdma_v5_2_set_buffer_funcs(struct amdgpu_device * adev)2062 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
2063 {
2064 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_2_buffer_funcs);
2065 }
2066
2067 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
2068 .type = AMD_IP_BLOCK_TYPE_SDMA,
2069 .major = 5,
2070 .minor = 2,
2071 .rev = 0,
2072 .funcs = &sdma_v5_2_ip_funcs,
2073 };
2074