1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/clock/nxp,imx95-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13#include "imx95-clock.h" 14#include "imx95-pinfunc.h" 15#include "imx95-power.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 idle-states { 27 entry-method = "psci"; 28 29 cpu_pd_wait: cpu-pd-wait { 30 compatible = "arm,idle-state"; 31 arm,psci-suspend-param = <0x0010033>; 32 local-timer-stop; 33 entry-latency-us = <10000>; 34 exit-latency-us = <7000>; 35 min-residency-us = <27000>; 36 wakeup-latency-us = <15000>; 37 }; 38 }; 39 40 A55_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&cpu_pd_wait>; 47 power-domains = <&scmi_perf IMX95_PERF_A55>; 48 power-domain-names = "perf"; 49 i-cache-size = <32768>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <128>; 52 d-cache-size = <32768>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 next-level-cache = <&l2_cache_l0>; 56 }; 57 58 A55_1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x100>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; 64 cpu-idle-states = <&cpu_pd_wait>; 65 power-domains = <&scmi_perf IMX95_PERF_A55>; 66 power-domain-names = "perf"; 67 i-cache-size = <32768>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <128>; 70 d-cache-size = <32768>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2_cache_l1>; 74 }; 75 76 A55_2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x200>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 power-domains = <&scmi_perf IMX95_PERF_A55>; 84 power-domain-names = "perf"; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l2>; 92 }; 93 94 A55_3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x300>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; 100 cpu-idle-states = <&cpu_pd_wait>; 101 power-domains = <&scmi_perf IMX95_PERF_A55>; 102 power-domain-names = "perf"; 103 i-cache-size = <32768>; 104 i-cache-line-size = <64>; 105 i-cache-sets = <128>; 106 d-cache-size = <32768>; 107 d-cache-line-size = <64>; 108 d-cache-sets = <128>; 109 next-level-cache = <&l2_cache_l3>; 110 }; 111 112 A55_4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x400>; 116 power-domains = <&scmi_perf IMX95_PERF_A55>; 117 power-domain-names = "perf"; 118 enable-method = "psci"; 119 #cooling-cells = <2>; 120 cpu-idle-states = <&cpu_pd_wait>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <128>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_cache_l4>; 128 }; 129 130 A55_5: cpu@500 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x500>; 134 power-domains = <&scmi_perf IMX95_PERF_A55>; 135 power-domain-names = "perf"; 136 enable-method = "psci"; 137 #cooling-cells = <2>; 138 cpu-idle-states = <&cpu_pd_wait>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l5>; 146 }; 147 148 l2_cache_l0: l2-cache-l0 { 149 compatible = "cache"; 150 cache-size = <65536>; 151 cache-line-size = <64>; 152 cache-sets = <256>; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&l3_cache>; 156 }; 157 158 l2_cache_l1: l2-cache-l1 { 159 compatible = "cache"; 160 cache-size = <65536>; 161 cache-line-size = <64>; 162 cache-sets = <256>; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&l3_cache>; 166 }; 167 168 l2_cache_l2: l2-cache-l2 { 169 compatible = "cache"; 170 cache-size = <65536>; 171 cache-line-size = <64>; 172 cache-sets = <256>; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_cache>; 176 }; 177 178 l2_cache_l3: l2-cache-l3 { 179 compatible = "cache"; 180 cache-size = <65536>; 181 cache-line-size = <64>; 182 cache-sets = <256>; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_cache>; 186 }; 187 188 l2_cache_l4: l2-cache-l4 { 189 compatible = "cache"; 190 cache-size = <65536>; 191 cache-line-size = <64>; 192 cache-sets = <256>; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_cache>; 196 }; 197 198 l2_cache_l5: l2-cache-l5 { 199 compatible = "cache"; 200 cache-size = <65536>; 201 cache-line-size = <64>; 202 cache-sets = <256>; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_cache>; 206 }; 207 208 l3_cache: l3-cache { 209 compatible = "cache"; 210 cache-size = <524288>; 211 cache-line-size = <64>; 212 cache-sets = <512>; 213 cache-level = <3>; 214 cache-unified; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&A55_0>; 221 }; 222 223 core1 { 224 cpu = <&A55_1>; 225 }; 226 227 core2 { 228 cpu = <&A55_2>; 229 }; 230 231 core3 { 232 cpu = <&A55_3>; 233 }; 234 235 core4 { 236 cpu = <&A55_4>; 237 }; 238 239 core5 { 240 cpu = <&A55_5>; 241 }; 242 }; 243 }; 244 }; 245 246 dummy: clock-dummy { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <0>; 250 clock-output-names = "dummy"; 251 }; 252 253 gpu_opp_table: opp-table { 254 compatible = "operating-points-v2"; 255 256 opp-500000000 { 257 opp-hz = /bits/ 64 <500000000>; 258 opp-hz-real = /bits/ 64 <500000000>; 259 opp-microvolt = <920000>; 260 }; 261 262 opp-800000000 { 263 opp-hz = /bits/ 64 <800000000>; 264 opp-hz-real = /bits/ 64 <800000000>; 265 opp-microvolt = <920000>; 266 }; 267 268 opp-1000000000 { 269 opp-hz = /bits/ 64 <1000000000>; 270 opp-hz-real = /bits/ 64 <1000000000>; 271 opp-microvolt = <920000>; 272 }; 273 }; 274 275 clk_ext1: clock-ext1 { 276 compatible = "fixed-clock"; 277 #clock-cells = <0>; 278 clock-frequency = <133000000>; 279 clock-output-names = "clk_ext1"; 280 }; 281 282 sai1_mclk: clock-sai-mclk1 { 283 compatible = "fixed-clock"; 284 #clock-cells = <0>; 285 clock-frequency = <0>; 286 clock-output-names = "sai1_mclk"; 287 }; 288 289 sai2_mclk: clock-sai-mclk2 { 290 compatible = "fixed-clock"; 291 #clock-cells = <0>; 292 clock-frequency = <0>; 293 clock-output-names = "sai2_mclk"; 294 }; 295 296 sai3_mclk: clock-sai-mclk3 { 297 compatible = "fixed-clock"; 298 #clock-cells = <0>; 299 clock-frequency = <0>; 300 clock-output-names = "sai3_mclk"; 301 }; 302 303 sai4_mclk: clock-sai-mclk4 { 304 compatible = "fixed-clock"; 305 #clock-cells = <0>; 306 clock-frequency = <0>; 307 clock-output-names = "sai4_mclk"; 308 }; 309 310 sai5_mclk: clock-sai-mclk5 { 311 compatible = "fixed-clock"; 312 #clock-cells = <0>; 313 clock-frequency = <0>; 314 clock-output-names = "sai5_mclk"; 315 }; 316 317 clk_sys100m: clock-sys100m { 318 compatible = "fixed-clock"; 319 #clock-cells = <0>; 320 clock-frequency = <100000000>; 321 clock-output-names = "clk_sys100m"; 322 }; 323 324 osc_24m: clock-24m { 325 compatible = "fixed-clock"; 326 #clock-cells = <0>; 327 clock-frequency = <24000000>; 328 clock-output-names = "osc_24m"; 329 }; 330 331 sram1: sram@204c0000 { 332 compatible = "mmio-sram"; 333 reg = <0x0 0x204c0000 0x0 0x18000>; 334 ranges = <0x0 0x0 0x204c0000 0x18000>; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 }; 338 339 firmware { 340 scmi { 341 compatible = "arm,scmi"; 342 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 343 shmem = <&scmi_buf0>, <&scmi_buf1>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 arm,max-rx-timeout-ms = <5000>; 347 348 scmi_devpd: protocol@11 { 349 reg = <0x11>; 350 #power-domain-cells = <1>; 351 }; 352 353 scmi_sys_power: protocol@12 { 354 reg = <0x12>; 355 }; 356 357 scmi_perf: protocol@13 { 358 reg = <0x13>; 359 #power-domain-cells = <1>; 360 }; 361 362 scmi_clk: protocol@14 { 363 reg = <0x14>; 364 #clock-cells = <1>; 365 }; 366 367 scmi_sensor: protocol@15 { 368 reg = <0x15>; 369 #thermal-sensor-cells = <1>; 370 }; 371 372 scmi_iomuxc: protocol@19 { 373 reg = <0x19>; 374 }; 375 376 scmi_lmm: protocol@80 { 377 reg = <0x80>; 378 }; 379 380 scmi_bbm: protocol@81 { 381 reg = <0x81>; 382 }; 383 384 scmi_cpu: protocol@82 { 385 reg = <0x82>; 386 }; 387 388 scmi_misc: protocol@84 { 389 reg = <0x84>; 390 }; 391 }; 392 }; 393 394 funnel0: funnel { 395 /* 396 * non-configurable funnel don't show up on the AMBA 397 * bus. As such no need to add "arm,primecell". 398 */ 399 compatible = "arm,coresight-static-funnel"; 400 status = "disabled"; 401 402 in-ports { 403 port { 404 ca_funnel_in_port0: endpoint { 405 remote-endpoint = <&etm0_out_port>; 406 }; 407 }; 408 }; 409 410 out-ports { 411 port { 412 ca_funnel_out_port0: endpoint { 413 remote-endpoint = <&hugo_funnel_in_port0>; 414 }; 415 }; 416 }; 417 }; 418 419 funnel1: funnel-sys { 420 compatible = "arm,coresight-static-funnel"; 421 status = "disabled"; 422 423 in-ports { 424 port { 425 hugo_funnel_in_port0: endpoint { 426 remote-endpoint = <&ca_funnel_out_port0>; 427 }; 428 }; 429 }; 430 431 out-ports { 432 port { 433 hugo_funnel_out_port0: endpoint { 434 remote-endpoint = <&etf_in_port>; 435 }; 436 }; 437 }; 438 }; 439 440 mqs1: mqs-1 { 441 compatible = "fsl,imx95-aonmix-mqs"; 442 status = "disabled"; 443 }; 444 445 pmu { 446 compatible = "arm,cortex-a55-pmu"; 447 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 448 }; 449 450 thermal_zones: thermal-zones { 451 a55-thermal { 452 polling-delay-passive = <250>; 453 polling-delay = <2000>; 454 thermal-sensors = <&scmi_sensor 1>; 455 456 trips { 457 cpu_alert0: trip0 { 458 temperature = <105000>; 459 hysteresis = <2000>; 460 type = "passive"; 461 }; 462 463 cpu_crit0: trip1 { 464 temperature = <125000>; 465 hysteresis = <2000>; 466 type = "critical"; 467 }; 468 }; 469 470 cooling-maps { 471 map0 { 472 trip = <&cpu_alert0>; 473 cooling-device = 474 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 475 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 476 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 480 }; 481 }; 482 }; 483 484 ana-thermal { 485 polling-delay-passive = <250>; 486 polling-delay = <2000>; 487 thermal-sensors = <&scmi_sensor 0>; 488 trips { 489 ana_alert: trip0 { 490 temperature = <105000>; 491 hysteresis = <2000>; 492 type = "passive"; 493 }; 494 495 ana_crit0: trip1 { 496 temperature = <125000>; 497 hysteresis = <2000>; 498 type = "critical"; 499 }; 500 }; 501 502 cooling-maps { 503 map0 { 504 trip = <&ana_alert>; 505 cooling-device = 506 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 507 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 508 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 509 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 510 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 511 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 512 }; 513 }; 514 }; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 timer { 523 compatible = "arm,armv8-timer"; 524 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 525 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 526 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 527 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 528 clock-frequency = <24000000>; 529 arm,no-tick-in-suspend; 530 interrupt-parent = <&gic>; 531 }; 532 533 gic: interrupt-controller@48000000 { 534 compatible = "arm,gic-v3"; 535 reg = <0 0x48000000 0 0x10000>, 536 <0 0x48060000 0 0xc0000>; 537 #address-cells = <2>; 538 #size-cells = <2>; 539 #interrupt-cells = <3>; 540 interrupt-controller; 541 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 542 interrupt-parent = <&gic>; 543 dma-noncoherent; 544 ranges; 545 546 its: msi-controller@48040000 { 547 compatible = "arm,gic-v3-its"; 548 reg = <0 0x48040000 0 0x20000>; 549 msi-controller; 550 #msi-cells = <1>; 551 dma-noncoherent; 552 }; 553 }; 554 555 usbphynop: usbphynop { 556 compatible = "usb-nop-xceiv"; 557 clocks = <&scmi_clk IMX95_CLK_HSIO>; 558 clock-names = "main_clk"; 559 #phy-cells = <0>; 560 }; 561 562 soc { 563 compatible = "simple-bus"; 564 #address-cells = <2>; 565 #size-cells = <2>; 566 ranges; 567 568 etm0: etm@40840000 { 569 compatible = "arm,coresight-etm4x", "arm,primecell"; 570 reg = <0x0 0x40840000 0x0 0x10000>; 571 arm,primecell-periphid = <0xbb95d>; 572 cpu = <&A55_0>; 573 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 574 clock-names = "apb_pclk"; 575 status = "disabled"; 576 577 out-ports { 578 port { 579 etm0_out_port: endpoint { 580 remote-endpoint = <&ca_funnel_in_port0>; 581 }; 582 }; 583 }; 584 }; 585 586 etf: etf@41030000 { 587 compatible = "arm,coresight-tmc", "arm,primecell"; 588 reg = <0x0 0x41030000 0x0 0x1000>; 589 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 590 clock-names = "apb_pclk"; 591 status = "disabled"; 592 593 in-ports { 594 port { 595 etf_in_port: endpoint { 596 remote-endpoint = <&hugo_funnel_out_port0>; 597 }; 598 }; 599 }; 600 601 out-ports { 602 port { 603 etf_out_port: endpoint { 604 remote-endpoint = <&etr_in_port>; 605 }; 606 }; 607 }; 608 }; 609 610 etr: etr@41040000 { 611 compatible = "arm,coresight-tmc", "arm,primecell"; 612 reg = <0x0 0x41040000 0x0 0x1000>; 613 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 614 clock-names = "apb_pclk"; 615 status = "disabled"; 616 617 in-ports { 618 port { 619 etr_in_port: endpoint { 620 remote-endpoint = <&etf_out_port>; 621 }; 622 }; 623 }; 624 }; 625 626 aips2: bus@42000000 { 627 compatible = "fsl,aips-bus", "simple-bus"; 628 reg = <0x0 0x42000000 0x0 0x800000>; 629 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 630 <0x28000000 0x0 0x28000000 0x10000000>; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 634 edma2: dma-controller@42000000 { 635 compatible = "fsl,imx95-edma5"; 636 reg = <0x42000000 0x210000>; 637 #dma-cells = <3>; 638 dma-channels = <64>; 639 /* channels 0 and 1 reserved for V2X fast hash */ 640 dma-channel-mask = <0x3>; 641 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 706 clock-names = "dma"; 707 }; 708 709 edma3: dma-controller@42210000 { 710 compatible = "fsl,imx95-edma5"; 711 reg = <0x42210000 0x210000>; 712 #dma-cells = <3>; 713 dma-channels = <64>; 714 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 779 clock-names = "dma"; 780 }; 781 782 mu7: mailbox@42430000 { 783 compatible = "fsl,imx95-mu"; 784 reg = <0x42430000 0x10000>; 785 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 787 #mbox-cells = <2>; 788 status = "disabled"; 789 }; 790 791 wdog3: watchdog@42490000 { 792 compatible = "fsl,imx93-wdt"; 793 reg = <0x42490000 0x10000>; 794 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 796 timeout-sec = <40>; 797 status = "disabled"; 798 }; 799 800 tpm3: pwm@424e0000 { 801 compatible = "fsl,imx7ulp-pwm"; 802 reg = <0x424e0000 0x1000>; 803 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 804 #pwm-cells = <3>; 805 status = "disabled"; 806 }; 807 808 tpm4: pwm@424f0000 { 809 compatible = "fsl,imx7ulp-pwm"; 810 reg = <0x424f0000 0x1000>; 811 clocks = <&scmi_clk IMX95_CLK_TPM4>; 812 #pwm-cells = <3>; 813 status = "disabled"; 814 }; 815 816 tpm5: pwm@42500000 { 817 compatible = "fsl,imx7ulp-pwm"; 818 reg = <0x42500000 0x1000>; 819 clocks = <&scmi_clk IMX95_CLK_TPM5>; 820 #pwm-cells = <3>; 821 status = "disabled"; 822 }; 823 824 tpm6: pwm@42510000 { 825 compatible = "fsl,imx7ulp-pwm"; 826 reg = <0x42510000 0x1000>; 827 clocks = <&scmi_clk IMX95_CLK_TPM6>; 828 #pwm-cells = <3>; 829 status = "disabled"; 830 }; 831 832 i3c2: i3c@42520000 { 833 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 834 reg = <0x42520000 0x10000>; 835 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 836 #address-cells = <3>; 837 #size-cells = <0>; 838 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 839 <&scmi_clk IMX95_CLK_I3C2SLOW>; 840 clock-names = "pclk", "fast_clk"; 841 status = "disabled"; 842 }; 843 844 lpi2c3: i2c@42530000 { 845 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 846 reg = <0x42530000 0x10000>; 847 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 849 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 850 clock-names = "per", "ipg"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 854 dma-names = "tx", "rx"; 855 status = "disabled"; 856 }; 857 858 lpi2c4: i2c@42540000 { 859 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 860 reg = <0x42540000 0x10000>; 861 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 863 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 864 clock-names = "per", "ipg"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 868 dma-names = "tx", "rx"; 869 status = "disabled"; 870 }; 871 872 lpspi3: spi@42550000 { 873 #address-cells = <1>; 874 #size-cells = <0>; 875 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 876 reg = <0x42550000 0x10000>; 877 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 879 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 880 clock-names = "per", "ipg"; 881 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 882 dma-names = "tx", "rx"; 883 status = "disabled"; 884 }; 885 886 lpspi4: spi@42560000 { 887 #address-cells = <1>; 888 #size-cells = <0>; 889 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 890 reg = <0x42560000 0x10000>; 891 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 893 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 894 clock-names = "per", "ipg"; 895 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 896 dma-names = "tx", "rx"; 897 status = "disabled"; 898 }; 899 900 lpuart3: serial@42570000 { 901 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 902 "fsl,imx7ulp-lpuart"; 903 reg = <0x42570000 0x1000>; 904 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 906 clock-names = "ipg"; 907 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 908 dma-names = "rx", "tx"; 909 status = "disabled"; 910 }; 911 912 lpuart4: serial@42580000 { 913 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 914 "fsl,imx7ulp-lpuart"; 915 reg = <0x42580000 0x1000>; 916 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 918 clock-names = "ipg"; 919 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 920 dma-names = "rx", "tx"; 921 status = "disabled"; 922 }; 923 924 lpuart5: serial@42590000 { 925 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 926 "fsl,imx7ulp-lpuart"; 927 reg = <0x42590000 0x1000>; 928 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 930 clock-names = "ipg"; 931 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 932 dma-names = "rx", "tx"; 933 status = "disabled"; 934 }; 935 936 lpuart6: serial@425a0000 { 937 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 938 "fsl,imx7ulp-lpuart"; 939 reg = <0x425a0000 0x1000>; 940 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 942 clock-names = "ipg"; 943 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 944 dma-names = "rx", "tx"; 945 status = "disabled"; 946 }; 947 948 flexcan2: can@425b0000 { 949 compatible = "fsl,imx95-flexcan"; 950 reg = <0x425b0000 0x10000>; 951 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 953 <&scmi_clk IMX95_CLK_CAN2>; 954 clock-names = "ipg", "per"; 955 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 956 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 957 assigned-clock-rates = <40000000>; 958 fsl,clk-source = /bits/ 8 <0>; 959 status = "disabled"; 960 }; 961 962 flexcan3: can@42600000 { 963 compatible = "fsl,imx95-flexcan"; 964 reg = <0x42600000 0x10000>; 965 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 967 <&scmi_clk IMX95_CLK_CAN3>; 968 clock-names = "ipg", "per"; 969 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 970 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 971 assigned-clock-rates = <40000000>; 972 fsl,clk-source = /bits/ 8 <0>; 973 status = "disabled"; 974 }; 975 976 flexspi1: spi@425e0000 { 977 compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi"; 978 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 979 reg-names = "fspi_base", "fspi_mmap"; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 984 <&scmi_clk IMX95_CLK_FLEXSPI1>; 985 clock-names = "fspi_en", "fspi"; 986 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 987 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 988 assigned-clock-rates = <200000000>; 989 status = "disabled"; 990 }; 991 992 sai3: sai@42650000 { 993 compatible = "fsl,imx95-sai"; 994 reg = <0x42650000 0x10000>; 995 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 997 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 998 <&dummy>; 999 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1000 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 1001 dma-names = "rx", "tx"; 1002 status = "disabled"; 1003 }; 1004 1005 sai4: sai@42660000 { 1006 compatible = "fsl,imx95-sai"; 1007 reg = <0x42660000 0x10000>; 1008 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 1010 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 1011 <&dummy>; 1012 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1013 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 1014 dma-names = "rx", "tx"; 1015 status = "disabled"; 1016 }; 1017 1018 sai5: sai@42670000 { 1019 compatible = "fsl,imx95-sai"; 1020 reg = <0x42670000 0x10000>; 1021 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 1023 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 1024 <&dummy>; 1025 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1026 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 1027 dma-names = "rx", "tx"; 1028 status = "disabled"; 1029 }; 1030 1031 xcvr: xcvr@42680000 { 1032 compatible = "fsl,imx95-xcvr"; 1033 reg = <0x42680000 0x800>, <0x42680800 0x400>, 1034 <0x42680c00 0x080>, <0x42680e00 0x080>; 1035 reg-names = "ram", "regs", "rxfifo", "txfifo"; 1036 interrupts = /* XCVR IRQ 0 */ 1037 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1038 /* XCVR IRQ 1 */ 1039 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1041 <&scmi_clk IMX95_CLK_SPDIF>, 1042 <&dummy>, 1043 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 1044 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1045 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 1046 dma-names = "rx", "tx"; 1047 status = "disabled"; 1048 }; 1049 1050 lpuart7: serial@42690000 { 1051 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1052 "fsl,imx7ulp-lpuart"; 1053 reg = <0x42690000 0x1000>; 1054 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 1056 clock-names = "ipg"; 1057 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 1058 dma-names = "rx", "tx"; 1059 status = "disabled"; 1060 }; 1061 1062 lpuart8: serial@426a0000 { 1063 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1064 "fsl,imx7ulp-lpuart"; 1065 reg = <0x426a0000 0x1000>; 1066 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 1068 clock-names = "ipg"; 1069 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 1070 dma-names = "rx", "tx"; 1071 status = "disabled"; 1072 }; 1073 1074 lpi2c5: i2c@426b0000 { 1075 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1076 reg = <0x426b0000 0x10000>; 1077 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 1079 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1080 clock-names = "per", "ipg"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 1084 dma-names = "tx", "rx"; 1085 status = "disabled"; 1086 }; 1087 1088 lpi2c6: i2c@426c0000 { 1089 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1090 reg = <0x426c0000 0x10000>; 1091 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 1093 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1094 clock-names = "per", "ipg"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 1098 dma-names = "tx", "rx"; 1099 status = "disabled"; 1100 }; 1101 1102 lpi2c7: i2c@426d0000 { 1103 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1104 reg = <0x426d0000 0x10000>; 1105 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 1107 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1108 clock-names = "per", "ipg"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 1112 dma-names = "tx", "rx"; 1113 status = "disabled"; 1114 }; 1115 1116 lpi2c8: i2c@426e0000 { 1117 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1118 reg = <0x426e0000 0x10000>; 1119 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 1121 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1122 clock-names = "per", "ipg"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 lpspi5: spi@426f0000 { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1134 reg = <0x426f0000 0x10000>; 1135 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 1137 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1138 clock-names = "per", "ipg"; 1139 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 1140 dma-names = "tx", "rx"; 1141 status = "disabled"; 1142 }; 1143 1144 lpspi6: spi@42700000 { 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1148 reg = <0x42700000 0x10000>; 1149 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 1151 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1152 clock-names = "per", "ipg"; 1153 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1154 dma-names = "tx", "rx"; 1155 status = "disabled"; 1156 }; 1157 1158 lpspi7: spi@42710000 { 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1162 reg = <0x42710000 0x10000>; 1163 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 1165 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1166 clock-names = "per", "ipg"; 1167 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1168 dma-names = "tx", "rx"; 1169 status = "disabled"; 1170 }; 1171 1172 lpspi8: spi@42720000 { 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1176 reg = <0x42720000 0x10000>; 1177 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1179 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1180 clock-names = "per", "ipg"; 1181 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1182 dma-names = "tx", "rx"; 1183 status = "disabled"; 1184 }; 1185 1186 mu8: mailbox@42730000 { 1187 compatible = "fsl,imx95-mu"; 1188 reg = <0x42730000 0x10000>; 1189 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1191 #mbox-cells = <2>; 1192 status = "disabled"; 1193 }; 1194 1195 flexcan4: can@427c0000 { 1196 compatible = "fsl,imx95-flexcan"; 1197 reg = <0x427c0000 0x10000>; 1198 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1200 <&scmi_clk IMX95_CLK_CAN4>; 1201 clock-names = "ipg", "per"; 1202 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1203 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1204 assigned-clock-rates = <40000000>; 1205 fsl,clk-source = /bits/ 8 <0>; 1206 status = "disabled"; 1207 }; 1208 1209 flexcan5: can@427d0000 { 1210 compatible = "fsl,imx95-flexcan"; 1211 reg = <0x427d0000 0x10000>; 1212 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1214 <&scmi_clk IMX95_CLK_CAN5>; 1215 clock-names = "ipg", "per"; 1216 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1217 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1218 assigned-clock-rates = <40000000>; 1219 fsl,clk-source = /bits/ 8 <0>; 1220 status = "disabled"; 1221 }; 1222 }; 1223 1224 aips3: bus@42800000 { 1225 compatible = "fsl,aips-bus", "simple-bus"; 1226 reg = <0 0x42800000 0 0x800000>; 1227 #address-cells = <1>; 1228 #size-cells = <1>; 1229 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1230 1231 usdhc1: mmc@42850000 { 1232 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1233 reg = <0x42850000 0x10000>; 1234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1236 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1237 <&scmi_clk IMX95_CLK_USDHC1>; 1238 clock-names = "ipg", "ahb", "per"; 1239 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1240 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1241 assigned-clock-rates = <400000000>; 1242 bus-width = <8>; 1243 fsl,tuning-start-tap = <1>; 1244 fsl,tuning-step = <2>; 1245 status = "disabled"; 1246 }; 1247 1248 usdhc2: mmc@42860000 { 1249 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1250 reg = <0x42860000 0x10000>; 1251 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1253 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1254 <&scmi_clk IMX95_CLK_USDHC2>; 1255 clock-names = "ipg", "ahb", "per"; 1256 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1257 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1258 assigned-clock-rates = <400000000>; 1259 bus-width = <4>; 1260 fsl,tuning-start-tap = <1>; 1261 fsl,tuning-step = <2>; 1262 status = "disabled"; 1263 }; 1264 1265 usdhc3: mmc@428b0000 { 1266 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1267 reg = <0x428b0000 0x10000>; 1268 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1270 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1271 <&scmi_clk IMX95_CLK_USDHC3>; 1272 clock-names = "ipg", "ahb", "per"; 1273 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1274 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1275 assigned-clock-rates = <400000000>; 1276 bus-width = <4>; 1277 fsl,tuning-start-tap = <1>; 1278 fsl,tuning-step = <2>; 1279 status = "disabled"; 1280 }; 1281 }; 1282 1283 gpio2: gpio@43810000 { 1284 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1285 reg = <0x0 0x43810000 0x0 0x1000>; 1286 gpio-controller; 1287 #gpio-cells = <2>; 1288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1290 interrupt-controller; 1291 #interrupt-cells = <2>; 1292 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1293 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1294 clock-names = "gpio", "port"; 1295 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1296 ngpios = <32>; 1297 }; 1298 1299 gpio3: gpio@43820000 { 1300 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1301 reg = <0x0 0x43820000 0x0 0x1000>; 1302 gpio-controller; 1303 #gpio-cells = <2>; 1304 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1306 interrupt-controller; 1307 #interrupt-cells = <2>; 1308 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1309 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1310 clock-names = "gpio", "port"; 1311 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1312 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1313 ngpios = <32>; 1314 }; 1315 1316 gpio4: gpio@43840000 { 1317 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1318 reg = <0x0 0x43840000 0x0 0x1000>; 1319 gpio-controller; 1320 #gpio-cells = <2>; 1321 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1323 interrupt-controller; 1324 #interrupt-cells = <2>; 1325 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1326 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1327 clock-names = "gpio", "port"; 1328 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1329 ngpios = <30>; 1330 }; 1331 1332 gpio5: gpio@43850000 { 1333 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1334 reg = <0x0 0x43850000 0x0 0x1000>; 1335 gpio-controller; 1336 #gpio-cells = <2>; 1337 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1339 interrupt-controller; 1340 #interrupt-cells = <2>; 1341 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1342 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1343 clock-names = "gpio", "port"; 1344 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1345 ngpios = <18>; 1346 }; 1347 1348 aips1: bus@44000000 { 1349 compatible = "fsl,aips-bus", "simple-bus"; 1350 reg = <0x0 0x44000000 0x0 0x800000>; 1351 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1352 #address-cells = <1>; 1353 #size-cells = <1>; 1354 1355 edma1: dma-controller@44000000 { 1356 compatible = "fsl,imx93-edma3"; 1357 reg = <0x44000000 0x200000>; 1358 #dma-cells = <3>; 1359 dma-channels = <31>; 1360 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1392 clock-names = "dma"; 1393 }; 1394 1395 mu1: mailbox@44220000 { 1396 compatible = "fsl,imx95-mu"; 1397 reg = <0x44220000 0x10000>; 1398 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1400 #mbox-cells = <2>; 1401 status = "disabled"; 1402 }; 1403 1404 system_counter: timer@44290000 { 1405 compatible = "nxp,imx95-sysctr-timer"; 1406 reg = <0x44290000 0x30000>; 1407 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&osc_24m>; 1409 clock-names = "per"; 1410 nxp,no-divider; 1411 }; 1412 1413 tpm1: pwm@44310000 { 1414 compatible = "fsl,imx7ulp-pwm"; 1415 reg = <0x44310000 0x1000>; 1416 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1417 #pwm-cells = <3>; 1418 status = "disabled"; 1419 }; 1420 1421 tpm2: pwm@44320000 { 1422 compatible = "fsl,imx7ulp-pwm"; 1423 reg = <0x44320000 0x1000>; 1424 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1425 #pwm-cells = <3>; 1426 status = "disabled"; 1427 }; 1428 1429 i3c1: i3c@44330000 { 1430 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 1431 reg = <0x44330000 0x10000>; 1432 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1433 #address-cells = <3>; 1434 #size-cells = <0>; 1435 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1436 <&scmi_clk IMX95_CLK_I3C1SLOW>; 1437 clock-names = "pclk", "fast_clk"; 1438 status = "disabled"; 1439 }; 1440 1441 lpi2c1: i2c@44340000 { 1442 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1443 reg = <0x44340000 0x10000>; 1444 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1446 <&scmi_clk IMX95_CLK_BUSAON>; 1447 clock-names = "per", "ipg"; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1451 dma-names = "tx", "rx"; 1452 status = "disabled"; 1453 }; 1454 1455 lpi2c2: i2c@44350000 { 1456 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1457 reg = <0x44350000 0x10000>; 1458 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1460 <&scmi_clk IMX95_CLK_BUSAON>; 1461 clock-names = "per", "ipg"; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1465 dma-names = "tx", "rx"; 1466 status = "disabled"; 1467 }; 1468 1469 lpspi1: spi@44360000 { 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1473 reg = <0x44360000 0x10000>; 1474 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1475 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1476 <&scmi_clk IMX95_CLK_BUSAON>; 1477 clock-names = "per", "ipg"; 1478 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1479 dma-names = "tx", "rx"; 1480 status = "disabled"; 1481 }; 1482 1483 lpspi2: spi@44370000 { 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1487 reg = <0x44370000 0x10000>; 1488 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1489 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1490 <&scmi_clk IMX95_CLK_BUSAON>; 1491 clock-names = "per", "ipg"; 1492 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1493 dma-names = "tx", "rx"; 1494 status = "disabled"; 1495 }; 1496 1497 lpuart1: serial@44380000 { 1498 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1499 "fsl,imx7ulp-lpuart"; 1500 reg = <0x44380000 0x1000>; 1501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1503 clock-names = "ipg"; 1504 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1505 dma-names = "rx", "tx"; 1506 status = "disabled"; 1507 }; 1508 1509 lpuart2: serial@44390000 { 1510 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1511 "fsl,imx7ulp-lpuart"; 1512 reg = <0x44390000 0x1000>; 1513 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1515 clock-names = "ipg"; 1516 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1517 dma-names = "rx", "tx"; 1518 status = "disabled"; 1519 }; 1520 1521 flexcan1: can@443a0000 { 1522 compatible = "fsl,imx95-flexcan"; 1523 reg = <0x443a0000 0x10000>; 1524 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1525 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1526 <&scmi_clk IMX95_CLK_CAN1>; 1527 clock-names = "ipg", "per"; 1528 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1529 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1530 assigned-clock-rates = <40000000>; 1531 fsl,clk-source = /bits/ 8 <0>; 1532 status = "disabled"; 1533 }; 1534 1535 sai1: sai@443b0000 { 1536 compatible = "fsl,imx95-sai"; 1537 reg = <0x443b0000 0x10000>; 1538 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1539 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1540 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1541 <&dummy>; 1542 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1543 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1544 dma-names = "rx", "tx"; 1545 status = "disabled"; 1546 }; 1547 1548 micfil: micfil@44520000 { 1549 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1550 reg = <0x44520000 0x10000>; 1551 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1556 <&scmi_clk IMX95_CLK_PDM>, 1557 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1558 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1559 <&dummy>; 1560 clock-names = "ipg_clk", "ipg_clk_app", 1561 "pll8k", "pll11k", "clkext3"; 1562 dmas = <&edma1 6 0 5>; 1563 dma-names = "rx"; 1564 status = "disabled"; 1565 }; 1566 1567 adc1: adc@44530000 { 1568 compatible = "nxp,imx93-adc"; 1569 reg = <0x44530000 0x10000>; 1570 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1573 clocks = <&scmi_clk IMX95_CLK_ADC>; 1574 clock-names = "ipg"; 1575 #io-channel-cells = <1>; 1576 status = "disabled"; 1577 }; 1578 1579 mu2: mailbox@445b0000 { 1580 compatible = "fsl,imx95-mu"; 1581 reg = <0x445b0000 0x1000>; 1582 ranges; 1583 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <1>; 1586 #mbox-cells = <2>; 1587 1588 sram0: sram@445b1000 { 1589 compatible = "mmio-sram"; 1590 reg = <0x445b1000 0x400>; 1591 ranges = <0x0 0x445b1000 0x400>; 1592 #address-cells = <1>; 1593 #size-cells = <1>; 1594 1595 scmi_buf0: scmi-sram-section@0 { 1596 compatible = "arm,scmi-shmem"; 1597 reg = <0x0 0x80>; 1598 }; 1599 1600 scmi_buf1: scmi-sram-section@80 { 1601 compatible = "arm,scmi-shmem"; 1602 reg = <0x80 0x80>; 1603 }; 1604 }; 1605 1606 }; 1607 1608 mu3: mailbox@445d0000 { 1609 compatible = "fsl,imx95-mu"; 1610 reg = <0x445d0000 0x10000>; 1611 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1612 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1613 #mbox-cells = <2>; 1614 status = "disabled"; 1615 }; 1616 1617 mu4: mailbox@445f0000 { 1618 compatible = "fsl,imx95-mu"; 1619 reg = <0x445f0000 0x10000>; 1620 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1621 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1622 #mbox-cells = <2>; 1623 status = "disabled"; 1624 }; 1625 1626 mu6: mailbox@44630000 { 1627 compatible = "fsl,imx95-mu"; 1628 reg = <0x44630000 0x10000>; 1629 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1630 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1631 #mbox-cells = <2>; 1632 status = "disabled"; 1633 }; 1634 }; 1635 1636 mailbox@47300000 { 1637 compatible = "fsl,imx95-mu-v2x"; 1638 reg = <0x0 0x47300000 0x0 0x10000>; 1639 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1640 #mbox-cells = <2>; 1641 }; 1642 1643 mailbox@47320000 { 1644 compatible = "fsl,imx95-mu-v2x"; 1645 reg = <0x0 0x47320000 0x0 0x10000>; 1646 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1647 #mbox-cells = <2>; 1648 }; 1649 1650 mailbox@47330000 { 1651 compatible = "fsl,imx95-mu-v2x"; 1652 reg = <0x0 0x47330000 0x0 0x10000>; 1653 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1654 #mbox-cells = <2>; 1655 }; 1656 1657 mailbox@47340000 { 1658 compatible = "fsl,imx95-mu-v2x"; 1659 reg = <0x0 0x47340000 0x0 0x10000>; 1660 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1661 #mbox-cells = <2>; 1662 }; 1663 1664 mailbox@47350000 { 1665 compatible = "fsl,imx95-mu-v2x"; 1666 reg = <0x0 0x47350000 0x0 0x10000>; 1667 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1668 #mbox-cells = <2>; 1669 }; 1670 1671 /* GPIO1 is under exclusive control of System Manager */ 1672 gpio1: gpio@47400000 { 1673 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1674 reg = <0x0 0x47400000 0x0 0x1000>; 1675 gpio-controller; 1676 #gpio-cells = <2>; 1677 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1679 interrupt-controller; 1680 #interrupt-cells = <2>; 1681 clocks = <&scmi_clk IMX95_CLK_M33>, 1682 <&scmi_clk IMX95_CLK_M33>; 1683 clock-names = "gpio", "port"; 1684 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1685 ngpios = <16>; 1686 status = "disabled"; 1687 }; 1688 1689 ocotp: efuse@47510000 { 1690 compatible = "fsl,imx95-ocotp", "syscon"; 1691 reg = <0x0 0x47510000 0x0 0x10000>; 1692 #address-cells = <1>; 1693 #size-cells = <1>; 1694 1695 eth_mac0: mac-address@0 { 1696 reg = <0x0514 0x6>; 1697 }; 1698 1699 eth_mac1: mac-address@1 { 1700 reg = <0x1514 0x6>; 1701 }; 1702 1703 eth_mac2: mac-address@2 { 1704 reg = <0x2514 0x6>; 1705 }; 1706 }; 1707 1708 elemu0: mailbox@47520000 { 1709 compatible = "fsl,imx95-mu-ele"; 1710 reg = <0x0 0x47520000 0x0 0x10000>; 1711 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1712 #mbox-cells = <2>; 1713 status = "disabled"; 1714 }; 1715 1716 elemu1: mailbox@47530000 { 1717 compatible = "fsl,imx95-mu-ele"; 1718 reg = <0x0 0x47530000 0x0 0x10000>; 1719 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1720 #mbox-cells = <2>; 1721 status = "disabled"; 1722 }; 1723 1724 elemu2: mailbox@47540000 { 1725 compatible = "fsl,imx95-mu-ele"; 1726 reg = <0x0 0x47540000 0x0 0x10000>; 1727 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1728 #mbox-cells = <2>; 1729 status = "disabled"; 1730 }; 1731 1732 elemu3: mailbox@47550000 { 1733 compatible = "fsl,imx95-mu-ele"; 1734 reg = <0x0 0x47550000 0x0 0x10000>; 1735 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1736 #mbox-cells = <2>; 1737 }; 1738 1739 elemu4: mailbox@47560000 { 1740 compatible = "fsl,imx95-mu-ele"; 1741 reg = <0x0 0x47560000 0x0 0x10000>; 1742 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1743 #mbox-cells = <2>; 1744 status = "disabled"; 1745 }; 1746 1747 elemu5: mailbox@47570000 { 1748 compatible = "fsl,imx95-mu-ele"; 1749 reg = <0x0 0x47570000 0x0 0x10000>; 1750 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1751 #mbox-cells = <2>; 1752 status = "disabled"; 1753 }; 1754 1755 aips4: bus@49000000 { 1756 compatible = "fsl,aips-bus", "simple-bus"; 1757 reg = <0x0 0x49000000 0x0 0x800000>; 1758 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1759 #address-cells = <1>; 1760 #size-cells = <1>; 1761 1762 smmu: iommu@490d0000 { 1763 compatible = "arm,smmu-v3"; 1764 reg = <0x490d0000 0x100000>; 1765 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1766 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1767 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1768 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1769 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1770 #iommu-cells = <1>; 1771 status = "disabled"; 1772 }; 1773 }; 1774 1775 usb3: usb@4c010010 { 1776 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; 1777 reg = <0x0 0x4c010010 0x0 0x04>, 1778 <0x0 0x4c1f0000 0x0 0x20>; 1779 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1780 <&scmi_clk IMX95_CLK_32K>; 1781 clock-names = "hsio", "suspend"; 1782 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1783 #address-cells = <2>; 1784 #size-cells = <2>; 1785 ranges; 1786 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1787 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 1788 status = "disabled"; 1789 1790 usb3_dwc3: usb@4c100000 { 1791 compatible = "snps,dwc3"; 1792 reg = <0x0 0x4c100000 0x0 0x10000>; 1793 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1794 <&scmi_clk IMX95_CLK_24M>, 1795 <&scmi_clk IMX95_CLK_32K>; 1796 clock-names = "bus_early", "ref", "suspend"; 1797 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1798 phys = <&usb3_phy>, <&usb3_phy>; 1799 phy-names = "usb2-phy", "usb3-phy"; 1800 snps,gfladj-refclk-lpm-sel-quirk; 1801 snps,parkmode-disable-ss-quirk; 1802 iommus = <&smmu 0xe>; 1803 }; 1804 }; 1805 1806 hsio_blk_ctl: syscon@4c0100c0 { 1807 compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; 1808 reg = <0x0 0x4c0100c0 0x0 0x1>; 1809 #clock-cells = <1>; 1810 clocks = <&clk_sys100m>; 1811 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1812 }; 1813 1814 usb3_phy: phy@4c1f0040 { 1815 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; 1816 reg = <0x0 0x4c1f0040 0x0 0x40>, 1817 <0x0 0x4c1fc000 0x0 0x100>; 1818 clocks = <&scmi_clk IMX95_CLK_HSIO>; 1819 clock-names = "phy"; 1820 #phy-cells = <0>; 1821 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1822 status = "disabled"; 1823 }; 1824 1825 usb2: usb@4c200000 { 1826 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1827 reg = <0x0 0x4c200000 0x0 0x200>; 1828 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1831 <&scmi_clk IMX95_CLK_32K>; 1832 clock-names = "usb_ctrl_root", "usb_wakeup"; 1833 iommus = <&smmu 0xf>; 1834 phys = <&usbphynop>; 1835 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1836 fsl,usbmisc = <&usbmisc 0>; 1837 status = "disabled"; 1838 }; 1839 1840 usbmisc: usbmisc@4c200200 { 1841 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", 1842 "fsl,imx6q-usbmisc"; 1843 reg = <0x0 0x4c200200 0x0 0x200>, 1844 <0x0 0x4c010014 0x0 0x04>; 1845 #index-cells = <1>; 1846 }; 1847 1848 pcie0: pcie@4c300000 { 1849 compatible = "fsl,imx95-pcie"; 1850 reg = <0 0x4c300000 0 0x10000>, 1851 <0 0x60100000 0 0xfe00000>, 1852 <0 0x4c360000 0 0x10000>, 1853 <0 0x4c340000 0 0x4000>; 1854 reg-names = "dbi", "config", "atu", "app"; 1855 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1856 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1857 #address-cells = <3>; 1858 #size-cells = <2>; 1859 device_type = "pci"; 1860 linux,pci-domain = <0>; 1861 bus-range = <0x00 0xff>; 1862 num-lanes = <1>; 1863 num-viewport = <8>; 1864 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1865 interrupt-names = "msi"; 1866 #interrupt-cells = <1>; 1867 interrupt-map-mask = <0 0 0 0x7>; 1868 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1869 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1870 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1871 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1873 <&scmi_clk IMX95_CLK_HSIOPLL>, 1874 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1875 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1876 <&hsio_blk_ctl 0>; 1877 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1878 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1879 <&scmi_clk IMX95_CLK_HSIOPLL>, 1880 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1881 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1882 assigned-clock-parents = <0>, <0>, 1883 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1884 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1885 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ 1886 msi-map = <0x0 &its 0x10 0x1>, 1887 <0x100 &its 0x11 0x7>; 1888 iommu-map = <0x000 &smmu 0x10 0x1>, 1889 <0x100 &smmu 0x11 0x7>; 1890 iommu-map-mask = <0x1ff>; 1891 fsl,max-link-speed = <3>; 1892 status = "disabled"; 1893 }; 1894 1895 pcie0_ep: pcie-ep@4c300000 { 1896 compatible = "fsl,imx95-pcie-ep"; 1897 reg = <0 0x4c300000 0 0x10000>, 1898 <0 0x4c360000 0 0x1000>, 1899 <0 0x4c320000 0 0x1000>, 1900 <0 0x4c340000 0 0x4000>, 1901 <0 0x4c370000 0 0x10000>, 1902 <0x9 0 1 0>; 1903 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1904 num-lanes = <1>; 1905 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1906 interrupt-names = "dma"; 1907 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1908 <&scmi_clk IMX95_CLK_HSIOPLL>, 1909 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1910 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1911 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1912 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1913 <&scmi_clk IMX95_CLK_HSIOPLL>, 1914 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1915 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1916 assigned-clock-parents = <0>, <0>, 1917 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1918 msi-map = <0x0 &its 0x10 0x1>; 1919 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1920 status = "disabled"; 1921 }; 1922 1923 pcie1: pcie@4c380000 { 1924 compatible = "fsl,imx95-pcie"; 1925 reg = <0 0x4c380000 0 0x10000>, 1926 <8 0x80100000 0 0xfe00000>, 1927 <0 0x4c3e0000 0 0x10000>, 1928 <0 0x4c3c0000 0 0x4000>; 1929 reg-names = "dbi", "config", "atu", "app"; 1930 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1931 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1932 #address-cells = <3>; 1933 #size-cells = <2>; 1934 device_type = "pci"; 1935 linux,pci-domain = <1>; 1936 bus-range = <0x00 0xff>; 1937 num-lanes = <1>; 1938 num-viewport = <8>; 1939 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1940 interrupt-names = "msi"; 1941 #interrupt-cells = <1>; 1942 interrupt-map-mask = <0 0 0 0x7>; 1943 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1944 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1945 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1946 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1947 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1948 <&scmi_clk IMX95_CLK_HSIOPLL>, 1949 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1950 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1951 <&hsio_blk_ctl 0>; 1952 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1953 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1954 <&scmi_clk IMX95_CLK_HSIOPLL>, 1955 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1956 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1957 assigned-clock-parents = <0>, <0>, 1958 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1959 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1960 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ 1961 msi-map = <0x0 &its 0x98 0x1>, 1962 <0x100 &its 0x99 0x7>; 1963 msi-map-mask = <0x1ff>; 1964 /* smmu have not Devid(BIT[7:6]) */ 1965 iommu-map = <0x000 &smmu 0x18 0x1>, 1966 <0x100 &smmu 0x19 0x7>; 1967 iommu-map-mask = <0x1ff>; 1968 fsl,max-link-speed = <3>; 1969 status = "disabled"; 1970 }; 1971 1972 pcie1_ep: pcie-ep@4c380000 { 1973 compatible = "fsl,imx95-pcie-ep"; 1974 reg = <0 0x4c380000 0 0x10000>, 1975 <0 0x4c3e0000 0 0x1000>, 1976 <0 0x4c3a0000 0 0x1000>, 1977 <0 0x4c3c0000 0 0x4000>, 1978 <0 0x4c3f0000 0 0x10000>, 1979 <0xa 0 1 0>; 1980 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1981 num-lanes = <1>; 1982 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1983 interrupt-names = "dma"; 1984 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1985 <&scmi_clk IMX95_CLK_HSIOPLL>, 1986 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1987 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1988 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1989 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1990 <&scmi_clk IMX95_CLK_HSIOPLL>, 1991 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1992 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1993 assigned-clock-parents = <0>, <0>, 1994 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1995 msi-map = <0x0 &its 0x98 0x1>; 1996 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1997 status = "disabled"; 1998 }; 1999 2000 vpu_blk_ctrl: clock-controller@4c410000 { 2001 compatible = "nxp,imx95-vpu-csr", "syscon"; 2002 reg = <0x0 0x4c410000 0x0 0x10000>; 2003 #clock-cells = <1>; 2004 clocks = <&scmi_clk IMX95_CLK_VPUAPB>; 2005 power-domains = <&scmi_devpd IMX95_PD_VPU>; 2006 assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>, 2007 <&scmi_clk IMX95_CLK_VPU>, 2008 <&scmi_clk IMX95_CLK_VPUJPEG>; 2009 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>, 2010 <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 2011 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 2012 assigned-clock-rates = <133333333>, <667000000>, <500000000>; 2013 }; 2014 2015 jpegdec: jpegdec@4c500000 { 2016 compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; 2017 reg = <0x0 0x4C500000 0x0 0x00050000>; 2018 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2022 clocks = <&scmi_clk IMX95_CLK_VPU>, 2023 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 2024 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 2025 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 2026 power-domains = <&scmi_devpd IMX95_PD_VPU>; 2027 }; 2028 2029 jpegenc: jpegenc@4c550000 { 2030 compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc"; 2031 reg = <0x0 0x4C550000 0x0 0x00050000>; 2032 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 2036 clocks = <&scmi_clk IMX95_CLK_VPU>, 2037 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 2038 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 2039 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 2040 power-domains = <&scmi_devpd IMX95_PD_VPU>; 2041 }; 2042 2043 netcmix_blk_ctrl: syscon@4c810000 { 2044 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 2045 reg = <0x0 0x4c810000 0x0 0x8>; 2046 #clock-cells = <1>; 2047 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 2048 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 2049 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 2050 assigned-clock-rates = <133333333>; 2051 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2052 status = "disabled"; 2053 }; 2054 2055 sai2: sai@4c880000 { 2056 compatible = "fsl,imx95-sai"; 2057 reg = <0x0 0x4c880000 0x0 0x10000>; 2058 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 2059 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 2060 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 2061 <&dummy>; 2062 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2063 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2064 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 2065 dma-names = "rx", "tx"; 2066 status = "disabled"; 2067 }; 2068 2069 netc_blk_ctrl: system-controller@4cde0000 { 2070 compatible = "nxp,imx95-netc-blk-ctrl"; 2071 reg = <0x0 0x4cde0000 0x0 0x10000>, 2072 <0x0 0x4cdf0000 0x0 0x10000>, 2073 <0x0 0x4c81000c 0x0 0x18>; 2074 reg-names = "ierb", "prb", "netcmix"; 2075 #address-cells = <2>; 2076 #size-cells = <2>; 2077 ranges; 2078 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2079 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, 2080 <&scmi_clk IMX95_CLK_ENETREF>; 2081 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 2082 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 2083 assigned-clock-rates = <666666666>, <250000000>; 2084 clocks = <&scmi_clk IMX95_CLK_ENET>; 2085 clock-names = "ipg"; 2086 status = "disabled"; 2087 2088 netc_bus0: pcie@4ca00000 { 2089 compatible = "pci-host-ecam-generic"; 2090 reg = <0x0 0x4ca00000 0x0 0x100000>; 2091 #address-cells = <3>; 2092 #size-cells = <2>; 2093 device_type = "pci"; 2094 bus-range = <0x0 0x0>; 2095 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 2096 <0x10 &its 0x61 0x1>, //ENETC0 VF0 2097 <0x20 &its 0x62 0x1>, //ENETC0 VF1 2098 <0x40 &its 0x63 0x1>, //ENETC1 PF 2099 <0x80 &its 0x64 0x1>, //ENETC2 PF 2100 <0x90 &its 0x65 0x1>, //ENETC2 VF0 2101 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 2102 <0xc0 &its 0x67 0x1>; //NETC Timer 2103 iommu-map = <0x0 &smmu 0x20 0x1>, 2104 <0x10 &smmu 0x21 0x1>, 2105 <0x20 &smmu 0x22 0x1>, 2106 <0x40 &smmu 0x23 0x1>, 2107 <0x80 &smmu 0x24 0x1>, 2108 <0x90 &smmu 0x25 0x1>, 2109 <0xa0 &smmu 0x26 0x1>, 2110 <0xc0 &smmu 0x27 0x1>; 2111 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ 2112 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 2113 /* Timer BAR2 - prefetchable memory */ 2114 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 2115 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ 2116 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 2117 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ 2118 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; 2119 2120 enetc_port0: ethernet@0,0 { 2121 compatible = "pci1131,e101"; 2122 reg = <0x000000 0 0 0 0>; 2123 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 2124 clock-names = "ref"; 2125 status = "disabled"; 2126 }; 2127 2128 enetc_port1: ethernet@8,0 { 2129 compatible = "pci1131,e101"; 2130 reg = <0x004000 0 0 0 0>; 2131 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 2132 clock-names = "ref"; 2133 status = "disabled"; 2134 }; 2135 2136 enetc_port2: ethernet@10,0 { 2137 compatible = "pci1131,e101"; 2138 reg = <0x008000 0 0 0 0>; 2139 status = "disabled"; 2140 }; 2141 2142 netc_timer: ethernet@18,0 { 2143 compatible = "pci1131,ee02"; 2144 reg = <0x00c000 0 0 0 0>; 2145 status = "disabled"; 2146 }; 2147 }; 2148 2149 netc_bus1: pcie@4cb00000 { 2150 compatible = "pci-host-ecam-generic"; 2151 reg = <0x0 0x4cb00000 0x0 0x100000>; 2152 #address-cells = <3>; 2153 #size-cells = <2>; 2154 device_type = "pci"; 2155 bus-range = <0x1 0x1>; 2156 /* EMDIO BAR0 - non-prefetchable memory */ 2157 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 2158 /* EMDIO BAR2 - prefetchable memory */ 2159 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; 2160 2161 netc_emdio: mdio@0,0 { 2162 compatible = "pci1131,ee00"; 2163 reg = <0x010000 0 0 0 0>; 2164 #address-cells = <1>; 2165 #size-cells = <0>; 2166 status = "disabled"; 2167 }; 2168 }; 2169 }; 2170 2171 gpu: gpu@4d900000 { 2172 compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; 2173 reg = <0 0x4d900000 0 0x480000>; 2174 clocks = <&scmi_clk IMX95_CLK_GPU_CGC>, <&scmi_clk IMX95_CLK_GPUAPB>; 2175 clock-names = "core", "coregroup"; 2176 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 2179 interrupt-names = "job", "mmu", "gpu"; 2180 operating-points-v2 = <&gpu_opp_table>; 2181 power-domains = <&scmi_devpd IMX95_PD_GPU>; 2182 #cooling-cells = <2>; 2183 dynamic-power-coefficient = <1013>; 2184 }; 2185 2186 ddr-pmu@4e090dc0 { 2187 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 2188 reg = <0x0 0x4e090dc0 0x0 0x200>; 2189 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2190 }; 2191 }; 2192}; 2193