1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
36 #include <linux/mm.h>
37 #include <linux/of.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/reset.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
55 #endif
56
57 #include "rsci.h"
58 #include "serial_mctrl_gpio.h"
59 #include "sh-sci.h"
60 #include "sh-sci-common.h"
61
62 #define SCIx_IRQ_IS_MUXED(port) \
63 ((port)->irqs[SCIx_ERI_IRQ] == \
64 (port)->irqs[SCIx_RXI_IRQ]) || \
65 ((port)->irqs[SCIx_ERI_IRQ] && \
66 ((port)->irqs[SCIx_RXI_IRQ] < 0))
67
68 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
69 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
70 SCI_SR(19) | SCI_SR(27)
71
72 /* Iterate over all supported sampling rates, from high to low */
73 #define for_each_sr(_sr, _port) \
74 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
75 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
76
77 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
78
79 #define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port))
80
81 static struct sci_port sci_ports[SCI_NPORTS];
82 static unsigned long sci_ports_in_use;
83 static struct uart_driver sci_uart_driver;
84 static bool sci_uart_earlycon;
85 static bool sci_uart_earlycon_dev_probing;
86
87 static const struct sci_port_params_bits sci_sci_port_params_bits = {
88 .rxtx_enable = SCSCR_RE | SCSCR_TE,
89 .te_clear = SCSCR_TE | SCSCR_TEIE,
90 .poll_sent_bits = SCI_TDRE | SCI_TEND
91 };
92
93 static const struct sci_port_params_bits sci_scif_port_params_bits = {
94 .rxtx_enable = SCSCR_RE | SCSCR_TE,
95 .te_clear = SCSCR_TE | SCSCR_TEIE,
96 .poll_sent_bits = SCIF_TDFE | SCIF_TEND
97 };
98
99 static const struct sci_common_regs sci_common_regs = {
100 .status = SCxSR,
101 .control = SCSCR,
102 };
103
104 struct sci_suspend_regs {
105 u16 scdl;
106 u16 sccks;
107 u16 scsmr;
108 u16 scscr;
109 u16 scfcr;
110 u16 scsptr;
111 u16 hssrr;
112 u16 scpcr;
113 u16 scpdr;
114 u8 scbrr;
115 u8 semr;
116 };
117
sci_suspend_regs_size(void)118 static size_t sci_suspend_regs_size(void)
119 {
120 return sizeof(struct sci_suspend_regs);
121 }
122
123 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
124 /*
125 * Common SCI definitions, dependent on the port's regshift
126 * value.
127 */
128 [SCIx_SCI_REGTYPE] = {
129 .regs = {
130 [SCSMR] = { 0x00, 8 },
131 [SCBRR] = { 0x01, 8 },
132 [SCSCR] = { 0x02, 8 },
133 [SCxTDR] = { 0x03, 8 },
134 [SCxSR] = { 0x04, 8 },
135 [SCxRDR] = { 0x05, 8 },
136 },
137 .fifosize = 1,
138 .overrun_reg = SCxSR,
139 .overrun_mask = SCI_ORER,
140 .sampling_rate_mask = SCI_SR(32),
141 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
142 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
143 .param_bits = &sci_sci_port_params_bits,
144 .common_regs = &sci_common_regs,
145 },
146
147 /*
148 * Common definitions for legacy IrDA ports.
149 */
150 [SCIx_IRDA_REGTYPE] = {
151 .regs = {
152 [SCSMR] = { 0x00, 8 },
153 [SCBRR] = { 0x02, 8 },
154 [SCSCR] = { 0x04, 8 },
155 [SCxTDR] = { 0x06, 8 },
156 [SCxSR] = { 0x08, 16 },
157 [SCxRDR] = { 0x0a, 8 },
158 [SCFCR] = { 0x0c, 8 },
159 [SCFDR] = { 0x0e, 16 },
160 },
161 .fifosize = 1,
162 .overrun_reg = SCxSR,
163 .overrun_mask = SCI_ORER,
164 .sampling_rate_mask = SCI_SR(32),
165 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
166 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
167 .param_bits = &sci_scif_port_params_bits,
168 .common_regs = &sci_common_regs,
169 },
170
171 /*
172 * Common SCIFA definitions.
173 */
174 [SCIx_SCIFA_REGTYPE] = {
175 .regs = {
176 [SCSMR] = { 0x00, 16 },
177 [SCBRR] = { 0x04, 8 },
178 [SCSCR] = { 0x08, 16 },
179 [SCxTDR] = { 0x20, 8 },
180 [SCxSR] = { 0x14, 16 },
181 [SCxRDR] = { 0x24, 8 },
182 [SCFCR] = { 0x18, 16 },
183 [SCFDR] = { 0x1c, 16 },
184 [SCPCR] = { 0x30, 16 },
185 [SCPDR] = { 0x34, 16 },
186 },
187 .fifosize = 64,
188 .overrun_reg = SCxSR,
189 .overrun_mask = SCIFA_ORER,
190 .sampling_rate_mask = SCI_SR_SCIFAB,
191 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
192 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
193 .param_bits = &sci_scif_port_params_bits,
194 .common_regs = &sci_common_regs,
195 },
196
197 /*
198 * Common SCIFB definitions.
199 */
200 [SCIx_SCIFB_REGTYPE] = {
201 .regs = {
202 [SCSMR] = { 0x00, 16 },
203 [SCBRR] = { 0x04, 8 },
204 [SCSCR] = { 0x08, 16 },
205 [SCxTDR] = { 0x40, 8 },
206 [SCxSR] = { 0x14, 16 },
207 [SCxRDR] = { 0x60, 8 },
208 [SCFCR] = { 0x18, 16 },
209 [SCTFDR] = { 0x38, 16 },
210 [SCRFDR] = { 0x3c, 16 },
211 [SCPCR] = { 0x30, 16 },
212 [SCPDR] = { 0x34, 16 },
213 },
214 .fifosize = 256,
215 .overrun_reg = SCxSR,
216 .overrun_mask = SCIFA_ORER,
217 .sampling_rate_mask = SCI_SR_SCIFAB,
218 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
219 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
220 .param_bits = &sci_scif_port_params_bits,
221 .common_regs = &sci_common_regs,
222 },
223
224 /*
225 * Common SH-2(A) SCIF definitions for ports with FIFO data
226 * count registers.
227 */
228 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
229 .regs = {
230 [SCSMR] = { 0x00, 16 },
231 [SCBRR] = { 0x04, 8 },
232 [SCSCR] = { 0x08, 16 },
233 [SCxTDR] = { 0x0c, 8 },
234 [SCxSR] = { 0x10, 16 },
235 [SCxRDR] = { 0x14, 8 },
236 [SCFCR] = { 0x18, 16 },
237 [SCFDR] = { 0x1c, 16 },
238 [SCSPTR] = { 0x20, 16 },
239 [SCLSR] = { 0x24, 16 },
240 },
241 .fifosize = 16,
242 .overrun_reg = SCLSR,
243 .overrun_mask = SCLSR_ORER,
244 .sampling_rate_mask = SCI_SR(32),
245 .error_mask = SCIF_DEFAULT_ERROR_MASK,
246 .error_clear = SCIF_ERROR_CLEAR,
247 .param_bits = &sci_scif_port_params_bits,
248 .common_regs = &sci_common_regs,
249 },
250
251 /*
252 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
253 * It looks like a normal SCIF with FIFO data, but with a
254 * compressed address space. Also, the break out of interrupts
255 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
256 */
257 [SCIx_RZ_SCIFA_REGTYPE] = {
258 .regs = {
259 [SCSMR] = { 0x00, 16 },
260 [SCBRR] = { 0x02, 8 },
261 [SCSCR] = { 0x04, 16 },
262 [SCxTDR] = { 0x06, 8 },
263 [SCxSR] = { 0x08, 16 },
264 [SCxRDR] = { 0x0A, 8 },
265 [SCFCR] = { 0x0C, 16 },
266 [SCFDR] = { 0x0E, 16 },
267 [SCSPTR] = { 0x10, 16 },
268 [SCLSR] = { 0x12, 16 },
269 [SEMR] = { 0x14, 8 },
270 },
271 .fifosize = 16,
272 .overrun_reg = SCLSR,
273 .overrun_mask = SCLSR_ORER,
274 .sampling_rate_mask = SCI_SR(32),
275 .error_mask = SCIF_DEFAULT_ERROR_MASK,
276 .error_clear = SCIF_ERROR_CLEAR,
277 .param_bits = &sci_scif_port_params_bits,
278 .common_regs = &sci_common_regs,
279 },
280
281 /*
282 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
283 * with below differences,
284 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
285 * TEI-DRI, RXI-EDGE and TXI-EDGE.
286 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
287 * - SCFCR register does not have SCFCR_MCE bit.
288 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
289 */
290 [SCIx_RZV2H_SCIF_REGTYPE] = {
291 .regs = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x02, 8 },
294 [SCSCR] = { 0x04, 16 },
295 [SCxTDR] = { 0x06, 8 },
296 [SCxSR] = { 0x08, 16 },
297 [SCxRDR] = { 0x0a, 8 },
298 [SCFCR] = { 0x0c, 16 },
299 [SCFDR] = { 0x0e, 16 },
300 [SCSPTR] = { 0x10, 16 },
301 [SCLSR] = { 0x12, 16 },
302 [SEMR] = { 0x14, 8 },
303 },
304 .fifosize = 16,
305 .overrun_reg = SCLSR,
306 .overrun_mask = SCLSR_ORER,
307 .sampling_rate_mask = SCI_SR(32),
308 .error_mask = SCIF_DEFAULT_ERROR_MASK,
309 .error_clear = SCIF_ERROR_CLEAR,
310 .param_bits = &sci_scif_port_params_bits,
311 .common_regs = &sci_common_regs,
312 },
313
314 /*
315 * Common SH-3 SCIF definitions.
316 */
317 [SCIx_SH3_SCIF_REGTYPE] = {
318 .regs = {
319 [SCSMR] = { 0x00, 8 },
320 [SCBRR] = { 0x02, 8 },
321 [SCSCR] = { 0x04, 8 },
322 [SCxTDR] = { 0x06, 8 },
323 [SCxSR] = { 0x08, 16 },
324 [SCxRDR] = { 0x0a, 8 },
325 [SCFCR] = { 0x0c, 8 },
326 [SCFDR] = { 0x0e, 16 },
327 },
328 .fifosize = 16,
329 .overrun_reg = SCLSR,
330 .overrun_mask = SCLSR_ORER,
331 .sampling_rate_mask = SCI_SR(32),
332 .error_mask = SCIF_DEFAULT_ERROR_MASK,
333 .error_clear = SCIF_ERROR_CLEAR,
334 .param_bits = &sci_scif_port_params_bits,
335 .common_regs = &sci_common_regs,
336 },
337
338 /*
339 * Common SH-4(A) SCIF(B) definitions.
340 */
341 [SCIx_SH4_SCIF_REGTYPE] = {
342 .regs = {
343 [SCSMR] = { 0x00, 16 },
344 [SCBRR] = { 0x04, 8 },
345 [SCSCR] = { 0x08, 16 },
346 [SCxTDR] = { 0x0c, 8 },
347 [SCxSR] = { 0x10, 16 },
348 [SCxRDR] = { 0x14, 8 },
349 [SCFCR] = { 0x18, 16 },
350 [SCFDR] = { 0x1c, 16 },
351 [SCSPTR] = { 0x20, 16 },
352 [SCLSR] = { 0x24, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 .param_bits = &sci_scif_port_params_bits,
361 .common_regs = &sci_common_regs,
362 },
363
364 /*
365 * Common SCIF definitions for ports with a Baud Rate Generator for
366 * External Clock (BRG).
367 */
368 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
369 .regs = {
370 [SCSMR] = { 0x00, 16 },
371 [SCBRR] = { 0x04, 8 },
372 [SCSCR] = { 0x08, 16 },
373 [SCxTDR] = { 0x0c, 8 },
374 [SCxSR] = { 0x10, 16 },
375 [SCxRDR] = { 0x14, 8 },
376 [SCFCR] = { 0x18, 16 },
377 [SCFDR] = { 0x1c, 16 },
378 [SCSPTR] = { 0x20, 16 },
379 [SCLSR] = { 0x24, 16 },
380 [SCDL] = { 0x30, 16 },
381 [SCCKS] = { 0x34, 16 },
382 },
383 .fifosize = 16,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR(32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 .param_bits = &sci_scif_port_params_bits,
390 .common_regs = &sci_common_regs,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 .param_bits = &sci_scif_port_params_bits,
421 .common_regs = &sci_common_regs,
422 },
423
424 /*
425 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
426 * register.
427 */
428 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
429 .regs = {
430 [SCSMR] = { 0x00, 16 },
431 [SCBRR] = { 0x04, 8 },
432 [SCSCR] = { 0x08, 16 },
433 [SCxTDR] = { 0x0c, 8 },
434 [SCxSR] = { 0x10, 16 },
435 [SCxRDR] = { 0x14, 8 },
436 [SCFCR] = { 0x18, 16 },
437 [SCFDR] = { 0x1c, 16 },
438 [SCLSR] = { 0x24, 16 },
439 },
440 .fifosize = 16,
441 .overrun_reg = SCLSR,
442 .overrun_mask = SCLSR_ORER,
443 .sampling_rate_mask = SCI_SR(32),
444 .error_mask = SCIF_DEFAULT_ERROR_MASK,
445 .error_clear = SCIF_ERROR_CLEAR,
446 .param_bits = &sci_scif_port_params_bits,
447 .common_regs = &sci_common_regs,
448 },
449
450 /*
451 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
452 * count registers.
453 */
454 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
455 .regs = {
456 [SCSMR] = { 0x00, 16 },
457 [SCBRR] = { 0x04, 8 },
458 [SCSCR] = { 0x08, 16 },
459 [SCxTDR] = { 0x0c, 8 },
460 [SCxSR] = { 0x10, 16 },
461 [SCxRDR] = { 0x14, 8 },
462 [SCFCR] = { 0x18, 16 },
463 [SCFDR] = { 0x1c, 16 },
464 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
465 [SCRFDR] = { 0x20, 16 },
466 [SCSPTR] = { 0x24, 16 },
467 [SCLSR] = { 0x28, 16 },
468 },
469 .fifosize = 16,
470 .overrun_reg = SCLSR,
471 .overrun_mask = SCLSR_ORER,
472 .sampling_rate_mask = SCI_SR(32),
473 .error_mask = SCIF_DEFAULT_ERROR_MASK,
474 .error_clear = SCIF_ERROR_CLEAR,
475 .param_bits = &sci_scif_port_params_bits,
476 .common_regs = &sci_common_regs,
477 },
478
479 /*
480 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
481 * registers.
482 */
483 [SCIx_SH7705_SCIF_REGTYPE] = {
484 .regs = {
485 [SCSMR] = { 0x00, 16 },
486 [SCBRR] = { 0x04, 8 },
487 [SCSCR] = { 0x08, 16 },
488 [SCxTDR] = { 0x20, 8 },
489 [SCxSR] = { 0x14, 16 },
490 [SCxRDR] = { 0x24, 8 },
491 [SCFCR] = { 0x18, 16 },
492 [SCFDR] = { 0x1c, 16 },
493 },
494 .fifosize = 64,
495 .overrun_reg = SCxSR,
496 .overrun_mask = SCIFA_ORER,
497 .sampling_rate_mask = SCI_SR(16),
498 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
499 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
500 .param_bits = &sci_scif_port_params_bits,
501 .common_regs = &sci_common_regs,
502 },
503 };
504
505 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
506
507 /*
508 * The "offset" here is rather misleading, in that it refers to an enum
509 * value relative to the port mapping rather than the fixed offset
510 * itself, which needs to be manually retrieved from the platform's
511 * register map for the given port.
512 */
sci_serial_in(struct uart_port * p,int offset)513 static unsigned int sci_serial_in(struct uart_port *p, int offset)
514 {
515 const struct plat_sci_reg *reg = sci_getreg(p, offset);
516
517 if (reg->size == 8)
518 return ioread8(p->membase + (reg->offset << p->regshift));
519 else if (reg->size == 16)
520 return ioread16(p->membase + (reg->offset << p->regshift));
521 else
522 WARN(1, "Invalid register access\n");
523
524 return 0;
525 }
526
sci_serial_out(struct uart_port * p,int offset,int value)527 static void sci_serial_out(struct uart_port *p, int offset, int value)
528 {
529 const struct plat_sci_reg *reg = sci_getreg(p, offset);
530
531 if (reg->size == 8)
532 iowrite8(value, p->membase + (reg->offset << p->regshift));
533 else if (reg->size == 16)
534 iowrite16(value, p->membase + (reg->offset << p->regshift));
535 else
536 WARN(1, "Invalid register access\n");
537 }
538
sci_port_enable(struct sci_port * sci_port)539 void sci_port_enable(struct sci_port *sci_port)
540 {
541 unsigned int i;
542
543 if (!sci_port->port.dev)
544 return;
545
546 pm_runtime_get_sync(sci_port->port.dev);
547
548 for (i = 0; i < SCI_NUM_CLKS; i++) {
549 clk_prepare_enable(sci_port->clks[i]);
550 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
551 }
552 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
553 }
554 EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI");
555
sci_port_disable(struct sci_port * sci_port)556 void sci_port_disable(struct sci_port *sci_port)
557 {
558 unsigned int i;
559
560 if (!sci_port->port.dev)
561 return;
562
563 for (i = SCI_NUM_CLKS; i-- > 0; )
564 clk_disable_unprepare(sci_port->clks[i]);
565
566 pm_runtime_put_sync(sci_port->port.dev);
567 }
568 EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI");
569
port_rx_irq_mask(struct uart_port * port)570 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
571 {
572 /*
573 * Not all ports (such as SCIFA) will support REIE. Rather than
574 * special-casing the port type, we check the port initialization
575 * IRQ enable mask to see whether the IRQ is desired at all. If
576 * it's unset, it's logically inferred that there's no point in
577 * testing for it.
578 */
579 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
580 }
581
sci_start_tx(struct uart_port * port)582 static void sci_start_tx(struct uart_port *port)
583 {
584 struct sci_port *s = to_sci_port(port);
585 unsigned short ctrl;
586
587 #ifdef CONFIG_SERIAL_SH_SCI_DMA
588 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
589 u16 new, scr = sci_serial_in(port, SCSCR);
590 if (s->chan_tx)
591 new = scr | SCSCR_TDRQE;
592 else
593 new = scr & ~SCSCR_TDRQE;
594 if (new != scr)
595 sci_serial_out(port, SCSCR, new);
596 }
597
598 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
599 dma_submit_error(s->cookie_tx)) {
600 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
601 /* Switch irq from SCIF to DMA */
602 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
603
604 s->cookie_tx = 0;
605 schedule_work(&s->work_tx);
606 }
607 #endif
608
609 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||
610 s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
611 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
612 ctrl = sci_serial_in(port, SCSCR);
613
614 /*
615 * For SCI, TE (transmit enable) must be set after setting TIE
616 * (transmit interrupt enable) or in the same instruction to start
617 * the transmit process.
618 */
619 if (s->type == PORT_SCI)
620 ctrl |= SCSCR_TE;
621
622 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
623 }
624 }
625
sci_stop_tx(struct uart_port * port)626 static void sci_stop_tx(struct uart_port *port)
627 {
628 struct sci_port *s = to_sci_port(port);
629 unsigned short ctrl;
630
631 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
632 ctrl = sci_serial_in(port, SCSCR);
633
634 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
635 ctrl &= ~SCSCR_TDRQE;
636
637 ctrl &= ~SCSCR_TIE;
638
639 sci_serial_out(port, SCSCR, ctrl);
640
641 #ifdef CONFIG_SERIAL_SH_SCI_DMA
642 if (s->chan_tx &&
643 !dma_submit_error(s->cookie_tx)) {
644 dmaengine_terminate_async(s->chan_tx);
645 s->cookie_tx = -EINVAL;
646 }
647 #endif
648 }
649
sci_start_rx(struct uart_port * port)650 static void sci_start_rx(struct uart_port *port)
651 {
652 struct sci_port *s = to_sci_port(port);
653 unsigned short ctrl;
654
655 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
656
657 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_RDRQE;
659
660 sci_serial_out(port, SCSCR, ctrl);
661 }
662
sci_stop_rx(struct uart_port * port)663 static void sci_stop_rx(struct uart_port *port)
664 {
665 struct sci_port *s = to_sci_port(port);
666 unsigned short ctrl;
667
668 ctrl = sci_serial_in(port, SCSCR);
669
670 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
671 ctrl &= ~SCSCR_RDRQE;
672
673 ctrl &= ~port_rx_irq_mask(port);
674
675 sci_serial_out(port, SCSCR, ctrl);
676 }
677
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)678 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
679 {
680 struct sci_port *s = to_sci_port(port);
681
682 if (s->type == PORT_SCI) {
683 /* Just store the mask */
684 sci_serial_out(port, SCxSR, mask);
685 } else if (s->params->overrun_mask == SCIFA_ORER) {
686 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
687 /* Only clear the status bits we want to clear */
688 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
689 } else {
690 /* Store the mask, clear parity/framing errors */
691 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
692 }
693 }
694
695 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
696 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
697
698 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)699 static int sci_poll_get_char(struct uart_port *port)
700 {
701 unsigned short status;
702 struct sci_port *s = to_sci_port(port);
703 int c;
704
705 do {
706 status = sci_serial_in(port, SCxSR);
707 if (status & SCxSR_ERRORS(port)) {
708 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
709 continue;
710 }
711 break;
712 } while (1);
713
714 if (!(status & SCxSR_RDxF(port)))
715 return NO_POLL_CHAR;
716
717 c = sci_serial_in(port, SCxRDR);
718
719 /* Dummy read */
720 sci_serial_in(port, SCxSR);
721 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
722
723 return c;
724 }
725 #endif
726
sci_poll_put_char(struct uart_port * port,unsigned char c)727 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
728 {
729 struct sci_port *s = to_sci_port(port);
730 const struct sci_common_regs *regs = s->params->common_regs;
731 unsigned int status;
732
733 do {
734 status = s->ops->read_reg(port, regs->status);
735 } while (!(status & SCxSR_TDxE(port)));
736
737 sci_serial_out(port, SCxTDR, c);
738 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
739 }
740 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
741 CONFIG_SERIAL_SH_SCI_EARLYCON */
742
sci_init_pins(struct uart_port * port,unsigned int cflag)743 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
744 {
745 struct sci_port *s = to_sci_port(port);
746
747 /*
748 * Use port-specific handler if provided.
749 */
750 if (s->cfg->ops && s->cfg->ops->init_pins) {
751 s->cfg->ops->init_pins(port, cflag);
752 return;
753 }
754
755 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
756 u16 data = sci_serial_in(port, SCPDR);
757 u16 ctrl = sci_serial_in(port, SCPCR);
758
759 /* Enable RXD and TXD pin functions */
760 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
761 if (s->has_rtscts) {
762 /* RTS# is output, active low, unless autorts */
763 if (!(port->mctrl & TIOCM_RTS)) {
764 ctrl |= SCPCR_RTSC;
765 data |= SCPDR_RTSD;
766 } else if (!s->autorts) {
767 ctrl |= SCPCR_RTSC;
768 data &= ~SCPDR_RTSD;
769 } else {
770 /* Enable RTS# pin function */
771 ctrl &= ~SCPCR_RTSC;
772 }
773 /* Enable CTS# pin function */
774 ctrl &= ~SCPCR_CTSC;
775 }
776 sci_serial_out(port, SCPDR, data);
777 sci_serial_out(port, SCPCR, ctrl);
778 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
779 u16 status = sci_serial_in(port, SCSPTR);
780
781 /* RTS# is always output; and active low, unless autorts */
782 status |= SCSPTR_RTSIO;
783 if (!(port->mctrl & TIOCM_RTS))
784 status |= SCSPTR_RTSDT;
785 else if (!s->autorts)
786 status &= ~SCSPTR_RTSDT;
787 /* CTS# and SCK are inputs */
788 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
789 sci_serial_out(port, SCSPTR, status);
790 }
791 }
792
sci_txfill(struct uart_port * port)793 static int sci_txfill(struct uart_port *port)
794 {
795 struct sci_port *s = to_sci_port(port);
796 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
797 const struct plat_sci_reg *reg;
798
799 reg = sci_getreg(port, SCTFDR);
800 if (reg->size)
801 return sci_serial_in(port, SCTFDR) & fifo_mask;
802
803 reg = sci_getreg(port, SCFDR);
804 if (reg->size)
805 return sci_serial_in(port, SCFDR) >> 8;
806
807 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
808 }
809
sci_txroom(struct uart_port * port)810 static int sci_txroom(struct uart_port *port)
811 {
812 return port->fifosize - sci_txfill(port);
813 }
814
sci_rxfill(struct uart_port * port)815 static int sci_rxfill(struct uart_port *port)
816 {
817 struct sci_port *s = to_sci_port(port);
818 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
819 const struct plat_sci_reg *reg;
820
821 reg = sci_getreg(port, SCRFDR);
822 if (reg->size)
823 return sci_serial_in(port, SCRFDR) & fifo_mask;
824
825 reg = sci_getreg(port, SCFDR);
826 if (reg->size)
827 return sci_serial_in(port, SCFDR) & fifo_mask;
828
829 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
830 }
831
832 /* ********************************************************************** *
833 * the interrupt related routines *
834 * ********************************************************************** */
835
sci_transmit_chars(struct uart_port * port)836 static void sci_transmit_chars(struct uart_port *port)
837 {
838 struct tty_port *tport = &port->state->port;
839 unsigned int stopped = uart_tx_stopped(port);
840 struct sci_port *s = to_sci_port(port);
841 unsigned short status;
842 unsigned short ctrl;
843 int count;
844
845 status = sci_serial_in(port, SCxSR);
846 if (!(status & SCxSR_TDxE(port))) {
847 ctrl = sci_serial_in(port, SCSCR);
848 if (kfifo_is_empty(&tport->xmit_fifo))
849 ctrl &= ~SCSCR_TIE;
850 else
851 ctrl |= SCSCR_TIE;
852 sci_serial_out(port, SCSCR, ctrl);
853 return;
854 }
855
856 count = sci_txroom(port);
857
858 do {
859 unsigned char c;
860
861 if (port->x_char) {
862 c = port->x_char;
863 port->x_char = 0;
864 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
865 if (s->type == PORT_SCI &&
866 kfifo_is_empty(&tport->xmit_fifo)) {
867 ctrl = sci_serial_in(port, SCSCR);
868 ctrl &= ~SCSCR_TE;
869 sci_serial_out(port, SCSCR, ctrl);
870 return;
871 }
872 break;
873 }
874
875 sci_serial_out(port, SCxTDR, c);
876 s->tx_occurred = true;
877
878 port->icount.tx++;
879 } while (--count > 0);
880
881 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
882
883 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
884 uart_write_wakeup(port);
885 if (kfifo_is_empty(&tport->xmit_fifo)) {
886 if (s->type == PORT_SCI) {
887 ctrl = sci_serial_in(port, SCSCR);
888 ctrl &= ~SCSCR_TIE;
889 ctrl |= SCSCR_TEIE;
890 sci_serial_out(port, SCSCR, ctrl);
891 }
892
893 sci_stop_tx(port);
894 }
895 }
896
sci_receive_chars(struct uart_port * port)897 static void sci_receive_chars(struct uart_port *port)
898 {
899 struct tty_port *tport = &port->state->port;
900 struct sci_port *s = to_sci_port(port);
901 int i, count, copied = 0;
902 unsigned short status;
903 unsigned char flag;
904
905 status = sci_serial_in(port, SCxSR);
906 if (!(status & SCxSR_RDxF(port)))
907 return;
908
909 while (1) {
910 /* Don't copy more bytes than there is room for in the buffer */
911 count = tty_buffer_request_room(tport, sci_rxfill(port));
912
913 /* If for any reason we can't copy more data, we're done! */
914 if (count == 0)
915 break;
916
917 if (s->type == PORT_SCI) {
918 char c = sci_serial_in(port, SCxRDR);
919 if (uart_handle_sysrq_char(port, c))
920 count = 0;
921 else
922 tty_insert_flip_char(tport, c, TTY_NORMAL);
923 } else {
924 for (i = 0; i < count; i++) {
925 char c;
926
927 if (s->type == PORT_SCIF ||
928 s->type == PORT_HSCIF) {
929 status = sci_serial_in(port, SCxSR);
930 c = sci_serial_in(port, SCxRDR);
931 } else {
932 c = sci_serial_in(port, SCxRDR);
933 status = sci_serial_in(port, SCxSR);
934 }
935 if (uart_handle_sysrq_char(port, c)) {
936 count--; i--;
937 continue;
938 }
939
940 /* Store data and status */
941 if (status & SCxSR_FER(port)) {
942 flag = TTY_FRAME;
943 port->icount.frame++;
944 } else if (status & SCxSR_PER(port)) {
945 flag = TTY_PARITY;
946 port->icount.parity++;
947 } else
948 flag = TTY_NORMAL;
949
950 tty_insert_flip_char(tport, c, flag);
951 }
952 }
953
954 sci_serial_in(port, SCxSR); /* dummy read */
955 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
956
957 copied += count;
958 port->icount.rx += count;
959 }
960
961 if (copied) {
962 /* Tell the rest of the system the news. New characters! */
963 tty_flip_buffer_push(tport);
964 } else {
965 /* TTY buffers full; read from RX reg to prevent lockup */
966 sci_serial_in(port, SCxRDR);
967 sci_serial_in(port, SCxSR); /* dummy read */
968 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
969 }
970 }
971
sci_handle_errors(struct uart_port * port)972 static int sci_handle_errors(struct uart_port *port)
973 {
974 int copied = 0;
975 struct sci_port *s = to_sci_port(port);
976 const struct sci_common_regs *regs = s->params->common_regs;
977 unsigned int status = s->ops->read_reg(port, regs->status);
978 struct tty_port *tport = &port->state->port;
979
980 /* Handle overruns */
981 if (status & s->params->overrun_mask) {
982 port->icount.overrun++;
983
984 /* overrun error */
985 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
986 copied++;
987 }
988
989 if (status & SCxSR_FER(port)) {
990 /* frame error */
991 port->icount.frame++;
992
993 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
994 copied++;
995 }
996
997 if (status & SCxSR_PER(port)) {
998 /* parity error */
999 port->icount.parity++;
1000
1001 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1002 copied++;
1003 }
1004
1005 if (copied)
1006 tty_flip_buffer_push(tport);
1007
1008 return copied;
1009 }
1010
sci_handle_fifo_overrun(struct uart_port * port)1011 static int sci_handle_fifo_overrun(struct uart_port *port)
1012 {
1013 struct tty_port *tport = &port->state->port;
1014 struct sci_port *s = to_sci_port(port);
1015 const struct plat_sci_reg *reg;
1016 int copied = 0;
1017 u16 status;
1018
1019 reg = sci_getreg(port, s->params->overrun_reg);
1020 if (!reg->size)
1021 return 0;
1022
1023 status = sci_serial_in(port, s->params->overrun_reg);
1024 if (status & s->params->overrun_mask) {
1025 status &= ~s->params->overrun_mask;
1026 sci_serial_out(port, s->params->overrun_reg, status);
1027
1028 port->icount.overrun++;
1029
1030 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1031 tty_flip_buffer_push(tport);
1032 copied++;
1033 }
1034
1035 return copied;
1036 }
1037
sci_handle_breaks(struct uart_port * port)1038 static int sci_handle_breaks(struct uart_port *port)
1039 {
1040 int copied = 0;
1041 unsigned short status = sci_serial_in(port, SCxSR);
1042 struct tty_port *tport = &port->state->port;
1043
1044 if (uart_handle_break(port))
1045 return 0;
1046
1047 if (status & SCxSR_BRK(port)) {
1048 port->icount.brk++;
1049
1050 /* Notify of BREAK */
1051 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1052 copied++;
1053 }
1054
1055 if (copied)
1056 tty_flip_buffer_push(tport);
1057
1058 copied += sci_handle_fifo_overrun(port);
1059
1060 return copied;
1061 }
1062
scif_set_rtrg(struct uart_port * port,int rx_trig)1063 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1064 {
1065 struct sci_port *s = to_sci_port(port);
1066 unsigned int bits;
1067
1068 if (rx_trig >= port->fifosize)
1069 rx_trig = port->fifosize - 1;
1070 if (rx_trig < 1)
1071 rx_trig = 1;
1072
1073 /* HSCIF can be set to an arbitrary level. */
1074 if (sci_getreg(port, HSRTRGR)->size) {
1075 sci_serial_out(port, HSRTRGR, rx_trig);
1076 return rx_trig;
1077 }
1078
1079 switch (s->type) {
1080 case PORT_SCIF:
1081 if (rx_trig < 4) {
1082 bits = 0;
1083 rx_trig = 1;
1084 } else if (rx_trig < 8) {
1085 bits = SCFCR_RTRG0;
1086 rx_trig = 4;
1087 } else if (rx_trig < 14) {
1088 bits = SCFCR_RTRG1;
1089 rx_trig = 8;
1090 } else {
1091 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1092 rx_trig = 14;
1093 }
1094 break;
1095 case PORT_SCIFA:
1096 case PORT_SCIFB:
1097 if (rx_trig < 16) {
1098 bits = 0;
1099 rx_trig = 1;
1100 } else if (rx_trig < 32) {
1101 bits = SCFCR_RTRG0;
1102 rx_trig = 16;
1103 } else if (rx_trig < 48) {
1104 bits = SCFCR_RTRG1;
1105 rx_trig = 32;
1106 } else {
1107 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1108 rx_trig = 48;
1109 }
1110 break;
1111 default:
1112 WARN(1, "unknown FIFO configuration");
1113 return 1;
1114 }
1115
1116 sci_serial_out(port, SCFCR,
1117 (sci_serial_in(port, SCFCR) &
1118 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1119
1120 return rx_trig;
1121 }
1122
scif_rtrg_enabled(struct uart_port * port)1123 static int scif_rtrg_enabled(struct uart_port *port)
1124 {
1125 if (sci_getreg(port, HSRTRGR)->size)
1126 return sci_serial_in(port, HSRTRGR) != 0;
1127 else
1128 return (sci_serial_in(port, SCFCR) &
1129 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1130 }
1131
rx_fifo_timer_fn(struct timer_list * t)1132 static void rx_fifo_timer_fn(struct timer_list *t)
1133 {
1134 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer);
1135 struct uart_port *port = &s->port;
1136
1137 dev_dbg(port->dev, "Rx timed out\n");
1138 s->ops->set_rtrg(port, 1);
1139 }
1140
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1141 static ssize_t rx_fifo_trigger_show(struct device *dev,
1142 struct device_attribute *attr, char *buf)
1143 {
1144 struct uart_port *port = dev_get_drvdata(dev);
1145 struct sci_port *sci = to_sci_port(port);
1146
1147 return sprintf(buf, "%d\n", sci->rx_trigger);
1148 }
1149
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1150 static ssize_t rx_fifo_trigger_store(struct device *dev,
1151 struct device_attribute *attr,
1152 const char *buf, size_t count)
1153 {
1154 struct uart_port *port = dev_get_drvdata(dev);
1155 struct sci_port *sci = to_sci_port(port);
1156 int ret;
1157 long r;
1158
1159 ret = kstrtol(buf, 0, &r);
1160 if (ret)
1161 return ret;
1162
1163 sci->rx_trigger = sci->ops->set_rtrg(port, r);
1164 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB)
1165 sci->ops->set_rtrg(port, 1);
1166
1167 return count;
1168 }
1169
1170 static DEVICE_ATTR_RW(rx_fifo_trigger);
1171
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1172 static ssize_t rx_fifo_timeout_show(struct device *dev,
1173 struct device_attribute *attr,
1174 char *buf)
1175 {
1176 struct uart_port *port = dev_get_drvdata(dev);
1177 struct sci_port *sci = to_sci_port(port);
1178 int v;
1179
1180 if (sci->type == PORT_HSCIF)
1181 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1182 else
1183 v = sci->rx_fifo_timeout;
1184
1185 return sprintf(buf, "%d\n", v);
1186 }
1187
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1188 static ssize_t rx_fifo_timeout_store(struct device *dev,
1189 struct device_attribute *attr,
1190 const char *buf,
1191 size_t count)
1192 {
1193 struct uart_port *port = dev_get_drvdata(dev);
1194 struct sci_port *sci = to_sci_port(port);
1195 int ret;
1196 long r;
1197
1198 ret = kstrtol(buf, 0, &r);
1199 if (ret)
1200 return ret;
1201
1202 if (sci->type == PORT_HSCIF) {
1203 if (r < 0 || r > 3)
1204 return -EINVAL;
1205 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1206 } else {
1207 sci->rx_fifo_timeout = r;
1208 sci->ops->set_rtrg(port, 1);
1209 if (r > 0)
1210 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1211 }
1212
1213 return count;
1214 }
1215
1216 static DEVICE_ATTR_RW(rx_fifo_timeout);
1217
1218
1219 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1220 static void sci_dma_tx_complete(void *arg)
1221 {
1222 struct sci_port *s = arg;
1223 struct uart_port *port = &s->port;
1224 struct tty_port *tport = &port->state->port;
1225 unsigned long flags;
1226
1227 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1228
1229 uart_port_lock_irqsave(port, &flags);
1230
1231 uart_xmit_advance(port, s->tx_dma_len);
1232
1233 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1234 uart_write_wakeup(port);
1235
1236 s->tx_occurred = true;
1237
1238 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1239 s->cookie_tx = 0;
1240 schedule_work(&s->work_tx);
1241 } else {
1242 s->cookie_tx = -EINVAL;
1243 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1244 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1245 u16 ctrl = sci_serial_in(port, SCSCR);
1246 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1247 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1248 /* Switch irq from DMA to SCIF */
1249 dmaengine_pause(s->chan_tx_saved);
1250 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1251 }
1252 }
1253 }
1254
1255 uart_port_unlock_irqrestore(port, flags);
1256 }
1257
1258 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1259 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1260 {
1261 struct uart_port *port = &s->port;
1262 struct tty_port *tport = &port->state->port;
1263 int copied;
1264
1265 copied = tty_insert_flip_string(tport, buf, count);
1266 if (copied < count)
1267 port->icount.buf_overrun++;
1268
1269 port->icount.rx += copied;
1270
1271 return copied;
1272 }
1273
sci_dma_rx_find_active(struct sci_port * s)1274 static int sci_dma_rx_find_active(struct sci_port *s)
1275 {
1276 unsigned int i;
1277
1278 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1279 if (s->active_rx == s->cookie_rx[i])
1280 return i;
1281
1282 return -1;
1283 }
1284
1285 /* Must only be called with uart_port_lock taken */
sci_dma_rx_chan_invalidate(struct sci_port * s)1286 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1287 {
1288 unsigned int i;
1289
1290 s->chan_rx = NULL;
1291 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1292 s->cookie_rx[i] = -EINVAL;
1293 s->active_rx = 0;
1294 }
1295
sci_dma_rx_release(struct sci_port * s)1296 static void sci_dma_rx_release(struct sci_port *s)
1297 {
1298 struct dma_chan *chan = s->chan_rx_saved;
1299 struct uart_port *port = &s->port;
1300 unsigned long flags;
1301
1302 uart_port_lock_irqsave(port, &flags);
1303 s->chan_rx_saved = NULL;
1304 sci_dma_rx_chan_invalidate(s);
1305 uart_port_unlock_irqrestore(port, flags);
1306
1307 dmaengine_terminate_sync(chan);
1308 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1309 sg_dma_address(&s->sg_rx[0]));
1310 dma_release_channel(chan);
1311 }
1312
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1313 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1314 {
1315 long sec = usec / 1000000;
1316 long nsec = (usec % 1000000) * 1000;
1317 ktime_t t = ktime_set(sec, nsec);
1318
1319 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1320 }
1321
sci_dma_rx_reenable_irq(struct sci_port * s)1322 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1323 {
1324 struct uart_port *port = &s->port;
1325 u16 scr;
1326
1327 /* Direct new serial port interrupts back to CPU */
1328 scr = sci_serial_in(port, SCSCR);
1329 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1330 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1331 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1332 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1333 s->ops->set_rtrg(port, s->rx_trigger);
1334 else
1335 scr &= ~SCSCR_RDRQE;
1336 }
1337 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1338 }
1339
sci_dma_rx_complete(void * arg)1340 static void sci_dma_rx_complete(void *arg)
1341 {
1342 struct sci_port *s = arg;
1343 struct dma_chan *chan = s->chan_rx;
1344 struct uart_port *port = &s->port;
1345 struct dma_async_tx_descriptor *desc;
1346 unsigned long flags;
1347 int active, count = 0;
1348
1349 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1350 s->active_rx);
1351
1352 hrtimer_cancel(&s->rx_timer);
1353
1354 uart_port_lock_irqsave(port, &flags);
1355
1356 active = sci_dma_rx_find_active(s);
1357 if (active >= 0)
1358 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1359
1360 if (count)
1361 tty_flip_buffer_push(&port->state->port);
1362
1363 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1364 DMA_DEV_TO_MEM,
1365 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1366 if (!desc)
1367 goto fail;
1368
1369 desc->callback = sci_dma_rx_complete;
1370 desc->callback_param = s;
1371 s->cookie_rx[active] = dmaengine_submit(desc);
1372 if (dma_submit_error(s->cookie_rx[active]))
1373 goto fail;
1374
1375 s->active_rx = s->cookie_rx[!active];
1376
1377 dma_async_issue_pending(chan);
1378
1379 uart_port_unlock_irqrestore(port, flags);
1380 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1381 __func__, s->cookie_rx[active], active, s->active_rx);
1382
1383 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1384
1385 return;
1386
1387 fail:
1388 /* Switch to PIO */
1389 dmaengine_terminate_async(chan);
1390 sci_dma_rx_chan_invalidate(s);
1391 sci_dma_rx_reenable_irq(s);
1392 uart_port_unlock_irqrestore(port, flags);
1393 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1394 }
1395
sci_dma_tx_release(struct sci_port * s)1396 static void sci_dma_tx_release(struct sci_port *s)
1397 {
1398 struct dma_chan *chan = s->chan_tx_saved;
1399
1400 cancel_work_sync(&s->work_tx);
1401 s->chan_tx_saved = s->chan_tx = NULL;
1402 s->cookie_tx = -EINVAL;
1403 dmaengine_terminate_sync(chan);
1404 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1405 DMA_TO_DEVICE);
1406 dma_release_channel(chan);
1407 }
1408
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1409 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1410 {
1411 struct dma_chan *chan = s->chan_rx;
1412 struct uart_port *port = &s->port;
1413 unsigned long flags;
1414 int i;
1415
1416 for (i = 0; i < 2; i++) {
1417 struct scatterlist *sg = &s->sg_rx[i];
1418 struct dma_async_tx_descriptor *desc;
1419
1420 desc = dmaengine_prep_slave_sg(chan,
1421 sg, 1, DMA_DEV_TO_MEM,
1422 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1423 if (!desc)
1424 goto fail;
1425
1426 desc->callback = sci_dma_rx_complete;
1427 desc->callback_param = s;
1428 s->cookie_rx[i] = dmaengine_submit(desc);
1429 if (dma_submit_error(s->cookie_rx[i]))
1430 goto fail;
1431
1432 }
1433
1434 s->active_rx = s->cookie_rx[0];
1435
1436 dma_async_issue_pending(chan);
1437 return 0;
1438
1439 fail:
1440 /* Switch to PIO */
1441 if (!port_lock_held)
1442 uart_port_lock_irqsave(port, &flags);
1443 if (i)
1444 dmaengine_terminate_async(chan);
1445 sci_dma_rx_chan_invalidate(s);
1446 sci_start_rx(port);
1447 if (!port_lock_held)
1448 uart_port_unlock_irqrestore(port, flags);
1449 return -EAGAIN;
1450 }
1451
sci_dma_tx_work_fn(struct work_struct * work)1452 static void sci_dma_tx_work_fn(struct work_struct *work)
1453 {
1454 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1455 struct dma_async_tx_descriptor *desc;
1456 struct dma_chan *chan = s->chan_tx;
1457 struct uart_port *port = &s->port;
1458 struct tty_port *tport = &port->state->port;
1459 unsigned long flags;
1460 unsigned int tail;
1461 dma_addr_t buf;
1462
1463 /*
1464 * DMA is idle now.
1465 * Port xmit buffer is already mapped, and it is one page... Just adjust
1466 * offsets and lengths. Since it is a circular buffer, we have to
1467 * transmit till the end, and then the rest. Take the port lock to get a
1468 * consistent xmit buffer state.
1469 */
1470 uart_port_lock_irq(port);
1471 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1472 UART_XMIT_SIZE);
1473 buf = s->tx_dma_addr + tail;
1474 if (!s->tx_dma_len) {
1475 /* Transmit buffer has been flushed */
1476 uart_port_unlock_irq(port);
1477 return;
1478 }
1479
1480 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1481 DMA_MEM_TO_DEV,
1482 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1483 if (!desc) {
1484 uart_port_unlock_irq(port);
1485 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1486 goto switch_to_pio;
1487 }
1488
1489 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1490 DMA_TO_DEVICE);
1491
1492 desc->callback = sci_dma_tx_complete;
1493 desc->callback_param = s;
1494 s->cookie_tx = dmaengine_submit(desc);
1495 if (dma_submit_error(s->cookie_tx)) {
1496 uart_port_unlock_irq(port);
1497 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1498 goto switch_to_pio;
1499 }
1500
1501 uart_port_unlock_irq(port);
1502 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1503 __func__, tport->xmit_buf, tail, s->cookie_tx);
1504
1505 dma_async_issue_pending(chan);
1506 return;
1507
1508 switch_to_pio:
1509 uart_port_lock_irqsave(port, &flags);
1510 s->chan_tx = NULL;
1511 sci_start_tx(port);
1512 uart_port_unlock_irqrestore(port, flags);
1513 return;
1514 }
1515
sci_dma_rx_timer_fn(struct hrtimer * t)1516 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1517 {
1518 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1519 struct dma_chan *chan = s->chan_rx;
1520 struct uart_port *port = &s->port;
1521 struct dma_tx_state state;
1522 enum dma_status status;
1523 unsigned long flags;
1524 unsigned int read;
1525 int active, count;
1526
1527 dev_dbg(port->dev, "DMA Rx timed out\n");
1528
1529 uart_port_lock_irqsave(port, &flags);
1530
1531 active = sci_dma_rx_find_active(s);
1532 if (active < 0) {
1533 uart_port_unlock_irqrestore(port, flags);
1534 return HRTIMER_NORESTART;
1535 }
1536
1537 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1538 if (status == DMA_COMPLETE) {
1539 uart_port_unlock_irqrestore(port, flags);
1540 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1541 s->active_rx, active);
1542
1543 /* Let packet complete handler take care of the packet */
1544 return HRTIMER_NORESTART;
1545 }
1546
1547 dmaengine_pause(chan);
1548
1549 /*
1550 * sometimes DMA transfer doesn't stop even if it is stopped and
1551 * data keeps on coming until transaction is complete so check
1552 * for DMA_COMPLETE again
1553 * Let packet complete handler take care of the packet
1554 */
1555 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1556 if (status == DMA_COMPLETE) {
1557 uart_port_unlock_irqrestore(port, flags);
1558 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1559 return HRTIMER_NORESTART;
1560 }
1561
1562 /* Handle incomplete DMA receive */
1563 dmaengine_terminate_async(s->chan_rx);
1564 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1565
1566 if (read) {
1567 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1568 if (count)
1569 tty_flip_buffer_push(&port->state->port);
1570 }
1571
1572 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1573 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1574 sci_dma_rx_submit(s, true);
1575
1576 sci_dma_rx_reenable_irq(s);
1577
1578 uart_port_unlock_irqrestore(port, flags);
1579
1580 return HRTIMER_NORESTART;
1581 }
1582
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1583 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1584 enum dma_transfer_direction dir)
1585 {
1586 struct dma_chan *chan;
1587 struct dma_slave_config cfg;
1588 int ret;
1589
1590 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1591 if (IS_ERR(chan)) {
1592 dev_dbg(port->dev, "dma_request_chan failed\n");
1593 return NULL;
1594 }
1595
1596 memset(&cfg, 0, sizeof(cfg));
1597 cfg.direction = dir;
1598 cfg.dst_addr = port->mapbase +
1599 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1600 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1601 cfg.src_addr = port->mapbase +
1602 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1603 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1604
1605 ret = dmaengine_slave_config(chan, &cfg);
1606 if (ret) {
1607 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1608 dma_release_channel(chan);
1609 return NULL;
1610 }
1611
1612 return chan;
1613 }
1614
sci_request_dma(struct uart_port * port)1615 static void sci_request_dma(struct uart_port *port)
1616 {
1617 struct sci_port *s = to_sci_port(port);
1618 struct tty_port *tport = &port->state->port;
1619 struct dma_chan *chan;
1620
1621 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1622
1623 /*
1624 * DMA on console may interfere with Kernel log messages which use
1625 * plain putchar(). So, simply don't use it with a console.
1626 */
1627 if (uart_console(port))
1628 return;
1629
1630 if (!port->dev->of_node)
1631 return;
1632
1633 s->cookie_tx = -EINVAL;
1634
1635 /*
1636 * Don't request a dma channel if no channel was specified
1637 * in the device tree.
1638 */
1639 if (!of_property_present(port->dev->of_node, "dmas"))
1640 return;
1641
1642 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1643 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1644 if (chan) {
1645 /* UART circular tx buffer is an aligned page. */
1646 s->tx_dma_addr = dma_map_single(chan->device->dev,
1647 tport->xmit_buf,
1648 UART_XMIT_SIZE,
1649 DMA_TO_DEVICE);
1650 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1651 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1652 dma_release_channel(chan);
1653 } else {
1654 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1655 __func__, UART_XMIT_SIZE,
1656 tport->xmit_buf, &s->tx_dma_addr);
1657
1658 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1659 s->chan_tx_saved = s->chan_tx = chan;
1660 }
1661 }
1662
1663 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1664 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1665 if (chan) {
1666 unsigned int i;
1667 dma_addr_t dma;
1668 void *buf;
1669
1670 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1671 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1672 &dma, GFP_KERNEL);
1673 if (!buf) {
1674 dev_warn(port->dev,
1675 "Failed to allocate Rx dma buffer, using PIO\n");
1676 dma_release_channel(chan);
1677 return;
1678 }
1679
1680 for (i = 0; i < 2; i++) {
1681 struct scatterlist *sg = &s->sg_rx[i];
1682
1683 sg_init_table(sg, 1);
1684 s->rx_buf[i] = buf;
1685 sg_dma_address(sg) = dma;
1686 sg_dma_len(sg) = s->buf_len_rx;
1687
1688 buf += s->buf_len_rx;
1689 dma += s->buf_len_rx;
1690 }
1691
1692 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1693
1694 s->chan_rx_saved = s->chan_rx = chan;
1695
1696 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1697 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1698 sci_dma_rx_submit(s, false);
1699 }
1700 }
1701
sci_free_dma(struct uart_port * port)1702 static void sci_free_dma(struct uart_port *port)
1703 {
1704 struct sci_port *s = to_sci_port(port);
1705
1706 if (s->chan_tx_saved)
1707 sci_dma_tx_release(s);
1708 if (s->chan_rx_saved)
1709 sci_dma_rx_release(s);
1710 }
1711
sci_flush_buffer(struct uart_port * port)1712 static void sci_flush_buffer(struct uart_port *port)
1713 {
1714 struct sci_port *s = to_sci_port(port);
1715
1716 /*
1717 * In uart_flush_buffer(), the xmit circular buffer has just been
1718 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1719 * pending transfers
1720 */
1721 s->tx_dma_len = 0;
1722 if (s->chan_tx) {
1723 dmaengine_terminate_async(s->chan_tx);
1724 s->cookie_tx = -EINVAL;
1725 }
1726 }
1727
sci_dma_check_tx_occurred(struct sci_port * s)1728 static void sci_dma_check_tx_occurred(struct sci_port *s)
1729 {
1730 struct dma_tx_state state;
1731 enum dma_status status;
1732
1733 if (!s->chan_tx)
1734 return;
1735
1736 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1737 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1738 s->tx_occurred = true;
1739 }
1740 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1741 static inline void sci_request_dma(struct uart_port *port)
1742 {
1743 }
1744
sci_free_dma(struct uart_port * port)1745 static inline void sci_free_dma(struct uart_port *port)
1746 {
1747 }
1748
sci_dma_check_tx_occurred(struct sci_port * s)1749 static void sci_dma_check_tx_occurred(struct sci_port *s)
1750 {
1751 }
1752
1753 #define sci_flush_buffer NULL
1754 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1755
sci_rx_interrupt(int irq,void * ptr)1756 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1757 {
1758 struct uart_port *port = ptr;
1759 struct sci_port *s = to_sci_port(port);
1760
1761 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1762 if (s->chan_rx) {
1763 u16 scr = sci_serial_in(port, SCSCR);
1764 u16 ssr = sci_serial_in(port, SCxSR);
1765
1766 /* Disable future Rx interrupts */
1767 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1768 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1769 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1770 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1771 s->ops->set_rtrg(port, 1);
1772 scr |= SCSCR_RIE;
1773 } else {
1774 scr |= SCSCR_RDRQE;
1775 }
1776 } else {
1777 if (sci_dma_rx_submit(s, false) < 0)
1778 goto handle_pio;
1779
1780 scr &= ~SCSCR_RIE;
1781 }
1782 sci_serial_out(port, SCSCR, scr);
1783 /* Clear current interrupt */
1784 sci_serial_out(port, SCxSR,
1785 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1786 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1787 jiffies, s->rx_timeout);
1788 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1789
1790 return IRQ_HANDLED;
1791 }
1792
1793 handle_pio:
1794 #endif
1795
1796 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1797 if (!s->ops->rtrg_enabled(port))
1798 s->ops->set_rtrg(port, s->rx_trigger);
1799
1800 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1801 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1802 }
1803
1804 /* I think sci_receive_chars has to be called irrespective
1805 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1806 * to be disabled?
1807 */
1808 s->ops->receive_chars(port);
1809
1810 return IRQ_HANDLED;
1811 }
1812
sci_tx_interrupt(int irq,void * ptr)1813 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1814 {
1815 struct uart_port *port = ptr;
1816 unsigned long flags;
1817 struct sci_port *s = to_sci_port(port);
1818
1819 uart_port_lock_irqsave(port, &flags);
1820 s->ops->transmit_chars(port);
1821 uart_port_unlock_irqrestore(port, flags);
1822
1823 return IRQ_HANDLED;
1824 }
1825
sci_tx_end_interrupt(int irq,void * ptr)1826 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1827 {
1828 struct uart_port *port = ptr;
1829 struct sci_port *s = to_sci_port(port);
1830 const struct sci_common_regs *regs = s->params->common_regs;
1831 unsigned long flags;
1832 u32 ctrl;
1833
1834 if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI)
1835 return sci_tx_interrupt(irq, ptr);
1836
1837 uart_port_lock_irqsave(port, &flags);
1838 ctrl = s->ops->read_reg(port, regs->control) &
1839 ~(s->params->param_bits->te_clear);
1840 s->ops->write_reg(port, regs->control, ctrl);
1841 uart_port_unlock_irqrestore(port, flags);
1842
1843 return IRQ_HANDLED;
1844 }
1845
sci_br_interrupt(int irq,void * ptr)1846 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1847 {
1848 struct uart_port *port = ptr;
1849 struct sci_port *s = to_sci_port(port);
1850
1851 /* Handle BREAKs */
1852 sci_handle_breaks(port);
1853
1854 /* drop invalid character received before break was detected */
1855 sci_serial_in(port, SCxRDR);
1856
1857 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1858
1859 return IRQ_HANDLED;
1860 }
1861
sci_er_interrupt(int irq,void * ptr)1862 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1863 {
1864 struct uart_port *port = ptr;
1865 struct sci_port *s = to_sci_port(port);
1866
1867 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1868 /* Break and Error interrupts are muxed */
1869 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1870
1871 /* Break Interrupt */
1872 if (ssr_status & SCxSR_BRK(port))
1873 sci_br_interrupt(irq, ptr);
1874
1875 /* Break only? */
1876 if (!(ssr_status & SCxSR_ERRORS(port)))
1877 return IRQ_HANDLED;
1878 }
1879
1880 /* Handle errors */
1881 if (s->type == PORT_SCI) {
1882 if (sci_handle_errors(port)) {
1883 /* discard character in rx buffer */
1884 sci_serial_in(port, SCxSR);
1885 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1886 }
1887 } else {
1888 sci_handle_fifo_overrun(port);
1889 if (!s->chan_rx)
1890 s->ops->receive_chars(port);
1891 }
1892
1893 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1894
1895 /* Kick the transmission */
1896 if (!s->chan_tx)
1897 sci_tx_interrupt(irq, ptr);
1898
1899 return IRQ_HANDLED;
1900 }
1901
sci_mpxed_interrupt(int irq,void * ptr)1902 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1903 {
1904 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1905 struct uart_port *port = ptr;
1906 struct sci_port *s = to_sci_port(port);
1907 irqreturn_t ret = IRQ_NONE;
1908
1909 ssr_status = sci_serial_in(port, SCxSR);
1910 scr_status = sci_serial_in(port, SCSCR);
1911 if (s->params->overrun_reg == SCxSR)
1912 orer_status = ssr_status;
1913 else if (sci_getreg(port, s->params->overrun_reg)->size)
1914 orer_status = sci_serial_in(port, s->params->overrun_reg);
1915
1916 err_enabled = scr_status & port_rx_irq_mask(port);
1917
1918 /* Tx Interrupt */
1919 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1920 !s->chan_tx)
1921 ret = sci_tx_interrupt(irq, ptr);
1922
1923 /*
1924 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1925 * DR flags
1926 */
1927 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1928 (scr_status & SCSCR_RIE))
1929 ret = sci_rx_interrupt(irq, ptr);
1930
1931 /* Error Interrupt */
1932 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1933 ret = sci_er_interrupt(irq, ptr);
1934
1935 /* Break Interrupt */
1936 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1937 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1938 ret = sci_br_interrupt(irq, ptr);
1939
1940 /* Overrun Interrupt */
1941 if (orer_status & s->params->overrun_mask) {
1942 sci_handle_fifo_overrun(port);
1943 ret = IRQ_HANDLED;
1944 }
1945
1946 return ret;
1947 }
1948
1949 static const struct sci_irq_desc {
1950 const char *desc;
1951 irq_handler_t handler;
1952 } sci_irq_desc[] = {
1953 /*
1954 * Split out handlers, the default case.
1955 */
1956 [SCIx_ERI_IRQ] = {
1957 .desc = "rx err",
1958 .handler = sci_er_interrupt,
1959 },
1960
1961 [SCIx_RXI_IRQ] = {
1962 .desc = "rx full",
1963 .handler = sci_rx_interrupt,
1964 },
1965
1966 [SCIx_TXI_IRQ] = {
1967 .desc = "tx empty",
1968 .handler = sci_tx_interrupt,
1969 },
1970
1971 [SCIx_BRI_IRQ] = {
1972 .desc = "break",
1973 .handler = sci_br_interrupt,
1974 },
1975
1976 [SCIx_DRI_IRQ] = {
1977 .desc = "rx ready",
1978 .handler = sci_rx_interrupt,
1979 },
1980
1981 [SCIx_TEI_IRQ] = {
1982 .desc = "tx end",
1983 .handler = sci_tx_end_interrupt,
1984 },
1985
1986 /*
1987 * Special muxed handler.
1988 */
1989 [SCIx_MUX_IRQ] = {
1990 .desc = "mux",
1991 .handler = sci_mpxed_interrupt,
1992 },
1993 };
1994
sci_request_irq(struct sci_port * port)1995 static int sci_request_irq(struct sci_port *port)
1996 {
1997 struct uart_port *up = &port->port;
1998 int i, j, w, ret = 0;
1999
2000 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2001 const struct sci_irq_desc *desc;
2002 int irq;
2003
2004 /* Check if already registered (muxed) */
2005 for (w = 0; w < i; w++)
2006 if (port->irqs[w] == port->irqs[i])
2007 w = i + 1;
2008 if (w > i)
2009 continue;
2010
2011 if (SCIx_IRQ_IS_MUXED(port)) {
2012 i = SCIx_MUX_IRQ;
2013 irq = up->irq;
2014 } else {
2015 irq = port->irqs[i];
2016
2017 /*
2018 * Certain port types won't support all of the
2019 * available interrupt sources.
2020 */
2021 if (unlikely(irq < 0))
2022 continue;
2023 }
2024
2025 desc = sci_irq_desc + i;
2026 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2027 dev_name(up->dev), desc->desc);
2028 if (!port->irqstr[j]) {
2029 ret = -ENOMEM;
2030 goto out_nomem;
2031 }
2032
2033 ret = request_irq(irq, desc->handler, up->irqflags,
2034 port->irqstr[j], port);
2035 if (unlikely(ret)) {
2036 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2037 goto out_noirq;
2038 }
2039 }
2040
2041 return 0;
2042
2043 out_noirq:
2044 while (--i >= 0)
2045 free_irq(port->irqs[i], port);
2046
2047 out_nomem:
2048 while (--j >= 0)
2049 kfree(port->irqstr[j]);
2050
2051 return ret;
2052 }
2053
sci_free_irq(struct sci_port * port)2054 static void sci_free_irq(struct sci_port *port)
2055 {
2056 int i, j;
2057
2058 /*
2059 * Intentionally in reverse order so we iterate over the muxed
2060 * IRQ first.
2061 */
2062 for (i = 0; i < SCIx_NR_IRQS; i++) {
2063 int irq = port->irqs[i];
2064
2065 /*
2066 * Certain port types won't support all of the available
2067 * interrupt sources.
2068 */
2069 if (unlikely(irq < 0))
2070 continue;
2071
2072 /* Check if already freed (irq was muxed) */
2073 for (j = 0; j < i; j++)
2074 if (port->irqs[j] == irq)
2075 j = i + 1;
2076 if (j > i)
2077 continue;
2078
2079 free_irq(port->irqs[i], port);
2080 kfree(port->irqstr[i]);
2081
2082 if (SCIx_IRQ_IS_MUXED(port)) {
2083 /* If there's only one IRQ, we're done. */
2084 return;
2085 }
2086 }
2087 }
2088
sci_tx_empty(struct uart_port * port)2089 static unsigned int sci_tx_empty(struct uart_port *port)
2090 {
2091 unsigned short status = sci_serial_in(port, SCxSR);
2092 unsigned short in_tx_fifo = sci_txfill(port);
2093 struct sci_port *s = to_sci_port(port);
2094
2095 sci_dma_check_tx_occurred(s);
2096
2097 if (!s->tx_occurred)
2098 return TIOCSER_TEMT;
2099
2100 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2101 }
2102
sci_set_rts(struct uart_port * port,bool state)2103 static void sci_set_rts(struct uart_port *port, bool state)
2104 {
2105 struct sci_port *s = to_sci_port(port);
2106
2107 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2108 u16 data = sci_serial_in(port, SCPDR);
2109
2110 /* Active low */
2111 if (state)
2112 data &= ~SCPDR_RTSD;
2113 else
2114 data |= SCPDR_RTSD;
2115 sci_serial_out(port, SCPDR, data);
2116
2117 /* RTS# is output */
2118 sci_serial_out(port, SCPCR,
2119 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2120 } else if (sci_getreg(port, SCSPTR)->size) {
2121 u16 ctrl = sci_serial_in(port, SCSPTR);
2122
2123 /* Active low */
2124 if (state)
2125 ctrl &= ~SCSPTR_RTSDT;
2126 else
2127 ctrl |= SCSPTR_RTSDT;
2128 sci_serial_out(port, SCSPTR, ctrl);
2129 }
2130 }
2131
sci_get_cts(struct uart_port * port)2132 static bool sci_get_cts(struct uart_port *port)
2133 {
2134 struct sci_port *s = to_sci_port(port);
2135
2136 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2137 /* Active low */
2138 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2139 } else if (sci_getreg(port, SCSPTR)->size) {
2140 /* Active low */
2141 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2142 }
2143
2144 return true;
2145 }
2146
2147 /*
2148 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2149 * CTS/RTS is supported in hardware by at least one port and controlled
2150 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2151 * handled via the ->init_pins() op, which is a bit of a one-way street,
2152 * lacking any ability to defer pin control -- this will later be
2153 * converted over to the GPIO framework).
2154 *
2155 * Other modes (such as loopback) are supported generically on certain
2156 * port types, but not others. For these it's sufficient to test for the
2157 * existence of the support register and simply ignore the port type.
2158 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2159 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2160 {
2161 struct sci_port *s = to_sci_port(port);
2162
2163 if (mctrl & TIOCM_LOOP) {
2164 const struct plat_sci_reg *reg;
2165
2166 /*
2167 * Standard loopback mode for SCFCR ports.
2168 */
2169 reg = sci_getreg(port, SCFCR);
2170 if (reg->size)
2171 sci_serial_out(port, SCFCR,
2172 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2173 }
2174
2175 mctrl_gpio_set(s->gpios, mctrl);
2176
2177 if (!s->has_rtscts)
2178 return;
2179
2180 if (!(mctrl & TIOCM_RTS)) {
2181 /* Disable Auto RTS */
2182 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2183 sci_serial_out(port, SCFCR,
2184 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2185
2186 /* Clear RTS */
2187 sci_set_rts(port, 0);
2188 } else if (s->autorts) {
2189 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2190 /* Enable RTS# pin function */
2191 sci_serial_out(port, SCPCR,
2192 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2193 }
2194
2195 /* Enable Auto RTS */
2196 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2197 sci_serial_out(port, SCFCR,
2198 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2199 } else {
2200 /* Set RTS */
2201 sci_set_rts(port, 1);
2202 }
2203 }
2204
sci_get_mctrl(struct uart_port * port)2205 static unsigned int sci_get_mctrl(struct uart_port *port)
2206 {
2207 struct sci_port *s = to_sci_port(port);
2208 struct mctrl_gpios *gpios = s->gpios;
2209 unsigned int mctrl = 0;
2210
2211 mctrl_gpio_get(gpios, &mctrl);
2212
2213 /*
2214 * CTS/RTS is handled in hardware when supported, while nothing
2215 * else is wired up.
2216 */
2217 if (s->autorts) {
2218 if (sci_get_cts(port))
2219 mctrl |= TIOCM_CTS;
2220 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2221 mctrl |= TIOCM_CTS;
2222 }
2223 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2224 mctrl |= TIOCM_DSR;
2225 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2226 mctrl |= TIOCM_CAR;
2227
2228 return mctrl;
2229 }
2230
sci_enable_ms(struct uart_port * port)2231 static void sci_enable_ms(struct uart_port *port)
2232 {
2233 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2234 }
2235
sci_break_ctl(struct uart_port * port,int break_state)2236 static void sci_break_ctl(struct uart_port *port, int break_state)
2237 {
2238 unsigned short scscr, scsptr;
2239 unsigned long flags;
2240
2241 /* check whether the port has SCSPTR */
2242 if (!sci_getreg(port, SCSPTR)->size) {
2243 /*
2244 * Not supported by hardware. Most parts couple break and rx
2245 * interrupts together, with break detection always enabled.
2246 */
2247 return;
2248 }
2249
2250 uart_port_lock_irqsave(port, &flags);
2251 scsptr = sci_serial_in(port, SCSPTR);
2252 scscr = sci_serial_in(port, SCSCR);
2253
2254 if (break_state == -1) {
2255 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2256 scscr &= ~SCSCR_TE;
2257 } else {
2258 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2259 scscr |= SCSCR_TE;
2260 }
2261
2262 sci_serial_out(port, SCSPTR, scsptr);
2263 sci_serial_out(port, SCSCR, scscr);
2264 uart_port_unlock_irqrestore(port, flags);
2265 }
2266
sci_shutdown_complete(struct uart_port * port)2267 static void sci_shutdown_complete(struct uart_port *port)
2268 {
2269 struct sci_port *s = to_sci_port(port);
2270 u16 scr;
2271
2272 scr = sci_serial_in(port, SCSCR);
2273 sci_serial_out(port, SCSCR,
2274 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2275 }
2276
sci_startup(struct uart_port * port)2277 int sci_startup(struct uart_port *port)
2278 {
2279 struct sci_port *s = to_sci_port(port);
2280 int ret;
2281
2282 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2283
2284 s->tx_occurred = false;
2285 sci_request_dma(port);
2286
2287 ret = sci_request_irq(s);
2288 if (unlikely(ret < 0)) {
2289 sci_free_dma(port);
2290 return ret;
2291 }
2292
2293 return 0;
2294 }
2295 EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI");
2296
sci_shutdown(struct uart_port * port)2297 void sci_shutdown(struct uart_port *port)
2298 {
2299 struct sci_port *s = to_sci_port(port);
2300 unsigned long flags;
2301
2302 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2303
2304 s->autorts = false;
2305 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2306
2307 uart_port_lock_irqsave(port, &flags);
2308 s->port.ops->stop_rx(port);
2309 s->port.ops->stop_tx(port);
2310 s->ops->shutdown_complete(port);
2311 uart_port_unlock_irqrestore(port, flags);
2312
2313 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2314 if (s->chan_rx_saved) {
2315 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2316 port->line);
2317 hrtimer_cancel(&s->rx_timer);
2318 }
2319 #endif
2320
2321 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2322 timer_delete_sync(&s->rx_fifo_timer);
2323 sci_free_irq(s);
2324 sci_free_dma(port);
2325 }
2326 EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI");
2327
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2328 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2329 unsigned int *srr)
2330 {
2331 unsigned long freq = s->clk_rates[SCI_SCK];
2332 int err, min_err = INT_MAX;
2333 unsigned int sr;
2334
2335 if (s->type != PORT_HSCIF)
2336 freq *= 2;
2337
2338 for_each_sr(sr, s) {
2339 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2340 if (abs(err) >= abs(min_err))
2341 continue;
2342
2343 min_err = err;
2344 *srr = sr - 1;
2345
2346 if (!err)
2347 break;
2348 }
2349
2350 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2351 *srr + 1);
2352 return min_err;
2353 }
2354
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2355 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2356 unsigned long freq, unsigned int *dlr,
2357 unsigned int *srr)
2358 {
2359 int err, min_err = INT_MAX;
2360 unsigned int sr, dl;
2361
2362 if (s->type != PORT_HSCIF)
2363 freq *= 2;
2364
2365 for_each_sr(sr, s) {
2366 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2367 dl = clamp(dl, 1U, 65535U);
2368
2369 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2370 if (abs(err) >= abs(min_err))
2371 continue;
2372
2373 min_err = err;
2374 *dlr = dl;
2375 *srr = sr - 1;
2376
2377 if (!err)
2378 break;
2379 }
2380
2381 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2382 min_err, *dlr, *srr + 1);
2383 return min_err;
2384 }
2385
2386 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2387 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2388 unsigned int *brr, unsigned int *srr,
2389 unsigned int *cks)
2390 {
2391 unsigned long freq = s->clk_rates[SCI_FCK];
2392 unsigned int sr, br, prediv, scrate, c;
2393 int err, min_err = INT_MAX;
2394
2395 if (s->type != PORT_HSCIF)
2396 freq *= 2;
2397
2398 /*
2399 * Find the combination of sample rate and clock select with the
2400 * smallest deviation from the desired baud rate.
2401 * Prefer high sample rates to maximise the receive margin.
2402 *
2403 * M: Receive margin (%)
2404 * N: Ratio of bit rate to clock (N = sampling rate)
2405 * D: Clock duty (D = 0 to 1.0)
2406 * L: Frame length (L = 9 to 12)
2407 * F: Absolute value of clock frequency deviation
2408 *
2409 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2410 * (|D - 0.5| / N * (1 + F))|
2411 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2412 */
2413 for_each_sr(sr, s) {
2414 for (c = 0; c <= 3; c++) {
2415 /* integerized formulas from HSCIF documentation */
2416 prediv = sr << (2 * c + 1);
2417
2418 /*
2419 * We need to calculate:
2420 *
2421 * br = freq / (prediv * bps) clamped to [1..256]
2422 * err = freq / (br * prediv) - bps
2423 *
2424 * Watch out for overflow when calculating the desired
2425 * sampling clock rate!
2426 */
2427 if (bps > UINT_MAX / prediv)
2428 break;
2429
2430 scrate = prediv * bps;
2431 br = DIV_ROUND_CLOSEST(freq, scrate);
2432 br = clamp(br, 1U, 256U);
2433
2434 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2435 if (abs(err) >= abs(min_err))
2436 continue;
2437
2438 min_err = err;
2439 *brr = br - 1;
2440 *srr = sr - 1;
2441 *cks = c;
2442
2443 if (!err)
2444 goto found;
2445 }
2446 }
2447
2448 found:
2449 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2450 min_err, *brr, *srr + 1, *cks);
2451 return min_err;
2452 }
2453
sci_reset(struct uart_port * port)2454 static void sci_reset(struct uart_port *port)
2455 {
2456 const struct plat_sci_reg *reg;
2457 unsigned int status;
2458 struct sci_port *s = to_sci_port(port);
2459
2460 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2461
2462 reg = sci_getreg(port, SCFCR);
2463 if (reg->size)
2464 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2465
2466 s->ops->clear_SCxSR(port,
2467 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2468 SCxSR_BREAK_CLEAR(port));
2469 if (sci_getreg(port, SCLSR)->size) {
2470 status = sci_serial_in(port, SCLSR);
2471 status &= ~(SCLSR_TO | SCLSR_ORER);
2472 sci_serial_out(port, SCLSR, status);
2473 }
2474
2475 if (s->rx_trigger > 1) {
2476 if (s->rx_fifo_timeout) {
2477 s->ops->set_rtrg(port, 1);
2478 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2479 } else {
2480 if (s->type == PORT_SCIFA ||
2481 s->type == PORT_SCIFB)
2482 s->ops->set_rtrg(port, 1);
2483 else
2484 s->ops->set_rtrg(port, s->rx_trigger);
2485 }
2486 }
2487 }
2488
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2489 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2490 const struct ktermios *old)
2491 {
2492 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2493 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2494 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2495 struct sci_port *s = to_sci_port(port);
2496 const struct plat_sci_reg *reg;
2497 int min_err = INT_MAX, err;
2498 unsigned long max_freq = 0;
2499 int best_clk = -1;
2500 unsigned long flags;
2501
2502 if ((termios->c_cflag & CSIZE) == CS7) {
2503 smr_val |= SCSMR_CHR;
2504 } else {
2505 termios->c_cflag &= ~CSIZE;
2506 termios->c_cflag |= CS8;
2507 }
2508 if (termios->c_cflag & PARENB)
2509 smr_val |= SCSMR_PE;
2510 if (termios->c_cflag & PARODD)
2511 smr_val |= SCSMR_PE | SCSMR_ODD;
2512 if (termios->c_cflag & CSTOPB)
2513 smr_val |= SCSMR_STOP;
2514
2515 /*
2516 * earlyprintk comes here early on with port->uartclk set to zero.
2517 * the clock framework is not up and running at this point so here
2518 * we assume that 115200 is the maximum baud rate. please note that
2519 * the baud rate is not programmed during earlyprintk - it is assumed
2520 * that the previous boot loader has enabled required clocks and
2521 * setup the baud rate generator hardware for us already.
2522 */
2523 if (!port->uartclk) {
2524 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2525 goto done;
2526 }
2527
2528 for (i = 0; i < SCI_NUM_CLKS; i++)
2529 max_freq = max(max_freq, s->clk_rates[i]);
2530
2531 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2532 if (!baud)
2533 goto done;
2534
2535 /*
2536 * There can be multiple sources for the sampling clock. Find the one
2537 * that gives us the smallest deviation from the desired baud rate.
2538 */
2539
2540 /* Optional Undivided External Clock */
2541 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA &&
2542 s->type != PORT_SCIFB) {
2543 err = sci_sck_calc(s, baud, &srr1);
2544 if (abs(err) < abs(min_err)) {
2545 best_clk = SCI_SCK;
2546 scr_val = SCSCR_CKE1;
2547 sccks = SCCKS_CKS;
2548 min_err = err;
2549 srr = srr1;
2550 if (!err)
2551 goto done;
2552 }
2553 }
2554
2555 /* Optional BRG Frequency Divided External Clock */
2556 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2557 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2558 &srr1);
2559 if (abs(err) < abs(min_err)) {
2560 best_clk = SCI_SCIF_CLK;
2561 scr_val = SCSCR_CKE1;
2562 sccks = 0;
2563 min_err = err;
2564 dl = dl1;
2565 srr = srr1;
2566 if (!err)
2567 goto done;
2568 }
2569 }
2570
2571 /* Optional BRG Frequency Divided Internal Clock */
2572 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2573 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2574 &srr1);
2575 if (abs(err) < abs(min_err)) {
2576 best_clk = SCI_BRG_INT;
2577 scr_val = SCSCR_CKE1;
2578 sccks = SCCKS_XIN;
2579 min_err = err;
2580 dl = dl1;
2581 srr = srr1;
2582 if (!min_err)
2583 goto done;
2584 }
2585 }
2586
2587 /* Divided Functional Clock using standard Bit Rate Register */
2588 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2589 if (abs(err) < abs(min_err)) {
2590 best_clk = SCI_FCK;
2591 scr_val = 0;
2592 min_err = err;
2593 brr = brr1;
2594 srr = srr1;
2595 cks = cks1;
2596 }
2597
2598 done:
2599 if (best_clk >= 0)
2600 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2601 s->clks[best_clk], baud, min_err);
2602
2603 sci_port_enable(s);
2604
2605 /*
2606 * Program the optional External Baud Rate Generator (BRG) first.
2607 * It controls the mux to select (H)SCK or frequency divided clock.
2608 */
2609 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2610 sci_serial_out(port, SCDL, dl);
2611 sci_serial_out(port, SCCKS, sccks);
2612 }
2613
2614 uart_port_lock_irqsave(port, &flags);
2615
2616 sci_reset(port);
2617
2618 uart_update_timeout(port, termios->c_cflag, baud);
2619
2620 /* byte size and parity */
2621 bits = tty_get_frame_size(termios->c_cflag);
2622
2623 if (sci_getreg(port, SEMR)->size)
2624 sci_serial_out(port, SEMR, 0);
2625
2626 if (best_clk >= 0) {
2627 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
2628 switch (srr + 1) {
2629 case 5: smr_val |= SCSMR_SRC_5; break;
2630 case 7: smr_val |= SCSMR_SRC_7; break;
2631 case 11: smr_val |= SCSMR_SRC_11; break;
2632 case 13: smr_val |= SCSMR_SRC_13; break;
2633 case 16: smr_val |= SCSMR_SRC_16; break;
2634 case 17: smr_val |= SCSMR_SRC_17; break;
2635 case 19: smr_val |= SCSMR_SRC_19; break;
2636 case 27: smr_val |= SCSMR_SRC_27; break;
2637 }
2638 smr_val |= cks;
2639 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2640 sci_serial_out(port, SCSMR, smr_val);
2641 sci_serial_out(port, SCBRR, brr);
2642 if (sci_getreg(port, HSSRR)->size) {
2643 unsigned int hssrr = srr | HSCIF_SRE;
2644 /* Calculate deviation from intended rate at the
2645 * center of the last stop bit in sampling clocks.
2646 */
2647 int last_stop = bits * 2 - 1;
2648 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2649 (int)(srr + 1),
2650 2 * (int)baud);
2651
2652 if (abs(deviation) >= 2) {
2653 /* At least two sampling clocks off at the
2654 * last stop bit; we can increase the error
2655 * margin by shifting the sampling point.
2656 */
2657 int shift = clamp(deviation / 2, -8, 7);
2658
2659 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2660 HSCIF_SRHP_MASK;
2661 hssrr |= HSCIF_SRDE;
2662 }
2663 sci_serial_out(port, HSSRR, hssrr);
2664 }
2665
2666 /* Wait one bit interval */
2667 udelay((1000000 + (baud - 1)) / baud);
2668 } else {
2669 /* Don't touch the bit rate configuration */
2670 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2671 smr_val |= sci_serial_in(port, SCSMR) &
2672 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2673 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2674 sci_serial_out(port, SCSMR, smr_val);
2675 }
2676
2677 sci_init_pins(port, termios->c_cflag);
2678
2679 port->status &= ~UPSTAT_AUTOCTS;
2680 s->autorts = false;
2681 reg = sci_getreg(port, SCFCR);
2682 if (reg->size) {
2683 unsigned short ctrl = sci_serial_in(port, SCFCR);
2684
2685 if ((port->flags & UPF_HARD_FLOW) &&
2686 (termios->c_cflag & CRTSCTS)) {
2687 /* There is no CTS interrupt to restart the hardware */
2688 port->status |= UPSTAT_AUTOCTS;
2689 /* MCE is enabled when RTS is raised */
2690 s->autorts = true;
2691 }
2692
2693 /*
2694 * As we've done a sci_reset() above, ensure we don't
2695 * interfere with the FIFOs while toggling MCE. As the
2696 * reset values could still be set, simply mask them out.
2697 */
2698 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2699
2700 sci_serial_out(port, SCFCR, ctrl);
2701 }
2702 if (port->flags & UPF_HARD_FLOW) {
2703 /* Refresh (Auto) RTS */
2704 sci_set_mctrl(port, port->mctrl);
2705 }
2706
2707 /*
2708 * For SCI, TE (transmit enable) must be set after setting TIE
2709 * (transmit interrupt enable) or in the same instruction to
2710 * start the transmitting process. So skip setting TE here for SCI.
2711 */
2712 if (s->type != PORT_SCI)
2713 scr_val |= SCSCR_TE;
2714 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2715 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2716 if ((srr + 1 == 5) &&
2717 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) {
2718 /*
2719 * In asynchronous mode, when the sampling rate is 1/5, first
2720 * received data may become invalid on some SCIFA and SCIFB.
2721 * To avoid this problem wait more than 1 serial data time (1
2722 * bit time x serial data number) after setting SCSCR.RE = 1.
2723 */
2724 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2725 }
2726
2727 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2728 s->rx_frame = (10000 * bits) / (baud / 100);
2729 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2730 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2731 #endif
2732
2733 if ((termios->c_cflag & CREAD) != 0)
2734 sci_start_rx(port);
2735
2736 uart_port_unlock_irqrestore(port, flags);
2737
2738 sci_port_disable(s);
2739
2740 if (UART_ENABLE_MS(port, termios->c_cflag))
2741 sci_enable_ms(port);
2742 }
2743
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2744 void sci_pm(struct uart_port *port, unsigned int state,
2745 unsigned int oldstate)
2746 {
2747 struct sci_port *sci_port = to_sci_port(port);
2748
2749 switch (state) {
2750 case UART_PM_STATE_OFF:
2751 sci_port_disable(sci_port);
2752 break;
2753 default:
2754 sci_port_enable(sci_port);
2755 break;
2756 }
2757 }
2758 EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI");
2759
sci_type(struct uart_port * port)2760 static const char *sci_type(struct uart_port *port)
2761 {
2762 struct sci_port *s = to_sci_port(port);
2763
2764 switch (s->type) {
2765 case PORT_IRDA:
2766 return "irda";
2767 case PORT_SCI:
2768 return "sci";
2769 case PORT_SCIF:
2770 return "scif";
2771 case PORT_SCIFA:
2772 return "scifa";
2773 case PORT_SCIFB:
2774 return "scifb";
2775 case PORT_HSCIF:
2776 return "hscif";
2777 }
2778
2779 return NULL;
2780 }
2781
sci_remap_port(struct uart_port * port)2782 static int sci_remap_port(struct uart_port *port)
2783 {
2784 struct sci_port *sport = to_sci_port(port);
2785
2786 /*
2787 * Nothing to do if there's already an established membase.
2788 */
2789 if (port->membase)
2790 return 0;
2791
2792 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2793 port->membase = ioremap(port->mapbase, sport->reg_size);
2794 if (unlikely(!port->membase)) {
2795 dev_err(port->dev, "can't remap port#%d\n", port->line);
2796 return -ENXIO;
2797 }
2798 } else {
2799 /*
2800 * For the simple (and majority of) cases where we don't
2801 * need to do any remapping, just cast the cookie
2802 * directly.
2803 */
2804 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2805 }
2806
2807 return 0;
2808 }
2809
sci_release_port(struct uart_port * port)2810 void sci_release_port(struct uart_port *port)
2811 {
2812 struct sci_port *sport = to_sci_port(port);
2813
2814 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2815 iounmap(port->membase);
2816 port->membase = NULL;
2817 }
2818
2819 release_mem_region(port->mapbase, sport->reg_size);
2820 }
2821 EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI");
2822
sci_request_port(struct uart_port * port)2823 int sci_request_port(struct uart_port *port)
2824 {
2825 struct resource *res;
2826 struct sci_port *sport = to_sci_port(port);
2827 int ret;
2828
2829 res = request_mem_region(port->mapbase, sport->reg_size,
2830 dev_name(port->dev));
2831 if (unlikely(res == NULL)) {
2832 dev_err(port->dev, "request_mem_region failed.");
2833 return -EBUSY;
2834 }
2835
2836 ret = sci_remap_port(port);
2837 if (unlikely(ret != 0)) {
2838 release_resource(res);
2839 return ret;
2840 }
2841
2842 return 0;
2843 }
2844 EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI");
2845
sci_config_port(struct uart_port * port,int flags)2846 void sci_config_port(struct uart_port *port, int flags)
2847 {
2848 if (flags & UART_CONFIG_TYPE) {
2849 struct sci_port *sport = to_sci_port(port);
2850 port->type = SCI_PUBLIC_PORT_ID(sport->type);
2851 sci_request_port(port);
2852 }
2853 }
2854 EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI");
2855
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2856 int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2857 {
2858 if (ser->baud_base < 2400)
2859 /* No paper tape reader for Mitch.. */
2860 return -EINVAL;
2861
2862 return 0;
2863 }
2864 EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI");
2865
sci_prepare_console_write(struct uart_port * port,u32 ctrl)2866 static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
2867 {
2868 struct sci_port *s = to_sci_port(port);
2869 u32 ctrl_temp =
2870 s->params->param_bits->rxtx_enable |
2871 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2872 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) |
2873 s->hscif_tot;
2874 sci_serial_out(port, SCSCR, ctrl_temp);
2875 }
2876
sci_console_save(struct uart_port * port)2877 static void sci_console_save(struct uart_port *port)
2878 {
2879 struct sci_port *s = to_sci_port(port);
2880 struct sci_suspend_regs *regs = s->suspend_regs;
2881
2882 if (sci_getreg(port, SCDL)->size)
2883 regs->scdl = sci_serial_in(port, SCDL);
2884 if (sci_getreg(port, SCCKS)->size)
2885 regs->sccks = sci_serial_in(port, SCCKS);
2886 if (sci_getreg(port, SCSMR)->size)
2887 regs->scsmr = sci_serial_in(port, SCSMR);
2888 if (sci_getreg(port, SCSCR)->size)
2889 regs->scscr = sci_serial_in(port, SCSCR);
2890 if (sci_getreg(port, SCFCR)->size)
2891 regs->scfcr = sci_serial_in(port, SCFCR);
2892 if (sci_getreg(port, SCSPTR)->size)
2893 regs->scsptr = sci_serial_in(port, SCSPTR);
2894 if (sci_getreg(port, SCBRR)->size)
2895 regs->scbrr = sci_serial_in(port, SCBRR);
2896 if (sci_getreg(port, HSSRR)->size)
2897 regs->hssrr = sci_serial_in(port, HSSRR);
2898 if (sci_getreg(port, SCPCR)->size)
2899 regs->scpcr = sci_serial_in(port, SCPCR);
2900 if (sci_getreg(port, SCPDR)->size)
2901 regs->scpdr = sci_serial_in(port, SCPDR);
2902 if (sci_getreg(port, SEMR)->size)
2903 regs->semr = sci_serial_in(port, SEMR);
2904 }
2905
sci_console_restore(struct uart_port * port)2906 static void sci_console_restore(struct uart_port *port)
2907 {
2908 struct sci_port *s = to_sci_port(port);
2909 struct sci_suspend_regs *regs = s->suspend_regs;
2910
2911 if (sci_getreg(port, SCDL)->size)
2912 sci_serial_out(port, SCDL, regs->scdl);
2913 if (sci_getreg(port, SCCKS)->size)
2914 sci_serial_out(port, SCCKS, regs->sccks);
2915 if (sci_getreg(port, SCSMR)->size)
2916 sci_serial_out(port, SCSMR, regs->scsmr);
2917 if (sci_getreg(port, SCSCR)->size)
2918 sci_serial_out(port, SCSCR, regs->scscr);
2919 if (sci_getreg(port, SCFCR)->size)
2920 sci_serial_out(port, SCFCR, regs->scfcr);
2921 if (sci_getreg(port, SCSPTR)->size)
2922 sci_serial_out(port, SCSPTR, regs->scsptr);
2923 if (sci_getreg(port, SCBRR)->size)
2924 sci_serial_out(port, SCBRR, regs->scbrr);
2925 if (sci_getreg(port, HSSRR)->size)
2926 sci_serial_out(port, HSSRR, regs->hssrr);
2927 if (sci_getreg(port, SCPCR)->size)
2928 sci_serial_out(port, SCPCR, regs->scpcr);
2929 if (sci_getreg(port, SCPDR)->size)
2930 sci_serial_out(port, SCPDR, regs->scpdr);
2931 if (sci_getreg(port, SEMR)->size)
2932 sci_serial_out(port, SEMR, regs->semr);
2933 }
2934
2935 static const struct uart_ops sci_uart_ops = {
2936 .tx_empty = sci_tx_empty,
2937 .set_mctrl = sci_set_mctrl,
2938 .get_mctrl = sci_get_mctrl,
2939 .start_tx = sci_start_tx,
2940 .stop_tx = sci_stop_tx,
2941 .stop_rx = sci_stop_rx,
2942 .enable_ms = sci_enable_ms,
2943 .break_ctl = sci_break_ctl,
2944 .startup = sci_startup,
2945 .shutdown = sci_shutdown,
2946 .flush_buffer = sci_flush_buffer,
2947 .set_termios = sci_set_termios,
2948 .pm = sci_pm,
2949 .type = sci_type,
2950 .release_port = sci_release_port,
2951 .request_port = sci_request_port,
2952 .config_port = sci_config_port,
2953 .verify_port = sci_verify_port,
2954 #ifdef CONFIG_CONSOLE_POLL
2955 .poll_get_char = sci_poll_get_char,
2956 .poll_put_char = sci_poll_put_char,
2957 #endif
2958 };
2959
2960 static const struct sci_port_ops sci_port_ops = {
2961 .read_reg = sci_serial_in,
2962 .write_reg = sci_serial_out,
2963 .clear_SCxSR = sci_clear_SCxSR,
2964 .transmit_chars = sci_transmit_chars,
2965 .receive_chars = sci_receive_chars,
2966 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2967 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2968 .poll_put_char = sci_poll_put_char,
2969 #endif
2970 .set_rtrg = scif_set_rtrg,
2971 .rtrg_enabled = scif_rtrg_enabled,
2972 .shutdown_complete = sci_shutdown_complete,
2973 .prepare_console_write = sci_prepare_console_write,
2974 .console_save = sci_console_save,
2975 .console_restore = sci_console_restore,
2976 .suspend_regs_size = sci_suspend_regs_size,
2977 };
2978
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2979 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2980 {
2981 const char *clk_names[] = {
2982 [SCI_FCK] = "fck",
2983 [SCI_SCK] = "sck",
2984 [SCI_BRG_INT] = "brg_int",
2985 [SCI_SCIF_CLK] = "scif_clk",
2986 };
2987 struct clk *clk;
2988 unsigned int i;
2989
2990 if (sci_port->type == PORT_HSCIF) {
2991 clk_names[SCI_SCK] = "hsck";
2992 } else if (sci_port->type == SCI_PORT_RSCI) {
2993 clk_names[SCI_FCK] = "operation";
2994 clk_names[SCI_BRG_INT] = "bus";
2995 }
2996
2997 for (i = 0; i < SCI_NUM_CLKS; i++) {
2998 const char *name = clk_names[i];
2999
3000 clk = devm_clk_get_optional(dev, name);
3001 if (IS_ERR(clk))
3002 return PTR_ERR(clk);
3003
3004 if (!clk && sci_port->type == SCI_PORT_RSCI &&
3005 (i == SCI_FCK || i == SCI_BRG_INT)) {
3006 return dev_err_probe(dev, -ENODEV,
3007 "failed to get %s\n",
3008 name);
3009 }
3010
3011 if (!clk && i == SCI_FCK) {
3012 /*
3013 * Not all SH platforms declare a clock lookup entry
3014 * for SCI devices, in which case we need to get the
3015 * global "peripheral_clk" clock.
3016 */
3017 clk = devm_clk_get(dev, "peripheral_clk");
3018 if (IS_ERR(clk))
3019 return dev_err_probe(dev, PTR_ERR(clk),
3020 "failed to get %s\n",
3021 name);
3022 }
3023
3024 if (!clk)
3025 dev_dbg(dev, "failed to get %s\n", name);
3026 else
3027 dev_dbg(dev, "clk %s is %pC rate %lu\n", name,
3028 clk, clk_get_rate(clk));
3029 sci_port->clks[i] = clk;
3030 }
3031 return 0;
3032 }
3033
3034 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg,struct sci_port * sci_port)3035 sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port)
3036 {
3037 unsigned int regtype;
3038
3039 sci_port->ops = &sci_port_ops;
3040 sci_port->port.ops = &sci_uart_ops;
3041
3042 if (cfg->regtype != SCIx_PROBE_REGTYPE)
3043 return &sci_port_params[cfg->regtype];
3044
3045 switch (cfg->type) {
3046 case PORT_SCI:
3047 regtype = SCIx_SCI_REGTYPE;
3048 break;
3049 case PORT_IRDA:
3050 regtype = SCIx_IRDA_REGTYPE;
3051 break;
3052 case PORT_SCIFA:
3053 regtype = SCIx_SCIFA_REGTYPE;
3054 break;
3055 case PORT_SCIFB:
3056 regtype = SCIx_SCIFB_REGTYPE;
3057 break;
3058 case PORT_SCIF:
3059 /*
3060 * The SH-4 is a bit of a misnomer here, although that's
3061 * where this particular port layout originated. This
3062 * configuration (or some slight variation thereof)
3063 * remains the dominant model for all SCIFs.
3064 */
3065 regtype = SCIx_SH4_SCIF_REGTYPE;
3066 break;
3067 case PORT_HSCIF:
3068 regtype = SCIx_HSCIF_REGTYPE;
3069 break;
3070 default:
3071 pr_err("Can't probe register map for given port\n");
3072 return NULL;
3073 }
3074
3075 return &sci_port_params[regtype];
3076 }
3077
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)3078 static int sci_init_single(struct platform_device *dev,
3079 struct sci_port *sci_port, unsigned int index,
3080 const struct plat_sci_port *p, bool early)
3081 {
3082 struct uart_port *port = &sci_port->port;
3083 const struct resource *res;
3084 unsigned int i;
3085 int ret;
3086
3087 sci_port->cfg = p;
3088
3089 sci_port->type = p->type;
3090 sci_port->regtype = p->regtype;
3091
3092 port->iotype = UPIO_MEM;
3093 port->line = index;
3094 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
3095
3096 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3097 if (res == NULL)
3098 return -ENOMEM;
3099
3100 port->mapbase = res->start;
3101 sci_port->reg_size = resource_size(res);
3102
3103 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
3104 if (i)
3105 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
3106 else
3107 sci_port->irqs[i] = platform_get_irq(dev, i);
3108 }
3109
3110 /*
3111 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
3112 * shuffle the interrupts.
3113 */
3114 if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI)
3115 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3116
3117 /* The SCI generates several interrupts. They can be muxed together or
3118 * connected to different interrupt lines. In the muxed case only one
3119 * interrupt resource is specified as there is only one interrupt ID.
3120 * In the non-muxed case, up to 6 interrupt signals might be generated
3121 * from the SCI, however those signals might have their own individual
3122 * interrupt ID numbers, or muxed together with another interrupt.
3123 */
3124 if (sci_port->irqs[0] < 0)
3125 return -ENXIO;
3126
3127 if (sci_port->irqs[1] < 0)
3128 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3129 sci_port->irqs[i] = sci_port->irqs[0];
3130
3131 switch (p->type) {
3132 case PORT_SCIFB:
3133 sci_port->rx_trigger = 48;
3134 break;
3135 case PORT_HSCIF:
3136 sci_port->rx_trigger = 64;
3137 break;
3138 case PORT_SCIFA:
3139 sci_port->rx_trigger = 32;
3140 break;
3141 case PORT_SCIF:
3142 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3143 /* RX triggering not implemented for this IP */
3144 sci_port->rx_trigger = 1;
3145 else
3146 sci_port->rx_trigger = 8;
3147 break;
3148 case SCI_PORT_RSCI:
3149 sci_port->rx_trigger = 15;
3150 break;
3151 default:
3152 sci_port->rx_trigger = 1;
3153 break;
3154 }
3155
3156 sci_port->rx_fifo_timeout = 0;
3157 sci_port->hscif_tot = 0;
3158
3159 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3160 * match the SoC datasheet, this should be investigated. Let platform
3161 * data override the sampling rate for now.
3162 */
3163 sci_port->sampling_rate_mask = p->sampling_rate
3164 ? SCI_SR(p->sampling_rate)
3165 : sci_port->params->sampling_rate_mask;
3166
3167 if (!early) {
3168 ret = sci_init_clocks(sci_port, &dev->dev);
3169 if (ret < 0)
3170 return ret;
3171 }
3172
3173 port->type = SCI_PUBLIC_PORT_ID(p->type);
3174 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3175 port->fifosize = sci_port->params->fifosize;
3176
3177 if (p->type == PORT_SCI && !dev->dev.of_node) {
3178 if (sci_port->reg_size >= 0x20)
3179 port->regshift = 2;
3180 else
3181 port->regshift = 1;
3182 }
3183
3184 /*
3185 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3186 * for the multi-IRQ ports, which is where we are primarily
3187 * concerned with the shutdown path synchronization.
3188 *
3189 * For the muxed case there's nothing more to do.
3190 */
3191 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3192 port->irqflags = 0;
3193
3194 return 0;
3195 }
3196
3197 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3198 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)3199 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3200 {
3201 to_sci_port(port)->ops->poll_put_char(port, ch);
3202 }
3203
3204 /*
3205 * Print a string to the serial port trying not to disturb
3206 * any possible real use of the port...
3207 */
serial_console_write(struct console * co,const char * s,unsigned count)3208 static void serial_console_write(struct console *co, const char *s,
3209 unsigned count)
3210 {
3211 struct sci_port *sci_port = &sci_ports[co->index];
3212 struct uart_port *port = &sci_port->port;
3213 const struct sci_common_regs *regs = sci_port->params->common_regs;
3214 unsigned int bits;
3215 u32 ctrl;
3216 unsigned long flags;
3217 int locked = 1;
3218
3219 if (port->sysrq)
3220 locked = 0;
3221 else if (oops_in_progress)
3222 locked = uart_port_trylock_irqsave(port, &flags);
3223 else
3224 uart_port_lock_irqsave(port, &flags);
3225
3226 /* first save SCSCR then disable interrupts, keep clock source */
3227
3228 ctrl = sci_port->ops->read_reg(port, regs->control);
3229 sci_port->ops->prepare_console_write(port, ctrl);
3230
3231 uart_console_write(port, s, count, serial_console_putchar);
3232
3233 /* wait until fifo is empty and last bit has been transmitted */
3234
3235 bits = sci_port->params->param_bits->poll_sent_bits;
3236
3237 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
3238 cpu_relax();
3239
3240 /* restore the SCSCR */
3241 sci_port->ops->write_reg(port, regs->control, ctrl);
3242
3243 if (locked)
3244 uart_port_unlock_irqrestore(port, flags);
3245 }
3246
serial_console_setup(struct console * co,char * options)3247 static int serial_console_setup(struct console *co, char *options)
3248 {
3249 struct sci_port *sci_port;
3250 struct uart_port *port;
3251 int baud = 115200;
3252 int bits = 8;
3253 int parity = 'n';
3254 int flow = 'n';
3255 int ret;
3256
3257 /*
3258 * Refuse to handle any bogus ports.
3259 */
3260 if (co->index < 0 || co->index >= SCI_NPORTS)
3261 return -ENODEV;
3262
3263 sci_port = &sci_ports[co->index];
3264 port = &sci_port->port;
3265
3266 /*
3267 * Refuse to handle uninitialized ports.
3268 */
3269 if (!port->ops)
3270 return -ENODEV;
3271
3272 ret = sci_remap_port(port);
3273 if (unlikely(ret != 0))
3274 return ret;
3275
3276 if (options)
3277 uart_parse_options(options, &baud, &parity, &bits, &flow);
3278
3279 return uart_set_options(port, co, baud, parity, bits, flow);
3280 }
3281
3282 static struct console serial_console = {
3283 .name = "ttySC",
3284 .device = uart_console_device,
3285 .write = serial_console_write,
3286 .setup = serial_console_setup,
3287 .flags = CON_PRINTBUFFER,
3288 .index = -1,
3289 .data = &sci_uart_driver,
3290 };
3291
3292 #ifdef CONFIG_SUPERH
3293 static char early_serial_buf[32];
3294
early_serial_console_setup(struct console * co,char * options)3295 static int early_serial_console_setup(struct console *co, char *options)
3296 {
3297 /*
3298 * This early console is always registered using the earlyprintk=
3299 * parameter, which does not call add_preferred_console(). Thus
3300 * @options is always NULL and the options for this early console
3301 * are passed using a custom buffer.
3302 */
3303 WARN_ON(options);
3304
3305 return serial_console_setup(co, early_serial_buf);
3306 }
3307
3308 static struct console early_serial_console = {
3309 .name = "early_ttySC",
3310 .write = serial_console_write,
3311 .setup = early_serial_console_setup,
3312 .flags = CON_PRINTBUFFER,
3313 .index = -1,
3314 };
3315
sci_probe_earlyprintk(struct platform_device * pdev)3316 static int sci_probe_earlyprintk(struct platform_device *pdev)
3317 {
3318 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3319 struct sci_port *sp = &sci_ports[pdev->id];
3320
3321 if (early_serial_console.data)
3322 return -EEXIST;
3323
3324 early_serial_console.index = pdev->id;
3325
3326 sp->params = sci_probe_regmap(cfg, sp);
3327 if (!sp->params)
3328 return -ENODEV;
3329
3330 sci_init_single(pdev, sp, pdev->id, cfg, true);
3331
3332 if (!strstr(early_serial_buf, "keep"))
3333 early_serial_console.flags |= CON_BOOT;
3334
3335 register_console(&early_serial_console);
3336 return 0;
3337 }
3338 #endif
3339
3340 #define SCI_CONSOLE (&serial_console)
3341
3342 #else
sci_probe_earlyprintk(struct platform_device * pdev)3343 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3344 {
3345 return -EINVAL;
3346 }
3347
3348 #define SCI_CONSOLE NULL
3349
3350 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3351
3352 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3353
3354 static DEFINE_MUTEX(sci_uart_registration_lock);
3355 static struct uart_driver sci_uart_driver = {
3356 .owner = THIS_MODULE,
3357 .driver_name = "sci",
3358 .dev_name = "ttySC",
3359 .major = SCI_MAJOR,
3360 .minor = SCI_MINOR_START,
3361 .nr = SCI_NPORTS,
3362 .cons = SCI_CONSOLE,
3363 };
3364
sci_remove(struct platform_device * dev)3365 static void sci_remove(struct platform_device *dev)
3366 {
3367 struct sci_port *s = platform_get_drvdata(dev);
3368 unsigned int type = s->type; /* uart_remove_... clears it */
3369
3370 sci_ports_in_use &= ~BIT(s->port.line);
3371 uart_remove_one_port(&sci_uart_driver, &s->port);
3372
3373 if (s->port.fifosize > 1)
3374 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3375 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
3376 type == SCI_PORT_RSCI)
3377 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3378 }
3379
3380 static const struct sci_of_data of_sci_scif_sh2 = {
3381 .type = PORT_SCIF,
3382 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
3383 .ops = &sci_port_ops,
3384 .uart_ops = &sci_uart_ops,
3385 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE],
3386 };
3387
3388 static const struct sci_of_data of_sci_scif_rz_scifa = {
3389 .type = PORT_SCIF,
3390 .regtype = SCIx_RZ_SCIFA_REGTYPE,
3391 .ops = &sci_port_ops,
3392 .uart_ops = &sci_uart_ops,
3393 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE],
3394 };
3395
3396 static const struct sci_of_data of_sci_scif_rzv2h = {
3397 .type = PORT_SCIF,
3398 .regtype = SCIx_RZV2H_SCIF_REGTYPE,
3399 .ops = &sci_port_ops,
3400 .uart_ops = &sci_uart_ops,
3401 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE],
3402 };
3403
3404 static const struct sci_of_data of_sci_rcar_scif = {
3405 .type = PORT_SCIF,
3406 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
3407 .ops = &sci_port_ops,
3408 .uart_ops = &sci_uart_ops,
3409 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE],
3410 };
3411
3412 static const struct sci_of_data of_sci_scif_sh4 = {
3413 .type = PORT_SCIF,
3414 .regtype = SCIx_SH4_SCIF_REGTYPE,
3415 .ops = &sci_port_ops,
3416 .uart_ops = &sci_uart_ops,
3417 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE],
3418 };
3419
3420 static const struct sci_of_data of_sci_scifa = {
3421 .type = PORT_SCIFA,
3422 .regtype = SCIx_SCIFA_REGTYPE,
3423 .ops = &sci_port_ops,
3424 .uart_ops = &sci_uart_ops,
3425 .params = &sci_port_params[SCIx_SCIFA_REGTYPE],
3426 };
3427
3428 static const struct sci_of_data of_sci_scifb = {
3429 .type = PORT_SCIFB,
3430 .regtype = SCIx_SCIFB_REGTYPE,
3431 .ops = &sci_port_ops,
3432 .uart_ops = &sci_uart_ops,
3433 .params = &sci_port_params[SCIx_SCIFB_REGTYPE],
3434 };
3435
3436 static const struct sci_of_data of_sci_hscif = {
3437 .type = PORT_HSCIF,
3438 .regtype = SCIx_HSCIF_REGTYPE,
3439 .ops = &sci_port_ops,
3440 .uart_ops = &sci_uart_ops,
3441 .params = &sci_port_params[SCIx_HSCIF_REGTYPE],
3442 };
3443
3444 static const struct sci_of_data of_sci_sci = {
3445 .type = PORT_SCI,
3446 .regtype = SCIx_SCI_REGTYPE,
3447 .ops = &sci_port_ops,
3448 .uart_ops = &sci_uart_ops,
3449 .params = &sci_port_params[SCIx_SCI_REGTYPE],
3450 };
3451
3452 static const struct of_device_id of_sci_match[] __maybe_unused = {
3453 /* SoC-specific types */
3454 {
3455 .compatible = "renesas,scif-r7s72100",
3456 .data = &of_sci_scif_sh2,
3457 },
3458 {
3459 .compatible = "renesas,scif-r7s9210",
3460 .data = &of_sci_scif_rz_scifa,
3461 },
3462 {
3463 .compatible = "renesas,scif-r9a07g044",
3464 .data = &of_sci_scif_rz_scifa,
3465 },
3466 {
3467 .compatible = "renesas,scif-r9a09g057",
3468 .data = &of_sci_scif_rzv2h,
3469 },
3470 #ifdef CONFIG_SERIAL_RSCI
3471 {
3472 .compatible = "renesas,r9a09g077-rsci",
3473 .data = &of_sci_rsci_data,
3474 },
3475 #endif /* CONFIG_SERIAL_RSCI */
3476 /* Family-specific types */
3477 {
3478 .compatible = "renesas,rcar-gen1-scif",
3479 .data = &of_sci_rcar_scif,
3480 }, {
3481 .compatible = "renesas,rcar-gen2-scif",
3482 .data = &of_sci_rcar_scif,
3483 }, {
3484 .compatible = "renesas,rcar-gen3-scif",
3485 .data = &of_sci_rcar_scif
3486 }, {
3487 .compatible = "renesas,rcar-gen4-scif",
3488 .data = &of_sci_rcar_scif
3489 }, {
3490 .compatible = "renesas,rcar-gen5-scif",
3491 .data = &of_sci_rcar_scif
3492 },
3493 /* Generic types */
3494 {
3495 .compatible = "renesas,scif",
3496 .data = &of_sci_scif_sh4,
3497 }, {
3498 .compatible = "renesas,scifa",
3499 .data = &of_sci_scifa,
3500 }, {
3501 .compatible = "renesas,scifb",
3502 .data = &of_sci_scifb,
3503 }, {
3504 .compatible = "renesas,hscif",
3505 .data = &of_sci_hscif,
3506 }, {
3507 .compatible = "renesas,sci",
3508 .data = &of_sci_sci,
3509 }, {
3510 /* Terminator */
3511 },
3512 };
3513 MODULE_DEVICE_TABLE(of, of_sci_match);
3514
sci_reset_control_assert(void * data)3515 static void sci_reset_control_assert(void *data)
3516 {
3517 reset_control_assert(data);
3518 }
3519
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3520 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3521 unsigned int *dev_id)
3522 {
3523 struct device_node *np = pdev->dev.of_node;
3524 struct reset_control *rstc;
3525 struct plat_sci_port *p;
3526 struct sci_port *sp;
3527 const struct sci_of_data *data;
3528 int id, ret;
3529
3530 if (!IS_ENABLED(CONFIG_OF) || !np)
3531 return ERR_PTR(-EINVAL);
3532
3533 data = of_device_get_match_data(&pdev->dev);
3534
3535 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3536 if (IS_ERR(rstc))
3537 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3538 "failed to get reset ctrl\n"));
3539
3540 ret = reset_control_deassert(rstc);
3541 if (ret) {
3542 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3543 return ERR_PTR(ret);
3544 }
3545
3546 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3547 if (ret) {
3548 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3549 ret);
3550 return ERR_PTR(ret);
3551 }
3552
3553 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3554 if (!p)
3555 return ERR_PTR(-ENOMEM);
3556
3557 /* Get the line number from the aliases node. */
3558 id = of_alias_get_id(np, "serial");
3559 if (id < 0 && ~sci_ports_in_use)
3560 id = ffz(sci_ports_in_use);
3561 if (id < 0) {
3562 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3563 return ERR_PTR(-EINVAL);
3564 }
3565 if (id >= ARRAY_SIZE(sci_ports)) {
3566 dev_err(&pdev->dev, "serial%d out of range\n", id);
3567 return ERR_PTR(-EINVAL);
3568 }
3569
3570 sp = &sci_ports[id];
3571 sp->rstc = rstc;
3572 *dev_id = id;
3573
3574 p->type = data->type;
3575 p->regtype = data->regtype;
3576
3577 sp->ops = data->ops;
3578 sp->port.ops = data->uart_ops;
3579 sp->params = data->params;
3580
3581 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3582
3583 return p;
3584 }
3585
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport,struct resource * sci_res)3586 static int sci_probe_single(struct platform_device *dev,
3587 unsigned int index,
3588 struct plat_sci_port *p,
3589 struct sci_port *sciport,
3590 struct resource *sci_res)
3591 {
3592 int ret;
3593
3594 /* Sanity check */
3595 if (unlikely(index >= SCI_NPORTS)) {
3596 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3597 index+1, SCI_NPORTS);
3598 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3599 return -EINVAL;
3600 }
3601 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3602 if (sci_ports_in_use & BIT(index))
3603 return -EBUSY;
3604
3605 mutex_lock(&sci_uart_registration_lock);
3606 if (!sci_uart_driver.state) {
3607 ret = uart_register_driver(&sci_uart_driver);
3608 if (ret) {
3609 mutex_unlock(&sci_uart_registration_lock);
3610 return ret;
3611 }
3612 }
3613 mutex_unlock(&sci_uart_registration_lock);
3614
3615 ret = sci_init_single(dev, sciport, index, p, false);
3616 if (ret)
3617 return ret;
3618
3619 sciport->port.dev = &dev->dev;
3620 ret = devm_pm_runtime_enable(&dev->dev);
3621 if (ret)
3622 return ret;
3623
3624 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3625 if (IS_ERR(sciport->gpios))
3626 return PTR_ERR(sciport->gpios);
3627
3628 if (sciport->has_rtscts) {
3629 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3630 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3631 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3632 return -EINVAL;
3633 }
3634 sciport->port.flags |= UPF_HARD_FLOW;
3635 }
3636
3637 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3638 /*
3639 * In case:
3640 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3641 * - it now maps to an alias other than zero and
3642 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3643 * available in bootargs)
3644 *
3645 * we need to avoid disabling clocks and PM domains through the runtime
3646 * PM APIs called in __device_attach(). For this, increment the runtime
3647 * PM reference counter (the clocks and PM domains were already enabled
3648 * by the bootloader). Otherwise the earlycon may access the HW when it
3649 * has no clocks enabled leading to failures (infinite loop in
3650 * sci_poll_put_char()).
3651 */
3652 pm_runtime_get_noresume(&dev->dev);
3653
3654 /*
3655 * Skip cleanup the sci_port[0] in early_console_exit(), this
3656 * port is the same as the earlycon one.
3657 */
3658 sci_uart_earlycon_dev_probing = true;
3659 }
3660
3661 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3662 }
3663
sci_probe(struct platform_device * dev)3664 static int sci_probe(struct platform_device *dev)
3665 {
3666 struct plat_sci_port *p;
3667 struct resource *res;
3668 struct sci_port *sp;
3669 unsigned int dev_id;
3670 int ret;
3671
3672 /*
3673 * If we've come here via earlyprintk initialization, head off to
3674 * the special early probe. We don't have sufficient device state
3675 * to make it beyond this yet.
3676 */
3677 #ifdef CONFIG_SUPERH
3678 if (is_sh_early_platform_device(dev))
3679 return sci_probe_earlyprintk(dev);
3680 #endif
3681
3682 if (dev->dev.of_node) {
3683 p = sci_parse_dt(dev, &dev_id);
3684 if (IS_ERR(p))
3685 return PTR_ERR(p);
3686 sp = &sci_ports[dev_id];
3687 } else {
3688 p = dev->dev.platform_data;
3689 if (p == NULL) {
3690 dev_err(&dev->dev, "no platform data supplied\n");
3691 return -EINVAL;
3692 }
3693
3694 dev_id = dev->id;
3695 sp = &sci_ports[dev_id];
3696 sp->params = sci_probe_regmap(p, sp);
3697 if (!sp->params)
3698 return -ENODEV;
3699 }
3700
3701 sp->suspend_regs = devm_kzalloc(&dev->dev,
3702 sp->ops->suspend_regs_size(),
3703 GFP_KERNEL);
3704 if (!sp->suspend_regs)
3705 return -ENOMEM;
3706
3707 /*
3708 * In case:
3709 * - the probed port alias is zero (as the one used by earlycon), and
3710 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3711 * bootargs)
3712 *
3713 * defer the probe of this serial. This is a debug scenario and the user
3714 * must be aware of it.
3715 *
3716 * Except when the probed port is the same as the earlycon port.
3717 */
3718
3719 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3720 if (!res)
3721 return -ENODEV;
3722
3723 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3724 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3725
3726 platform_set_drvdata(dev, sp);
3727
3728 ret = sci_probe_single(dev, dev_id, p, sp, res);
3729 if (ret)
3730 return ret;
3731
3732 if (sp->port.fifosize > 1) {
3733 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3734 if (ret)
3735 return ret;
3736 }
3737 if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
3738 sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
3739 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3740 if (ret) {
3741 if (sp->port.fifosize > 1) {
3742 device_remove_file(&dev->dev,
3743 &dev_attr_rx_fifo_trigger);
3744 }
3745 return ret;
3746 }
3747 }
3748
3749 #ifdef CONFIG_SH_STANDARD_BIOS
3750 sh_bios_gdb_detach();
3751 #endif
3752
3753 sci_ports_in_use |= BIT(dev_id);
3754 return 0;
3755 }
3756
sci_suspend(struct device * dev)3757 static int sci_suspend(struct device *dev)
3758 {
3759 struct sci_port *sport = dev_get_drvdata(dev);
3760
3761 if (sport) {
3762 uart_suspend_port(&sci_uart_driver, &sport->port);
3763
3764 if (!console_suspend_enabled && uart_console(&sport->port)) {
3765 if (sport->ops->console_save)
3766 sport->ops->console_save(&sport->port);
3767 }
3768 else
3769 return reset_control_assert(sport->rstc);
3770 }
3771
3772 return 0;
3773 }
3774
sci_resume(struct device * dev)3775 static int sci_resume(struct device *dev)
3776 {
3777 struct sci_port *sport = dev_get_drvdata(dev);
3778
3779 if (sport) {
3780 if (!console_suspend_enabled && uart_console(&sport->port)) {
3781 if (sport->ops->console_restore)
3782 sport->ops->console_restore(&sport->port);
3783 } else {
3784 int ret = reset_control_deassert(sport->rstc);
3785
3786 if (ret)
3787 return ret;
3788 }
3789
3790 uart_resume_port(&sci_uart_driver, &sport->port);
3791 }
3792
3793 return 0;
3794 }
3795
3796 static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3797
3798 static struct platform_driver sci_driver = {
3799 .probe = sci_probe,
3800 .remove = sci_remove,
3801 .driver = {
3802 .name = "sh-sci",
3803 .pm = pm_sleep_ptr(&sci_dev_pm_ops),
3804 .of_match_table = of_match_ptr(of_sci_match),
3805 },
3806 };
3807
sci_init(void)3808 static int __init sci_init(void)
3809 {
3810 pr_info("%s\n", banner);
3811
3812 return platform_driver_register(&sci_driver);
3813 }
3814
sci_exit(void)3815 static void __exit sci_exit(void)
3816 {
3817 platform_driver_unregister(&sci_driver);
3818
3819 if (sci_uart_driver.state)
3820 uart_unregister_driver(&sci_uart_driver);
3821 }
3822
3823 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3824 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3825 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3826 #endif
3827 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3828 static struct plat_sci_port port_cfg;
3829
early_console_exit(struct console * co)3830 static int early_console_exit(struct console *co)
3831 {
3832 struct sci_port *sci_port = &sci_ports[0];
3833
3834 /*
3835 * Clean the slot used by earlycon. A new SCI device might
3836 * map to this slot.
3837 */
3838 if (!sci_uart_earlycon_dev_probing) {
3839 memset(sci_port, 0, sizeof(*sci_port));
3840 sci_uart_earlycon = false;
3841 }
3842
3843 return 0;
3844 }
3845
scix_early_console_setup(struct earlycon_device * device,const struct sci_of_data * data)3846 int __init scix_early_console_setup(struct earlycon_device *device,
3847 const struct sci_of_data *data)
3848 {
3849 const struct sci_common_regs *regs;
3850
3851 if (!device->port.membase)
3852 return -ENODEV;
3853
3854 device->port.type = SCI_PUBLIC_PORT_ID(data->type);
3855
3856 sci_ports[0].port = device->port;
3857 sci_ports[0].type = data->type;
3858 sci_ports[0].regtype = data->regtype;
3859
3860 port_cfg.type = data->type;
3861 port_cfg.regtype = data->regtype;
3862
3863 sci_ports[0].cfg = &port_cfg;
3864 sci_ports[0].params = data->params;
3865 sci_ports[0].ops = data->ops;
3866 sci_ports[0].port.ops = data->uart_ops;
3867 sci_uart_earlycon = true;
3868 regs = sci_ports[0].params->common_regs;
3869
3870 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
3871 sci_ports[0].ops->write_reg(&sci_ports[0].port,
3872 regs->control,
3873 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);
3874
3875 device->con->write = serial_console_write;
3876 device->con->exit = early_console_exit;
3877
3878 return 0;
3879 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3880 static int __init sci_early_console_setup(struct earlycon_device *device,
3881 const char *opt)
3882 {
3883 return scix_early_console_setup(device, &of_sci_sci);
3884 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3885 static int __init scif_early_console_setup(struct earlycon_device *device,
3886 const char *opt)
3887 {
3888 return scix_early_console_setup(device, &of_sci_scif_sh4);
3889 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3890 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3891 const char *opt)
3892 {
3893 return scix_early_console_setup(device, &of_sci_scif_rz_scifa);
3894 }
3895
rzv2hscif_early_console_setup(struct earlycon_device * device,const char * opt)3896 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3897 const char *opt)
3898 {
3899 return scix_early_console_setup(device, &of_sci_scif_rzv2h);
3900 }
3901
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3902 static int __init scifa_early_console_setup(struct earlycon_device *device,
3903 const char *opt)
3904 {
3905 return scix_early_console_setup(device, &of_sci_scifa);
3906 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3907 static int __init scifb_early_console_setup(struct earlycon_device *device,
3908 const char *opt)
3909 {
3910 return scix_early_console_setup(device, &of_sci_scifb);
3911 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3912 static int __init hscif_early_console_setup(struct earlycon_device *device,
3913 const char *opt)
3914 {
3915 return scix_early_console_setup(device, &of_sci_hscif);
3916 }
3917
3918 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3919 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3920 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3921 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3922 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3923 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3924 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3925 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3926 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3927
3928 module_init(sci_init);
3929 module_exit(sci_exit);
3930
3931 MODULE_LICENSE("GPL");
3932 MODULE_ALIAS("platform:sh-sci");
3933 MODULE_AUTHOR("Paul Mundt");
3934 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3935