1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
36 #include <linux/mm.h>
37 #include <linux/of.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/reset.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
55 #endif
56
57 #include "serial_mctrl_gpio.h"
58 #include "sh-sci.h"
59 #include "sh-sci-common.h"
60
61 #define SCIx_IRQ_IS_MUXED(port) \
62 ((port)->irqs[SCIx_ERI_IRQ] == \
63 (port)->irqs[SCIx_RXI_IRQ]) || \
64 ((port)->irqs[SCIx_ERI_IRQ] && \
65 ((port)->irqs[SCIx_RXI_IRQ] < 0))
66
67 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
68 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
69 SCI_SR(19) | SCI_SR(27)
70
71 /* Iterate over all supported sampling rates, from high to low */
72 #define for_each_sr(_sr, _port) \
73 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
74 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
75
76 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
77
78 static struct sci_port sci_ports[SCI_NPORTS];
79 static unsigned long sci_ports_in_use;
80 static struct uart_driver sci_uart_driver;
81 static bool sci_uart_earlycon;
82 static bool sci_uart_earlycon_dev_probing;
83
84 static const struct sci_port_params_bits sci_sci_port_params_bits = {
85 .rxtx_enable = SCSCR_RE | SCSCR_TE,
86 .te_clear = SCSCR_TE | SCSCR_TEIE,
87 .poll_sent_bits = SCI_TDRE | SCI_TEND
88 };
89
90 static const struct sci_port_params_bits sci_scif_port_params_bits = {
91 .rxtx_enable = SCSCR_RE | SCSCR_TE,
92 .te_clear = SCSCR_TE | SCSCR_TEIE,
93 .poll_sent_bits = SCIF_TDFE | SCIF_TEND
94 };
95
96 static const struct sci_common_regs sci_common_regs = {
97 .status = SCxSR,
98 .control = SCSCR,
99 };
100
101 struct sci_suspend_regs {
102 u16 scdl;
103 u16 sccks;
104 u16 scsmr;
105 u16 scscr;
106 u16 scfcr;
107 u16 scsptr;
108 u16 hssrr;
109 u16 scpcr;
110 u16 scpdr;
111 u8 scbrr;
112 u8 semr;
113 };
114
sci_suspend_regs_size(void)115 static size_t sci_suspend_regs_size(void)
116 {
117 return sizeof(struct sci_suspend_regs);
118 }
119
120 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
121 /*
122 * Common SCI definitions, dependent on the port's regshift
123 * value.
124 */
125 [SCIx_SCI_REGTYPE] = {
126 .regs = {
127 [SCSMR] = { 0x00, 8 },
128 [SCBRR] = { 0x01, 8 },
129 [SCSCR] = { 0x02, 8 },
130 [SCxTDR] = { 0x03, 8 },
131 [SCxSR] = { 0x04, 8 },
132 [SCxRDR] = { 0x05, 8 },
133 },
134 .fifosize = 1,
135 .overrun_reg = SCxSR,
136 .overrun_mask = SCI_ORER,
137 .sampling_rate_mask = SCI_SR(32),
138 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
139 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
140 .param_bits = &sci_sci_port_params_bits,
141 .common_regs = &sci_common_regs,
142 },
143
144 /*
145 * Common definitions for legacy IrDA ports.
146 */
147 [SCIx_IRDA_REGTYPE] = {
148 .regs = {
149 [SCSMR] = { 0x00, 8 },
150 [SCBRR] = { 0x02, 8 },
151 [SCSCR] = { 0x04, 8 },
152 [SCxTDR] = { 0x06, 8 },
153 [SCxSR] = { 0x08, 16 },
154 [SCxRDR] = { 0x0a, 8 },
155 [SCFCR] = { 0x0c, 8 },
156 [SCFDR] = { 0x0e, 16 },
157 },
158 .fifosize = 1,
159 .overrun_reg = SCxSR,
160 .overrun_mask = SCI_ORER,
161 .sampling_rate_mask = SCI_SR(32),
162 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
163 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
164 .param_bits = &sci_scif_port_params_bits,
165 .common_regs = &sci_common_regs,
166 },
167
168 /*
169 * Common SCIFA definitions.
170 */
171 [SCIx_SCIFA_REGTYPE] = {
172 .regs = {
173 [SCSMR] = { 0x00, 16 },
174 [SCBRR] = { 0x04, 8 },
175 [SCSCR] = { 0x08, 16 },
176 [SCxTDR] = { 0x20, 8 },
177 [SCxSR] = { 0x14, 16 },
178 [SCxRDR] = { 0x24, 8 },
179 [SCFCR] = { 0x18, 16 },
180 [SCFDR] = { 0x1c, 16 },
181 [SCPCR] = { 0x30, 16 },
182 [SCPDR] = { 0x34, 16 },
183 },
184 .fifosize = 64,
185 .overrun_reg = SCxSR,
186 .overrun_mask = SCIFA_ORER,
187 .sampling_rate_mask = SCI_SR_SCIFAB,
188 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
189 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
190 .param_bits = &sci_scif_port_params_bits,
191 .common_regs = &sci_common_regs,
192 },
193
194 /*
195 * Common SCIFB definitions.
196 */
197 [SCIx_SCIFB_REGTYPE] = {
198 .regs = {
199 [SCSMR] = { 0x00, 16 },
200 [SCBRR] = { 0x04, 8 },
201 [SCSCR] = { 0x08, 16 },
202 [SCxTDR] = { 0x40, 8 },
203 [SCxSR] = { 0x14, 16 },
204 [SCxRDR] = { 0x60, 8 },
205 [SCFCR] = { 0x18, 16 },
206 [SCTFDR] = { 0x38, 16 },
207 [SCRFDR] = { 0x3c, 16 },
208 [SCPCR] = { 0x30, 16 },
209 [SCPDR] = { 0x34, 16 },
210 },
211 .fifosize = 256,
212 .overrun_reg = SCxSR,
213 .overrun_mask = SCIFA_ORER,
214 .sampling_rate_mask = SCI_SR_SCIFAB,
215 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
216 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
217 .param_bits = &sci_scif_port_params_bits,
218 .common_regs = &sci_common_regs,
219 },
220
221 /*
222 * Common SH-2(A) SCIF definitions for ports with FIFO data
223 * count registers.
224 */
225 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
226 .regs = {
227 [SCSMR] = { 0x00, 16 },
228 [SCBRR] = { 0x04, 8 },
229 [SCSCR] = { 0x08, 16 },
230 [SCxTDR] = { 0x0c, 8 },
231 [SCxSR] = { 0x10, 16 },
232 [SCxRDR] = { 0x14, 8 },
233 [SCFCR] = { 0x18, 16 },
234 [SCFDR] = { 0x1c, 16 },
235 [SCSPTR] = { 0x20, 16 },
236 [SCLSR] = { 0x24, 16 },
237 },
238 .fifosize = 16,
239 .overrun_reg = SCLSR,
240 .overrun_mask = SCLSR_ORER,
241 .sampling_rate_mask = SCI_SR(32),
242 .error_mask = SCIF_DEFAULT_ERROR_MASK,
243 .error_clear = SCIF_ERROR_CLEAR,
244 .param_bits = &sci_scif_port_params_bits,
245 .common_regs = &sci_common_regs,
246 },
247
248 /*
249 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
250 * It looks like a normal SCIF with FIFO data, but with a
251 * compressed address space. Also, the break out of interrupts
252 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
253 */
254 [SCIx_RZ_SCIFA_REGTYPE] = {
255 .regs = {
256 [SCSMR] = { 0x00, 16 },
257 [SCBRR] = { 0x02, 8 },
258 [SCSCR] = { 0x04, 16 },
259 [SCxTDR] = { 0x06, 8 },
260 [SCxSR] = { 0x08, 16 },
261 [SCxRDR] = { 0x0A, 8 },
262 [SCFCR] = { 0x0C, 16 },
263 [SCFDR] = { 0x0E, 16 },
264 [SCSPTR] = { 0x10, 16 },
265 [SCLSR] = { 0x12, 16 },
266 [SEMR] = { 0x14, 8 },
267 },
268 .fifosize = 16,
269 .overrun_reg = SCLSR,
270 .overrun_mask = SCLSR_ORER,
271 .sampling_rate_mask = SCI_SR(32),
272 .error_mask = SCIF_DEFAULT_ERROR_MASK,
273 .error_clear = SCIF_ERROR_CLEAR,
274 .param_bits = &sci_scif_port_params_bits,
275 .common_regs = &sci_common_regs,
276 },
277
278 /*
279 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
280 * with below differences,
281 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
282 * TEI-DRI, RXI-EDGE and TXI-EDGE.
283 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
284 * - SCFCR register does not have SCFCR_MCE bit.
285 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
286 */
287 [SCIx_RZV2H_SCIF_REGTYPE] = {
288 .regs = {
289 [SCSMR] = { 0x00, 16 },
290 [SCBRR] = { 0x02, 8 },
291 [SCSCR] = { 0x04, 16 },
292 [SCxTDR] = { 0x06, 8 },
293 [SCxSR] = { 0x08, 16 },
294 [SCxRDR] = { 0x0a, 8 },
295 [SCFCR] = { 0x0c, 16 },
296 [SCFDR] = { 0x0e, 16 },
297 [SCSPTR] = { 0x10, 16 },
298 [SCLSR] = { 0x12, 16 },
299 [SEMR] = { 0x14, 8 },
300 },
301 .fifosize = 16,
302 .overrun_reg = SCLSR,
303 .overrun_mask = SCLSR_ORER,
304 .sampling_rate_mask = SCI_SR(32),
305 .error_mask = SCIF_DEFAULT_ERROR_MASK,
306 .error_clear = SCIF_ERROR_CLEAR,
307 .param_bits = &sci_scif_port_params_bits,
308 .common_regs = &sci_common_regs,
309 },
310
311 /*
312 * Common SH-3 SCIF definitions.
313 */
314 [SCIx_SH3_SCIF_REGTYPE] = {
315 .regs = {
316 [SCSMR] = { 0x00, 8 },
317 [SCBRR] = { 0x02, 8 },
318 [SCSCR] = { 0x04, 8 },
319 [SCxTDR] = { 0x06, 8 },
320 [SCxSR] = { 0x08, 16 },
321 [SCxRDR] = { 0x0a, 8 },
322 [SCFCR] = { 0x0c, 8 },
323 [SCFDR] = { 0x0e, 16 },
324 },
325 .fifosize = 16,
326 .overrun_reg = SCLSR,
327 .overrun_mask = SCLSR_ORER,
328 .sampling_rate_mask = SCI_SR(32),
329 .error_mask = SCIF_DEFAULT_ERROR_MASK,
330 .error_clear = SCIF_ERROR_CLEAR,
331 .param_bits = &sci_scif_port_params_bits,
332 .common_regs = &sci_common_regs,
333 },
334
335 /*
336 * Common SH-4(A) SCIF(B) definitions.
337 */
338 [SCIx_SH4_SCIF_REGTYPE] = {
339 .regs = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 },
351 .fifosize = 16,
352 .overrun_reg = SCLSR,
353 .overrun_mask = SCLSR_ORER,
354 .sampling_rate_mask = SCI_SR(32),
355 .error_mask = SCIF_DEFAULT_ERROR_MASK,
356 .error_clear = SCIF_ERROR_CLEAR,
357 .param_bits = &sci_scif_port_params_bits,
358 .common_regs = &sci_common_regs,
359 },
360
361 /*
362 * Common SCIF definitions for ports with a Baud Rate Generator for
363 * External Clock (BRG).
364 */
365 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [SCDL] = { 0x30, 16 },
378 [SCCKS] = { 0x34, 16 },
379 },
380 .fifosize = 16,
381 .overrun_reg = SCLSR,
382 .overrun_mask = SCLSR_ORER,
383 .sampling_rate_mask = SCI_SR(32),
384 .error_mask = SCIF_DEFAULT_ERROR_MASK,
385 .error_clear = SCIF_ERROR_CLEAR,
386 .param_bits = &sci_scif_port_params_bits,
387 .common_regs = &sci_common_regs,
388 },
389
390 /*
391 * Common HSCIF definitions.
392 */
393 [SCIx_HSCIF_REGTYPE] = {
394 .regs = {
395 [SCSMR] = { 0x00, 16 },
396 [SCBRR] = { 0x04, 8 },
397 [SCSCR] = { 0x08, 16 },
398 [SCxTDR] = { 0x0c, 8 },
399 [SCxSR] = { 0x10, 16 },
400 [SCxRDR] = { 0x14, 8 },
401 [SCFCR] = { 0x18, 16 },
402 [SCFDR] = { 0x1c, 16 },
403 [SCSPTR] = { 0x20, 16 },
404 [SCLSR] = { 0x24, 16 },
405 [HSSRR] = { 0x40, 16 },
406 [SCDL] = { 0x30, 16 },
407 [SCCKS] = { 0x34, 16 },
408 [HSRTRGR] = { 0x54, 16 },
409 [HSTTRGR] = { 0x58, 16 },
410 },
411 .fifosize = 128,
412 .overrun_reg = SCLSR,
413 .overrun_mask = SCLSR_ORER,
414 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
415 .error_mask = SCIF_DEFAULT_ERROR_MASK,
416 .error_clear = SCIF_ERROR_CLEAR,
417 .param_bits = &sci_scif_port_params_bits,
418 .common_regs = &sci_common_regs,
419 },
420
421 /*
422 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
423 * register.
424 */
425 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
426 .regs = {
427 [SCSMR] = { 0x00, 16 },
428 [SCBRR] = { 0x04, 8 },
429 [SCSCR] = { 0x08, 16 },
430 [SCxTDR] = { 0x0c, 8 },
431 [SCxSR] = { 0x10, 16 },
432 [SCxRDR] = { 0x14, 8 },
433 [SCFCR] = { 0x18, 16 },
434 [SCFDR] = { 0x1c, 16 },
435 [SCLSR] = { 0x24, 16 },
436 },
437 .fifosize = 16,
438 .overrun_reg = SCLSR,
439 .overrun_mask = SCLSR_ORER,
440 .sampling_rate_mask = SCI_SR(32),
441 .error_mask = SCIF_DEFAULT_ERROR_MASK,
442 .error_clear = SCIF_ERROR_CLEAR,
443 .param_bits = &sci_scif_port_params_bits,
444 .common_regs = &sci_common_regs,
445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
472 .param_bits = &sci_scif_port_params_bits,
473 .common_regs = &sci_common_regs,
474 },
475
476 /*
477 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
478 * registers.
479 */
480 [SCIx_SH7705_SCIF_REGTYPE] = {
481 .regs = {
482 [SCSMR] = { 0x00, 16 },
483 [SCBRR] = { 0x04, 8 },
484 [SCSCR] = { 0x08, 16 },
485 [SCxTDR] = { 0x20, 8 },
486 [SCxSR] = { 0x14, 16 },
487 [SCxRDR] = { 0x24, 8 },
488 [SCFCR] = { 0x18, 16 },
489 [SCFDR] = { 0x1c, 16 },
490 },
491 .fifosize = 64,
492 .overrun_reg = SCxSR,
493 .overrun_mask = SCIFA_ORER,
494 .sampling_rate_mask = SCI_SR(16),
495 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
496 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
497 .param_bits = &sci_scif_port_params_bits,
498 .common_regs = &sci_common_regs,
499 },
500 };
501
502 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
503
504 /*
505 * The "offset" here is rather misleading, in that it refers to an enum
506 * value relative to the port mapping rather than the fixed offset
507 * itself, which needs to be manually retrieved from the platform's
508 * register map for the given port.
509 */
sci_serial_in(struct uart_port * p,int offset)510 static unsigned int sci_serial_in(struct uart_port *p, int offset)
511 {
512 const struct plat_sci_reg *reg = sci_getreg(p, offset);
513
514 if (reg->size == 8)
515 return ioread8(p->membase + (reg->offset << p->regshift));
516 else if (reg->size == 16)
517 return ioread16(p->membase + (reg->offset << p->regshift));
518 else
519 WARN(1, "Invalid register access\n");
520
521 return 0;
522 }
523
sci_serial_out(struct uart_port * p,int offset,int value)524 static void sci_serial_out(struct uart_port *p, int offset, int value)
525 {
526 const struct plat_sci_reg *reg = sci_getreg(p, offset);
527
528 if (reg->size == 8)
529 iowrite8(value, p->membase + (reg->offset << p->regshift));
530 else if (reg->size == 16)
531 iowrite16(value, p->membase + (reg->offset << p->regshift));
532 else
533 WARN(1, "Invalid register access\n");
534 }
535
sci_port_enable(struct sci_port * sci_port)536 void sci_port_enable(struct sci_port *sci_port)
537 {
538 unsigned int i;
539
540 if (!sci_port->port.dev)
541 return;
542
543 pm_runtime_get_sync(sci_port->port.dev);
544
545 for (i = 0; i < SCI_NUM_CLKS; i++) {
546 clk_prepare_enable(sci_port->clks[i]);
547 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
548 }
549 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
550 }
551
sci_port_disable(struct sci_port * sci_port)552 void sci_port_disable(struct sci_port *sci_port)
553 {
554 unsigned int i;
555
556 if (!sci_port->port.dev)
557 return;
558
559 for (i = SCI_NUM_CLKS; i-- > 0; )
560 clk_disable_unprepare(sci_port->clks[i]);
561
562 pm_runtime_put_sync(sci_port->port.dev);
563 }
564
port_rx_irq_mask(struct uart_port * port)565 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
566 {
567 /*
568 * Not all ports (such as SCIFA) will support REIE. Rather than
569 * special-casing the port type, we check the port initialization
570 * IRQ enable mask to see whether the IRQ is desired at all. If
571 * it's unset, it's logically inferred that there's no point in
572 * testing for it.
573 */
574 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
575 }
576
sci_start_tx(struct uart_port * port)577 static void sci_start_tx(struct uart_port *port)
578 {
579 struct sci_port *s = to_sci_port(port);
580 unsigned short ctrl;
581
582 #ifdef CONFIG_SERIAL_SH_SCI_DMA
583 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
584 u16 new, scr = sci_serial_in(port, SCSCR);
585 if (s->chan_tx)
586 new = scr | SCSCR_TDRQE;
587 else
588 new = scr & ~SCSCR_TDRQE;
589 if (new != scr)
590 sci_serial_out(port, SCSCR, new);
591 }
592
593 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
594 dma_submit_error(s->cookie_tx)) {
595 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
596 /* Switch irq from SCIF to DMA */
597 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
598
599 s->cookie_tx = 0;
600 schedule_work(&s->work_tx);
601 }
602 #endif
603
604 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
605 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
606 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
607 ctrl = sci_serial_in(port, SCSCR);
608
609 /*
610 * For SCI, TE (transmit enable) must be set after setting TIE
611 * (transmit interrupt enable) or in the same instruction to start
612 * the transmit process.
613 */
614 if (port->type == PORT_SCI)
615 ctrl |= SCSCR_TE;
616
617 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
618 }
619 }
620
sci_stop_tx(struct uart_port * port)621 static void sci_stop_tx(struct uart_port *port)
622 {
623 unsigned short ctrl;
624
625 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
626 ctrl = sci_serial_in(port, SCSCR);
627
628 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
629 ctrl &= ~SCSCR_TDRQE;
630
631 ctrl &= ~SCSCR_TIE;
632
633 sci_serial_out(port, SCSCR, ctrl);
634
635 #ifdef CONFIG_SERIAL_SH_SCI_DMA
636 if (to_sci_port(port)->chan_tx &&
637 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
638 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
639 to_sci_port(port)->cookie_tx = -EINVAL;
640 }
641 #endif
642 }
643
sci_start_rx(struct uart_port * port)644 static void sci_start_rx(struct uart_port *port)
645 {
646 unsigned short ctrl;
647
648 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
649
650 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
651 ctrl &= ~SCSCR_RDRQE;
652
653 sci_serial_out(port, SCSCR, ctrl);
654 }
655
sci_stop_rx(struct uart_port * port)656 static void sci_stop_rx(struct uart_port *port)
657 {
658 unsigned short ctrl;
659
660 ctrl = sci_serial_in(port, SCSCR);
661
662 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
663 ctrl &= ~SCSCR_RDRQE;
664
665 ctrl &= ~port_rx_irq_mask(port);
666
667 sci_serial_out(port, SCSCR, ctrl);
668 }
669
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)670 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
671 {
672 if (port->type == PORT_SCI) {
673 /* Just store the mask */
674 sci_serial_out(port, SCxSR, mask);
675 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
676 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
677 /* Only clear the status bits we want to clear */
678 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
679 } else {
680 /* Store the mask, clear parity/framing errors */
681 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
682 }
683 }
684
685 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
686 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
687
688 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)689 static int sci_poll_get_char(struct uart_port *port)
690 {
691 unsigned short status;
692 struct sci_port *s = to_sci_port(port);
693 int c;
694
695 do {
696 status = sci_serial_in(port, SCxSR);
697 if (status & SCxSR_ERRORS(port)) {
698 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
699 continue;
700 }
701 break;
702 } while (1);
703
704 if (!(status & SCxSR_RDxF(port)))
705 return NO_POLL_CHAR;
706
707 c = sci_serial_in(port, SCxRDR);
708
709 /* Dummy read */
710 sci_serial_in(port, SCxSR);
711 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
712
713 return c;
714 }
715 #endif
716
sci_poll_put_char(struct uart_port * port,unsigned char c)717 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
718 {
719 struct sci_port *s = to_sci_port(port);
720 const struct sci_common_regs *regs = s->params->common_regs;
721 unsigned int status;
722
723 do {
724 status = s->ops->read_reg(port, regs->status);
725 } while (!(status & SCxSR_TDxE(port)));
726
727 sci_serial_out(port, SCxTDR, c);
728 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
729 }
730 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
731 CONFIG_SERIAL_SH_SCI_EARLYCON */
732
sci_init_pins(struct uart_port * port,unsigned int cflag)733 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
734 {
735 struct sci_port *s = to_sci_port(port);
736
737 /*
738 * Use port-specific handler if provided.
739 */
740 if (s->cfg->ops && s->cfg->ops->init_pins) {
741 s->cfg->ops->init_pins(port, cflag);
742 return;
743 }
744
745 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
746 u16 data = sci_serial_in(port, SCPDR);
747 u16 ctrl = sci_serial_in(port, SCPCR);
748
749 /* Enable RXD and TXD pin functions */
750 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
751 if (to_sci_port(port)->has_rtscts) {
752 /* RTS# is output, active low, unless autorts */
753 if (!(port->mctrl & TIOCM_RTS)) {
754 ctrl |= SCPCR_RTSC;
755 data |= SCPDR_RTSD;
756 } else if (!s->autorts) {
757 ctrl |= SCPCR_RTSC;
758 data &= ~SCPDR_RTSD;
759 } else {
760 /* Enable RTS# pin function */
761 ctrl &= ~SCPCR_RTSC;
762 }
763 /* Enable CTS# pin function */
764 ctrl &= ~SCPCR_CTSC;
765 }
766 sci_serial_out(port, SCPDR, data);
767 sci_serial_out(port, SCPCR, ctrl);
768 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
769 u16 status = sci_serial_in(port, SCSPTR);
770
771 /* RTS# is always output; and active low, unless autorts */
772 status |= SCSPTR_RTSIO;
773 if (!(port->mctrl & TIOCM_RTS))
774 status |= SCSPTR_RTSDT;
775 else if (!s->autorts)
776 status &= ~SCSPTR_RTSDT;
777 /* CTS# and SCK are inputs */
778 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
779 sci_serial_out(port, SCSPTR, status);
780 }
781 }
782
sci_txfill(struct uart_port * port)783 static int sci_txfill(struct uart_port *port)
784 {
785 struct sci_port *s = to_sci_port(port);
786 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
787 const struct plat_sci_reg *reg;
788
789 reg = sci_getreg(port, SCTFDR);
790 if (reg->size)
791 return sci_serial_in(port, SCTFDR) & fifo_mask;
792
793 reg = sci_getreg(port, SCFDR);
794 if (reg->size)
795 return sci_serial_in(port, SCFDR) >> 8;
796
797 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
798 }
799
sci_txroom(struct uart_port * port)800 static int sci_txroom(struct uart_port *port)
801 {
802 return port->fifosize - sci_txfill(port);
803 }
804
sci_rxfill(struct uart_port * port)805 static int sci_rxfill(struct uart_port *port)
806 {
807 struct sci_port *s = to_sci_port(port);
808 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
809 const struct plat_sci_reg *reg;
810
811 reg = sci_getreg(port, SCRFDR);
812 if (reg->size)
813 return sci_serial_in(port, SCRFDR) & fifo_mask;
814
815 reg = sci_getreg(port, SCFDR);
816 if (reg->size)
817 return sci_serial_in(port, SCFDR) & fifo_mask;
818
819 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
820 }
821
822 /* ********************************************************************** *
823 * the interrupt related routines *
824 * ********************************************************************** */
825
sci_transmit_chars(struct uart_port * port)826 static void sci_transmit_chars(struct uart_port *port)
827 {
828 struct tty_port *tport = &port->state->port;
829 unsigned int stopped = uart_tx_stopped(port);
830 struct sci_port *s = to_sci_port(port);
831 unsigned short status;
832 unsigned short ctrl;
833 int count;
834
835 status = sci_serial_in(port, SCxSR);
836 if (!(status & SCxSR_TDxE(port))) {
837 ctrl = sci_serial_in(port, SCSCR);
838 if (kfifo_is_empty(&tport->xmit_fifo))
839 ctrl &= ~SCSCR_TIE;
840 else
841 ctrl |= SCSCR_TIE;
842 sci_serial_out(port, SCSCR, ctrl);
843 return;
844 }
845
846 count = sci_txroom(port);
847
848 do {
849 unsigned char c;
850
851 if (port->x_char) {
852 c = port->x_char;
853 port->x_char = 0;
854 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
855 if (port->type == PORT_SCI &&
856 kfifo_is_empty(&tport->xmit_fifo)) {
857 ctrl = sci_serial_in(port, SCSCR);
858 ctrl &= ~SCSCR_TE;
859 sci_serial_out(port, SCSCR, ctrl);
860 return;
861 }
862 break;
863 }
864
865 sci_serial_out(port, SCxTDR, c);
866 s->tx_occurred = true;
867
868 port->icount.tx++;
869 } while (--count > 0);
870
871 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
872
873 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
874 uart_write_wakeup(port);
875 if (kfifo_is_empty(&tport->xmit_fifo)) {
876 if (port->type == PORT_SCI) {
877 ctrl = sci_serial_in(port, SCSCR);
878 ctrl &= ~SCSCR_TIE;
879 ctrl |= SCSCR_TEIE;
880 sci_serial_out(port, SCSCR, ctrl);
881 }
882
883 sci_stop_tx(port);
884 }
885 }
886
sci_receive_chars(struct uart_port * port)887 static void sci_receive_chars(struct uart_port *port)
888 {
889 struct tty_port *tport = &port->state->port;
890 struct sci_port *s = to_sci_port(port);
891 int i, count, copied = 0;
892 unsigned short status;
893 unsigned char flag;
894
895 status = sci_serial_in(port, SCxSR);
896 if (!(status & SCxSR_RDxF(port)))
897 return;
898
899 while (1) {
900 /* Don't copy more bytes than there is room for in the buffer */
901 count = tty_buffer_request_room(tport, sci_rxfill(port));
902
903 /* If for any reason we can't copy more data, we're done! */
904 if (count == 0)
905 break;
906
907 if (port->type == PORT_SCI) {
908 char c = sci_serial_in(port, SCxRDR);
909 if (uart_handle_sysrq_char(port, c))
910 count = 0;
911 else
912 tty_insert_flip_char(tport, c, TTY_NORMAL);
913 } else {
914 for (i = 0; i < count; i++) {
915 char c;
916
917 if (port->type == PORT_SCIF ||
918 port->type == PORT_HSCIF) {
919 status = sci_serial_in(port, SCxSR);
920 c = sci_serial_in(port, SCxRDR);
921 } else {
922 c = sci_serial_in(port, SCxRDR);
923 status = sci_serial_in(port, SCxSR);
924 }
925 if (uart_handle_sysrq_char(port, c)) {
926 count--; i--;
927 continue;
928 }
929
930 /* Store data and status */
931 if (status & SCxSR_FER(port)) {
932 flag = TTY_FRAME;
933 port->icount.frame++;
934 } else if (status & SCxSR_PER(port)) {
935 flag = TTY_PARITY;
936 port->icount.parity++;
937 } else
938 flag = TTY_NORMAL;
939
940 tty_insert_flip_char(tport, c, flag);
941 }
942 }
943
944 sci_serial_in(port, SCxSR); /* dummy read */
945 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
946
947 copied += count;
948 port->icount.rx += count;
949 }
950
951 if (copied) {
952 /* Tell the rest of the system the news. New characters! */
953 tty_flip_buffer_push(tport);
954 } else {
955 /* TTY buffers full; read from RX reg to prevent lockup */
956 sci_serial_in(port, SCxRDR);
957 sci_serial_in(port, SCxSR); /* dummy read */
958 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
959 }
960 }
961
sci_handle_errors(struct uart_port * port)962 static int sci_handle_errors(struct uart_port *port)
963 {
964 int copied = 0;
965 struct sci_port *s = to_sci_port(port);
966 const struct sci_common_regs *regs = s->params->common_regs;
967 unsigned int status = s->ops->read_reg(port, regs->status);
968 struct tty_port *tport = &port->state->port;
969
970 /* Handle overruns */
971 if (status & s->params->overrun_mask) {
972 port->icount.overrun++;
973
974 /* overrun error */
975 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
976 copied++;
977 }
978
979 if (status & SCxSR_FER(port)) {
980 /* frame error */
981 port->icount.frame++;
982
983 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
984 copied++;
985 }
986
987 if (status & SCxSR_PER(port)) {
988 /* parity error */
989 port->icount.parity++;
990
991 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
992 copied++;
993 }
994
995 if (copied)
996 tty_flip_buffer_push(tport);
997
998 return copied;
999 }
1000
sci_handle_fifo_overrun(struct uart_port * port)1001 static int sci_handle_fifo_overrun(struct uart_port *port)
1002 {
1003 struct tty_port *tport = &port->state->port;
1004 struct sci_port *s = to_sci_port(port);
1005 const struct plat_sci_reg *reg;
1006 int copied = 0;
1007 u16 status;
1008
1009 reg = sci_getreg(port, s->params->overrun_reg);
1010 if (!reg->size)
1011 return 0;
1012
1013 status = sci_serial_in(port, s->params->overrun_reg);
1014 if (status & s->params->overrun_mask) {
1015 status &= ~s->params->overrun_mask;
1016 sci_serial_out(port, s->params->overrun_reg, status);
1017
1018 port->icount.overrun++;
1019
1020 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1021 tty_flip_buffer_push(tport);
1022 copied++;
1023 }
1024
1025 return copied;
1026 }
1027
sci_handle_breaks(struct uart_port * port)1028 static int sci_handle_breaks(struct uart_port *port)
1029 {
1030 int copied = 0;
1031 unsigned short status = sci_serial_in(port, SCxSR);
1032 struct tty_port *tport = &port->state->port;
1033
1034 if (uart_handle_break(port))
1035 return 0;
1036
1037 if (status & SCxSR_BRK(port)) {
1038 port->icount.brk++;
1039
1040 /* Notify of BREAK */
1041 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1042 copied++;
1043 }
1044
1045 if (copied)
1046 tty_flip_buffer_push(tport);
1047
1048 copied += sci_handle_fifo_overrun(port);
1049
1050 return copied;
1051 }
1052
scif_set_rtrg(struct uart_port * port,int rx_trig)1053 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1054 {
1055 unsigned int bits;
1056
1057 if (rx_trig >= port->fifosize)
1058 rx_trig = port->fifosize - 1;
1059 if (rx_trig < 1)
1060 rx_trig = 1;
1061
1062 /* HSCIF can be set to an arbitrary level. */
1063 if (sci_getreg(port, HSRTRGR)->size) {
1064 sci_serial_out(port, HSRTRGR, rx_trig);
1065 return rx_trig;
1066 }
1067
1068 switch (port->type) {
1069 case PORT_SCIF:
1070 if (rx_trig < 4) {
1071 bits = 0;
1072 rx_trig = 1;
1073 } else if (rx_trig < 8) {
1074 bits = SCFCR_RTRG0;
1075 rx_trig = 4;
1076 } else if (rx_trig < 14) {
1077 bits = SCFCR_RTRG1;
1078 rx_trig = 8;
1079 } else {
1080 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1081 rx_trig = 14;
1082 }
1083 break;
1084 case PORT_SCIFA:
1085 case PORT_SCIFB:
1086 if (rx_trig < 16) {
1087 bits = 0;
1088 rx_trig = 1;
1089 } else if (rx_trig < 32) {
1090 bits = SCFCR_RTRG0;
1091 rx_trig = 16;
1092 } else if (rx_trig < 48) {
1093 bits = SCFCR_RTRG1;
1094 rx_trig = 32;
1095 } else {
1096 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1097 rx_trig = 48;
1098 }
1099 break;
1100 default:
1101 WARN(1, "unknown FIFO configuration");
1102 return 1;
1103 }
1104
1105 sci_serial_out(port, SCFCR,
1106 (sci_serial_in(port, SCFCR) &
1107 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1108
1109 return rx_trig;
1110 }
1111
scif_rtrg_enabled(struct uart_port * port)1112 static int scif_rtrg_enabled(struct uart_port *port)
1113 {
1114 if (sci_getreg(port, HSRTRGR)->size)
1115 return sci_serial_in(port, HSRTRGR) != 0;
1116 else
1117 return (sci_serial_in(port, SCFCR) &
1118 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1119 }
1120
rx_fifo_timer_fn(struct timer_list * t)1121 static void rx_fifo_timer_fn(struct timer_list *t)
1122 {
1123 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer);
1124 struct uart_port *port = &s->port;
1125
1126 dev_dbg(port->dev, "Rx timed out\n");
1127 s->ops->set_rtrg(port, 1);
1128 }
1129
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1130 static ssize_t rx_fifo_trigger_show(struct device *dev,
1131 struct device_attribute *attr, char *buf)
1132 {
1133 struct uart_port *port = dev_get_drvdata(dev);
1134 struct sci_port *sci = to_sci_port(port);
1135
1136 return sprintf(buf, "%d\n", sci->rx_trigger);
1137 }
1138
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1139 static ssize_t rx_fifo_trigger_store(struct device *dev,
1140 struct device_attribute *attr,
1141 const char *buf, size_t count)
1142 {
1143 struct uart_port *port = dev_get_drvdata(dev);
1144 struct sci_port *sci = to_sci_port(port);
1145 int ret;
1146 long r;
1147
1148 ret = kstrtol(buf, 0, &r);
1149 if (ret)
1150 return ret;
1151
1152 sci->rx_trigger = sci->ops->set_rtrg(port, r);
1153 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1154 sci->ops->set_rtrg(port, 1);
1155
1156 return count;
1157 }
1158
1159 static DEVICE_ATTR_RW(rx_fifo_trigger);
1160
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1161 static ssize_t rx_fifo_timeout_show(struct device *dev,
1162 struct device_attribute *attr,
1163 char *buf)
1164 {
1165 struct uart_port *port = dev_get_drvdata(dev);
1166 struct sci_port *sci = to_sci_port(port);
1167 int v;
1168
1169 if (port->type == PORT_HSCIF)
1170 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1171 else
1172 v = sci->rx_fifo_timeout;
1173
1174 return sprintf(buf, "%d\n", v);
1175 }
1176
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1177 static ssize_t rx_fifo_timeout_store(struct device *dev,
1178 struct device_attribute *attr,
1179 const char *buf,
1180 size_t count)
1181 {
1182 struct uart_port *port = dev_get_drvdata(dev);
1183 struct sci_port *sci = to_sci_port(port);
1184 int ret;
1185 long r;
1186
1187 ret = kstrtol(buf, 0, &r);
1188 if (ret)
1189 return ret;
1190
1191 if (port->type == PORT_HSCIF) {
1192 if (r < 0 || r > 3)
1193 return -EINVAL;
1194 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1195 } else {
1196 sci->rx_fifo_timeout = r;
1197 sci->ops->set_rtrg(port, 1);
1198 if (r > 0)
1199 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1200 }
1201
1202 return count;
1203 }
1204
1205 static DEVICE_ATTR_RW(rx_fifo_timeout);
1206
1207
1208 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1209 static void sci_dma_tx_complete(void *arg)
1210 {
1211 struct sci_port *s = arg;
1212 struct uart_port *port = &s->port;
1213 struct tty_port *tport = &port->state->port;
1214 unsigned long flags;
1215
1216 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1217
1218 uart_port_lock_irqsave(port, &flags);
1219
1220 uart_xmit_advance(port, s->tx_dma_len);
1221
1222 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1223 uart_write_wakeup(port);
1224
1225 s->tx_occurred = true;
1226
1227 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1228 s->cookie_tx = 0;
1229 schedule_work(&s->work_tx);
1230 } else {
1231 s->cookie_tx = -EINVAL;
1232 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1233 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1234 u16 ctrl = sci_serial_in(port, SCSCR);
1235 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1236 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1237 /* Switch irq from DMA to SCIF */
1238 dmaengine_pause(s->chan_tx_saved);
1239 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1240 }
1241 }
1242 }
1243
1244 uart_port_unlock_irqrestore(port, flags);
1245 }
1246
1247 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1248 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1249 {
1250 struct uart_port *port = &s->port;
1251 struct tty_port *tport = &port->state->port;
1252 int copied;
1253
1254 copied = tty_insert_flip_string(tport, buf, count);
1255 if (copied < count)
1256 port->icount.buf_overrun++;
1257
1258 port->icount.rx += copied;
1259
1260 return copied;
1261 }
1262
sci_dma_rx_find_active(struct sci_port * s)1263 static int sci_dma_rx_find_active(struct sci_port *s)
1264 {
1265 unsigned int i;
1266
1267 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1268 if (s->active_rx == s->cookie_rx[i])
1269 return i;
1270
1271 return -1;
1272 }
1273
1274 /* Must only be called with uart_port_lock taken */
sci_dma_rx_chan_invalidate(struct sci_port * s)1275 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1276 {
1277 unsigned int i;
1278
1279 s->chan_rx = NULL;
1280 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1281 s->cookie_rx[i] = -EINVAL;
1282 s->active_rx = 0;
1283 }
1284
sci_dma_rx_release(struct sci_port * s)1285 static void sci_dma_rx_release(struct sci_port *s)
1286 {
1287 struct dma_chan *chan = s->chan_rx_saved;
1288 struct uart_port *port = &s->port;
1289 unsigned long flags;
1290
1291 uart_port_lock_irqsave(port, &flags);
1292 s->chan_rx_saved = NULL;
1293 sci_dma_rx_chan_invalidate(s);
1294 uart_port_unlock_irqrestore(port, flags);
1295
1296 dmaengine_terminate_sync(chan);
1297 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1298 sg_dma_address(&s->sg_rx[0]));
1299 dma_release_channel(chan);
1300 }
1301
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1302 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1303 {
1304 long sec = usec / 1000000;
1305 long nsec = (usec % 1000000) * 1000;
1306 ktime_t t = ktime_set(sec, nsec);
1307
1308 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1309 }
1310
sci_dma_rx_reenable_irq(struct sci_port * s)1311 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1312 {
1313 struct uart_port *port = &s->port;
1314 u16 scr;
1315
1316 /* Direct new serial port interrupts back to CPU */
1317 scr = sci_serial_in(port, SCSCR);
1318 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1319 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1320 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1321 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1322 s->ops->set_rtrg(port, s->rx_trigger);
1323 else
1324 scr &= ~SCSCR_RDRQE;
1325 }
1326 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1327 }
1328
sci_dma_rx_complete(void * arg)1329 static void sci_dma_rx_complete(void *arg)
1330 {
1331 struct sci_port *s = arg;
1332 struct dma_chan *chan = s->chan_rx;
1333 struct uart_port *port = &s->port;
1334 struct dma_async_tx_descriptor *desc;
1335 unsigned long flags;
1336 int active, count = 0;
1337
1338 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1339 s->active_rx);
1340
1341 hrtimer_cancel(&s->rx_timer);
1342
1343 uart_port_lock_irqsave(port, &flags);
1344
1345 active = sci_dma_rx_find_active(s);
1346 if (active >= 0)
1347 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1348
1349 if (count)
1350 tty_flip_buffer_push(&port->state->port);
1351
1352 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1353 DMA_DEV_TO_MEM,
1354 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1355 if (!desc)
1356 goto fail;
1357
1358 desc->callback = sci_dma_rx_complete;
1359 desc->callback_param = s;
1360 s->cookie_rx[active] = dmaengine_submit(desc);
1361 if (dma_submit_error(s->cookie_rx[active]))
1362 goto fail;
1363
1364 s->active_rx = s->cookie_rx[!active];
1365
1366 dma_async_issue_pending(chan);
1367
1368 uart_port_unlock_irqrestore(port, flags);
1369 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1370 __func__, s->cookie_rx[active], active, s->active_rx);
1371
1372 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1373
1374 return;
1375
1376 fail:
1377 /* Switch to PIO */
1378 dmaengine_terminate_async(chan);
1379 sci_dma_rx_chan_invalidate(s);
1380 sci_dma_rx_reenable_irq(s);
1381 uart_port_unlock_irqrestore(port, flags);
1382 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1383 }
1384
sci_dma_tx_release(struct sci_port * s)1385 static void sci_dma_tx_release(struct sci_port *s)
1386 {
1387 struct dma_chan *chan = s->chan_tx_saved;
1388
1389 cancel_work_sync(&s->work_tx);
1390 s->chan_tx_saved = s->chan_tx = NULL;
1391 s->cookie_tx = -EINVAL;
1392 dmaengine_terminate_sync(chan);
1393 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1394 DMA_TO_DEVICE);
1395 dma_release_channel(chan);
1396 }
1397
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1398 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1399 {
1400 struct dma_chan *chan = s->chan_rx;
1401 struct uart_port *port = &s->port;
1402 unsigned long flags;
1403 int i;
1404
1405 for (i = 0; i < 2; i++) {
1406 struct scatterlist *sg = &s->sg_rx[i];
1407 struct dma_async_tx_descriptor *desc;
1408
1409 desc = dmaengine_prep_slave_sg(chan,
1410 sg, 1, DMA_DEV_TO_MEM,
1411 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1412 if (!desc)
1413 goto fail;
1414
1415 desc->callback = sci_dma_rx_complete;
1416 desc->callback_param = s;
1417 s->cookie_rx[i] = dmaengine_submit(desc);
1418 if (dma_submit_error(s->cookie_rx[i]))
1419 goto fail;
1420
1421 }
1422
1423 s->active_rx = s->cookie_rx[0];
1424
1425 dma_async_issue_pending(chan);
1426 return 0;
1427
1428 fail:
1429 /* Switch to PIO */
1430 if (!port_lock_held)
1431 uart_port_lock_irqsave(port, &flags);
1432 if (i)
1433 dmaengine_terminate_async(chan);
1434 sci_dma_rx_chan_invalidate(s);
1435 sci_start_rx(port);
1436 if (!port_lock_held)
1437 uart_port_unlock_irqrestore(port, flags);
1438 return -EAGAIN;
1439 }
1440
sci_dma_tx_work_fn(struct work_struct * work)1441 static void sci_dma_tx_work_fn(struct work_struct *work)
1442 {
1443 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1444 struct dma_async_tx_descriptor *desc;
1445 struct dma_chan *chan = s->chan_tx;
1446 struct uart_port *port = &s->port;
1447 struct tty_port *tport = &port->state->port;
1448 unsigned long flags;
1449 unsigned int tail;
1450 dma_addr_t buf;
1451
1452 /*
1453 * DMA is idle now.
1454 * Port xmit buffer is already mapped, and it is one page... Just adjust
1455 * offsets and lengths. Since it is a circular buffer, we have to
1456 * transmit till the end, and then the rest. Take the port lock to get a
1457 * consistent xmit buffer state.
1458 */
1459 uart_port_lock_irq(port);
1460 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1461 UART_XMIT_SIZE);
1462 buf = s->tx_dma_addr + tail;
1463 if (!s->tx_dma_len) {
1464 /* Transmit buffer has been flushed */
1465 uart_port_unlock_irq(port);
1466 return;
1467 }
1468
1469 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1470 DMA_MEM_TO_DEV,
1471 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1472 if (!desc) {
1473 uart_port_unlock_irq(port);
1474 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1475 goto switch_to_pio;
1476 }
1477
1478 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1479 DMA_TO_DEVICE);
1480
1481 desc->callback = sci_dma_tx_complete;
1482 desc->callback_param = s;
1483 s->cookie_tx = dmaengine_submit(desc);
1484 if (dma_submit_error(s->cookie_tx)) {
1485 uart_port_unlock_irq(port);
1486 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1487 goto switch_to_pio;
1488 }
1489
1490 uart_port_unlock_irq(port);
1491 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1492 __func__, tport->xmit_buf, tail, s->cookie_tx);
1493
1494 dma_async_issue_pending(chan);
1495 return;
1496
1497 switch_to_pio:
1498 uart_port_lock_irqsave(port, &flags);
1499 s->chan_tx = NULL;
1500 sci_start_tx(port);
1501 uart_port_unlock_irqrestore(port, flags);
1502 return;
1503 }
1504
sci_dma_rx_timer_fn(struct hrtimer * t)1505 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1506 {
1507 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1508 struct dma_chan *chan = s->chan_rx;
1509 struct uart_port *port = &s->port;
1510 struct dma_tx_state state;
1511 enum dma_status status;
1512 unsigned long flags;
1513 unsigned int read;
1514 int active, count;
1515
1516 dev_dbg(port->dev, "DMA Rx timed out\n");
1517
1518 uart_port_lock_irqsave(port, &flags);
1519
1520 active = sci_dma_rx_find_active(s);
1521 if (active < 0) {
1522 uart_port_unlock_irqrestore(port, flags);
1523 return HRTIMER_NORESTART;
1524 }
1525
1526 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1527 if (status == DMA_COMPLETE) {
1528 uart_port_unlock_irqrestore(port, flags);
1529 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1530 s->active_rx, active);
1531
1532 /* Let packet complete handler take care of the packet */
1533 return HRTIMER_NORESTART;
1534 }
1535
1536 dmaengine_pause(chan);
1537
1538 /*
1539 * sometimes DMA transfer doesn't stop even if it is stopped and
1540 * data keeps on coming until transaction is complete so check
1541 * for DMA_COMPLETE again
1542 * Let packet complete handler take care of the packet
1543 */
1544 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1545 if (status == DMA_COMPLETE) {
1546 uart_port_unlock_irqrestore(port, flags);
1547 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1548 return HRTIMER_NORESTART;
1549 }
1550
1551 /* Handle incomplete DMA receive */
1552 dmaengine_terminate_async(s->chan_rx);
1553 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1554
1555 if (read) {
1556 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1557 if (count)
1558 tty_flip_buffer_push(&port->state->port);
1559 }
1560
1561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1562 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1563 sci_dma_rx_submit(s, true);
1564
1565 sci_dma_rx_reenable_irq(s);
1566
1567 uart_port_unlock_irqrestore(port, flags);
1568
1569 return HRTIMER_NORESTART;
1570 }
1571
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1572 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1573 enum dma_transfer_direction dir)
1574 {
1575 struct dma_chan *chan;
1576 struct dma_slave_config cfg;
1577 int ret;
1578
1579 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1580 if (IS_ERR(chan)) {
1581 dev_dbg(port->dev, "dma_request_chan failed\n");
1582 return NULL;
1583 }
1584
1585 memset(&cfg, 0, sizeof(cfg));
1586 cfg.direction = dir;
1587 cfg.dst_addr = port->mapbase +
1588 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1589 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1590 cfg.src_addr = port->mapbase +
1591 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1592 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1593
1594 ret = dmaengine_slave_config(chan, &cfg);
1595 if (ret) {
1596 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1597 dma_release_channel(chan);
1598 return NULL;
1599 }
1600
1601 return chan;
1602 }
1603
sci_request_dma(struct uart_port * port)1604 static void sci_request_dma(struct uart_port *port)
1605 {
1606 struct sci_port *s = to_sci_port(port);
1607 struct tty_port *tport = &port->state->port;
1608 struct dma_chan *chan;
1609
1610 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1611
1612 /*
1613 * DMA on console may interfere with Kernel log messages which use
1614 * plain putchar(). So, simply don't use it with a console.
1615 */
1616 if (uart_console(port))
1617 return;
1618
1619 if (!port->dev->of_node)
1620 return;
1621
1622 s->cookie_tx = -EINVAL;
1623
1624 /*
1625 * Don't request a dma channel if no channel was specified
1626 * in the device tree.
1627 */
1628 if (!of_property_present(port->dev->of_node, "dmas"))
1629 return;
1630
1631 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1632 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1633 if (chan) {
1634 /* UART circular tx buffer is an aligned page. */
1635 s->tx_dma_addr = dma_map_single(chan->device->dev,
1636 tport->xmit_buf,
1637 UART_XMIT_SIZE,
1638 DMA_TO_DEVICE);
1639 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1640 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1641 dma_release_channel(chan);
1642 } else {
1643 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1644 __func__, UART_XMIT_SIZE,
1645 tport->xmit_buf, &s->tx_dma_addr);
1646
1647 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1648 s->chan_tx_saved = s->chan_tx = chan;
1649 }
1650 }
1651
1652 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1653 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1654 if (chan) {
1655 unsigned int i;
1656 dma_addr_t dma;
1657 void *buf;
1658
1659 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1660 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1661 &dma, GFP_KERNEL);
1662 if (!buf) {
1663 dev_warn(port->dev,
1664 "Failed to allocate Rx dma buffer, using PIO\n");
1665 dma_release_channel(chan);
1666 return;
1667 }
1668
1669 for (i = 0; i < 2; i++) {
1670 struct scatterlist *sg = &s->sg_rx[i];
1671
1672 sg_init_table(sg, 1);
1673 s->rx_buf[i] = buf;
1674 sg_dma_address(sg) = dma;
1675 sg_dma_len(sg) = s->buf_len_rx;
1676
1677 buf += s->buf_len_rx;
1678 dma += s->buf_len_rx;
1679 }
1680
1681 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1682
1683 s->chan_rx_saved = s->chan_rx = chan;
1684
1685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1686 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1687 sci_dma_rx_submit(s, false);
1688 }
1689 }
1690
sci_free_dma(struct uart_port * port)1691 static void sci_free_dma(struct uart_port *port)
1692 {
1693 struct sci_port *s = to_sci_port(port);
1694
1695 if (s->chan_tx_saved)
1696 sci_dma_tx_release(s);
1697 if (s->chan_rx_saved)
1698 sci_dma_rx_release(s);
1699 }
1700
sci_flush_buffer(struct uart_port * port)1701 static void sci_flush_buffer(struct uart_port *port)
1702 {
1703 struct sci_port *s = to_sci_port(port);
1704
1705 /*
1706 * In uart_flush_buffer(), the xmit circular buffer has just been
1707 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1708 * pending transfers
1709 */
1710 s->tx_dma_len = 0;
1711 if (s->chan_tx) {
1712 dmaengine_terminate_async(s->chan_tx);
1713 s->cookie_tx = -EINVAL;
1714 }
1715 }
1716
sci_dma_check_tx_occurred(struct sci_port * s)1717 static void sci_dma_check_tx_occurred(struct sci_port *s)
1718 {
1719 struct dma_tx_state state;
1720 enum dma_status status;
1721
1722 if (!s->chan_tx)
1723 return;
1724
1725 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1726 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1727 s->tx_occurred = true;
1728 }
1729 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1730 static inline void sci_request_dma(struct uart_port *port)
1731 {
1732 }
1733
sci_free_dma(struct uart_port * port)1734 static inline void sci_free_dma(struct uart_port *port)
1735 {
1736 }
1737
sci_dma_check_tx_occurred(struct sci_port * s)1738 static void sci_dma_check_tx_occurred(struct sci_port *s)
1739 {
1740 }
1741
1742 #define sci_flush_buffer NULL
1743 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1744
sci_rx_interrupt(int irq,void * ptr)1745 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1746 {
1747 struct uart_port *port = ptr;
1748 struct sci_port *s = to_sci_port(port);
1749
1750 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1751 if (s->chan_rx) {
1752 u16 scr = sci_serial_in(port, SCSCR);
1753 u16 ssr = sci_serial_in(port, SCxSR);
1754
1755 /* Disable future Rx interrupts */
1756 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1757 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1758 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1759 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1760 s->ops->set_rtrg(port, 1);
1761 scr |= SCSCR_RIE;
1762 } else {
1763 scr |= SCSCR_RDRQE;
1764 }
1765 } else {
1766 if (sci_dma_rx_submit(s, false) < 0)
1767 goto handle_pio;
1768
1769 scr &= ~SCSCR_RIE;
1770 }
1771 sci_serial_out(port, SCSCR, scr);
1772 /* Clear current interrupt */
1773 sci_serial_out(port, SCxSR,
1774 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1775 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1776 jiffies, s->rx_timeout);
1777 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1778
1779 return IRQ_HANDLED;
1780 }
1781
1782 handle_pio:
1783 #endif
1784
1785 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1786 if (!s->ops->rtrg_enabled(port))
1787 s->ops->set_rtrg(port, s->rx_trigger);
1788
1789 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1790 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1791 }
1792
1793 /* I think sci_receive_chars has to be called irrespective
1794 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1795 * to be disabled?
1796 */
1797 s->ops->receive_chars(port);
1798
1799 return IRQ_HANDLED;
1800 }
1801
sci_tx_interrupt(int irq,void * ptr)1802 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1803 {
1804 struct uart_port *port = ptr;
1805 unsigned long flags;
1806 struct sci_port *s = to_sci_port(port);
1807
1808 uart_port_lock_irqsave(port, &flags);
1809 s->ops->transmit_chars(port);
1810 uart_port_unlock_irqrestore(port, flags);
1811
1812 return IRQ_HANDLED;
1813 }
1814
sci_tx_end_interrupt(int irq,void * ptr)1815 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1816 {
1817 struct uart_port *port = ptr;
1818 struct sci_port *s = to_sci_port(port);
1819 const struct sci_common_regs *regs = s->params->common_regs;
1820 unsigned long flags;
1821 u32 ctrl;
1822
1823 if (port->type != PORT_SCI)
1824 return sci_tx_interrupt(irq, ptr);
1825
1826 uart_port_lock_irqsave(port, &flags);
1827 ctrl = s->ops->read_reg(port, regs->control) &
1828 ~(s->params->param_bits->te_clear);
1829 s->ops->write_reg(port, regs->control, ctrl);
1830 uart_port_unlock_irqrestore(port, flags);
1831
1832 return IRQ_HANDLED;
1833 }
1834
sci_br_interrupt(int irq,void * ptr)1835 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1836 {
1837 struct uart_port *port = ptr;
1838 struct sci_port *s = to_sci_port(port);
1839
1840 /* Handle BREAKs */
1841 sci_handle_breaks(port);
1842
1843 /* drop invalid character received before break was detected */
1844 sci_serial_in(port, SCxRDR);
1845
1846 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1847
1848 return IRQ_HANDLED;
1849 }
1850
sci_er_interrupt(int irq,void * ptr)1851 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1852 {
1853 struct uart_port *port = ptr;
1854 struct sci_port *s = to_sci_port(port);
1855
1856 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1857 /* Break and Error interrupts are muxed */
1858 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1859
1860 /* Break Interrupt */
1861 if (ssr_status & SCxSR_BRK(port))
1862 sci_br_interrupt(irq, ptr);
1863
1864 /* Break only? */
1865 if (!(ssr_status & SCxSR_ERRORS(port)))
1866 return IRQ_HANDLED;
1867 }
1868
1869 /* Handle errors */
1870 if (port->type == PORT_SCI) {
1871 if (sci_handle_errors(port)) {
1872 /* discard character in rx buffer */
1873 sci_serial_in(port, SCxSR);
1874 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1875 }
1876 } else {
1877 sci_handle_fifo_overrun(port);
1878 if (!s->chan_rx)
1879 s->ops->receive_chars(port);
1880 }
1881
1882 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1883
1884 /* Kick the transmission */
1885 if (!s->chan_tx)
1886 sci_tx_interrupt(irq, ptr);
1887
1888 return IRQ_HANDLED;
1889 }
1890
sci_mpxed_interrupt(int irq,void * ptr)1891 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1892 {
1893 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1894 struct uart_port *port = ptr;
1895 struct sci_port *s = to_sci_port(port);
1896 irqreturn_t ret = IRQ_NONE;
1897
1898 ssr_status = sci_serial_in(port, SCxSR);
1899 scr_status = sci_serial_in(port, SCSCR);
1900 if (s->params->overrun_reg == SCxSR)
1901 orer_status = ssr_status;
1902 else if (sci_getreg(port, s->params->overrun_reg)->size)
1903 orer_status = sci_serial_in(port, s->params->overrun_reg);
1904
1905 err_enabled = scr_status & port_rx_irq_mask(port);
1906
1907 /* Tx Interrupt */
1908 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1909 !s->chan_tx)
1910 ret = sci_tx_interrupt(irq, ptr);
1911
1912 /*
1913 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1914 * DR flags
1915 */
1916 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1917 (scr_status & SCSCR_RIE))
1918 ret = sci_rx_interrupt(irq, ptr);
1919
1920 /* Error Interrupt */
1921 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1922 ret = sci_er_interrupt(irq, ptr);
1923
1924 /* Break Interrupt */
1925 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1926 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1927 ret = sci_br_interrupt(irq, ptr);
1928
1929 /* Overrun Interrupt */
1930 if (orer_status & s->params->overrun_mask) {
1931 sci_handle_fifo_overrun(port);
1932 ret = IRQ_HANDLED;
1933 }
1934
1935 return ret;
1936 }
1937
1938 static const struct sci_irq_desc {
1939 const char *desc;
1940 irq_handler_t handler;
1941 } sci_irq_desc[] = {
1942 /*
1943 * Split out handlers, the default case.
1944 */
1945 [SCIx_ERI_IRQ] = {
1946 .desc = "rx err",
1947 .handler = sci_er_interrupt,
1948 },
1949
1950 [SCIx_RXI_IRQ] = {
1951 .desc = "rx full",
1952 .handler = sci_rx_interrupt,
1953 },
1954
1955 [SCIx_TXI_IRQ] = {
1956 .desc = "tx empty",
1957 .handler = sci_tx_interrupt,
1958 },
1959
1960 [SCIx_BRI_IRQ] = {
1961 .desc = "break",
1962 .handler = sci_br_interrupt,
1963 },
1964
1965 [SCIx_DRI_IRQ] = {
1966 .desc = "rx ready",
1967 .handler = sci_rx_interrupt,
1968 },
1969
1970 [SCIx_TEI_IRQ] = {
1971 .desc = "tx end",
1972 .handler = sci_tx_end_interrupt,
1973 },
1974
1975 /*
1976 * Special muxed handler.
1977 */
1978 [SCIx_MUX_IRQ] = {
1979 .desc = "mux",
1980 .handler = sci_mpxed_interrupt,
1981 },
1982 };
1983
sci_request_irq(struct sci_port * port)1984 static int sci_request_irq(struct sci_port *port)
1985 {
1986 struct uart_port *up = &port->port;
1987 int i, j, w, ret = 0;
1988
1989 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1990 const struct sci_irq_desc *desc;
1991 int irq;
1992
1993 /* Check if already registered (muxed) */
1994 for (w = 0; w < i; w++)
1995 if (port->irqs[w] == port->irqs[i])
1996 w = i + 1;
1997 if (w > i)
1998 continue;
1999
2000 if (SCIx_IRQ_IS_MUXED(port)) {
2001 i = SCIx_MUX_IRQ;
2002 irq = up->irq;
2003 } else {
2004 irq = port->irqs[i];
2005
2006 /*
2007 * Certain port types won't support all of the
2008 * available interrupt sources.
2009 */
2010 if (unlikely(irq < 0))
2011 continue;
2012 }
2013
2014 desc = sci_irq_desc + i;
2015 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2016 dev_name(up->dev), desc->desc);
2017 if (!port->irqstr[j]) {
2018 ret = -ENOMEM;
2019 goto out_nomem;
2020 }
2021
2022 ret = request_irq(irq, desc->handler, up->irqflags,
2023 port->irqstr[j], port);
2024 if (unlikely(ret)) {
2025 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2026 goto out_noirq;
2027 }
2028 }
2029
2030 return 0;
2031
2032 out_noirq:
2033 while (--i >= 0)
2034 free_irq(port->irqs[i], port);
2035
2036 out_nomem:
2037 while (--j >= 0)
2038 kfree(port->irqstr[j]);
2039
2040 return ret;
2041 }
2042
sci_free_irq(struct sci_port * port)2043 static void sci_free_irq(struct sci_port *port)
2044 {
2045 int i, j;
2046
2047 /*
2048 * Intentionally in reverse order so we iterate over the muxed
2049 * IRQ first.
2050 */
2051 for (i = 0; i < SCIx_NR_IRQS; i++) {
2052 int irq = port->irqs[i];
2053
2054 /*
2055 * Certain port types won't support all of the available
2056 * interrupt sources.
2057 */
2058 if (unlikely(irq < 0))
2059 continue;
2060
2061 /* Check if already freed (irq was muxed) */
2062 for (j = 0; j < i; j++)
2063 if (port->irqs[j] == irq)
2064 j = i + 1;
2065 if (j > i)
2066 continue;
2067
2068 free_irq(port->irqs[i], port);
2069 kfree(port->irqstr[i]);
2070
2071 if (SCIx_IRQ_IS_MUXED(port)) {
2072 /* If there's only one IRQ, we're done. */
2073 return;
2074 }
2075 }
2076 }
2077
sci_tx_empty(struct uart_port * port)2078 static unsigned int sci_tx_empty(struct uart_port *port)
2079 {
2080 unsigned short status = sci_serial_in(port, SCxSR);
2081 unsigned short in_tx_fifo = sci_txfill(port);
2082 struct sci_port *s = to_sci_port(port);
2083
2084 sci_dma_check_tx_occurred(s);
2085
2086 if (!s->tx_occurred)
2087 return TIOCSER_TEMT;
2088
2089 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2090 }
2091
sci_set_rts(struct uart_port * port,bool state)2092 static void sci_set_rts(struct uart_port *port, bool state)
2093 {
2094 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2095 u16 data = sci_serial_in(port, SCPDR);
2096
2097 /* Active low */
2098 if (state)
2099 data &= ~SCPDR_RTSD;
2100 else
2101 data |= SCPDR_RTSD;
2102 sci_serial_out(port, SCPDR, data);
2103
2104 /* RTS# is output */
2105 sci_serial_out(port, SCPCR,
2106 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2107 } else if (sci_getreg(port, SCSPTR)->size) {
2108 u16 ctrl = sci_serial_in(port, SCSPTR);
2109
2110 /* Active low */
2111 if (state)
2112 ctrl &= ~SCSPTR_RTSDT;
2113 else
2114 ctrl |= SCSPTR_RTSDT;
2115 sci_serial_out(port, SCSPTR, ctrl);
2116 }
2117 }
2118
sci_get_cts(struct uart_port * port)2119 static bool sci_get_cts(struct uart_port *port)
2120 {
2121 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2122 /* Active low */
2123 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2124 } else if (sci_getreg(port, SCSPTR)->size) {
2125 /* Active low */
2126 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2127 }
2128
2129 return true;
2130 }
2131
2132 /*
2133 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2134 * CTS/RTS is supported in hardware by at least one port and controlled
2135 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2136 * handled via the ->init_pins() op, which is a bit of a one-way street,
2137 * lacking any ability to defer pin control -- this will later be
2138 * converted over to the GPIO framework).
2139 *
2140 * Other modes (such as loopback) are supported generically on certain
2141 * port types, but not others. For these it's sufficient to test for the
2142 * existence of the support register and simply ignore the port type.
2143 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2144 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2145 {
2146 struct sci_port *s = to_sci_port(port);
2147
2148 if (mctrl & TIOCM_LOOP) {
2149 const struct plat_sci_reg *reg;
2150
2151 /*
2152 * Standard loopback mode for SCFCR ports.
2153 */
2154 reg = sci_getreg(port, SCFCR);
2155 if (reg->size)
2156 sci_serial_out(port, SCFCR,
2157 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2158 }
2159
2160 mctrl_gpio_set(s->gpios, mctrl);
2161
2162 if (!s->has_rtscts)
2163 return;
2164
2165 if (!(mctrl & TIOCM_RTS)) {
2166 /* Disable Auto RTS */
2167 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2168 sci_serial_out(port, SCFCR,
2169 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2170
2171 /* Clear RTS */
2172 sci_set_rts(port, 0);
2173 } else if (s->autorts) {
2174 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2175 /* Enable RTS# pin function */
2176 sci_serial_out(port, SCPCR,
2177 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2178 }
2179
2180 /* Enable Auto RTS */
2181 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2182 sci_serial_out(port, SCFCR,
2183 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2184 } else {
2185 /* Set RTS */
2186 sci_set_rts(port, 1);
2187 }
2188 }
2189
sci_get_mctrl(struct uart_port * port)2190 static unsigned int sci_get_mctrl(struct uart_port *port)
2191 {
2192 struct sci_port *s = to_sci_port(port);
2193 struct mctrl_gpios *gpios = s->gpios;
2194 unsigned int mctrl = 0;
2195
2196 mctrl_gpio_get(gpios, &mctrl);
2197
2198 /*
2199 * CTS/RTS is handled in hardware when supported, while nothing
2200 * else is wired up.
2201 */
2202 if (s->autorts) {
2203 if (sci_get_cts(port))
2204 mctrl |= TIOCM_CTS;
2205 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2206 mctrl |= TIOCM_CTS;
2207 }
2208 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2209 mctrl |= TIOCM_DSR;
2210 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2211 mctrl |= TIOCM_CAR;
2212
2213 return mctrl;
2214 }
2215
sci_enable_ms(struct uart_port * port)2216 static void sci_enable_ms(struct uart_port *port)
2217 {
2218 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2219 }
2220
sci_break_ctl(struct uart_port * port,int break_state)2221 static void sci_break_ctl(struct uart_port *port, int break_state)
2222 {
2223 unsigned short scscr, scsptr;
2224 unsigned long flags;
2225
2226 /* check whether the port has SCSPTR */
2227 if (!sci_getreg(port, SCSPTR)->size) {
2228 /*
2229 * Not supported by hardware. Most parts couple break and rx
2230 * interrupts together, with break detection always enabled.
2231 */
2232 return;
2233 }
2234
2235 uart_port_lock_irqsave(port, &flags);
2236 scsptr = sci_serial_in(port, SCSPTR);
2237 scscr = sci_serial_in(port, SCSCR);
2238
2239 if (break_state == -1) {
2240 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2241 scscr &= ~SCSCR_TE;
2242 } else {
2243 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2244 scscr |= SCSCR_TE;
2245 }
2246
2247 sci_serial_out(port, SCSPTR, scsptr);
2248 sci_serial_out(port, SCSCR, scscr);
2249 uart_port_unlock_irqrestore(port, flags);
2250 }
2251
sci_shutdown_complete(struct uart_port * port)2252 static void sci_shutdown_complete(struct uart_port *port)
2253 {
2254 struct sci_port *s = to_sci_port(port);
2255 u16 scr;
2256
2257 scr = sci_serial_in(port, SCSCR);
2258 sci_serial_out(port, SCSCR,
2259 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2260 }
2261
sci_startup(struct uart_port * port)2262 int sci_startup(struct uart_port *port)
2263 {
2264 struct sci_port *s = to_sci_port(port);
2265 int ret;
2266
2267 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2268
2269 s->tx_occurred = false;
2270 sci_request_dma(port);
2271
2272 ret = sci_request_irq(s);
2273 if (unlikely(ret < 0)) {
2274 sci_free_dma(port);
2275 return ret;
2276 }
2277
2278 return 0;
2279 }
2280
sci_shutdown(struct uart_port * port)2281 void sci_shutdown(struct uart_port *port)
2282 {
2283 struct sci_port *s = to_sci_port(port);
2284 unsigned long flags;
2285
2286 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2287
2288 s->autorts = false;
2289 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2290
2291 uart_port_lock_irqsave(port, &flags);
2292 sci_stop_rx(port);
2293 sci_stop_tx(port);
2294 s->ops->shutdown_complete(port);
2295 uart_port_unlock_irqrestore(port, flags);
2296
2297 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2298 if (s->chan_rx_saved) {
2299 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2300 port->line);
2301 hrtimer_cancel(&s->rx_timer);
2302 }
2303 #endif
2304
2305 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2306 timer_delete_sync(&s->rx_fifo_timer);
2307 sci_free_irq(s);
2308 sci_free_dma(port);
2309 }
2310
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2311 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2312 unsigned int *srr)
2313 {
2314 unsigned long freq = s->clk_rates[SCI_SCK];
2315 int err, min_err = INT_MAX;
2316 unsigned int sr;
2317
2318 if (s->port.type != PORT_HSCIF)
2319 freq *= 2;
2320
2321 for_each_sr(sr, s) {
2322 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2323 if (abs(err) >= abs(min_err))
2324 continue;
2325
2326 min_err = err;
2327 *srr = sr - 1;
2328
2329 if (!err)
2330 break;
2331 }
2332
2333 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2334 *srr + 1);
2335 return min_err;
2336 }
2337
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2338 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2339 unsigned long freq, unsigned int *dlr,
2340 unsigned int *srr)
2341 {
2342 int err, min_err = INT_MAX;
2343 unsigned int sr, dl;
2344
2345 if (s->port.type != PORT_HSCIF)
2346 freq *= 2;
2347
2348 for_each_sr(sr, s) {
2349 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2350 dl = clamp(dl, 1U, 65535U);
2351
2352 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2353 if (abs(err) >= abs(min_err))
2354 continue;
2355
2356 min_err = err;
2357 *dlr = dl;
2358 *srr = sr - 1;
2359
2360 if (!err)
2361 break;
2362 }
2363
2364 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2365 min_err, *dlr, *srr + 1);
2366 return min_err;
2367 }
2368
2369 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2370 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2371 unsigned int *brr, unsigned int *srr,
2372 unsigned int *cks)
2373 {
2374 unsigned long freq = s->clk_rates[SCI_FCK];
2375 unsigned int sr, br, prediv, scrate, c;
2376 int err, min_err = INT_MAX;
2377
2378 if (s->port.type != PORT_HSCIF)
2379 freq *= 2;
2380
2381 /*
2382 * Find the combination of sample rate and clock select with the
2383 * smallest deviation from the desired baud rate.
2384 * Prefer high sample rates to maximise the receive margin.
2385 *
2386 * M: Receive margin (%)
2387 * N: Ratio of bit rate to clock (N = sampling rate)
2388 * D: Clock duty (D = 0 to 1.0)
2389 * L: Frame length (L = 9 to 12)
2390 * F: Absolute value of clock frequency deviation
2391 *
2392 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2393 * (|D - 0.5| / N * (1 + F))|
2394 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2395 */
2396 for_each_sr(sr, s) {
2397 for (c = 0; c <= 3; c++) {
2398 /* integerized formulas from HSCIF documentation */
2399 prediv = sr << (2 * c + 1);
2400
2401 /*
2402 * We need to calculate:
2403 *
2404 * br = freq / (prediv * bps) clamped to [1..256]
2405 * err = freq / (br * prediv) - bps
2406 *
2407 * Watch out for overflow when calculating the desired
2408 * sampling clock rate!
2409 */
2410 if (bps > UINT_MAX / prediv)
2411 break;
2412
2413 scrate = prediv * bps;
2414 br = DIV_ROUND_CLOSEST(freq, scrate);
2415 br = clamp(br, 1U, 256U);
2416
2417 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2418 if (abs(err) >= abs(min_err))
2419 continue;
2420
2421 min_err = err;
2422 *brr = br - 1;
2423 *srr = sr - 1;
2424 *cks = c;
2425
2426 if (!err)
2427 goto found;
2428 }
2429 }
2430
2431 found:
2432 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2433 min_err, *brr, *srr + 1, *cks);
2434 return min_err;
2435 }
2436
sci_reset(struct uart_port * port)2437 static void sci_reset(struct uart_port *port)
2438 {
2439 const struct plat_sci_reg *reg;
2440 unsigned int status;
2441 struct sci_port *s = to_sci_port(port);
2442
2443 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2444
2445 reg = sci_getreg(port, SCFCR);
2446 if (reg->size)
2447 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2448
2449 s->ops->clear_SCxSR(port,
2450 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2451 SCxSR_BREAK_CLEAR(port));
2452 if (sci_getreg(port, SCLSR)->size) {
2453 status = sci_serial_in(port, SCLSR);
2454 status &= ~(SCLSR_TO | SCLSR_ORER);
2455 sci_serial_out(port, SCLSR, status);
2456 }
2457
2458 if (s->rx_trigger > 1) {
2459 if (s->rx_fifo_timeout) {
2460 s->ops->set_rtrg(port, 1);
2461 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2462 } else {
2463 if (port->type == PORT_SCIFA ||
2464 port->type == PORT_SCIFB)
2465 s->ops->set_rtrg(port, 1);
2466 else
2467 s->ops->set_rtrg(port, s->rx_trigger);
2468 }
2469 }
2470 }
2471
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2472 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2473 const struct ktermios *old)
2474 {
2475 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2476 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2477 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2478 struct sci_port *s = to_sci_port(port);
2479 const struct plat_sci_reg *reg;
2480 int min_err = INT_MAX, err;
2481 unsigned long max_freq = 0;
2482 int best_clk = -1;
2483 unsigned long flags;
2484
2485 if ((termios->c_cflag & CSIZE) == CS7) {
2486 smr_val |= SCSMR_CHR;
2487 } else {
2488 termios->c_cflag &= ~CSIZE;
2489 termios->c_cflag |= CS8;
2490 }
2491 if (termios->c_cflag & PARENB)
2492 smr_val |= SCSMR_PE;
2493 if (termios->c_cflag & PARODD)
2494 smr_val |= SCSMR_PE | SCSMR_ODD;
2495 if (termios->c_cflag & CSTOPB)
2496 smr_val |= SCSMR_STOP;
2497
2498 /*
2499 * earlyprintk comes here early on with port->uartclk set to zero.
2500 * the clock framework is not up and running at this point so here
2501 * we assume that 115200 is the maximum baud rate. please note that
2502 * the baud rate is not programmed during earlyprintk - it is assumed
2503 * that the previous boot loader has enabled required clocks and
2504 * setup the baud rate generator hardware for us already.
2505 */
2506 if (!port->uartclk) {
2507 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2508 goto done;
2509 }
2510
2511 for (i = 0; i < SCI_NUM_CLKS; i++)
2512 max_freq = max(max_freq, s->clk_rates[i]);
2513
2514 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2515 if (!baud)
2516 goto done;
2517
2518 /*
2519 * There can be multiple sources for the sampling clock. Find the one
2520 * that gives us the smallest deviation from the desired baud rate.
2521 */
2522
2523 /* Optional Undivided External Clock */
2524 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2525 port->type != PORT_SCIFB) {
2526 err = sci_sck_calc(s, baud, &srr1);
2527 if (abs(err) < abs(min_err)) {
2528 best_clk = SCI_SCK;
2529 scr_val = SCSCR_CKE1;
2530 sccks = SCCKS_CKS;
2531 min_err = err;
2532 srr = srr1;
2533 if (!err)
2534 goto done;
2535 }
2536 }
2537
2538 /* Optional BRG Frequency Divided External Clock */
2539 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2540 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2541 &srr1);
2542 if (abs(err) < abs(min_err)) {
2543 best_clk = SCI_SCIF_CLK;
2544 scr_val = SCSCR_CKE1;
2545 sccks = 0;
2546 min_err = err;
2547 dl = dl1;
2548 srr = srr1;
2549 if (!err)
2550 goto done;
2551 }
2552 }
2553
2554 /* Optional BRG Frequency Divided Internal Clock */
2555 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2556 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2557 &srr1);
2558 if (abs(err) < abs(min_err)) {
2559 best_clk = SCI_BRG_INT;
2560 scr_val = SCSCR_CKE1;
2561 sccks = SCCKS_XIN;
2562 min_err = err;
2563 dl = dl1;
2564 srr = srr1;
2565 if (!min_err)
2566 goto done;
2567 }
2568 }
2569
2570 /* Divided Functional Clock using standard Bit Rate Register */
2571 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2572 if (abs(err) < abs(min_err)) {
2573 best_clk = SCI_FCK;
2574 scr_val = 0;
2575 min_err = err;
2576 brr = brr1;
2577 srr = srr1;
2578 cks = cks1;
2579 }
2580
2581 done:
2582 if (best_clk >= 0)
2583 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2584 s->clks[best_clk], baud, min_err);
2585
2586 sci_port_enable(s);
2587
2588 /*
2589 * Program the optional External Baud Rate Generator (BRG) first.
2590 * It controls the mux to select (H)SCK or frequency divided clock.
2591 */
2592 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2593 sci_serial_out(port, SCDL, dl);
2594 sci_serial_out(port, SCCKS, sccks);
2595 }
2596
2597 uart_port_lock_irqsave(port, &flags);
2598
2599 sci_reset(port);
2600
2601 uart_update_timeout(port, termios->c_cflag, baud);
2602
2603 /* byte size and parity */
2604 bits = tty_get_frame_size(termios->c_cflag);
2605
2606 if (sci_getreg(port, SEMR)->size)
2607 sci_serial_out(port, SEMR, 0);
2608
2609 if (best_clk >= 0) {
2610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2611 switch (srr + 1) {
2612 case 5: smr_val |= SCSMR_SRC_5; break;
2613 case 7: smr_val |= SCSMR_SRC_7; break;
2614 case 11: smr_val |= SCSMR_SRC_11; break;
2615 case 13: smr_val |= SCSMR_SRC_13; break;
2616 case 16: smr_val |= SCSMR_SRC_16; break;
2617 case 17: smr_val |= SCSMR_SRC_17; break;
2618 case 19: smr_val |= SCSMR_SRC_19; break;
2619 case 27: smr_val |= SCSMR_SRC_27; break;
2620 }
2621 smr_val |= cks;
2622 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2623 sci_serial_out(port, SCSMR, smr_val);
2624 sci_serial_out(port, SCBRR, brr);
2625 if (sci_getreg(port, HSSRR)->size) {
2626 unsigned int hssrr = srr | HSCIF_SRE;
2627 /* Calculate deviation from intended rate at the
2628 * center of the last stop bit in sampling clocks.
2629 */
2630 int last_stop = bits * 2 - 1;
2631 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2632 (int)(srr + 1),
2633 2 * (int)baud);
2634
2635 if (abs(deviation) >= 2) {
2636 /* At least two sampling clocks off at the
2637 * last stop bit; we can increase the error
2638 * margin by shifting the sampling point.
2639 */
2640 int shift = clamp(deviation / 2, -8, 7);
2641
2642 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2643 HSCIF_SRHP_MASK;
2644 hssrr |= HSCIF_SRDE;
2645 }
2646 sci_serial_out(port, HSSRR, hssrr);
2647 }
2648
2649 /* Wait one bit interval */
2650 udelay((1000000 + (baud - 1)) / baud);
2651 } else {
2652 /* Don't touch the bit rate configuration */
2653 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2654 smr_val |= sci_serial_in(port, SCSMR) &
2655 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2656 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2657 sci_serial_out(port, SCSMR, smr_val);
2658 }
2659
2660 sci_init_pins(port, termios->c_cflag);
2661
2662 port->status &= ~UPSTAT_AUTOCTS;
2663 s->autorts = false;
2664 reg = sci_getreg(port, SCFCR);
2665 if (reg->size) {
2666 unsigned short ctrl = sci_serial_in(port, SCFCR);
2667
2668 if ((port->flags & UPF_HARD_FLOW) &&
2669 (termios->c_cflag & CRTSCTS)) {
2670 /* There is no CTS interrupt to restart the hardware */
2671 port->status |= UPSTAT_AUTOCTS;
2672 /* MCE is enabled when RTS is raised */
2673 s->autorts = true;
2674 }
2675
2676 /*
2677 * As we've done a sci_reset() above, ensure we don't
2678 * interfere with the FIFOs while toggling MCE. As the
2679 * reset values could still be set, simply mask them out.
2680 */
2681 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2682
2683 sci_serial_out(port, SCFCR, ctrl);
2684 }
2685 if (port->flags & UPF_HARD_FLOW) {
2686 /* Refresh (Auto) RTS */
2687 sci_set_mctrl(port, port->mctrl);
2688 }
2689
2690 /*
2691 * For SCI, TE (transmit enable) must be set after setting TIE
2692 * (transmit interrupt enable) or in the same instruction to
2693 * start the transmitting process. So skip setting TE here for SCI.
2694 */
2695 if (port->type != PORT_SCI)
2696 scr_val |= SCSCR_TE;
2697 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2698 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2699 if ((srr + 1 == 5) &&
2700 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2701 /*
2702 * In asynchronous mode, when the sampling rate is 1/5, first
2703 * received data may become invalid on some SCIFA and SCIFB.
2704 * To avoid this problem wait more than 1 serial data time (1
2705 * bit time x serial data number) after setting SCSCR.RE = 1.
2706 */
2707 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2708 }
2709
2710 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2711 s->rx_frame = (10000 * bits) / (baud / 100);
2712 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2713 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2714 #endif
2715
2716 if ((termios->c_cflag & CREAD) != 0)
2717 sci_start_rx(port);
2718
2719 uart_port_unlock_irqrestore(port, flags);
2720
2721 sci_port_disable(s);
2722
2723 if (UART_ENABLE_MS(port, termios->c_cflag))
2724 sci_enable_ms(port);
2725 }
2726
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2727 void sci_pm(struct uart_port *port, unsigned int state,
2728 unsigned int oldstate)
2729 {
2730 struct sci_port *sci_port = to_sci_port(port);
2731
2732 switch (state) {
2733 case UART_PM_STATE_OFF:
2734 sci_port_disable(sci_port);
2735 break;
2736 default:
2737 sci_port_enable(sci_port);
2738 break;
2739 }
2740 }
2741
sci_type(struct uart_port * port)2742 static const char *sci_type(struct uart_port *port)
2743 {
2744 switch (port->type) {
2745 case PORT_IRDA:
2746 return "irda";
2747 case PORT_SCI:
2748 return "sci";
2749 case PORT_SCIF:
2750 return "scif";
2751 case PORT_SCIFA:
2752 return "scifa";
2753 case PORT_SCIFB:
2754 return "scifb";
2755 case PORT_HSCIF:
2756 return "hscif";
2757 }
2758
2759 return NULL;
2760 }
2761
sci_remap_port(struct uart_port * port)2762 static int sci_remap_port(struct uart_port *port)
2763 {
2764 struct sci_port *sport = to_sci_port(port);
2765
2766 /*
2767 * Nothing to do if there's already an established membase.
2768 */
2769 if (port->membase)
2770 return 0;
2771
2772 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2773 port->membase = ioremap(port->mapbase, sport->reg_size);
2774 if (unlikely(!port->membase)) {
2775 dev_err(port->dev, "can't remap port#%d\n", port->line);
2776 return -ENXIO;
2777 }
2778 } else {
2779 /*
2780 * For the simple (and majority of) cases where we don't
2781 * need to do any remapping, just cast the cookie
2782 * directly.
2783 */
2784 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2785 }
2786
2787 return 0;
2788 }
2789
sci_release_port(struct uart_port * port)2790 void sci_release_port(struct uart_port *port)
2791 {
2792 struct sci_port *sport = to_sci_port(port);
2793
2794 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2795 iounmap(port->membase);
2796 port->membase = NULL;
2797 }
2798
2799 release_mem_region(port->mapbase, sport->reg_size);
2800 }
2801
sci_request_port(struct uart_port * port)2802 int sci_request_port(struct uart_port *port)
2803 {
2804 struct resource *res;
2805 struct sci_port *sport = to_sci_port(port);
2806 int ret;
2807
2808 res = request_mem_region(port->mapbase, sport->reg_size,
2809 dev_name(port->dev));
2810 if (unlikely(res == NULL)) {
2811 dev_err(port->dev, "request_mem_region failed.");
2812 return -EBUSY;
2813 }
2814
2815 ret = sci_remap_port(port);
2816 if (unlikely(ret != 0)) {
2817 release_resource(res);
2818 return ret;
2819 }
2820
2821 return 0;
2822 }
2823
sci_config_port(struct uart_port * port,int flags)2824 void sci_config_port(struct uart_port *port, int flags)
2825 {
2826 if (flags & UART_CONFIG_TYPE) {
2827 struct sci_port *sport = to_sci_port(port);
2828
2829 port->type = sport->cfg->type;
2830 sci_request_port(port);
2831 }
2832 }
2833
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2834 int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2835 {
2836 if (ser->baud_base < 2400)
2837 /* No paper tape reader for Mitch.. */
2838 return -EINVAL;
2839
2840 return 0;
2841 }
2842
sci_prepare_console_write(struct uart_port * port,u32 ctrl)2843 static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
2844 {
2845 struct sci_port *s = to_sci_port(port);
2846 u32 ctrl_temp =
2847 s->params->param_bits->rxtx_enable |
2848 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2849 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) |
2850 s->hscif_tot;
2851 sci_serial_out(port, SCSCR, ctrl_temp);
2852 }
2853
sci_console_save(struct uart_port * port)2854 static void sci_console_save(struct uart_port *port)
2855 {
2856 struct sci_port *s = to_sci_port(port);
2857 struct sci_suspend_regs *regs = s->suspend_regs;
2858
2859 if (sci_getreg(port, SCDL)->size)
2860 regs->scdl = sci_serial_in(port, SCDL);
2861 if (sci_getreg(port, SCCKS)->size)
2862 regs->sccks = sci_serial_in(port, SCCKS);
2863 if (sci_getreg(port, SCSMR)->size)
2864 regs->scsmr = sci_serial_in(port, SCSMR);
2865 if (sci_getreg(port, SCSCR)->size)
2866 regs->scscr = sci_serial_in(port, SCSCR);
2867 if (sci_getreg(port, SCFCR)->size)
2868 regs->scfcr = sci_serial_in(port, SCFCR);
2869 if (sci_getreg(port, SCSPTR)->size)
2870 regs->scsptr = sci_serial_in(port, SCSPTR);
2871 if (sci_getreg(port, SCBRR)->size)
2872 regs->scbrr = sci_serial_in(port, SCBRR);
2873 if (sci_getreg(port, HSSRR)->size)
2874 regs->hssrr = sci_serial_in(port, HSSRR);
2875 if (sci_getreg(port, SCPCR)->size)
2876 regs->scpcr = sci_serial_in(port, SCPCR);
2877 if (sci_getreg(port, SCPDR)->size)
2878 regs->scpdr = sci_serial_in(port, SCPDR);
2879 if (sci_getreg(port, SEMR)->size)
2880 regs->semr = sci_serial_in(port, SEMR);
2881 }
2882
sci_console_restore(struct uart_port * port)2883 static void sci_console_restore(struct uart_port *port)
2884 {
2885 struct sci_port *s = to_sci_port(port);
2886 struct sci_suspend_regs *regs = s->suspend_regs;
2887
2888 if (sci_getreg(port, SCDL)->size)
2889 sci_serial_out(port, SCDL, regs->scdl);
2890 if (sci_getreg(port, SCCKS)->size)
2891 sci_serial_out(port, SCCKS, regs->sccks);
2892 if (sci_getreg(port, SCSMR)->size)
2893 sci_serial_out(port, SCSMR, regs->scsmr);
2894 if (sci_getreg(port, SCSCR)->size)
2895 sci_serial_out(port, SCSCR, regs->scscr);
2896 if (sci_getreg(port, SCFCR)->size)
2897 sci_serial_out(port, SCFCR, regs->scfcr);
2898 if (sci_getreg(port, SCSPTR)->size)
2899 sci_serial_out(port, SCSPTR, regs->scsptr);
2900 if (sci_getreg(port, SCBRR)->size)
2901 sci_serial_out(port, SCBRR, regs->scbrr);
2902 if (sci_getreg(port, HSSRR)->size)
2903 sci_serial_out(port, HSSRR, regs->hssrr);
2904 if (sci_getreg(port, SCPCR)->size)
2905 sci_serial_out(port, SCPCR, regs->scpcr);
2906 if (sci_getreg(port, SCPDR)->size)
2907 sci_serial_out(port, SCPDR, regs->scpdr);
2908 if (sci_getreg(port, SEMR)->size)
2909 sci_serial_out(port, SEMR, regs->semr);
2910 }
2911
2912 static const struct uart_ops sci_uart_ops = {
2913 .tx_empty = sci_tx_empty,
2914 .set_mctrl = sci_set_mctrl,
2915 .get_mctrl = sci_get_mctrl,
2916 .start_tx = sci_start_tx,
2917 .stop_tx = sci_stop_tx,
2918 .stop_rx = sci_stop_rx,
2919 .enable_ms = sci_enable_ms,
2920 .break_ctl = sci_break_ctl,
2921 .startup = sci_startup,
2922 .shutdown = sci_shutdown,
2923 .flush_buffer = sci_flush_buffer,
2924 .set_termios = sci_set_termios,
2925 .pm = sci_pm,
2926 .type = sci_type,
2927 .release_port = sci_release_port,
2928 .request_port = sci_request_port,
2929 .config_port = sci_config_port,
2930 .verify_port = sci_verify_port,
2931 #ifdef CONFIG_CONSOLE_POLL
2932 .poll_get_char = sci_poll_get_char,
2933 .poll_put_char = sci_poll_put_char,
2934 #endif
2935 };
2936
2937 static const struct sci_port_ops sci_port_ops = {
2938 .read_reg = sci_serial_in,
2939 .write_reg = sci_serial_out,
2940 .clear_SCxSR = sci_clear_SCxSR,
2941 .transmit_chars = sci_transmit_chars,
2942 .receive_chars = sci_receive_chars,
2943 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2944 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2945 .poll_put_char = sci_poll_put_char,
2946 #endif
2947 .set_rtrg = scif_set_rtrg,
2948 .rtrg_enabled = scif_rtrg_enabled,
2949 .shutdown_complete = sci_shutdown_complete,
2950 .prepare_console_write = sci_prepare_console_write,
2951 .console_save = sci_console_save,
2952 .console_restore = sci_console_restore,
2953 .suspend_regs_size = sci_suspend_regs_size,
2954 };
2955
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2956 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2957 {
2958 const char *clk_names[] = {
2959 [SCI_FCK] = "fck",
2960 [SCI_SCK] = "sck",
2961 [SCI_BRG_INT] = "brg_int",
2962 [SCI_SCIF_CLK] = "scif_clk",
2963 };
2964 struct clk *clk;
2965 unsigned int i;
2966
2967 if (sci_port->cfg->type == PORT_HSCIF)
2968 clk_names[SCI_SCK] = "hsck";
2969
2970 for (i = 0; i < SCI_NUM_CLKS; i++) {
2971 clk = devm_clk_get_optional(dev, clk_names[i]);
2972 if (IS_ERR(clk))
2973 return PTR_ERR(clk);
2974
2975 if (!clk && i == SCI_FCK) {
2976 /*
2977 * Not all SH platforms declare a clock lookup entry
2978 * for SCI devices, in which case we need to get the
2979 * global "peripheral_clk" clock.
2980 */
2981 clk = devm_clk_get(dev, "peripheral_clk");
2982 if (IS_ERR(clk))
2983 return dev_err_probe(dev, PTR_ERR(clk),
2984 "failed to get %s\n",
2985 clk_names[i]);
2986 }
2987
2988 if (!clk)
2989 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2990 else
2991 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2992 clk, clk_get_rate(clk));
2993 sci_port->clks[i] = clk;
2994 }
2995 return 0;
2996 }
2997
2998 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg,struct sci_port * sci_port)2999 sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port)
3000 {
3001 unsigned int regtype;
3002
3003 sci_port->ops = &sci_port_ops;
3004 sci_port->port.ops = &sci_uart_ops;
3005
3006 if (cfg->regtype != SCIx_PROBE_REGTYPE)
3007 return &sci_port_params[cfg->regtype];
3008
3009 switch (cfg->type) {
3010 case PORT_SCI:
3011 regtype = SCIx_SCI_REGTYPE;
3012 break;
3013 case PORT_IRDA:
3014 regtype = SCIx_IRDA_REGTYPE;
3015 break;
3016 case PORT_SCIFA:
3017 regtype = SCIx_SCIFA_REGTYPE;
3018 break;
3019 case PORT_SCIFB:
3020 regtype = SCIx_SCIFB_REGTYPE;
3021 break;
3022 case PORT_SCIF:
3023 /*
3024 * The SH-4 is a bit of a misnomer here, although that's
3025 * where this particular port layout originated. This
3026 * configuration (or some slight variation thereof)
3027 * remains the dominant model for all SCIFs.
3028 */
3029 regtype = SCIx_SH4_SCIF_REGTYPE;
3030 break;
3031 case PORT_HSCIF:
3032 regtype = SCIx_HSCIF_REGTYPE;
3033 break;
3034 default:
3035 pr_err("Can't probe register map for given port\n");
3036 return NULL;
3037 }
3038
3039 return &sci_port_params[regtype];
3040 }
3041
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)3042 static int sci_init_single(struct platform_device *dev,
3043 struct sci_port *sci_port, unsigned int index,
3044 const struct plat_sci_port *p, bool early)
3045 {
3046 struct uart_port *port = &sci_port->port;
3047 const struct resource *res;
3048 unsigned int i;
3049 int ret;
3050
3051 sci_port->cfg = p;
3052
3053 port->iotype = UPIO_MEM;
3054 port->line = index;
3055 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
3056
3057 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3058 if (res == NULL)
3059 return -ENOMEM;
3060
3061 port->mapbase = res->start;
3062 sci_port->reg_size = resource_size(res);
3063
3064 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
3065 if (i)
3066 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
3067 else
3068 sci_port->irqs[i] = platform_get_irq(dev, i);
3069 }
3070
3071 /*
3072 * The fourth interrupt on SCI port is transmit end interrupt, so
3073 * shuffle the interrupts.
3074 */
3075 if (p->type == PORT_SCI)
3076 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3077
3078 /* The SCI generates several interrupts. They can be muxed together or
3079 * connected to different interrupt lines. In the muxed case only one
3080 * interrupt resource is specified as there is only one interrupt ID.
3081 * In the non-muxed case, up to 6 interrupt signals might be generated
3082 * from the SCI, however those signals might have their own individual
3083 * interrupt ID numbers, or muxed together with another interrupt.
3084 */
3085 if (sci_port->irqs[0] < 0)
3086 return -ENXIO;
3087
3088 if (sci_port->irqs[1] < 0)
3089 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3090 sci_port->irqs[i] = sci_port->irqs[0];
3091
3092 switch (p->type) {
3093 case PORT_SCIFB:
3094 sci_port->rx_trigger = 48;
3095 break;
3096 case PORT_HSCIF:
3097 sci_port->rx_trigger = 64;
3098 break;
3099 case PORT_SCIFA:
3100 sci_port->rx_trigger = 32;
3101 break;
3102 case PORT_SCIF:
3103 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3104 /* RX triggering not implemented for this IP */
3105 sci_port->rx_trigger = 1;
3106 else
3107 sci_port->rx_trigger = 8;
3108 break;
3109 default:
3110 sci_port->rx_trigger = 1;
3111 break;
3112 }
3113
3114 sci_port->rx_fifo_timeout = 0;
3115 sci_port->hscif_tot = 0;
3116
3117 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3118 * match the SoC datasheet, this should be investigated. Let platform
3119 * data override the sampling rate for now.
3120 */
3121 sci_port->sampling_rate_mask = p->sampling_rate
3122 ? SCI_SR(p->sampling_rate)
3123 : sci_port->params->sampling_rate_mask;
3124
3125 if (!early) {
3126 ret = sci_init_clocks(sci_port, &dev->dev);
3127 if (ret < 0)
3128 return ret;
3129 }
3130
3131 port->type = p->type;
3132 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3133 port->fifosize = sci_port->params->fifosize;
3134
3135 if (port->type == PORT_SCI && !dev->dev.of_node) {
3136 if (sci_port->reg_size >= 0x20)
3137 port->regshift = 2;
3138 else
3139 port->regshift = 1;
3140 }
3141
3142 /*
3143 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3144 * for the multi-IRQ ports, which is where we are primarily
3145 * concerned with the shutdown path synchronization.
3146 *
3147 * For the muxed case there's nothing more to do.
3148 */
3149 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3150 port->irqflags = 0;
3151
3152 return 0;
3153 }
3154
3155 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3156 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)3157 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3158 {
3159 to_sci_port(port)->ops->poll_put_char(port, ch);
3160 }
3161
3162 /*
3163 * Print a string to the serial port trying not to disturb
3164 * any possible real use of the port...
3165 */
serial_console_write(struct console * co,const char * s,unsigned count)3166 static void serial_console_write(struct console *co, const char *s,
3167 unsigned count)
3168 {
3169 struct sci_port *sci_port = &sci_ports[co->index];
3170 struct uart_port *port = &sci_port->port;
3171 const struct sci_common_regs *regs = sci_port->params->common_regs;
3172 unsigned int bits;
3173 u32 ctrl;
3174 unsigned long flags;
3175 int locked = 1;
3176
3177 if (port->sysrq)
3178 locked = 0;
3179 else if (oops_in_progress)
3180 locked = uart_port_trylock_irqsave(port, &flags);
3181 else
3182 uart_port_lock_irqsave(port, &flags);
3183
3184 /* first save SCSCR then disable interrupts, keep clock source */
3185
3186 ctrl = sci_port->ops->read_reg(port, regs->control);
3187 sci_port->ops->prepare_console_write(port, ctrl);
3188
3189 uart_console_write(port, s, count, serial_console_putchar);
3190
3191 /* wait until fifo is empty and last bit has been transmitted */
3192
3193 bits = sci_port->params->param_bits->poll_sent_bits;
3194
3195 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
3196 cpu_relax();
3197
3198 /* restore the SCSCR */
3199 sci_port->ops->write_reg(port, regs->control, ctrl);
3200
3201 if (locked)
3202 uart_port_unlock_irqrestore(port, flags);
3203 }
3204
serial_console_setup(struct console * co,char * options)3205 static int serial_console_setup(struct console *co, char *options)
3206 {
3207 struct sci_port *sci_port;
3208 struct uart_port *port;
3209 int baud = 115200;
3210 int bits = 8;
3211 int parity = 'n';
3212 int flow = 'n';
3213 int ret;
3214
3215 /*
3216 * Refuse to handle any bogus ports.
3217 */
3218 if (co->index < 0 || co->index >= SCI_NPORTS)
3219 return -ENODEV;
3220
3221 sci_port = &sci_ports[co->index];
3222 port = &sci_port->port;
3223
3224 /*
3225 * Refuse to handle uninitialized ports.
3226 */
3227 if (!port->ops)
3228 return -ENODEV;
3229
3230 ret = sci_remap_port(port);
3231 if (unlikely(ret != 0))
3232 return ret;
3233
3234 if (options)
3235 uart_parse_options(options, &baud, &parity, &bits, &flow);
3236
3237 return uart_set_options(port, co, baud, parity, bits, flow);
3238 }
3239
3240 static struct console serial_console = {
3241 .name = "ttySC",
3242 .device = uart_console_device,
3243 .write = serial_console_write,
3244 .setup = serial_console_setup,
3245 .flags = CON_PRINTBUFFER,
3246 .index = -1,
3247 .data = &sci_uart_driver,
3248 };
3249
3250 #ifdef CONFIG_SUPERH
3251 static char early_serial_buf[32];
3252
early_serial_console_setup(struct console * co,char * options)3253 static int early_serial_console_setup(struct console *co, char *options)
3254 {
3255 /*
3256 * This early console is always registered using the earlyprintk=
3257 * parameter, which does not call add_preferred_console(). Thus
3258 * @options is always NULL and the options for this early console
3259 * are passed using a custom buffer.
3260 */
3261 WARN_ON(options);
3262
3263 return serial_console_setup(co, early_serial_buf);
3264 }
3265
3266 static struct console early_serial_console = {
3267 .name = "early_ttySC",
3268 .write = serial_console_write,
3269 .setup = early_serial_console_setup,
3270 .flags = CON_PRINTBUFFER,
3271 .index = -1,
3272 };
3273
sci_probe_earlyprintk(struct platform_device * pdev)3274 static int sci_probe_earlyprintk(struct platform_device *pdev)
3275 {
3276 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3277 struct sci_port *sp = &sci_ports[pdev->id];
3278
3279 if (early_serial_console.data)
3280 return -EEXIST;
3281
3282 early_serial_console.index = pdev->id;
3283
3284 sp->params = sci_probe_regmap(cfg, sp);
3285 if (!sp->params)
3286 return -ENODEV;
3287
3288 sci_init_single(pdev, sp, pdev->id, cfg, true);
3289
3290 if (!strstr(early_serial_buf, "keep"))
3291 early_serial_console.flags |= CON_BOOT;
3292
3293 register_console(&early_serial_console);
3294 return 0;
3295 }
3296 #endif
3297
3298 #define SCI_CONSOLE (&serial_console)
3299
3300 #else
sci_probe_earlyprintk(struct platform_device * pdev)3301 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3302 {
3303 return -EINVAL;
3304 }
3305
3306 #define SCI_CONSOLE NULL
3307
3308 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3309
3310 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3311
3312 static DEFINE_MUTEX(sci_uart_registration_lock);
3313 static struct uart_driver sci_uart_driver = {
3314 .owner = THIS_MODULE,
3315 .driver_name = "sci",
3316 .dev_name = "ttySC",
3317 .major = SCI_MAJOR,
3318 .minor = SCI_MINOR_START,
3319 .nr = SCI_NPORTS,
3320 .cons = SCI_CONSOLE,
3321 };
3322
sci_remove(struct platform_device * dev)3323 static void sci_remove(struct platform_device *dev)
3324 {
3325 struct sci_port *port = platform_get_drvdata(dev);
3326 unsigned int type = port->port.type; /* uart_remove_... clears it */
3327
3328 sci_ports_in_use &= ~BIT(port->port.line);
3329 uart_remove_one_port(&sci_uart_driver, &port->port);
3330
3331 if (port->port.fifosize > 1)
3332 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3333 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3334 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3335 }
3336
3337 static const struct sci_of_data of_sci_scif_sh2 = {
3338 .type = PORT_SCIF,
3339 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
3340 .ops = &sci_port_ops,
3341 .uart_ops = &sci_uart_ops,
3342 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE],
3343 };
3344
3345 static const struct sci_of_data of_sci_scif_rz_scifa = {
3346 .type = PORT_SCIF,
3347 .regtype = SCIx_RZ_SCIFA_REGTYPE,
3348 .ops = &sci_port_ops,
3349 .uart_ops = &sci_uart_ops,
3350 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE],
3351 };
3352
3353 static const struct sci_of_data of_sci_scif_rzv2h = {
3354 .type = PORT_SCIF,
3355 .regtype = SCIx_RZV2H_SCIF_REGTYPE,
3356 .ops = &sci_port_ops,
3357 .uart_ops = &sci_uart_ops,
3358 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE],
3359 };
3360
3361 static const struct sci_of_data of_sci_rcar_scif = {
3362 .type = PORT_SCIF,
3363 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
3364 .ops = &sci_port_ops,
3365 .uart_ops = &sci_uart_ops,
3366 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE],
3367 };
3368
3369 static const struct sci_of_data of_sci_scif_sh4 = {
3370 .type = PORT_SCIF,
3371 .regtype = SCIx_SH4_SCIF_REGTYPE,
3372 .ops = &sci_port_ops,
3373 .uart_ops = &sci_uart_ops,
3374 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE],
3375 };
3376
3377 static const struct sci_of_data of_sci_scifa = {
3378 .type = PORT_SCIFA,
3379 .regtype = SCIx_SCIFA_REGTYPE,
3380 .ops = &sci_port_ops,
3381 .uart_ops = &sci_uart_ops,
3382 .params = &sci_port_params[SCIx_SCIFA_REGTYPE],
3383 };
3384
3385 static const struct sci_of_data of_sci_scifb = {
3386 .type = PORT_SCIFB,
3387 .regtype = SCIx_SCIFB_REGTYPE,
3388 .ops = &sci_port_ops,
3389 .uart_ops = &sci_uart_ops,
3390 .params = &sci_port_params[SCIx_SCIFB_REGTYPE],
3391 };
3392
3393 static const struct sci_of_data of_sci_hscif = {
3394 .type = PORT_HSCIF,
3395 .regtype = SCIx_HSCIF_REGTYPE,
3396 .ops = &sci_port_ops,
3397 .uart_ops = &sci_uart_ops,
3398 .params = &sci_port_params[SCIx_HSCIF_REGTYPE],
3399 };
3400
3401 static const struct sci_of_data of_sci_sci = {
3402 .type = PORT_SCI,
3403 .regtype = SCIx_SCI_REGTYPE,
3404 .ops = &sci_port_ops,
3405 .uart_ops = &sci_uart_ops,
3406 .params = &sci_port_params[SCIx_SCI_REGTYPE],
3407 };
3408
3409 static const struct of_device_id of_sci_match[] __maybe_unused = {
3410 /* SoC-specific types */
3411 {
3412 .compatible = "renesas,scif-r7s72100",
3413 .data = &of_sci_scif_sh2,
3414 },
3415 {
3416 .compatible = "renesas,scif-r7s9210",
3417 .data = &of_sci_scif_rz_scifa,
3418 },
3419 {
3420 .compatible = "renesas,scif-r9a07g044",
3421 .data = &of_sci_scif_rz_scifa,
3422 },
3423 {
3424 .compatible = "renesas,scif-r9a09g057",
3425 .data = &of_sci_scif_rzv2h,
3426 },
3427 /* Family-specific types */
3428 {
3429 .compatible = "renesas,rcar-gen1-scif",
3430 .data = &of_sci_rcar_scif,
3431 }, {
3432 .compatible = "renesas,rcar-gen2-scif",
3433 .data = &of_sci_rcar_scif,
3434 }, {
3435 .compatible = "renesas,rcar-gen3-scif",
3436 .data = &of_sci_rcar_scif
3437 }, {
3438 .compatible = "renesas,rcar-gen4-scif",
3439 .data = &of_sci_rcar_scif
3440 },
3441 /* Generic types */
3442 {
3443 .compatible = "renesas,scif",
3444 .data = &of_sci_scif_sh4,
3445 }, {
3446 .compatible = "renesas,scifa",
3447 .data = &of_sci_scifa,
3448 }, {
3449 .compatible = "renesas,scifb",
3450 .data = &of_sci_scifb,
3451 }, {
3452 .compatible = "renesas,hscif",
3453 .data = &of_sci_hscif,
3454 }, {
3455 .compatible = "renesas,sci",
3456 .data = &of_sci_sci,
3457 }, {
3458 /* Terminator */
3459 },
3460 };
3461 MODULE_DEVICE_TABLE(of, of_sci_match);
3462
sci_reset_control_assert(void * data)3463 static void sci_reset_control_assert(void *data)
3464 {
3465 reset_control_assert(data);
3466 }
3467
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3468 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3469 unsigned int *dev_id)
3470 {
3471 struct device_node *np = pdev->dev.of_node;
3472 struct reset_control *rstc;
3473 struct plat_sci_port *p;
3474 struct sci_port *sp;
3475 const struct sci_of_data *data;
3476 int id, ret;
3477
3478 if (!IS_ENABLED(CONFIG_OF) || !np)
3479 return ERR_PTR(-EINVAL);
3480
3481 data = of_device_get_match_data(&pdev->dev);
3482
3483 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3484 if (IS_ERR(rstc))
3485 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3486 "failed to get reset ctrl\n"));
3487
3488 ret = reset_control_deassert(rstc);
3489 if (ret) {
3490 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3491 return ERR_PTR(ret);
3492 }
3493
3494 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3495 if (ret) {
3496 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3497 ret);
3498 return ERR_PTR(ret);
3499 }
3500
3501 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3502 if (!p)
3503 return ERR_PTR(-ENOMEM);
3504
3505 /* Get the line number from the aliases node. */
3506 id = of_alias_get_id(np, "serial");
3507 if (id < 0 && ~sci_ports_in_use)
3508 id = ffz(sci_ports_in_use);
3509 if (id < 0) {
3510 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3511 return ERR_PTR(-EINVAL);
3512 }
3513 if (id >= ARRAY_SIZE(sci_ports)) {
3514 dev_err(&pdev->dev, "serial%d out of range\n", id);
3515 return ERR_PTR(-EINVAL);
3516 }
3517
3518 sp = &sci_ports[id];
3519 sp->rstc = rstc;
3520 *dev_id = id;
3521
3522 p->type = data->type;
3523 p->regtype = data->regtype;
3524
3525 sp->ops = data->ops;
3526 sp->port.ops = data->uart_ops;
3527 sp->params = data->params;
3528
3529 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3530
3531 return p;
3532 }
3533
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport,struct resource * sci_res)3534 static int sci_probe_single(struct platform_device *dev,
3535 unsigned int index,
3536 struct plat_sci_port *p,
3537 struct sci_port *sciport,
3538 struct resource *sci_res)
3539 {
3540 int ret;
3541
3542 /* Sanity check */
3543 if (unlikely(index >= SCI_NPORTS)) {
3544 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3545 index+1, SCI_NPORTS);
3546 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3547 return -EINVAL;
3548 }
3549 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3550 if (sci_ports_in_use & BIT(index))
3551 return -EBUSY;
3552
3553 mutex_lock(&sci_uart_registration_lock);
3554 if (!sci_uart_driver.state) {
3555 ret = uart_register_driver(&sci_uart_driver);
3556 if (ret) {
3557 mutex_unlock(&sci_uart_registration_lock);
3558 return ret;
3559 }
3560 }
3561 mutex_unlock(&sci_uart_registration_lock);
3562
3563 ret = sci_init_single(dev, sciport, index, p, false);
3564 if (ret)
3565 return ret;
3566
3567 sciport->port.dev = &dev->dev;
3568 ret = devm_pm_runtime_enable(&dev->dev);
3569 if (ret)
3570 return ret;
3571
3572 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3573 if (IS_ERR(sciport->gpios))
3574 return PTR_ERR(sciport->gpios);
3575
3576 if (sciport->has_rtscts) {
3577 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3578 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3579 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3580 return -EINVAL;
3581 }
3582 sciport->port.flags |= UPF_HARD_FLOW;
3583 }
3584
3585 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3586 /*
3587 * In case:
3588 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3589 * - it now maps to an alias other than zero and
3590 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3591 * available in bootargs)
3592 *
3593 * we need to avoid disabling clocks and PM domains through the runtime
3594 * PM APIs called in __device_attach(). For this, increment the runtime
3595 * PM reference counter (the clocks and PM domains were already enabled
3596 * by the bootloader). Otherwise the earlycon may access the HW when it
3597 * has no clocks enabled leading to failures (infinite loop in
3598 * sci_poll_put_char()).
3599 */
3600 pm_runtime_get_noresume(&dev->dev);
3601
3602 /*
3603 * Skip cleanup the sci_port[0] in early_console_exit(), this
3604 * port is the same as the earlycon one.
3605 */
3606 sci_uart_earlycon_dev_probing = true;
3607 }
3608
3609 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3610 }
3611
sci_probe(struct platform_device * dev)3612 static int sci_probe(struct platform_device *dev)
3613 {
3614 struct plat_sci_port *p;
3615 struct resource *res;
3616 struct sci_port *sp;
3617 unsigned int dev_id;
3618 int ret;
3619
3620 /*
3621 * If we've come here via earlyprintk initialization, head off to
3622 * the special early probe. We don't have sufficient device state
3623 * to make it beyond this yet.
3624 */
3625 #ifdef CONFIG_SUPERH
3626 if (is_sh_early_platform_device(dev))
3627 return sci_probe_earlyprintk(dev);
3628 #endif
3629
3630 if (dev->dev.of_node) {
3631 p = sci_parse_dt(dev, &dev_id);
3632 if (IS_ERR(p))
3633 return PTR_ERR(p);
3634 sp = &sci_ports[dev_id];
3635 } else {
3636 p = dev->dev.platform_data;
3637 if (p == NULL) {
3638 dev_err(&dev->dev, "no platform data supplied\n");
3639 return -EINVAL;
3640 }
3641
3642 dev_id = dev->id;
3643 sp = &sci_ports[dev_id];
3644 sp->params = sci_probe_regmap(p, sp);
3645 if (!sp->params)
3646 return -ENODEV;
3647 }
3648
3649 sp->suspend_regs = devm_kzalloc(&dev->dev,
3650 sp->ops->suspend_regs_size(),
3651 GFP_KERNEL);
3652 if (!sp->suspend_regs)
3653 return -ENOMEM;
3654
3655 /*
3656 * In case:
3657 * - the probed port alias is zero (as the one used by earlycon), and
3658 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3659 * bootargs)
3660 *
3661 * defer the probe of this serial. This is a debug scenario and the user
3662 * must be aware of it.
3663 *
3664 * Except when the probed port is the same as the earlycon port.
3665 */
3666
3667 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3668 if (!res)
3669 return -ENODEV;
3670
3671 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3672 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3673
3674 platform_set_drvdata(dev, sp);
3675
3676 ret = sci_probe_single(dev, dev_id, p, sp, res);
3677 if (ret)
3678 return ret;
3679
3680 if (sp->port.fifosize > 1) {
3681 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3682 if (ret)
3683 return ret;
3684 }
3685 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3686 sp->port.type == PORT_HSCIF) {
3687 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3688 if (ret) {
3689 if (sp->port.fifosize > 1) {
3690 device_remove_file(&dev->dev,
3691 &dev_attr_rx_fifo_trigger);
3692 }
3693 return ret;
3694 }
3695 }
3696
3697 #ifdef CONFIG_SH_STANDARD_BIOS
3698 sh_bios_gdb_detach();
3699 #endif
3700
3701 sci_ports_in_use |= BIT(dev_id);
3702 return 0;
3703 }
3704
sci_suspend(struct device * dev)3705 static __maybe_unused int sci_suspend(struct device *dev)
3706 {
3707 struct sci_port *sport = dev_get_drvdata(dev);
3708
3709 if (sport) {
3710 uart_suspend_port(&sci_uart_driver, &sport->port);
3711
3712 if (!console_suspend_enabled && uart_console(&sport->port)) {
3713 if (sport->ops->console_save)
3714 sport->ops->console_save(&sport->port);
3715 }
3716 else
3717 return reset_control_assert(sport->rstc);
3718 }
3719
3720 return 0;
3721 }
3722
sci_resume(struct device * dev)3723 static __maybe_unused int sci_resume(struct device *dev)
3724 {
3725 struct sci_port *sport = dev_get_drvdata(dev);
3726
3727 if (sport) {
3728 if (!console_suspend_enabled && uart_console(&sport->port)) {
3729 if (sport->ops->console_restore)
3730 sport->ops->console_restore(&sport->port);
3731 } else {
3732 int ret = reset_control_deassert(sport->rstc);
3733
3734 if (ret)
3735 return ret;
3736 }
3737
3738 uart_resume_port(&sci_uart_driver, &sport->port);
3739 }
3740
3741 return 0;
3742 }
3743
3744 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3745
3746 static struct platform_driver sci_driver = {
3747 .probe = sci_probe,
3748 .remove = sci_remove,
3749 .driver = {
3750 .name = "sh-sci",
3751 .pm = &sci_dev_pm_ops,
3752 .of_match_table = of_match_ptr(of_sci_match),
3753 },
3754 };
3755
sci_init(void)3756 static int __init sci_init(void)
3757 {
3758 pr_info("%s\n", banner);
3759
3760 return platform_driver_register(&sci_driver);
3761 }
3762
sci_exit(void)3763 static void __exit sci_exit(void)
3764 {
3765 platform_driver_unregister(&sci_driver);
3766
3767 if (sci_uart_driver.state)
3768 uart_unregister_driver(&sci_uart_driver);
3769 }
3770
3771 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3772 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3773 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3774 #endif
3775 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3776 static struct plat_sci_port port_cfg;
3777
early_console_exit(struct console * co)3778 static int early_console_exit(struct console *co)
3779 {
3780 struct sci_port *sci_port = &sci_ports[0];
3781
3782 /*
3783 * Clean the slot used by earlycon. A new SCI device might
3784 * map to this slot.
3785 */
3786 if (!sci_uart_earlycon_dev_probing) {
3787 memset(sci_port, 0, sizeof(*sci_port));
3788 sci_uart_earlycon = false;
3789 }
3790
3791 return 0;
3792 }
3793
scix_early_console_setup(struct earlycon_device * device,const struct sci_of_data * data)3794 int __init scix_early_console_setup(struct earlycon_device *device,
3795 const struct sci_of_data *data)
3796 {
3797 const struct sci_common_regs *regs;
3798
3799 if (!device->port.membase)
3800 return -ENODEV;
3801
3802 device->port.type = data->type;
3803 sci_ports[0].port = device->port;
3804
3805 port_cfg.type = data->type;
3806 port_cfg.regtype = data->regtype;
3807
3808 sci_ports[0].cfg = &port_cfg;
3809 sci_ports[0].params = data->params;
3810 sci_ports[0].ops = data->ops;
3811 sci_ports[0].port.ops = data->uart_ops;
3812 sci_uart_earlycon = true;
3813 regs = sci_ports[0].params->common_regs;
3814
3815 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
3816 sci_ports[0].ops->write_reg(&sci_ports[0].port,
3817 regs->control,
3818 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);
3819
3820 device->con->write = serial_console_write;
3821 device->con->exit = early_console_exit;
3822
3823 return 0;
3824 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3825 static int __init sci_early_console_setup(struct earlycon_device *device,
3826 const char *opt)
3827 {
3828 return scix_early_console_setup(device, &of_sci_sci);
3829 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3830 static int __init scif_early_console_setup(struct earlycon_device *device,
3831 const char *opt)
3832 {
3833 return scix_early_console_setup(device, &of_sci_scif_sh4);
3834 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3835 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3836 const char *opt)
3837 {
3838 return scix_early_console_setup(device, &of_sci_scif_rz_scifa);
3839 }
3840
rzv2hscif_early_console_setup(struct earlycon_device * device,const char * opt)3841 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3842 const char *opt)
3843 {
3844 return scix_early_console_setup(device, &of_sci_scif_rzv2h);
3845 }
3846
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3847 static int __init scifa_early_console_setup(struct earlycon_device *device,
3848 const char *opt)
3849 {
3850 return scix_early_console_setup(device, &of_sci_scifa);
3851 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3852 static int __init scifb_early_console_setup(struct earlycon_device *device,
3853 const char *opt)
3854 {
3855 return scix_early_console_setup(device, &of_sci_scifb);
3856 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3857 static int __init hscif_early_console_setup(struct earlycon_device *device,
3858 const char *opt)
3859 {
3860 return scix_early_console_setup(device, &of_sci_hscif);
3861 }
3862
3863 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3864 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3865 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3866 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3867 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3868 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3869 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3870 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3871 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3872
3873 module_init(sci_init);
3874 module_exit(sci_exit);
3875
3876 MODULE_LICENSE("GPL");
3877 MODULE_ALIAS("platform:sh-sci");
3878 MODULE_AUTHOR("Paul Mundt");
3879 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3880