1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ST SPEAr ADC driver 4 * 5 * Copyright 2012 Stefan Roese <sr@denx.de> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/dev_printk.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/math.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/platform_device.h> 22 #include <linux/property.h> 23 #include <linux/types.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/types.h> 27 28 /* SPEAR registers definitions */ 29 #define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF) 30 #define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF) 31 #define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0) 32 #define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4) 33 34 /* Bit definitions for SPEAR_ADC_STATUS */ 35 #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0) 36 #define SPEAR_ADC_STATUS_CHANNEL_NUM_MASK GENMASK(3, 1) 37 #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4) 38 #define SPEAR_ADC_STATUS_AVG_SAMPLE_MASK GENMASK(8, 5) 39 #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9) 40 41 #define SPEAR_ADC_DATA_MASK 0x03ff 42 #define SPEAR_ADC_DATA_BITS 10 43 44 #define SPEAR_ADC_MOD_NAME "spear-adc" 45 46 #define SPEAR_ADC_CHANNEL_NUM 8 47 48 #define SPEAR_ADC_CLK_MIN 2500000 49 #define SPEAR_ADC_CLK_MAX 20000000 50 51 struct adc_regs_spear3xx { 52 u32 status; 53 u32 average; 54 u32 scan_rate; 55 u32 clk; /* Not avail for 1340 & 1310 */ 56 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM]; 57 u32 ch_data[SPEAR_ADC_CHANNEL_NUM]; 58 }; 59 60 struct chan_data { 61 u32 lsb; 62 u32 msb; 63 }; 64 65 struct adc_regs_spear6xx { 66 u32 status; 67 u32 pad[2]; 68 u32 clk; 69 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM]; 70 struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM]; 71 u32 scan_rate_lo; 72 u32 scan_rate_hi; 73 struct chan_data average; 74 }; 75 76 struct spear_adc_state { 77 struct device *dev; 78 struct adc_regs_spear3xx __iomem *adc_base_spear3xx; 79 struct adc_regs_spear6xx __iomem *adc_base_spear6xx; 80 struct clk *clk; 81 struct completion completion; 82 /* 83 * Lock to protect the device state during a potential concurrent 84 * read access from userspace. Reading a raw value requires a sequence 85 * of register writes, then a wait for a completion callback, 86 * and finally a register read, during which userspace could issue 87 * another read request. This lock protects a read access from 88 * occurring before another one has finished. 89 */ 90 struct mutex lock; 91 u32 current_clk; 92 u32 sampling_freq; 93 u32 avg_samples; 94 u32 vref_external; 95 u32 value; 96 }; 97 98 /* 99 * Functions to access some SPEAr ADC register. Abstracted into 100 * static inline functions, because of different register offsets 101 * on different SoC variants (SPEAr300 vs SPEAr600 etc). 102 */ 103 static void spear_adc_set_status(struct spear_adc_state *st, u32 val) 104 { 105 __raw_writel(val, &st->adc_base_spear6xx->status); 106 } 107 108 static void spear_adc_set_clk(struct spear_adc_state *st, u32 val) 109 { 110 u32 clk_high, clk_low, count; 111 u32 apb_clk = clk_get_rate(st->clk); 112 113 count = DIV_ROUND_UP(apb_clk, val); 114 clk_low = count / 2; 115 clk_high = count - clk_low; 116 st->current_clk = apb_clk / count; 117 118 __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high), 119 &st->adc_base_spear6xx->clk); 120 } 121 122 static void spear_adc_set_ctrl(struct spear_adc_state *st, int n, 123 u32 val) 124 { 125 __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]); 126 } 127 128 static u32 spear_adc_get_average(struct spear_adc_state *st) 129 { 130 if (device_is_compatible(st->dev, "st,spear600-adc")) { 131 return __raw_readl(&st->adc_base_spear6xx->average.msb) & 132 SPEAR_ADC_DATA_MASK; 133 } else { 134 return __raw_readl(&st->adc_base_spear3xx->average) & 135 SPEAR_ADC_DATA_MASK; 136 } 137 } 138 139 static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate) 140 { 141 if (device_is_compatible(st->dev, "st,spear600-adc")) { 142 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate), 143 &st->adc_base_spear6xx->scan_rate_lo); 144 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate), 145 &st->adc_base_spear6xx->scan_rate_hi); 146 } else { 147 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate); 148 } 149 } 150 151 static int spear_adc_read_raw(struct iio_dev *indio_dev, 152 struct iio_chan_spec const *chan, 153 int *val, 154 int *val2, 155 long mask) 156 { 157 struct spear_adc_state *st = iio_priv(indio_dev); 158 u32 status; 159 160 switch (mask) { 161 case IIO_CHAN_INFO_RAW: 162 mutex_lock(&st->lock); 163 164 status = FIELD_PREP(SPEAR_ADC_STATUS_CHANNEL_NUM_MASK, chan->channel) | 165 FIELD_PREP(SPEAR_ADC_STATUS_AVG_SAMPLE_MASK, st->avg_samples) | 166 SPEAR_ADC_STATUS_START_CONVERSION | 167 SPEAR_ADC_STATUS_ADC_ENABLE; 168 if (st->vref_external == 0) 169 status |= SPEAR_ADC_STATUS_VREF_INTERNAL; 170 171 spear_adc_set_status(st, status); 172 wait_for_completion(&st->completion); /* set by ISR */ 173 *val = st->value; 174 175 mutex_unlock(&st->lock); 176 177 return IIO_VAL_INT; 178 179 case IIO_CHAN_INFO_SCALE: 180 *val = st->vref_external; 181 *val2 = SPEAR_ADC_DATA_BITS; 182 return IIO_VAL_FRACTIONAL_LOG2; 183 case IIO_CHAN_INFO_SAMP_FREQ: 184 *val = st->current_clk; 185 return IIO_VAL_INT; 186 } 187 188 return -EINVAL; 189 } 190 191 static int spear_adc_write_raw(struct iio_dev *indio_dev, 192 struct iio_chan_spec const *chan, 193 int val, 194 int val2, 195 long mask) 196 { 197 struct spear_adc_state *st = iio_priv(indio_dev); 198 int ret = 0; 199 200 if (mask != IIO_CHAN_INFO_SAMP_FREQ) 201 return -EINVAL; 202 203 mutex_lock(&st->lock); 204 205 if ((val < SPEAR_ADC_CLK_MIN) || 206 (val > SPEAR_ADC_CLK_MAX) || 207 (val2 != 0)) { 208 ret = -EINVAL; 209 goto out; 210 } 211 212 spear_adc_set_clk(st, val); 213 214 out: 215 mutex_unlock(&st->lock); 216 return ret; 217 } 218 219 #define SPEAR_ADC_CHAN(idx) { \ 220 .type = IIO_VOLTAGE, \ 221 .indexed = 1, \ 222 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 223 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 224 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 225 .channel = idx, \ 226 } 227 228 static const struct iio_chan_spec spear_adc_iio_channels[] = { 229 SPEAR_ADC_CHAN(0), 230 SPEAR_ADC_CHAN(1), 231 SPEAR_ADC_CHAN(2), 232 SPEAR_ADC_CHAN(3), 233 SPEAR_ADC_CHAN(4), 234 SPEAR_ADC_CHAN(5), 235 SPEAR_ADC_CHAN(6), 236 SPEAR_ADC_CHAN(7), 237 }; 238 239 static irqreturn_t spear_adc_isr(int irq, void *dev_id) 240 { 241 struct spear_adc_state *st = dev_id; 242 243 /* Read value to clear IRQ */ 244 st->value = spear_adc_get_average(st); 245 complete(&st->completion); 246 247 return IRQ_HANDLED; 248 } 249 250 static int spear_adc_configure(struct spear_adc_state *st) 251 { 252 int i; 253 254 /* Reset ADC core */ 255 spear_adc_set_status(st, 0); 256 __raw_writel(0, &st->adc_base_spear6xx->clk); 257 for (i = 0; i < 8; i++) 258 spear_adc_set_ctrl(st, i, 0); 259 spear_adc_set_scanrate(st, 0); 260 261 spear_adc_set_clk(st, st->sampling_freq); 262 263 return 0; 264 } 265 266 static const struct iio_info spear_adc_info = { 267 .read_raw = &spear_adc_read_raw, 268 .write_raw = &spear_adc_write_raw, 269 }; 270 271 static int spear_adc_probe(struct platform_device *pdev) 272 { 273 struct device *dev = &pdev->dev; 274 struct spear_adc_state *st; 275 struct iio_dev *indio_dev = NULL; 276 int ret = -ENODEV; 277 int irq; 278 279 indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state)); 280 if (!indio_dev) 281 return -ENOMEM; 282 283 st = iio_priv(indio_dev); 284 st->dev = dev; 285 286 mutex_init(&st->lock); 287 288 /* 289 * SPEAr600 has a different register layout than other SPEAr SoC's 290 * (e.g. SPEAr3xx). Let's provide two register base addresses 291 * to support multi-arch kernels. 292 */ 293 st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0); 294 if (IS_ERR(st->adc_base_spear6xx)) 295 return PTR_ERR(st->adc_base_spear6xx); 296 297 st->adc_base_spear3xx = 298 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx; 299 300 st->clk = devm_clk_get_enabled(dev, NULL); 301 if (IS_ERR(st->clk)) 302 return dev_err_probe(dev, PTR_ERR(st->clk), 303 "failed enabling clock\n"); 304 305 irq = platform_get_irq(pdev, 0); 306 if (irq < 0) 307 return irq; 308 309 ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME, 310 st); 311 if (ret < 0) 312 return dev_err_probe(dev, ret, "failed requesting interrupt\n"); 313 314 if (device_property_read_u32(dev, "sampling-frequency", &st->sampling_freq)) 315 return dev_err_probe(dev, -EINVAL, 316 "sampling-frequency missing in DT\n"); 317 318 /* 319 * Optional avg_samples defaults to 0, resulting in single data 320 * conversion 321 */ 322 device_property_read_u32(dev, "average-samples", &st->avg_samples); 323 324 /* 325 * Optional vref_external defaults to 0, resulting in internal vref 326 * selection 327 */ 328 device_property_read_u32(dev, "vref-external", &st->vref_external); 329 330 spear_adc_configure(st); 331 332 init_completion(&st->completion); 333 334 indio_dev->name = SPEAR_ADC_MOD_NAME; 335 indio_dev->info = &spear_adc_info; 336 indio_dev->modes = INDIO_DIRECT_MODE; 337 indio_dev->channels = spear_adc_iio_channels; 338 indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels); 339 340 ret = devm_iio_device_register(dev, indio_dev); 341 if (ret) 342 return ret; 343 344 dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq); 345 346 return 0; 347 } 348 349 static const struct of_device_id spear_adc_dt_ids[] = { 350 { .compatible = "st,spear600-adc", }, 351 { } 352 }; 353 MODULE_DEVICE_TABLE(of, spear_adc_dt_ids); 354 355 static struct platform_driver spear_adc_driver = { 356 .probe = spear_adc_probe, 357 .driver = { 358 .name = SPEAR_ADC_MOD_NAME, 359 .of_match_table = spear_adc_dt_ids, 360 }, 361 }; 362 363 module_platform_driver(spear_adc_driver); 364 365 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 366 MODULE_DESCRIPTION("SPEAr ADC driver"); 367 MODULE_LICENSE("GPL"); 368