1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADS1015 - Texas Instruments Analog-to-Digital Converter
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 *
7 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
8 * * 0x48 - ADDR connected to Ground
9 * * 0x49 - ADDR connected to Vdd
10 * * 0x4A - ADDR connected to SDA
11 * * 0x4B - ADDR connected to SCL
12 */
13
14 #include <linux/module.h>
15 #include <linux/cleanup.h>
16 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/i2c.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/mutex.h>
23 #include <linux/delay.h>
24
25 #include <linux/iio/iio.h>
26 #include <linux/iio/types.h>
27 #include <linux/iio/sysfs.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/trigger_consumer.h>
32
33 #define ADS1015_DRV_NAME "ads1015"
34
35 #define ADS1015_CHANNELS 8
36
37 #define ADS1015_CONV_REG 0x00
38 #define ADS1015_CFG_REG 0x01
39 #define ADS1015_LO_THRESH_REG 0x02
40 #define ADS1015_HI_THRESH_REG 0x03
41
42 #define ADS1015_CFG_COMP_QUE_SHIFT 0
43 #define ADS1015_CFG_COMP_LAT_SHIFT 2
44 #define ADS1015_CFG_COMP_POL_SHIFT 3
45 #define ADS1015_CFG_COMP_MODE_SHIFT 4
46 #define ADS1015_CFG_DR_SHIFT 5
47 #define ADS1015_CFG_MOD_SHIFT 8
48 #define ADS1015_CFG_PGA_SHIFT 9
49 #define ADS1015_CFG_MUX_SHIFT 12
50
51 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
52 #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
53 #define ADS1015_CFG_COMP_POL_MASK BIT(3)
54 #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
55 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
56 #define ADS1015_CFG_MOD_MASK BIT(8)
57 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
58 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
59
60 /* Comparator queue and disable field */
61 #define ADS1015_CFG_COMP_DISABLE 3
62
63 /* Comparator polarity field */
64 #define ADS1015_CFG_COMP_POL_LOW 0
65 #define ADS1015_CFG_COMP_POL_HIGH 1
66
67 /* Comparator mode field */
68 #define ADS1015_CFG_COMP_MODE_TRAD 0
69 #define ADS1015_CFG_COMP_MODE_WINDOW 1
70
71 /* device operating modes */
72 #define ADS1015_CONTINUOUS 0
73 #define ADS1015_SINGLESHOT 1
74
75 #define ADS1015_SLEEP_DELAY_MS 2000
76 #define ADS1015_DEFAULT_PGA 2
77 #define ADS1015_DEFAULT_DATA_RATE 4
78 #define ADS1015_DEFAULT_CHAN 0
79
80 struct ads1015_chip_data {
81 struct iio_chan_spec const *channels;
82 int num_channels;
83 const struct iio_info *info;
84 const int *data_rate;
85 const int data_rate_len;
86 const int *scale;
87 const int scale_len;
88 bool has_comparator;
89 };
90
91 enum ads1015_channels {
92 ADS1015_AIN0_AIN1 = 0,
93 ADS1015_AIN0_AIN3,
94 ADS1015_AIN1_AIN3,
95 ADS1015_AIN2_AIN3,
96 ADS1015_AIN0,
97 ADS1015_AIN1,
98 ADS1015_AIN2,
99 ADS1015_AIN3,
100 ADS1015_TIMESTAMP,
101 };
102
103 static const int ads1015_data_rate[] = {
104 128, 250, 490, 920, 1600, 2400, 3300, 3300
105 };
106
107 static const int ads1115_data_rate[] = {
108 8, 16, 32, 64, 128, 250, 475, 860
109 };
110
111 /*
112 * Translation from PGA bits to full-scale positive and negative input voltage
113 * range in mV
114 */
115 static const int ads1015_fullscale_range[] = {
116 6144, 4096, 2048, 1024, 512, 256, 256, 256
117 };
118
119 static const int ads1015_scale[] = { /* 12bit ADC */
120 256, 11,
121 512, 11,
122 1024, 11,
123 2048, 11,
124 4096, 11,
125 6144, 11
126 };
127
128 static const int ads1115_scale[] = { /* 16bit ADC */
129 256, 15,
130 512, 15,
131 1024, 15,
132 2048, 15,
133 4096, 15,
134 6144, 15
135 };
136
137 /*
138 * Translation from COMP_QUE field value to the number of successive readings
139 * exceed the threshold values before an interrupt is generated
140 */
141 static const int ads1015_comp_queue[] = { 1, 2, 4 };
142
143 static const struct iio_event_spec ads1015_events[] = {
144 {
145 .type = IIO_EV_TYPE_THRESH,
146 .dir = IIO_EV_DIR_RISING,
147 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
148 BIT(IIO_EV_INFO_ENABLE),
149 }, {
150 .type = IIO_EV_TYPE_THRESH,
151 .dir = IIO_EV_DIR_FALLING,
152 .mask_separate = BIT(IIO_EV_INFO_VALUE),
153 }, {
154 .type = IIO_EV_TYPE_THRESH,
155 .dir = IIO_EV_DIR_EITHER,
156 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
157 BIT(IIO_EV_INFO_PERIOD),
158 },
159 };
160
161 /*
162 * Compile-time check whether _fitbits can accommodate up to _testbits
163 * bits. Returns _fitbits on success, fails to compile otherwise.
164 *
165 * The test works such that it multiplies constant _fitbits by constant
166 * double-negation of size of a non-empty structure, i.e. it multiplies
167 * constant _fitbits by constant 1 in each successful compilation case.
168 * The non-empty structure may contain C11 _Static_assert(), make use of
169 * this and place the kernel variant of static assert in there, so that
170 * it performs the compile-time check for _testbits <= _fitbits. Note
171 * that it is not possible to directly use static_assert in compound
172 * statements, hence this convoluted construct.
173 */
174 #define FIT_CHECK(_testbits, _fitbits) \
175 ( \
176 (_fitbits) * \
177 !!sizeof(struct { \
178 static_assert((_testbits) <= (_fitbits)); \
179 int pad; \
180 }) \
181 )
182
183 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
184 .type = IIO_VOLTAGE, \
185 .indexed = 1, \
186 .address = _addr, \
187 .channel = _chan, \
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
189 BIT(IIO_CHAN_INFO_SCALE) | \
190 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
191 .info_mask_shared_by_all_available = \
192 BIT(IIO_CHAN_INFO_SCALE) | \
193 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
194 .scan_index = _addr, \
195 .scan_type = { \
196 .sign = 's', \
197 .realbits = (_realbits), \
198 .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
199 .shift = (_shift), \
200 .endianness = IIO_CPU, \
201 }, \
202 .event_spec = (_event_spec), \
203 .num_event_specs = (_num_event_specs), \
204 .datasheet_name = "AIN"#_chan, \
205 }
206
207 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
208 .type = IIO_VOLTAGE, \
209 .differential = 1, \
210 .indexed = 1, \
211 .address = _addr, \
212 .channel = _chan, \
213 .channel2 = _chan2, \
214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
215 BIT(IIO_CHAN_INFO_SCALE) | \
216 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
217 .info_mask_shared_by_all_available = \
218 BIT(IIO_CHAN_INFO_SCALE) | \
219 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
220 .scan_index = _addr, \
221 .scan_type = { \
222 .sign = 's', \
223 .realbits = (_realbits), \
224 .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
225 .shift = (_shift), \
226 .endianness = IIO_CPU, \
227 }, \
228 .event_spec = (_event_spec), \
229 .num_event_specs = (_num_event_specs), \
230 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
231 }
232
233 struct ads1015_channel_data {
234 unsigned int pga;
235 unsigned int data_rate;
236 };
237
238 struct ads1015_thresh_data {
239 unsigned int comp_queue;
240 int high_thresh;
241 int low_thresh;
242 };
243
244 struct ads1015_data {
245 struct regmap *regmap;
246 /*
247 * Protects ADC ops, e.g: concurrent sysfs/buffered
248 * data reads, configuration updates
249 */
250 struct mutex lock;
251 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
252
253 unsigned int event_channel;
254 unsigned int comp_mode;
255 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
256
257 const struct ads1015_chip_data *chip;
258 /*
259 * Set to true when the ADC is switched to the continuous-conversion
260 * mode and exits from a power-down state. This flag is used to avoid
261 * getting the stale result from the conversion register.
262 */
263 bool conv_invalid;
264 };
265
ads1015_event_channel_enabled(struct ads1015_data * data)266 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
267 {
268 return (data->event_channel != ADS1015_CHANNELS);
269 }
270
ads1015_event_channel_enable(struct ads1015_data * data,int chan,int comp_mode)271 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
272 int comp_mode)
273 {
274 WARN_ON(ads1015_event_channel_enabled(data));
275
276 data->event_channel = chan;
277 data->comp_mode = comp_mode;
278 }
279
ads1015_event_channel_disable(struct ads1015_data * data,int chan)280 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
281 {
282 data->event_channel = ADS1015_CHANNELS;
283 }
284
285 static const struct regmap_range ads1015_writeable_ranges[] = {
286 regmap_reg_range(ADS1015_CFG_REG, ADS1015_HI_THRESH_REG),
287 };
288
289 static const struct regmap_access_table ads1015_writeable_table = {
290 .yes_ranges = ads1015_writeable_ranges,
291 .n_yes_ranges = ARRAY_SIZE(ads1015_writeable_ranges),
292 };
293
294 static const struct regmap_config ads1015_regmap_config = {
295 .reg_bits = 8,
296 .val_bits = 16,
297 .max_register = ADS1015_HI_THRESH_REG,
298 .wr_table = &ads1015_writeable_table,
299 };
300
301 static const struct regmap_range tla2024_writeable_ranges[] = {
302 regmap_reg_range(ADS1015_CFG_REG, ADS1015_CFG_REG),
303 };
304
305 static const struct regmap_access_table tla2024_writeable_table = {
306 .yes_ranges = tla2024_writeable_ranges,
307 .n_yes_ranges = ARRAY_SIZE(tla2024_writeable_ranges),
308 };
309
310 static const struct regmap_config tla2024_regmap_config = {
311 .reg_bits = 8,
312 .val_bits = 16,
313 .max_register = ADS1015_CFG_REG,
314 .wr_table = &tla2024_writeable_table,
315 };
316
317 static const struct iio_chan_spec ads1015_channels[] = {
318 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4,
319 ads1015_events, ARRAY_SIZE(ads1015_events)),
320 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4,
321 ads1015_events, ARRAY_SIZE(ads1015_events)),
322 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4,
323 ads1015_events, ARRAY_SIZE(ads1015_events)),
324 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4,
325 ads1015_events, ARRAY_SIZE(ads1015_events)),
326 ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4,
327 ads1015_events, ARRAY_SIZE(ads1015_events)),
328 ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4,
329 ads1015_events, ARRAY_SIZE(ads1015_events)),
330 ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4,
331 ads1015_events, ARRAY_SIZE(ads1015_events)),
332 ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4,
333 ads1015_events, ARRAY_SIZE(ads1015_events)),
334 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
335 };
336
337 static const struct iio_chan_spec ads1115_channels[] = {
338 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 16, 0,
339 ads1015_events, ARRAY_SIZE(ads1015_events)),
340 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 16, 0,
341 ads1015_events, ARRAY_SIZE(ads1015_events)),
342 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 16, 0,
343 ads1015_events, ARRAY_SIZE(ads1015_events)),
344 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 16, 0,
345 ads1015_events, ARRAY_SIZE(ads1015_events)),
346 ADS1015_V_CHAN(0, ADS1015_AIN0, 16, 0,
347 ads1015_events, ARRAY_SIZE(ads1015_events)),
348 ADS1015_V_CHAN(1, ADS1015_AIN1, 16, 0,
349 ads1015_events, ARRAY_SIZE(ads1015_events)),
350 ADS1015_V_CHAN(2, ADS1015_AIN2, 16, 0,
351 ads1015_events, ARRAY_SIZE(ads1015_events)),
352 ADS1015_V_CHAN(3, ADS1015_AIN3, 16, 0,
353 ads1015_events, ARRAY_SIZE(ads1015_events)),
354 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
355 };
356
357 static const struct iio_chan_spec tla2024_channels[] = {
358 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, NULL, 0),
359 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, NULL, 0),
360 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, NULL, 0),
361 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, NULL, 0),
362 ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, NULL, 0),
363 ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, NULL, 0),
364 ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, NULL, 0),
365 ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, NULL, 0),
366 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
367 };
368
369
370 #ifdef CONFIG_PM
ads1015_set_power_state(struct ads1015_data * data,bool on)371 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
372 {
373 int ret;
374 struct device *dev = regmap_get_device(data->regmap);
375
376 if (on)
377 ret = pm_runtime_resume_and_get(dev);
378 else
379 ret = pm_runtime_put_autosuspend(dev);
380
381 return ret < 0 ? ret : 0;
382 }
383
384 #else /* !CONFIG_PM */
385
ads1015_set_power_state(struct ads1015_data * data,bool on)386 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
387 {
388 return 0;
389 }
390
391 #endif /* !CONFIG_PM */
392
393 static
ads1015_get_adc_result(struct ads1015_data * data,int chan,int * val)394 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
395 {
396 const int *data_rate = data->chip->data_rate;
397 int ret, pga, dr, dr_old, conv_time;
398 unsigned int old, mask, cfg;
399
400 if (chan < 0 || chan >= ADS1015_CHANNELS)
401 return -EINVAL;
402
403 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
404 if (ret)
405 return ret;
406
407 pga = data->channel_data[chan].pga;
408 dr = data->channel_data[chan].data_rate;
409 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
410 ADS1015_CFG_DR_MASK;
411 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
412 dr << ADS1015_CFG_DR_SHIFT;
413
414 if (ads1015_event_channel_enabled(data)) {
415 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
416 cfg |= data->thresh_data[chan].comp_queue <<
417 ADS1015_CFG_COMP_QUE_SHIFT |
418 data->comp_mode <<
419 ADS1015_CFG_COMP_MODE_SHIFT;
420 }
421
422 cfg = (old & ~mask) | (cfg & mask);
423 if (old != cfg) {
424 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
425 if (ret)
426 return ret;
427 data->conv_invalid = true;
428 }
429 if (data->conv_invalid) {
430 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
431 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]);
432 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]);
433 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
434 usleep_range(conv_time, conv_time + 1);
435 data->conv_invalid = false;
436 }
437
438 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
439 }
440
ads1015_trigger_handler(int irq,void * p)441 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
442 {
443 struct iio_poll_func *pf = p;
444 struct iio_dev *indio_dev = pf->indio_dev;
445 struct ads1015_data *data = iio_priv(indio_dev);
446 /* Ensure natural alignment of timestamp */
447 struct {
448 s16 chan;
449 aligned_s64 timestamp;
450 } scan = { };
451 int chan, ret, res;
452
453 mutex_lock(&data->lock);
454 chan = find_first_bit(indio_dev->active_scan_mask,
455 iio_get_masklength(indio_dev));
456 ret = ads1015_get_adc_result(data, chan, &res);
457 if (ret < 0) {
458 mutex_unlock(&data->lock);
459 goto err;
460 }
461
462 scan.chan = res;
463 mutex_unlock(&data->lock);
464
465 iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan),
466 iio_get_time_ns(indio_dev));
467
468 err:
469 iio_trigger_notify_done(indio_dev->trig);
470
471 return IRQ_HANDLED;
472 }
473
ads1015_set_scale(struct ads1015_data * data,struct iio_chan_spec const * chan,int scale,int uscale)474 static int ads1015_set_scale(struct ads1015_data *data,
475 struct iio_chan_spec const *chan,
476 int scale, int uscale)
477 {
478 int i;
479 int fullscale = div_s64((scale * 1000000LL + uscale) <<
480 (chan->scan_type.realbits - 1), 1000000);
481
482 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
483 if (ads1015_fullscale_range[i] == fullscale) {
484 data->channel_data[chan->address].pga = i;
485 return 0;
486 }
487 }
488
489 return -EINVAL;
490 }
491
ads1015_set_data_rate(struct ads1015_data * data,int chan,int rate)492 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
493 {
494 int i;
495
496 for (i = 0; i < data->chip->data_rate_len; i++) {
497 if (data->chip->data_rate[i] == rate) {
498 data->channel_data[chan].data_rate = i;
499 return 0;
500 }
501 }
502
503 return -EINVAL;
504 }
505
ads1015_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)506 static int ads1015_read_avail(struct iio_dev *indio_dev,
507 struct iio_chan_spec const *chan,
508 const int **vals, int *type, int *length,
509 long mask)
510 {
511 struct ads1015_data *data = iio_priv(indio_dev);
512
513 if (chan->type != IIO_VOLTAGE)
514 return -EINVAL;
515
516 switch (mask) {
517 case IIO_CHAN_INFO_SCALE:
518 *type = IIO_VAL_FRACTIONAL_LOG2;
519 *vals = data->chip->scale;
520 *length = data->chip->scale_len;
521 return IIO_AVAIL_LIST;
522 case IIO_CHAN_INFO_SAMP_FREQ:
523 *type = IIO_VAL_INT;
524 *vals = data->chip->data_rate;
525 *length = data->chip->data_rate_len;
526 return IIO_AVAIL_LIST;
527 default:
528 return -EINVAL;
529 }
530 }
531
__ads1015_read_info_raw(struct ads1015_data * data,struct iio_chan_spec const * chan,int * val)532 static int __ads1015_read_info_raw(struct ads1015_data *data,
533 struct iio_chan_spec const *chan, int *val)
534 {
535 int ret;
536
537 if (ads1015_event_channel_enabled(data) &&
538 data->event_channel != chan->address)
539 return -EBUSY;
540
541 ret = ads1015_set_power_state(data, true);
542 if (ret < 0)
543 return ret;
544
545 ret = ads1015_get_adc_result(data, chan->address, val);
546 if (ret < 0) {
547 ads1015_set_power_state(data, false);
548 return ret;
549 }
550
551 *val = sign_extend32(*val >> chan->scan_type.shift,
552 chan->scan_type.realbits - 1);
553
554 return ads1015_set_power_state(data, false);
555 }
556
ads1015_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)557 static int ads1015_read_raw(struct iio_dev *indio_dev,
558 struct iio_chan_spec const *chan, int *val,
559 int *val2, long mask)
560 {
561 int ret, idx;
562 struct ads1015_data *data = iio_priv(indio_dev);
563
564 guard(mutex)(&data->lock);
565 switch (mask) {
566 case IIO_CHAN_INFO_RAW:
567 if (!iio_device_claim_direct(indio_dev))
568 return -EBUSY;
569 ret = __ads1015_read_info_raw(data, chan, val);
570 iio_device_release_direct(indio_dev);
571 if (ret)
572 return ret;
573
574 return IIO_VAL_INT;
575 case IIO_CHAN_INFO_SCALE:
576 idx = data->channel_data[chan->address].pga;
577 *val = ads1015_fullscale_range[idx];
578 *val2 = chan->scan_type.realbits - 1;
579 return IIO_VAL_FRACTIONAL_LOG2;
580 case IIO_CHAN_INFO_SAMP_FREQ:
581 idx = data->channel_data[chan->address].data_rate;
582 *val = data->chip->data_rate[idx];
583 return IIO_VAL_INT;
584 default:
585 return -EINVAL;
586 }
587 }
588
ads1015_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)589 static int ads1015_write_raw(struct iio_dev *indio_dev,
590 struct iio_chan_spec const *chan, int val,
591 int val2, long mask)
592 {
593 struct ads1015_data *data = iio_priv(indio_dev);
594
595 guard(mutex)(&data->lock);
596 switch (mask) {
597 case IIO_CHAN_INFO_SCALE:
598 return ads1015_set_scale(data, chan, val, val2);
599 case IIO_CHAN_INFO_SAMP_FREQ:
600 return ads1015_set_data_rate(data, chan->address, val);
601 default:
602 return -EINVAL;
603 }
604 }
605
ads1015_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)606 static int ads1015_read_event(struct iio_dev *indio_dev,
607 const struct iio_chan_spec *chan, enum iio_event_type type,
608 enum iio_event_direction dir, enum iio_event_info info, int *val,
609 int *val2)
610 {
611 struct ads1015_data *data = iio_priv(indio_dev);
612 unsigned int comp_queue;
613 int period;
614 int dr;
615
616 guard(mutex)(&data->lock);
617
618 switch (info) {
619 case IIO_EV_INFO_VALUE:
620 *val = (dir == IIO_EV_DIR_RISING) ?
621 data->thresh_data[chan->address].high_thresh :
622 data->thresh_data[chan->address].low_thresh;
623 return IIO_VAL_INT;
624 case IIO_EV_INFO_PERIOD:
625 dr = data->channel_data[chan->address].data_rate;
626 comp_queue = data->thresh_data[chan->address].comp_queue;
627 period = ads1015_comp_queue[comp_queue] *
628 USEC_PER_SEC / data->chip->data_rate[dr];
629
630 *val = period / USEC_PER_SEC;
631 *val2 = period % USEC_PER_SEC;
632 return IIO_VAL_INT_PLUS_MICRO;
633 default:
634 return -EINVAL;
635 }
636 }
637
ads1015_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)638 static int ads1015_write_event(struct iio_dev *indio_dev,
639 const struct iio_chan_spec *chan, enum iio_event_type type,
640 enum iio_event_direction dir, enum iio_event_info info, int val,
641 int val2)
642 {
643 struct ads1015_data *data = iio_priv(indio_dev);
644 const int *data_rate = data->chip->data_rate;
645 int realbits = chan->scan_type.realbits;
646 long long period;
647 int i;
648 int dr;
649
650 guard(mutex)(&data->lock);
651
652 switch (info) {
653 case IIO_EV_INFO_VALUE:
654 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1))
655 return -EINVAL;
656
657 if (dir == IIO_EV_DIR_RISING)
658 data->thresh_data[chan->address].high_thresh = val;
659 else
660 data->thresh_data[chan->address].low_thresh = val;
661 return 0;
662 case IIO_EV_INFO_PERIOD:
663 dr = data->channel_data[chan->address].data_rate;
664 period = val * USEC_PER_SEC + val2;
665
666 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
667 if (period <= ads1015_comp_queue[i] *
668 USEC_PER_SEC / data_rate[dr])
669 break;
670 }
671 data->thresh_data[chan->address].comp_queue = i;
672 return 0;
673 default:
674 return -EINVAL;
675 }
676 }
677
ads1015_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)678 static int ads1015_read_event_config(struct iio_dev *indio_dev,
679 const struct iio_chan_spec *chan, enum iio_event_type type,
680 enum iio_event_direction dir)
681 {
682 struct ads1015_data *data = iio_priv(indio_dev);
683
684 guard(mutex)(&data->lock);
685 if (data->event_channel != chan->address)
686 return 0;
687
688 switch (dir) {
689 case IIO_EV_DIR_RISING:
690 return 1;
691 case IIO_EV_DIR_EITHER:
692 return (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
693 default:
694 return -EINVAL;
695 }
696 }
697
ads1015_enable_event_config(struct ads1015_data * data,const struct iio_chan_spec * chan,int comp_mode)698 static int ads1015_enable_event_config(struct ads1015_data *data,
699 const struct iio_chan_spec *chan, int comp_mode)
700 {
701 int low_thresh = data->thresh_data[chan->address].low_thresh;
702 int high_thresh = data->thresh_data[chan->address].high_thresh;
703 int ret;
704 unsigned int val;
705
706 if (ads1015_event_channel_enabled(data)) {
707 if (data->event_channel != chan->address ||
708 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
709 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
710 return -EBUSY;
711
712 return 0;
713 }
714
715 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
716 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
717 high_thresh - 1);
718 }
719 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
720 low_thresh << chan->scan_type.shift);
721 if (ret)
722 return ret;
723
724 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
725 high_thresh << chan->scan_type.shift);
726 if (ret)
727 return ret;
728
729 ret = ads1015_set_power_state(data, true);
730 if (ret < 0)
731 return ret;
732
733 ads1015_event_channel_enable(data, chan->address, comp_mode);
734
735 ret = ads1015_get_adc_result(data, chan->address, &val);
736 if (ret) {
737 ads1015_event_channel_disable(data, chan->address);
738 ads1015_set_power_state(data, false);
739 }
740
741 return ret;
742 }
743
ads1015_disable_event_config(struct ads1015_data * data,const struct iio_chan_spec * chan,int comp_mode)744 static int ads1015_disable_event_config(struct ads1015_data *data,
745 const struct iio_chan_spec *chan, int comp_mode)
746 {
747 int ret;
748
749 if (!ads1015_event_channel_enabled(data))
750 return 0;
751
752 if (data->event_channel != chan->address)
753 return 0;
754
755 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
756 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
757 return 0;
758
759 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
760 ADS1015_CFG_COMP_QUE_MASK,
761 ADS1015_CFG_COMP_DISABLE <<
762 ADS1015_CFG_COMP_QUE_SHIFT);
763 if (ret)
764 return ret;
765
766 ads1015_event_channel_disable(data, chan->address);
767
768 return ads1015_set_power_state(data, false);
769 }
770
ads1015_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)771 static int ads1015_write_event_config(struct iio_dev *indio_dev,
772 const struct iio_chan_spec *chan, enum iio_event_type type,
773 enum iio_event_direction dir, bool state)
774 {
775 struct ads1015_data *data = iio_priv(indio_dev);
776 int ret;
777 int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
778 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
779
780 guard(mutex)(&data->lock);
781
782 /* Prevent from enabling both buffer and event at a time */
783 if (!iio_device_claim_direct(indio_dev))
784 return -EBUSY;
785
786 if (state)
787 ret = ads1015_enable_event_config(data, chan, comp_mode);
788 else
789 ret = ads1015_disable_event_config(data, chan, comp_mode);
790
791 iio_device_release_direct(indio_dev);
792 return ret;
793 }
794
ads1015_event_handler(int irq,void * priv)795 static irqreturn_t ads1015_event_handler(int irq, void *priv)
796 {
797 struct iio_dev *indio_dev = priv;
798 struct ads1015_data *data = iio_priv(indio_dev);
799 int val;
800 int ret;
801
802 /* Clear the latched ALERT/RDY pin */
803 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
804 if (ret)
805 return IRQ_HANDLED;
806
807 if (ads1015_event_channel_enabled(data)) {
808 enum iio_event_direction dir;
809 u64 code;
810
811 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
812 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
813 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
814 IIO_EV_TYPE_THRESH, dir);
815 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
816 }
817
818 return IRQ_HANDLED;
819 }
820
ads1015_buffer_preenable(struct iio_dev * indio_dev)821 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
822 {
823 struct ads1015_data *data = iio_priv(indio_dev);
824
825 /* Prevent from enabling both buffer and event at a time */
826 if (ads1015_event_channel_enabled(data))
827 return -EBUSY;
828
829 return ads1015_set_power_state(iio_priv(indio_dev), true);
830 }
831
ads1015_buffer_postdisable(struct iio_dev * indio_dev)832 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
833 {
834 return ads1015_set_power_state(iio_priv(indio_dev), false);
835 }
836
837 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
838 .preenable = ads1015_buffer_preenable,
839 .postdisable = ads1015_buffer_postdisable,
840 .validate_scan_mask = &iio_validate_scan_mask_onehot,
841 };
842
843 static const struct iio_info ads1015_info = {
844 .read_avail = ads1015_read_avail,
845 .read_raw = ads1015_read_raw,
846 .write_raw = ads1015_write_raw,
847 .read_event_value = ads1015_read_event,
848 .write_event_value = ads1015_write_event,
849 .read_event_config = ads1015_read_event_config,
850 .write_event_config = ads1015_write_event_config,
851 };
852
853 static const struct iio_info tla2024_info = {
854 .read_avail = ads1015_read_avail,
855 .read_raw = ads1015_read_raw,
856 .write_raw = ads1015_write_raw,
857 };
858
ads1015_client_get_channels_config(struct i2c_client * client)859 static int ads1015_client_get_channels_config(struct i2c_client *client)
860 {
861 struct iio_dev *indio_dev = i2c_get_clientdata(client);
862 struct ads1015_data *data = iio_priv(indio_dev);
863 struct device *dev = &client->dev;
864 int i = -1;
865
866 device_for_each_child_node_scoped(dev, node) {
867 u32 pval;
868 unsigned int channel;
869 unsigned int pga = ADS1015_DEFAULT_PGA;
870 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
871
872 if (fwnode_property_read_u32(node, "reg", &pval)) {
873 dev_err(dev, "invalid reg on %pfw\n", node);
874 continue;
875 }
876
877 channel = pval;
878 if (channel >= ADS1015_CHANNELS) {
879 dev_err(dev, "invalid channel index %d on %pfw\n",
880 channel, node);
881 continue;
882 }
883
884 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
885 pga = pval;
886 if (pga > 5) {
887 dev_err(dev, "invalid gain on %pfw\n", node);
888 return -EINVAL;
889 }
890 }
891
892 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
893 data_rate = pval;
894 if (data_rate > 7) {
895 dev_err(dev, "invalid data_rate on %pfw\n", node);
896 return -EINVAL;
897 }
898 }
899
900 data->channel_data[channel].pga = pga;
901 data->channel_data[channel].data_rate = data_rate;
902
903 i++;
904 }
905
906 return i < 0 ? -EINVAL : 0;
907 }
908
ads1015_get_channels_config(struct i2c_client * client)909 static void ads1015_get_channels_config(struct i2c_client *client)
910 {
911 unsigned int k;
912
913 struct iio_dev *indio_dev = i2c_get_clientdata(client);
914 struct ads1015_data *data = iio_priv(indio_dev);
915
916 if (!ads1015_client_get_channels_config(client))
917 return;
918
919 /* fallback on default configuration */
920 for (k = 0; k < ADS1015_CHANNELS; ++k) {
921 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
922 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
923 }
924 }
925
ads1015_set_conv_mode(struct ads1015_data * data,int mode)926 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
927 {
928 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
929 ADS1015_CFG_MOD_MASK,
930 mode << ADS1015_CFG_MOD_SHIFT);
931 }
932
ads1015_probe(struct i2c_client * client)933 static int ads1015_probe(struct i2c_client *client)
934 {
935 const struct ads1015_chip_data *chip;
936 struct iio_dev *indio_dev;
937 struct ads1015_data *data;
938 int ret;
939 int i;
940
941 chip = i2c_get_match_data(client);
942 if (!chip)
943 return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
944
945 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
946 if (!indio_dev)
947 return -ENOMEM;
948
949 data = iio_priv(indio_dev);
950 i2c_set_clientdata(client, indio_dev);
951
952 mutex_init(&data->lock);
953
954 indio_dev->name = ADS1015_DRV_NAME;
955 indio_dev->modes = INDIO_DIRECT_MODE;
956
957 indio_dev->channels = chip->channels;
958 indio_dev->num_channels = chip->num_channels;
959 indio_dev->info = chip->info;
960 data->chip = chip;
961 data->event_channel = ADS1015_CHANNELS;
962
963 /*
964 * Set default lower and upper threshold to min and max value
965 * respectively.
966 */
967 for (i = 0; i < ADS1015_CHANNELS; i++) {
968 int realbits = indio_dev->channels[i].scan_type.realbits;
969
970 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
971 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
972 }
973
974 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
975 ads1015_get_channels_config(client);
976
977 data->regmap = devm_regmap_init_i2c(client, chip->has_comparator ?
978 &ads1015_regmap_config :
979 &tla2024_regmap_config);
980 if (IS_ERR(data->regmap)) {
981 dev_err(&client->dev, "Failed to allocate register map\n");
982 return PTR_ERR(data->regmap);
983 }
984
985 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
986 ads1015_trigger_handler,
987 &ads1015_buffer_setup_ops);
988 if (ret < 0) {
989 dev_err(&client->dev, "iio triggered buffer setup failed\n");
990 return ret;
991 }
992
993 if (client->irq && chip->has_comparator) {
994 unsigned long irq_trig = irq_get_trigger_type(client->irq);
995 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
996 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
997 unsigned int cfg_comp =
998 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
999 1 << ADS1015_CFG_COMP_LAT_SHIFT;
1000
1001 switch (irq_trig) {
1002 case IRQF_TRIGGER_FALLING:
1003 case IRQF_TRIGGER_LOW:
1004 cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1005 ADS1015_CFG_COMP_POL_SHIFT;
1006 break;
1007 case IRQF_TRIGGER_HIGH:
1008 case IRQF_TRIGGER_RISING:
1009 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1010 ADS1015_CFG_COMP_POL_SHIFT;
1011 break;
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1017 cfg_comp_mask, cfg_comp);
1018 if (ret)
1019 return ret;
1020
1021 ret = devm_request_threaded_irq(&client->dev, client->irq,
1022 NULL, ads1015_event_handler,
1023 irq_trig | IRQF_ONESHOT,
1024 client->name, indio_dev);
1025 if (ret)
1026 return ret;
1027 }
1028
1029 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1030 if (ret)
1031 return ret;
1032
1033 data->conv_invalid = true;
1034
1035 ret = pm_runtime_set_active(&client->dev);
1036 if (ret)
1037 return ret;
1038 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1039 pm_runtime_use_autosuspend(&client->dev);
1040 pm_runtime_enable(&client->dev);
1041
1042 ret = iio_device_register(indio_dev);
1043 if (ret < 0) {
1044 dev_err(&client->dev, "Failed to register IIO device\n");
1045 return ret;
1046 }
1047
1048 return 0;
1049 }
1050
ads1015_remove(struct i2c_client * client)1051 static void ads1015_remove(struct i2c_client *client)
1052 {
1053 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1054 struct ads1015_data *data = iio_priv(indio_dev);
1055 int ret;
1056
1057 iio_device_unregister(indio_dev);
1058
1059 pm_runtime_disable(&client->dev);
1060 pm_runtime_set_suspended(&client->dev);
1061
1062 /* power down single shot mode */
1063 ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1064 if (ret)
1065 dev_warn(&client->dev, "Failed to power down (%pe)\n",
1066 ERR_PTR(ret));
1067 }
1068
1069 #ifdef CONFIG_PM
ads1015_runtime_suspend(struct device * dev)1070 static int ads1015_runtime_suspend(struct device *dev)
1071 {
1072 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1073 struct ads1015_data *data = iio_priv(indio_dev);
1074
1075 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1076 }
1077
ads1015_runtime_resume(struct device * dev)1078 static int ads1015_runtime_resume(struct device *dev)
1079 {
1080 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1081 struct ads1015_data *data = iio_priv(indio_dev);
1082 int ret;
1083
1084 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1085 if (!ret)
1086 data->conv_invalid = true;
1087
1088 return ret;
1089 }
1090 #endif
1091
1092 static const struct dev_pm_ops ads1015_pm_ops = {
1093 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1094 ads1015_runtime_resume, NULL)
1095 };
1096
1097 static const struct ads1015_chip_data ads1015_data = {
1098 .channels = ads1015_channels,
1099 .num_channels = ARRAY_SIZE(ads1015_channels),
1100 .info = &ads1015_info,
1101 .data_rate = ads1015_data_rate,
1102 .data_rate_len = ARRAY_SIZE(ads1015_data_rate),
1103 .scale = ads1015_scale,
1104 .scale_len = ARRAY_SIZE(ads1015_scale),
1105 .has_comparator = true,
1106 };
1107
1108 static const struct ads1015_chip_data ads1115_data = {
1109 .channels = ads1115_channels,
1110 .num_channels = ARRAY_SIZE(ads1115_channels),
1111 .info = &ads1015_info,
1112 .data_rate = ads1115_data_rate,
1113 .data_rate_len = ARRAY_SIZE(ads1115_data_rate),
1114 .scale = ads1115_scale,
1115 .scale_len = ARRAY_SIZE(ads1115_scale),
1116 .has_comparator = true,
1117 };
1118
1119 static const struct ads1015_chip_data tla2024_data = {
1120 .channels = tla2024_channels,
1121 .num_channels = ARRAY_SIZE(tla2024_channels),
1122 .info = &tla2024_info,
1123 .data_rate = ads1015_data_rate,
1124 .data_rate_len = ARRAY_SIZE(ads1015_data_rate),
1125 .scale = ads1015_scale,
1126 .scale_len = ARRAY_SIZE(ads1015_scale),
1127 .has_comparator = false,
1128 };
1129
1130 static const struct i2c_device_id ads1015_id[] = {
1131 { "ads1015", (kernel_ulong_t)&ads1015_data },
1132 { "ads1115", (kernel_ulong_t)&ads1115_data },
1133 { "tla2024", (kernel_ulong_t)&tla2024_data },
1134 { }
1135 };
1136 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1137
1138 static const struct of_device_id ads1015_of_match[] = {
1139 { .compatible = "ti,ads1015", .data = &ads1015_data },
1140 { .compatible = "ti,ads1115", .data = &ads1115_data },
1141 { .compatible = "ti,tla2024", .data = &tla2024_data },
1142 { }
1143 };
1144 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1145
1146 static struct i2c_driver ads1015_driver = {
1147 .driver = {
1148 .name = ADS1015_DRV_NAME,
1149 .of_match_table = ads1015_of_match,
1150 .pm = &ads1015_pm_ops,
1151 },
1152 .probe = ads1015_probe,
1153 .remove = ads1015_remove,
1154 .id_table = ads1015_id,
1155 };
1156
1157 module_i2c_driver(ads1015_driver);
1158
1159 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1160 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1161 MODULE_LICENSE("GPL v2");
1162