1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module 3 * 4 * This driver supports the memory controllers found on the Intel 5 * processor family Sandy Bridge. 6 * 7 * Copyright (c) 2011 by: 8 * Mauro Carvalho Chehab 9 */ 10 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pci_ids.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/edac.h> 18 #include <linux/mmzone.h> 19 #include <linux/smp.h> 20 #include <linux/bitmap.h> 21 #include <linux/math64.h> 22 #include <linux/mod_devicetable.h> 23 #include <asm/cpu_device_id.h> 24 #include <asm/intel-family.h> 25 #include <asm/processor.h> 26 #include <asm/mce.h> 27 28 #include "edac_module.h" 29 30 /* Static vars */ 31 static LIST_HEAD(sbridge_edac_list); 32 static char sb_msg[256]; 33 static char sb_msg_full[512]; 34 35 /* 36 * Alter this version for the module when modifications are made 37 */ 38 #define SBRIDGE_REVISION " Ver: 1.1.2 " 39 #define EDAC_MOD_STR "sb_edac" 40 41 /* 42 * Debug macros 43 */ 44 #define sbridge_printk(level, fmt, arg...) \ 45 edac_printk(level, "sbridge", fmt, ##arg) 46 47 #define sbridge_mc_printk(mci, level, fmt, arg...) \ 48 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) 49 50 /* 51 * Get a bit field at register value <v>, from bit <lo> to bit <hi> 52 */ 53 #define GET_BITFIELD(v, lo, hi) \ 54 (((v) & GENMASK_ULL(hi, lo)) >> (lo)) 55 56 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ 57 static const u32 sbridge_dram_rule[] = { 58 0x80, 0x88, 0x90, 0x98, 0xa0, 59 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, 60 }; 61 62 static const u32 ibridge_dram_rule[] = { 63 0x60, 0x68, 0x70, 0x78, 0x80, 64 0x88, 0x90, 0x98, 0xa0, 0xa8, 65 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, 66 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, 67 }; 68 69 static const u32 knl_dram_rule[] = { 70 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */ 71 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */ 72 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */ 73 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */ 74 0x100, 0x108, 0x110, 0x118, /* 20-23 */ 75 }; 76 77 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 78 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) 79 80 static char *show_dram_attr(u32 attr) 81 { 82 switch (attr) { 83 case 0: 84 return "DRAM"; 85 case 1: 86 return "MMCFG"; 87 case 2: 88 return "NXM"; 89 default: 90 return "unknown"; 91 } 92 } 93 94 static const u32 sbridge_interleave_list[] = { 95 0x84, 0x8c, 0x94, 0x9c, 0xa4, 96 0xac, 0xb4, 0xbc, 0xc4, 0xcc, 97 }; 98 99 static const u32 ibridge_interleave_list[] = { 100 0x64, 0x6c, 0x74, 0x7c, 0x84, 101 0x8c, 0x94, 0x9c, 0xa4, 0xac, 102 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, 103 0xdc, 0xe4, 0xec, 0xf4, 0xfc, 104 }; 105 106 static const u32 knl_interleave_list[] = { 107 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */ 108 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */ 109 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */ 110 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */ 111 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */ 112 }; 113 #define MAX_INTERLEAVE \ 114 (MAX_T(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \ 115 MAX_T(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \ 116 ARRAY_SIZE(knl_interleave_list)))) 117 118 struct interleave_pkg { 119 unsigned char start; 120 unsigned char end; 121 }; 122 123 static const struct interleave_pkg sbridge_interleave_pkg[] = { 124 { 0, 2 }, 125 { 3, 5 }, 126 { 8, 10 }, 127 { 11, 13 }, 128 { 16, 18 }, 129 { 19, 21 }, 130 { 24, 26 }, 131 { 27, 29 }, 132 }; 133 134 static const struct interleave_pkg ibridge_interleave_pkg[] = { 135 { 0, 3 }, 136 { 4, 7 }, 137 { 8, 11 }, 138 { 12, 15 }, 139 { 16, 19 }, 140 { 20, 23 }, 141 { 24, 27 }, 142 { 28, 31 }, 143 }; 144 145 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, 146 int interleave) 147 { 148 return GET_BITFIELD(reg, table[interleave].start, 149 table[interleave].end); 150 } 151 152 /* Devices 12 Function 7 */ 153 154 #define TOLM 0x80 155 #define TOHM 0x84 156 #define HASWELL_TOLM 0xd0 157 #define HASWELL_TOHM_0 0xd4 158 #define HASWELL_TOHM_1 0xd8 159 #define KNL_TOLM 0xd0 160 #define KNL_TOHM_0 0xd4 161 #define KNL_TOHM_1 0xd8 162 163 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) 164 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) 165 166 /* Device 13 Function 6 */ 167 168 #define SAD_TARGET 0xf0 169 170 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) 171 172 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14) 173 174 #define SAD_CONTROL 0xf4 175 176 /* Device 14 function 0 */ 177 178 static const u32 tad_dram_rule[] = { 179 0x40, 0x44, 0x48, 0x4c, 180 0x50, 0x54, 0x58, 0x5c, 181 0x60, 0x64, 0x68, 0x6c, 182 }; 183 #define MAX_TAD ARRAY_SIZE(tad_dram_rule) 184 185 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) 186 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) 187 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) 188 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) 189 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) 190 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) 191 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) 192 193 /* Device 15, function 0 */ 194 195 #define MCMTR 0x7c 196 #define KNL_MCMTR 0x624 197 198 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) 199 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) 200 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) 201 202 /* Device 15, function 1 */ 203 204 #define RASENABLES 0xac 205 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) 206 207 /* Device 15, functions 2-5 */ 208 209 static const int mtr_regs[] = { 210 0x80, 0x84, 0x88, 211 }; 212 213 static const int knl_mtr_reg = 0xb60; 214 215 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) 216 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) 217 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) 218 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) 219 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) 220 221 static const u32 tad_ch_nilv_offset[] = { 222 0x90, 0x94, 0x98, 0x9c, 223 0xa0, 0xa4, 0xa8, 0xac, 224 0xb0, 0xb4, 0xb8, 0xbc, 225 }; 226 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) 227 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) 228 229 static const u32 rir_way_limit[] = { 230 0x108, 0x10c, 0x110, 0x114, 0x118, 231 }; 232 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) 233 234 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) 235 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) 236 237 #define MAX_RIR_WAY 8 238 239 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { 240 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, 241 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, 242 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, 243 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, 244 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, 245 }; 246 247 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ 248 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) 249 250 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ 251 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) 252 253 /* Device 16, functions 2-7 */ 254 255 /* 256 * FIXME: Implement the error count reads directly 257 */ 258 259 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) 260 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) 261 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) 262 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) 263 264 #if 0 /* Currently unused*/ 265 static const u32 correrrcnt[] = { 266 0x104, 0x108, 0x10c, 0x110, 267 }; 268 269 static const u32 correrrthrsld[] = { 270 0x11c, 0x120, 0x124, 0x128, 271 }; 272 #endif 273 274 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) 275 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) 276 277 278 /* Device 17, function 0 */ 279 280 #define SB_RANK_CFG_A 0x0328 281 282 #define IB_RANK_CFG_A 0x0320 283 284 /* 285 * sbridge structs 286 */ 287 288 #define NUM_CHANNELS 6 /* Max channels per MC */ 289 #define MAX_DIMMS 3 /* Max DIMMS per channel */ 290 #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */ 291 #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */ 292 #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */ 293 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ 294 295 enum type { 296 SANDY_BRIDGE, 297 IVY_BRIDGE, 298 HASWELL, 299 BROADWELL, 300 KNIGHTS_LANDING, 301 }; 302 303 enum domain { 304 IMC0 = 0, 305 IMC1, 306 SOCK, 307 }; 308 309 enum mirroring_mode { 310 NON_MIRRORING, 311 ADDR_RANGE_MIRRORING, 312 FULL_MIRRORING, 313 }; 314 315 struct sbridge_pvt; 316 struct sbridge_info { 317 enum type type; 318 u32 mcmtr; 319 u32 rankcfgr; 320 u64 (*get_tolm)(struct sbridge_pvt *pvt); 321 u64 (*get_tohm)(struct sbridge_pvt *pvt); 322 u64 (*rir_limit)(u32 reg); 323 u64 (*sad_limit)(u32 reg); 324 u32 (*interleave_mode)(u32 reg); 325 u32 (*dram_attr)(u32 reg); 326 const u32 *dram_rule; 327 const u32 *interleave_list; 328 const struct interleave_pkg *interleave_pkg; 329 u8 max_sad; 330 u8 (*get_node_id)(struct sbridge_pvt *pvt); 331 u8 (*get_ha)(u8 bank); 332 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); 333 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); 334 struct pci_dev *pci_vtd; 335 }; 336 337 struct sbridge_channel { 338 u32 ranks; 339 u32 dimms; 340 struct dimm { 341 u32 rowbits; 342 u32 colbits; 343 u32 bank_xor_enable; 344 u32 amap_fine; 345 } dimm[MAX_DIMMS]; 346 }; 347 348 struct pci_id_descr { 349 int dev_id; 350 int optional; 351 enum domain dom; 352 }; 353 354 struct pci_id_table { 355 const struct pci_id_descr *descr; 356 int n_devs_per_imc; 357 int n_devs_per_sock; 358 int n_imcs_per_sock; 359 enum type type; 360 }; 361 362 struct sbridge_dev { 363 struct list_head list; 364 int seg; 365 u8 bus, mc; 366 u8 node_id, source_id; 367 enum domain dom; 368 int n_devs; 369 int i_devs; 370 struct mem_ctl_info *mci; 371 struct pci_dev *pdev[] __counted_by(n_devs); 372 }; 373 374 struct knl_pvt { 375 struct pci_dev *pci_cha[KNL_MAX_CHAS]; 376 struct pci_dev *pci_channel[KNL_MAX_CHANNELS]; 377 struct pci_dev *pci_mc0; 378 struct pci_dev *pci_mc1; 379 struct pci_dev *pci_mc0_misc; 380 struct pci_dev *pci_mc1_misc; 381 struct pci_dev *pci_mc_info; /* tolm, tohm */ 382 }; 383 384 struct sbridge_pvt { 385 /* Devices per socket */ 386 struct pci_dev *pci_ddrio; 387 struct pci_dev *pci_sad0, *pci_sad1; 388 struct pci_dev *pci_br0, *pci_br1; 389 /* Devices per memory controller */ 390 struct pci_dev *pci_ha, *pci_ta, *pci_ras; 391 struct pci_dev *pci_tad[NUM_CHANNELS]; 392 393 struct sbridge_dev *sbridge_dev; 394 395 struct sbridge_info info; 396 struct sbridge_channel channel[NUM_CHANNELS]; 397 398 /* Memory type detection */ 399 bool is_cur_addr_mirrored, is_lockstep, is_close_pg; 400 bool is_chan_hash; 401 enum mirroring_mode mirror_mode; 402 403 /* Memory description */ 404 u64 tolm, tohm; 405 struct knl_pvt knl; 406 }; 407 408 #define PCI_DESCR(device_id, opt, domain) \ 409 .dev_id = (device_id), \ 410 .optional = opt, \ 411 .dom = domain 412 413 static const struct pci_id_descr pci_dev_descr_sbridge[] = { 414 /* Processor Home Agent */ 415 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) }, 416 417 /* Memory controller */ 418 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) }, 419 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) }, 420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) }, 421 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) }, 422 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) }, 423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) }, 424 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) }, 425 426 /* System Address Decoder */ 427 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) }, 428 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) }, 429 430 /* Broadcast Registers */ 431 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) }, 432 }; 433 434 #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \ 435 .descr = A, \ 436 .n_devs_per_imc = N, \ 437 .n_devs_per_sock = ARRAY_SIZE(A), \ 438 .n_imcs_per_sock = M, \ 439 .type = T \ 440 } 441 442 static const struct pci_id_table pci_dev_descr_sbridge_table[] = { 443 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE), 444 { NULL, } 445 }; 446 447 /* This changes depending if 1HA or 2HA: 448 * 1HA: 449 * 0x0eb8 (17.0) is DDRIO0 450 * 2HA: 451 * 0x0ebc (17.4) is DDRIO0 452 */ 453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc 455 456 /* pci ids */ 457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa 461 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab 462 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac 463 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead 464 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 465 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 466 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca 467 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 468 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 469 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 470 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a 471 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b 472 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c 473 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d 474 475 static const struct pci_id_descr pci_dev_descr_ibridge[] = { 476 /* Processor Home Agent */ 477 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) }, 478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) }, 479 480 /* Memory controller */ 481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) }, 482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) }, 483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) }, 484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) }, 485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) }, 486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) }, 487 488 /* Optional, mode 2HA */ 489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) }, 490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) }, 491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) }, 492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) }, 493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) }, 494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) }, 495 496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) }, 497 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) }, 498 499 /* System Address Decoder */ 500 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) }, 501 502 /* Broadcast Registers */ 503 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) }, 504 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) }, 505 506 }; 507 508 static const struct pci_id_table pci_dev_descr_ibridge_table[] = { 509 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE), 510 { NULL, } 511 }; 512 513 /* Haswell support */ 514 /* EN processor: 515 * - 1 IMC 516 * - 3 DDR3 channels, 2 DPC per channel 517 * EP processor: 518 * - 1 or 2 IMC 519 * - 4 DDR4 channels, 3 DPC per channel 520 * EP 4S processor: 521 * - 2 IMC 522 * - 4 DDR4 channels, 3 DPC per channel 523 * EX processor: 524 * - 2 IMC 525 * - each IMC interfaces with a SMI 2 channel 526 * - each SMI channel interfaces with a scalable memory buffer 527 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 528 */ 529 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ 530 #define HASWELL_HASYSDEFEATURE2 0x84 531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71 536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79 538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc 539 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd 540 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa 541 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab 542 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac 543 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad 544 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a 545 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b 546 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c 547 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d 548 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd 549 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf 550 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9 551 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb 552 static const struct pci_id_descr pci_dev_descr_haswell[] = { 553 /* first item must be the HA */ 554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) }, 555 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) }, 556 557 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) }, 558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) }, 559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) }, 560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) }, 561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) }, 562 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) }, 563 564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) }, 565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) }, 566 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) }, 567 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) }, 568 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) }, 569 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) }, 570 571 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) }, 572 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) }, 573 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) }, 574 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) }, 575 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) }, 576 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) }, 577 }; 578 579 static const struct pci_id_table pci_dev_descr_haswell_table[] = { 580 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL), 581 { NULL, } 582 }; 583 584 /* Knight's Landing Support */ 585 /* 586 * KNL's memory channels are swizzled between memory controllers. 587 * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2 588 */ 589 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3) 590 591 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ 592 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840 593 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ 594 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843 595 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ 596 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844 597 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ 598 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a 599 /* SAD target - 1-29-1 (1 of these) */ 600 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b 601 /* Caching / Home Agent */ 602 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c 603 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */ 604 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810 605 606 /* 607 * KNL differs from SB, IB, and Haswell in that it has multiple 608 * instances of the same device with the same device ID, so we handle that 609 * by creating as many copies in the table as we expect to find. 610 * (Like device ID must be grouped together.) 611 */ 612 613 static const struct pci_id_descr pci_dev_descr_knl[] = { 614 [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)}, 615 [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) }, 616 [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) }, 617 [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) }, 618 [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) }, 619 [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) }, 620 [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) }, 621 }; 622 623 static const struct pci_id_table pci_dev_descr_knl_table[] = { 624 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING), 625 { NULL, } 626 }; 627 628 /* 629 * Broadwell support 630 * 631 * DE processor: 632 * - 1 IMC 633 * - 2 DDR3 channels, 2 DPC per channel 634 * EP processor: 635 * - 1 or 2 IMC 636 * - 4 DDR4 channels, 3 DPC per channel 637 * EP 4S processor: 638 * - 2 IMC 639 * - 4 DDR4 channels, 3 DPC per channel 640 * EX processor: 641 * - 2 IMC 642 * - each IMC interfaces with a SMI 2 channel 643 * - each SMI channel interfaces with a scalable memory buffer 644 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC 645 */ 646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71 651 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 652 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79 653 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc 654 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd 655 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa 656 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab 657 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac 658 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad 659 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a 660 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b 661 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c 662 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d 663 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf 664 665 static const struct pci_id_descr pci_dev_descr_broadwell[] = { 666 /* first item must be the HA */ 667 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) }, 668 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) }, 669 670 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) }, 671 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) }, 672 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) }, 673 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) }, 674 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) }, 675 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) }, 676 677 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) }, 678 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) }, 679 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) }, 680 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) }, 681 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) }, 682 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) }, 683 684 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) }, 685 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) }, 686 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) }, 687 }; 688 689 static const struct pci_id_table pci_dev_descr_broadwell_table[] = { 690 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL), 691 { NULL, } 692 }; 693 694 695 /**************************************************************************** 696 Ancillary status routines 697 ****************************************************************************/ 698 699 static inline int numrank(enum type type, u32 mtr) 700 { 701 int ranks = (1 << RANK_CNT_BITS(mtr)); 702 int max = 4; 703 704 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING) 705 max = 8; 706 707 if (ranks > max) { 708 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", 709 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); 710 return -EINVAL; 711 } 712 713 return ranks; 714 } 715 716 static inline int numrow(u32 mtr) 717 { 718 int rows = (RANK_WIDTH_BITS(mtr) + 12); 719 720 if (rows < 13 || rows > 18) { 721 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", 722 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); 723 return -EINVAL; 724 } 725 726 return 1 << rows; 727 } 728 729 static inline int numcol(u32 mtr) 730 { 731 int cols = (COL_WIDTH_BITS(mtr) + 10); 732 733 if (cols > 12) { 734 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", 735 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); 736 return -EINVAL; 737 } 738 739 return 1 << cols; 740 } 741 742 static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom, 743 int multi_bus, 744 struct sbridge_dev *prev) 745 { 746 struct sbridge_dev *sbridge_dev; 747 748 /* 749 * If we have devices scattered across several busses that pertain 750 * to the same memory controller, we'll lump them all together. 751 */ 752 if (multi_bus) { 753 return list_first_entry_or_null(&sbridge_edac_list, 754 struct sbridge_dev, list); 755 } 756 757 sbridge_dev = list_entry(prev ? prev->list.next 758 : sbridge_edac_list.next, struct sbridge_dev, list); 759 760 list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) { 761 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && 762 (dom == SOCK || dom == sbridge_dev->dom)) 763 return sbridge_dev; 764 } 765 766 return NULL; 767 } 768 769 static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom, 770 const struct pci_id_table *table) 771 { 772 struct sbridge_dev *sbridge_dev; 773 774 sbridge_dev = kzalloc_flex(*sbridge_dev, pdev, table->n_devs_per_imc); 775 if (!sbridge_dev) 776 return NULL; 777 778 sbridge_dev->n_devs = table->n_devs_per_imc; 779 sbridge_dev->seg = seg; 780 sbridge_dev->bus = bus; 781 sbridge_dev->dom = dom; 782 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); 783 784 return sbridge_dev; 785 } 786 787 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) 788 { 789 list_del(&sbridge_dev->list); 790 kfree(sbridge_dev); 791 } 792 793 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) 794 { 795 u32 reg; 796 797 /* Address range is 32:28 */ 798 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); 799 return GET_TOLM(reg); 800 } 801 802 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) 803 { 804 u32 reg; 805 806 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); 807 return GET_TOHM(reg); 808 } 809 810 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) 811 { 812 u32 reg; 813 814 pci_read_config_dword(pvt->pci_br1, TOLM, ®); 815 816 return GET_TOLM(reg); 817 } 818 819 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) 820 { 821 u32 reg; 822 823 pci_read_config_dword(pvt->pci_br1, TOHM, ®); 824 825 return GET_TOHM(reg); 826 } 827 828 static u64 rir_limit(u32 reg) 829 { 830 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; 831 } 832 833 static u64 sad_limit(u32 reg) 834 { 835 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; 836 } 837 838 static u32 interleave_mode(u32 reg) 839 { 840 return GET_BITFIELD(reg, 1, 1); 841 } 842 843 static u32 dram_attr(u32 reg) 844 { 845 return GET_BITFIELD(reg, 2, 3); 846 } 847 848 static u64 knl_sad_limit(u32 reg) 849 { 850 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff; 851 } 852 853 static u32 knl_interleave_mode(u32 reg) 854 { 855 return GET_BITFIELD(reg, 1, 2); 856 } 857 858 static const char * const knl_intlv_mode[] = { 859 "[8:6]", "[10:8]", "[14:12]", "[32:30]" 860 }; 861 862 static const char *get_intlv_mode_str(u32 reg, enum type t) 863 { 864 if (t == KNIGHTS_LANDING) 865 return knl_intlv_mode[knl_interleave_mode(reg)]; 866 else 867 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]"; 868 } 869 870 static u32 dram_attr_knl(u32 reg) 871 { 872 return GET_BITFIELD(reg, 3, 4); 873 } 874 875 876 static enum mem_type get_memory_type(struct sbridge_pvt *pvt) 877 { 878 u32 reg; 879 enum mem_type mtype; 880 881 if (pvt->pci_ddrio) { 882 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, 883 ®); 884 if (GET_BITFIELD(reg, 11, 11)) 885 /* FIXME: Can also be LRDIMM */ 886 mtype = MEM_RDDR3; 887 else 888 mtype = MEM_DDR3; 889 } else 890 mtype = MEM_UNKNOWN; 891 892 return mtype; 893 } 894 895 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) 896 { 897 u32 reg; 898 bool registered = false; 899 enum mem_type mtype = MEM_UNKNOWN; 900 901 if (!pvt->pci_ddrio) 902 goto out; 903 904 pci_read_config_dword(pvt->pci_ddrio, 905 HASWELL_DDRCRCLKCONTROLS, ®); 906 /* Is_Rdimm */ 907 if (GET_BITFIELD(reg, 16, 16)) 908 registered = true; 909 910 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); 911 if (GET_BITFIELD(reg, 14, 14)) { 912 if (registered) 913 mtype = MEM_RDDR4; 914 else 915 mtype = MEM_DDR4; 916 } else { 917 if (registered) 918 mtype = MEM_RDDR3; 919 else 920 mtype = MEM_DDR3; 921 } 922 923 out: 924 return mtype; 925 } 926 927 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) 928 { 929 /* for KNL value is fixed */ 930 return DEV_X16; 931 } 932 933 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) 934 { 935 /* there's no way to figure out */ 936 return DEV_UNKNOWN; 937 } 938 939 static enum dev_type __ibridge_get_width(u32 mtr) 940 { 941 enum dev_type type = DEV_UNKNOWN; 942 943 switch (mtr) { 944 case 2: 945 type = DEV_X16; 946 break; 947 case 1: 948 type = DEV_X8; 949 break; 950 case 0: 951 type = DEV_X4; 952 break; 953 } 954 955 return type; 956 } 957 958 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) 959 { 960 /* 961 * ddr3_width on the documentation but also valid for DDR4 on 962 * Haswell 963 */ 964 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); 965 } 966 967 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) 968 { 969 /* ddr3_width on the documentation but also valid for DDR4 */ 970 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); 971 } 972 973 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) 974 { 975 /* DDR4 RDIMMS and LRDIMMS are supported */ 976 return MEM_RDDR4; 977 } 978 979 static u8 get_node_id(struct sbridge_pvt *pvt) 980 { 981 u32 reg; 982 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); 983 return GET_BITFIELD(reg, 0, 2); 984 } 985 986 static u8 haswell_get_node_id(struct sbridge_pvt *pvt) 987 { 988 u32 reg; 989 990 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); 991 return GET_BITFIELD(reg, 0, 3); 992 } 993 994 static u8 knl_get_node_id(struct sbridge_pvt *pvt) 995 { 996 u32 reg; 997 998 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); 999 return GET_BITFIELD(reg, 0, 2); 1000 } 1001 1002 /* 1003 * Use the reporting bank number to determine which memory 1004 * controller (also known as "ha" for "home agent"). Sandy 1005 * Bridge only has one memory controller per socket, so the 1006 * answer is always zero. 1007 */ 1008 static u8 sbridge_get_ha(u8 bank) 1009 { 1010 return 0; 1011 } 1012 1013 /* 1014 * On Ivy Bridge, Haswell and Broadwell the error may be in a 1015 * home agent bank (7, 8), or one of the per-channel memory 1016 * controller banks (9 .. 16). 1017 */ 1018 static u8 ibridge_get_ha(u8 bank) 1019 { 1020 switch (bank) { 1021 case 7 ... 8: 1022 return bank - 7; 1023 case 9 ... 16: 1024 return (bank - 9) / 4; 1025 default: 1026 return 0xff; 1027 } 1028 } 1029 1030 /* Not used, but included for safety/symmetry */ 1031 static u8 knl_get_ha(u8 bank) 1032 { 1033 return 0xff; 1034 } 1035 1036 static u64 haswell_get_tolm(struct sbridge_pvt *pvt) 1037 { 1038 u32 reg; 1039 1040 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); 1041 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; 1042 } 1043 1044 static u64 haswell_get_tohm(struct sbridge_pvt *pvt) 1045 { 1046 u64 rc; 1047 u32 reg; 1048 1049 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); 1050 rc = GET_BITFIELD(reg, 26, 31); 1051 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); 1052 rc = ((reg << 6) | rc) << 26; 1053 1054 return rc | 0x3ffffff; 1055 } 1056 1057 static u64 knl_get_tolm(struct sbridge_pvt *pvt) 1058 { 1059 u32 reg; 1060 1061 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); 1062 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; 1063 } 1064 1065 static u64 knl_get_tohm(struct sbridge_pvt *pvt) 1066 { 1067 u64 rc; 1068 u32 reg_lo, reg_hi; 1069 1070 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); 1071 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); 1072 rc = ((u64)reg_hi << 32) | reg_lo; 1073 return rc | 0x3ffffff; 1074 } 1075 1076 1077 static u64 haswell_rir_limit(u32 reg) 1078 { 1079 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; 1080 } 1081 1082 static inline u8 sad_pkg_socket(u8 pkg) 1083 { 1084 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ 1085 return ((pkg >> 3) << 2) | (pkg & 0x3); 1086 } 1087 1088 static inline u8 sad_pkg_ha(u8 pkg) 1089 { 1090 return (pkg >> 2) & 0x1; 1091 } 1092 1093 static int haswell_chan_hash(int idx, u64 addr) 1094 { 1095 int i; 1096 1097 /* 1098 * XOR even bits from 12:26 to bit0 of idx, 1099 * odd bits from 13:27 to bit1 1100 */ 1101 for (i = 12; i < 28; i += 2) 1102 idx ^= (addr >> i) & 3; 1103 1104 return idx; 1105 } 1106 1107 /* Low bits of TAD limit, and some metadata. */ 1108 static const u32 knl_tad_dram_limit_lo[] = { 1109 0x400, 0x500, 0x600, 0x700, 1110 0x800, 0x900, 0xa00, 0xb00, 1111 }; 1112 1113 /* Low bits of TAD offset. */ 1114 static const u32 knl_tad_dram_offset_lo[] = { 1115 0x404, 0x504, 0x604, 0x704, 1116 0x804, 0x904, 0xa04, 0xb04, 1117 }; 1118 1119 /* High 16 bits of TAD limit and offset. */ 1120 static const u32 knl_tad_dram_hi[] = { 1121 0x408, 0x508, 0x608, 0x708, 1122 0x808, 0x908, 0xa08, 0xb08, 1123 }; 1124 1125 /* Number of ways a tad entry is interleaved. */ 1126 static const u32 knl_tad_ways[] = { 1127 8, 6, 4, 3, 2, 1, 1128 }; 1129 1130 /* 1131 * Retrieve the n'th Target Address Decode table entry 1132 * from the memory controller's TAD table. 1133 * 1134 * @pvt: driver private data 1135 * @entry: which entry you want to retrieve 1136 * @mc: which memory controller (0 or 1) 1137 * @offset: output tad range offset 1138 * @limit: output address of first byte above tad range 1139 * @ways: output number of interleave ways 1140 * 1141 * The offset value has curious semantics. It's a sort of running total 1142 * of the sizes of all the memory regions that aren't mapped in this 1143 * tad table. 1144 */ 1145 static int knl_get_tad(const struct sbridge_pvt *pvt, 1146 const int entry, 1147 const int mc, 1148 u64 *offset, 1149 u64 *limit, 1150 int *ways) 1151 { 1152 u32 reg_limit_lo, reg_offset_lo, reg_hi; 1153 struct pci_dev *pci_mc; 1154 int way_id; 1155 1156 switch (mc) { 1157 case 0: 1158 pci_mc = pvt->knl.pci_mc0; 1159 break; 1160 case 1: 1161 pci_mc = pvt->knl.pci_mc1; 1162 break; 1163 default: 1164 WARN_ON(1); 1165 return -EINVAL; 1166 } 1167 1168 pci_read_config_dword(pci_mc, 1169 knl_tad_dram_limit_lo[entry], ®_limit_lo); 1170 pci_read_config_dword(pci_mc, 1171 knl_tad_dram_offset_lo[entry], ®_offset_lo); 1172 pci_read_config_dword(pci_mc, 1173 knl_tad_dram_hi[entry], ®_hi); 1174 1175 /* Is this TAD entry enabled? */ 1176 if (!GET_BITFIELD(reg_limit_lo, 0, 0)) 1177 return -ENODEV; 1178 1179 way_id = GET_BITFIELD(reg_limit_lo, 3, 5); 1180 1181 if (way_id < ARRAY_SIZE(knl_tad_ways)) { 1182 *ways = knl_tad_ways[way_id]; 1183 } else { 1184 *ways = 0; 1185 sbridge_printk(KERN_ERR, 1186 "Unexpected value %d in mc_tad_limit_lo wayness field\n", 1187 way_id); 1188 return -ENODEV; 1189 } 1190 1191 /* 1192 * The least significant 6 bits of base and limit are truncated. 1193 * For limit, we fill the missing bits with 1s. 1194 */ 1195 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) | 1196 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32); 1197 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 | 1198 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32); 1199 1200 return 0; 1201 } 1202 1203 /* Determine which memory controller is responsible for a given channel. */ 1204 static int knl_channel_mc(int channel) 1205 { 1206 WARN_ON(channel < 0 || channel >= 6); 1207 1208 return channel < 3 ? 1 : 0; 1209 } 1210 1211 /* 1212 * Get the Nth entry from EDC_ROUTE_TABLE register. 1213 * (This is the per-tile mapping of logical interleave targets to 1214 * physical EDC modules.) 1215 * 1216 * entry 0: 0:2 1217 * 1: 3:5 1218 * 2: 6:8 1219 * 3: 9:11 1220 * 4: 12:14 1221 * 5: 15:17 1222 * 6: 18:20 1223 * 7: 21:23 1224 * reserved: 24:31 1225 */ 1226 static u32 knl_get_edc_route(int entry, u32 reg) 1227 { 1228 WARN_ON(entry >= KNL_MAX_EDCS); 1229 return GET_BITFIELD(reg, entry*3, (entry*3)+2); 1230 } 1231 1232 /* 1233 * Get the Nth entry from MC_ROUTE_TABLE register. 1234 * (This is the per-tile mapping of logical interleave targets to 1235 * physical DRAM channels modules.) 1236 * 1237 * entry 0: mc 0:2 channel 18:19 1238 * 1: mc 3:5 channel 20:21 1239 * 2: mc 6:8 channel 22:23 1240 * 3: mc 9:11 channel 24:25 1241 * 4: mc 12:14 channel 26:27 1242 * 5: mc 15:17 channel 28:29 1243 * reserved: 30:31 1244 * 1245 * Though we have 3 bits to identify the MC, we should only see 1246 * the values 0 or 1. 1247 */ 1248 1249 static u32 knl_get_mc_route(int entry, u32 reg) 1250 { 1251 int mc, chan; 1252 1253 WARN_ON(entry >= KNL_MAX_CHANNELS); 1254 1255 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2); 1256 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1); 1257 1258 return knl_channel_remap(mc, chan); 1259 } 1260 1261 /* 1262 * Render the EDC_ROUTE register in human-readable form. 1263 * Output string s should be at least KNL_MAX_EDCS*2 bytes. 1264 */ 1265 static void knl_show_edc_route(u32 reg, char *s) 1266 { 1267 int i; 1268 1269 for (i = 0; i < KNL_MAX_EDCS; i++) { 1270 s[i*2] = knl_get_edc_route(i, reg) + '0'; 1271 s[i*2+1] = '-'; 1272 } 1273 1274 s[KNL_MAX_EDCS*2 - 1] = '\0'; 1275 } 1276 1277 /* 1278 * Render the MC_ROUTE register in human-readable form. 1279 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes. 1280 */ 1281 static void knl_show_mc_route(u32 reg, char *s) 1282 { 1283 int i; 1284 1285 for (i = 0; i < KNL_MAX_CHANNELS; i++) { 1286 s[i*2] = knl_get_mc_route(i, reg) + '0'; 1287 s[i*2+1] = '-'; 1288 } 1289 1290 s[KNL_MAX_CHANNELS*2 - 1] = '\0'; 1291 } 1292 1293 #define KNL_EDC_ROUTE 0xb8 1294 #define KNL_MC_ROUTE 0xb4 1295 1296 /* Is this dram rule backed by regular DRAM in flat mode? */ 1297 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29) 1298 1299 /* Is this dram rule cached? */ 1300 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) 1301 1302 /* Is this rule backed by edc ? */ 1303 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29) 1304 1305 /* Is this rule backed by DRAM, cacheable in EDRAM? */ 1306 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) 1307 1308 /* Is this rule mod3? */ 1309 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27) 1310 1311 /* 1312 * Figure out how big our RAM modules are. 1313 * 1314 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we 1315 * have to figure this out from the SAD rules, interleave lists, route tables, 1316 * and TAD rules. 1317 * 1318 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to 1319 * inspect the TAD rules to figure out how large the SAD regions really are. 1320 * 1321 * When we know the real size of a SAD region and how many ways it's 1322 * interleaved, we know the individual contribution of each channel to 1323 * TAD is size/ways. 1324 * 1325 * Finally, we have to check whether each channel participates in each SAD 1326 * region. 1327 * 1328 * Fortunately, KNL only supports one DIMM per channel, so once we know how 1329 * much memory the channel uses, we know the DIMM is at least that large. 1330 * (The BIOS might possibly choose not to map all available memory, in which 1331 * case we will underreport the size of the DIMM.) 1332 * 1333 * In theory, we could try to determine the EDC sizes as well, but that would 1334 * only work in flat mode, not in cache mode. 1335 * 1336 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS 1337 * elements) 1338 */ 1339 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) 1340 { 1341 u64 sad_base, sad_limit = 0; 1342 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace; 1343 int sad_rule = 0; 1344 int tad_rule = 0; 1345 int intrlv_ways, tad_ways; 1346 u32 first_pkg, pkg; 1347 int i; 1348 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */ 1349 u32 dram_rule, interleave_reg; 1350 u32 mc_route_reg[KNL_MAX_CHAS]; 1351 u32 edc_route_reg[KNL_MAX_CHAS]; 1352 int edram_only; 1353 char edc_route_string[KNL_MAX_EDCS*2]; 1354 char mc_route_string[KNL_MAX_CHANNELS*2]; 1355 int cur_reg_start; 1356 int mc; 1357 int channel; 1358 int participants[KNL_MAX_CHANNELS]; 1359 1360 for (i = 0; i < KNL_MAX_CHANNELS; i++) 1361 mc_sizes[i] = 0; 1362 1363 /* Read the EDC route table in each CHA. */ 1364 cur_reg_start = 0; 1365 for (i = 0; i < KNL_MAX_CHAS; i++) { 1366 pci_read_config_dword(pvt->knl.pci_cha[i], 1367 KNL_EDC_ROUTE, &edc_route_reg[i]); 1368 1369 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { 1370 knl_show_edc_route(edc_route_reg[i-1], 1371 edc_route_string); 1372 if (cur_reg_start == i-1) 1373 edac_dbg(0, "edc route table for CHA %d: %s\n", 1374 cur_reg_start, edc_route_string); 1375 else 1376 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", 1377 cur_reg_start, i-1, edc_route_string); 1378 cur_reg_start = i; 1379 } 1380 } 1381 knl_show_edc_route(edc_route_reg[i-1], edc_route_string); 1382 if (cur_reg_start == i-1) 1383 edac_dbg(0, "edc route table for CHA %d: %s\n", 1384 cur_reg_start, edc_route_string); 1385 else 1386 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", 1387 cur_reg_start, i-1, edc_route_string); 1388 1389 /* Read the MC route table in each CHA. */ 1390 cur_reg_start = 0; 1391 for (i = 0; i < KNL_MAX_CHAS; i++) { 1392 pci_read_config_dword(pvt->knl.pci_cha[i], 1393 KNL_MC_ROUTE, &mc_route_reg[i]); 1394 1395 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { 1396 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); 1397 if (cur_reg_start == i-1) 1398 edac_dbg(0, "mc route table for CHA %d: %s\n", 1399 cur_reg_start, mc_route_string); 1400 else 1401 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", 1402 cur_reg_start, i-1, mc_route_string); 1403 cur_reg_start = i; 1404 } 1405 } 1406 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); 1407 if (cur_reg_start == i-1) 1408 edac_dbg(0, "mc route table for CHA %d: %s\n", 1409 cur_reg_start, mc_route_string); 1410 else 1411 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", 1412 cur_reg_start, i-1, mc_route_string); 1413 1414 /* Process DRAM rules */ 1415 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { 1416 /* previous limit becomes the new base */ 1417 sad_base = sad_limit; 1418 1419 pci_read_config_dword(pvt->pci_sad0, 1420 pvt->info.dram_rule[sad_rule], &dram_rule); 1421 1422 if (!DRAM_RULE_ENABLE(dram_rule)) 1423 break; 1424 1425 edram_only = KNL_EDRAM_ONLY(dram_rule); 1426 1427 sad_limit = pvt->info.sad_limit(dram_rule)+1; 1428 1429 pci_read_config_dword(pvt->pci_sad0, 1430 pvt->info.interleave_list[sad_rule], &interleave_reg); 1431 1432 /* 1433 * Find out how many ways this dram rule is interleaved. 1434 * We stop when we see the first channel again. 1435 */ 1436 first_pkg = sad_pkg(pvt->info.interleave_pkg, 1437 interleave_reg, 0); 1438 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) { 1439 pkg = sad_pkg(pvt->info.interleave_pkg, 1440 interleave_reg, intrlv_ways); 1441 1442 if ((pkg & 0x8) == 0) { 1443 /* 1444 * 0 bit means memory is non-local, 1445 * which KNL doesn't support 1446 */ 1447 edac_dbg(0, "Unexpected interleave target %d\n", 1448 pkg); 1449 return -1; 1450 } 1451 1452 if (pkg == first_pkg) 1453 break; 1454 } 1455 if (KNL_MOD3(dram_rule)) 1456 intrlv_ways *= 3; 1457 1458 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", 1459 sad_rule, 1460 sad_base, 1461 sad_limit, 1462 intrlv_ways, 1463 edram_only ? ", EDRAM" : ""); 1464 1465 /* 1466 * Find out how big the SAD region really is by iterating 1467 * over TAD tables (SAD regions may contain holes). 1468 * Each memory controller might have a different TAD table, so 1469 * we have to look at both. 1470 * 1471 * Livespace is the memory that's mapped in this TAD table, 1472 * deadspace is the holes (this could be the MMIO hole, or it 1473 * could be memory that's mapped by the other TAD table but 1474 * not this one). 1475 */ 1476 for (mc = 0; mc < 2; mc++) { 1477 sad_actual_size[mc] = 0; 1478 tad_livespace = 0; 1479 for (tad_rule = 0; 1480 tad_rule < ARRAY_SIZE( 1481 knl_tad_dram_limit_lo); 1482 tad_rule++) { 1483 if (knl_get_tad(pvt, 1484 tad_rule, 1485 mc, 1486 &tad_deadspace, 1487 &tad_limit, 1488 &tad_ways)) 1489 break; 1490 1491 tad_size = (tad_limit+1) - 1492 (tad_livespace + tad_deadspace); 1493 tad_livespace += tad_size; 1494 tad_base = (tad_limit+1) - tad_size; 1495 1496 if (tad_base < sad_base) { 1497 if (tad_limit > sad_base) 1498 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n"); 1499 } else if (tad_base < sad_limit) { 1500 if (tad_limit+1 > sad_limit) { 1501 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n"); 1502 } else { 1503 /* TAD region is completely inside SAD region */ 1504 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", 1505 tad_rule, tad_base, 1506 tad_limit, tad_size, 1507 mc); 1508 sad_actual_size[mc] += tad_size; 1509 } 1510 } 1511 } 1512 } 1513 1514 for (mc = 0; mc < 2; mc++) { 1515 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n", 1516 mc, sad_actual_size[mc], sad_actual_size[mc]); 1517 } 1518 1519 /* Ignore EDRAM rule */ 1520 if (edram_only) 1521 continue; 1522 1523 /* Figure out which channels participate in interleave. */ 1524 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) 1525 participants[channel] = 0; 1526 1527 /* For each channel, does at least one CHA have 1528 * this channel mapped to the given target? 1529 */ 1530 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { 1531 int target; 1532 int cha; 1533 1534 for (target = 0; target < KNL_MAX_CHANNELS; target++) { 1535 for (cha = 0; cha < KNL_MAX_CHAS; cha++) { 1536 if (knl_get_mc_route(target, 1537 mc_route_reg[cha]) == channel 1538 && !participants[channel]) { 1539 participants[channel] = 1; 1540 break; 1541 } 1542 } 1543 } 1544 } 1545 1546 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) { 1547 mc = knl_channel_mc(channel); 1548 if (participants[channel]) { 1549 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n", 1550 channel, 1551 sad_actual_size[mc]/intrlv_ways, 1552 sad_rule); 1553 mc_sizes[channel] += 1554 sad_actual_size[mc]/intrlv_ways; 1555 } 1556 } 1557 } 1558 1559 return 0; 1560 } 1561 1562 static void get_source_id(struct mem_ctl_info *mci) 1563 { 1564 struct sbridge_pvt *pvt = mci->pvt_info; 1565 u32 reg; 1566 1567 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || 1568 pvt->info.type == KNIGHTS_LANDING) 1569 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); 1570 else 1571 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); 1572 1573 if (pvt->info.type == KNIGHTS_LANDING) 1574 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); 1575 else 1576 pvt->sbridge_dev->source_id = SOURCE_ID(reg); 1577 } 1578 1579 static int __populate_dimms(struct mem_ctl_info *mci, 1580 u64 knl_mc_sizes[KNL_MAX_CHANNELS], 1581 enum edac_type mode) 1582 { 1583 struct sbridge_pvt *pvt = mci->pvt_info; 1584 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS 1585 : NUM_CHANNELS; 1586 unsigned int i, j, banks, ranks, rows, cols, npages; 1587 struct dimm_info *dimm; 1588 enum mem_type mtype; 1589 u64 size; 1590 1591 mtype = pvt->info.get_memory_type(pvt); 1592 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) 1593 edac_dbg(0, "Memory is registered\n"); 1594 else if (mtype == MEM_UNKNOWN) 1595 edac_dbg(0, "Cannot determine memory type\n"); 1596 else 1597 edac_dbg(0, "Memory is unregistered\n"); 1598 1599 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) 1600 banks = 16; 1601 else 1602 banks = 8; 1603 1604 for (i = 0; i < channels; i++) { 1605 u32 mtr, amap = 0; 1606 1607 int max_dimms_per_channel; 1608 1609 if (pvt->info.type == KNIGHTS_LANDING) { 1610 max_dimms_per_channel = 1; 1611 if (!pvt->knl.pci_channel[i]) 1612 continue; 1613 } else { 1614 max_dimms_per_channel = ARRAY_SIZE(mtr_regs); 1615 if (!pvt->pci_tad[i]) 1616 continue; 1617 pci_read_config_dword(pvt->pci_tad[i], 0x8c, &amap); 1618 } 1619 1620 for (j = 0; j < max_dimms_per_channel; j++) { 1621 dimm = edac_get_dimm(mci, i, j, 0); 1622 if (pvt->info.type == KNIGHTS_LANDING) { 1623 pci_read_config_dword(pvt->knl.pci_channel[i], 1624 knl_mtr_reg, &mtr); 1625 } else { 1626 pci_read_config_dword(pvt->pci_tad[i], 1627 mtr_regs[j], &mtr); 1628 } 1629 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); 1630 1631 if (IS_DIMM_PRESENT(mtr)) { 1632 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { 1633 sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n", 1634 pvt->sbridge_dev->source_id, 1635 pvt->sbridge_dev->dom, i); 1636 return -ENODEV; 1637 } 1638 pvt->channel[i].dimms++; 1639 1640 ranks = numrank(pvt->info.type, mtr); 1641 1642 if (pvt->info.type == KNIGHTS_LANDING) { 1643 /* For DDR4, this is fixed. */ 1644 cols = 1 << 10; 1645 rows = knl_mc_sizes[i] / 1646 ((u64) cols * ranks * banks * 8); 1647 } else { 1648 rows = numrow(mtr); 1649 cols = numcol(mtr); 1650 } 1651 1652 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); 1653 npages = MiB_TO_PAGES(size); 1654 1655 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 1656 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, 1657 size, npages, 1658 banks, ranks, rows, cols); 1659 1660 dimm->nr_pages = npages; 1661 dimm->grain = 32; 1662 dimm->dtype = pvt->info.get_width(pvt, mtr); 1663 dimm->mtype = mtype; 1664 dimm->edac_mode = mode; 1665 pvt->channel[i].dimm[j].rowbits = order_base_2(rows); 1666 pvt->channel[i].dimm[j].colbits = order_base_2(cols); 1667 pvt->channel[i].dimm[j].bank_xor_enable = 1668 GET_BITFIELD(pvt->info.mcmtr, 9, 9); 1669 pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0); 1670 snprintf(dimm->label, sizeof(dimm->label), 1671 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", 1672 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); 1673 } 1674 } 1675 } 1676 1677 return 0; 1678 } 1679 1680 static int get_dimm_config(struct mem_ctl_info *mci) 1681 { 1682 struct sbridge_pvt *pvt = mci->pvt_info; 1683 u64 knl_mc_sizes[KNL_MAX_CHANNELS]; 1684 enum edac_type mode; 1685 u32 reg; 1686 1687 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); 1688 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", 1689 pvt->sbridge_dev->mc, 1690 pvt->sbridge_dev->node_id, 1691 pvt->sbridge_dev->source_id); 1692 1693 /* KNL doesn't support mirroring or lockstep, 1694 * and is always closed page 1695 */ 1696 if (pvt->info.type == KNIGHTS_LANDING) { 1697 mode = EDAC_S4ECD4ED; 1698 pvt->mirror_mode = NON_MIRRORING; 1699 pvt->is_cur_addr_mirrored = false; 1700 1701 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) 1702 return -1; 1703 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { 1704 edac_dbg(0, "Failed to read KNL_MCMTR register\n"); 1705 return -ENODEV; 1706 } 1707 } else { 1708 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { 1709 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { 1710 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n"); 1711 return -ENODEV; 1712 } 1713 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); 1714 if (GET_BITFIELD(reg, 28, 28)) { 1715 pvt->mirror_mode = ADDR_RANGE_MIRRORING; 1716 edac_dbg(0, "Address range partial memory mirroring is enabled\n"); 1717 goto next; 1718 } 1719 } 1720 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { 1721 edac_dbg(0, "Failed to read RASENABLES register\n"); 1722 return -ENODEV; 1723 } 1724 if (IS_MIRROR_ENABLED(reg)) { 1725 pvt->mirror_mode = FULL_MIRRORING; 1726 edac_dbg(0, "Full memory mirroring is enabled\n"); 1727 } else { 1728 pvt->mirror_mode = NON_MIRRORING; 1729 edac_dbg(0, "Memory mirroring is disabled\n"); 1730 } 1731 1732 next: 1733 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { 1734 edac_dbg(0, "Failed to read MCMTR register\n"); 1735 return -ENODEV; 1736 } 1737 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { 1738 edac_dbg(0, "Lockstep is enabled\n"); 1739 mode = EDAC_S8ECD8ED; 1740 pvt->is_lockstep = true; 1741 } else { 1742 edac_dbg(0, "Lockstep is disabled\n"); 1743 mode = EDAC_S4ECD4ED; 1744 pvt->is_lockstep = false; 1745 } 1746 if (IS_CLOSE_PG(pvt->info.mcmtr)) { 1747 edac_dbg(0, "address map is on closed page mode\n"); 1748 pvt->is_close_pg = true; 1749 } else { 1750 edac_dbg(0, "address map is on open page mode\n"); 1751 pvt->is_close_pg = false; 1752 } 1753 } 1754 1755 return __populate_dimms(mci, knl_mc_sizes, mode); 1756 } 1757 1758 static void get_memory_layout(const struct mem_ctl_info *mci) 1759 { 1760 struct sbridge_pvt *pvt = mci->pvt_info; 1761 int i, j, k, n_sads, n_tads, sad_interl; 1762 u32 reg; 1763 u64 limit, prv = 0; 1764 u64 tmp_mb; 1765 u32 gb, mb; 1766 u32 rir_way; 1767 1768 /* 1769 * Step 1) Get TOLM/TOHM ranges 1770 */ 1771 1772 pvt->tolm = pvt->info.get_tolm(pvt); 1773 tmp_mb = (1 + pvt->tolm) >> 20; 1774 1775 gb = div_u64_rem(tmp_mb, 1024, &mb); 1776 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", 1777 gb, (mb*1000)/1024, (u64)pvt->tolm); 1778 1779 /* Address range is already 45:25 */ 1780 pvt->tohm = pvt->info.get_tohm(pvt); 1781 tmp_mb = (1 + pvt->tohm) >> 20; 1782 1783 gb = div_u64_rem(tmp_mb, 1024, &mb); 1784 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", 1785 gb, (mb*1000)/1024, (u64)pvt->tohm); 1786 1787 /* 1788 * Step 2) Get SAD range and SAD Interleave list 1789 * TAD registers contain the interleave wayness. However, it 1790 * seems simpler to just discover it indirectly, with the 1791 * algorithm bellow. 1792 */ 1793 prv = 0; 1794 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { 1795 /* SAD_LIMIT Address range is 45:26 */ 1796 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], 1797 ®); 1798 limit = pvt->info.sad_limit(reg); 1799 1800 if (!DRAM_RULE_ENABLE(reg)) 1801 continue; 1802 1803 if (limit <= prv) 1804 break; 1805 1806 tmp_mb = (limit + 1) >> 20; 1807 gb = div_u64_rem(tmp_mb, 1024, &mb); 1808 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", 1809 n_sads, 1810 show_dram_attr(pvt->info.dram_attr(reg)), 1811 gb, (mb*1000)/1024, 1812 ((u64)tmp_mb) << 20L, 1813 get_intlv_mode_str(reg, pvt->info.type), 1814 reg); 1815 prv = limit; 1816 1817 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 1818 ®); 1819 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); 1820 for (j = 0; j < 8; j++) { 1821 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); 1822 if (j > 0 && sad_interl == pkg) 1823 break; 1824 1825 edac_dbg(0, "SAD#%d, interleave #%d: %d\n", 1826 n_sads, j, pkg); 1827 } 1828 } 1829 1830 if (pvt->info.type == KNIGHTS_LANDING) 1831 return; 1832 1833 /* 1834 * Step 3) Get TAD range 1835 */ 1836 prv = 0; 1837 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 1838 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); 1839 limit = TAD_LIMIT(reg); 1840 if (limit <= prv) 1841 break; 1842 tmp_mb = (limit + 1) >> 20; 1843 1844 gb = div_u64_rem(tmp_mb, 1024, &mb); 1845 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", 1846 n_tads, gb, (mb*1000)/1024, 1847 ((u64)tmp_mb) << 20L, 1848 (u32)(1 << TAD_SOCK(reg)), 1849 (u32)TAD_CH(reg) + 1, 1850 (u32)TAD_TGT0(reg), 1851 (u32)TAD_TGT1(reg), 1852 (u32)TAD_TGT2(reg), 1853 (u32)TAD_TGT3(reg), 1854 reg); 1855 prv = limit; 1856 } 1857 1858 /* 1859 * Step 4) Get TAD offsets, per each channel 1860 */ 1861 for (i = 0; i < NUM_CHANNELS; i++) { 1862 if (!pvt->channel[i].dimms) 1863 continue; 1864 for (j = 0; j < n_tads; j++) { 1865 pci_read_config_dword(pvt->pci_tad[i], 1866 tad_ch_nilv_offset[j], 1867 ®); 1868 tmp_mb = TAD_OFFSET(reg) >> 20; 1869 gb = div_u64_rem(tmp_mb, 1024, &mb); 1870 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", 1871 i, j, 1872 gb, (mb*1000)/1024, 1873 ((u64)tmp_mb) << 20L, 1874 reg); 1875 } 1876 } 1877 1878 /* 1879 * Step 6) Get RIR Wayness/Limit, per each channel 1880 */ 1881 for (i = 0; i < NUM_CHANNELS; i++) { 1882 if (!pvt->channel[i].dimms) 1883 continue; 1884 for (j = 0; j < MAX_RIR_RANGES; j++) { 1885 pci_read_config_dword(pvt->pci_tad[i], 1886 rir_way_limit[j], 1887 ®); 1888 1889 if (!IS_RIR_VALID(reg)) 1890 continue; 1891 1892 tmp_mb = pvt->info.rir_limit(reg) >> 20; 1893 rir_way = 1 << RIR_WAY(reg); 1894 gb = div_u64_rem(tmp_mb, 1024, &mb); 1895 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", 1896 i, j, 1897 gb, (mb*1000)/1024, 1898 ((u64)tmp_mb) << 20L, 1899 rir_way, 1900 reg); 1901 1902 for (k = 0; k < rir_way; k++) { 1903 pci_read_config_dword(pvt->pci_tad[i], 1904 rir_offset[j][k], 1905 ®); 1906 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; 1907 1908 gb = div_u64_rem(tmp_mb, 1024, &mb); 1909 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", 1910 i, j, k, 1911 gb, (mb*1000)/1024, 1912 ((u64)tmp_mb) << 20L, 1913 (u32)RIR_RNK_TGT(pvt->info.type, reg), 1914 reg); 1915 } 1916 } 1917 } 1918 } 1919 1920 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha) 1921 { 1922 struct sbridge_dev *sbridge_dev; 1923 1924 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 1925 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) 1926 return sbridge_dev->mci; 1927 } 1928 return NULL; 1929 } 1930 1931 static u8 sb_close_row[] = { 1932 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 1933 }; 1934 1935 static u8 sb_close_column[] = { 1936 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 1937 }; 1938 1939 static u8 sb_open_row[] = { 1940 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 1941 }; 1942 1943 static u8 sb_open_column[] = { 1944 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 1945 }; 1946 1947 static u8 sb_open_fine_column[] = { 1948 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 1949 }; 1950 1951 static int sb_bits(u64 addr, int nbits, u8 *bits) 1952 { 1953 int i, res = 0; 1954 1955 for (i = 0; i < nbits; i++) 1956 res |= ((addr >> bits[i]) & 1) << i; 1957 return res; 1958 } 1959 1960 static int sb_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) 1961 { 1962 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); 1963 1964 if (do_xor) 1965 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); 1966 1967 return ret; 1968 } 1969 1970 static bool sb_decode_ddr4(struct mem_ctl_info *mci, int ch, u8 rank, 1971 u64 rank_addr, char *msg) 1972 { 1973 int dimmno = 0; 1974 int row, col, bank_address, bank_group; 1975 struct sbridge_pvt *pvt; 1976 u32 bg0 = 0, rowbits = 0, colbits = 0; 1977 u32 amap_fine = 0, bank_xor_enable = 0; 1978 1979 dimmno = (rank < 12) ? rank / 4 : 2; 1980 pvt = mci->pvt_info; 1981 amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine; 1982 bg0 = amap_fine ? 6 : 13; 1983 rowbits = pvt->channel[ch].dimm[dimmno].rowbits; 1984 colbits = pvt->channel[ch].dimm[dimmno].colbits; 1985 bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable; 1986 1987 if (pvt->is_lockstep) { 1988 pr_warn_once("LockStep row/column decode is not supported yet!\n"); 1989 msg[0] = '\0'; 1990 return false; 1991 } 1992 1993 if (pvt->is_close_pg) { 1994 row = sb_bits(rank_addr, rowbits, sb_close_row); 1995 col = sb_bits(rank_addr, colbits, sb_close_column); 1996 col |= 0x400; /* C10 is autoprecharge, always set */ 1997 bank_address = sb_bank_bits(rank_addr, 8, 9, bank_xor_enable, 22, 28); 1998 bank_group = sb_bank_bits(rank_addr, 6, 7, bank_xor_enable, 20, 21); 1999 } else { 2000 row = sb_bits(rank_addr, rowbits, sb_open_row); 2001 if (amap_fine) 2002 col = sb_bits(rank_addr, colbits, sb_open_fine_column); 2003 else 2004 col = sb_bits(rank_addr, colbits, sb_open_column); 2005 bank_address = sb_bank_bits(rank_addr, 18, 19, bank_xor_enable, 22, 23); 2006 bank_group = sb_bank_bits(rank_addr, bg0, 17, bank_xor_enable, 20, 21); 2007 } 2008 2009 row &= (1u << rowbits) - 1; 2010 2011 sprintf(msg, "row:0x%x col:0x%x bank_addr:%d bank_group:%d", 2012 row, col, bank_address, bank_group); 2013 return true; 2014 } 2015 2016 static bool sb_decode_ddr3(struct mem_ctl_info *mci, int ch, u8 rank, 2017 u64 rank_addr, char *msg) 2018 { 2019 pr_warn_once("DDR3 row/column decode not support yet!\n"); 2020 msg[0] = '\0'; 2021 return false; 2022 } 2023 2024 static int get_memory_error_data(struct mem_ctl_info *mci, 2025 u64 addr, 2026 u8 *socket, u8 *ha, 2027 long *channel_mask, 2028 u8 *rank, 2029 char **area_type, char *msg) 2030 { 2031 struct mem_ctl_info *new_mci; 2032 struct sbridge_pvt *pvt = mci->pvt_info; 2033 struct pci_dev *pci_ha; 2034 int n_rir, n_sads, n_tads, sad_way, sck_xch; 2035 int sad_interl, idx, base_ch; 2036 int interleave_mode, shiftup = 0; 2037 unsigned int sad_interleave[MAX_INTERLEAVE]; 2038 u32 reg, dram_rule; 2039 u8 ch_way, sck_way, pkg, sad_ha = 0, rankid = 0; 2040 u32 tad_offset; 2041 u32 rir_way; 2042 u32 mb, gb; 2043 u64 ch_addr, offset, limit = 0, prv = 0; 2044 u64 rank_addr; 2045 enum mem_type mtype; 2046 2047 /* 2048 * Step 0) Check if the address is at special memory ranges 2049 * The check bellow is probably enough to fill all cases where 2050 * the error is not inside a memory, except for the legacy 2051 * range (e. g. VGA addresses). It is unlikely, however, that the 2052 * memory controller would generate an error on that range. 2053 */ 2054 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { 2055 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); 2056 return -EINVAL; 2057 } 2058 if (addr >= (u64)pvt->tohm) { 2059 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); 2060 return -EINVAL; 2061 } 2062 2063 /* 2064 * Step 1) Get socket 2065 */ 2066 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { 2067 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], 2068 ®); 2069 2070 if (!DRAM_RULE_ENABLE(reg)) 2071 continue; 2072 2073 limit = pvt->info.sad_limit(reg); 2074 if (limit <= prv) { 2075 sprintf(msg, "Can't discover the memory socket"); 2076 return -EINVAL; 2077 } 2078 if (addr <= limit) 2079 break; 2080 prv = limit; 2081 } 2082 if (n_sads == pvt->info.max_sad) { 2083 sprintf(msg, "Can't discover the memory socket"); 2084 return -EINVAL; 2085 } 2086 dram_rule = reg; 2087 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); 2088 interleave_mode = pvt->info.interleave_mode(dram_rule); 2089 2090 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], 2091 ®); 2092 2093 if (pvt->info.type == SANDY_BRIDGE) { 2094 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); 2095 for (sad_way = 0; sad_way < 8; sad_way++) { 2096 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); 2097 if (sad_way > 0 && sad_interl == pkg) 2098 break; 2099 sad_interleave[sad_way] = pkg; 2100 edac_dbg(0, "SAD interleave #%d: %d\n", 2101 sad_way, sad_interleave[sad_way]); 2102 } 2103 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", 2104 pvt->sbridge_dev->mc, 2105 n_sads, 2106 addr, 2107 limit, 2108 sad_way + 7, 2109 !interleave_mode ? "" : "XOR[18:16]"); 2110 if (interleave_mode) 2111 idx = ((addr >> 6) ^ (addr >> 16)) & 7; 2112 else 2113 idx = (addr >> 6) & 7; 2114 switch (sad_way) { 2115 case 1: 2116 idx = 0; 2117 break; 2118 case 2: 2119 idx = idx & 1; 2120 break; 2121 case 4: 2122 idx = idx & 3; 2123 break; 2124 case 8: 2125 break; 2126 default: 2127 sprintf(msg, "Can't discover socket interleave"); 2128 return -EINVAL; 2129 } 2130 *socket = sad_interleave[idx]; 2131 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", 2132 idx, sad_way, *socket); 2133 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { 2134 int bits, a7mode = A7MODE(dram_rule); 2135 2136 if (a7mode) { 2137 /* A7 mode swaps P9 with P6 */ 2138 bits = GET_BITFIELD(addr, 7, 8) << 1; 2139 bits |= GET_BITFIELD(addr, 9, 9); 2140 } else 2141 bits = GET_BITFIELD(addr, 6, 8); 2142 2143 if (interleave_mode == 0) { 2144 /* interleave mode will XOR {8,7,6} with {18,17,16} */ 2145 idx = GET_BITFIELD(addr, 16, 18); 2146 idx ^= bits; 2147 } else 2148 idx = bits; 2149 2150 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 2151 *socket = sad_pkg_socket(pkg); 2152 sad_ha = sad_pkg_ha(pkg); 2153 2154 if (a7mode) { 2155 /* MCChanShiftUpEnable */ 2156 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); 2157 shiftup = GET_BITFIELD(reg, 22, 22); 2158 } 2159 2160 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", 2161 idx, *socket, sad_ha, shiftup); 2162 } else { 2163 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ 2164 idx = (addr >> 6) & 7; 2165 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); 2166 *socket = sad_pkg_socket(pkg); 2167 sad_ha = sad_pkg_ha(pkg); 2168 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", 2169 idx, *socket, sad_ha); 2170 } 2171 2172 *ha = sad_ha; 2173 2174 /* 2175 * Move to the proper node structure, in order to access the 2176 * right PCI registers 2177 */ 2178 new_mci = get_mci_for_node_id(*socket, sad_ha); 2179 if (!new_mci) { 2180 sprintf(msg, "Struct for socket #%u wasn't initialized", 2181 *socket); 2182 return -EINVAL; 2183 } 2184 mci = new_mci; 2185 pvt = mci->pvt_info; 2186 2187 /* 2188 * Step 2) Get memory channel 2189 */ 2190 prv = 0; 2191 pci_ha = pvt->pci_ha; 2192 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 2193 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); 2194 limit = TAD_LIMIT(reg); 2195 if (limit <= prv) { 2196 sprintf(msg, "Can't discover the memory channel"); 2197 return -EINVAL; 2198 } 2199 if (addr <= limit) 2200 break; 2201 prv = limit; 2202 } 2203 if (n_tads == MAX_TAD) { 2204 sprintf(msg, "Can't discover the memory channel"); 2205 return -EINVAL; 2206 } 2207 2208 ch_way = TAD_CH(reg) + 1; 2209 sck_way = TAD_SOCK(reg); 2210 2211 if (ch_way == 3) 2212 idx = addr >> 6; 2213 else { 2214 idx = (addr >> (6 + sck_way + shiftup)) & 0x3; 2215 if (pvt->is_chan_hash) 2216 idx = haswell_chan_hash(idx, addr); 2217 } 2218 idx = idx % ch_way; 2219 2220 /* 2221 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? 2222 */ 2223 switch (idx) { 2224 case 0: 2225 base_ch = TAD_TGT0(reg); 2226 break; 2227 case 1: 2228 base_ch = TAD_TGT1(reg); 2229 break; 2230 case 2: 2231 base_ch = TAD_TGT2(reg); 2232 break; 2233 case 3: 2234 base_ch = TAD_TGT3(reg); 2235 break; 2236 default: 2237 sprintf(msg, "Can't discover the TAD target"); 2238 return -EINVAL; 2239 } 2240 *channel_mask = 1 << base_ch; 2241 2242 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); 2243 2244 if (pvt->mirror_mode == FULL_MIRRORING || 2245 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { 2246 *channel_mask |= 1 << ((base_ch + 2) % 4); 2247 switch(ch_way) { 2248 case 2: 2249 case 4: 2250 sck_xch = (1 << sck_way) * (ch_way >> 1); 2251 break; 2252 default: 2253 sprintf(msg, "Invalid mirror set. Can't decode addr"); 2254 return -EINVAL; 2255 } 2256 2257 pvt->is_cur_addr_mirrored = true; 2258 } else { 2259 sck_xch = (1 << sck_way) * ch_way; 2260 pvt->is_cur_addr_mirrored = false; 2261 } 2262 2263 if (pvt->is_lockstep) 2264 *channel_mask |= 1 << ((base_ch + 1) % 4); 2265 2266 offset = TAD_OFFSET(tad_offset); 2267 2268 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", 2269 n_tads, 2270 addr, 2271 limit, 2272 sck_way, 2273 ch_way, 2274 offset, 2275 idx, 2276 base_ch, 2277 *channel_mask); 2278 2279 /* Calculate channel address */ 2280 /* Remove the TAD offset */ 2281 2282 if (offset > addr) { 2283 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", 2284 offset, addr); 2285 return -EINVAL; 2286 } 2287 2288 ch_addr = addr - offset; 2289 ch_addr >>= (6 + shiftup); 2290 ch_addr /= sck_xch; 2291 ch_addr <<= (6 + shiftup); 2292 ch_addr |= addr & ((1 << (6 + shiftup)) - 1); 2293 2294 /* 2295 * Step 3) Decode rank 2296 */ 2297 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { 2298 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); 2299 2300 if (!IS_RIR_VALID(reg)) 2301 continue; 2302 2303 limit = pvt->info.rir_limit(reg); 2304 gb = div_u64_rem(limit >> 20, 1024, &mb); 2305 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", 2306 n_rir, 2307 gb, (mb*1000)/1024, 2308 limit, 2309 1 << RIR_WAY(reg)); 2310 if (ch_addr <= limit) 2311 break; 2312 } 2313 if (n_rir == MAX_RIR_RANGES) { 2314 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", 2315 ch_addr); 2316 return -EINVAL; 2317 } 2318 rir_way = RIR_WAY(reg); 2319 2320 if (pvt->is_close_pg) 2321 idx = (ch_addr >> 6); 2322 else 2323 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ 2324 idx %= 1 << rir_way; 2325 2326 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); 2327 *rank = RIR_RNK_TGT(pvt->info.type, reg); 2328 2329 if (pvt->info.type == BROADWELL) { 2330 if (pvt->is_close_pg) 2331 shiftup = 6; 2332 else 2333 shiftup = 13; 2334 2335 rank_addr = ch_addr >> shiftup; 2336 rank_addr /= (1 << rir_way); 2337 rank_addr <<= shiftup; 2338 rank_addr |= ch_addr & GENMASK_ULL(shiftup - 1, 0); 2339 rank_addr -= RIR_OFFSET(pvt->info.type, reg); 2340 2341 mtype = pvt->info.get_memory_type(pvt); 2342 rankid = *rank; 2343 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) 2344 sb_decode_ddr4(mci, base_ch, rankid, rank_addr, msg); 2345 else 2346 sb_decode_ddr3(mci, base_ch, rankid, rank_addr, msg); 2347 } else { 2348 msg[0] = '\0'; 2349 } 2350 2351 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", 2352 n_rir, 2353 ch_addr, 2354 limit, 2355 rir_way, 2356 idx); 2357 2358 return 0; 2359 } 2360 2361 static int get_memory_error_data_from_mce(struct mem_ctl_info *mci, 2362 const struct mce *m, u8 *socket, 2363 u8 *ha, long *channel_mask, 2364 char *msg) 2365 { 2366 u32 reg, channel = GET_BITFIELD(m->status, 0, 3); 2367 struct mem_ctl_info *new_mci; 2368 struct sbridge_pvt *pvt; 2369 struct pci_dev *pci_ha; 2370 bool tad0; 2371 2372 if (channel >= NUM_CHANNELS) { 2373 sprintf(msg, "Invalid channel 0x%x", channel); 2374 return -EINVAL; 2375 } 2376 2377 pvt = mci->pvt_info; 2378 if (!pvt->info.get_ha) { 2379 sprintf(msg, "No get_ha()"); 2380 return -EINVAL; 2381 } 2382 *ha = pvt->info.get_ha(m->bank); 2383 if (*ha != 0 && *ha != 1) { 2384 sprintf(msg, "Impossible bank %d", m->bank); 2385 return -EINVAL; 2386 } 2387 2388 *socket = m->socketid; 2389 new_mci = get_mci_for_node_id(*socket, *ha); 2390 if (!new_mci) { 2391 strcpy(msg, "mci socket got corrupted!"); 2392 return -EINVAL; 2393 } 2394 2395 pvt = new_mci->pvt_info; 2396 pci_ha = pvt->pci_ha; 2397 pci_read_config_dword(pci_ha, tad_dram_rule[0], ®); 2398 tad0 = m->addr <= TAD_LIMIT(reg); 2399 2400 *channel_mask = 1 << channel; 2401 if (pvt->mirror_mode == FULL_MIRRORING || 2402 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { 2403 *channel_mask |= 1 << ((channel + 2) % 4); 2404 pvt->is_cur_addr_mirrored = true; 2405 } else { 2406 pvt->is_cur_addr_mirrored = false; 2407 } 2408 2409 if (pvt->is_lockstep) 2410 *channel_mask |= 1 << ((channel + 1) % 4); 2411 2412 return 0; 2413 } 2414 2415 /**************************************************************************** 2416 Device initialization routines: put/get, init/exit 2417 ****************************************************************************/ 2418 2419 /* 2420 * sbridge_put_all_devices 'put' all the devices that we have 2421 * reserved via 'get' 2422 */ 2423 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) 2424 { 2425 int i; 2426 2427 edac_dbg(0, "\n"); 2428 for (i = 0; i < sbridge_dev->n_devs; i++) { 2429 struct pci_dev *pdev = sbridge_dev->pdev[i]; 2430 if (!pdev) 2431 continue; 2432 edac_dbg(0, "Removing dev %02x:%02x.%d\n", 2433 pdev->bus->number, 2434 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 2435 pci_dev_put(pdev); 2436 } 2437 } 2438 2439 static void sbridge_put_all_devices(void) 2440 { 2441 struct sbridge_dev *sbridge_dev, *tmp; 2442 2443 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { 2444 sbridge_put_devices(sbridge_dev); 2445 free_sbridge_dev(sbridge_dev); 2446 } 2447 } 2448 2449 static int sbridge_get_onedevice(struct pci_dev **prev, 2450 u8 *num_mc, 2451 const struct pci_id_table *table, 2452 const unsigned devno, 2453 const int multi_bus) 2454 { 2455 struct sbridge_dev *sbridge_dev = NULL; 2456 const struct pci_id_descr *dev_descr = &table->descr[devno]; 2457 struct pci_dev *pdev = NULL; 2458 int seg = 0; 2459 u8 bus = 0; 2460 int i = 0; 2461 2462 sbridge_printk(KERN_DEBUG, 2463 "Seeking for: PCI ID %04x:%04x\n", 2464 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2465 2466 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 2467 dev_descr->dev_id, *prev); 2468 2469 if (!pdev) { 2470 if (*prev) { 2471 *prev = pdev; 2472 return 0; 2473 } 2474 2475 if (dev_descr->optional) 2476 return 0; 2477 2478 /* if the HA wasn't found */ 2479 if (devno == 0) 2480 return -ENODEV; 2481 2482 sbridge_printk(KERN_INFO, 2483 "Device not found: %04x:%04x\n", 2484 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2485 2486 /* End of list, leave */ 2487 return -ENODEV; 2488 } 2489 seg = pci_domain_nr(pdev->bus); 2490 bus = pdev->bus->number; 2491 2492 next_imc: 2493 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, 2494 multi_bus, sbridge_dev); 2495 if (!sbridge_dev) { 2496 /* If the HA1 wasn't found, don't create EDAC second memory controller */ 2497 if (dev_descr->dom == IMC1 && devno != 1) { 2498 edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n", 2499 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2500 pci_dev_put(pdev); 2501 return 0; 2502 } 2503 2504 if (dev_descr->dom == SOCK) 2505 goto out_imc; 2506 2507 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); 2508 if (!sbridge_dev) { 2509 pci_dev_put(pdev); 2510 return -ENOMEM; 2511 } 2512 (*num_mc)++; 2513 } 2514 2515 if (sbridge_dev->pdev[sbridge_dev->i_devs]) { 2516 sbridge_printk(KERN_ERR, 2517 "Duplicated device for %04x:%04x\n", 2518 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2519 pci_dev_put(pdev); 2520 return -ENODEV; 2521 } 2522 2523 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; 2524 2525 /* pdev belongs to more than one IMC, do extra gets */ 2526 if (++i > 1) 2527 pci_dev_get(pdev); 2528 2529 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) 2530 goto next_imc; 2531 2532 out_imc: 2533 /* Be sure that the device is enabled */ 2534 if (unlikely(pci_enable_device(pdev) < 0)) { 2535 sbridge_printk(KERN_ERR, 2536 "Couldn't enable %04x:%04x\n", 2537 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2538 return -ENODEV; 2539 } 2540 2541 edac_dbg(0, "Detected %04x:%04x\n", 2542 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 2543 2544 /* 2545 * As stated on drivers/pci/search.c, the reference count for 2546 * @from is always decremented if it is not %NULL. So, as we need 2547 * to get all devices up to null, we need to do a get for the device 2548 */ 2549 pci_dev_get(pdev); 2550 2551 *prev = pdev; 2552 2553 return 0; 2554 } 2555 2556 /* 2557 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's 2558 * devices we want to reference for this driver. 2559 * @num_mc: pointer to the memory controllers count, to be incremented in case 2560 * of success. 2561 * @table: model specific table 2562 * 2563 * returns 0 in case of success or error code 2564 */ 2565 static int sbridge_get_all_devices(u8 *num_mc, 2566 const struct pci_id_table *table) 2567 { 2568 int i, rc; 2569 struct pci_dev *pdev = NULL; 2570 int allow_dups = 0; 2571 int multi_bus = 0; 2572 2573 if (table->type == KNIGHTS_LANDING) 2574 allow_dups = multi_bus = 1; 2575 while (table && table->descr) { 2576 for (i = 0; i < table->n_devs_per_sock; i++) { 2577 if (!allow_dups || i == 0 || 2578 table->descr[i].dev_id != 2579 table->descr[i-1].dev_id) { 2580 pdev = NULL; 2581 } 2582 do { 2583 rc = sbridge_get_onedevice(&pdev, num_mc, 2584 table, i, multi_bus); 2585 if (rc < 0) { 2586 if (i == 0) { 2587 i = table->n_devs_per_sock; 2588 break; 2589 } 2590 sbridge_put_all_devices(); 2591 return -ENODEV; 2592 } 2593 } while (pdev && !allow_dups); 2594 } 2595 table++; 2596 } 2597 2598 return 0; 2599 } 2600 2601 /* 2602 * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in 2603 * the format: XXXa. So we can convert from a device to the corresponding 2604 * channel like this 2605 */ 2606 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa) 2607 2608 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, 2609 struct sbridge_dev *sbridge_dev) 2610 { 2611 struct sbridge_pvt *pvt = mci->pvt_info; 2612 struct pci_dev *pdev; 2613 u8 saw_chan_mask = 0; 2614 int i; 2615 2616 for (i = 0; i < sbridge_dev->n_devs; i++) { 2617 pdev = sbridge_dev->pdev[i]; 2618 if (!pdev) 2619 continue; 2620 2621 switch (pdev->device) { 2622 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: 2623 pvt->pci_sad0 = pdev; 2624 break; 2625 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: 2626 pvt->pci_sad1 = pdev; 2627 break; 2628 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: 2629 pvt->pci_br0 = pdev; 2630 break; 2631 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: 2632 pvt->pci_ha = pdev; 2633 break; 2634 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: 2635 pvt->pci_ta = pdev; 2636 break; 2637 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: 2638 pvt->pci_ras = pdev; 2639 break; 2640 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: 2641 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: 2642 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: 2643 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: 2644 { 2645 int id = TAD_DEV_TO_CHAN(pdev->device); 2646 pvt->pci_tad[id] = pdev; 2647 saw_chan_mask |= 1 << id; 2648 } 2649 break; 2650 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: 2651 pvt->pci_ddrio = pdev; 2652 break; 2653 default: 2654 goto error; 2655 } 2656 2657 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", 2658 pdev->vendor, pdev->device, 2659 sbridge_dev->bus, 2660 pdev); 2661 } 2662 2663 /* Check if everything were registered */ 2664 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || 2665 !pvt->pci_ras || !pvt->pci_ta) 2666 goto enodev; 2667 2668 if (saw_chan_mask != 0x0f) 2669 goto enodev; 2670 return 0; 2671 2672 enodev: 2673 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2674 return -ENODEV; 2675 2676 error: 2677 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", 2678 PCI_VENDOR_ID_INTEL, pdev->device); 2679 return -EINVAL; 2680 } 2681 2682 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, 2683 struct sbridge_dev *sbridge_dev) 2684 { 2685 struct sbridge_pvt *pvt = mci->pvt_info; 2686 struct pci_dev *pdev; 2687 u8 saw_chan_mask = 0; 2688 int i; 2689 2690 for (i = 0; i < sbridge_dev->n_devs; i++) { 2691 pdev = sbridge_dev->pdev[i]; 2692 if (!pdev) 2693 continue; 2694 2695 switch (pdev->device) { 2696 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: 2697 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: 2698 pvt->pci_ha = pdev; 2699 break; 2700 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: 2701 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA: 2702 pvt->pci_ta = pdev; 2703 break; 2704 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: 2705 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS: 2706 pvt->pci_ras = pdev; 2707 break; 2708 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: 2709 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: 2710 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: 2711 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: 2712 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: 2713 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: 2714 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: 2715 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: 2716 { 2717 int id = TAD_DEV_TO_CHAN(pdev->device); 2718 pvt->pci_tad[id] = pdev; 2719 saw_chan_mask |= 1 << id; 2720 } 2721 break; 2722 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: 2723 pvt->pci_ddrio = pdev; 2724 break; 2725 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: 2726 pvt->pci_ddrio = pdev; 2727 break; 2728 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: 2729 pvt->pci_sad0 = pdev; 2730 break; 2731 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: 2732 pvt->pci_br0 = pdev; 2733 break; 2734 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: 2735 pvt->pci_br1 = pdev; 2736 break; 2737 default: 2738 goto error; 2739 } 2740 2741 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2742 sbridge_dev->bus, 2743 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2744 pdev); 2745 } 2746 2747 /* Check if everything were registered */ 2748 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || 2749 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) 2750 goto enodev; 2751 2752 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2753 saw_chan_mask != 0x03) /* -EP */ 2754 goto enodev; 2755 return 0; 2756 2757 enodev: 2758 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2759 return -ENODEV; 2760 2761 error: 2762 sbridge_printk(KERN_ERR, 2763 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, 2764 pdev->device); 2765 return -EINVAL; 2766 } 2767 2768 static int haswell_mci_bind_devs(struct mem_ctl_info *mci, 2769 struct sbridge_dev *sbridge_dev) 2770 { 2771 struct sbridge_pvt *pvt = mci->pvt_info; 2772 struct pci_dev *pdev; 2773 u8 saw_chan_mask = 0; 2774 int i; 2775 2776 /* there's only one device per system; not tied to any bus */ 2777 if (pvt->info.pci_vtd == NULL) 2778 /* result will be checked later */ 2779 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 2780 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, 2781 NULL); 2782 2783 for (i = 0; i < sbridge_dev->n_devs; i++) { 2784 pdev = sbridge_dev->pdev[i]; 2785 if (!pdev) 2786 continue; 2787 2788 switch (pdev->device) { 2789 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: 2790 pvt->pci_sad0 = pdev; 2791 break; 2792 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: 2793 pvt->pci_sad1 = pdev; 2794 break; 2795 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: 2796 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: 2797 pvt->pci_ha = pdev; 2798 break; 2799 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: 2800 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: 2801 pvt->pci_ta = pdev; 2802 break; 2803 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM: 2804 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM: 2805 pvt->pci_ras = pdev; 2806 break; 2807 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: 2808 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: 2809 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: 2810 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: 2811 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: 2812 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: 2813 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: 2814 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: 2815 { 2816 int id = TAD_DEV_TO_CHAN(pdev->device); 2817 pvt->pci_tad[id] = pdev; 2818 saw_chan_mask |= 1 << id; 2819 } 2820 break; 2821 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: 2822 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1: 2823 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2: 2824 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3: 2825 if (!pvt->pci_ddrio) 2826 pvt->pci_ddrio = pdev; 2827 break; 2828 default: 2829 break; 2830 } 2831 2832 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2833 sbridge_dev->bus, 2834 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2835 pdev); 2836 } 2837 2838 /* Check if everything were registered */ 2839 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || 2840 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 2841 goto enodev; 2842 2843 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2844 saw_chan_mask != 0x03) /* -EP */ 2845 goto enodev; 2846 return 0; 2847 2848 enodev: 2849 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2850 return -ENODEV; 2851 } 2852 2853 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, 2854 struct sbridge_dev *sbridge_dev) 2855 { 2856 struct sbridge_pvt *pvt = mci->pvt_info; 2857 struct pci_dev *pdev; 2858 u8 saw_chan_mask = 0; 2859 int i; 2860 2861 /* there's only one device per system; not tied to any bus */ 2862 if (pvt->info.pci_vtd == NULL) 2863 /* result will be checked later */ 2864 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, 2865 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, 2866 NULL); 2867 2868 for (i = 0; i < sbridge_dev->n_devs; i++) { 2869 pdev = sbridge_dev->pdev[i]; 2870 if (!pdev) 2871 continue; 2872 2873 switch (pdev->device) { 2874 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: 2875 pvt->pci_sad0 = pdev; 2876 break; 2877 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: 2878 pvt->pci_sad1 = pdev; 2879 break; 2880 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: 2881 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1: 2882 pvt->pci_ha = pdev; 2883 break; 2884 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: 2885 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA: 2886 pvt->pci_ta = pdev; 2887 break; 2888 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM: 2889 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM: 2890 pvt->pci_ras = pdev; 2891 break; 2892 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: 2893 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: 2894 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: 2895 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: 2896 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0: 2897 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1: 2898 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2: 2899 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3: 2900 { 2901 int id = TAD_DEV_TO_CHAN(pdev->device); 2902 pvt->pci_tad[id] = pdev; 2903 saw_chan_mask |= 1 << id; 2904 } 2905 break; 2906 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: 2907 pvt->pci_ddrio = pdev; 2908 break; 2909 default: 2910 break; 2911 } 2912 2913 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 2914 sbridge_dev->bus, 2915 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2916 pdev); 2917 } 2918 2919 /* Check if everything were registered */ 2920 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || 2921 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) 2922 goto enodev; 2923 2924 if (saw_chan_mask != 0x0f && /* -EN/-EX */ 2925 saw_chan_mask != 0x03) /* -EP */ 2926 goto enodev; 2927 return 0; 2928 2929 enodev: 2930 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 2931 return -ENODEV; 2932 } 2933 2934 static int knl_mci_bind_devs(struct mem_ctl_info *mci, 2935 struct sbridge_dev *sbridge_dev) 2936 { 2937 struct sbridge_pvt *pvt = mci->pvt_info; 2938 struct pci_dev *pdev; 2939 int dev, func; 2940 2941 int i; 2942 int devidx; 2943 2944 for (i = 0; i < sbridge_dev->n_devs; i++) { 2945 pdev = sbridge_dev->pdev[i]; 2946 if (!pdev) 2947 continue; 2948 2949 /* Extract PCI device and function. */ 2950 dev = (pdev->devfn >> 3) & 0x1f; 2951 func = pdev->devfn & 0x7; 2952 2953 switch (pdev->device) { 2954 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC: 2955 if (dev == 8) 2956 pvt->knl.pci_mc0 = pdev; 2957 else if (dev == 9) 2958 pvt->knl.pci_mc1 = pdev; 2959 else { 2960 sbridge_printk(KERN_ERR, 2961 "Memory controller in unexpected place! (dev %d, fn %d)\n", 2962 dev, func); 2963 continue; 2964 } 2965 break; 2966 2967 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0: 2968 pvt->pci_sad0 = pdev; 2969 break; 2970 2971 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1: 2972 pvt->pci_sad1 = pdev; 2973 break; 2974 2975 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA: 2976 /* There are one of these per tile, and range from 2977 * 1.14.0 to 1.18.5. 2978 */ 2979 devidx = ((dev-14)*8)+func; 2980 2981 if (devidx < 0 || devidx >= KNL_MAX_CHAS) { 2982 sbridge_printk(KERN_ERR, 2983 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n", 2984 dev, func); 2985 continue; 2986 } 2987 2988 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); 2989 2990 pvt->knl.pci_cha[devidx] = pdev; 2991 break; 2992 2993 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN: 2994 devidx = -1; 2995 2996 /* 2997 * MC0 channels 0-2 are device 9 function 2-4, 2998 * MC1 channels 3-5 are device 8 function 2-4. 2999 */ 3000 3001 if (dev == 9) 3002 devidx = func-2; 3003 else if (dev == 8) 3004 devidx = 3 + (func-2); 3005 3006 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) { 3007 sbridge_printk(KERN_ERR, 3008 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n", 3009 dev, func); 3010 continue; 3011 } 3012 3013 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); 3014 pvt->knl.pci_channel[devidx] = pdev; 3015 break; 3016 3017 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM: 3018 pvt->knl.pci_mc_info = pdev; 3019 break; 3020 3021 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA: 3022 pvt->pci_ta = pdev; 3023 break; 3024 3025 default: 3026 sbridge_printk(KERN_ERR, "Unexpected device %d\n", 3027 pdev->device); 3028 break; 3029 } 3030 } 3031 3032 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || 3033 !pvt->pci_sad0 || !pvt->pci_sad1 || 3034 !pvt->pci_ta) { 3035 goto enodev; 3036 } 3037 3038 for (i = 0; i < KNL_MAX_CHANNELS; i++) { 3039 if (!pvt->knl.pci_channel[i]) { 3040 sbridge_printk(KERN_ERR, "Missing channel %d\n", i); 3041 goto enodev; 3042 } 3043 } 3044 3045 for (i = 0; i < KNL_MAX_CHAS; i++) { 3046 if (!pvt->knl.pci_cha[i]) { 3047 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i); 3048 goto enodev; 3049 } 3050 } 3051 3052 return 0; 3053 3054 enodev: 3055 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 3056 return -ENODEV; 3057 } 3058 3059 /**************************************************************************** 3060 Error check routines 3061 ****************************************************************************/ 3062 3063 /* 3064 * While Sandy Bridge has error count registers, SMI BIOS read values from 3065 * and resets the counters. So, they are not reliable for the OS to read 3066 * from them. So, we have no option but to just trust on whatever MCE is 3067 * telling us about the errors. 3068 */ 3069 static void sbridge_mce_output_error(struct mem_ctl_info *mci, 3070 const struct mce *m) 3071 { 3072 struct mem_ctl_info *new_mci; 3073 struct sbridge_pvt *pvt = mci->pvt_info; 3074 enum hw_event_mc_err_type tp_event; 3075 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 3076 bool overflow = GET_BITFIELD(m->status, 62, 62); 3077 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 3078 bool recoverable; 3079 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 3080 u32 mscod = GET_BITFIELD(m->status, 16, 31); 3081 u32 errcode = GET_BITFIELD(m->status, 0, 15); 3082 u32 channel = GET_BITFIELD(m->status, 0, 3); 3083 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 3084 /* 3085 * Bits 5-0 of MCi_MISC give the least significant bit that is valid. 3086 * A value 6 is for cache line aligned address, a value 12 is for page 3087 * aligned address reported by patrol scrubber. 3088 */ 3089 u32 lsb = GET_BITFIELD(m->misc, 0, 5); 3090 char *optype, *area_type = "DRAM"; 3091 long channel_mask, first_channel; 3092 u8 rank = 0xff, socket, ha; 3093 int rc, dimm; 3094 3095 if (pvt->info.type != SANDY_BRIDGE) 3096 recoverable = true; 3097 else 3098 recoverable = GET_BITFIELD(m->status, 56, 56); 3099 3100 if (uncorrected_error) { 3101 core_err_cnt = 1; 3102 if (ripv) { 3103 tp_event = HW_EVENT_ERR_UNCORRECTED; 3104 } else { 3105 tp_event = HW_EVENT_ERR_FATAL; 3106 } 3107 } else { 3108 tp_event = HW_EVENT_ERR_CORRECTED; 3109 } 3110 3111 /* 3112 * According with Table 15-9 of the Intel Architecture spec vol 3A, 3113 * memory errors should fit in this mask: 3114 * 000f 0000 1mmm cccc (binary) 3115 * where: 3116 * f = Correction Report Filtering Bit. If 1, subsequent errors 3117 * won't be shown 3118 * mmm = error type 3119 * cccc = channel 3120 * If the mask doesn't match, report an error to the parsing logic 3121 */ 3122 switch (optypenum) { 3123 case 0: 3124 optype = "generic undef request error"; 3125 break; 3126 case 1: 3127 optype = "memory read error"; 3128 break; 3129 case 2: 3130 optype = "memory write error"; 3131 break; 3132 case 3: 3133 optype = "addr/cmd error"; 3134 break; 3135 case 4: 3136 optype = "memory scrubbing error"; 3137 break; 3138 default: 3139 optype = "reserved"; 3140 break; 3141 } 3142 3143 if (pvt->info.type == KNIGHTS_LANDING) { 3144 if (channel == 14) { 3145 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n", 3146 overflow ? " OVERFLOW" : "", 3147 (uncorrected_error && recoverable) 3148 ? " recoverable" : "", 3149 mscod, errcode, 3150 m->bank); 3151 } else { 3152 char A = *("A"); 3153 3154 /* 3155 * Reported channel is in range 0-2, so we can't map it 3156 * back to mc. To figure out mc we check machine check 3157 * bank register that reported this error. 3158 * bank15 means mc0 and bank16 means mc1. 3159 */ 3160 channel = knl_channel_remap(m->bank == 16, channel); 3161 channel_mask = 1 << channel; 3162 3163 snprintf(sb_msg, sizeof(sb_msg), 3164 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)", 3165 overflow ? " OVERFLOW" : "", 3166 (uncorrected_error && recoverable) 3167 ? " recoverable" : " ", 3168 mscod, errcode, channel, A + channel); 3169 edac_mc_handle_error(tp_event, mci, core_err_cnt, 3170 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 3171 channel, 0, -1, 3172 optype, sb_msg); 3173 } 3174 return; 3175 } else if (lsb < 12) { 3176 rc = get_memory_error_data(mci, m->addr, &socket, &ha, 3177 &channel_mask, &rank, 3178 &area_type, sb_msg); 3179 } else { 3180 rc = get_memory_error_data_from_mce(mci, m, &socket, &ha, 3181 &channel_mask, sb_msg); 3182 } 3183 3184 if (rc < 0) 3185 goto err_parsing; 3186 new_mci = get_mci_for_node_id(socket, ha); 3187 if (!new_mci) { 3188 strscpy(sb_msg, "Error: socket got corrupted!"); 3189 goto err_parsing; 3190 } 3191 mci = new_mci; 3192 pvt = mci->pvt_info; 3193 3194 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); 3195 3196 if (rank == 0xff) 3197 dimm = -1; 3198 else if (rank < 4) 3199 dimm = 0; 3200 else if (rank < 8) 3201 dimm = 1; 3202 else 3203 dimm = 2; 3204 3205 /* 3206 * FIXME: On some memory configurations (mirror, lockstep), the 3207 * Memory Controller can't point the error to a single DIMM. The 3208 * EDAC core should be handling the channel mask, in order to point 3209 * to the group of dimm's where the error may be happening. 3210 */ 3211 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) 3212 channel = first_channel; 3213 snprintf(sb_msg_full, sizeof(sb_msg_full), 3214 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d %s", 3215 overflow ? " OVERFLOW" : "", 3216 (uncorrected_error && recoverable) ? " recoverable" : "", 3217 area_type, 3218 mscod, errcode, 3219 socket, ha, 3220 channel_mask, 3221 rank, sb_msg); 3222 3223 edac_dbg(0, "%s\n", sb_msg_full); 3224 3225 /* FIXME: need support for channel mask */ 3226 3227 if (channel == CHANNEL_UNSPECIFIED) 3228 channel = -1; 3229 3230 /* Call the helper to output message */ 3231 edac_mc_handle_error(tp_event, mci, core_err_cnt, 3232 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 3233 channel, dimm, -1, 3234 optype, sb_msg_full); 3235 return; 3236 err_parsing: 3237 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, 3238 -1, -1, -1, 3239 sb_msg, ""); 3240 3241 } 3242 3243 /* 3244 * Check that logging is enabled and that this is the right type 3245 * of error for us to handle. 3246 */ 3247 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, 3248 void *data) 3249 { 3250 struct mce *mce = (struct mce *)data; 3251 struct mem_ctl_info *mci; 3252 char *type; 3253 3254 if (mce->kflags & MCE_HANDLED_CEC) 3255 return NOTIFY_DONE; 3256 3257 /* 3258 * Just let mcelog handle it if the error is 3259 * outside the memory controller. A memory error 3260 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. 3261 * bit 12 has an special meaning. 3262 */ 3263 if ((mce->status & 0xefff) >> 7 != 1) 3264 return NOTIFY_DONE; 3265 3266 /* Check ADDRV bit in STATUS */ 3267 if (!GET_BITFIELD(mce->status, 58, 58)) 3268 return NOTIFY_DONE; 3269 3270 /* Check MISCV bit in STATUS */ 3271 if (!GET_BITFIELD(mce->status, 59, 59)) 3272 return NOTIFY_DONE; 3273 3274 /* Check address type in MISC (physical address only) */ 3275 if (GET_BITFIELD(mce->misc, 6, 8) != 2) 3276 return NOTIFY_DONE; 3277 3278 mci = get_mci_for_node_id(mce->socketid, IMC0); 3279 if (!mci) 3280 return NOTIFY_DONE; 3281 3282 if (mce->mcgstatus & MCG_STATUS_MCIP) 3283 type = "Exception"; 3284 else 3285 type = "Event"; 3286 3287 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 3288 3289 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " 3290 "Bank %d: %016Lx\n", mce->extcpu, type, 3291 mce->mcgstatus, mce->bank, mce->status); 3292 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); 3293 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); 3294 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); 3295 3296 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " 3297 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, 3298 mce->time, mce->socketid, mce->apicid); 3299 3300 sbridge_mce_output_error(mci, mce); 3301 3302 /* Advice mcelog that the error were handled */ 3303 mce->kflags |= MCE_HANDLED_EDAC; 3304 return NOTIFY_OK; 3305 } 3306 3307 static struct notifier_block sbridge_mce_dec = { 3308 .notifier_call = sbridge_mce_check_error, 3309 .priority = MCE_PRIO_EDAC, 3310 }; 3311 3312 /**************************************************************************** 3313 EDAC register/unregister logic 3314 ****************************************************************************/ 3315 3316 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) 3317 { 3318 struct mem_ctl_info *mci = sbridge_dev->mci; 3319 3320 if (unlikely(!mci || !mci->pvt_info)) { 3321 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); 3322 3323 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); 3324 return; 3325 } 3326 3327 edac_dbg(0, "MC: mci = %p, dev = %p\n", 3328 mci, &sbridge_dev->pdev[0]->dev); 3329 3330 /* Remove MC sysfs nodes */ 3331 edac_mc_del_mc(mci->pdev); 3332 3333 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 3334 kfree(mci->ctl_name); 3335 edac_mc_free(mci); 3336 sbridge_dev->mci = NULL; 3337 } 3338 3339 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) 3340 { 3341 struct mem_ctl_info *mci; 3342 struct edac_mc_layer layers[2]; 3343 struct sbridge_pvt *pvt; 3344 struct pci_dev *pdev = sbridge_dev->pdev[0]; 3345 int rc; 3346 3347 /* allocate a new MC control structure */ 3348 layers[0].type = EDAC_MC_LAYER_CHANNEL; 3349 layers[0].size = type == KNIGHTS_LANDING ? 3350 KNL_MAX_CHANNELS : NUM_CHANNELS; 3351 layers[0].is_virt_csrow = false; 3352 layers[1].type = EDAC_MC_LAYER_SLOT; 3353 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; 3354 layers[1].is_virt_csrow = true; 3355 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, 3356 sizeof(*pvt)); 3357 3358 if (unlikely(!mci)) 3359 return -ENOMEM; 3360 3361 edac_dbg(0, "MC: mci = %p, dev = %p\n", 3362 mci, &pdev->dev); 3363 3364 pvt = mci->pvt_info; 3365 memset(pvt, 0, sizeof(*pvt)); 3366 3367 /* Associate sbridge_dev and mci for future usage */ 3368 pvt->sbridge_dev = sbridge_dev; 3369 sbridge_dev->mci = mci; 3370 3371 mci->mtype_cap = type == KNIGHTS_LANDING ? 3372 MEM_FLAG_DDR4 : MEM_FLAG_DDR3; 3373 mci->edac_ctl_cap = EDAC_FLAG_NONE; 3374 mci->edac_cap = EDAC_FLAG_NONE; 3375 mci->mod_name = EDAC_MOD_STR; 3376 mci->dev_name = pci_name(pdev); 3377 mci->ctl_page_to_phys = NULL; 3378 3379 pvt->info.type = type; 3380 switch (type) { 3381 case IVY_BRIDGE: 3382 pvt->info.rankcfgr = IB_RANK_CFG_A; 3383 pvt->info.get_tolm = ibridge_get_tolm; 3384 pvt->info.get_tohm = ibridge_get_tohm; 3385 pvt->info.dram_rule = ibridge_dram_rule; 3386 pvt->info.get_memory_type = get_memory_type; 3387 pvt->info.get_node_id = get_node_id; 3388 pvt->info.get_ha = ibridge_get_ha; 3389 pvt->info.rir_limit = rir_limit; 3390 pvt->info.sad_limit = sad_limit; 3391 pvt->info.interleave_mode = interleave_mode; 3392 pvt->info.dram_attr = dram_attr; 3393 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3394 pvt->info.interleave_list = ibridge_interleave_list; 3395 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3396 pvt->info.get_width = ibridge_get_width; 3397 3398 /* Store pci devices at mci for faster access */ 3399 rc = ibridge_mci_bind_devs(mci, sbridge_dev); 3400 if (unlikely(rc < 0)) 3401 goto fail0; 3402 get_source_id(mci); 3403 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", 3404 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3405 break; 3406 case SANDY_BRIDGE: 3407 pvt->info.rankcfgr = SB_RANK_CFG_A; 3408 pvt->info.get_tolm = sbridge_get_tolm; 3409 pvt->info.get_tohm = sbridge_get_tohm; 3410 pvt->info.dram_rule = sbridge_dram_rule; 3411 pvt->info.get_memory_type = get_memory_type; 3412 pvt->info.get_node_id = get_node_id; 3413 pvt->info.get_ha = sbridge_get_ha; 3414 pvt->info.rir_limit = rir_limit; 3415 pvt->info.sad_limit = sad_limit; 3416 pvt->info.interleave_mode = interleave_mode; 3417 pvt->info.dram_attr = dram_attr; 3418 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); 3419 pvt->info.interleave_list = sbridge_interleave_list; 3420 pvt->info.interleave_pkg = sbridge_interleave_pkg; 3421 pvt->info.get_width = sbridge_get_width; 3422 3423 /* Store pci devices at mci for faster access */ 3424 rc = sbridge_mci_bind_devs(mci, sbridge_dev); 3425 if (unlikely(rc < 0)) 3426 goto fail0; 3427 get_source_id(mci); 3428 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", 3429 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3430 break; 3431 case HASWELL: 3432 /* rankcfgr isn't used */ 3433 pvt->info.get_tolm = haswell_get_tolm; 3434 pvt->info.get_tohm = haswell_get_tohm; 3435 pvt->info.dram_rule = ibridge_dram_rule; 3436 pvt->info.get_memory_type = haswell_get_memory_type; 3437 pvt->info.get_node_id = haswell_get_node_id; 3438 pvt->info.get_ha = ibridge_get_ha; 3439 pvt->info.rir_limit = haswell_rir_limit; 3440 pvt->info.sad_limit = sad_limit; 3441 pvt->info.interleave_mode = interleave_mode; 3442 pvt->info.dram_attr = dram_attr; 3443 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3444 pvt->info.interleave_list = ibridge_interleave_list; 3445 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3446 pvt->info.get_width = ibridge_get_width; 3447 3448 /* Store pci devices at mci for faster access */ 3449 rc = haswell_mci_bind_devs(mci, sbridge_dev); 3450 if (unlikely(rc < 0)) 3451 goto fail0; 3452 get_source_id(mci); 3453 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", 3454 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3455 break; 3456 case BROADWELL: 3457 /* rankcfgr isn't used */ 3458 pvt->info.get_tolm = haswell_get_tolm; 3459 pvt->info.get_tohm = haswell_get_tohm; 3460 pvt->info.dram_rule = ibridge_dram_rule; 3461 pvt->info.get_memory_type = haswell_get_memory_type; 3462 pvt->info.get_node_id = haswell_get_node_id; 3463 pvt->info.get_ha = ibridge_get_ha; 3464 pvt->info.rir_limit = haswell_rir_limit; 3465 pvt->info.sad_limit = sad_limit; 3466 pvt->info.interleave_mode = interleave_mode; 3467 pvt->info.dram_attr = dram_attr; 3468 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); 3469 pvt->info.interleave_list = ibridge_interleave_list; 3470 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3471 pvt->info.get_width = broadwell_get_width; 3472 3473 /* Store pci devices at mci for faster access */ 3474 rc = broadwell_mci_bind_devs(mci, sbridge_dev); 3475 if (unlikely(rc < 0)) 3476 goto fail0; 3477 get_source_id(mci); 3478 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", 3479 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3480 break; 3481 case KNIGHTS_LANDING: 3482 /* pvt->info.rankcfgr == ??? */ 3483 pvt->info.get_tolm = knl_get_tolm; 3484 pvt->info.get_tohm = knl_get_tohm; 3485 pvt->info.dram_rule = knl_dram_rule; 3486 pvt->info.get_memory_type = knl_get_memory_type; 3487 pvt->info.get_node_id = knl_get_node_id; 3488 pvt->info.get_ha = knl_get_ha; 3489 pvt->info.rir_limit = NULL; 3490 pvt->info.sad_limit = knl_sad_limit; 3491 pvt->info.interleave_mode = knl_interleave_mode; 3492 pvt->info.dram_attr = dram_attr_knl; 3493 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); 3494 pvt->info.interleave_list = knl_interleave_list; 3495 pvt->info.interleave_pkg = ibridge_interleave_pkg; 3496 pvt->info.get_width = knl_get_width; 3497 3498 rc = knl_mci_bind_devs(mci, sbridge_dev); 3499 if (unlikely(rc < 0)) 3500 goto fail0; 3501 get_source_id(mci); 3502 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", 3503 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); 3504 break; 3505 } 3506 3507 if (!mci->ctl_name) { 3508 rc = -ENOMEM; 3509 goto fail0; 3510 } 3511 3512 /* Get dimm basic config and the memory layout */ 3513 rc = get_dimm_config(mci); 3514 if (rc < 0) { 3515 edac_dbg(0, "MC: failed to get_dimm_config()\n"); 3516 goto fail; 3517 } 3518 get_memory_layout(mci); 3519 3520 /* record ptr to the generic device */ 3521 mci->pdev = &pdev->dev; 3522 3523 /* add this new MC control structure to EDAC's list of MCs */ 3524 if (unlikely(edac_mc_add_mc(mci))) { 3525 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 3526 rc = -EINVAL; 3527 goto fail; 3528 } 3529 3530 return 0; 3531 3532 fail: 3533 kfree(mci->ctl_name); 3534 fail0: 3535 edac_mc_free(mci); 3536 sbridge_dev->mci = NULL; 3537 return rc; 3538 } 3539 3540 static const struct x86_cpu_id sbridge_cpuids[] = { 3541 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &pci_dev_descr_sbridge_table), 3542 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &pci_dev_descr_ibridge_table), 3543 X86_MATCH_VFM(INTEL_HASWELL_X, &pci_dev_descr_haswell_table), 3544 X86_MATCH_VFM(INTEL_BROADWELL_X, &pci_dev_descr_broadwell_table), 3545 X86_MATCH_VFM(INTEL_BROADWELL_D, &pci_dev_descr_broadwell_table), 3546 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &pci_dev_descr_knl_table), 3547 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &pci_dev_descr_knl_table), 3548 { } 3549 }; 3550 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids); 3551 3552 /* 3553 * sbridge_probe Get all devices and register memory controllers 3554 * present. 3555 * return: 3556 * 0 for FOUND a device 3557 * < 0 for error code 3558 */ 3559 3560 static int sbridge_probe(const struct x86_cpu_id *id) 3561 { 3562 int rc; 3563 u8 mc, num_mc = 0; 3564 struct sbridge_dev *sbridge_dev; 3565 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; 3566 3567 /* get the pci devices we want to reserve for our use */ 3568 rc = sbridge_get_all_devices(&num_mc, ptable); 3569 3570 if (unlikely(rc < 0)) { 3571 edac_dbg(0, "couldn't get all devices\n"); 3572 goto fail0; 3573 } 3574 3575 mc = 0; 3576 3577 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 3578 edac_dbg(0, "Registering MC#%d (%d of %d)\n", 3579 mc, mc + 1, num_mc); 3580 3581 sbridge_dev->mc = mc++; 3582 rc = sbridge_register_mci(sbridge_dev, ptable->type); 3583 if (unlikely(rc < 0)) 3584 goto fail1; 3585 } 3586 3587 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); 3588 3589 return 0; 3590 3591 fail1: 3592 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 3593 sbridge_unregister_mci(sbridge_dev); 3594 3595 sbridge_put_all_devices(); 3596 fail0: 3597 return rc; 3598 } 3599 3600 /* 3601 * sbridge_remove cleanup 3602 * 3603 */ 3604 static void sbridge_remove(void) 3605 { 3606 struct sbridge_dev *sbridge_dev; 3607 3608 edac_dbg(0, "\n"); 3609 3610 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 3611 sbridge_unregister_mci(sbridge_dev); 3612 3613 /* Release PCI resources */ 3614 sbridge_put_all_devices(); 3615 } 3616 3617 /* 3618 * sbridge_init Module entry function 3619 * Try to initialize this module for its devices 3620 */ 3621 static int __init sbridge_init(void) 3622 { 3623 const struct x86_cpu_id *id; 3624 const char *owner; 3625 int rc; 3626 3627 edac_dbg(2, "\n"); 3628 3629 if (ghes_get_devices()) 3630 return -EBUSY; 3631 3632 owner = edac_get_owner(); 3633 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 3634 return -EBUSY; 3635 3636 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 3637 return -ENODEV; 3638 3639 id = x86_match_cpu(sbridge_cpuids); 3640 if (!id) 3641 return -ENODEV; 3642 3643 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 3644 opstate_init(); 3645 3646 rc = sbridge_probe(id); 3647 3648 if (rc >= 0) { 3649 mce_register_decode_chain(&sbridge_mce_dec); 3650 return 0; 3651 } 3652 3653 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", 3654 rc); 3655 3656 return rc; 3657 } 3658 3659 /* 3660 * sbridge_exit() Module exit function 3661 * Unregister the driver 3662 */ 3663 static void __exit sbridge_exit(void) 3664 { 3665 edac_dbg(2, "\n"); 3666 sbridge_remove(); 3667 mce_unregister_decode_chain(&sbridge_mce_dec); 3668 } 3669 3670 module_init(sbridge_init); 3671 module_exit(sbridge_exit); 3672 3673 module_param(edac_op_state, int, 0444); 3674 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 3675 3676 MODULE_LICENSE("GPL"); 3677 MODULE_AUTHOR("Mauro Carvalho Chehab"); 3678 MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)"); 3679 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " 3680 SBRIDGE_REVISION); 3681