1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015, 2016 ARM Ltd.
4 */
5
6 #include <linux/irqchip/arm-gic.h>
7 #include <linux/kvm.h>
8 #include <linux/kvm_host.h>
9 #include <kvm/arm_vgic.h>
10 #include <asm/kvm_mmu.h>
11
12 #include "vgic-mmio.h"
13 #include "vgic.h"
14
vgic_v2_write_lr(int lr,u32 val)15 static inline void vgic_v2_write_lr(int lr, u32 val)
16 {
17 void __iomem *base = kvm_vgic_global_state.vctrl_base;
18
19 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
20 }
21
vgic_v2_init_lrs(void)22 void vgic_v2_init_lrs(void)
23 {
24 int i;
25
26 for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
27 vgic_v2_write_lr(i, 0);
28 }
29
vgic_v2_configure_hcr(struct kvm_vcpu * vcpu,struct ap_list_summary * als)30 void vgic_v2_configure_hcr(struct kvm_vcpu *vcpu,
31 struct ap_list_summary *als)
32 {
33 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
34
35 cpuif->vgic_hcr = GICH_HCR_EN;
36
37 if (irqs_pending_outside_lrs(als))
38 cpuif->vgic_hcr |= GICH_HCR_NPIE;
39 if (irqs_active_outside_lrs(als))
40 cpuif->vgic_hcr |= GICH_HCR_LRENPIE;
41 if (irqs_outside_lrs(als))
42 cpuif->vgic_hcr |= GICH_HCR_UIE;
43
44 cpuif->vgic_hcr |= (cpuif->vgic_vmcr & GICH_VMCR_ENABLE_GRP0_MASK) ?
45 GICH_HCR_VGrp0DIE : GICH_HCR_VGrp0EIE;
46 cpuif->vgic_hcr |= (cpuif->vgic_vmcr & GICH_VMCR_ENABLE_GRP1_MASK) ?
47 GICH_HCR_VGrp1DIE : GICH_HCR_VGrp1EIE;
48 }
49
lr_signals_eoi_mi(u32 lr_val)50 static bool lr_signals_eoi_mi(u32 lr_val)
51 {
52 return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
53 !(lr_val & GICH_LR_HW);
54 }
55
vgic_v2_fold_lr(struct kvm_vcpu * vcpu,u32 val)56 static void vgic_v2_fold_lr(struct kvm_vcpu *vcpu, u32 val)
57 {
58 u32 cpuid, intid = val & GICH_LR_VIRTUALID;
59 struct vgic_irq *irq;
60 bool deactivated;
61
62 /* Extract the source vCPU id from the LR */
63 cpuid = FIELD_GET(GICH_LR_PHYSID_CPUID, val) & 7;
64
65 /* Notify fds when the guest EOI'ed a level-triggered SPI */
66 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
67 kvm_notify_acked_irq(vcpu->kvm, 0,
68 intid - VGIC_NR_PRIVATE_IRQS);
69
70 irq = vgic_get_vcpu_irq(vcpu, intid);
71
72 scoped_guard(raw_spinlock, &irq->irq_lock) {
73 /* Always preserve the active bit, note deactivation */
74 deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT);
75 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
76
77 if (irq->active && vgic_irq_is_sgi(intid))
78 irq->active_source = cpuid;
79
80 /* Edge is the only case where we preserve the pending bit */
81 if (irq->config == VGIC_CONFIG_EDGE &&
82 (val & GICH_LR_PENDING_BIT)) {
83 irq->pending_latch = true;
84
85 if (vgic_irq_is_sgi(intid))
86 irq->source |= (1 << cpuid);
87 }
88
89 /*
90 * Clear soft pending state when level irqs have been acked.
91 */
92 if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
93 irq->pending_latch = false;
94
95 /* Handle resampling for mapped interrupts if required */
96 vgic_irq_handle_resampling(irq, deactivated, val & GICH_LR_PENDING_BIT);
97
98 irq->on_lr = false;
99 }
100
101 vgic_put_irq(vcpu->kvm, irq);
102 }
103
104 static u32 vgic_v2_compute_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq);
105
106 /*
107 * transfer the content of the LRs back into the corresponding ap_list:
108 * - active bit is transferred as is
109 * - pending bit is
110 * - transferred as is in case of edge sensitive IRQs
111 * - set to the line-level (resample time) for level sensitive IRQs
112 */
vgic_v2_fold_lr_state(struct kvm_vcpu * vcpu)113 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
114 {
115 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
116 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
117 u32 eoicount = FIELD_GET(GICH_HCR_EOICOUNT, cpuif->vgic_hcr);
118 struct vgic_irq *irq = *host_data_ptr(last_lr_irq);
119
120 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
121
122 for (int lr = 0; lr < vgic_cpu->vgic_v2.used_lrs; lr++)
123 vgic_v2_fold_lr(vcpu, cpuif->vgic_lr[lr]);
124
125 cpuif->used_lrs = 0;
126 if (!irq)
127 return;
128
129 /* See the GICv3 equivalent for the EOIcount handling rationale */
130 list_for_each_entry_continue(irq, &vgic_cpu->ap_list_head, ap_list) {
131 u32 lr;
132
133 if (!eoicount) {
134 break;
135 } else {
136 guard(raw_spinlock)(&irq->irq_lock);
137
138 if (!(likely(vgic_target_oracle(irq) == vcpu) &&
139 irq->active))
140 continue;
141
142 lr = vgic_v2_compute_lr(vcpu, irq) & ~GICH_LR_ACTIVE_BIT;
143 }
144
145 if (lr & GICH_LR_HW)
146 writel_relaxed(FIELD_GET(GICH_LR_PHYSID_CPUID, lr),
147 kvm_vgic_global_state.gicc_base + GIC_CPU_DEACTIVATE);
148 vgic_v2_fold_lr(vcpu, lr);
149 eoicount--;
150 }
151 }
152
vgic_v2_deactivate(struct kvm_vcpu * vcpu,u32 val)153 void vgic_v2_deactivate(struct kvm_vcpu *vcpu, u32 val)
154 {
155 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
156 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
157 struct kvm_vcpu *target_vcpu = NULL;
158 bool mmio = false;
159 struct vgic_irq *irq;
160 unsigned long flags;
161 u64 lr = 0;
162 u8 cpuid;
163
164 /* Snapshot CPUID, and remove it from the INTID */
165 cpuid = FIELD_GET(GENMASK_ULL(12, 10), val);
166 val &= ~GENMASK_ULL(12, 10);
167
168 /* We only deal with DIR when EOIMode==1 */
169 if (!(cpuif->vgic_vmcr & GICH_VMCR_EOI_MODE_MASK))
170 return;
171
172 /* Make sure we're in the same context as LR handling */
173 local_irq_save(flags);
174
175 /* Guest-supplied INTID: out of range yields no irq, so ignore it */
176 irq = vgic_get_vcpu_irq(vcpu, val);
177 if (!irq)
178 goto out;
179
180 /* See the corresponding v3 code for the rationale */
181 scoped_guard(raw_spinlock, &irq->irq_lock) {
182 target_vcpu = irq->vcpu;
183
184 /* Not on any ap_list? */
185 if (!target_vcpu)
186 goto put;
187
188 /*
189 * Urgh. We're deactivating something that we cannot
190 * observe yet... Big hammer time.
191 */
192 if (irq->on_lr) {
193 mmio = true;
194 goto put;
195 }
196
197 /* SGI: check that the cpuid matches */
198 if (val < VGIC_NR_SGIS && irq->active_source != cpuid) {
199 target_vcpu = NULL;
200 goto put;
201 }
202
203 /* (with a Dalek voice) DEACTIVATE!!!! */
204 lr = vgic_v2_compute_lr(vcpu, irq) & ~GICH_LR_ACTIVE_BIT;
205 }
206
207 if (lr & GICH_LR_HW)
208 writel_relaxed(FIELD_GET(GICH_LR_PHYSID_CPUID, lr),
209 kvm_vgic_global_state.gicc_base + GIC_CPU_DEACTIVATE);
210
211 vgic_v2_fold_lr(vcpu, lr);
212
213 put:
214 vgic_put_irq(vcpu->kvm, irq);
215
216 out:
217 local_irq_restore(flags);
218
219 if (mmio)
220 vgic_mmio_write_cactive(vcpu, (val / 32) * 4, 4, BIT(val % 32));
221
222 /* Force the ap_list to be pruned */
223 if (target_vcpu)
224 kvm_make_request(KVM_REQ_VGIC_PROCESS_UPDATE, target_vcpu);
225 }
226
vgic_v2_compute_lr(struct kvm_vcpu * vcpu,struct vgic_irq * irq)227 static u32 vgic_v2_compute_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
228 {
229 u32 val = irq->intid;
230 bool allow_pending = true;
231
232 WARN_ON(irq->on_lr);
233
234 if (irq->active) {
235 val |= GICH_LR_ACTIVE_BIT;
236 if (vgic_irq_is_sgi(irq->intid))
237 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
238 if (vgic_irq_is_multi_sgi(irq)) {
239 allow_pending = false;
240 val |= GICH_LR_EOI;
241 }
242 }
243
244 if (irq->group)
245 val |= GICH_LR_GROUP1;
246
247 if (irq->hw && !vgic_irq_needs_resampling(irq)) {
248 val |= GICH_LR_HW;
249 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
250 /*
251 * Never set pending+active on a HW interrupt, as the
252 * pending state is kept at the physical distributor
253 * level.
254 */
255 if (irq->active)
256 allow_pending = false;
257 } else {
258 if (irq->config == VGIC_CONFIG_LEVEL) {
259 val |= GICH_LR_EOI;
260
261 /*
262 * Software resampling doesn't work very well
263 * if we allow P+A, so let's not do that.
264 */
265 if (irq->active)
266 allow_pending = false;
267 }
268 }
269
270 if (allow_pending && irq_is_pending(irq)) {
271 val |= GICH_LR_PENDING_BIT;
272
273 if (vgic_irq_is_sgi(irq->intid)) {
274 u32 src = ffs(irq->source);
275
276 if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
277 irq->intid))
278 return 0;
279
280 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
281 if (irq->source & ~BIT(src - 1))
282 val |= GICH_LR_EOI;
283 }
284 }
285
286 /* The GICv2 LR only holds five bits of priority. */
287 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
288
289 return val;
290 }
291
292 /*
293 * Populates the particular LR with the state of a given IRQ:
294 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
295 * - for a level sensitive IRQ the pending state value is unchanged;
296 * it is dictated directly by the input level
297 *
298 * If @irq describes an SGI with multiple sources, we choose the
299 * lowest-numbered source VCPU and clear that bit in the source bitmap.
300 *
301 * The irq_lock must be held by the caller.
302 */
vgic_v2_populate_lr(struct kvm_vcpu * vcpu,struct vgic_irq * irq,int lr)303 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
304 {
305 u32 val = vgic_v2_compute_lr(vcpu, irq);
306
307 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
308
309 if (val & GICH_LR_PENDING_BIT) {
310 if (irq->config == VGIC_CONFIG_EDGE)
311 irq->pending_latch = false;
312
313 if (vgic_irq_is_sgi(irq->intid)) {
314 u32 src = ffs(irq->source);
315
316 irq->source &= ~BIT(src - 1);
317 if (irq->source)
318 irq->pending_latch = true;
319 }
320 }
321
322 /*
323 * Level-triggered mapped IRQs are special because we only observe
324 * rising edges as input to the VGIC. We therefore lower the line
325 * level here, so that we can take new virtual IRQs. See
326 * vgic_v2_fold_lr_state for more info.
327 */
328 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
329 irq->line_level = false;
330
331 /* The GICv2 LR only holds five bits of priority. */
332 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
333
334 irq->on_lr = true;
335 }
336
vgic_v2_clear_lr(struct kvm_vcpu * vcpu,int lr)337 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
338 {
339 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
340 }
341
vgic_v2_set_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)342 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
343 {
344 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
345 u32 vmcr;
346
347 vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
348 GICH_VMCR_ENABLE_GRP0_MASK;
349 vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
350 GICH_VMCR_ENABLE_GRP1_MASK;
351 vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
352 GICH_VMCR_ACK_CTL_MASK;
353 vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
354 GICH_VMCR_FIQ_EN_MASK;
355 vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
356 GICH_VMCR_CBPR_MASK;
357 vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
358 GICH_VMCR_EOI_MODE_MASK;
359 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
360 GICH_VMCR_ALIAS_BINPOINT_MASK;
361 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
362 GICH_VMCR_BINPOINT_MASK;
363 vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
364 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
365
366 cpu_if->vgic_vmcr = vmcr;
367 }
368
vgic_v2_get_vmcr(struct kvm_vcpu * vcpu,struct vgic_vmcr * vmcrp)369 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
370 {
371 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
372 u32 vmcr;
373
374 vmcr = cpu_if->vgic_vmcr;
375
376 vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
377 GICH_VMCR_ENABLE_GRP0_SHIFT;
378 vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
379 GICH_VMCR_ENABLE_GRP1_SHIFT;
380 vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
381 GICH_VMCR_ACK_CTL_SHIFT;
382 vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
383 GICH_VMCR_FIQ_EN_SHIFT;
384 vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
385 GICH_VMCR_CBPR_SHIFT;
386 vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
387 GICH_VMCR_EOI_MODE_SHIFT;
388
389 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
390 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
391 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
392 GICH_VMCR_BINPOINT_SHIFT;
393 vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
394 GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
395 }
396
vgic_v2_reset(struct kvm_vcpu * vcpu)397 void vgic_v2_reset(struct kvm_vcpu *vcpu)
398 {
399 /*
400 * By forcing VMCR to zero, the GIC will restore the binary
401 * points to their reset values. Anything else resets to zero
402 * anyway.
403 */
404 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
405 }
406
407 /* check for overlapping regions and for regions crossing the end of memory */
vgic_v2_check_base(gpa_t dist_base,gpa_t cpu_base)408 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
409 {
410 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
411 return false;
412 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
413 return false;
414
415 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
416 return true;
417 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
418 return true;
419
420 return false;
421 }
422
vgic_v2_map_resources(struct kvm * kvm)423 int vgic_v2_map_resources(struct kvm *kvm)
424 {
425 struct vgic_dist *dist = &kvm->arch.vgic;
426 unsigned int len;
427 int ret = 0;
428
429 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
430 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
431 kvm_debug("Need to set vgic cpu and dist addresses first\n");
432 return -ENXIO;
433 }
434
435 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
436 kvm_debug("VGIC CPU and dist frames overlap\n");
437 return -EINVAL;
438 }
439
440 /*
441 * Initialize the vgic if this hasn't already been done on demand by
442 * accessing the vgic state from userspace.
443 */
444 ret = vgic_init(kvm);
445 if (ret) {
446 kvm_err("Unable to initialize VGIC dynamic data structures\n");
447 return ret;
448 }
449
450 len = vgic_v2_init_cpuif_iodev(&dist->cpuif_iodev);
451 dist->cpuif_iodev.base_addr = dist->vgic_cpu_base;
452 dist->cpuif_iodev.iodev_type = IODEV_CPUIF;
453 dist->cpuif_iodev.redist_vcpu = NULL;
454
455 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist->vgic_cpu_base,
456 len, &dist->cpuif_iodev.dev);
457 if (ret)
458 return ret;
459
460 if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
461 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
462 kvm_vgic_global_state.vcpu_base,
463 KVM_VGIC_V2_CPU_SIZE - SZ_4K, true);
464 if (ret) {
465 kvm_err("Unable to remap VGIC CPU to VCPU\n");
466 return ret;
467 }
468 }
469
470 return 0;
471 }
472
473 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
474
475 /**
476 * vgic_v2_probe - probe for a VGICv2 compatible interrupt controller
477 * @info: pointer to the GIC description
478 *
479 * Returns 0 if the VGICv2 has been probed successfully, returns an error code
480 * otherwise
481 */
vgic_v2_probe(const struct gic_kvm_info * info)482 int vgic_v2_probe(const struct gic_kvm_info *info)
483 {
484 int ret;
485 u32 vtr;
486
487 if (is_protected_kvm_enabled()) {
488 kvm_err("GICv2 not supported in protected mode\n");
489 return -ENXIO;
490 }
491
492 if (!info->vctrl.start) {
493 kvm_err("GICH not present in the firmware table\n");
494 return -ENXIO;
495 }
496
497 if (!PAGE_ALIGNED(info->vcpu.start) ||
498 !PAGE_ALIGNED(resource_size(&info->vcpu))) {
499 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
500
501 ret = create_hyp_io_mappings(info->vcpu.start,
502 resource_size(&info->vcpu),
503 &kvm_vgic_global_state.vcpu_base_va,
504 &kvm_vgic_global_state.vcpu_hyp_va);
505 if (ret) {
506 kvm_err("Cannot map GICV into hyp\n");
507 goto out;
508 }
509
510 static_branch_enable(&vgic_v2_cpuif_trap);
511 }
512
513 ret = create_hyp_io_mappings(info->vctrl.start,
514 resource_size(&info->vctrl),
515 &kvm_vgic_global_state.vctrl_base,
516 &kvm_vgic_global_state.vctrl_hyp);
517 if (ret) {
518 kvm_err("Cannot map VCTRL into hyp\n");
519 goto out;
520 }
521
522 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
523 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
524
525 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
526 if (ret) {
527 kvm_err("Cannot register GICv2 KVM device\n");
528 goto out;
529 }
530
531 kvm_vgic_global_state.can_emulate_gicv2 = true;
532 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
533 kvm_vgic_global_state.gicc_base = info->gicc_base;
534 kvm_vgic_global_state.type = VGIC_V2;
535 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
536
537 kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
538
539 return 0;
540 out:
541 if (kvm_vgic_global_state.vctrl_base)
542 iounmap(kvm_vgic_global_state.vctrl_base);
543 if (kvm_vgic_global_state.vcpu_base_va)
544 iounmap(kvm_vgic_global_state.vcpu_base_va);
545
546 return ret;
547 }
548
save_lrs(struct kvm_vcpu * vcpu,void __iomem * base)549 static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
550 {
551 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
552 u64 used_lrs = cpu_if->used_lrs;
553 u64 elrsr;
554 int i;
555
556 elrsr = readl_relaxed(base + GICH_ELRSR0);
557 if (unlikely(used_lrs > 32))
558 elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;
559
560 for (i = 0; i < used_lrs; i++) {
561 if (elrsr & (1UL << i))
562 cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
563 else
564 cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
565
566 writel_relaxed(0, base + GICH_LR0 + (i * 4));
567 }
568 }
569
vgic_v2_save_state(struct kvm_vcpu * vcpu)570 void vgic_v2_save_state(struct kvm_vcpu *vcpu)
571 {
572 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
573 void __iomem *base = kvm_vgic_global_state.vctrl_base;
574 u64 used_lrs = vcpu->arch.vgic_cpu.vgic_v2.used_lrs;
575
576 if (!base)
577 return;
578
579 cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
580
581 if (used_lrs)
582 save_lrs(vcpu, base);
583
584 if (cpu_if->vgic_hcr & GICH_HCR_LRENPIE) {
585 u32 val = readl_relaxed(base + GICH_HCR);
586
587 cpu_if->vgic_hcr &= ~GICH_HCR_EOICOUNT;
588 cpu_if->vgic_hcr |= val & GICH_HCR_EOICOUNT;
589 }
590
591 writel_relaxed(0, base + GICH_HCR);
592 }
593
vgic_v2_restore_state(struct kvm_vcpu * vcpu)594 void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
595 {
596 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
597 void __iomem *base = kvm_vgic_global_state.vctrl_base;
598 u64 used_lrs = cpu_if->used_lrs;
599 int i;
600
601 if (!base)
602 return;
603
604 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
605
606 for (i = 0; i < used_lrs; i++)
607 writel_relaxed(cpu_if->vgic_lr[i], base + GICH_LR0 + (i * 4));
608 }
609
vgic_v2_load(struct kvm_vcpu * vcpu)610 void vgic_v2_load(struct kvm_vcpu *vcpu)
611 {
612 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
613
614 writel_relaxed(cpu_if->vgic_vmcr,
615 kvm_vgic_global_state.vctrl_base + GICH_VMCR);
616 writel_relaxed(cpu_if->vgic_apr,
617 kvm_vgic_global_state.vctrl_base + GICH_APR);
618 }
619
vgic_v2_put(struct kvm_vcpu * vcpu)620 void vgic_v2_put(struct kvm_vcpu *vcpu)
621 {
622 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
623
624 cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
625 }
626